1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include <hal_tx.h> 44 #include <hal_reo.h> 45 #include "wlan_cfg.h" 46 #include "hal_rx.h" 47 #include <hal_api.h> 48 #include <hal_api_mon.h> 49 #include "hal_rx.h" 50 51 #define MAX_BW 7 52 #define MAX_RETRIES 4 53 #define MAX_RECEPTION_TYPES 4 54 55 #ifndef REMOVE_PKT_LOG 56 #include <pktlog.h> 57 #endif 58 59 #define REPT_MU_MIMO 1 60 #define REPT_MU_OFDMA_MIMO 3 61 #define DP_VO_TID 6 62 63 #define DP_MAX_INTERRUPT_CONTEXTS 8 64 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 65 #define DSCP_TID_MAP_MAX (64) 66 #define DP_IP_DSCP_SHIFT 2 67 #define DP_IP_DSCP_MASK 0x3f 68 #define DP_FC0_SUBTYPE_QOS 0x80 69 #define DP_QOS_TID 0x0f 70 #define DP_IPV6_PRIORITY_SHIFT 20 71 #define MAX_MON_LINK_DESC_BANKS 2 72 #define DP_VDEV_ALL 0xff 73 74 #if defined(CONFIG_MCL) 75 #define MAX_PDEV_CNT 1 76 #else 77 #define MAX_PDEV_CNT 3 78 #endif 79 80 #define MAX_LINK_DESC_BANKS 8 81 #define MAX_TXDESC_POOLS 4 82 #define MAX_RXDESC_POOLS 4 83 #define MAX_REO_DEST_RINGS 4 84 #define MAX_TCL_DATA_RINGS 4 85 #define MAX_IDLE_SCATTER_BUFS 16 86 #define DP_MAX_IRQ_PER_CONTEXT 12 87 #define DP_MAX_INTERRUPT_CONTEXTS 8 88 #define DEFAULT_HW_PEER_ID 0xffff 89 90 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 91 92 #define DP_MAX_INTERRUPT_CONTEXTS 8 93 94 #ifndef REMOVE_PKT_LOG 95 enum rx_pktlog_mode { 96 DP_RX_PKTLOG_DISABLED = 0, 97 DP_RX_PKTLOG_FULL, 98 DP_RX_PKTLOG_LITE, 99 }; 100 #endif 101 102 struct dp_soc_cmn; 103 struct dp_pdev; 104 struct dp_vdev; 105 struct dp_tx_desc_s; 106 struct dp_soc; 107 union dp_rx_desc_list_elem_t; 108 109 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 110 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 111 112 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 113 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 114 115 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 116 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 117 118 #define DP_MUTEX_TYPE qdf_spinlock_t 119 120 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 121 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 122 123 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 124 ((_a)[0] == 0x33 && \ 125 (_a)[1] == 0x33) 126 127 #define DP_FRAME_IS_BROADCAST(_a) \ 128 ((_a)[0] == 0xff && \ 129 (_a)[1] == 0xff && \ 130 (_a)[2] == 0xff && \ 131 (_a)[3] == 0xff && \ 132 (_a)[4] == 0xff && \ 133 (_a)[5] == 0xff) 134 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 135 (_llc)->llc_ssap == 0xaa && \ 136 (_llc)->llc_un.type_snap.control == 0x3) 137 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 138 #define DP_FRAME_FC0_TYPE_MASK 0x0c 139 #define DP_FRAME_FC0_TYPE_DATA 0x08 140 #define DP_FRAME_IS_DATA(_frame) \ 141 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 142 143 /** 144 * macros to convert hw mac id to sw mac id: 145 * mac ids used by hardware start from a value of 1 while 146 * those in host software start from a value of 0. Use the 147 * macros below to convert between mac ids used by software and 148 * hardware 149 */ 150 #define DP_SW2HW_MACID(id) ((id) + 1) 151 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 152 #define DP_MAC_ADDR_LEN 6 153 154 /** 155 * enum dp_intr_mode 156 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 157 * @DP_INTR_MSI: MSI interrupts, for MCL 158 * @DP_INTR_POLL: Polling 159 */ 160 enum dp_intr_mode { 161 DP_INTR_LEGACY = 0, 162 DP_INTR_MSI, 163 DP_INTR_POLL, 164 }; 165 166 /** 167 * enum dp_tx_frm_type 168 * @dp_tx_frm_std: Regular frame, no added header fragments 169 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 170 * @dp_tx_frm_sg: SG segment 171 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 172 * @dp_tx_frm_me: Multicast to Unicast Converted frame 173 * @dp_tx_frm_raw: Raw Frame 174 */ 175 enum dp_tx_frm_type { 176 dp_tx_frm_std = 0, 177 dp_tx_frm_tso, 178 dp_tx_frm_sg, 179 dp_tx_frm_audio, 180 dp_tx_frm_me, 181 dp_tx_frm_raw, 182 }; 183 184 /** 185 * enum dp_ast_type 186 * @dp_ast_type_wds: WDS peer AST type 187 * @dp_ast_type_static: static ast entry type 188 * @dp_ast_type_mec: Multicast echo ast entry type 189 */ 190 enum dp_ast_type { 191 dp_ast_type_wds = 0, 192 dp_ast_type_static, 193 dp_ast_type_mec, 194 }; 195 196 /** 197 * enum dp_nss_cfg 198 * @dp_nss_cfg_default: No radios are offloaded 199 * @dp_nss_cfg_first_radio: First radio offloaded 200 * @dp_nss_cfg_second_radio: Second radio offloaded 201 * @dp_nss_cfg_dbdc: Dual radios offloaded 202 */ 203 enum dp_nss_cfg { 204 dp_nss_cfg_default, 205 dp_nss_cfg_first_radio, 206 dp_nss_cfg_second_radio, 207 dp_nss_cfg_dbdc, 208 }; 209 210 /** 211 * struct rx_desc_pool 212 * @pool_size: number of RX descriptor in the pool 213 * @array: pointer to array of RX descriptor 214 * @freelist: pointer to free RX descriptor link list 215 * @lock: Protection for the RX descriptor pool 216 * @owner: owner for nbuf 217 */ 218 struct rx_desc_pool { 219 uint32_t pool_size; 220 union dp_rx_desc_list_elem_t *array; 221 union dp_rx_desc_list_elem_t *freelist; 222 qdf_spinlock_t lock; 223 uint8_t owner; 224 }; 225 226 /** 227 * struct dp_tx_ext_desc_elem_s 228 * @next: next extension descriptor pointer 229 * @vaddr: hlos virtual address pointer 230 * @paddr: physical address pointer for descriptor 231 */ 232 struct dp_tx_ext_desc_elem_s { 233 struct dp_tx_ext_desc_elem_s *next; 234 void *vaddr; 235 qdf_dma_addr_t paddr; 236 }; 237 238 /** 239 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 240 * @elem_count: Number of descriptors in the pool 241 * @elem_size: Size of each descriptor 242 * @num_free: Number of free descriptors 243 * @msdu_ext_desc: MSDU extension descriptor 244 * @desc_pages: multiple page allocation information for actual descriptors 245 * @link_elem_size: size of the link descriptor in cacheable memory used for 246 * chaining the extension descriptors 247 * @desc_link_pages: multiple page allocation information for link descriptors 248 */ 249 struct dp_tx_ext_desc_pool_s { 250 uint16_t elem_count; 251 int elem_size; 252 uint16_t num_free; 253 struct qdf_mem_multi_page_t desc_pages; 254 int link_elem_size; 255 struct qdf_mem_multi_page_t desc_link_pages; 256 struct dp_tx_ext_desc_elem_s *freelist; 257 qdf_spinlock_t lock; 258 qdf_dma_mem_context(memctx); 259 }; 260 261 /** 262 * struct dp_tx_desc_s - Tx Descriptor 263 * @next: Next in the chain of descriptors in freelist or in the completion list 264 * @nbuf: Buffer Address 265 * @msdu_ext_desc: MSDU extension descriptor 266 * @id: Descriptor ID 267 * @vdev: vdev over which the packet was transmitted 268 * @pdev: Handle to pdev 269 * @pool_id: Pool ID - used when releasing the descriptor 270 * @flags: Flags to track the state of descriptor and special frame handling 271 * @comp: Pool ID - used when releasing the descriptor 272 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 273 * This is maintained in descriptor to allow more efficient 274 * processing in completion event processing code. 275 * This field is filled in with the htt_pkt_type enum. 276 * @frm_type: Frame Type - ToDo check if this is redundant 277 * @pkt_offset: Offset from which the actual packet data starts 278 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 279 * Tx completion of ME packet 280 * @pool: handle to flow_pool this descriptor belongs to. 281 */ 282 struct dp_tx_desc_s { 283 struct dp_tx_desc_s *next; 284 qdf_nbuf_t nbuf; 285 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 286 uint32_t id; 287 struct dp_vdev *vdev; 288 struct dp_pdev *pdev; 289 uint8_t pool_id; 290 uint16_t flags; 291 struct hal_tx_desc_comp_s comp; 292 uint16_t tx_encap_type; 293 uint8_t frm_type; 294 uint8_t pkt_offset; 295 void *me_buffer; 296 void *tso_desc; 297 void *tso_num_desc; 298 }; 299 300 /** 301 * enum flow_pool_status - flow pool status 302 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 303 * and network queues are unpaused 304 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 305 * and network queues are paused 306 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 307 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 308 */ 309 enum flow_pool_status { 310 FLOW_POOL_ACTIVE_UNPAUSED = 0, 311 FLOW_POOL_ACTIVE_PAUSED = 1, 312 FLOW_POOL_INVALID = 2, 313 FLOW_POOL_INACTIVE = 3, 314 }; 315 316 /** 317 * struct dp_tx_tso_seg_pool_s 318 * @pool_size: total number of pool elements 319 * @num_free: free element count 320 * @freelist: first free element pointer 321 * @lock: lock for accessing the pool 322 */ 323 struct dp_tx_tso_seg_pool_s { 324 uint16_t pool_size; 325 uint16_t num_free; 326 struct qdf_tso_seg_elem_t *freelist; 327 qdf_spinlock_t lock; 328 }; 329 330 /** 331 * struct dp_tx_tso_num_seg_pool_s { 332 * @num_seg_pool_size: total number of pool elements 333 * @num_free: free element count 334 * @freelist: first free element pointer 335 * @lock: lock for accessing the pool 336 */ 337 338 struct dp_tx_tso_num_seg_pool_s { 339 uint16_t num_seg_pool_size; 340 uint16_t num_free; 341 struct qdf_tso_num_seg_elem_t *freelist; 342 /*tso mutex */ 343 qdf_spinlock_t lock; 344 }; 345 346 /** 347 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 348 * @elem_size: Size of each descriptor in the pool 349 * @pool_size: Total number of descriptors in the pool 350 * @num_free: Number of free descriptors 351 * @num_allocated: Number of used descriptors 352 * @freelist: Chain of free descriptors 353 * @desc_pages: multiple page allocation information for actual descriptors 354 * @num_invalid_bin: Deleted pool with pending Tx completions. 355 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 356 * @flow_pool_array: List of allocated flow pools 357 * @lock- Lock for descriptor allocation/free from/to the pool 358 */ 359 struct dp_tx_desc_pool_s { 360 uint16_t elem_size; 361 uint32_t num_allocated; 362 struct dp_tx_desc_s *freelist; 363 struct qdf_mem_multi_page_t desc_pages; 364 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 365 uint16_t pool_size; 366 uint8_t flow_pool_id; 367 uint8_t num_invalid_bin; 368 uint16_t avail_desc; 369 enum flow_pool_status status; 370 enum htt_flow_type flow_type; 371 uint16_t stop_th; 372 uint16_t start_th; 373 uint16_t pkt_drop_no_desc; 374 qdf_spinlock_t flow_pool_lock; 375 void *pool_owner_ctx; 376 #else 377 uint16_t elem_count; 378 uint32_t num_free; 379 qdf_spinlock_t lock; 380 #endif 381 }; 382 383 /** 384 * struct dp_txrx_pool_stats - flow pool related statistics 385 * @pool_map_count: flow pool map received 386 * @pool_unmap_count: flow pool unmap received 387 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 388 */ 389 struct dp_txrx_pool_stats { 390 uint16_t pool_map_count; 391 uint16_t pool_unmap_count; 392 uint16_t pkt_drop_no_pool; 393 }; 394 395 struct dp_srng { 396 void *hal_srng; 397 void *base_vaddr_unaligned; 398 qdf_dma_addr_t base_paddr_unaligned; 399 uint32_t alloc_size; 400 int irq; 401 uint32_t num_entries; 402 }; 403 404 struct dp_rx_reorder_array_elem { 405 qdf_nbuf_t head; 406 qdf_nbuf_t tail; 407 }; 408 409 #define DP_RX_BA_INACTIVE 0 410 #define DP_RX_BA_ACTIVE 1 411 struct dp_reo_cmd_info { 412 uint16_t cmd; 413 enum hal_reo_cmd_type cmd_type; 414 void *data; 415 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 416 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 417 }; 418 419 /* Rx TID */ 420 struct dp_rx_tid { 421 /* TID */ 422 int tid; 423 424 /* Num of addba requests */ 425 uint32_t num_of_addba_req; 426 427 /* Num of addba responses */ 428 uint32_t num_of_addba_resp; 429 430 /* Num of delba requests */ 431 uint32_t num_of_delba_req; 432 433 /* pn size */ 434 uint8_t pn_size; 435 /* REO TID queue descriptors */ 436 void *hw_qdesc_vaddr_unaligned; 437 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 438 qdf_dma_addr_t hw_qdesc_paddr; 439 uint32_t hw_qdesc_alloc_size; 440 441 /* RX ADDBA session state */ 442 int ba_status; 443 444 /* RX BA window size */ 445 uint16_t ba_win_size; 446 447 /* TODO: Check the following while adding defragmentation support */ 448 struct dp_rx_reorder_array_elem *array; 449 /* base - single rx reorder element used for non-aggr cases */ 450 struct dp_rx_reorder_array_elem base; 451 452 /* only used for defrag right now */ 453 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 454 455 /* Store dst desc for reinjection */ 456 void *dst_ring_desc; 457 struct dp_rx_desc *head_frag_desc; 458 459 /* Sequence and fragments that are being processed currently */ 460 uint32_t curr_seq_num; 461 uint32_t curr_frag_num; 462 463 uint32_t defrag_timeout_ms; 464 uint16_t dialogtoken; 465 uint16_t statuscode; 466 /* user defined ADDBA response status code */ 467 uint16_t userstatuscode; 468 }; 469 470 /* per interrupt context */ 471 struct dp_intr { 472 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 473 associated with this napi context */ 474 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 475 with this interrupt context */ 476 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 477 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 478 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 479 uint8_t reo_status_ring_mask; /* REO command response ring */ 480 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 481 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 482 struct dp_soc *soc; /* Reference to SoC structure , 483 to get DMA ring handles */ 484 qdf_lro_ctx_t lro_ctx; 485 uint8_t dp_intr_id; 486 }; 487 488 #define REO_DESC_FREELIST_SIZE 64 489 #define REO_DESC_FREE_DEFER_MS 1000 490 struct reo_desc_list_node { 491 qdf_list_node_t node; 492 unsigned long free_ts; 493 struct dp_rx_tid rx_tid; 494 }; 495 496 /* SoC level data path statistics */ 497 struct dp_soc_stats { 498 struct { 499 uint32_t added; 500 uint32_t deleted; 501 uint32_t aged_out; 502 } ast; 503 504 /* SOC level TX stats */ 505 struct { 506 /* packets dropped on tx because of no peer */ 507 struct cdp_pkt_info tx_invalid_peer; 508 /* descriptors in each tcl ring */ 509 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 510 /* Descriptors in use at soc */ 511 uint32_t desc_in_use; 512 /* tqm_release_reason == FW removed */ 513 uint32_t dropped_fw_removed; 514 515 } tx; 516 517 /* SOC level RX stats */ 518 struct { 519 /* Rx errors */ 520 /* Total Packets in Rx Error ring */ 521 uint32_t err_ring_pkts; 522 /* No of Fragments */ 523 uint32_t rx_frags; 524 struct { 525 /* Invalid RBM error count */ 526 uint32_t invalid_rbm; 527 /* Invalid VDEV Error count */ 528 uint32_t invalid_vdev; 529 /* Invalid PDEV error count */ 530 uint32_t invalid_pdev; 531 /* Invalid PEER Error count */ 532 struct cdp_pkt_info rx_invalid_peer; 533 /* HAL ring access Fail error count */ 534 uint32_t hal_ring_access_fail; 535 /* RX DMA error count */ 536 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 537 /* REO Error count */ 538 uint32_t reo_error[HAL_REO_ERR_MAX]; 539 /* HAL REO ERR Count */ 540 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 541 } err; 542 543 /* packet count per core - per ring */ 544 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 545 } rx; 546 }; 547 548 #define DP_MAC_ADDR_LEN 6 549 union dp_align_mac_addr { 550 uint8_t raw[DP_MAC_ADDR_LEN]; 551 struct { 552 uint16_t bytes_ab; 553 uint16_t bytes_cd; 554 uint16_t bytes_ef; 555 } align2; 556 struct { 557 uint32_t bytes_abcd; 558 uint16_t bytes_ef; 559 } align4; 560 struct { 561 uint16_t bytes_ab; 562 uint32_t bytes_cdef; 563 } align4_2; 564 }; 565 566 /* 567 * dp_ast_entry 568 * 569 * @ast_idx: Hardware AST Index 570 * @mac_addr: MAC Address for this AST entry 571 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 572 * associated peer with this MAC address) 573 * @next_hop: Set to 1 if this is for a WDS node 574 * @is_active: flag to indicate active data traffic on this node 575 * (used for aging out/expiry) 576 * @ase_list_elem: node in peer AST list 577 * @is_bss: flag to indicate if entry corresponds to bss peer 578 * @pdev_id: pdev ID 579 * @vdev_id: vdev ID 580 * @type: flag to indicate type of the entry(static/WDS/MEC) 581 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 582 */ 583 struct dp_ast_entry { 584 uint16_t ast_idx; 585 /* MAC address */ 586 union dp_align_mac_addr mac_addr; 587 struct dp_peer *peer; 588 bool next_hop; 589 bool is_active; 590 bool is_bss; 591 uint8_t pdev_id; 592 uint8_t vdev_id; 593 enum cdp_txrx_ast_entry_type type; 594 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 595 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 596 }; 597 598 /* SOC level htt stats */ 599 struct htt_t2h_stats { 600 /* lock to protect htt_stats_msg update */ 601 qdf_spinlock_t lock; 602 603 /* work queue to process htt stats */ 604 qdf_work_t work; 605 606 /* T2H Ext stats message queue */ 607 qdf_nbuf_queue_t msg; 608 609 /* number of completed stats in htt_stats_msg */ 610 uint32_t num_stats; 611 }; 612 613 /* SOC level structure for data path */ 614 struct dp_soc { 615 /* Common base structure - Should be the first member */ 616 struct cdp_soc_t cdp_soc; 617 618 /* SoC Obj */ 619 void *ctrl_psoc; 620 621 /* OS device abstraction */ 622 qdf_device_t osdev; 623 624 /* WLAN config context */ 625 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 626 627 /* HTT handle for host-fw interaction */ 628 void *htt_handle; 629 630 /* Commint init done */ 631 qdf_atomic_t cmn_init_done; 632 633 /* Opaque hif handle */ 634 struct hif_opaque_softc *hif_handle; 635 636 /* PDEVs on this SOC */ 637 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 638 639 /* Number of PDEVs */ 640 uint8_t pdev_count; 641 642 /*cce disable*/ 643 bool cce_disable; 644 645 /* Link descriptor memory banks */ 646 struct { 647 void *base_vaddr_unaligned; 648 void *base_vaddr; 649 qdf_dma_addr_t base_paddr_unaligned; 650 qdf_dma_addr_t base_paddr; 651 uint32_t size; 652 } link_desc_banks[MAX_LINK_DESC_BANKS]; 653 654 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 655 struct dp_srng wbm_idle_link_ring; 656 657 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 658 */ 659 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 660 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 661 uint32_t wbm_idle_scatter_buf_size; 662 663 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 664 qdf_spinlock_t flow_pool_array_lock; 665 tx_pause_callback pause_cb; 666 struct dp_txrx_pool_stats pool_stats; 667 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 668 /* Tx SW descriptor pool */ 669 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 670 671 /* Tx MSDU Extension descriptor pool */ 672 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 673 674 /* Tx TSO descriptor pool */ 675 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 676 677 /* Tx TSO Num of segments pool */ 678 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 679 680 /* Tx H/W queues lock */ 681 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 682 683 /* Rx SW descriptor pool for RXDMA buffer */ 684 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 685 686 /* Rx SW descriptor pool for RXDMA monitor buffer */ 687 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 688 689 /* Rx SW descriptor pool for RXDMA status buffer */ 690 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 691 692 /* HAL SOC handle */ 693 void *hal_soc; 694 695 /* DP Interrupts */ 696 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 697 698 /* REO destination rings */ 699 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 700 701 /* Number of REO destination rings */ 702 uint8_t num_reo_dest_rings; 703 704 /* REO exception ring - See if should combine this with reo_dest_ring */ 705 struct dp_srng reo_exception_ring; 706 707 /* REO reinjection ring */ 708 struct dp_srng reo_reinject_ring; 709 710 /* REO command ring */ 711 struct dp_srng reo_cmd_ring; 712 713 /* REO command status ring */ 714 struct dp_srng reo_status_ring; 715 716 /* WBM Rx release ring */ 717 struct dp_srng rx_rel_ring; 718 719 /* Number of TCL data rings */ 720 uint8_t num_tcl_data_rings; 721 722 /* TCL data ring */ 723 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 724 725 /* TCL command ring */ 726 struct dp_srng tcl_cmd_ring; 727 728 /* TCL command status ring */ 729 struct dp_srng tcl_status_ring; 730 731 /* WBM Tx completion rings */ 732 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 733 734 /* Common WBM link descriptor release ring (SW to WBM) */ 735 struct dp_srng wbm_desc_rel_ring; 736 737 /* Tx ring map for interrupt processing */ 738 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 739 740 /* Rx ring map for interrupt processing */ 741 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 742 743 /* peer ID to peer object map (array of pointers to peer objects) */ 744 struct dp_peer **peer_id_to_obj_map; 745 746 struct { 747 unsigned mask; 748 unsigned idx_bits; 749 TAILQ_HEAD(, dp_peer) * bins; 750 } peer_hash; 751 752 /* rx defrag state – TBD: do we need this per radio? */ 753 struct { 754 struct { 755 TAILQ_HEAD(, dp_rx_tid) waitlist; 756 uint32_t timeout_ms; 757 } defrag; 758 struct { 759 int defrag_timeout_check; 760 int dup_check; 761 } flags; 762 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 763 qdf_spinlock_t reo_cmd_lock; 764 } rx; 765 766 /* optional rx processing function */ 767 void (*rx_opt_proc)( 768 struct dp_vdev *vdev, 769 struct dp_peer *peer, 770 unsigned tid, 771 qdf_nbuf_t msdu_list); 772 773 /* pool addr for mcast enhance buff */ 774 struct { 775 int size; 776 uint32_t paddr; 777 uint32_t *vaddr; 778 struct dp_tx_me_buf_t *freelist; 779 int buf_in_use; 780 qdf_dma_mem_context(memctx); 781 } me_buf; 782 783 /** 784 * peer ref mutex: 785 * 1. Protect peer object lookups until the returned peer object's 786 * reference count is incremented. 787 * 2. Provide mutex when accessing peer object lookup structures. 788 */ 789 DP_MUTEX_TYPE peer_ref_mutex; 790 791 /* maximum value for peer_id */ 792 uint32_t max_peers; 793 794 /* SoC level data path statistics */ 795 struct dp_soc_stats stats; 796 797 /* Enable processing of Tx completion status words */ 798 bool process_tx_status; 799 bool process_rx_status; 800 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 801 struct { 802 unsigned mask; 803 unsigned idx_bits; 804 TAILQ_HEAD(, dp_ast_entry) * bins; 805 } ast_hash; 806 807 qdf_spinlock_t ast_lock; 808 qdf_timer_t wds_aging_timer; 809 810 /*interrupt timer*/ 811 qdf_timer_t mon_reap_timer; 812 uint8_t reap_timer_init; 813 qdf_timer_t int_timer; 814 uint8_t intr_mode; 815 816 qdf_list_t reo_desc_freelist; 817 qdf_spinlock_t reo_desc_freelist_lock; 818 819 #ifdef QCA_SUPPORT_SON 820 /* The timer to check station's inactivity status */ 821 os_timer_t pdev_bs_inact_timer; 822 /* The current inactivity count reload value 823 based on overload condition */ 824 u_int16_t pdev_bs_inact_reload; 825 826 /* The inactivity timer value when not overloaded */ 827 u_int16_t pdev_bs_inact_normal; 828 829 /* The inactivity timer value when overloaded */ 830 u_int16_t pdev_bs_inact_overload; 831 832 /* The inactivity timer check interval */ 833 u_int16_t pdev_bs_inact_interval; 834 /* Inactivity timer */ 835 #endif /* QCA_SUPPORT_SON */ 836 837 /* htt stats */ 838 struct htt_t2h_stats htt_stats; 839 840 void *external_txrx_handle; /* External data path handle */ 841 #ifdef IPA_OFFLOAD 842 /* IPA uC datapath offload Wlan Tx resources */ 843 struct { 844 /* Resource info to be passed to IPA */ 845 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 846 void *ipa_tcl_ring_base_vaddr; 847 uint32_t ipa_tcl_ring_size; 848 qdf_dma_addr_t ipa_tcl_hp_paddr; 849 uint32_t alloc_tx_buf_cnt; 850 851 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 852 void *ipa_wbm_ring_base_vaddr; 853 uint32_t ipa_wbm_ring_size; 854 qdf_dma_addr_t ipa_wbm_tp_paddr; 855 856 /* TX buffers populated into the WBM ring */ 857 void **tx_buf_pool_vaddr_unaligned; 858 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 859 } ipa_uc_tx_rsc; 860 861 /* IPA uC datapath offload Wlan Rx resources */ 862 struct { 863 /* Resource info to be passed to IPA */ 864 qdf_dma_addr_t ipa_reo_ring_base_paddr; 865 void *ipa_reo_ring_base_vaddr; 866 uint32_t ipa_reo_ring_size; 867 qdf_dma_addr_t ipa_reo_tp_paddr; 868 869 /* Resource info to be passed to firmware and IPA */ 870 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 871 void *ipa_rx_refill_buf_ring_base_vaddr; 872 uint32_t ipa_rx_refill_buf_ring_size; 873 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 874 } ipa_uc_rx_rsc; 875 #endif 876 }; 877 878 #ifdef IPA_OFFLOAD 879 /** 880 * dp_ipa_resources - Resources needed for IPA 881 */ 882 struct dp_ipa_resources { 883 qdf_dma_addr_t tx_ring_base_paddr; 884 uint32_t tx_ring_size; 885 uint32_t tx_num_alloc_buffer; 886 887 qdf_dma_addr_t tx_comp_ring_base_paddr; 888 uint32_t tx_comp_ring_size; 889 890 qdf_dma_addr_t rx_rdy_ring_base_paddr; 891 uint32_t rx_rdy_ring_size; 892 893 qdf_dma_addr_t rx_refill_ring_base_paddr; 894 uint32_t rx_refill_ring_size; 895 896 /* IPA UC doorbell registers paddr */ 897 qdf_dma_addr_t tx_comp_doorbell_paddr; 898 uint32_t *tx_comp_doorbell_vaddr; 899 qdf_dma_addr_t rx_ready_doorbell_paddr; 900 }; 901 #endif 902 903 #define MAX_RX_MAC_RINGS 2 904 /* Same as NAC_MAX_CLENT */ 905 #define DP_NAC_MAX_CLIENT 24 906 907 /* 908 * Macros to setup link descriptor cookies - for link descriptors, we just 909 * need first 3 bits to store bank ID. The remaining bytes will be used set a 910 * unique ID, which will be useful in debugging 911 */ 912 #define LINK_DESC_BANK_ID_MASK 0x7 913 #define LINK_DESC_ID_SHIFT 3 914 #define LINK_DESC_ID_START 0x8000 915 916 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 917 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 918 919 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 920 ((_cookie) & LINK_DESC_BANK_ID_MASK) 921 922 /* same as ieee80211_nac_param */ 923 enum dp_nac_param_cmd { 924 /* IEEE80211_NAC_PARAM_ADD */ 925 DP_NAC_PARAM_ADD = 1, 926 /* IEEE80211_NAC_PARAM_DEL */ 927 DP_NAC_PARAM_DEL, 928 /* IEEE80211_NAC_PARAM_LIST */ 929 DP_NAC_PARAM_LIST, 930 }; 931 932 /** 933 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 934 * @neighbour_peers_macaddr: neighbour peer's mac address 935 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 936 */ 937 struct dp_neighbour_peer { 938 /* MAC address of neighbour's peer */ 939 union dp_align_mac_addr neighbour_peers_macaddr; 940 /* node in the list of neighbour's peer */ 941 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 942 }; 943 944 /** 945 * struct ppdu_info - PPDU Status info descriptor 946 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 947 * @max_ppdu_id - wrap around for ppdu id 948 * @last_tlv_cnt - Keep track for missing ppdu tlvs 949 * @last_user - last ppdu processed for user 950 * @is_ampdu - set if Ampdu aggregate 951 * @nbuf - ppdu descriptor payload 952 * @ppdu_desc - ppdu descriptor 953 * @ppdu_info_list_elem - linked list of ppdu tlvs 954 */ 955 struct ppdu_info { 956 uint32_t ppdu_id; 957 uint32_t max_ppdu_id; 958 uint16_t tlv_bitmap; 959 uint16_t last_tlv_cnt; 960 uint16_t last_user:8, 961 is_ampdu:1; 962 qdf_nbuf_t nbuf; 963 struct cdp_tx_completion_ppdu *ppdu_desc; 964 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 965 }; 966 967 /* PDEV level structure for data path */ 968 struct dp_pdev { 969 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 970 void *osif_pdev; 971 972 /* PDEV Id */ 973 int pdev_id; 974 975 /* TXRX SOC handle */ 976 struct dp_soc *soc; 977 978 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 979 struct dp_srng rx_refill_buf_ring; 980 981 /* Second ring used to replenish rx buffers */ 982 struct dp_srng rx_refill_buf_ring2; 983 984 /* Empty ring used by firmware to post rx buffers to the MAC */ 985 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 986 987 /* wlan_cfg pdev ctxt*/ 988 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 989 990 /* RXDMA monitor buffer replenish ring */ 991 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 992 993 /* RXDMA monitor destination ring */ 994 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 995 996 /* RXDMA monitor status ring. TBD: Check format of this ring */ 997 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 998 999 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1000 1001 /* RXDMA error destination ring */ 1002 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1003 1004 /* Link descriptor memory banks */ 1005 struct { 1006 void *base_vaddr_unaligned; 1007 void *base_vaddr; 1008 qdf_dma_addr_t base_paddr_unaligned; 1009 qdf_dma_addr_t base_paddr; 1010 uint32_t size; 1011 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1012 1013 1014 /** 1015 * TODO: See if we need a ring map here for LMAC rings. 1016 * 1. Monitor rings are currently planning to be processed on receiving 1017 * PPDU end interrupts and hence wont need ring based interrupts. 1018 * 2. Rx buffer rings will be replenished during REO destination 1019 * processing and doesn't require regular interrupt handling - we will 1020 * only handle low water mark interrupts which is not expected 1021 * frequently 1022 */ 1023 1024 /* VDEV list */ 1025 TAILQ_HEAD(, dp_vdev) vdev_list; 1026 1027 /* vdev list lock */ 1028 qdf_spinlock_t vdev_list_lock; 1029 1030 /* Number of vdevs this device have */ 1031 uint16_t vdev_count; 1032 1033 /* PDEV transmit lock */ 1034 qdf_spinlock_t tx_lock; 1035 1036 #ifndef REMOVE_PKT_LOG 1037 bool pkt_log_init; 1038 /* Pktlog pdev */ 1039 struct pktlog_dev_t *pl_dev; 1040 #endif /* #ifndef REMOVE_PKT_LOG */ 1041 1042 /* Monitor mode interface and status storage */ 1043 struct dp_vdev *monitor_vdev; 1044 1045 /* monitor mode lock */ 1046 qdf_spinlock_t mon_lock; 1047 1048 /*tx_mutex for me*/ 1049 DP_MUTEX_TYPE tx_mutex; 1050 1051 /* Smart Mesh */ 1052 bool filter_neighbour_peers; 1053 /* smart mesh mutex */ 1054 qdf_spinlock_t neighbour_peer_mutex; 1055 /* Neighnour peer list */ 1056 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1057 /* msdu chain head & tail */ 1058 qdf_nbuf_t invalid_peer_head_msdu; 1059 qdf_nbuf_t invalid_peer_tail_msdu; 1060 1061 /* Band steering */ 1062 /* TBD */ 1063 1064 /* PDEV level data path statistics */ 1065 struct cdp_pdev_stats stats; 1066 1067 /* Global RX decap mode for the device */ 1068 enum htt_pkt_type rx_decap_mode; 1069 1070 /* Enhanced Stats is enabled */ 1071 bool enhanced_stats_en; 1072 1073 /* advance filter mode and type*/ 1074 uint8_t mon_filter_mode; 1075 uint16_t fp_mgmt_filter; 1076 uint16_t fp_ctrl_filter; 1077 uint16_t fp_data_filter; 1078 uint16_t mo_mgmt_filter; 1079 uint16_t mo_ctrl_filter; 1080 uint16_t mo_data_filter; 1081 1082 qdf_atomic_t num_tx_outstanding; 1083 1084 qdf_atomic_t num_tx_exception; 1085 1086 /* MCL specific local peer handle */ 1087 struct { 1088 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1089 uint8_t freelist; 1090 qdf_spinlock_t lock; 1091 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1092 } local_peer_ids; 1093 1094 /* dscp_tid_map_*/ 1095 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1096 1097 struct hal_rx_ppdu_info ppdu_info; 1098 1099 /* operating channel */ 1100 uint8_t operating_channel; 1101 1102 qdf_nbuf_queue_t rx_status_q; 1103 uint32_t mon_ppdu_status; 1104 struct cdp_mon_status rx_mon_recv_status; 1105 /* monitor mode status/destination ring PPDU and MPDU count */ 1106 struct cdp_pdev_mon_stats rx_mon_stats; 1107 1108 /* pool addr for mcast enhance buff */ 1109 struct { 1110 int size; 1111 uint32_t paddr; 1112 char *vaddr; 1113 struct dp_tx_me_buf_t *freelist; 1114 int buf_in_use; 1115 qdf_dma_mem_context(memctx); 1116 } me_buf; 1117 1118 /* Number of VAPs with mcast enhancement enabled */ 1119 qdf_atomic_t mc_num_vap_attached; 1120 1121 qdf_atomic_t stats_cmd_complete; 1122 1123 #ifdef IPA_OFFLOAD 1124 ipa_uc_op_cb_type ipa_uc_op_cb; 1125 void *usr_ctxt; 1126 struct dp_ipa_resources ipa_resource; 1127 #endif 1128 1129 /* TBD */ 1130 1131 /* map this pdev to a particular Reo Destination ring */ 1132 enum cdp_host_reo_dest_ring reo_dest; 1133 1134 #ifndef REMOVE_PKT_LOG 1135 /* Packet log mode */ 1136 uint8_t rx_pktlog_mode; 1137 #endif 1138 1139 /* WDI event handlers */ 1140 struct wdi_event_subscribe_t **wdi_event_list; 1141 1142 /* ppdu_id of last received HTT TX stats */ 1143 uint32_t last_ppdu_id; 1144 struct { 1145 uint8_t last_user; 1146 qdf_nbuf_t buf; 1147 } tx_ppdu_info; 1148 1149 bool tx_sniffer_enable; 1150 /* mirror copy mode */ 1151 bool mcopy_mode; 1152 1153 struct { 1154 uint16_t tx_ppdu_id; 1155 uint16_t tx_peer_id; 1156 uint16_t rx_ppdu_id; 1157 } m_copy_id; 1158 1159 /* To check if PPDU Tx stats are enabled for Pktlog */ 1160 bool pktlog_ppdu_stats; 1161 1162 void *dp_txrx_handle; /* Advanced data path handle */ 1163 1164 #ifdef ATH_SUPPORT_NAC_RSSI 1165 bool nac_rssi_filtering; 1166 #endif 1167 /* list of ppdu tlvs */ 1168 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1169 uint32_t tlv_count; 1170 uint32_t list_depth; 1171 uint32_t ppdu_id; 1172 bool first_nbuf; 1173 }; 1174 1175 struct dp_peer; 1176 1177 /* VDEV structure for data path state */ 1178 struct dp_vdev { 1179 /* OS device abstraction */ 1180 qdf_device_t osdev; 1181 /* physical device that is the parent of this virtual device */ 1182 struct dp_pdev *pdev; 1183 1184 /* Handle to the OS shim SW's virtual device */ 1185 ol_osif_vdev_handle osif_vdev; 1186 1187 /* vdev_id - ID used to specify a particular vdev to the target */ 1188 uint8_t vdev_id; 1189 1190 /* MAC address */ 1191 union dp_align_mac_addr mac_addr; 1192 1193 /* node in the pdev's list of vdevs */ 1194 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1195 1196 /* dp_peer list */ 1197 TAILQ_HEAD(, dp_peer) peer_list; 1198 1199 /* callback to hand rx frames to the OS shim */ 1200 ol_txrx_rx_fp osif_rx; 1201 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1202 ol_txrx_get_key_fp osif_get_key; 1203 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1204 1205 #ifdef notyet 1206 /* callback to check if the msdu is an WAI (WAPI) frame */ 1207 ol_rx_check_wai_fp osif_check_wai; 1208 #endif 1209 1210 /* proxy arp function */ 1211 ol_txrx_proxy_arp_fp osif_proxy_arp; 1212 1213 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1214 ol_txrx_rx_mon_fp osif_rx_mon; 1215 1216 ol_txrx_mcast_me_fp me_convert; 1217 /* deferred vdev deletion state */ 1218 struct { 1219 /* VDEV delete pending */ 1220 int pending; 1221 /* 1222 * callback and a context argument to provide a 1223 * notification for when the vdev is deleted. 1224 */ 1225 ol_txrx_vdev_delete_cb callback; 1226 void *context; 1227 } delete; 1228 1229 /* tx data delivery notification callback function */ 1230 struct { 1231 ol_txrx_data_tx_cb func; 1232 void *ctxt; 1233 } tx_non_std_data_callback; 1234 1235 1236 /* safe mode control to bypass the encrypt and decipher process*/ 1237 uint32_t safemode; 1238 1239 /* rx filter related */ 1240 uint32_t drop_unenc; 1241 #ifdef notyet 1242 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1243 uint32_t filters_num; 1244 #endif 1245 /* TDLS Link status */ 1246 bool tdls_link_connected; 1247 bool is_tdls_frame; 1248 1249 1250 /* VDEV operating mode */ 1251 enum wlan_op_mode opmode; 1252 1253 /* Tx encapsulation type for this VAP */ 1254 enum htt_cmn_pkt_type tx_encap_type; 1255 /* Rx Decapsulation type for this VAP */ 1256 enum htt_cmn_pkt_type rx_decap_type; 1257 1258 /* BSS peer */ 1259 struct dp_peer *vap_bss_peer; 1260 1261 /* WDS enabled */ 1262 bool wds_enabled; 1263 1264 /* WDS Aging timer period */ 1265 uint32_t wds_aging_timer_val; 1266 1267 /* NAWDS enabled */ 1268 bool nawds_enabled; 1269 1270 /* Default HTT meta data for this VDEV */ 1271 /* TBD: check alignment constraints */ 1272 uint16_t htt_tcl_metadata; 1273 1274 /* Mesh mode vdev */ 1275 uint32_t mesh_vdev; 1276 1277 /* Mesh mode rx filter setting */ 1278 uint32_t mesh_rx_filter; 1279 1280 /* DSCP-TID mapping table ID */ 1281 uint8_t dscp_tid_map_id; 1282 1283 /* Multicast enhancement enabled */ 1284 uint8_t mcast_enhancement_en; 1285 1286 /* per vdev rx nbuf queue */ 1287 qdf_nbuf_queue_t rxq; 1288 1289 uint8_t tx_ring_id; 1290 struct dp_tx_desc_pool_s *tx_desc; 1291 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1292 1293 /* VDEV Stats */ 1294 struct cdp_vdev_stats stats; 1295 bool lro_enable; 1296 1297 /* Is this a proxySTA VAP */ 1298 bool proxysta_vdev; 1299 /* Is isolation mode enabled */ 1300 bool isolation_vdev; 1301 1302 /* Address search flags to be configured in HAL descriptor */ 1303 uint8_t hal_desc_addr_search_flags; 1304 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1305 struct dp_tx_desc_pool_s *pool; 1306 #endif 1307 /* AP BRIDGE enabled */ 1308 uint32_t ap_bridge_enabled; 1309 1310 enum cdp_sec_type sec_type; 1311 1312 #ifdef ATH_SUPPORT_NAC_RSSI 1313 bool cdp_nac_rssi_enabled; 1314 struct { 1315 uint8_t bssid_mac[6]; 1316 uint8_t client_mac[6]; 1317 uint8_t chan_num; 1318 uint8_t client_rssi_valid; 1319 uint8_t client_rssi; 1320 uint8_t vdev_id; 1321 } cdp_nac_rssi; 1322 #endif 1323 }; 1324 1325 1326 enum { 1327 dp_sec_mcast = 0, 1328 dp_sec_ucast 1329 }; 1330 1331 #ifdef WDS_VENDOR_EXTENSION 1332 typedef struct { 1333 uint8_t wds_tx_mcast_4addr:1, 1334 wds_tx_ucast_4addr:1, 1335 wds_rx_filter:1, /* enforce rx filter */ 1336 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1337 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1338 1339 } dp_ecm_policy; 1340 #endif 1341 1342 /* Peer structure for data path state */ 1343 struct dp_peer { 1344 /* VDEV to which this peer is associated */ 1345 struct dp_vdev *vdev; 1346 1347 struct dp_ast_entry *self_ast_entry; 1348 1349 qdf_atomic_t ref_cnt; 1350 1351 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1352 /* peer ID(s) for this peer */ 1353 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1354 1355 union dp_align_mac_addr mac_addr; 1356 1357 /* node in the vdev's list of peers */ 1358 TAILQ_ENTRY(dp_peer) peer_list_elem; 1359 /* node in the hash table bin's list of peers */ 1360 TAILQ_ENTRY(dp_peer) hash_list_elem; 1361 1362 /* TID structures */ 1363 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1364 1365 /* TBD: No transmit TID state required? */ 1366 1367 struct { 1368 enum htt_sec_type sec_type; 1369 u_int32_t michael_key[2]; /* relevant for TKIP */ 1370 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1371 1372 /* 1373 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1374 * regular rx processing, or has been redirected to a /dev/null discard 1375 * function when peer deletion is in progress. 1376 */ 1377 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1378 unsigned tid, qdf_nbuf_t msdu_list); 1379 1380 /* set when node is authorized */ 1381 uint8_t authorize:1; 1382 1383 u_int8_t nac; 1384 1385 /* Band steering: Set when node is inactive */ 1386 uint8_t peer_bs_inact_flag:1; 1387 u_int16_t peer_bs_inact; /* inactivity mark count */ 1388 1389 /* NAWDS Flag and Bss Peer bit */ 1390 uint8_t nawds_enabled:1, 1391 bss_peer:1, 1392 wapi:1, 1393 wds_enabled:1; 1394 1395 /* MCL specific peer local id */ 1396 uint16_t local_id; 1397 enum ol_txrx_peer_state state; 1398 qdf_spinlock_t peer_info_lock; 1399 1400 qdf_time_t last_assoc_rcvd; 1401 qdf_time_t last_disassoc_rcvd; 1402 qdf_time_t last_deauth_rcvd; 1403 /* Peer Stats */ 1404 struct cdp_peer_stats stats; 1405 1406 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1407 /* TBD */ 1408 1409 #ifdef WDS_VENDOR_EXTENSION 1410 dp_ecm_policy wds_ecm; 1411 #endif 1412 bool delete_in_progress; 1413 }; 1414 1415 #ifdef CONFIG_WIN 1416 /* 1417 * dp_invalid_peer_msg 1418 * @nbuf: data buffer 1419 * @wh: 802.11 header 1420 * @vdev_id: id of vdev 1421 */ 1422 struct dp_invalid_peer_msg { 1423 qdf_nbuf_t nbuf; 1424 struct ieee80211_frame *wh; 1425 uint8_t vdev_id; 1426 }; 1427 #endif 1428 1429 /* 1430 * dp_tx_me_buf_t: ME buffer 1431 * next: pointer to next buffer 1432 * data: Destination Mac address 1433 */ 1434 struct dp_tx_me_buf_t { 1435 /* Note: ME buf pool initialization logic expects next pointer to 1436 * be the first element. Dont add anything before next */ 1437 struct dp_tx_me_buf_t *next; 1438 uint8_t data[DP_MAC_ADDR_LEN]; 1439 }; 1440 1441 #endif /* _DP_TYPES_H_ */ 1442