1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 //#include "hal_rx_flow.h" 49 50 #define MAX_BW 8 51 #define MAX_RETRIES 4 52 #define MAX_RECEPTION_TYPES 4 53 54 #define MINIDUMP_STR_SIZE 25 55 #ifndef REMOVE_PKT_LOG 56 #include <pktlog.h> 57 #endif 58 #include <dp_umac_reset.h> 59 60 //#include "dp_tx.h" 61 62 #define REPT_MU_MIMO 1 63 #define REPT_MU_OFDMA_MIMO 3 64 #define DP_VO_TID 6 65 /** MAX TID MAPS AVAILABLE PER PDEV */ 66 #define DP_MAX_TID_MAPS 16 67 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 68 #define DSCP_TID_MAP_MAX (64 + 6) 69 #define DP_IP_DSCP_SHIFT 2 70 #define DP_IP_DSCP_MASK 0x3f 71 #define DP_FC0_SUBTYPE_QOS 0x80 72 #define DP_QOS_TID 0x0f 73 #define DP_IPV6_PRIORITY_SHIFT 20 74 #define MAX_MON_LINK_DESC_BANKS 2 75 #define DP_VDEV_ALL 0xff 76 77 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 78 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 79 #define MAX_TXDESC_POOLS 6 80 #else 81 #define MAX_TXDESC_POOLS 4 82 #endif 83 84 #define MAX_RXDESC_POOLS 4 85 86 /* Max no. of VDEV per PSOC */ 87 #ifdef WLAN_PSOC_MAX_VDEVS 88 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 89 #else 90 #define MAX_VDEV_CNT 51 91 #endif 92 93 /* Max no. of VDEVs, a PDEV can support */ 94 #ifdef WLAN_PDEV_MAX_VDEVS 95 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 96 #else 97 #define DP_PDEV_MAX_VDEVS 17 98 #endif 99 100 #define EXCEPTION_DEST_RING_ID 0 101 #define MAX_IDLE_SCATTER_BUFS 16 102 #define DP_MAX_IRQ_PER_CONTEXT 12 103 #define DEFAULT_HW_PEER_ID 0xffff 104 105 #define MAX_AST_AGEOUT_COUNT 128 106 107 #ifdef TX_ADDR_INDEX_SEARCH 108 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 109 #else 110 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 111 #endif 112 113 #define WBM_INT_ERROR_ALL 0 114 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 115 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 116 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 117 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 118 #define MAX_WBM_INT_ERROR_REASONS 5 119 120 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 121 /* Maximum retries for Delba per tid per peer */ 122 #define DP_MAX_DELBA_RETRY 3 123 124 #ifdef AST_OFFLOAD_ENABLE 125 #define AST_OFFLOAD_ENABLE_STATUS 1 126 #else 127 #define AST_OFFLOAD_ENABLE_STATUS 0 128 #endif 129 130 #ifdef FEATURE_MEC_OFFLOAD 131 #define FW_MEC_FW_OFFLOAD_ENABLED 1 132 #else 133 #define FW_MEC_FW_OFFLOAD_ENABLED 0 134 #endif 135 136 #define PCP_TID_MAP_MAX 8 137 #define MAX_MU_USERS 37 138 139 #define REO_CMD_EVENT_HIST_MAX 64 140 141 #define DP_MAX_SRNGS 64 142 143 /* 2G PHYB */ 144 #define PHYB_2G_LMAC_ID 2 145 #define PHYB_2G_TARGET_PDEV_ID 2 146 147 /* Flags for skippig s/w tid classification */ 148 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 149 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 150 #define DP_TX_MESH_ENABLED 0x4 151 #define DP_TX_INVALID_QOS_TAG 0xf 152 153 #ifdef WLAN_SUPPORT_RX_FISA 154 #define FISA_FLOW_MAX_AGGR_COUNT 16 /* max flow aggregate count */ 155 #endif 156 157 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 158 #define DP_RX_REFILL_BUFF_POOL_SIZE 2048 159 #define DP_RX_REFILL_BUFF_POOL_BURST 64 160 #define DP_RX_REFILL_THRD_THRESHOLD 512 161 #endif 162 163 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 164 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 165 #endif 166 167 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 168 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 169 170 #ifdef IPA_OFFLOAD 171 #define DP_PEER_REO_STATS_TID_SHIFT 16 172 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 173 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 174 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 175 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 176 DP_PEER_REO_STATS_TID_SHIFT) 177 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 178 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 179 #endif 180 181 enum rx_pktlog_mode { 182 DP_RX_PKTLOG_DISABLED = 0, 183 DP_RX_PKTLOG_FULL, 184 DP_RX_PKTLOG_LITE, 185 }; 186 187 /* enum m_copy_mode - Available mcopy mode 188 * 189 */ 190 enum m_copy_mode { 191 M_COPY_DISABLED = 0, 192 M_COPY = 2, 193 M_COPY_EXTENDED = 4, 194 }; 195 196 struct msdu_list { 197 qdf_nbuf_t head; 198 qdf_nbuf_t tail; 199 uint32_t sum_len; 200 }; 201 202 struct dp_soc_cmn; 203 struct dp_pdev; 204 struct dp_vdev; 205 struct dp_tx_desc_s; 206 struct dp_soc; 207 union dp_rx_desc_list_elem_t; 208 struct cdp_peer_rate_stats_ctx; 209 struct cdp_soc_rate_stats_ctx; 210 struct dp_rx_fst; 211 struct dp_mon_filter; 212 struct dp_mon_mpdu; 213 #ifdef BE_PKTLOG_SUPPORT 214 struct dp_mon_filter_be; 215 #endif 216 struct dp_peer; 217 struct dp_txrx_peer; 218 219 /** 220 * enum for DP peer state 221 */ 222 enum dp_peer_state { 223 DP_PEER_STATE_NONE, 224 DP_PEER_STATE_INIT, 225 DP_PEER_STATE_ACTIVE, 226 DP_PEER_STATE_LOGICAL_DELETE, 227 DP_PEER_STATE_INACTIVE, 228 DP_PEER_STATE_FREED, 229 DP_PEER_STATE_INVALID, 230 }; 231 232 /** 233 * enum for modules ids of 234 */ 235 enum dp_mod_id { 236 DP_MOD_ID_TX_RX, 237 DP_MOD_ID_TX_COMP, 238 DP_MOD_ID_RX, 239 DP_MOD_ID_HTT_COMP, 240 DP_MOD_ID_RX_ERR, 241 DP_MOD_ID_TX_PPDU_STATS, 242 DP_MOD_ID_RX_PPDU_STATS, 243 DP_MOD_ID_CDP, 244 DP_MOD_ID_GENERIC_STATS, 245 DP_MOD_ID_TX_MULTIPASS, 246 DP_MOD_ID_TX_CAPTURE, 247 DP_MOD_ID_NSS_OFFLOAD, 248 DP_MOD_ID_CONFIG, 249 DP_MOD_ID_HTT, 250 DP_MOD_ID_IPA, 251 DP_MOD_ID_AST, 252 DP_MOD_ID_MCAST2UCAST, 253 DP_MOD_ID_CHILD, 254 DP_MOD_ID_MESH, 255 DP_MOD_ID_TX_EXCEPTION, 256 DP_MOD_ID_TDLS, 257 DP_MOD_ID_MISC, 258 DP_MOD_ID_MSCS, 259 DP_MOD_ID_TX, 260 DP_MOD_ID_SAWF, 261 DP_MOD_ID_REINJECT, 262 DP_MOD_ID_SCS, 263 DP_MOD_ID_UMAC_RESET, 264 DP_MOD_ID_MAX, 265 }; 266 267 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 268 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 269 270 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 271 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 272 273 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 274 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 275 276 #define DP_MUTEX_TYPE qdf_spinlock_t 277 278 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 279 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 280 281 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 282 ((_a)[0] == 0x33 && \ 283 (_a)[1] == 0x33) 284 285 #define DP_FRAME_IS_BROADCAST(_a) \ 286 ((_a)[0] == 0xff && \ 287 (_a)[1] == 0xff && \ 288 (_a)[2] == 0xff && \ 289 (_a)[3] == 0xff && \ 290 (_a)[4] == 0xff && \ 291 (_a)[5] == 0xff) 292 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 293 (_llc)->llc_ssap == 0xaa && \ 294 (_llc)->llc_un.type_snap.control == 0x3) 295 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 296 #define DP_FRAME_FC0_TYPE_MASK 0x0c 297 #define DP_FRAME_FC0_TYPE_DATA 0x08 298 #define DP_FRAME_IS_DATA(_frame) \ 299 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 300 301 /** 302 * macros to convert hw mac id to sw mac id: 303 * mac ids used by hardware start from a value of 1 while 304 * those in host software start from a value of 0. Use the 305 * macros below to convert between mac ids used by software and 306 * hardware 307 */ 308 #define DP_SW2HW_MACID(id) ((id) + 1) 309 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 310 311 /** 312 * Number of Tx Queues 313 * enum and macro to define how many threshold levels is used 314 * for the AC based flow control 315 */ 316 #ifdef QCA_AC_BASED_FLOW_CONTROL 317 enum dp_fl_ctrl_threshold { 318 DP_TH_BE_BK = 0, 319 DP_TH_VI, 320 DP_TH_VO, 321 DP_TH_HI, 322 }; 323 324 #define FL_TH_MAX (4) 325 #define FL_TH_VI_PERCENTAGE (80) 326 #define FL_TH_VO_PERCENTAGE (60) 327 #define FL_TH_HI_PERCENTAGE (40) 328 #endif 329 330 /** 331 * enum dp_intr_mode 332 * @DP_INTR_INTEGRATED: Line interrupts 333 * @DP_INTR_MSI: MSI interrupts 334 * @DP_INTR_POLL: Polling 335 */ 336 enum dp_intr_mode { 337 DP_INTR_INTEGRATED = 0, 338 DP_INTR_MSI, 339 DP_INTR_POLL, 340 DP_INTR_LEGACY_VIRTUAL_IRQ, 341 }; 342 343 /** 344 * enum dp_tx_frm_type 345 * @dp_tx_frm_std: Regular frame, no added header fragments 346 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 347 * @dp_tx_frm_sg: SG segment 348 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 349 * @dp_tx_frm_me: Multicast to Unicast Converted frame 350 * @dp_tx_frm_raw: Raw Frame 351 */ 352 enum dp_tx_frm_type { 353 dp_tx_frm_std = 0, 354 dp_tx_frm_tso, 355 dp_tx_frm_sg, 356 dp_tx_frm_audio, 357 dp_tx_frm_me, 358 dp_tx_frm_raw, 359 }; 360 361 /** 362 * enum dp_ast_type 363 * @dp_ast_type_wds: WDS peer AST type 364 * @dp_ast_type_static: static ast entry type 365 * @dp_ast_type_mec: Multicast echo ast entry type 366 */ 367 enum dp_ast_type { 368 dp_ast_type_wds = 0, 369 dp_ast_type_static, 370 dp_ast_type_mec, 371 }; 372 373 /** 374 * enum dp_nss_cfg 375 * @dp_nss_cfg_default: No radios are offloaded 376 * @dp_nss_cfg_first_radio: First radio offloaded 377 * @dp_nss_cfg_second_radio: Second radio offloaded 378 * @dp_nss_cfg_dbdc: Dual radios offloaded 379 * @dp_nss_cfg_dbtc: Three radios offloaded 380 */ 381 enum dp_nss_cfg { 382 dp_nss_cfg_default = 0x0, 383 dp_nss_cfg_first_radio = 0x1, 384 dp_nss_cfg_second_radio = 0x2, 385 dp_nss_cfg_dbdc = 0x3, 386 dp_nss_cfg_dbtc = 0x7, 387 dp_nss_cfg_max 388 }; 389 390 #ifdef WLAN_TX_PKT_CAPTURE_ENH 391 #define DP_CPU_RING_MAP_1 1 392 #endif 393 394 /** 395 * dp_cpu_ring_map_type - dp tx cpu ring map 396 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 397 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 398 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 399 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 400 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 401 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 402 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 403 */ 404 enum dp_cpu_ring_map_types { 405 DP_NSS_DEFAULT_MAP, 406 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 407 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 408 DP_NSS_DBDC_OFFLOADED_MAP, 409 DP_NSS_DBTC_OFFLOADED_MAP, 410 #ifdef WLAN_TX_PKT_CAPTURE_ENH 411 DP_SINGLE_TX_RING_MAP, 412 #endif 413 DP_NSS_CPU_RING_MAP_MAX 414 }; 415 416 /** 417 * dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 418 * 419 * paddr: Physical address of buffer allocated. 420 * nbuf: Allocated nbuf in case of nbuf approach. 421 * vaddr: Virtual address of frag allocated in case of frag approach. 422 */ 423 struct dp_rx_nbuf_frag_info { 424 qdf_dma_addr_t paddr; 425 union { 426 qdf_nbuf_t nbuf; 427 qdf_frag_t vaddr; 428 } virt_addr; 429 }; 430 431 /** 432 * enum dp_ctxt - context type 433 * @DP_PDEV_TYPE: PDEV context 434 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 435 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 436 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 437 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 438 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 439 * @DP_MON_SOC_TYPE: Datapath monitor soc context 440 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 441 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 442 */ 443 enum dp_ctxt_type { 444 DP_PDEV_TYPE, 445 DP_RX_RING_HIST_TYPE, 446 DP_RX_ERR_RING_HIST_TYPE, 447 DP_RX_REINJECT_RING_HIST_TYPE, 448 DP_TX_TCL_HIST_TYPE, 449 DP_TX_COMP_HIST_TYPE, 450 DP_FISA_RX_FT_TYPE, 451 DP_RX_REFILL_RING_HIST_TYPE, 452 DP_TX_HW_DESC_HIST_TYPE, 453 DP_MON_SOC_TYPE, 454 DP_MON_PDEV_TYPE, 455 DP_MON_STATUS_BUF_HIST_TYPE, 456 }; 457 458 /** 459 * enum dp_desc_type - source type for multiple pages allocation 460 * @DP_TX_DESC_TYPE: DP SW TX descriptor 461 * @DP_TX_EXT_DESC_TYPE: DP TX msdu extension descriptor 462 * @DP_TX_EXT_DESC_LINK_TYPE: DP link descriptor for msdu ext_desc 463 * @DP_TX_TSO_DESC_TYPE: DP TX TSO descriptor 464 * @DP_TX_TSO_NUM_SEG_TYPE: DP TX number of segments 465 * @DP_RX_DESC_BUF_TYPE: DP RX SW descriptor 466 * @DP_RX_DESC_STATUS_TYPE: DP RX SW descriptor for monitor status 467 * @DP_HW_LINK_DESC_TYPE: DP HW link descriptor 468 * @DP_HW_CC_SPT_PAGE_TYPE: DP pages for HW CC secondary page table 469 */ 470 enum dp_desc_type { 471 DP_TX_DESC_TYPE, 472 DP_TX_EXT_DESC_TYPE, 473 DP_TX_EXT_DESC_LINK_TYPE, 474 DP_TX_TSO_DESC_TYPE, 475 DP_TX_TSO_NUM_SEG_TYPE, 476 DP_RX_DESC_BUF_TYPE, 477 DP_RX_DESC_STATUS_TYPE, 478 DP_HW_LINK_DESC_TYPE, 479 DP_HW_CC_SPT_PAGE_TYPE, 480 }; 481 482 /** 483 * struct rx_desc_pool 484 * @pool_size: number of RX descriptor in the pool 485 * @elem_size: Element size 486 * @desc_pages: Multi page descriptors 487 * @array: pointer to array of RX descriptor 488 * @freelist: pointer to free RX descriptor link list 489 * @lock: Protection for the RX descriptor pool 490 * @owner: owner for nbuf 491 * @buf_size: Buffer size 492 * @buf_alignment: Buffer alignment 493 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 494 * @desc_type: type of desc this pool serves 495 */ 496 struct rx_desc_pool { 497 uint32_t pool_size; 498 #ifdef RX_DESC_MULTI_PAGE_ALLOC 499 uint16_t elem_size; 500 struct qdf_mem_multi_page_t desc_pages; 501 #else 502 union dp_rx_desc_list_elem_t *array; 503 #endif 504 union dp_rx_desc_list_elem_t *freelist; 505 qdf_spinlock_t lock; 506 uint8_t owner; 507 uint16_t buf_size; 508 uint8_t buf_alignment; 509 bool rx_mon_dest_frag_enable; 510 enum dp_desc_type desc_type; 511 }; 512 513 /** 514 * struct dp_tx_ext_desc_elem_s 515 * @next: next extension descriptor pointer 516 * @vaddr: hlos virtual address pointer 517 * @paddr: physical address pointer for descriptor 518 * @flags: mark features for extension descriptor 519 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 520 * Tx completion of ME packet 521 * @tso_desc: Pointer to Tso desc 522 * @tso_num_desc: Pointer to tso_num_desc 523 */ 524 struct dp_tx_ext_desc_elem_s { 525 struct dp_tx_ext_desc_elem_s *next; 526 void *vaddr; 527 qdf_dma_addr_t paddr; 528 uint16_t flags; 529 struct dp_tx_me_buf_t *me_buffer; 530 struct qdf_tso_seg_elem_t *tso_desc; 531 struct qdf_tso_num_seg_elem_t *tso_num_desc; 532 }; 533 534 /** 535 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 536 * @elem_count: Number of descriptors in the pool 537 * @elem_size: Size of each descriptor 538 * @num_free: Number of free descriptors 539 * @msdu_ext_desc: MSDU extension descriptor 540 * @desc_pages: multiple page allocation information for actual descriptors 541 * @link_elem_size: size of the link descriptor in cacheable memory used for 542 * chaining the extension descriptors 543 * @desc_link_pages: multiple page allocation information for link descriptors 544 */ 545 struct dp_tx_ext_desc_pool_s { 546 uint16_t elem_count; 547 int elem_size; 548 uint16_t num_free; 549 struct qdf_mem_multi_page_t desc_pages; 550 int link_elem_size; 551 struct qdf_mem_multi_page_t desc_link_pages; 552 struct dp_tx_ext_desc_elem_s *freelist; 553 qdf_spinlock_t lock; 554 qdf_dma_mem_context(memctx); 555 }; 556 557 /** 558 * struct dp_tx_desc_s - Tx Descriptor 559 * @next: Next in the chain of descriptors in freelist or in the completion list 560 * @nbuf: Buffer Address 561 * @msdu_ext_desc: MSDU extension descriptor 562 * @id: Descriptor ID 563 * @vdev_id: vdev_id of vdev over which the packet was transmitted 564 * @pdev: Handle to pdev 565 * @pool_id: Pool ID - used when releasing the descriptor 566 * @flags: Flags to track the state of descriptor and special frame handling 567 * @comp: Pool ID - used when releasing the descriptor 568 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 569 * This is maintained in descriptor to allow more efficient 570 * processing in completion event processing code. 571 * This field is filled in with the htt_pkt_type enum. 572 * @buffer_src: buffer source TQM, REO, FW etc. 573 * @frm_type: Frame Type - ToDo check if this is redundant 574 * @pkt_offset: Offset from which the actual packet data starts 575 * @pool: handle to flow_pool this descriptor belongs to. 576 */ 577 struct dp_tx_desc_s { 578 struct dp_tx_desc_s *next; 579 qdf_nbuf_t nbuf; 580 uint16_t length; 581 #ifdef DP_TX_TRACKING 582 uint32_t magic; 583 uint64_t timestamp_tick; 584 #endif 585 uint16_t flags; 586 uint32_t id; 587 qdf_dma_addr_t dma_addr; 588 uint8_t vdev_id; 589 uint8_t tx_status; 590 uint16_t peer_id; 591 struct dp_pdev *pdev; 592 uint8_t tx_encap_type:2, 593 buffer_src:3, 594 reserved:3; 595 uint8_t frm_type; 596 uint8_t pkt_offset; 597 uint8_t pool_id; 598 unsigned char *shinfo_addr; 599 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 600 qdf_ktime_t timestamp; 601 struct hal_tx_desc_comp_s comp; 602 }; 603 604 #ifdef QCA_AC_BASED_FLOW_CONTROL 605 /** 606 * enum flow_pool_status - flow pool status 607 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 608 * and network queues are unpaused 609 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 610 * and network queues are paused 611 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 612 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 613 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 614 * queues are not paused 615 */ 616 enum flow_pool_status { 617 FLOW_POOL_ACTIVE_UNPAUSED = 0, 618 FLOW_POOL_ACTIVE_PAUSED = 1, 619 FLOW_POOL_BE_BK_PAUSED = 2, 620 FLOW_POOL_VI_PAUSED = 3, 621 FLOW_POOL_VO_PAUSED = 4, 622 FLOW_POOL_INVALID = 5, 623 FLOW_POOL_INACTIVE = 6, 624 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 625 }; 626 627 #else 628 /** 629 * enum flow_pool_status - flow pool status 630 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 631 * and network queues are unpaused 632 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 633 * and network queues are paused 634 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 635 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 636 */ 637 enum flow_pool_status { 638 FLOW_POOL_ACTIVE_UNPAUSED = 0, 639 FLOW_POOL_ACTIVE_PAUSED = 1, 640 FLOW_POOL_BE_BK_PAUSED = 2, 641 FLOW_POOL_VI_PAUSED = 3, 642 FLOW_POOL_VO_PAUSED = 4, 643 FLOW_POOL_INVALID = 5, 644 FLOW_POOL_INACTIVE = 6, 645 }; 646 647 #endif 648 649 /** 650 * struct dp_tx_tso_seg_pool_s 651 * @pool_size: total number of pool elements 652 * @num_free: free element count 653 * @freelist: first free element pointer 654 * @desc_pages: multiple page allocation information for actual descriptors 655 * @lock: lock for accessing the pool 656 */ 657 struct dp_tx_tso_seg_pool_s { 658 uint16_t pool_size; 659 uint16_t num_free; 660 struct qdf_tso_seg_elem_t *freelist; 661 struct qdf_mem_multi_page_t desc_pages; 662 qdf_spinlock_t lock; 663 }; 664 665 /** 666 * struct dp_tx_tso_num_seg_pool_s { 667 * @num_seg_pool_size: total number of pool elements 668 * @num_free: free element count 669 * @freelist: first free element pointer 670 * @desc_pages: multiple page allocation information for actual descriptors 671 * @lock: lock for accessing the pool 672 */ 673 674 struct dp_tx_tso_num_seg_pool_s { 675 uint16_t num_seg_pool_size; 676 uint16_t num_free; 677 struct qdf_tso_num_seg_elem_t *freelist; 678 struct qdf_mem_multi_page_t desc_pages; 679 /*tso mutex */ 680 qdf_spinlock_t lock; 681 }; 682 683 /** 684 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 685 * @elem_size: Size of each descriptor in the pool 686 * @pool_size: Total number of descriptors in the pool 687 * @num_free: Number of free descriptors 688 * @num_allocated: Number of used descriptors 689 * @freelist: Chain of free descriptors 690 * @desc_pages: multiple page allocation information for actual descriptors 691 * @num_invalid_bin: Deleted pool with pending Tx completions. 692 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 693 * @flow_pool_array: List of allocated flow pools 694 * @lock- Lock for descriptor allocation/free from/to the pool 695 */ 696 struct dp_tx_desc_pool_s { 697 uint16_t elem_size; 698 uint32_t num_allocated; 699 struct dp_tx_desc_s *freelist; 700 struct qdf_mem_multi_page_t desc_pages; 701 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 702 uint16_t pool_size; 703 uint8_t flow_pool_id; 704 uint8_t num_invalid_bin; 705 uint16_t avail_desc; 706 enum flow_pool_status status; 707 enum htt_flow_type flow_type; 708 #ifdef QCA_AC_BASED_FLOW_CONTROL 709 uint16_t stop_th[FL_TH_MAX]; 710 uint16_t start_th[FL_TH_MAX]; 711 qdf_time_t max_pause_time[FL_TH_MAX]; 712 qdf_time_t latest_pause_time[FL_TH_MAX]; 713 #else 714 uint16_t stop_th; 715 uint16_t start_th; 716 #endif 717 uint16_t pkt_drop_no_desc; 718 qdf_spinlock_t flow_pool_lock; 719 uint8_t pool_create_cnt; 720 void *pool_owner_ctx; 721 #else 722 uint16_t elem_count; 723 uint32_t num_free; 724 qdf_spinlock_t lock; 725 #endif 726 }; 727 728 /** 729 * struct dp_txrx_pool_stats - flow pool related statistics 730 * @pool_map_count: flow pool map received 731 * @pool_unmap_count: flow pool unmap received 732 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 733 */ 734 struct dp_txrx_pool_stats { 735 uint16_t pool_map_count; 736 uint16_t pool_unmap_count; 737 uint16_t pkt_drop_no_pool; 738 }; 739 740 /** 741 * struct dp_srng - DP srng structure 742 * @hal_srng: hal_srng handle 743 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 744 * @base_vaddr_aligned: aligned virtual base address of the srng ring 745 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 746 * @base_paddr_aligned: aligned physical base address of the srng ring 747 * @alloc_size: size of the srng ring 748 * @cached: is the srng ring memory cached or un-cached memory 749 * @irq: irq number of the srng ring 750 * @num_entries: number of entries in the srng ring 751 * @is_mem_prealloc: Is this srng memory pre-allocated 752 * @crit_thresh: Critical threshold for near-full processing of this srng 753 * @safe_thresh: Safe threshold for near-full processing of this srng 754 * @near_full: Flag to indicate srng is near-full 755 */ 756 struct dp_srng { 757 hal_ring_handle_t hal_srng; 758 void *base_vaddr_unaligned; 759 void *base_vaddr_aligned; 760 qdf_dma_addr_t base_paddr_unaligned; 761 qdf_dma_addr_t base_paddr_aligned; 762 uint32_t alloc_size; 763 uint8_t cached; 764 int irq; 765 uint32_t num_entries; 766 #ifdef DP_MEM_PRE_ALLOC 767 uint8_t is_mem_prealloc; 768 #endif 769 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 770 uint16_t crit_thresh; 771 uint16_t safe_thresh; 772 qdf_atomic_t near_full; 773 #endif 774 }; 775 776 struct dp_rx_reorder_array_elem { 777 qdf_nbuf_t head; 778 qdf_nbuf_t tail; 779 }; 780 781 #define DP_RX_BA_INACTIVE 0 782 #define DP_RX_BA_ACTIVE 1 783 #define DP_RX_BA_IN_PROGRESS 2 784 struct dp_reo_cmd_info { 785 uint16_t cmd; 786 enum hal_reo_cmd_type cmd_type; 787 void *data; 788 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 789 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 790 }; 791 792 struct dp_peer_delay_stats { 793 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 794 [CDP_MAX_TXRX_CTX]; 795 }; 796 797 /* Rx TID defrag*/ 798 struct dp_rx_tid_defrag { 799 /* TID */ 800 int tid; 801 802 /* only used for defrag right now */ 803 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 804 805 /* Store dst desc for reinjection */ 806 hal_ring_desc_t dst_ring_desc; 807 struct dp_rx_desc *head_frag_desc; 808 809 /* Sequence and fragments that are being processed currently */ 810 uint32_t curr_seq_num; 811 uint32_t curr_frag_num; 812 813 /* TODO: Check the following while adding defragmentation support */ 814 struct dp_rx_reorder_array_elem *array; 815 /* base - single rx reorder element used for non-aggr cases */ 816 struct dp_rx_reorder_array_elem base; 817 /* rx_tid lock */ 818 qdf_spinlock_t defrag_tid_lock; 819 820 /* head PN number */ 821 uint64_t pn128[2]; 822 823 uint32_t defrag_timeout_ms; 824 825 /* defrag usage only, dp_peer pointer related with this tid */ 826 struct dp_txrx_peer *defrag_peer; 827 }; 828 829 /* Rx TID */ 830 struct dp_rx_tid { 831 /* TID */ 832 int tid; 833 834 /* Num of addba requests */ 835 uint32_t num_of_addba_req; 836 837 /* Num of addba responses */ 838 uint32_t num_of_addba_resp; 839 840 /* Num of delba requests */ 841 uint32_t num_of_delba_req; 842 843 /* Num of addba responses successful */ 844 uint32_t num_addba_rsp_success; 845 846 /* Num of addba responses failed */ 847 uint32_t num_addba_rsp_failed; 848 849 /* pn size */ 850 uint8_t pn_size; 851 /* REO TID queue descriptors */ 852 void *hw_qdesc_vaddr_unaligned; 853 void *hw_qdesc_vaddr_aligned; 854 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 855 qdf_dma_addr_t hw_qdesc_paddr; 856 uint32_t hw_qdesc_alloc_size; 857 858 /* RX ADDBA session state */ 859 int ba_status; 860 861 /* RX BA window size */ 862 uint16_t ba_win_size; 863 864 /* Starting sequence number in Addba request */ 865 uint16_t startseqnum; 866 uint16_t dialogtoken; 867 uint16_t statuscode; 868 /* user defined ADDBA response status code */ 869 uint16_t userstatuscode; 870 871 /* rx_tid lock */ 872 qdf_spinlock_t tid_lock; 873 874 /* Store ppdu_id when 2k exception is received */ 875 uint32_t ppdu_id_2k; 876 877 /* Delba Tx completion status */ 878 uint8_t delba_tx_status; 879 880 /* Delba Tx retry count */ 881 uint8_t delba_tx_retry; 882 883 /* Delba stats */ 884 uint32_t delba_tx_success_cnt; 885 uint32_t delba_tx_fail_cnt; 886 887 /* Delba reason code for retries */ 888 uint8_t delba_rcode; 889 890 /* Coex Override preserved windows size 1 based */ 891 uint16_t rx_ba_win_size_override; 892 #ifdef IPA_OFFLOAD 893 /* rx msdu count per tid */ 894 struct cdp_pkt_info rx_msdu_cnt; 895 #endif 896 897 }; 898 899 /** 900 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 901 * @num_tx_ring_masks: interrupts with tx_ring_mask set 902 * @num_rx_ring_masks: interrupts with rx_ring_mask set 903 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 904 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 905 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 906 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 907 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 908 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 909 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 910 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 911 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 912 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 913 * near full interrupt was received 914 * @num_reo_status_ring_near_full_masks: total number of times the reo status 915 * near full interrupt was received 916 * @num_near_full_masks: total number of times the near full interrupt 917 * was received 918 * @num_masks: total number of times the interrupt was received 919 * @num_host2txmon_ring_masks: interrupts with host2txmon_ring_mask set 920 * @num_near_full_masks: total number of times the interrupt was received 921 * @num_masks: total number of times the near full interrupt was received 922 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 923 * 924 * Counter for individual masks are incremented only if there are any packets 925 * on that ring. 926 */ 927 struct dp_intr_stats { 928 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 929 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 930 uint32_t num_rx_mon_ring_masks; 931 uint32_t num_rx_err_ring_masks; 932 uint32_t num_rx_wbm_rel_ring_masks; 933 uint32_t num_reo_status_ring_masks; 934 uint32_t num_rxdma2host_ring_masks; 935 uint32_t num_host2rxdma_ring_masks; 936 uint32_t num_host2rxdma_mon_ring_masks; 937 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 938 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 939 uint32_t num_rx_wbm_rel_ring_near_full_masks; 940 uint32_t num_reo_status_ring_near_full_masks; 941 uint32_t num_host2txmon_ring__masks; 942 uint32_t num_near_full_masks; 943 uint32_t num_masks; 944 uint32_t num_tx_mon_ring_masks; 945 }; 946 947 #ifdef DP_UMAC_HW_RESET_SUPPORT 948 /** 949 * struct dp_intr_bkp - DP per interrupt context ring masks old state 950 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 951 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 952 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 953 * @rx_err_ring_mask: REO Exception Ring 954 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 955 * @reo_status_ring_mask: REO command response ring 956 * @rxdma2host_ring_mask: RXDMA to host destination ring 957 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 958 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 959 * @host2txmon_ring_mask: Tx monitor buffer ring 960 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 961 * 962 */ 963 struct dp_intr_bkp { 964 uint8_t tx_ring_mask; 965 uint8_t rx_ring_mask; 966 uint8_t rx_mon_ring_mask; 967 uint8_t rx_err_ring_mask; 968 uint8_t rx_wbm_rel_ring_mask; 969 uint8_t reo_status_ring_mask; 970 uint8_t rxdma2host_ring_mask; 971 uint8_t host2rxdma_ring_mask; 972 uint8_t host2rxdma_mon_ring_mask; 973 uint8_t host2txmon_ring_mask; 974 uint8_t tx_mon_ring_mask; 975 }; 976 #endif 977 978 /* per interrupt context */ 979 struct dp_intr { 980 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 981 associated with this napi context */ 982 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 983 with this interrupt context */ 984 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 985 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 986 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 987 uint8_t reo_status_ring_mask; /* REO command response ring */ 988 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 989 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 990 /* Host to RXDMA monitor buffer ring */ 991 uint8_t host2rxdma_mon_ring_mask; 992 /* RX REO rings near full interrupt mask */ 993 uint8_t rx_near_full_grp_1_mask; 994 /* RX REO rings near full interrupt mask */ 995 uint8_t rx_near_full_grp_2_mask; 996 /* WBM TX completion rings near full interrupt mask */ 997 uint8_t tx_ring_near_full_mask; 998 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 999 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1000 struct dp_soc *soc; /* Reference to SoC structure , 1001 to get DMA ring handles */ 1002 qdf_lro_ctx_t lro_ctx; 1003 uint8_t dp_intr_id; 1004 1005 /* Interrupt Stats for individual masks */ 1006 struct dp_intr_stats intr_stats; 1007 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1008 }; 1009 1010 #define REO_DESC_FREELIST_SIZE 64 1011 #define REO_DESC_FREE_DEFER_MS 1000 1012 struct reo_desc_list_node { 1013 qdf_list_node_t node; 1014 unsigned long free_ts; 1015 struct dp_rx_tid rx_tid; 1016 bool resend_update_reo_cmd; 1017 uint32_t pending_ext_desc_size; 1018 #ifdef REO_QDESC_HISTORY 1019 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1020 #endif 1021 }; 1022 1023 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1024 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1025 #define REO_DESC_DEFERRED_FREE_MS 30000 1026 1027 struct reo_desc_deferred_freelist_node { 1028 qdf_list_node_t node; 1029 unsigned long free_ts; 1030 void *hw_qdesc_vaddr_unaligned; 1031 qdf_dma_addr_t hw_qdesc_paddr; 1032 uint32_t hw_qdesc_alloc_size; 1033 #ifdef REO_QDESC_HISTORY 1034 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1035 #endif /* REO_QDESC_HISTORY */ 1036 }; 1037 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1038 1039 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1040 /** 1041 * struct reo_cmd_event_record: Elements to record for each reo command 1042 * @cmd_type: reo command type 1043 * @cmd_return_status: reo command post status 1044 * @timestamp: record timestamp for the reo command 1045 */ 1046 struct reo_cmd_event_record { 1047 enum hal_reo_cmd_type cmd_type; 1048 uint8_t cmd_return_status; 1049 uint64_t timestamp; 1050 }; 1051 1052 /** 1053 * struct reo_cmd_event_history: Account for reo cmd events 1054 * @index: record number 1055 * @cmd_record: list of records 1056 */ 1057 struct reo_cmd_event_history { 1058 qdf_atomic_t index; 1059 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1060 }; 1061 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1062 1063 /* SoC level data path statistics */ 1064 struct dp_soc_stats { 1065 struct { 1066 uint32_t added; 1067 uint32_t deleted; 1068 uint32_t aged_out; 1069 uint32_t map_err; 1070 uint32_t ast_mismatch; 1071 } ast; 1072 1073 struct { 1074 uint32_t added; 1075 uint32_t deleted; 1076 } mec; 1077 1078 /* SOC level TX stats */ 1079 struct { 1080 /* Total packets transmitted */ 1081 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1082 /* Enqueues per tcl ring */ 1083 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1084 /* packets dropped on tx because of no peer */ 1085 struct cdp_pkt_info tx_invalid_peer; 1086 /* descriptors in each tcl ring */ 1087 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1088 /* Descriptors in use at soc */ 1089 uint32_t desc_in_use; 1090 /* tqm_release_reason == FW removed */ 1091 uint32_t dropped_fw_removed; 1092 /* tx completion release_src != TQM or FW */ 1093 uint32_t invalid_release_source; 1094 /* tx completion wbm_internal_error */ 1095 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1096 /* tx completion non_wbm_internal_error */ 1097 uint32_t non_wbm_internal_err; 1098 /* TX Comp loop packet limit hit */ 1099 uint32_t tx_comp_loop_pkt_limit_hit; 1100 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1101 uint32_t hp_oos2; 1102 /* tx desc freed as part of vdev detach */ 1103 uint32_t tx_comp_exception; 1104 /* TQM drops after/during peer delete */ 1105 uint64_t tqm_drop_no_peer; 1106 /* Number of tx completions reaped per WBM2SW release ring */ 1107 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1108 /* Number of tx completions force freed */ 1109 uint32_t tx_comp_force_freed; 1110 } tx; 1111 1112 /* SOC level RX stats */ 1113 struct { 1114 /* Total rx packets count */ 1115 struct cdp_pkt_info ingress; 1116 /* Rx errors */ 1117 /* Total Packets in Rx Error ring */ 1118 uint32_t err_ring_pkts; 1119 /* No of Fragments */ 1120 uint32_t rx_frags; 1121 /* No of incomplete fragments in waitlist */ 1122 uint32_t rx_frag_wait; 1123 /* Fragments dropped due to errors */ 1124 uint32_t rx_frag_err; 1125 /* Fragments received OOR causing sequence num mismatch */ 1126 uint32_t rx_frag_oor; 1127 /* Fragments dropped due to len errors in skb */ 1128 uint32_t rx_frag_err_len_error; 1129 /* Fragments dropped due to no peer found */ 1130 uint32_t rx_frag_err_no_peer; 1131 /* No of reinjected packets */ 1132 uint32_t reo_reinject; 1133 /* Reap loop packet limit hit */ 1134 uint32_t reap_loop_pkt_limit_hit; 1135 /* Head pointer Out of sync at the end of dp_rx_process */ 1136 uint32_t hp_oos2; 1137 /* Rx ring near full */ 1138 uint32_t near_full; 1139 /* Break ring reaping as not all scattered msdu received */ 1140 uint32_t msdu_scatter_wait_break; 1141 /* Number of bar frames received */ 1142 uint32_t bar_frame; 1143 /* Number of frames routed from rxdma */ 1144 uint32_t rxdma2rel_route_drop; 1145 /* Number of frames routed from reo*/ 1146 uint32_t reo2rel_route_drop; 1147 1148 struct { 1149 /* Invalid RBM error count */ 1150 uint32_t invalid_rbm; 1151 /* Invalid VDEV Error count */ 1152 uint32_t invalid_vdev; 1153 /* Invalid PDEV error count */ 1154 uint32_t invalid_pdev; 1155 1156 /* Packets delivered to stack that no related peer */ 1157 uint32_t pkt_delivered_no_peer; 1158 /* Defrag peer uninit error count */ 1159 uint32_t defrag_peer_uninit; 1160 /* Invalid sa_idx or da_idx*/ 1161 uint32_t invalid_sa_da_idx; 1162 /* MSDU DONE failures */ 1163 uint32_t msdu_done_fail; 1164 /* Invalid PEER Error count */ 1165 struct cdp_pkt_info rx_invalid_peer; 1166 /* Invalid PEER ID count */ 1167 struct cdp_pkt_info rx_invalid_peer_id; 1168 /* Invalid packet length */ 1169 struct cdp_pkt_info rx_invalid_pkt_len; 1170 /* HAL ring access Fail error count */ 1171 uint32_t hal_ring_access_fail; 1172 /* HAL ring access full Fail error count */ 1173 uint32_t hal_ring_access_full_fail; 1174 /* RX DMA error count */ 1175 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1176 /* RX REO DEST Desc Invalid Magic count */ 1177 uint32_t rx_desc_invalid_magic; 1178 /* REO Error count */ 1179 uint32_t reo_error[HAL_REO_ERR_MAX]; 1180 /* HAL REO ERR Count */ 1181 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1182 /* HAL REO DEST Duplicate count */ 1183 uint32_t hal_reo_dest_dup; 1184 /* HAL WBM RELEASE Duplicate count */ 1185 uint32_t hal_wbm_rel_dup; 1186 /* HAL RXDMA error Duplicate count */ 1187 uint32_t hal_rxdma_err_dup; 1188 /* ipa smmu map duplicate count */ 1189 uint32_t ipa_smmu_map_dup; 1190 /* ipa smmu unmap duplicate count */ 1191 uint32_t ipa_smmu_unmap_dup; 1192 /* ipa smmu unmap while ipa pipes is disabled */ 1193 uint32_t ipa_unmap_no_pipe; 1194 /* REO cmd send fail/requeue count */ 1195 uint32_t reo_cmd_send_fail; 1196 /* REO cmd send drain count */ 1197 uint32_t reo_cmd_send_drain; 1198 /* RX msdu drop count due to scatter */ 1199 uint32_t scatter_msdu; 1200 /* RX msdu drop count due to invalid cookie */ 1201 uint32_t invalid_cookie; 1202 /* Count of stale cookie read in RX path */ 1203 uint32_t stale_cookie; 1204 /* Delba sent count due to RX 2k jump */ 1205 uint32_t rx_2k_jump_delba_sent; 1206 /* RX 2k jump msdu indicated to stack count */ 1207 uint32_t rx_2k_jump_to_stack; 1208 /* RX 2k jump msdu dropped count */ 1209 uint32_t rx_2k_jump_drop; 1210 /* REO ERR msdu buffer received */ 1211 uint32_t reo_err_msdu_buf_rcved; 1212 /* REO ERR msdu buffer with invalid coookie received */ 1213 uint32_t reo_err_msdu_buf_invalid_cookie; 1214 /* REO OOR msdu drop count */ 1215 uint32_t reo_err_oor_drop; 1216 /* REO OOR msdu indicated to stack count */ 1217 uint32_t reo_err_oor_to_stack; 1218 /* REO OOR scattered msdu count */ 1219 uint32_t reo_err_oor_sg_count; 1220 /* REO ERR RAW mpdu drops */ 1221 uint32_t reo_err_raw_mpdu_drop; 1222 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1223 uint32_t rejected; 1224 /* Incorrect msdu count in MPDU desc info */ 1225 uint32_t msdu_count_mismatch; 1226 /* RX raw frame dropped count */ 1227 uint32_t raw_frm_drop; 1228 /* Stale link desc cookie count*/ 1229 uint32_t invalid_link_cookie; 1230 /* Nbuf sanity failure */ 1231 uint32_t nbuf_sanity_fail; 1232 /* Duplicate link desc refilled */ 1233 uint32_t dup_refill_link_desc; 1234 /* Incorrect msdu continuation bit in MSDU desc */ 1235 uint32_t msdu_continuation_err; 1236 /* count of start sequence (ssn) updates */ 1237 uint32_t ssn_update_count; 1238 /* count of bar handling fail */ 1239 uint32_t bar_handle_fail_count; 1240 /* EAPOL drop count in intrabss scenario */ 1241 uint32_t intrabss_eapol_drop; 1242 /* PN check failed for 2K-jump or OOR error */ 1243 uint32_t pn_in_dest_check_fail; 1244 /* MSDU len err count */ 1245 uint32_t msdu_len_err; 1246 /* Rx flush count */ 1247 uint32_t rx_flush_count; 1248 /* Rx invalid tid count */ 1249 uint32_t rx_invalid_tid_err; 1250 } err; 1251 1252 /* packet count per core - per ring */ 1253 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1254 } rx; 1255 1256 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1257 struct reo_cmd_event_history cmd_event_history; 1258 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1259 }; 1260 1261 union dp_align_mac_addr { 1262 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1263 struct { 1264 uint16_t bytes_ab; 1265 uint16_t bytes_cd; 1266 uint16_t bytes_ef; 1267 } align2; 1268 struct { 1269 uint32_t bytes_abcd; 1270 uint16_t bytes_ef; 1271 } align4; 1272 struct __attribute__((__packed__)) { 1273 uint16_t bytes_ab; 1274 uint32_t bytes_cdef; 1275 } align4_2; 1276 }; 1277 1278 /** 1279 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1280 * @mac_addr: ast mac address 1281 * @peer_mac_addr: mac address of peer 1282 * @type: ast entry type 1283 * @vdev_id: vdev_id 1284 * @flags: ast flags 1285 */ 1286 struct dp_ast_free_cb_params { 1287 union dp_align_mac_addr mac_addr; 1288 union dp_align_mac_addr peer_mac_addr; 1289 enum cdp_txrx_ast_entry_type type; 1290 uint8_t vdev_id; 1291 uint32_t flags; 1292 }; 1293 1294 /* 1295 * dp_ast_entry 1296 * 1297 * @ast_idx: Hardware AST Index 1298 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1299 * associated peer with this MAC address) 1300 * @mac_addr: MAC Address for this AST entry 1301 * @next_hop: Set to 1 if this is for a WDS node 1302 * @is_active: flag to indicate active data traffic on this node 1303 * (used for aging out/expiry) 1304 * @ase_list_elem: node in peer AST list 1305 * @is_bss: flag to indicate if entry corresponds to bss peer 1306 * @is_mapped: flag to indicate that we have mapped the AST entry 1307 * in ast_table 1308 * @pdev_id: pdev ID 1309 * @vdev_id: vdev ID 1310 * @ast_hash_value: hast value in HW 1311 * @ref_cnt: reference count 1312 * @type: flag to indicate type of the entry(static/WDS/MEC) 1313 * @delete_in_progress: Flag to indicate that delete commands send to FW 1314 * and host is waiting for response from FW 1315 * @callback: ast free/unmap callback 1316 * @cookie: argument to callback 1317 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1318 */ 1319 struct dp_ast_entry { 1320 uint16_t ast_idx; 1321 uint16_t peer_id; 1322 union dp_align_mac_addr mac_addr; 1323 bool next_hop; 1324 bool is_active; 1325 bool is_mapped; 1326 uint8_t pdev_id; 1327 uint8_t vdev_id; 1328 uint16_t ast_hash_value; 1329 qdf_atomic_t ref_cnt; 1330 enum cdp_txrx_ast_entry_type type; 1331 bool delete_in_progress; 1332 txrx_ast_free_cb callback; 1333 void *cookie; 1334 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1335 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1336 }; 1337 1338 /* 1339 * dp_mec_entry 1340 * 1341 * @mac_addr: MAC Address for this MEC entry 1342 * @is_active: flag to indicate active data traffic on this node 1343 * (used for aging out/expiry) 1344 * @pdev_id: pdev ID 1345 * @vdev_id: vdev ID 1346 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1347 */ 1348 struct dp_mec_entry { 1349 union dp_align_mac_addr mac_addr; 1350 bool is_active; 1351 uint8_t pdev_id; 1352 uint8_t vdev_id; 1353 1354 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1355 }; 1356 1357 /* SOC level htt stats */ 1358 struct htt_t2h_stats { 1359 /* lock to protect htt_stats_msg update */ 1360 qdf_spinlock_t lock; 1361 1362 /* work queue to process htt stats */ 1363 qdf_work_t work; 1364 1365 /* T2H Ext stats message queue */ 1366 qdf_nbuf_queue_t msg; 1367 1368 /* number of completed stats in htt_stats_msg */ 1369 uint32_t num_stats; 1370 }; 1371 1372 struct link_desc_bank { 1373 void *base_vaddr_unaligned; 1374 void *base_vaddr; 1375 qdf_dma_addr_t base_paddr_unaligned; 1376 qdf_dma_addr_t base_paddr; 1377 uint32_t size; 1378 }; 1379 1380 struct rx_buff_pool { 1381 qdf_nbuf_queue_head_t emerg_nbuf_q; 1382 uint32_t nbuf_fail_cnt; 1383 bool is_initialized; 1384 }; 1385 1386 struct rx_refill_buff_pool { 1387 bool is_initialized; 1388 uint16_t head; 1389 uint16_t tail; 1390 struct dp_pdev *dp_pdev; 1391 uint16_t max_bufq_len; 1392 qdf_nbuf_t buf_elem[2048]; 1393 }; 1394 1395 #ifdef DP_TX_HW_DESC_HISTORY 1396 #define DP_TX_HW_DESC_HIST_MAX 6144 1397 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1398 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1399 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1400 1401 struct dp_tx_hw_desc_evt { 1402 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1403 uint8_t tcl_ring_id; 1404 uint64_t posted; 1405 uint32_t hp; 1406 uint32_t tp; 1407 }; 1408 1409 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1410 * @index: Index where the last entry is written 1411 * @entry: history entries 1412 */ 1413 struct dp_tx_hw_desc_history { 1414 qdf_atomic_t index; 1415 uint16_t num_entries_per_slot; 1416 uint16_t allocated; 1417 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1418 }; 1419 #endif 1420 1421 /* 1422 * enum dp_mon_status_process_event - Events for monitor status buffer record 1423 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1424 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1425 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1426 */ 1427 enum dp_mon_status_process_event { 1428 DP_MON_STATUS_BUF_REAP, 1429 DP_MON_STATUS_BUF_ENQUEUE, 1430 DP_MON_STATUS_BUF_DEQUEUE, 1431 }; 1432 1433 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1434 #define DP_MON_STATUS_HIST_MAX 2048 1435 1436 /** 1437 * struct dp_buf_info_record - ring buffer info 1438 * @hbi: HW ring buffer info 1439 * @timestamp: timestamp when this entry was recorded 1440 * @event: event 1441 * @rx_desc: RX descriptor corresponding to the received buffer 1442 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1443 * which was enqueued or dequeued. 1444 * @rx_desc_nbuf_data: nbuf data pointer. 1445 */ 1446 struct dp_mon_stat_info_record { 1447 struct hal_buf_info hbi; 1448 uint64_t timestamp; 1449 enum dp_mon_status_process_event event; 1450 void *rx_desc; 1451 qdf_nbuf_t nbuf; 1452 uint8_t *rx_desc_nbuf_data; 1453 }; 1454 1455 /* struct dp_rx_history - rx ring hisotry 1456 * @index: Index where the last entry is written 1457 * @entry: history entries 1458 */ 1459 struct dp_mon_status_ring_history { 1460 qdf_atomic_t index; 1461 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1462 }; 1463 #endif 1464 1465 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1466 /* 1467 * The logic for get current index of these history is dependent on this 1468 * value being power of 2. 1469 */ 1470 #define DP_RX_HIST_MAX 2048 1471 #define DP_RX_ERR_HIST_MAX 2048 1472 #define DP_RX_REINJECT_HIST_MAX 1024 1473 #define DP_RX_REFILL_HIST_MAX 2048 1474 1475 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1476 (DP_RX_HIST_MAX & 1477 (DP_RX_HIST_MAX - 1)) == 0); 1478 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1479 (DP_RX_ERR_HIST_MAX & 1480 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1481 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1482 (DP_RX_REINJECT_HIST_MAX & 1483 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1484 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1485 (DP_RX_REFILL_HIST_MAX & 1486 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1487 1488 1489 /** 1490 * struct dp_buf_info_record - ring buffer info 1491 * @hbi: HW ring buffer info 1492 * @timestamp: timestamp when this entry was recorded 1493 */ 1494 struct dp_buf_info_record { 1495 struct hal_buf_info hbi; 1496 uint64_t timestamp; 1497 }; 1498 1499 /** 1500 * struct dp_refill_info_record - ring refill buffer info 1501 * @hp: HP value after refill 1502 * @tp: cached tail value during refill 1503 * @num_req: number of buffers requested to refill 1504 * @num_refill: number of buffers refilled to ring 1505 * @timestamp: timestamp when this entry was recorded 1506 */ 1507 struct dp_refill_info_record { 1508 uint32_t hp; 1509 uint32_t tp; 1510 uint32_t num_req; 1511 uint32_t num_refill; 1512 uint64_t timestamp; 1513 }; 1514 1515 /* struct dp_rx_history - rx ring hisotry 1516 * @index: Index where the last entry is written 1517 * @entry: history entries 1518 */ 1519 struct dp_rx_history { 1520 qdf_atomic_t index; 1521 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1522 }; 1523 1524 /* struct dp_rx_err_history - rx err ring hisotry 1525 * @index: Index where the last entry is written 1526 * @entry: history entries 1527 */ 1528 struct dp_rx_err_history { 1529 qdf_atomic_t index; 1530 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1531 }; 1532 1533 /* struct dp_rx_reinject_history - rx reinject ring hisotry 1534 * @index: Index where the last entry is written 1535 * @entry: history entries 1536 */ 1537 struct dp_rx_reinject_history { 1538 qdf_atomic_t index; 1539 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1540 }; 1541 1542 /* struct dp_rx_refill_history - rx buf refill hisotry 1543 * @index: Index where the last entry is written 1544 * @entry: history entries 1545 */ 1546 struct dp_rx_refill_history { 1547 qdf_atomic_t index; 1548 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1549 }; 1550 1551 #endif 1552 1553 enum dp_tx_event_type { 1554 DP_TX_DESC_INVAL_EVT = 0, 1555 DP_TX_DESC_MAP, 1556 DP_TX_DESC_COOKIE, 1557 DP_TX_DESC_FLUSH, 1558 DP_TX_DESC_UNMAP, 1559 DP_TX_COMP_UNMAP, 1560 DP_TX_COMP_UNMAP_ERR, 1561 DP_TX_COMP_MSDU_EXT, 1562 }; 1563 1564 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1565 /* Size must be in 2 power, for bitwise index rotation */ 1566 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1567 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1568 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1569 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1570 1571 /* Size must be in 2 power, for bitwise index rotation */ 1572 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1573 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1574 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1575 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1576 1577 struct dp_tx_desc_event { 1578 qdf_nbuf_t skb; 1579 dma_addr_t paddr; 1580 uint32_t sw_cookie; 1581 enum dp_tx_event_type type; 1582 uint64_t ts; 1583 }; 1584 1585 struct dp_tx_tcl_history { 1586 qdf_atomic_t index; 1587 uint16_t num_entries_per_slot; 1588 uint16_t allocated; 1589 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1590 }; 1591 1592 struct dp_tx_comp_history { 1593 qdf_atomic_t index; 1594 uint16_t num_entries_per_slot; 1595 uint16_t allocated; 1596 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1597 }; 1598 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1599 1600 /* structure to record recent operation related variable */ 1601 struct dp_last_op_info { 1602 /* last link desc buf info through WBM release ring */ 1603 struct hal_buf_info wbm_rel_link_desc; 1604 /* last link desc buf info through REO reinject ring */ 1605 struct hal_buf_info reo_reinject_link_desc; 1606 }; 1607 1608 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1609 1610 /** 1611 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1612 * decision making 1613 * @nbuf: TX packet 1614 * @tid: tid for transmitting the current packet 1615 * @num_ll_connections: Number of low latency connections on this vdev 1616 * @ring_id: TCL ring id 1617 * @pkt_len: Packet length 1618 * 1619 * This structure contains the information required by the software 1620 * latency manager to decide on whether to coalesce the current TCL 1621 * register write or not. 1622 */ 1623 struct dp_swlm_tcl_data { 1624 qdf_nbuf_t nbuf; 1625 uint8_t tid; 1626 uint8_t num_ll_connections; 1627 uint8_t ring_id; 1628 uint32_t pkt_len; 1629 }; 1630 1631 /** 1632 * union swlm_data - SWLM query data 1633 * @tcl_data: data for TCL query in SWLM 1634 */ 1635 union swlm_data { 1636 struct dp_swlm_tcl_data *tcl_data; 1637 }; 1638 1639 /** 1640 * struct dp_swlm_ops - SWLM ops 1641 * @tcl_wr_coalesce_check: handler to check if the current TCL register 1642 * write can be coalesced or not 1643 */ 1644 struct dp_swlm_ops { 1645 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 1646 struct dp_swlm_tcl_data *tcl_data); 1647 }; 1648 1649 /** 1650 * struct dp_swlm_stats - Stats for Software Latency manager. 1651 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 1652 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 1653 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 1654 * was being transmitted on a TID above coalescing threshold 1655 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 1656 * being transmitted was a special frame 1657 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 1658 * vdev has low latency connections 1659 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 1660 * bytes threshold was reached 1661 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 1662 * session time expired 1663 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 1664 * throughput did not meet session threshold 1665 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 1666 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 1667 */ 1668 struct dp_swlm_stats { 1669 struct { 1670 uint32_t timer_flush_success; 1671 uint32_t timer_flush_fail; 1672 uint32_t tid_fail; 1673 uint32_t sp_frames; 1674 uint32_t ll_connection; 1675 uint32_t bytes_thresh_reached; 1676 uint32_t time_thresh_reached; 1677 uint32_t tput_criteria_fail; 1678 uint32_t coalesce_success; 1679 uint32_t coalesce_fail; 1680 } tcl[MAX_TCL_DATA_RINGS]; 1681 }; 1682 1683 /** 1684 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 1685 * in the Software latency manager. 1686 * @soc: DP soc reference 1687 * @ring_id: TCL ring id 1688 * @flush_timer: Timer for flushing the coalesced TCL HP writes 1689 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 1690 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 1691 * @coalesce_end_time: End timestamp for current coalescing session 1692 * @bytes_coalesced: Num bytes coalesced in the current session 1693 * @prev_tx_packets: Previous TX packets accounted 1694 * @prev_tx_bytes: Previous TX bytes accounted 1695 * @prev_rx_bytes: Previous RX bytes accounted 1696 * @expire_time: expiry time for sample 1697 * @tput_pass_cnt: threshold throughput pass counter 1698 */ 1699 struct dp_swlm_tcl_params { 1700 struct dp_soc *soc; 1701 uint32_t ring_id; 1702 qdf_timer_t flush_timer; 1703 uint32_t sampling_session_tx_bytes; 1704 uint32_t bytes_flush_thresh; 1705 uint64_t coalesce_end_time; 1706 uint32_t bytes_coalesced; 1707 uint32_t prev_tx_packets; 1708 uint32_t prev_tx_bytes; 1709 uint32_t prev_rx_bytes; 1710 uint64_t expire_time; 1711 uint32_t tput_pass_cnt; 1712 }; 1713 1714 /** 1715 * struct dp_swlm_params: Parameters for different modules in the 1716 * Software latency manager. 1717 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 1718 * write coalescing 1719 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 1720 * write coalescing 1721 * @sampling_time: Sampling time to test the throughput threshold 1722 * @time_flush_thresh: Time threshold to flush the TCL HP register write 1723 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 1724 * which the TCL HP register is written, thereby 1725 * ending the coalescing. 1726 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 1727 * write coalescing 1728 * @tcl: TCL ring specific params 1729 */ 1730 1731 struct dp_swlm_params { 1732 uint32_t rx_traffic_thresh; 1733 uint32_t tx_traffic_thresh; 1734 uint32_t sampling_time; 1735 uint32_t time_flush_thresh; 1736 uint32_t tx_thresh_multiplier; 1737 uint32_t tx_pkt_thresh; 1738 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 1739 }; 1740 1741 /** 1742 * struct dp_swlm - Software latency manager context 1743 * @ops: SWLM ops pointers 1744 * @is_enabled: SWLM enabled/disabled 1745 * @is_init: SWLM module initialized 1746 * @stats: SWLM stats 1747 * @params: SWLM SRNG params 1748 * @tcl_flush_timer: flush timer for TCL register writes 1749 */ 1750 struct dp_swlm { 1751 struct dp_swlm_ops *ops; 1752 uint8_t is_enabled:1, 1753 is_init:1; 1754 struct dp_swlm_stats stats; 1755 struct dp_swlm_params params; 1756 }; 1757 #endif 1758 1759 #ifdef IPA_OFFLOAD 1760 /* IPA uC datapath offload Wlan Tx resources */ 1761 struct ipa_dp_tx_rsc { 1762 /* Resource info to be passed to IPA */ 1763 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 1764 void *ipa_tcl_ring_base_vaddr; 1765 uint32_t ipa_tcl_ring_size; 1766 qdf_dma_addr_t ipa_tcl_hp_paddr; 1767 uint32_t alloc_tx_buf_cnt; 1768 1769 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 1770 void *ipa_wbm_ring_base_vaddr; 1771 uint32_t ipa_wbm_ring_size; 1772 qdf_dma_addr_t ipa_wbm_tp_paddr; 1773 /* WBM2SW HP shadow paddr */ 1774 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 1775 1776 /* TX buffers populated into the WBM ring */ 1777 void **tx_buf_pool_vaddr_unaligned; 1778 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 1779 }; 1780 1781 /* IPA uC datapath offload Wlan Rx resources */ 1782 struct ipa_dp_rx_rsc { 1783 /* Resource info to be passed to IPA */ 1784 qdf_dma_addr_t ipa_reo_ring_base_paddr; 1785 void *ipa_reo_ring_base_vaddr; 1786 uint32_t ipa_reo_ring_size; 1787 qdf_dma_addr_t ipa_reo_tp_paddr; 1788 1789 /* Resource info to be passed to firmware and IPA */ 1790 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 1791 void *ipa_rx_refill_buf_ring_base_vaddr; 1792 uint32_t ipa_rx_refill_buf_ring_size; 1793 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1794 }; 1795 #endif 1796 1797 struct dp_tx_msdu_info_s; 1798 /* 1799 * enum dp_context_type- DP Context Type 1800 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 1801 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 1802 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 1803 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 1804 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 1805 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 1806 * 1807 * Helper enums to be used to retrieve the size of the corresponding 1808 * data structure by passing the type. 1809 */ 1810 enum dp_context_type { 1811 DP_CONTEXT_TYPE_SOC, 1812 DP_CONTEXT_TYPE_PDEV, 1813 DP_CONTEXT_TYPE_VDEV, 1814 DP_CONTEXT_TYPE_PEER, 1815 DP_CONTEXT_TYPE_MON_SOC, 1816 DP_CONTEXT_TYPE_MON_PDEV 1817 }; 1818 1819 /* 1820 * struct dp_arch_ops- DP target specific arch ops 1821 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 1822 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 1823 * @tx_hw_enqueue: enqueue TX data to HW 1824 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 1825 * source from HAL desc for wbm release ring 1826 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 1827 * @txrx_set_vdev_param: target specific ops while setting vdev params 1828 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 1829 * and set the near-full params. 1830 * @ipa_get_bank_id: Get TCL bank id used by IPA 1831 */ 1832 struct dp_arch_ops { 1833 /* INIT/DEINIT Arch Ops */ 1834 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 1835 struct cdp_soc_attach_params *params); 1836 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 1837 QDF_STATUS (*txrx_soc_init)(struct dp_soc *soc); 1838 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 1839 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 1840 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 1841 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 1842 void (*txrx_soc_srng_free)(struct dp_soc *soc); 1843 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 1844 struct cdp_pdev_attach_params *params); 1845 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 1846 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 1847 struct dp_vdev *vdev); 1848 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 1849 struct dp_vdev *vdev); 1850 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 1851 void (*txrx_peer_map_detach)(struct dp_soc *soc); 1852 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 1853 void (*soc_cfg_attach)(struct dp_soc *soc); 1854 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 1855 struct cdp_peer_setup_info *setup_info, 1856 enum cdp_host_reo_dest_ring *reo_dest, 1857 bool *hash_based, 1858 uint8_t *lmac_peer_id_msb); 1859 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 1860 uint32_t *remap1, uint32_t *remap2); 1861 1862 /* TX RX Arch Ops */ 1863 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 1864 struct dp_tx_desc_s *tx_desc, 1865 uint16_t fw_metadata, 1866 struct cdp_tx_exception_metadata *metadata, 1867 struct dp_tx_msdu_info_s *msdu_info); 1868 1869 void (*tx_comp_get_params_from_hal_desc)(struct dp_soc *soc, 1870 void *tx_comp_hal_desc, 1871 struct dp_tx_desc_s **desc); 1872 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 1873 struct dp_tx_desc_s *tx_desc, 1874 uint8_t *status, 1875 uint8_t ring_id); 1876 1877 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 1878 hal_ring_handle_t hal_ring_hdl, 1879 uint8_t reo_ring_num, uint32_t quota); 1880 1881 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 1882 uint8_t vdev_id, 1883 qdf_nbuf_t nbuf); 1884 1885 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 1886 uint32_t num_elem, 1887 uint8_t pool_id); 1888 void (*dp_tx_desc_pool_deinit)( 1889 struct dp_soc *soc, 1890 struct dp_tx_desc_pool_s *tx_desc_pool, 1891 uint8_t pool_id); 1892 1893 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 1894 struct rx_desc_pool *rx_desc_pool, 1895 uint32_t pool_id); 1896 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 1897 struct rx_desc_pool *rx_desc_pool, 1898 uint32_t pool_id); 1899 1900 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 1901 struct dp_soc *soc, 1902 void *ring_desc, 1903 struct dp_rx_desc **r_rx_desc); 1904 1905 bool 1906 (*dp_rx_intrabss_handle_nawds)(struct dp_soc *soc, 1907 struct dp_txrx_peer *ta_txrx_peer, 1908 qdf_nbuf_t nbuf_copy, 1909 struct cdp_tid_rx_stats *tid_stats); 1910 1911 void (*dp_rx_word_mask_subscribe)( 1912 struct dp_soc *soc, 1913 uint32_t *msg_word, 1914 void *rx_filter); 1915 1916 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 1917 uint32_t cookie); 1918 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 1919 struct dp_intr *int_ctx, 1920 uint32_t dp_budget); 1921 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 1922 uint8_t bm_id); 1923 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 1924 uint32_t peer_metadata); 1925 /* Control Arch Ops */ 1926 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 1927 struct dp_vdev *vdev, 1928 enum cdp_vdev_param_type param, 1929 cdp_config_param_type val); 1930 1931 /* Misc Arch Ops */ 1932 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 1933 #ifdef WIFI_MONITOR_SUPPORT 1934 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 1935 #endif 1936 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 1937 struct dp_srng *dp_srng, 1938 int *max_reap_limit); 1939 1940 /* MLO ops */ 1941 #ifdef WLAN_FEATURE_11BE_MLO 1942 #ifdef WLAN_MCAST_MLO 1943 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 1944 qdf_nbuf_t nbuf); 1945 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 1946 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf); 1947 #endif 1948 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 1949 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 1950 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 1951 struct dp_peer *peer); 1952 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 1953 struct dp_peer *peer); 1954 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 1955 uint8_t *peer_mac_addr, 1956 int mac_addr_is_aligned, 1957 enum dp_mod_id mod_id, 1958 uint8_t vdev_id); 1959 #endif 1960 void (*get_rx_hash_key)(struct dp_soc *soc, 1961 struct cdp_lro_hash_config *lro_hash); 1962 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 1963 enum peer_stats_type stats_type); 1964 /* Dp peer reorder queue setup */ 1965 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 1966 struct dp_peer *peer, 1967 int tid, 1968 uint32_t ba_window_size); 1969 struct dp_peer *(*dp_find_peer_by_destmac)(struct dp_soc *soc, 1970 uint8_t *dest_mac_addr, 1971 uint8_t vdev_id); 1972 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 1973 1974 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 1975 struct dp_vdev *vdev); 1976 1977 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 1978 1979 QDF_STATUS 1980 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 1981 struct dp_vdev *vdev, 1982 struct hal_tx_completion_status *ts, 1983 uint32_t *delay_us); 1984 void (*print_mlo_ast_stats)(struct dp_soc *soc); 1985 void (*dp_partner_chips_map)(struct dp_soc *soc, 1986 struct dp_peer *peer, 1987 uint16_t peer_id); 1988 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 1989 uint16_t peer_id); 1990 1991 #ifdef IPA_OFFLOAD 1992 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 1993 #endif 1994 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 1995 }; 1996 1997 /** 1998 * struct dp_soc_features: Data structure holding the SOC level feature flags. 1999 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2000 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2001 * buffer source rings 2002 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2003 * @umac_hw_reset_support: UMAC HW reset support 2004 */ 2005 struct dp_soc_features { 2006 uint8_t pn_in_reo_dest:1, 2007 dmac_cmn_src_rxbuf_ring_enabled:1; 2008 bool rssi_dbm_conv_support; 2009 bool umac_hw_reset_support; 2010 }; 2011 2012 enum sysfs_printing_mode { 2013 PRINTING_MODE_DISABLED = 0, 2014 PRINTING_MODE_ENABLED 2015 }; 2016 2017 /** 2018 * @typedef tx_pause_callback 2019 * @brief OSIF function registered with the data path 2020 */ 2021 2022 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2023 2024 #ifdef WLAN_SYSFS_DP_STATS 2025 /** 2026 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2027 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2028 * @sysfs_read_lock: Lock held while another stat req is being executed. 2029 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2030 * and *buf. 2031 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2032 * @stat_type_requested: stat type requested. 2033 * @mac_id: mac id for which stat type are requested. 2034 * @printing_mode: Should a print go through. 2035 * @process_id: Process allowed to write to buffer. 2036 * @curr_buffer_length: Curr length of buffer written 2037 * @max_buffer_length: Max buffer length. 2038 * @buf: Sysfs buffer. 2039 */ 2040 struct sysfs_stats_config { 2041 /* lock held to read stats */ 2042 qdf_spinlock_t rw_stats_lock; 2043 qdf_mutex_t sysfs_read_lock; 2044 qdf_spinlock_t sysfs_write_user_buffer; 2045 qdf_event_t sysfs_txrx_fw_request_done; 2046 uint32_t stat_type_requested; 2047 uint32_t mac_id; 2048 enum sysfs_printing_mode printing_mode; 2049 int process_id; 2050 uint16_t curr_buffer_length; 2051 uint16_t max_buffer_length; 2052 char *buf; 2053 }; 2054 #endif 2055 2056 /* SOC level structure for data path */ 2057 struct dp_soc { 2058 /** 2059 * re-use memory section starts 2060 */ 2061 2062 /* Common base structure - Should be the first member */ 2063 struct cdp_soc_t cdp_soc; 2064 2065 /* SoC Obj */ 2066 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2067 2068 /* OS device abstraction */ 2069 qdf_device_t osdev; 2070 2071 /*cce disable*/ 2072 bool cce_disable; 2073 2074 /* WLAN config context */ 2075 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2076 2077 /* HTT handle for host-fw interaction */ 2078 struct htt_soc *htt_handle; 2079 2080 /* Commint init done */ 2081 qdf_atomic_t cmn_init_done; 2082 2083 /* Opaque hif handle */ 2084 struct hif_opaque_softc *hif_handle; 2085 2086 /* PDEVs on this SOC */ 2087 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2088 2089 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2090 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2091 2092 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2093 2094 /* RXDMA error destination ring */ 2095 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2096 2097 /* RXDMA monitor buffer replenish ring */ 2098 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2099 2100 /* RXDMA monitor destination ring */ 2101 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2102 2103 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2104 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2105 2106 /* Number of PDEVs */ 2107 uint8_t pdev_count; 2108 2109 /*ast override support in HW*/ 2110 bool ast_override_support; 2111 2112 /*number of hw dscp tid map*/ 2113 uint8_t num_hw_dscp_tid_map; 2114 2115 /* HAL SOC handle */ 2116 hal_soc_handle_t hal_soc; 2117 2118 /* rx monitor pkt tlv size */ 2119 uint16_t rx_mon_pkt_tlv_size; 2120 /* rx pkt tlv size */ 2121 uint16_t rx_pkt_tlv_size; 2122 2123 struct dp_arch_ops arch_ops; 2124 2125 /* Device ID coming from Bus sub-system */ 2126 uint32_t device_id; 2127 2128 /* Link descriptor pages */ 2129 struct qdf_mem_multi_page_t link_desc_pages; 2130 2131 /* total link descriptors for regular RX and TX */ 2132 uint32_t total_link_descs; 2133 2134 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2135 struct dp_srng wbm_idle_link_ring; 2136 2137 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2138 */ 2139 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2140 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2141 uint32_t num_scatter_bufs; 2142 2143 /* Tx SW descriptor pool */ 2144 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2145 2146 /* Tx MSDU Extension descriptor pool */ 2147 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2148 2149 /* Tx TSO descriptor pool */ 2150 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2151 2152 /* Tx TSO Num of segments pool */ 2153 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2154 2155 /* REO destination rings */ 2156 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2157 2158 /* REO exception ring - See if should combine this with reo_dest_ring */ 2159 struct dp_srng reo_exception_ring; 2160 2161 /* REO reinjection ring */ 2162 struct dp_srng reo_reinject_ring; 2163 2164 /* REO command ring */ 2165 struct dp_srng reo_cmd_ring; 2166 2167 /* REO command status ring */ 2168 struct dp_srng reo_status_ring; 2169 2170 /* WBM Rx release ring */ 2171 struct dp_srng rx_rel_ring; 2172 2173 /* TCL data ring */ 2174 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2175 2176 /* Number of Tx comp rings */ 2177 uint8_t num_tx_comp_rings; 2178 2179 /* Number of TCL data rings */ 2180 uint8_t num_tcl_data_rings; 2181 2182 /* TCL CMD_CREDIT ring */ 2183 bool init_tcl_cmd_cred_ring; 2184 2185 /* It is used as credit based ring on QCN9000 else command ring */ 2186 struct dp_srng tcl_cmd_credit_ring; 2187 2188 /* TCL command status ring */ 2189 struct dp_srng tcl_status_ring; 2190 2191 /* WBM Tx completion rings */ 2192 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2193 2194 /* Common WBM link descriptor release ring (SW to WBM) */ 2195 struct dp_srng wbm_desc_rel_ring; 2196 2197 /* DP Interrupts */ 2198 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2199 2200 /* Monitor mode mac id to dp_intr_id map */ 2201 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2202 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2203 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2204 2205 /* Rx SW descriptor pool for RXDMA status buffer */ 2206 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2207 2208 /* Rx SW descriptor pool for RXDMA buffer */ 2209 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2210 2211 /* Number of REO destination rings */ 2212 uint8_t num_reo_dest_rings; 2213 2214 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2215 /* lock to control access to soc TX descriptors */ 2216 qdf_spinlock_t flow_pool_array_lock; 2217 2218 /* pause callback to pause TX queues as per flow control */ 2219 tx_pause_callback pause_cb; 2220 2221 /* flow pool related statistics */ 2222 struct dp_txrx_pool_stats pool_stats; 2223 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2224 2225 notify_pre_reset_fw_callback notify_fw_callback; 2226 2227 unsigned long service_rings_running; 2228 2229 uint32_t wbm_idle_scatter_buf_size; 2230 2231 /* VDEVs on this SOC */ 2232 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2233 2234 /* Tx H/W queues lock */ 2235 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2236 2237 /* Tx ring map for interrupt processing */ 2238 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2239 2240 /* Rx ring map for interrupt processing */ 2241 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2242 2243 /* peer ID to peer object map (array of pointers to peer objects) */ 2244 struct dp_peer **peer_id_to_obj_map; 2245 2246 struct { 2247 unsigned mask; 2248 unsigned idx_bits; 2249 TAILQ_HEAD(, dp_peer) * bins; 2250 } peer_hash; 2251 2252 /* rx defrag state – TBD: do we need this per radio? */ 2253 struct { 2254 struct { 2255 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2256 uint32_t timeout_ms; 2257 uint32_t next_flush_ms; 2258 qdf_spinlock_t defrag_lock; 2259 } defrag; 2260 struct { 2261 int defrag_timeout_check; 2262 int dup_check; 2263 } flags; 2264 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2265 qdf_spinlock_t reo_cmd_lock; 2266 } rx; 2267 2268 /* optional rx processing function */ 2269 void (*rx_opt_proc)( 2270 struct dp_vdev *vdev, 2271 struct dp_peer *peer, 2272 unsigned tid, 2273 qdf_nbuf_t msdu_list); 2274 2275 /* pool addr for mcast enhance buff */ 2276 struct { 2277 int size; 2278 uint32_t paddr; 2279 uint32_t *vaddr; 2280 struct dp_tx_me_buf_t *freelist; 2281 int buf_in_use; 2282 qdf_dma_mem_context(memctx); 2283 } me_buf; 2284 2285 /* Protect peer hash table */ 2286 DP_MUTEX_TYPE peer_hash_lock; 2287 /* Protect peer_id_to_objmap */ 2288 DP_MUTEX_TYPE peer_map_lock; 2289 2290 /* maximum number of suppoerted peers */ 2291 uint32_t max_peers; 2292 /* maximum value for peer_id */ 2293 uint32_t max_peer_id; 2294 2295 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2296 uint32_t peer_id_shift; 2297 uint32_t peer_id_mask; 2298 #endif 2299 2300 /* SoC level data path statistics */ 2301 struct dp_soc_stats stats; 2302 #ifdef WLAN_SYSFS_DP_STATS 2303 /* sysfs config for DP stats */ 2304 struct sysfs_stats_config *sysfs_config; 2305 #endif 2306 /* timestamp to keep track of msdu buffers received on reo err ring */ 2307 uint64_t rx_route_err_start_pkt_ts; 2308 2309 /* Num RX Route err in a given window to keep track of rate of errors */ 2310 uint32_t rx_route_err_in_window; 2311 2312 /* Enable processing of Tx completion status words */ 2313 bool process_tx_status; 2314 bool process_rx_status; 2315 struct dp_ast_entry **ast_table; 2316 struct { 2317 unsigned mask; 2318 unsigned idx_bits; 2319 TAILQ_HEAD(, dp_ast_entry) * bins; 2320 } ast_hash; 2321 2322 #ifdef DP_TX_HW_DESC_HISTORY 2323 struct dp_tx_hw_desc_history tx_hw_desc_history; 2324 #endif 2325 2326 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2327 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2328 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2329 struct dp_rx_err_history *rx_err_ring_history; 2330 struct dp_rx_reinject_history *rx_reinject_ring_history; 2331 #endif 2332 2333 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2334 struct dp_mon_status_ring_history *mon_status_ring_history; 2335 #endif 2336 2337 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2338 struct dp_tx_tcl_history tx_tcl_history; 2339 struct dp_tx_comp_history tx_comp_history; 2340 #endif 2341 2342 qdf_spinlock_t ast_lock; 2343 /*Timer for AST entry ageout maintenance */ 2344 qdf_timer_t ast_aging_timer; 2345 2346 /*Timer counter for WDS AST entry ageout*/ 2347 uint8_t wds_ast_aging_timer_cnt; 2348 bool pending_ageout; 2349 bool ast_offload_support; 2350 bool host_ast_db_enable; 2351 uint32_t max_ast_ageout_count; 2352 uint8_t eapol_over_control_port; 2353 2354 uint8_t sta_mode_search_policy; 2355 qdf_timer_t lmac_reap_timer; 2356 uint8_t lmac_timer_init; 2357 qdf_timer_t int_timer; 2358 uint8_t intr_mode; 2359 uint8_t lmac_polled_mode; 2360 2361 qdf_list_t reo_desc_freelist; 2362 qdf_spinlock_t reo_desc_freelist_lock; 2363 2364 /* htt stats */ 2365 struct htt_t2h_stats htt_stats; 2366 2367 void *external_txrx_handle; /* External data path handle */ 2368 #ifdef IPA_OFFLOAD 2369 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 2370 #ifdef IPA_WDI3_TX_TWO_PIPES 2371 /* Resources for the alternative IPA TX pipe */ 2372 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 2373 #endif 2374 2375 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 2376 #ifdef IPA_WDI3_VLAN_SUPPORT 2377 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 2378 #endif 2379 qdf_atomic_t ipa_pipes_enabled; 2380 bool ipa_first_tx_db_access; 2381 qdf_spinlock_t ipa_rx_buf_map_lock; 2382 bool ipa_rx_buf_map_lock_initialized; 2383 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 2384 #endif 2385 2386 #ifdef WLAN_FEATURE_STATS_EXT 2387 struct { 2388 uint32_t rx_mpdu_received; 2389 uint32_t rx_mpdu_missed; 2390 } ext_stats; 2391 qdf_event_t rx_hw_stats_event; 2392 qdf_spinlock_t rx_hw_stats_lock; 2393 bool is_last_stats_ctx_init; 2394 #endif /* WLAN_FEATURE_STATS_EXT */ 2395 2396 /* Indicates HTT map/unmap versions*/ 2397 uint8_t peer_map_unmap_versions; 2398 /* Per peer per Tid ba window size support */ 2399 uint8_t per_tid_basize_max_tid; 2400 /* Soc level flag to enable da_war */ 2401 uint8_t da_war_enabled; 2402 /* number of active ast entries */ 2403 uint32_t num_ast_entries; 2404 /* peer extended rate statistics context at soc level*/ 2405 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 2406 /* peer extended rate statistics control flag */ 2407 bool peerstats_enabled; 2408 2409 /* 8021p PCP-TID map values */ 2410 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 2411 /* TID map priority value */ 2412 uint8_t tidmap_prty; 2413 /* Pointer to global per ring type specific configuration table */ 2414 struct wlan_srng_cfg *wlan_srng_cfg; 2415 /* Num Tx outstanding on device */ 2416 qdf_atomic_t num_tx_outstanding; 2417 /* Num Tx exception on device */ 2418 qdf_atomic_t num_tx_exception; 2419 /* Num Tx allowed */ 2420 uint32_t num_tx_allowed; 2421 /* Preferred HW mode */ 2422 uint8_t preferred_hw_mode; 2423 2424 /** 2425 * Flag to indicate whether WAR to address single cache entry 2426 * invalidation bug is enabled or not 2427 */ 2428 bool is_rx_fse_full_cache_invalidate_war_enabled; 2429 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 2430 /** 2431 * Pointer to DP RX Flow FST at SOC level if 2432 * is_rx_flow_search_table_per_pdev is false 2433 * TBD: rx_fst[num_macs] if we decide to have per mac FST 2434 */ 2435 struct dp_rx_fst *rx_fst; 2436 #ifdef WLAN_SUPPORT_RX_FISA 2437 uint8_t fisa_enable; 2438 uint8_t fisa_lru_del_enable; 2439 /** 2440 * Params used for controlling the fisa aggregation dynamically 2441 */ 2442 struct { 2443 qdf_atomic_t skip_fisa; 2444 uint8_t fisa_force_flush[MAX_REO_DEST_RINGS]; 2445 } skip_fisa_param; 2446 2447 /** 2448 * CMEM address and size for FST in CMEM, This is the address 2449 * shared during init time. 2450 */ 2451 uint64_t fst_cmem_base; 2452 uint64_t fst_cmem_size; 2453 #endif 2454 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 2455 /* SG supported for msdu continued packets from wbm release ring */ 2456 bool wbm_release_desc_rx_sg_support; 2457 bool peer_map_attach_success; 2458 /* Flag to disable mac1 ring interrupts */ 2459 bool disable_mac1_intr; 2460 /* Flag to disable mac2 ring interrupts */ 2461 bool disable_mac2_intr; 2462 2463 struct { 2464 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 2465 bool wbm_is_first_msdu_in_sg; 2466 /* Wbm sg list head */ 2467 qdf_nbuf_t wbm_sg_nbuf_head; 2468 /* Wbm sg list tail */ 2469 qdf_nbuf_t wbm_sg_nbuf_tail; 2470 uint32_t wbm_sg_desc_msdu_len; 2471 } wbm_sg_param; 2472 /* Number of msdu exception descriptors */ 2473 uint32_t num_msdu_exception_desc; 2474 2475 /* RX buffer params */ 2476 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 2477 struct rx_refill_buff_pool rx_refill_buff_pool; 2478 /* Save recent operation related variable */ 2479 struct dp_last_op_info last_op_info; 2480 TAILQ_HEAD(, dp_peer) inactive_peer_list; 2481 qdf_spinlock_t inactive_peer_list_lock; 2482 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 2483 qdf_spinlock_t inactive_vdev_list_lock; 2484 /* lock to protect vdev_id_map table*/ 2485 qdf_spinlock_t vdev_map_lock; 2486 2487 /* Flow Search Table is in CMEM */ 2488 bool fst_in_cmem; 2489 2490 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 2491 struct dp_swlm swlm; 2492 #endif 2493 2494 #ifdef FEATURE_RUNTIME_PM 2495 /* DP Rx timestamp */ 2496 qdf_time_t rx_last_busy; 2497 /* Dp runtime refcount */ 2498 qdf_atomic_t dp_runtime_refcount; 2499 /* Dp tx pending count in RTPM */ 2500 qdf_atomic_t tx_pending_rtpm; 2501 #endif 2502 /* Invalid buffer that allocated for RX buffer */ 2503 qdf_nbuf_queue_t invalid_buf_queue; 2504 2505 #ifdef FEATURE_MEC 2506 /** @mec_lock: spinlock for MEC table */ 2507 qdf_spinlock_t mec_lock; 2508 /** @mec_cnt: number of active mec entries */ 2509 qdf_atomic_t mec_cnt; 2510 struct { 2511 /** @mask: mask bits */ 2512 uint32_t mask; 2513 /** @idx_bits: index to shift bits */ 2514 uint32_t idx_bits; 2515 /** @bins: MEC table */ 2516 TAILQ_HEAD(, dp_mec_entry) * bins; 2517 } mec_hash; 2518 #endif 2519 2520 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 2521 qdf_list_t reo_desc_deferred_freelist; 2522 qdf_spinlock_t reo_desc_deferred_freelist_lock; 2523 bool reo_desc_deferred_freelist_init; 2524 #endif 2525 /* BM id for first WBM2SW ring */ 2526 uint32_t wbm_sw0_bm_id; 2527 2528 /* Store arch_id from device_id */ 2529 uint16_t arch_id; 2530 2531 /* link desc ID start per device type */ 2532 uint32_t link_desc_id_start; 2533 2534 /* CMEM buffer target reserved for host usage */ 2535 uint64_t cmem_base; 2536 /* CMEM size in bytes */ 2537 uint64_t cmem_total_size; 2538 /* CMEM free size in bytes */ 2539 uint64_t cmem_avail_size; 2540 2541 /* SOC level feature flags */ 2542 struct dp_soc_features features; 2543 2544 #ifdef WIFI_MONITOR_SUPPORT 2545 struct dp_mon_soc *monitor_soc; 2546 #endif 2547 uint8_t rxdma2sw_rings_not_supported:1, 2548 wbm_sg_last_msdu_war:1, 2549 mec_fw_offload:1, 2550 multi_peer_grp_cmd_supported:1; 2551 2552 /* Number of Rx refill rings */ 2553 uint8_t num_rx_refill_buf_rings; 2554 #ifdef FEATURE_RUNTIME_PM 2555 /* flag to indicate vote for runtime_pm for high tput castt*/ 2556 qdf_atomic_t rtpm_high_tput_flag; 2557 #endif 2558 /* Buffer manager ID for idle link descs */ 2559 uint8_t idle_link_bm_id; 2560 qdf_atomic_t ref_count; 2561 2562 unsigned long vdev_stats_id_map; 2563 bool txmon_hw_support; 2564 2565 #ifdef DP_UMAC_HW_RESET_SUPPORT 2566 struct dp_soc_umac_reset_ctx umac_reset_ctx; 2567 #endif 2568 /* PPDU to link_id mapping parameters */ 2569 uint8_t link_id_offset; 2570 uint8_t link_id_bits; 2571 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 2572 /* A flag using to decide the switch of rx link speed */ 2573 bool high_throughput; 2574 #endif 2575 bool is_tx_pause; 2576 }; 2577 2578 #ifdef IPA_OFFLOAD 2579 /** 2580 * dp_ipa_resources - Resources needed for IPA 2581 */ 2582 struct dp_ipa_resources { 2583 qdf_shared_mem_t tx_ring; 2584 uint32_t tx_num_alloc_buffer; 2585 2586 qdf_shared_mem_t tx_comp_ring; 2587 qdf_shared_mem_t rx_rdy_ring; 2588 qdf_shared_mem_t rx_refill_ring; 2589 2590 /* IPA UC doorbell registers paddr */ 2591 qdf_dma_addr_t tx_comp_doorbell_paddr; 2592 uint32_t *tx_comp_doorbell_vaddr; 2593 qdf_dma_addr_t rx_ready_doorbell_paddr; 2594 2595 bool is_db_ddr_mapped; 2596 2597 #ifdef IPA_WDI3_TX_TWO_PIPES 2598 qdf_shared_mem_t tx_alt_ring; 2599 uint32_t tx_alt_ring_num_alloc_buffer; 2600 qdf_shared_mem_t tx_alt_comp_ring; 2601 2602 /* IPA UC doorbell registers paddr */ 2603 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 2604 uint32_t *tx_alt_comp_doorbell_vaddr; 2605 #endif 2606 #ifdef IPA_WDI3_VLAN_SUPPORT 2607 qdf_shared_mem_t rx_alt_rdy_ring; 2608 qdf_shared_mem_t rx_alt_refill_ring; 2609 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 2610 #endif 2611 }; 2612 #endif 2613 2614 #define MAX_RX_MAC_RINGS 2 2615 /* Same as NAC_MAX_CLENT */ 2616 #define DP_NAC_MAX_CLIENT 24 2617 2618 /* 2619 * 24 bits cookie size 2620 * 10 bits page id 0 ~ 1023 for MCL 2621 * 3 bits page id 0 ~ 7 for WIN 2622 * WBM Idle List Desc size = 128, 2623 * Num descs per page = 4096/128 = 32 for MCL 2624 * Num descs per page = 2MB/128 = 16384 for WIN 2625 */ 2626 /* 2627 * Macros to setup link descriptor cookies - for link descriptors, we just 2628 * need first 3 bits to store bank/page ID for WIN. The 2629 * remaining bytes will be used to set a unique ID, which will 2630 * be useful in debugging 2631 */ 2632 #ifdef MAX_ALLOC_PAGE_SIZE 2633 #if PAGE_SIZE == 4096 2634 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 2635 #define LINK_DESC_ID_SHIFT 5 2636 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 2637 #elif PAGE_SIZE == 65536 2638 #define LINK_DESC_PAGE_ID_MASK 0x007E00 2639 #define LINK_DESC_ID_SHIFT 9 2640 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 2641 #else 2642 #error "Unsupported kernel PAGE_SIZE" 2643 #endif 2644 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 2645 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 2646 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 2647 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 2648 #else 2649 #define LINK_DESC_PAGE_ID_MASK 0x7 2650 #define LINK_DESC_ID_SHIFT 3 2651 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 2652 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 2653 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 2654 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 2655 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 2656 #endif 2657 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 2658 2659 /* same as ieee80211_nac_param */ 2660 enum dp_nac_param_cmd { 2661 /* IEEE80211_NAC_PARAM_ADD */ 2662 DP_NAC_PARAM_ADD = 1, 2663 /* IEEE80211_NAC_PARAM_DEL */ 2664 DP_NAC_PARAM_DEL, 2665 /* IEEE80211_NAC_PARAM_LIST */ 2666 DP_NAC_PARAM_LIST, 2667 }; 2668 2669 /** 2670 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 2671 * @neighbour_peers_macaddr: neighbour peer's mac address 2672 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 2673 * @ast_entry: ast_entry for neighbour peer 2674 * @rssi: rssi value 2675 */ 2676 struct dp_neighbour_peer { 2677 /* MAC address of neighbour's peer */ 2678 union dp_align_mac_addr neighbour_peers_macaddr; 2679 struct dp_vdev *vdev; 2680 struct dp_ast_entry *ast_entry; 2681 uint8_t rssi; 2682 /* node in the list of neighbour's peer */ 2683 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 2684 }; 2685 2686 #ifdef WLAN_TX_PKT_CAPTURE_ENH 2687 #define WLAN_TX_PKT_CAPTURE_ENH 1 2688 #define DP_TX_PPDU_PROC_THRESHOLD 8 2689 #define DP_TX_PPDU_PROC_TIMEOUT 10 2690 #endif 2691 2692 /** 2693 * struct ppdu_info - PPDU Status info descriptor 2694 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 2695 * @sched_cmdid: schedule command id, which will be same in a burst 2696 * @max_ppdu_id: wrap around for ppdu id 2697 * @last_tlv_cnt: Keep track for missing ppdu tlvs 2698 * @last_user: last ppdu processed for user 2699 * @is_ampdu: set if Ampdu aggregate 2700 * @nbuf: ppdu descriptor payload 2701 * @ppdu_desc: ppdu descriptor 2702 * @ppdu_info_list_elem: linked list of ppdu tlvs 2703 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 2704 * @mpdu_compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 2705 * @mpdu_ack_ba_tlv: Successful tlv counter from ACK BA tlv 2706 */ 2707 struct ppdu_info { 2708 uint32_t ppdu_id; 2709 uint32_t sched_cmdid; 2710 uint32_t max_ppdu_id; 2711 uint32_t tsf_l32; 2712 uint16_t tlv_bitmap; 2713 uint16_t last_tlv_cnt; 2714 uint16_t last_user:8, 2715 is_ampdu:1; 2716 qdf_nbuf_t nbuf; 2717 struct cdp_tx_completion_ppdu *ppdu_desc; 2718 #ifdef WLAN_TX_PKT_CAPTURE_ENH 2719 union { 2720 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 2721 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 2722 } ulist; 2723 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 2724 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 2725 #else 2726 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 2727 #endif 2728 uint8_t compltn_common_tlv; 2729 uint8_t ack_ba_tlv; 2730 bool done; 2731 }; 2732 2733 /** 2734 * struct msdu_completion_info - wbm msdu completion info 2735 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 2736 * @peer_id - peer_id 2737 * @tid - tid which used during transmit 2738 * @first_msdu - first msdu indication 2739 * @last_msdu - last msdu indication 2740 * @msdu_part_of_amsdu - msdu part of amsdu 2741 * @transmit_cnt - retried count 2742 * @status - transmit status 2743 * @tsf - timestamp which it transmitted 2744 */ 2745 struct msdu_completion_info { 2746 uint32_t ppdu_id; 2747 uint16_t peer_id; 2748 uint8_t tid; 2749 uint8_t first_msdu:1, 2750 last_msdu:1, 2751 msdu_part_of_amsdu:1; 2752 uint8_t transmit_cnt; 2753 uint8_t status; 2754 uint32_t tsf; 2755 }; 2756 2757 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 2758 struct rx_protocol_tag_map { 2759 /* This is the user configured tag for the said protocol type */ 2760 uint16_t tag; 2761 }; 2762 2763 /** 2764 * rx_protocol_tag_stats - protocol statistics 2765 * @tag_ctr: number of rx msdus matching this tag 2766 * @mon_tag_ctr: number of msdus matching this tag in mon path 2767 */ 2768 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 2769 struct rx_protocol_tag_stats { 2770 uint32_t tag_ctr; 2771 }; 2772 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 2773 2774 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 2775 2776 #ifdef WLAN_RX_PKT_CAPTURE_ENH 2777 /* Template data to be set for Enhanced RX Monitor packets */ 2778 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 2779 2780 /** 2781 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 2782 * at end of each MSDU in monitor-lite mode 2783 * @reserved1: reserved for future use 2784 * @reserved2: reserved for future use 2785 * @flow_tag: flow tag value read from skb->cb 2786 * @protocol_tag: protocol tag value read from skb->cb 2787 */ 2788 struct dp_rx_mon_enh_trailer_data { 2789 uint16_t reserved1; 2790 uint16_t reserved2; 2791 uint16_t flow_tag; 2792 uint16_t protocol_tag; 2793 }; 2794 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 2795 2796 #ifdef HTT_STATS_DEBUGFS_SUPPORT 2797 /* Number of debugfs entries created for HTT stats */ 2798 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 2799 2800 /* struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 2801 * of HTT stats 2802 * @pdev: dp pdev of debugfs entry 2803 * @stats_id: stats id of debugfs entry 2804 */ 2805 struct pdev_htt_stats_dbgfs_priv { 2806 struct dp_pdev *pdev; 2807 uint16_t stats_id; 2808 }; 2809 2810 /* struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 2811 * support for HTT stats 2812 * @debugfs_entry: qdf_debugfs directory entry 2813 * @m: qdf debugfs file handler 2814 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 2815 * @priv: HTT stats debugfs private object 2816 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 2817 * @lock: HTT stats debugfs lock 2818 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 2819 */ 2820 struct pdev_htt_stats_dbgfs_cfg { 2821 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 2822 qdf_debugfs_file_t m; 2823 struct qdf_debugfs_fops 2824 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 2825 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 2826 qdf_event_t htt_stats_dbgfs_event; 2827 qdf_mutex_t lock; 2828 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 2829 }; 2830 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 2831 2832 struct dp_srng_ring_state { 2833 enum hal_ring_type ring_type; 2834 uint32_t sw_head; 2835 uint32_t sw_tail; 2836 uint32_t hw_head; 2837 uint32_t hw_tail; 2838 2839 }; 2840 2841 struct dp_soc_srngs_state { 2842 uint32_t seq_num; 2843 uint32_t max_ring_id; 2844 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 2845 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 2846 }; 2847 2848 #ifdef WLAN_FEATURE_11BE_MLO 2849 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 2850 * MLO timestamp received via HTT msg. 2851 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 2852 * pdev_id: pdev_id 2853 * chip_id: chip_id 2854 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 2855 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 2856 * which last sync interrupt was received 2857 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 2858 * which last sync interrupt was received 2859 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 2860 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 2861 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 2862 * mlo_comp_us: MLO time stamp compensation applied in us 2863 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 2864 * for sub us resolution 2865 * mlo_comp_timer: period of MLO compensation timer at which compensation 2866 * is applied, in us 2867 */ 2868 struct dp_mlo_sync_timestamp { 2869 uint32_t msg_type:8, 2870 pdev_id:2, 2871 chip_id:2, 2872 rsvd1:4, 2873 mac_clk_freq:16; 2874 uint32_t sync_tstmp_lo_us; 2875 uint32_t sync_tstmp_hi_us; 2876 uint32_t mlo_offset_lo_us; 2877 uint32_t mlo_offset_hi_us; 2878 uint32_t mlo_offset_clks; 2879 uint32_t mlo_comp_us:16, 2880 mlo_comp_clks:10, 2881 rsvd2:6; 2882 uint32_t mlo_comp_timer:22, 2883 rsvd3:10; 2884 }; 2885 #endif 2886 2887 /* PDEV level structure for data path */ 2888 struct dp_pdev { 2889 /** 2890 * Re-use Memory Section Starts 2891 */ 2892 2893 /* PDEV Id */ 2894 uint8_t pdev_id; 2895 2896 /* LMAC Id */ 2897 uint8_t lmac_id; 2898 2899 /* Target pdev Id */ 2900 uint8_t target_pdev_id; 2901 2902 bool pdev_deinit; 2903 2904 /* TXRX SOC handle */ 2905 struct dp_soc *soc; 2906 2907 /* pdev status down or up required to handle dynamic hw 2908 * mode switch between DBS and DBS_SBS. 2909 * 1 = down 2910 * 0 = up 2911 */ 2912 bool is_pdev_down; 2913 2914 /* Enhanced Stats is enabled */ 2915 bool enhanced_stats_en; 2916 2917 /* Flag to indicate fast RX */ 2918 bool rx_fast_flag; 2919 2920 /* Second ring used to replenish rx buffers */ 2921 struct dp_srng rx_refill_buf_ring2; 2922 #ifdef IPA_WDI3_VLAN_SUPPORT 2923 /* Third ring used to replenish rx buffers */ 2924 struct dp_srng rx_refill_buf_ring3; 2925 #endif 2926 2927 /* Empty ring used by firmware to post rx buffers to the MAC */ 2928 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 2929 2930 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 2931 2932 /* wlan_cfg pdev ctxt*/ 2933 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 2934 2935 /** 2936 * TODO: See if we need a ring map here for LMAC rings. 2937 * 1. Monitor rings are currently planning to be processed on receiving 2938 * PPDU end interrupts and hence won't need ring based interrupts. 2939 * 2. Rx buffer rings will be replenished during REO destination 2940 * processing and doesn't require regular interrupt handling - we will 2941 * only handle low water mark interrupts which is not expected 2942 * frequently 2943 */ 2944 2945 /* VDEV list */ 2946 TAILQ_HEAD(, dp_vdev) vdev_list; 2947 2948 /* vdev list lock */ 2949 qdf_spinlock_t vdev_list_lock; 2950 2951 /* Number of vdevs this device have */ 2952 uint16_t vdev_count; 2953 2954 /* PDEV transmit lock */ 2955 qdf_spinlock_t tx_lock; 2956 2957 /*tx_mutex for me*/ 2958 DP_MUTEX_TYPE tx_mutex; 2959 2960 /* msdu chain head & tail */ 2961 qdf_nbuf_t invalid_peer_head_msdu; 2962 qdf_nbuf_t invalid_peer_tail_msdu; 2963 2964 /* Band steering */ 2965 /* TBD */ 2966 2967 /* PDEV level data path statistics */ 2968 struct cdp_pdev_stats stats; 2969 2970 /* Global RX decap mode for the device */ 2971 enum htt_pkt_type rx_decap_mode; 2972 2973 qdf_atomic_t num_tx_outstanding; 2974 int32_t tx_descs_max; 2975 2976 qdf_atomic_t num_tx_exception; 2977 2978 /* MCL specific local peer handle */ 2979 struct { 2980 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 2981 uint8_t freelist; 2982 qdf_spinlock_t lock; 2983 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 2984 } local_peer_ids; 2985 2986 /* dscp_tid_map_*/ 2987 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 2988 2989 /* operating channel */ 2990 struct { 2991 uint8_t num; 2992 uint8_t band; 2993 uint16_t freq; 2994 } operating_channel; 2995 2996 /* pool addr for mcast enhance buff */ 2997 struct { 2998 int size; 2999 uint32_t paddr; 3000 char *vaddr; 3001 struct dp_tx_me_buf_t *freelist; 3002 int buf_in_use; 3003 qdf_dma_mem_context(memctx); 3004 } me_buf; 3005 3006 bool hmmc_tid_override_en; 3007 uint8_t hmmc_tid; 3008 3009 /* Number of VAPs with mcast enhancement enabled */ 3010 qdf_atomic_t mc_num_vap_attached; 3011 3012 qdf_atomic_t stats_cmd_complete; 3013 3014 #ifdef IPA_OFFLOAD 3015 ipa_uc_op_cb_type ipa_uc_op_cb; 3016 void *usr_ctxt; 3017 struct dp_ipa_resources ipa_resource; 3018 #endif 3019 3020 /* TBD */ 3021 3022 /* map this pdev to a particular Reo Destination ring */ 3023 enum cdp_host_reo_dest_ring reo_dest; 3024 3025 /* WDI event handlers */ 3026 struct wdi_event_subscribe_t **wdi_event_list; 3027 3028 bool cfr_rcc_mode; 3029 3030 /* enable time latency check for tx completion */ 3031 bool latency_capture_enable; 3032 3033 /* enable calculation of delay stats*/ 3034 bool delay_stats_flag; 3035 void *dp_txrx_handle; /* Advanced data path handle */ 3036 uint32_t ppdu_id; 3037 bool first_nbuf; 3038 /* Current noise-floor reading for the pdev channel */ 3039 int16_t chan_noise_floor; 3040 3041 /* 3042 * For multiradio device, this flag indicates if 3043 * this radio is primary or secondary. 3044 * 3045 * For HK 1.0, this is used for WAR for the AST issue. 3046 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3047 * across 2 radios. is_primary indicates the radio on which DP should 3048 * install HW AST entry if there is a request to add 2 AST entries 3049 * with same MAC address across 2 radios 3050 */ 3051 uint8_t is_primary; 3052 struct cdp_tx_sojourn_stats sojourn_stats; 3053 qdf_nbuf_t sojourn_buf; 3054 3055 union dp_rx_desc_list_elem_t *free_list_head; 3056 union dp_rx_desc_list_elem_t *free_list_tail; 3057 /* Cached peer_id from htt_peer_details_tlv */ 3058 uint16_t fw_stats_peer_id; 3059 3060 /* qdf_event for fw_peer_stats */ 3061 qdf_event_t fw_peer_stats_event; 3062 3063 /* qdf_event for fw_stats */ 3064 qdf_event_t fw_stats_event; 3065 3066 /* qdf_event for fw__obss_stats */ 3067 qdf_event_t fw_obss_stats_event; 3068 3069 /* To check if request is already sent for obss stats */ 3070 bool pending_fw_obss_stats_response; 3071 3072 /* User configured max number of tx buffers */ 3073 uint32_t num_tx_allowed; 3074 3075 /* unique cookie required for peer session */ 3076 uint32_t next_peer_cookie; 3077 3078 /* 3079 * Run time enabled when the first protocol tag is added, 3080 * run time disabled when the last protocol tag is deleted 3081 */ 3082 bool is_rx_protocol_tagging_enabled; 3083 3084 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3085 /* 3086 * The protocol type is used as array index to save 3087 * user provided tag info 3088 */ 3089 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3090 3091 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3092 /* 3093 * Track msdus received from each reo ring separately to avoid 3094 * simultaneous writes from different core 3095 */ 3096 struct rx_protocol_tag_stats 3097 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3098 /* Track msdus received from exception ring separately */ 3099 struct rx_protocol_tag_stats 3100 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3101 struct rx_protocol_tag_stats 3102 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3103 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3104 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3105 3106 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3107 /** 3108 * Pointer to DP Flow FST at SOC level if 3109 * is_rx_flow_search_table_per_pdev is true 3110 */ 3111 struct dp_rx_fst *rx_fst; 3112 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3113 3114 #ifdef FEATURE_TSO_STATS 3115 /* TSO Id to index into TSO packet information */ 3116 qdf_atomic_t tso_idx; 3117 #endif /* FEATURE_TSO_STATS */ 3118 3119 #ifdef WLAN_SUPPORT_DATA_STALL 3120 data_stall_detect_cb data_stall_detect_callback; 3121 #endif /* WLAN_SUPPORT_DATA_STALL */ 3122 3123 /* flag to indicate whether LRO hash command has been sent to FW */ 3124 uint8_t is_lro_hash_configured; 3125 3126 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3127 /* HTT stats debugfs params */ 3128 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3129 #endif 3130 struct { 3131 qdf_work_t work; 3132 qdf_workqueue_t *work_queue; 3133 uint32_t seq_num; 3134 uint8_t queue_depth; 3135 qdf_spinlock_t list_lock; 3136 3137 TAILQ_HEAD(, dp_soc_srngs_state) list; 3138 } bkp_stats; 3139 #ifdef WIFI_MONITOR_SUPPORT 3140 struct dp_mon_pdev *monitor_pdev; 3141 #endif 3142 #ifdef WLAN_FEATURE_11BE_MLO 3143 struct dp_mlo_sync_timestamp timestamp; 3144 #endif 3145 /* Is isolation mode enabled */ 3146 bool isolation; 3147 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3148 uint8_t is_first_wakeup_packet; 3149 #endif 3150 #ifdef CONNECTIVITY_PKTLOG 3151 /* packetdump callback functions */ 3152 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3153 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3154 #endif 3155 3156 /* Firmware Stats for TLV received from Firmware */ 3157 uint64_t fw_stats_tlv_bitmap_rcvd; 3158 3159 /* For Checking Pending Firmware Response */ 3160 bool pending_fw_stats_response; 3161 }; 3162 3163 struct dp_peer; 3164 3165 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3166 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3167 /** 3168 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3169 * in connection mgr 3170 */ 3171 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3172 #endif 3173 3174 /* VDEV structure for data path state */ 3175 struct dp_vdev { 3176 /* OS device abstraction */ 3177 qdf_device_t osdev; 3178 3179 /* physical device that is the parent of this virtual device */ 3180 struct dp_pdev *pdev; 3181 3182 /* VDEV operating mode */ 3183 enum wlan_op_mode opmode; 3184 3185 /* VDEV subtype */ 3186 enum wlan_op_subtype subtype; 3187 3188 /* Tx encapsulation type for this VAP */ 3189 enum htt_cmn_pkt_type tx_encap_type; 3190 3191 /* Rx Decapsulation type for this VAP */ 3192 enum htt_cmn_pkt_type rx_decap_type; 3193 3194 /* WDS enabled */ 3195 bool wds_enabled; 3196 3197 /* MEC enabled */ 3198 bool mec_enabled; 3199 3200 #ifdef QCA_SUPPORT_WDS_EXTENDED 3201 bool wds_ext_enabled; 3202 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3203 bool drop_3addr_mcast; 3204 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3205 bool skip_bar_update; 3206 unsigned long skip_bar_update_last_ts; 3207 #endif 3208 /* WDS Aging timer period */ 3209 uint32_t wds_aging_timer_val; 3210 3211 /* NAWDS enabled */ 3212 bool nawds_enabled; 3213 3214 /* Multicast enhancement enabled */ 3215 uint8_t mcast_enhancement_en; 3216 3217 /* IGMP multicast enhancement enabled */ 3218 uint8_t igmp_mcast_enhanc_en; 3219 3220 /* vdev_id - ID used to specify a particular vdev to the target */ 3221 uint8_t vdev_id; 3222 3223 /* Default HTT meta data for this VDEV */ 3224 /* TBD: check alignment constraints */ 3225 uint16_t htt_tcl_metadata; 3226 3227 /* vdev lmac_id */ 3228 uint8_t lmac_id; 3229 3230 /* vdev bank_id */ 3231 uint8_t bank_id; 3232 3233 /* Mesh mode vdev */ 3234 uint32_t mesh_vdev; 3235 3236 /* Mesh mode rx filter setting */ 3237 uint32_t mesh_rx_filter; 3238 3239 /* DSCP-TID mapping table ID */ 3240 uint8_t dscp_tid_map_id; 3241 3242 /* Address search type to be set in TX descriptor */ 3243 uint8_t search_type; 3244 3245 /* 3246 * Flag to indicate if s/w tid classification should be 3247 * skipped 3248 */ 3249 uint8_t skip_sw_tid_classification; 3250 3251 /* Flag to enable peer authorization */ 3252 uint8_t peer_authorize; 3253 3254 /* AST hash value for BSS peer in HW valid for STA VAP*/ 3255 uint16_t bss_ast_hash; 3256 3257 /* AST hash index for BSS peer in HW valid for STA VAP*/ 3258 uint16_t bss_ast_idx; 3259 3260 bool multipass_en; 3261 3262 /* Address search flags to be configured in HAL descriptor */ 3263 uint8_t hal_desc_addr_search_flags; 3264 3265 /* Handle to the OS shim SW's virtual device */ 3266 ol_osif_vdev_handle osif_vdev; 3267 3268 /* MAC address */ 3269 union dp_align_mac_addr mac_addr; 3270 3271 #ifdef WLAN_FEATURE_11BE_MLO 3272 /* MLO MAC address corresponding to vdev */ 3273 union dp_align_mac_addr mld_mac_addr; 3274 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 3275 bool mlo_vdev; 3276 #endif 3277 #endif 3278 3279 /* node in the pdev's list of vdevs */ 3280 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 3281 3282 /* dp_peer list */ 3283 TAILQ_HEAD(, dp_peer) peer_list; 3284 /* to protect peer_list */ 3285 DP_MUTEX_TYPE peer_list_lock; 3286 3287 /* RX call back function to flush GRO packets*/ 3288 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 3289 /* default RX call back function called by dp */ 3290 ol_txrx_rx_fp osif_rx; 3291 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 3292 /* callback to receive eapol frames */ 3293 ol_txrx_rx_fp osif_rx_eapol; 3294 #endif 3295 /* callback to deliver rx frames to the OS */ 3296 ol_txrx_rx_fp osif_rx_stack; 3297 /* Callback to handle rx fisa frames */ 3298 ol_txrx_fisa_rx_fp osif_fisa_rx; 3299 ol_txrx_fisa_flush_fp osif_fisa_flush; 3300 3301 /* call back function to flush out queued rx packets*/ 3302 ol_txrx_rx_flush_fp osif_rx_flush; 3303 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 3304 ol_txrx_get_key_fp osif_get_key; 3305 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 3306 3307 #ifdef notyet 3308 /* callback to check if the msdu is an WAI (WAPI) frame */ 3309 ol_rx_check_wai_fp osif_check_wai; 3310 #endif 3311 3312 /* proxy arp function */ 3313 ol_txrx_proxy_arp_fp osif_proxy_arp; 3314 3315 ol_txrx_mcast_me_fp me_convert; 3316 3317 /* completion function used by this vdev*/ 3318 ol_txrx_completion_fp tx_comp; 3319 3320 ol_txrx_get_tsf_time get_tsf_time; 3321 3322 /* callback to classify critical packets */ 3323 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 3324 3325 /* deferred vdev deletion state */ 3326 struct { 3327 /* VDEV delete pending */ 3328 int pending; 3329 /* 3330 * callback and a context argument to provide a 3331 * notification for when the vdev is deleted. 3332 */ 3333 ol_txrx_vdev_delete_cb callback; 3334 void *context; 3335 } delete; 3336 3337 /* tx data delivery notification callback function */ 3338 struct { 3339 ol_txrx_data_tx_cb func; 3340 void *ctxt; 3341 } tx_non_std_data_callback; 3342 3343 3344 /* safe mode control to bypass the encrypt and decipher process*/ 3345 uint32_t safemode; 3346 3347 /* rx filter related */ 3348 uint32_t drop_unenc; 3349 #ifdef notyet 3350 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 3351 uint32_t filters_num; 3352 #endif 3353 /* TDLS Link status */ 3354 bool tdls_link_connected; 3355 bool is_tdls_frame; 3356 3357 /* per vdev rx nbuf queue */ 3358 qdf_nbuf_queue_t rxq; 3359 3360 uint8_t tx_ring_id; 3361 struct dp_tx_desc_pool_s *tx_desc; 3362 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 3363 3364 /* Capture timestamp of previous tx packet enqueued */ 3365 uint64_t prev_tx_enq_tstamp; 3366 3367 /* Capture timestamp of previous rx packet delivered */ 3368 uint64_t prev_rx_deliver_tstamp; 3369 3370 /* VDEV Stats */ 3371 struct cdp_vdev_stats stats; 3372 3373 /* Is this a proxySTA VAP */ 3374 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 3375 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 3376 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 3377 reserved : 5; /* Reserved */ 3378 3379 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 3380 struct dp_tx_desc_pool_s *pool; 3381 #endif 3382 /* AP BRIDGE enabled */ 3383 bool ap_bridge_enabled; 3384 3385 enum cdp_sec_type sec_type; 3386 3387 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 3388 bool raw_mode_war; 3389 3390 3391 /* 8021p PCP-TID mapping table ID */ 3392 uint8_t tidmap_tbl_id; 3393 3394 /* 8021p PCP-TID map values */ 3395 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3396 3397 /* TIDmap priority */ 3398 uint8_t tidmap_prty; 3399 3400 #ifdef QCA_MULTIPASS_SUPPORT 3401 uint16_t *iv_vlan_map; 3402 3403 /* dp_peer special list */ 3404 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 3405 DP_MUTEX_TYPE mpass_peer_mutex; 3406 #endif 3407 /* Extended data path handle */ 3408 struct cdp_ext_vdev *vdev_dp_ext_handle; 3409 #ifdef VDEV_PEER_PROTOCOL_COUNT 3410 /* 3411 * Rx-Ingress and Tx-Egress are in the lower level DP layer 3412 * Rx-Egress and Tx-ingress are handled in osif layer for DP 3413 * So 3414 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 3415 * Rx-Ingress and Tx-Egress definitions are here below 3416 */ 3417 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 3418 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 3419 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 3420 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 3421 bool peer_protocol_count_track; 3422 int peer_protocol_count_dropmask; 3423 #endif 3424 /* callback to collect connectivity stats */ 3425 ol_txrx_stats_rx_fp stats_cb; 3426 uint32_t num_peers; 3427 /* entry to inactive_list*/ 3428 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 3429 3430 #ifdef WLAN_SUPPORT_RX_FISA 3431 /** 3432 * Params used for controlling the fisa aggregation dynamically 3433 */ 3434 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 3435 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 3436 #endif 3437 /* 3438 * Refcount for VDEV currently incremented when 3439 * peer is created for VDEV 3440 */ 3441 qdf_atomic_t ref_cnt; 3442 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 3443 uint8_t num_latency_critical_conn; 3444 #ifdef WLAN_SUPPORT_MESH_LATENCY 3445 uint8_t peer_tid_latency_enabled; 3446 /* tid latency configuration parameters */ 3447 struct { 3448 uint32_t service_interval; 3449 uint32_t burst_size; 3450 uint8_t latency_tid; 3451 } mesh_tid_latency_config; 3452 #endif 3453 #ifdef WIFI_MONITOR_SUPPORT 3454 struct dp_mon_vdev *monitor_vdev; 3455 #endif 3456 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 3457 /* Delta between TQM clock and TSF clock */ 3458 uint32_t delta_tsf; 3459 #endif 3460 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 3461 /* Indicate if uplink delay report is enabled or not */ 3462 qdf_atomic_t ul_delay_report; 3463 /* accumulative delay for every TX completion */ 3464 qdf_atomic_t ul_delay_accum; 3465 /* accumulative number of packets delay has accumulated */ 3466 qdf_atomic_t ul_pkts_accum; 3467 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 3468 3469 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 3470 uint8_t vdev_stats_id; 3471 #ifdef HW_TX_DELAY_STATS_ENABLE 3472 /* hw tx delay stats enable */ 3473 uint8_t hw_tx_delay_stats_enabled; 3474 #endif 3475 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3476 uint32_t roaming_peer_status; 3477 union dp_align_mac_addr roaming_peer_mac; 3478 #endif 3479 #ifdef DP_TRAFFIC_END_INDICATION 3480 /* per vdev feature enable/disable status */ 3481 bool traffic_end_ind_en; 3482 /* per vdev nbuf queue for traffic end indication packets */ 3483 qdf_nbuf_queue_t end_ind_pkt_q; 3484 #endif 3485 }; 3486 3487 enum { 3488 dp_sec_mcast = 0, 3489 dp_sec_ucast 3490 }; 3491 3492 #ifdef WDS_VENDOR_EXTENSION 3493 typedef struct { 3494 uint8_t wds_tx_mcast_4addr:1, 3495 wds_tx_ucast_4addr:1, 3496 wds_rx_filter:1, /* enforce rx filter */ 3497 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 3498 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 3499 3500 } dp_ecm_policy; 3501 #endif 3502 3503 /* 3504 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 3505 * @cached_bufq: nbuff list to enqueue rx packets 3506 * @bufq_lock: spinlock for nbuff list access 3507 * @thres: maximum threshold for number of rx buff to enqueue 3508 * @entries: number of entries 3509 * @dropped: number of packets dropped 3510 */ 3511 struct dp_peer_cached_bufq { 3512 qdf_list_t cached_bufq; 3513 qdf_spinlock_t bufq_lock; 3514 uint32_t thresh; 3515 uint32_t entries; 3516 uint32_t dropped; 3517 }; 3518 3519 /** 3520 * enum dp_peer_ast_flowq 3521 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 3522 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 3523 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 3524 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 3525 */ 3526 enum dp_peer_ast_flowq { 3527 DP_PEER_AST_FLOWQ_HI_PRIO, 3528 DP_PEER_AST_FLOWQ_LOW_PRIO, 3529 DP_PEER_AST_FLOWQ_UDP, 3530 DP_PEER_AST_FLOWQ_NON_UDP, 3531 DP_PEER_AST_FLOWQ_MAX, 3532 }; 3533 3534 /* 3535 * struct dp_ast_flow_override_info - ast override info 3536 * @ast_index - ast indexes in peer map message 3537 * @ast_valid_mask - ast valid mask for each ast index 3538 * @ast_flow_mask - ast flow mask for each ast index 3539 * @tid_valid_low_pri_mask - per tid mask for low priority flow 3540 * @tid_valid_hi_pri_mask - per tid mask for hi priority flow 3541 */ 3542 struct dp_ast_flow_override_info { 3543 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 3544 uint8_t ast_valid_mask; 3545 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 3546 uint8_t tid_valid_low_pri_mask; 3547 uint8_t tid_valid_hi_pri_mask; 3548 }; 3549 3550 /* 3551 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 3552 * @ast_index - ast index populated by FW 3553 * @is_valid - ast flow valid mask 3554 * @valid_tid_mask - per tid mask for this ast index 3555 * @flowQ - flow queue id associated with this ast index 3556 */ 3557 struct dp_peer_ast_params { 3558 uint16_t ast_idx; 3559 uint8_t is_valid; 3560 uint8_t valid_tid_mask; 3561 uint8_t flowQ; 3562 }; 3563 3564 #define DP_MLO_FLOW_INFO_MAX 3 3565 3566 /** 3567 * struct dp_mlo_flow_override_info - Flow override info 3568 * @ast_idx: Primary TCL AST Index 3569 * @ast_idx_valid: Is AST index valid 3570 * @chip_id: CHIP ID 3571 * @tidmask: tidmask 3572 * @cache_set_num: Cache set number 3573 */ 3574 struct dp_mlo_flow_override_info { 3575 uint16_t ast_idx; 3576 uint8_t ast_idx_valid; 3577 uint8_t chip_id; 3578 uint8_t tidmask; 3579 uint8_t cache_set_num; 3580 }; 3581 3582 /** 3583 * struct dp_mlo_link_info - Link info 3584 * @peer_chip_id: Peer Chip ID 3585 * @vdev_id: Vdev ID 3586 */ 3587 struct dp_mlo_link_info { 3588 uint8_t peer_chip_id; 3589 uint8_t vdev_id; 3590 }; 3591 3592 #ifdef WLAN_SUPPORT_MSCS 3593 /*MSCS Procedure based macros */ 3594 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 3595 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 3596 /* 3597 * struct dp_peer_mscs_parameter - MSCS database obtained from 3598 * MSCS Request and Response in the control path. This data is used 3599 * by the AP to find out what priority to set based on the tuple 3600 * classification during packet processing. 3601 * @user_priority_bitmap - User priority bitmap obtained during 3602 * handshake 3603 * @user_priority_limit - User priority limit obtained during 3604 * handshake 3605 * @classifier_mask - params to be compared during processing 3606 */ 3607 struct dp_peer_mscs_parameter { 3608 uint8_t user_priority_bitmap; 3609 uint8_t user_priority_limit; 3610 uint8_t classifier_mask; 3611 }; 3612 #endif 3613 3614 #ifdef QCA_SUPPORT_WDS_EXTENDED 3615 #define WDS_EXT_PEER_INIT_BIT 0 3616 3617 /** 3618 * struct dp_wds_ext_peer - wds ext peer structure 3619 * This is used when wds extended feature is enabled 3620 * both compile time and run time. It is created 3621 * when 1st 4 address frame is received from 3622 * wds backhaul. 3623 * @osif_vdev: Handle to the OS shim SW's virtual device 3624 * @init: wds ext netdev state 3625 */ 3626 struct dp_wds_ext_peer { 3627 ol_osif_peer_handle osif_peer; 3628 unsigned long init; 3629 }; 3630 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3631 3632 #ifdef WLAN_SUPPORT_MESH_LATENCY 3633 /*Advanced Mesh latency feature based macros */ 3634 /* 3635 * struct dp_peer_mesh_latency parameter - Mesh latency related 3636 * parameters. This data is updated per peer per TID based on 3637 * the flow tuple classification in external rule database 3638 * during packet processing. 3639 * @service_interval_dl - Service interval associated with TID in DL 3640 * @burst_size_dl - Burst size additive over multiple flows in DL 3641 * @service_interval_ul - Service interval associated with TID in UL 3642 * @burst_size_ul - Burst size additive over multiple flows in UL 3643 * @ac - custom ac derived from service interval 3644 * @msduq - MSDU queue number within TID 3645 */ 3646 struct dp_peer_mesh_latency_parameter { 3647 uint32_t service_interval_dl; 3648 uint32_t burst_size_dl; 3649 uint32_t service_interval_ul; 3650 uint32_t burst_size_ul; 3651 uint8_t ac; 3652 uint8_t msduq; 3653 }; 3654 #endif 3655 3656 #ifdef WLAN_FEATURE_11BE_MLO 3657 /* Max number of links for MLO connection */ 3658 #define DP_MAX_MLO_LINKS 3 3659 3660 /** 3661 * struct dp_peer_link_info - link peer information for MLO 3662 * @mac_add: Mac address 3663 * @vdev_id: Vdev ID for current link peer 3664 * @is_valid: flag for link peer info valid or not 3665 * @chip_id: chip id 3666 */ 3667 struct dp_peer_link_info { 3668 union dp_align_mac_addr mac_addr; 3669 uint8_t vdev_id; 3670 uint8_t is_valid; 3671 uint8_t chip_id; 3672 }; 3673 3674 /** 3675 * struct dp_mld_link_peers - this structure is used to get link peers 3676 pointer from mld peer 3677 * @link_peers: link peers pointer array 3678 * @num_links: number of link peers fetched 3679 */ 3680 struct dp_mld_link_peers { 3681 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 3682 uint8_t num_links; 3683 }; 3684 #endif 3685 3686 typedef void *dp_txrx_ref_handle; 3687 3688 /** 3689 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 3690 * Tx completion path 3691 * @cdp_pkt_info ucast: Unicast Packet Count 3692 * @cdp_pkt_info mcast: Multicast Packet Count 3693 * @cdp_pkt_info bcast: Broadcast Packet Count 3694 * @cdp_pkt_info nawds_mcast: NAWDS Multicast Packet Count 3695 * @cdp_pkt_info tx_success: Successful Tx Packets 3696 * @nawds_mcast_drop: NAWDS Multicast Drop Count 3697 * @ofdma: Total Packets as ofdma 3698 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 3699 * @amsdu_cnt: Number of MSDUs part of AMSDU 3700 * @cdp_pkt_info fw_rem: Discarded by firmware 3701 * @fw_rem_notx: firmware_discard_untransmitted 3702 * @fw_rem_tx: firmware_discard_transmitted 3703 * @age_out: aged out in mpdu/msdu queues 3704 * @fw_reason1: discarded by firmware reason 1 3705 * @fw_reason2: discarded by firmware reason 2 3706 * @fw_reason3: discarded by firmware reason 3 3707 * @fw_rem_no_match: dropped due to fw no match command 3708 * @drop_threshold: dropped due to HW threshold 3709 * @drop_link_desc_na: dropped due resource not available in HW 3710 * @invalid_drop: Invalid msdu drop 3711 * @mcast_vdev_drop: MCAST drop configured for VDEV in HW 3712 * @invalid_rr: Invalid TQM release reason 3713 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 3714 * @retry_count: packets successfully send after one or more retry 3715 * @multiple_retry_count: packets successfully sent after more than one retry 3716 * @no_ack_count: no ack pkt count for different protocols 3717 * @tx_success_twt: Successful Tx Packets in TWT session 3718 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 3719 * @avg_sojourn_msdu[CDP_DATA_TID_MAX]: Avg sojourn msdu stat 3720 * @protocol_trace_cnt: per-peer protocol counter 3721 * @release_src_not_tqm: Counter to keep track of release source is not TQM 3722 * in TX completion status processing 3723 */ 3724 struct dp_peer_per_pkt_tx_stats { 3725 struct cdp_pkt_info ucast; 3726 struct cdp_pkt_info mcast; 3727 struct cdp_pkt_info bcast; 3728 struct cdp_pkt_info nawds_mcast; 3729 struct cdp_pkt_info tx_success; 3730 uint32_t nawds_mcast_drop; 3731 uint32_t ofdma; 3732 uint32_t non_amsdu_cnt; 3733 uint32_t amsdu_cnt; 3734 struct { 3735 struct cdp_pkt_info fw_rem; 3736 uint32_t fw_rem_notx; 3737 uint32_t fw_rem_tx; 3738 uint32_t age_out; 3739 uint32_t fw_reason1; 3740 uint32_t fw_reason2; 3741 uint32_t fw_reason3; 3742 uint32_t fw_rem_queue_disable; 3743 uint32_t fw_rem_no_match; 3744 uint32_t drop_threshold; 3745 uint32_t drop_link_desc_na; 3746 uint32_t invalid_drop; 3747 uint32_t mcast_vdev_drop; 3748 uint32_t invalid_rr; 3749 } dropped; 3750 uint32_t failed_retry_count; 3751 uint32_t retry_count; 3752 uint32_t multiple_retry_count; 3753 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 3754 struct cdp_pkt_info tx_success_twt; 3755 unsigned long last_tx_ts; 3756 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 3757 #ifdef VDEV_PEER_PROTOCOL_COUNT 3758 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 3759 #endif 3760 uint32_t release_src_not_tqm; 3761 }; 3762 3763 /** 3764 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 3765 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 3766 * disabled or in HTT Tx PPDU completion path when macro is enabled 3767 * @stbc: Packets in STBC 3768 * @ldpc: Packets in LDPC 3769 * @retries: Packet retries 3770 * @pkt_type[DOT11_MAX]: pkt count for different .11 modes 3771 * @wme_ac_type[WME_AC_MAX]: Wireless Multimedia type Count 3772 * @excess_retries_per_ac[WME_AC_MAX]: Wireless Multimedia type Count 3773 * @ampdu_cnt: completion of aggregation 3774 * @non_ampdu_cnt: tx completion not aggregated 3775 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 3776 * @tx_ppdus: ppdus in tx 3777 * @tx_mpdus_success: mpdus successful in tx 3778 * @tx_mpdus_tried: mpdus tried in tx 3779 * @tx_rate: Tx Rate in kbps 3780 * @last_tx_rate: Last tx rate for unicast packets 3781 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 3782 * @mcast_last_tx_rate: Last tx rate for multicast packets 3783 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 3784 * @rnd_avg_tx_rate: Rounded average tx rate 3785 * @avg_tx_rate: Average TX rate 3786 * @tx_ratecode: Tx rate code of last frame 3787 * @pream_punct_cnt: Preamble Punctured count 3788 * @sgi_count[MAX_GI]: SGI count 3789 * @nss[SS_COUNT]: Packet count for different num_spatial_stream values 3790 * @bw[MAX_BW]: Packet Count for different bandwidths 3791 * @ru_start: RU start index 3792 * @ru_tones: RU tones size 3793 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 3794 * @transmit_type: pkt info for tx transmit type 3795 * @mu_group_id: mumimo mu group id 3796 * @last_ack_rssi: RSSI of last acked packet 3797 * @nss_info: NSS 1,2, ...8 3798 * @mcs_info: MCS index 3799 * @bw_info: Bandwidth 3800 * <enum 0 bw_20_MHz> 3801 * <enum 1 bw_40_MHz> 3802 * <enum 2 bw_80_MHz> 3803 * <enum 3 bw_160_MHz> 3804 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 3805 * <enum 1 0_4_us_sgi > Legacy short GI 3806 * <enum 2 1_6_us_sgi > HE related GI 3807 * <enum 3 3_2_us_sgi > HE 3808 * @preamble_info: preamble 3809 * @tx_ucast_total: total ucast count 3810 * @tx_ucast_success: total ucast success count 3811 * @retries_mpdu: mpdu number of successfully transmitted after retries 3812 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 3813 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 3814 * @mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]: MU Tx packet count for 11BE 3815 * @punc_bw[MAX_PUNCTURED_MODE]: MSDU count for punctured bw 3816 */ 3817 struct dp_peer_extd_tx_stats { 3818 uint32_t stbc; 3819 uint32_t ldpc; 3820 uint32_t retries; 3821 struct cdp_pkt_type pkt_type[DOT11_MAX]; 3822 uint32_t wme_ac_type[WME_AC_MAX]; 3823 uint32_t excess_retries_per_ac[WME_AC_MAX]; 3824 uint32_t ampdu_cnt; 3825 uint32_t non_ampdu_cnt; 3826 uint32_t num_ppdu_cookie_valid; 3827 uint32_t tx_ppdus; 3828 uint32_t tx_mpdus_success; 3829 uint32_t tx_mpdus_tried; 3830 3831 uint32_t tx_rate; 3832 uint32_t last_tx_rate; 3833 uint32_t last_tx_rate_mcs; 3834 uint32_t mcast_last_tx_rate; 3835 uint32_t mcast_last_tx_rate_mcs; 3836 uint64_t rnd_avg_tx_rate; 3837 uint64_t avg_tx_rate; 3838 uint16_t tx_ratecode; 3839 3840 uint32_t sgi_count[MAX_GI]; 3841 uint32_t pream_punct_cnt; 3842 uint32_t nss[SS_COUNT]; 3843 uint32_t bw[MAX_BW]; 3844 uint32_t ru_start; 3845 uint32_t ru_tones; 3846 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 3847 3848 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 3849 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 3850 3851 uint32_t last_ack_rssi; 3852 3853 uint32_t nss_info:4, 3854 mcs_info:4, 3855 bw_info:4, 3856 gi_info:4, 3857 preamble_info:4; 3858 3859 uint32_t retries_mpdu; 3860 uint32_t mpdu_success_with_retries; 3861 struct cdp_pkt_info tx_ucast_total; 3862 struct cdp_pkt_info tx_ucast_success; 3863 #ifdef WLAN_FEATURE_11BE 3864 struct cdp_pkt_type su_be_ppdu_cnt; 3865 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 3866 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 3867 #endif 3868 }; 3869 3870 /** 3871 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 3872 * @rcvd_reo[CDP_MAX_RX_RINGS]: Packets received on the reo ring 3873 * @rx_lmac[CDP_MAX_LMACS]: Packets received on each lmac 3874 * @unicast: Total unicast packets 3875 * @multicast: Total multicast packets 3876 * @bcast: Broadcast Packet Count 3877 * @raw: Raw Pakets received 3878 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 3879 * @mec_drop: Total MEC packets dropped 3880 * @last_rx_ts: last timestamp in jiffies when RX happened 3881 * @intra_bss.pkts: Intra BSS packets received 3882 * @intra_bss.fail: Intra BSS packets failed 3883 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 3884 * @mic_err: Rx MIC errors CCMP 3885 * @decrypt_err: Rx Decryption Errors CRC 3886 * @fcserr: rx MIC check failed (CCMP) 3887 * @pn_err: pn check failed 3888 * @oor_err: Rx OOR errors 3889 * @jump_2k_err: 2k jump errors 3890 * @rxdma_wifi_parse_err: rxdma wifi parse errors 3891 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 3892 * @amsdu_cnt: Number of MSDUs part of AMSDU 3893 * @rx_retries: retries of packet in rx 3894 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 3895 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 3896 * @policy_check_drop: policy check drops 3897 * @to_stack_twt: Total packets sent up the stack in TWT session 3898 * @protocol_trace_cnt: per-peer protocol counters 3899 */ 3900 struct dp_peer_per_pkt_rx_stats { 3901 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 3902 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 3903 struct cdp_pkt_info unicast; 3904 struct cdp_pkt_info multicast; 3905 struct cdp_pkt_info bcast; 3906 struct cdp_pkt_info raw; 3907 uint32_t nawds_mcast_drop; 3908 struct cdp_pkt_info mec_drop; 3909 unsigned long last_rx_ts; 3910 struct { 3911 struct cdp_pkt_info pkts; 3912 struct cdp_pkt_info fail; 3913 uint32_t mdns_no_fwd; 3914 } intra_bss; 3915 struct { 3916 uint32_t mic_err; 3917 uint32_t decrypt_err; 3918 uint32_t fcserr; 3919 uint32_t pn_err; 3920 uint32_t oor_err; 3921 uint32_t jump_2k_err; 3922 uint32_t rxdma_wifi_parse_err; 3923 } err; 3924 uint32_t non_amsdu_cnt; 3925 uint32_t amsdu_cnt; 3926 uint32_t rx_retries; 3927 uint32_t multipass_rx_pkt_drop; 3928 uint32_t peer_unauth_rx_pkt_drop; 3929 uint32_t policy_check_drop; 3930 struct cdp_pkt_info to_stack_twt; 3931 #ifdef VDEV_PEER_PROTOCOL_COUNT 3932 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 3933 #endif 3934 uint32_t mcast_3addr_drop; 3935 }; 3936 3937 /** 3938 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 3939 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 3940 * Rx monitor patch when macro is enabled 3941 * @pkt_type[DOT11_MAX]: pkt counter for different .11 modes 3942 * @wme_ac_type[WME_AC_MAX]: Wireless Multimedia type Count 3943 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 3944 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 3945 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 3946 * @ampdu_cnt: Number of MSDUs part of AMSPU 3947 * @rx_mpdus: mpdu in rx 3948 * @rx_ppdus: ppdu in rx 3949 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 3950 * @rx_mu[TXRX_TYPE_MU_MAX]: Rx MU stats 3951 * @reception_type[MAX_RECEPTION_TYPES]: Reception type of packets 3952 * @ppdu_cnt[MAX_RECEPTION_TYPES]: PPDU packet count in reception type 3953 * @sgi_count[MAX_GI]: sgi count 3954 * @nss[SS_COUNT]: packet count in spatiel Streams 3955 * @ppdu_nss[SS_COUNT]: PPDU packet count in spatial streams 3956 * @bw[MAX_BW]: Packet Count in different bandwidths 3957 * @rx_mpdu_cnt[MAX_MCS]: rx mpdu count per MCS rate 3958 * @rx_rate: Rx rate 3959 * @last_rx_rate: Previous rx rate 3960 * @rnd_avg_rx_rate: Rounded average rx rate 3961 * @avg_rx_rate: Average Rx rate 3962 * @rx_ratecode: Rx rate code of last frame 3963 * @avg_snr: Average snr 3964 * @rx_snr_measured_time: Time at which snr is measured 3965 * @snr: SNR of received signal 3966 * @last_snr: Previous snr 3967 * @nss_info: NSS 1,2, ...8 3968 * @mcs_info: MCS index 3969 * @bw_info: Bandwidth 3970 * <enum 0 bw_20_MHz> 3971 * <enum 1 bw_40_MHz> 3972 * <enum 2 bw_80_MHz> 3973 * <enum 3 bw_160_MHz> 3974 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 3975 * <enum 1 0_4_us_sgi > Legacy short GI 3976 * <enum 2 1_6_us_sgi > HE related GI 3977 * <enum 3 3_2_us_sgi > HE 3978 * @preamble_info: preamble 3979 * @mpdu_retry_cnt: retries of mpdu in rx 3980 * @su_be_ppdu_cnt: SU Rx packet count for BE 3981 * @mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]: MU rx packet count for BE 3982 * @punc_bw[MAX_PUNCTURED_MODE]: MSDU count for punctured bw 3983 */ 3984 struct dp_peer_extd_rx_stats { 3985 struct cdp_pkt_type pkt_type[DOT11_MAX]; 3986 uint32_t wme_ac_type[WME_AC_MAX]; 3987 uint32_t mpdu_cnt_fcs_ok; 3988 uint32_t mpdu_cnt_fcs_err; 3989 uint32_t non_ampdu_cnt; 3990 uint32_t ampdu_cnt; 3991 uint32_t rx_mpdus; 3992 uint32_t rx_ppdus; 3993 3994 struct cdp_pkt_type su_ax_ppdu_cnt; 3995 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 3996 uint32_t reception_type[MAX_RECEPTION_TYPES]; 3997 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 3998 3999 uint32_t sgi_count[MAX_GI]; 4000 uint32_t nss[SS_COUNT]; 4001 uint32_t ppdu_nss[SS_COUNT]; 4002 uint32_t bw[MAX_BW]; 4003 uint32_t rx_mpdu_cnt[MAX_MCS]; 4004 4005 uint32_t rx_rate; 4006 uint32_t last_rx_rate; 4007 uint32_t rnd_avg_rx_rate; 4008 uint32_t avg_rx_rate; 4009 uint32_t rx_ratecode; 4010 4011 uint32_t avg_snr; 4012 unsigned long rx_snr_measured_time; 4013 uint8_t snr; 4014 uint8_t last_snr; 4015 4016 uint32_t nss_info:4, 4017 mcs_info:4, 4018 bw_info:4, 4019 gi_info:4, 4020 preamble_info:4; 4021 4022 uint32_t mpdu_retry_cnt; 4023 #ifdef WLAN_FEATURE_11BE 4024 struct cdp_pkt_type su_be_ppdu_cnt; 4025 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4026 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4027 #endif 4028 }; 4029 4030 /** 4031 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4032 * @tx: Per pkt Tx stats 4033 * @rx: Per pkt Rx stats 4034 */ 4035 struct dp_peer_per_pkt_stats { 4036 struct dp_peer_per_pkt_tx_stats tx; 4037 struct dp_peer_per_pkt_rx_stats rx; 4038 }; 4039 4040 /** 4041 * struct dp_peer_extd_stats - Stats from extended path for peer 4042 * @tx: Extended path tx stats 4043 * @rx: Extended path rx stats 4044 */ 4045 struct dp_peer_extd_stats { 4046 struct dp_peer_extd_tx_stats tx; 4047 struct dp_peer_extd_rx_stats rx; 4048 }; 4049 4050 /** 4051 * struct dp_peer_stats - Peer stats 4052 * @per_pkt_stats: Per packet path stats 4053 * @extd_stats: Extended path stats 4054 */ 4055 struct dp_peer_stats { 4056 struct dp_peer_per_pkt_stats per_pkt_stats; 4057 #ifndef QCA_ENHANCED_STATS_SUPPORT 4058 struct dp_peer_extd_stats extd_stats; 4059 #endif 4060 }; 4061 4062 /** 4063 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4064 * @tx_failed: Total Tx failure 4065 * @cdp_pkt_info comp_pkt: Pkt Info for which completions were received 4066 * @to_stack: Total packets sent up the stack 4067 * @stats: Peer stats 4068 * @delay_stats: Peer delay stats 4069 * @jitter_stats: Peer jitter stats 4070 * @bw: bandwidth of peer connection 4071 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4072 */ 4073 struct dp_txrx_peer { 4074 /* Core TxRx Peer */ 4075 4076 /* VDEV to which this peer is associated */ 4077 struct dp_vdev *vdev; 4078 4079 /* peer ID for this peer */ 4080 uint16_t peer_id; 4081 4082 uint8_t authorize:1, /* Set when authorized */ 4083 in_twt:1, /* in TWT session */ 4084 hw_txrx_stats_en:1, /*Indicate HW offload vdev stats */ 4085 mld_peer:1; /* MLD peer*/ 4086 4087 uint32_t tx_failed; 4088 struct cdp_pkt_info comp_pkt; 4089 struct cdp_pkt_info to_stack; 4090 4091 struct dp_peer_stats stats; 4092 4093 struct dp_peer_delay_stats *delay_stats; 4094 4095 struct cdp_peer_tid_stats *jitter_stats; 4096 4097 struct { 4098 enum cdp_sec_type sec_type; 4099 u_int32_t michael_key[2]; /* relevant for TKIP */ 4100 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4101 4102 uint16_t nawds_enabled:1, /* NAWDS flag */ 4103 bss_peer:1, /* set for bss peer */ 4104 isolation:1, /* enable peer isolation for this peer */ 4105 wds_enabled:1; /* WDS peer */ 4106 #ifdef WDS_VENDOR_EXTENSION 4107 dp_ecm_policy wds_ecm; 4108 #endif 4109 #ifdef PEER_CACHE_RX_PKTS 4110 qdf_atomic_t flush_in_progress; 4111 struct dp_peer_cached_bufq bufq_info; 4112 #endif 4113 #ifdef QCA_MULTIPASS_SUPPORT 4114 /* node in the special peer list element */ 4115 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 4116 /* vlan id for key */ 4117 uint16_t vlan_id; 4118 #endif 4119 #ifdef QCA_SUPPORT_WDS_EXTENDED 4120 struct dp_wds_ext_peer wds_ext; 4121 ol_txrx_rx_fp osif_rx; 4122 #endif 4123 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 4124 #ifdef CONFIG_SAWF 4125 struct dp_peer_sawf_stats *sawf_stats; 4126 #endif 4127 #ifdef DP_PEER_EXTENDED_API 4128 enum cdp_peer_bw bw; 4129 uint8_t mpdu_retry_threshold; 4130 #endif 4131 }; 4132 4133 /* Peer structure for data path state */ 4134 struct dp_peer { 4135 struct dp_txrx_peer *txrx_peer; 4136 #ifdef WIFI_MONITOR_SUPPORT 4137 struct dp_mon_peer *monitor_peer; 4138 #endif 4139 /* peer ID for this peer */ 4140 uint16_t peer_id; 4141 4142 /* VDEV to which this peer is associated */ 4143 struct dp_vdev *vdev; 4144 4145 struct dp_ast_entry *self_ast_entry; 4146 4147 qdf_atomic_t ref_cnt; 4148 4149 union dp_align_mac_addr mac_addr; 4150 4151 /* node in the vdev's list of peers */ 4152 TAILQ_ENTRY(dp_peer) peer_list_elem; 4153 /* node in the hash table bin's list of peers */ 4154 TAILQ_ENTRY(dp_peer) hash_list_elem; 4155 4156 /* TID structures pointer */ 4157 struct dp_rx_tid *rx_tid; 4158 4159 /* TBD: No transmit TID state required? */ 4160 4161 struct { 4162 enum cdp_sec_type sec_type; 4163 u_int32_t michael_key[2]; /* relevant for TKIP */ 4164 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4165 4166 /* NAWDS Flag and Bss Peer bit */ 4167 uint16_t bss_peer:1, /* set for bss peer */ 4168 authorize:1, /* Set when authorized */ 4169 valid:1, /* valid bit */ 4170 delete_in_progress:1, /* Indicate kickout sent */ 4171 sta_self_peer:1, /* Indicate STA self peer */ 4172 is_tdls_peer:1; /* Indicate TDLS peer */ 4173 4174 #ifdef WLAN_FEATURE_11BE_MLO 4175 uint8_t first_link:1, /* first link peer for MLO */ 4176 primary_link:1; /* primary link for MLO */ 4177 #endif 4178 4179 /* MCL specific peer local id */ 4180 uint16_t local_id; 4181 enum ol_txrx_peer_state state; 4182 qdf_spinlock_t peer_info_lock; 4183 4184 /* Peer calibrated stats */ 4185 struct cdp_calibr_stats stats; 4186 4187 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 4188 /* TBD */ 4189 4190 /* Active Block ack sessions */ 4191 uint16_t active_ba_session_cnt; 4192 4193 /* Current HW buffersize setting */ 4194 uint16_t hw_buffer_size; 4195 4196 /* 4197 * Flag to check if sessions with 256 buffersize 4198 * should be terminated. 4199 */ 4200 uint8_t kill_256_sessions; 4201 qdf_atomic_t is_default_route_set; 4202 4203 #ifdef QCA_PEER_MULTIQ_SUPPORT 4204 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 4205 #endif 4206 /* entry to inactive_list*/ 4207 TAILQ_ENTRY(dp_peer) inactive_list_elem; 4208 4209 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4210 4211 uint8_t peer_state; 4212 qdf_spinlock_t peer_state_lock; 4213 #ifdef WLAN_SUPPORT_MSCS 4214 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 4215 bool mscs_active; 4216 #endif 4217 #ifdef WLAN_SUPPORT_MESH_LATENCY 4218 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 4219 #endif 4220 #ifdef WLAN_FEATURE_11BE_MLO 4221 /* peer type */ 4222 enum cdp_peer_type peer_type; 4223 /*---------for link peer---------*/ 4224 struct dp_peer *mld_peer; 4225 /*---------for mld peer----------*/ 4226 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 4227 uint8_t num_links; 4228 DP_MUTEX_TYPE link_peers_info_lock; 4229 #endif 4230 #ifdef CONFIG_SAWF_DEF_QUEUES 4231 struct dp_peer_sawf *sawf; 4232 #endif 4233 }; 4234 4235 /* 4236 * dp_invalid_peer_msg 4237 * @nbuf: data buffer 4238 * @wh: 802.11 header 4239 * @vdev_id: id of vdev 4240 */ 4241 struct dp_invalid_peer_msg { 4242 qdf_nbuf_t nbuf; 4243 struct ieee80211_frame *wh; 4244 uint8_t vdev_id; 4245 }; 4246 4247 /* 4248 * dp_tx_me_buf_t: ME buffer 4249 * next: pointer to next buffer 4250 * data: Destination Mac address 4251 * paddr_macbuf: physical address for dest_mac 4252 */ 4253 struct dp_tx_me_buf_t { 4254 /* Note: ME buf pool initialization logic expects next pointer to 4255 * be the first element. Dont add anything before next */ 4256 struct dp_tx_me_buf_t *next; 4257 uint8_t data[QDF_MAC_ADDR_SIZE]; 4258 qdf_dma_addr_t paddr_macbuf; 4259 }; 4260 4261 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 4262 struct hal_rx_fst; 4263 4264 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 4265 struct dp_rx_fse { 4266 /* HAL Rx Flow Search Entry which matches HW definition */ 4267 void *hal_rx_fse; 4268 /* Toeplitz hash value */ 4269 uint32_t flow_hash; 4270 /* Flow index, equivalent to hash value truncated to FST size */ 4271 uint32_t flow_id; 4272 /* Stats tracking for this flow */ 4273 struct cdp_flow_stats stats; 4274 /* Flag indicating whether flow is IPv4 address tuple */ 4275 uint8_t is_ipv4_addr_entry; 4276 /* Flag indicating whether flow is valid */ 4277 uint8_t is_valid; 4278 }; 4279 4280 struct dp_rx_fst { 4281 /* Software (DP) FST */ 4282 uint8_t *base; 4283 /* Pointer to HAL FST */ 4284 struct hal_rx_fst *hal_rx_fst; 4285 /* Base physical address of HAL RX HW FST */ 4286 uint64_t hal_rx_fst_base_paddr; 4287 /* Maximum number of flows FSE supports */ 4288 uint16_t max_entries; 4289 /* Num entries in flow table */ 4290 uint16_t num_entries; 4291 /* SKID Length */ 4292 uint16_t max_skid_length; 4293 /* Hash mask to obtain legitimate hash entry */ 4294 uint32_t hash_mask; 4295 /* Timer for bundling of flows */ 4296 qdf_timer_t cache_invalidate_timer; 4297 /** 4298 * Flag which tracks whether cache update 4299 * is needed on timer expiry 4300 */ 4301 qdf_atomic_t is_cache_update_pending; 4302 /* Flag to indicate completion of FSE setup in HW/FW */ 4303 bool fse_setup_done; 4304 }; 4305 4306 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 4307 #elif WLAN_SUPPORT_RX_FISA 4308 4309 /** 4310 * struct dp_fisa_reo_mismatch_stats - reo mismatch sub-case stats for FISA 4311 * @allow_cce_match: packet allowed due to cce mismatch 4312 * @allow_fse_metdata_mismatch: packet allowed since it belongs to same flow, 4313 * only fse_metadata is not same. 4314 * @allow_non_aggr: packet allowed due to any other reason. 4315 */ 4316 struct dp_fisa_reo_mismatch_stats { 4317 uint32_t allow_cce_match; 4318 uint32_t allow_fse_metdata_mismatch; 4319 uint32_t allow_non_aggr; 4320 }; 4321 4322 struct dp_fisa_stats { 4323 /* flow index invalid from RX HW TLV */ 4324 uint32_t invalid_flow_index; 4325 struct dp_fisa_reo_mismatch_stats reo_mismatch; 4326 }; 4327 4328 enum fisa_aggr_ret { 4329 FISA_AGGR_DONE, 4330 FISA_AGGR_NOT_ELIGIBLE, 4331 FISA_FLUSH_FLOW 4332 }; 4333 4334 /** 4335 * struct fisa_pkt_hist - FISA Packet history structure 4336 * @tlv_hist: array of TLV history 4337 * @ts: array of timestamps of fisa packets 4338 * @idx: index indicating the next location to be used in the array. 4339 */ 4340 struct fisa_pkt_hist { 4341 uint8_t *tlv_hist; 4342 qdf_time_t ts_hist[FISA_FLOW_MAX_AGGR_COUNT]; 4343 uint32_t idx; 4344 }; 4345 4346 struct dp_fisa_rx_sw_ft { 4347 /* HAL Rx Flow Search Entry which matches HW definition */ 4348 void *hw_fse; 4349 /* hash value */ 4350 uint32_t flow_hash; 4351 /* toeplitz hash value*/ 4352 uint32_t flow_id_toeplitz; 4353 /* Flow index, equivalent to hash value truncated to FST size */ 4354 uint32_t flow_id; 4355 /* Stats tracking for this flow */ 4356 struct cdp_flow_stats stats; 4357 /* Flag indicating whether flow is IPv4 address tuple */ 4358 uint8_t is_ipv4_addr_entry; 4359 /* Flag indicating whether flow is valid */ 4360 uint8_t is_valid; 4361 uint8_t is_populated; 4362 uint8_t is_flow_udp; 4363 uint8_t is_flow_tcp; 4364 qdf_nbuf_t head_skb; 4365 uint16_t cumulative_l4_checksum; 4366 uint16_t adjusted_cumulative_ip_length; 4367 uint16_t cur_aggr; 4368 uint16_t napi_flush_cumulative_l4_checksum; 4369 uint16_t napi_flush_cumulative_ip_length; 4370 qdf_nbuf_t last_skb; 4371 uint32_t head_skb_ip_hdr_offset; 4372 uint32_t head_skb_l4_hdr_offset; 4373 struct cdp_rx_flow_tuple_info rx_flow_tuple_info; 4374 uint8_t napi_id; 4375 struct dp_vdev *vdev; 4376 uint64_t bytes_aggregated; 4377 uint32_t flush_count; 4378 uint32_t aggr_count; 4379 uint8_t do_not_aggregate; 4380 uint16_t hal_cumultive_ip_len; 4381 struct dp_soc *soc_hdl; 4382 /* last aggregate count fetched from RX PKT TLV */ 4383 uint32_t last_hal_aggr_count; 4384 uint32_t cur_aggr_gso_size; 4385 qdf_net_udphdr_t *head_skb_udp_hdr; 4386 uint16_t frags_cumulative_len; 4387 /* CMEM parameters */ 4388 uint32_t cmem_offset; 4389 uint32_t metadata; 4390 uint32_t reo_dest_indication; 4391 qdf_time_t flow_init_ts; 4392 qdf_time_t last_accessed_ts; 4393 #ifdef WLAN_SUPPORT_RX_FISA_HIST 4394 struct fisa_pkt_hist pkt_hist; 4395 #endif 4396 }; 4397 4398 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_fisa_rx_sw_ft) 4399 #define MAX_FSE_CACHE_FL_HST 10 4400 /** 4401 * struct fse_cache_flush_history - Debug history cache flush 4402 * @timestamp: Entry update timestamp 4403 * @flows_added: Number of flows added for this flush 4404 * @flows_deleted: Number of flows deleted for this flush 4405 */ 4406 struct fse_cache_flush_history { 4407 uint64_t timestamp; 4408 uint32_t flows_added; 4409 uint32_t flows_deleted; 4410 }; 4411 4412 struct dp_rx_fst { 4413 /* Software (DP) FST */ 4414 uint8_t *base; 4415 /* Pointer to HAL FST */ 4416 struct hal_rx_fst *hal_rx_fst; 4417 /* Base physical address of HAL RX HW FST */ 4418 uint64_t hal_rx_fst_base_paddr; 4419 /* Maximum number of flows FSE supports */ 4420 uint16_t max_entries; 4421 /* Num entries in flow table */ 4422 uint16_t num_entries; 4423 /* SKID Length */ 4424 uint16_t max_skid_length; 4425 /* Hash mask to obtain legitimate hash entry */ 4426 uint32_t hash_mask; 4427 /* Lock for adding/deleting entries of FST */ 4428 qdf_spinlock_t dp_rx_fst_lock; 4429 uint32_t add_flow_count; 4430 uint32_t del_flow_count; 4431 uint32_t hash_collision_cnt; 4432 struct dp_soc *soc_hdl; 4433 qdf_atomic_t fse_cache_flush_posted; 4434 qdf_timer_t fse_cache_flush_timer; 4435 /* Allow FSE cache flush cmd to FW */ 4436 bool fse_cache_flush_allow; 4437 struct fse_cache_flush_history cache_fl_rec[MAX_FSE_CACHE_FL_HST]; 4438 /* FISA DP stats */ 4439 struct dp_fisa_stats stats; 4440 4441 /* CMEM params */ 4442 qdf_work_t fst_update_work; 4443 qdf_workqueue_t *fst_update_wq; 4444 qdf_list_t fst_update_list; 4445 uint32_t meta_counter; 4446 uint32_t cmem_ba; 4447 qdf_spinlock_t dp_rx_sw_ft_lock[MAX_REO_DEST_RINGS]; 4448 qdf_event_t cmem_resp_event; 4449 bool flow_deletion_supported; 4450 bool fst_in_cmem; 4451 bool pm_suspended; 4452 }; 4453 4454 #endif /* WLAN_SUPPORT_RX_FISA */ 4455 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 4456 4457 #ifdef WLAN_FEATURE_STATS_EXT 4458 /* 4459 * dp_req_rx_hw_stats_t: RX peer HW stats query structure 4460 * @pending_tid_query_cnt: pending tid stats count which waits for REO status 4461 * @is_query_timeout: flag to show is stats query timeout 4462 */ 4463 struct dp_req_rx_hw_stats_t { 4464 qdf_atomic_t pending_tid_stats_cnt; 4465 bool is_query_timeout; 4466 }; 4467 #endif 4468 /* soc level structure to declare arch specific ops for DP */ 4469 4470 4471 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 4472 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 4473 uint32_t mac_id); 4474 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 4475 4476 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 4477 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 4478 #else 4479 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 4480 #endif 4481 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 4482 int ring_type, uint32_t num_entries, 4483 bool cached); 4484 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 4485 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 4486 int ring_type, int ring_num, int mac_id); 4487 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 4488 int ring_type, int ring_num); 4489 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 4490 enum peer_stats_type stats_type); 4491 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 4492 enum peer_stats_type stats_type); 4493 4494 enum timer_yield_status 4495 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 4496 uint64_t start_time); 4497 4498 /* 4499 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 4500 * @vdev: Datapath VDEV handle 4501 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 4502 * @hash_based: pointer to hash value (enabled/disabled) to be populated 4503 * 4504 * Return: None 4505 */ 4506 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 4507 enum cdp_host_reo_dest_ring *reo_dest, 4508 bool *hash_based); 4509 4510 /** 4511 * dp_reo_remap_config() - configure reo remap register value based 4512 * nss configuration. 4513 * based on offload_radio value below remap configuration 4514 * get applied. 4515 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 4516 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 4517 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 4518 * 3 - both Radios handled by NSS (remap not required) 4519 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 4520 * 4521 * @remap0: output parameter indicates reo remap 0 register value 4522 * @remap1: output parameter indicates reo remap 1 register value 4523 * @remap2: output parameter indicates reo remap 2 register value 4524 * Return: bool type, true if remap is configured else false. 4525 */ 4526 4527 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 4528 uint32_t *remap1, uint32_t *remap2); 4529 4530 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 4531 /** 4532 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 4533 * @soc: DP soc handle 4534 * @tx_comp_hal_desc: HAL TX Comp Descriptor 4535 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 4536 * 4537 * Return: None 4538 */ 4539 void dp_tx_comp_get_prefetched_params_from_hal_desc( 4540 struct dp_soc *soc, 4541 void *tx_comp_hal_desc, 4542 struct dp_tx_desc_s **r_tx_desc); 4543 #endif 4544 #endif /* _DP_TYPES_H_ */ 4545