1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 64 #define DP_MAX_INTERRUPT_CONTEXTS 8 65 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 66 #define DSCP_TID_MAP_MAX (64) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(CONFIG_MCL) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 #define MAX_LINK_DESC_BANKS 8 82 #define MAX_TXDESC_POOLS 4 83 #define MAX_RXDESC_POOLS 4 84 #define MAX_REO_DEST_RINGS 4 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DP_MAX_INTERRUPT_CONTEXTS 8 89 #define DEFAULT_HW_PEER_ID 0xffff 90 91 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 92 93 #define DP_MAX_INTERRUPT_CONTEXTS 8 94 95 /* Maximum retries for Delba per tid per peer */ 96 #define DP_MAX_DELBA_RETRY 3 97 98 #ifndef REMOVE_PKT_LOG 99 enum rx_pktlog_mode { 100 DP_RX_PKTLOG_DISABLED = 0, 101 DP_RX_PKTLOG_FULL, 102 DP_RX_PKTLOG_LITE, 103 }; 104 #endif 105 106 struct dp_soc_cmn; 107 struct dp_pdev; 108 struct dp_vdev; 109 struct dp_tx_desc_s; 110 struct dp_soc; 111 union dp_rx_desc_list_elem_t; 112 113 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 114 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 115 116 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 117 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 118 119 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 120 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 121 122 #define DP_MUTEX_TYPE qdf_spinlock_t 123 124 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 125 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 126 127 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 128 ((_a)[0] == 0x33 && \ 129 (_a)[1] == 0x33) 130 131 #define DP_FRAME_IS_BROADCAST(_a) \ 132 ((_a)[0] == 0xff && \ 133 (_a)[1] == 0xff && \ 134 (_a)[2] == 0xff && \ 135 (_a)[3] == 0xff && \ 136 (_a)[4] == 0xff && \ 137 (_a)[5] == 0xff) 138 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 139 (_llc)->llc_ssap == 0xaa && \ 140 (_llc)->llc_un.type_snap.control == 0x3) 141 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 142 #define DP_FRAME_FC0_TYPE_MASK 0x0c 143 #define DP_FRAME_FC0_TYPE_DATA 0x08 144 #define DP_FRAME_IS_DATA(_frame) \ 145 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 146 147 /** 148 * macros to convert hw mac id to sw mac id: 149 * mac ids used by hardware start from a value of 1 while 150 * those in host software start from a value of 0. Use the 151 * macros below to convert between mac ids used by software and 152 * hardware 153 */ 154 #define DP_SW2HW_MACID(id) ((id) + 1) 155 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 156 #define DP_MAC_ADDR_LEN 6 157 158 /** 159 * Number of Tx Queues 160 * enum and macro to define how many threshold levels is used 161 * for the AC based flow control 162 */ 163 #ifdef QCA_AC_BASED_FLOW_CONTROL 164 enum dp_fl_ctrl_threshold { 165 DP_TH_BE_BK = 0, 166 DP_TH_VI, 167 DP_TH_VO, 168 DP_TH_HI, 169 }; 170 171 #define FL_TH_MAX (4) 172 #define FL_TH_VI_PERCENTAGE (80) 173 #define FL_TH_VO_PERCENTAGE (60) 174 #define FL_TH_HI_PERCENTAGE (40) 175 #endif 176 177 /** 178 * enum dp_intr_mode 179 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 180 * @DP_INTR_MSI: MSI interrupts, for MCL 181 * @DP_INTR_POLL: Polling 182 */ 183 enum dp_intr_mode { 184 DP_INTR_LEGACY = 0, 185 DP_INTR_MSI, 186 DP_INTR_POLL, 187 }; 188 189 /** 190 * enum dp_tx_frm_type 191 * @dp_tx_frm_std: Regular frame, no added header fragments 192 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 193 * @dp_tx_frm_sg: SG segment 194 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 195 * @dp_tx_frm_me: Multicast to Unicast Converted frame 196 * @dp_tx_frm_raw: Raw Frame 197 */ 198 enum dp_tx_frm_type { 199 dp_tx_frm_std = 0, 200 dp_tx_frm_tso, 201 dp_tx_frm_sg, 202 dp_tx_frm_audio, 203 dp_tx_frm_me, 204 dp_tx_frm_raw, 205 }; 206 207 /** 208 * enum dp_ast_type 209 * @dp_ast_type_wds: WDS peer AST type 210 * @dp_ast_type_static: static ast entry type 211 * @dp_ast_type_mec: Multicast echo ast entry type 212 */ 213 enum dp_ast_type { 214 dp_ast_type_wds = 0, 215 dp_ast_type_static, 216 dp_ast_type_mec, 217 }; 218 219 /** 220 * enum dp_nss_cfg 221 * @dp_nss_cfg_default: No radios are offloaded 222 * @dp_nss_cfg_first_radio: First radio offloaded 223 * @dp_nss_cfg_second_radio: Second radio offloaded 224 * @dp_nss_cfg_dbdc: Dual radios offloaded 225 */ 226 enum dp_nss_cfg { 227 dp_nss_cfg_default, 228 dp_nss_cfg_first_radio, 229 dp_nss_cfg_second_radio, 230 dp_nss_cfg_dbdc, 231 }; 232 233 /** 234 * struct rx_desc_pool 235 * @pool_size: number of RX descriptor in the pool 236 * @array: pointer to array of RX descriptor 237 * @freelist: pointer to free RX descriptor link list 238 * @lock: Protection for the RX descriptor pool 239 * @owner: owner for nbuf 240 */ 241 struct rx_desc_pool { 242 uint32_t pool_size; 243 union dp_rx_desc_list_elem_t *array; 244 union dp_rx_desc_list_elem_t *freelist; 245 qdf_spinlock_t lock; 246 uint8_t owner; 247 }; 248 249 /** 250 * struct dp_tx_ext_desc_elem_s 251 * @next: next extension descriptor pointer 252 * @vaddr: hlos virtual address pointer 253 * @paddr: physical address pointer for descriptor 254 */ 255 struct dp_tx_ext_desc_elem_s { 256 struct dp_tx_ext_desc_elem_s *next; 257 void *vaddr; 258 qdf_dma_addr_t paddr; 259 }; 260 261 /** 262 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 263 * @elem_count: Number of descriptors in the pool 264 * @elem_size: Size of each descriptor 265 * @num_free: Number of free descriptors 266 * @msdu_ext_desc: MSDU extension descriptor 267 * @desc_pages: multiple page allocation information for actual descriptors 268 * @link_elem_size: size of the link descriptor in cacheable memory used for 269 * chaining the extension descriptors 270 * @desc_link_pages: multiple page allocation information for link descriptors 271 */ 272 struct dp_tx_ext_desc_pool_s { 273 uint16_t elem_count; 274 int elem_size; 275 uint16_t num_free; 276 struct qdf_mem_multi_page_t desc_pages; 277 int link_elem_size; 278 struct qdf_mem_multi_page_t desc_link_pages; 279 struct dp_tx_ext_desc_elem_s *freelist; 280 qdf_spinlock_t lock; 281 qdf_dma_mem_context(memctx); 282 }; 283 284 /** 285 * struct dp_tx_desc_s - Tx Descriptor 286 * @next: Next in the chain of descriptors in freelist or in the completion list 287 * @nbuf: Buffer Address 288 * @msdu_ext_desc: MSDU extension descriptor 289 * @id: Descriptor ID 290 * @vdev: vdev over which the packet was transmitted 291 * @pdev: Handle to pdev 292 * @pool_id: Pool ID - used when releasing the descriptor 293 * @flags: Flags to track the state of descriptor and special frame handling 294 * @comp: Pool ID - used when releasing the descriptor 295 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 296 * This is maintained in descriptor to allow more efficient 297 * processing in completion event processing code. 298 * This field is filled in with the htt_pkt_type enum. 299 * @frm_type: Frame Type - ToDo check if this is redundant 300 * @pkt_offset: Offset from which the actual packet data starts 301 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 302 * Tx completion of ME packet 303 * @pool: handle to flow_pool this descriptor belongs to. 304 */ 305 struct dp_tx_desc_s { 306 struct dp_tx_desc_s *next; 307 qdf_nbuf_t nbuf; 308 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 309 uint32_t id; 310 struct dp_vdev *vdev; 311 struct dp_pdev *pdev; 312 uint8_t pool_id; 313 uint16_t flags; 314 struct hal_tx_desc_comp_s comp; 315 uint16_t tx_encap_type; 316 uint8_t frm_type; 317 uint8_t pkt_offset; 318 void *me_buffer; 319 void *tso_desc; 320 void *tso_num_desc; 321 uint64_t timestamp; 322 }; 323 324 /** 325 * enum flow_pool_status - flow pool status 326 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 327 * and network queues are unpaused 328 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 329 * and network queues are paused 330 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 331 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 332 */ 333 enum flow_pool_status { 334 FLOW_POOL_ACTIVE_UNPAUSED = 0, 335 FLOW_POOL_ACTIVE_PAUSED = 1, 336 FLOW_POOL_BE_BK_PAUSED = 2, 337 FLOW_POOL_VI_PAUSED = 3, 338 FLOW_POOL_VO_PAUSED = 4, 339 FLOW_POOL_INVALID = 5, 340 FLOW_POOL_INACTIVE = 6, 341 }; 342 343 /** 344 * struct dp_tx_tso_seg_pool_s 345 * @pool_size: total number of pool elements 346 * @num_free: free element count 347 * @freelist: first free element pointer 348 * @desc_pages: multiple page allocation information for actual descriptors 349 * @lock: lock for accessing the pool 350 */ 351 struct dp_tx_tso_seg_pool_s { 352 uint16_t pool_size; 353 uint16_t num_free; 354 struct qdf_tso_seg_elem_t *freelist; 355 struct qdf_mem_multi_page_t desc_pages; 356 qdf_spinlock_t lock; 357 }; 358 359 /** 360 * struct dp_tx_tso_num_seg_pool_s { 361 * @num_seg_pool_size: total number of pool elements 362 * @num_free: free element count 363 * @freelist: first free element pointer 364 * @desc_pages: multiple page allocation information for actual descriptors 365 * @lock: lock for accessing the pool 366 */ 367 368 struct dp_tx_tso_num_seg_pool_s { 369 uint16_t num_seg_pool_size; 370 uint16_t num_free; 371 struct qdf_tso_num_seg_elem_t *freelist; 372 struct qdf_mem_multi_page_t desc_pages; 373 /*tso mutex */ 374 qdf_spinlock_t lock; 375 }; 376 377 /** 378 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 379 * @elem_size: Size of each descriptor in the pool 380 * @pool_size: Total number of descriptors in the pool 381 * @num_free: Number of free descriptors 382 * @num_allocated: Number of used descriptors 383 * @freelist: Chain of free descriptors 384 * @desc_pages: multiple page allocation information for actual descriptors 385 * @num_invalid_bin: Deleted pool with pending Tx completions. 386 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 387 * @flow_pool_array: List of allocated flow pools 388 * @lock- Lock for descriptor allocation/free from/to the pool 389 */ 390 struct dp_tx_desc_pool_s { 391 uint16_t elem_size; 392 uint32_t num_allocated; 393 struct dp_tx_desc_s *freelist; 394 struct qdf_mem_multi_page_t desc_pages; 395 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 396 uint16_t pool_size; 397 uint8_t flow_pool_id; 398 uint8_t num_invalid_bin; 399 uint16_t avail_desc; 400 enum flow_pool_status status; 401 enum htt_flow_type flow_type; 402 #ifdef QCA_AC_BASED_FLOW_CONTROL 403 uint16_t stop_th[FL_TH_MAX]; 404 uint16_t start_th[FL_TH_MAX]; 405 qdf_time_t max_pause_time[FL_TH_MAX]; 406 qdf_time_t latest_pause_time[FL_TH_MAX]; 407 #else 408 uint16_t stop_th; 409 uint16_t start_th; 410 #endif 411 uint16_t pkt_drop_no_desc; 412 qdf_spinlock_t flow_pool_lock; 413 uint8_t pool_create_cnt; 414 void *pool_owner_ctx; 415 #else 416 uint16_t elem_count; 417 uint32_t num_free; 418 qdf_spinlock_t lock; 419 #endif 420 }; 421 422 /** 423 * struct dp_txrx_pool_stats - flow pool related statistics 424 * @pool_map_count: flow pool map received 425 * @pool_unmap_count: flow pool unmap received 426 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 427 */ 428 struct dp_txrx_pool_stats { 429 uint16_t pool_map_count; 430 uint16_t pool_unmap_count; 431 uint16_t pkt_drop_no_pool; 432 }; 433 434 struct dp_srng { 435 void *hal_srng; 436 void *base_vaddr_unaligned; 437 qdf_dma_addr_t base_paddr_unaligned; 438 uint32_t alloc_size; 439 int irq; 440 uint32_t num_entries; 441 }; 442 443 struct dp_rx_reorder_array_elem { 444 qdf_nbuf_t head; 445 qdf_nbuf_t tail; 446 }; 447 448 #define DP_RX_BA_INACTIVE 0 449 #define DP_RX_BA_ACTIVE 1 450 #define DP_RX_BA_IN_PROGRESS 2 451 struct dp_reo_cmd_info { 452 uint16_t cmd; 453 enum hal_reo_cmd_type cmd_type; 454 void *data; 455 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 456 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 457 }; 458 459 /* Rx TID */ 460 struct dp_rx_tid { 461 /* TID */ 462 int tid; 463 464 /* Num of addba requests */ 465 uint32_t num_of_addba_req; 466 467 /* Num of addba responses */ 468 uint32_t num_of_addba_resp; 469 470 /* Num of delba requests */ 471 uint32_t num_of_delba_req; 472 473 /* Num of addba responses successful */ 474 uint32_t num_addba_rsp_success; 475 476 /* Num of addba responses failed */ 477 uint32_t num_addba_rsp_failed; 478 479 /* pn size */ 480 uint8_t pn_size; 481 /* REO TID queue descriptors */ 482 void *hw_qdesc_vaddr_unaligned; 483 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 484 qdf_dma_addr_t hw_qdesc_paddr; 485 uint32_t hw_qdesc_alloc_size; 486 487 /* RX ADDBA session state */ 488 int ba_status; 489 490 /* RX BA window size */ 491 uint16_t ba_win_size; 492 493 /* Starting sequence number in Addba request */ 494 uint16_t startseqnum; 495 496 /* TODO: Check the following while adding defragmentation support */ 497 struct dp_rx_reorder_array_elem *array; 498 /* base - single rx reorder element used for non-aggr cases */ 499 struct dp_rx_reorder_array_elem base; 500 501 /* only used for defrag right now */ 502 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 503 504 /* Store dst desc for reinjection */ 505 void *dst_ring_desc; 506 struct dp_rx_desc *head_frag_desc; 507 508 /* rx_tid lock */ 509 qdf_spinlock_t tid_lock; 510 511 /* Sequence and fragments that are being processed currently */ 512 uint32_t curr_seq_num; 513 uint32_t curr_frag_num; 514 515 uint32_t defrag_timeout_ms; 516 uint16_t dialogtoken; 517 uint16_t statuscode; 518 /* user defined ADDBA response status code */ 519 uint16_t userstatuscode; 520 521 /* Store ppdu_id when 2k exception is received */ 522 uint32_t ppdu_id_2k; 523 524 /* Delba Tx completion status */ 525 uint8_t delba_tx_status; 526 527 /* Delba Tx retry count */ 528 uint8_t delba_tx_retry; 529 530 /* Delba stats */ 531 uint32_t delba_tx_success_cnt; 532 uint32_t delba_tx_fail_cnt; 533 534 /* Delba reason code for retries */ 535 uint8_t delba_rcode; 536 537 }; 538 539 /* per interrupt context */ 540 struct dp_intr { 541 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 542 associated with this napi context */ 543 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 544 with this interrupt context */ 545 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 546 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 547 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 548 uint8_t reo_status_ring_mask; /* REO command response ring */ 549 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 550 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 551 struct dp_soc *soc; /* Reference to SoC structure , 552 to get DMA ring handles */ 553 qdf_lro_ctx_t lro_ctx; 554 uint8_t dp_intr_id; 555 }; 556 557 #define REO_DESC_FREELIST_SIZE 64 558 #define REO_DESC_FREE_DEFER_MS 1000 559 struct reo_desc_list_node { 560 qdf_list_node_t node; 561 unsigned long free_ts; 562 struct dp_rx_tid rx_tid; 563 }; 564 565 /* SoC level data path statistics */ 566 struct dp_soc_stats { 567 struct { 568 uint32_t added; 569 uint32_t deleted; 570 uint32_t aged_out; 571 } ast; 572 573 /* SOC level TX stats */ 574 struct { 575 /* packets dropped on tx because of no peer */ 576 struct cdp_pkt_info tx_invalid_peer; 577 /* descriptors in each tcl ring */ 578 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 579 /* Descriptors in use at soc */ 580 uint32_t desc_in_use; 581 /* tqm_release_reason == FW removed */ 582 uint32_t dropped_fw_removed; 583 584 } tx; 585 586 /* SOC level RX stats */ 587 struct { 588 /* Rx errors */ 589 /* Total Packets in Rx Error ring */ 590 uint32_t err_ring_pkts; 591 /* No of Fragments */ 592 uint32_t rx_frags; 593 /* No of reinjected packets */ 594 uint32_t reo_reinject; 595 /* Head pointer Out of sync */ 596 uint32_t hp_oos; 597 struct { 598 /* Invalid RBM error count */ 599 uint32_t invalid_rbm; 600 /* Invalid VDEV Error count */ 601 uint32_t invalid_vdev; 602 /* Invalid PDEV error count */ 603 uint32_t invalid_pdev; 604 /* Invalid PEER Error count */ 605 struct cdp_pkt_info rx_invalid_peer; 606 /* HAL ring access Fail error count */ 607 uint32_t hal_ring_access_fail; 608 /* RX DMA error count */ 609 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 610 /* REO Error count */ 611 uint32_t reo_error[HAL_REO_ERR_MAX]; 612 /* HAL REO ERR Count */ 613 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 614 } err; 615 616 /* packet count per core - per ring */ 617 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 618 } rx; 619 }; 620 621 #define DP_MAC_ADDR_LEN 6 622 union dp_align_mac_addr { 623 uint8_t raw[DP_MAC_ADDR_LEN]; 624 struct { 625 uint16_t bytes_ab; 626 uint16_t bytes_cd; 627 uint16_t bytes_ef; 628 } align2; 629 struct { 630 uint32_t bytes_abcd; 631 uint16_t bytes_ef; 632 } align4; 633 struct __attribute__((__packed__)) { 634 uint16_t bytes_ab; 635 uint32_t bytes_cdef; 636 } align4_2; 637 }; 638 639 #define DP_INVALID_AST_IDX 0xFFFF 640 /* 641 * dp_ast_entry 642 * 643 * @ast_idx: Hardware AST Index 644 * @mac_addr: MAC Address for this AST entry 645 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 646 * associated peer with this MAC address) 647 * @next_hop: Set to 1 if this is for a WDS node 648 * @is_active: flag to indicate active data traffic on this node 649 * (used for aging out/expiry) 650 * @ase_list_elem: node in peer AST list 651 * @is_bss: flag to indicate if entry corresponds to bss peer 652 * @pdev_id: pdev ID 653 * @vdev_id: vdev ID 654 * @ast_hash_value: hast value in HW 655 * @ref_cnt: reference count 656 * @type: flag to indicate type of the entry(static/WDS/MEC) 657 * @wmi_sent: Flag to identify of WMI to del ast is sent (AST_HKV1_WORKAROUND) 658 * @cp_ctx: Opaque context used by control path (AST_HKV1_WORKAROUND) 659 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 660 */ 661 struct dp_ast_entry { 662 uint16_t ast_idx; 663 /* MAC address */ 664 union dp_align_mac_addr mac_addr; 665 struct dp_peer *peer; 666 bool next_hop; 667 bool is_active; 668 bool is_bss; 669 uint8_t pdev_id; 670 uint8_t vdev_id; 671 uint16_t ast_hash_value; 672 qdf_atomic_t ref_cnt; 673 enum cdp_txrx_ast_entry_type type; 674 #ifdef AST_HKV1_WORKAROUND 675 bool wmi_sent; 676 void *cp_ctx; 677 #endif 678 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 679 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 680 }; 681 682 /* SOC level htt stats */ 683 struct htt_t2h_stats { 684 /* lock to protect htt_stats_msg update */ 685 qdf_spinlock_t lock; 686 687 /* work queue to process htt stats */ 688 qdf_work_t work; 689 690 /* T2H Ext stats message queue */ 691 qdf_nbuf_queue_t msg; 692 693 /* number of completed stats in htt_stats_msg */ 694 uint32_t num_stats; 695 }; 696 697 /* SOC level structure for data path */ 698 struct dp_soc { 699 /* Common base structure - Should be the first member */ 700 struct cdp_soc_t cdp_soc; 701 702 /* SoC Obj */ 703 void *ctrl_psoc; 704 705 /* OS device abstraction */ 706 qdf_device_t osdev; 707 708 /* WLAN config context */ 709 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 710 711 /* HTT handle for host-fw interaction */ 712 void *htt_handle; 713 714 /* Commint init done */ 715 qdf_atomic_t cmn_init_done; 716 717 /* Opaque hif handle */ 718 struct hif_opaque_softc *hif_handle; 719 720 /* PDEVs on this SOC */ 721 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 722 723 /* Number of PDEVs */ 724 uint8_t pdev_count; 725 726 /*cce disable*/ 727 bool cce_disable; 728 729 /*ast override support in HW*/ 730 bool ast_override_support; 731 732 /*number of hw dscp tid map*/ 733 uint8_t num_hw_dscp_tid_map; 734 735 /* Link descriptor memory banks */ 736 struct { 737 void *base_vaddr_unaligned; 738 void *base_vaddr; 739 qdf_dma_addr_t base_paddr_unaligned; 740 qdf_dma_addr_t base_paddr; 741 uint32_t size; 742 } link_desc_banks[MAX_LINK_DESC_BANKS]; 743 744 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 745 struct dp_srng wbm_idle_link_ring; 746 747 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 748 */ 749 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 750 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 751 uint32_t wbm_idle_scatter_buf_size; 752 753 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 754 qdf_spinlock_t flow_pool_array_lock; 755 tx_pause_callback pause_cb; 756 struct dp_txrx_pool_stats pool_stats; 757 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 758 /* Tx SW descriptor pool */ 759 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 760 761 /* Tx MSDU Extension descriptor pool */ 762 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 763 764 /* Tx TSO descriptor pool */ 765 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 766 767 /* Tx TSO Num of segments pool */ 768 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 769 770 /* Tx H/W queues lock */ 771 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 772 773 /* Rx SW descriptor pool for RXDMA buffer */ 774 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 775 776 /* Rx SW descriptor pool for RXDMA monitor buffer */ 777 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 778 779 /* Rx SW descriptor pool for RXDMA status buffer */ 780 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 781 782 /* HAL SOC handle */ 783 void *hal_soc; 784 785 /* DP Interrupts */ 786 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 787 788 /* REO destination rings */ 789 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 790 791 /* Number of REO destination rings */ 792 uint8_t num_reo_dest_rings; 793 794 /* REO exception ring - See if should combine this with reo_dest_ring */ 795 struct dp_srng reo_exception_ring; 796 797 /* REO reinjection ring */ 798 struct dp_srng reo_reinject_ring; 799 800 /* REO command ring */ 801 struct dp_srng reo_cmd_ring; 802 803 /* REO command status ring */ 804 struct dp_srng reo_status_ring; 805 806 /* WBM Rx release ring */ 807 struct dp_srng rx_rel_ring; 808 809 /* Number of TCL data rings */ 810 uint8_t num_tcl_data_rings; 811 812 /* TCL data ring */ 813 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 814 815 /* TCL command ring */ 816 struct dp_srng tcl_cmd_ring; 817 818 /* TCL command status ring */ 819 struct dp_srng tcl_status_ring; 820 821 /* WBM Tx completion rings */ 822 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 823 824 /* Common WBM link descriptor release ring (SW to WBM) */ 825 struct dp_srng wbm_desc_rel_ring; 826 827 /* Tx ring map for interrupt processing */ 828 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 829 830 /* Rx ring map for interrupt processing */ 831 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 832 833 /* peer ID to peer object map (array of pointers to peer objects) */ 834 struct dp_peer **peer_id_to_obj_map; 835 836 struct { 837 unsigned mask; 838 unsigned idx_bits; 839 TAILQ_HEAD(, dp_peer) * bins; 840 } peer_hash; 841 842 /* rx defrag state – TBD: do we need this per radio? */ 843 struct { 844 struct { 845 TAILQ_HEAD(, dp_rx_tid) waitlist; 846 uint32_t timeout_ms; 847 qdf_spinlock_t defrag_lock; 848 } defrag; 849 struct { 850 int defrag_timeout_check; 851 int dup_check; 852 } flags; 853 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 854 qdf_spinlock_t reo_cmd_lock; 855 } rx; 856 857 /* optional rx processing function */ 858 void (*rx_opt_proc)( 859 struct dp_vdev *vdev, 860 struct dp_peer *peer, 861 unsigned tid, 862 qdf_nbuf_t msdu_list); 863 864 /* pool addr for mcast enhance buff */ 865 struct { 866 int size; 867 uint32_t paddr; 868 uint32_t *vaddr; 869 struct dp_tx_me_buf_t *freelist; 870 int buf_in_use; 871 qdf_dma_mem_context(memctx); 872 } me_buf; 873 874 /** 875 * peer ref mutex: 876 * 1. Protect peer object lookups until the returned peer object's 877 * reference count is incremented. 878 * 2. Provide mutex when accessing peer object lookup structures. 879 */ 880 DP_MUTEX_TYPE peer_ref_mutex; 881 882 /* maximum value for peer_id */ 883 uint32_t max_peers; 884 885 /* SoC level data path statistics */ 886 struct dp_soc_stats stats; 887 888 /* Enable processing of Tx completion status words */ 889 bool process_tx_status; 890 bool process_rx_status; 891 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 892 struct { 893 unsigned mask; 894 unsigned idx_bits; 895 TAILQ_HEAD(, dp_ast_entry) * bins; 896 } ast_hash; 897 898 qdf_spinlock_t ast_lock; 899 qdf_timer_t wds_aging_timer; 900 901 /*interrupt timer*/ 902 qdf_timer_t mon_reap_timer; 903 uint8_t reap_timer_init; 904 qdf_timer_t int_timer; 905 uint8_t intr_mode; 906 907 qdf_list_t reo_desc_freelist; 908 qdf_spinlock_t reo_desc_freelist_lock; 909 910 /* htt stats */ 911 struct htt_t2h_stats htt_stats; 912 913 void *external_txrx_handle; /* External data path handle */ 914 #ifdef IPA_OFFLOAD 915 /* IPA uC datapath offload Wlan Tx resources */ 916 struct { 917 /* Resource info to be passed to IPA */ 918 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 919 void *ipa_tcl_ring_base_vaddr; 920 uint32_t ipa_tcl_ring_size; 921 qdf_dma_addr_t ipa_tcl_hp_paddr; 922 uint32_t alloc_tx_buf_cnt; 923 924 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 925 void *ipa_wbm_ring_base_vaddr; 926 uint32_t ipa_wbm_ring_size; 927 qdf_dma_addr_t ipa_wbm_tp_paddr; 928 929 /* TX buffers populated into the WBM ring */ 930 void **tx_buf_pool_vaddr_unaligned; 931 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 932 } ipa_uc_tx_rsc; 933 934 /* IPA uC datapath offload Wlan Rx resources */ 935 struct { 936 /* Resource info to be passed to IPA */ 937 qdf_dma_addr_t ipa_reo_ring_base_paddr; 938 void *ipa_reo_ring_base_vaddr; 939 uint32_t ipa_reo_ring_size; 940 qdf_dma_addr_t ipa_reo_tp_paddr; 941 942 /* Resource info to be passed to firmware and IPA */ 943 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 944 void *ipa_rx_refill_buf_ring_base_vaddr; 945 uint32_t ipa_rx_refill_buf_ring_size; 946 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 947 } ipa_uc_rx_rsc; 948 #endif 949 /* Device ID coming from Bus sub-system */ 950 uint32_t device_id; 951 952 /* Smart monitor capability for HKv2 */ 953 uint8_t hw_nac_monitor_support; 954 /* Flag to indicate if HTT v2 is enabled*/ 955 bool is_peer_map_unmap_v2; 956 }; 957 958 #ifdef IPA_OFFLOAD 959 /** 960 * dp_ipa_resources - Resources needed for IPA 961 */ 962 struct dp_ipa_resources { 963 qdf_dma_addr_t tx_ring_base_paddr; 964 uint32_t tx_ring_size; 965 uint32_t tx_num_alloc_buffer; 966 967 qdf_dma_addr_t tx_comp_ring_base_paddr; 968 uint32_t tx_comp_ring_size; 969 970 qdf_dma_addr_t rx_rdy_ring_base_paddr; 971 uint32_t rx_rdy_ring_size; 972 973 qdf_dma_addr_t rx_refill_ring_base_paddr; 974 uint32_t rx_refill_ring_size; 975 976 /* IPA UC doorbell registers paddr */ 977 qdf_dma_addr_t tx_comp_doorbell_paddr; 978 uint32_t *tx_comp_doorbell_vaddr; 979 qdf_dma_addr_t rx_ready_doorbell_paddr; 980 }; 981 #endif 982 983 #define MAX_RX_MAC_RINGS 2 984 /* Same as NAC_MAX_CLENT */ 985 #define DP_NAC_MAX_CLIENT 24 986 987 /* 988 * Macros to setup link descriptor cookies - for link descriptors, we just 989 * need first 3 bits to store bank ID. The remaining bytes will be used set a 990 * unique ID, which will be useful in debugging 991 */ 992 #define LINK_DESC_BANK_ID_MASK 0x7 993 #define LINK_DESC_ID_SHIFT 3 994 #define LINK_DESC_ID_START 0x8000 995 996 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 997 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 998 999 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1000 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1001 1002 /* same as ieee80211_nac_param */ 1003 enum dp_nac_param_cmd { 1004 /* IEEE80211_NAC_PARAM_ADD */ 1005 DP_NAC_PARAM_ADD = 1, 1006 /* IEEE80211_NAC_PARAM_DEL */ 1007 DP_NAC_PARAM_DEL, 1008 /* IEEE80211_NAC_PARAM_LIST */ 1009 DP_NAC_PARAM_LIST, 1010 }; 1011 1012 /** 1013 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1014 * @neighbour_peers_macaddr: neighbour peer's mac address 1015 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1016 * @ast_entry: ast_entry for neighbour peer 1017 * @rssi: rssi value 1018 */ 1019 struct dp_neighbour_peer { 1020 /* MAC address of neighbour's peer */ 1021 union dp_align_mac_addr neighbour_peers_macaddr; 1022 struct dp_vdev *vdev; 1023 struct dp_ast_entry *ast_entry; 1024 uint8_t rssi; 1025 /* node in the list of neighbour's peer */ 1026 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1027 }; 1028 1029 /** 1030 * struct ppdu_info - PPDU Status info descriptor 1031 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1032 * @max_ppdu_id - wrap around for ppdu id 1033 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1034 * @last_user - last ppdu processed for user 1035 * @is_ampdu - set if Ampdu aggregate 1036 * @nbuf - ppdu descriptor payload 1037 * @ppdu_desc - ppdu descriptor 1038 * @ppdu_info_list_elem - linked list of ppdu tlvs 1039 */ 1040 struct ppdu_info { 1041 uint32_t ppdu_id; 1042 uint32_t max_ppdu_id; 1043 uint16_t tlv_bitmap; 1044 uint16_t last_tlv_cnt; 1045 uint16_t last_user:8, 1046 is_ampdu:1; 1047 qdf_nbuf_t nbuf; 1048 struct cdp_tx_completion_ppdu *ppdu_desc; 1049 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1050 }; 1051 1052 /* PDEV level structure for data path */ 1053 struct dp_pdev { 1054 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1055 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1056 1057 /* PDEV Id */ 1058 int pdev_id; 1059 1060 /* LMAC Id */ 1061 int lmac_id; 1062 1063 /* TXRX SOC handle */ 1064 struct dp_soc *soc; 1065 1066 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1067 struct dp_srng rx_refill_buf_ring; 1068 1069 /* Second ring used to replenish rx buffers */ 1070 struct dp_srng rx_refill_buf_ring2; 1071 1072 /* Empty ring used by firmware to post rx buffers to the MAC */ 1073 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1074 1075 /* wlan_cfg pdev ctxt*/ 1076 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1077 1078 /* RXDMA monitor buffer replenish ring */ 1079 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1080 1081 /* RXDMA monitor destination ring */ 1082 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1083 1084 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1085 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1086 1087 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1088 1089 /* RXDMA error destination ring */ 1090 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1091 1092 /* Link descriptor memory banks */ 1093 struct { 1094 void *base_vaddr_unaligned; 1095 void *base_vaddr; 1096 qdf_dma_addr_t base_paddr_unaligned; 1097 qdf_dma_addr_t base_paddr; 1098 uint32_t size; 1099 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1100 1101 1102 /** 1103 * TODO: See if we need a ring map here for LMAC rings. 1104 * 1. Monitor rings are currently planning to be processed on receiving 1105 * PPDU end interrupts and hence wont need ring based interrupts. 1106 * 2. Rx buffer rings will be replenished during REO destination 1107 * processing and doesn't require regular interrupt handling - we will 1108 * only handle low water mark interrupts which is not expected 1109 * frequently 1110 */ 1111 1112 /* VDEV list */ 1113 TAILQ_HEAD(, dp_vdev) vdev_list; 1114 1115 /* vdev list lock */ 1116 qdf_spinlock_t vdev_list_lock; 1117 1118 /* Number of vdevs this device have */ 1119 uint16_t vdev_count; 1120 1121 /* PDEV transmit lock */ 1122 qdf_spinlock_t tx_lock; 1123 1124 #ifndef REMOVE_PKT_LOG 1125 bool pkt_log_init; 1126 /* Pktlog pdev */ 1127 struct pktlog_dev_t *pl_dev; 1128 #endif /* #ifndef REMOVE_PKT_LOG */ 1129 1130 /* Monitor mode interface and status storage */ 1131 struct dp_vdev *monitor_vdev; 1132 1133 /* monitor mode lock */ 1134 qdf_spinlock_t mon_lock; 1135 1136 /*tx_mutex for me*/ 1137 DP_MUTEX_TYPE tx_mutex; 1138 1139 /* Smart Mesh */ 1140 bool filter_neighbour_peers; 1141 1142 /*flag to indicate neighbour_peers_list not empty */ 1143 bool neighbour_peers_added; 1144 /* smart mesh mutex */ 1145 qdf_spinlock_t neighbour_peer_mutex; 1146 /* Neighnour peer list */ 1147 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1148 /* msdu chain head & tail */ 1149 qdf_nbuf_t invalid_peer_head_msdu; 1150 qdf_nbuf_t invalid_peer_tail_msdu; 1151 1152 /* Band steering */ 1153 /* TBD */ 1154 1155 /* PDEV level data path statistics */ 1156 struct cdp_pdev_stats stats; 1157 1158 /* Global RX decap mode for the device */ 1159 enum htt_pkt_type rx_decap_mode; 1160 1161 /* Enhanced Stats is enabled */ 1162 bool enhanced_stats_en; 1163 1164 /* advance filter mode and type*/ 1165 uint8_t mon_filter_mode; 1166 uint16_t fp_mgmt_filter; 1167 uint16_t fp_ctrl_filter; 1168 uint16_t fp_data_filter; 1169 uint16_t mo_mgmt_filter; 1170 uint16_t mo_ctrl_filter; 1171 uint16_t mo_data_filter; 1172 uint16_t md_data_filter; 1173 1174 qdf_atomic_t num_tx_outstanding; 1175 1176 qdf_atomic_t num_tx_exception; 1177 1178 /* MCL specific local peer handle */ 1179 struct { 1180 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1181 uint8_t freelist; 1182 qdf_spinlock_t lock; 1183 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1184 } local_peer_ids; 1185 1186 /* dscp_tid_map_*/ 1187 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1188 1189 struct hal_rx_ppdu_info ppdu_info; 1190 1191 /* operating channel */ 1192 uint8_t operating_channel; 1193 1194 qdf_nbuf_queue_t rx_status_q; 1195 uint32_t mon_ppdu_status; 1196 struct cdp_mon_status rx_mon_recv_status; 1197 /* monitor mode status/destination ring PPDU and MPDU count */ 1198 struct cdp_pdev_mon_stats rx_mon_stats; 1199 1200 /* pool addr for mcast enhance buff */ 1201 struct { 1202 int size; 1203 uint32_t paddr; 1204 char *vaddr; 1205 struct dp_tx_me_buf_t *freelist; 1206 int buf_in_use; 1207 qdf_dma_mem_context(memctx); 1208 } me_buf; 1209 1210 /* Number of VAPs with mcast enhancement enabled */ 1211 qdf_atomic_t mc_num_vap_attached; 1212 1213 qdf_atomic_t stats_cmd_complete; 1214 1215 #ifdef IPA_OFFLOAD 1216 ipa_uc_op_cb_type ipa_uc_op_cb; 1217 void *usr_ctxt; 1218 struct dp_ipa_resources ipa_resource; 1219 #endif 1220 1221 /* TBD */ 1222 1223 /* map this pdev to a particular Reo Destination ring */ 1224 enum cdp_host_reo_dest_ring reo_dest; 1225 1226 #ifndef REMOVE_PKT_LOG 1227 /* Packet log mode */ 1228 uint8_t rx_pktlog_mode; 1229 #endif 1230 1231 /* WDI event handlers */ 1232 struct wdi_event_subscribe_t **wdi_event_list; 1233 1234 /* ppdu_id of last received HTT TX stats */ 1235 uint32_t last_ppdu_id; 1236 struct { 1237 uint8_t last_user; 1238 qdf_nbuf_t buf; 1239 } tx_ppdu_info; 1240 1241 bool tx_sniffer_enable; 1242 /* mirror copy mode */ 1243 bool mcopy_mode; 1244 bool bpr_enable; 1245 struct { 1246 uint16_t tx_ppdu_id; 1247 uint16_t tx_peer_id; 1248 uint16_t rx_ppdu_id; 1249 } m_copy_id; 1250 1251 /* To check if PPDU Tx stats are enabled for Pktlog */ 1252 bool pktlog_ppdu_stats; 1253 1254 void *dp_txrx_handle; /* Advanced data path handle */ 1255 1256 #ifdef ATH_SUPPORT_NAC_RSSI 1257 bool nac_rssi_filtering; 1258 #endif 1259 /* list of ppdu tlvs */ 1260 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1261 uint32_t tlv_count; 1262 uint32_t list_depth; 1263 uint32_t ppdu_id; 1264 bool first_nbuf; 1265 struct { 1266 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1267 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1268 uint32_t ppdu_id; 1269 } mgmtctrl_frm_info; 1270 1271 /* Current noise-floor reading for the pdev channel */ 1272 int16_t chan_noise_floor; 1273 1274 /* 1275 * For multiradio device, this flag indicates if 1276 * this radio is primary or secondary. 1277 * 1278 * For HK 1.0, this is used for WAR for the AST issue. 1279 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1280 * across 2 radios. is_primary indicates the radio on which DP should 1281 * install HW AST entry if there is a request to add 2 AST entries 1282 * with same MAC address across 2 radios 1283 */ 1284 uint8_t is_primary; 1285 /* Context of cal client timer */ 1286 void *cal_client_ctx; 1287 struct cdp_tx_sojourn_stats sojourn_stats; 1288 qdf_nbuf_t sojourn_buf; 1289 1290 }; 1291 1292 struct dp_peer; 1293 1294 /* VDEV structure for data path state */ 1295 struct dp_vdev { 1296 /* OS device abstraction */ 1297 qdf_device_t osdev; 1298 /* physical device that is the parent of this virtual device */ 1299 struct dp_pdev *pdev; 1300 1301 /* Handle to the OS shim SW's virtual device */ 1302 ol_osif_vdev_handle osif_vdev; 1303 1304 /* Handle to the UMAC handle */ 1305 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1306 /* vdev_id - ID used to specify a particular vdev to the target */ 1307 uint8_t vdev_id; 1308 1309 /* MAC address */ 1310 union dp_align_mac_addr mac_addr; 1311 1312 /* node in the pdev's list of vdevs */ 1313 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1314 1315 /* dp_peer list */ 1316 TAILQ_HEAD(, dp_peer) peer_list; 1317 1318 /* default RX call back function called by dp */ 1319 ol_txrx_rx_fp osif_rx; 1320 /* callback to deliver rx frames to the OS */ 1321 ol_txrx_rx_fp osif_rx_stack; 1322 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1323 ol_txrx_get_key_fp osif_get_key; 1324 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1325 1326 #ifdef notyet 1327 /* callback to check if the msdu is an WAI (WAPI) frame */ 1328 ol_rx_check_wai_fp osif_check_wai; 1329 #endif 1330 1331 /* proxy arp function */ 1332 ol_txrx_proxy_arp_fp osif_proxy_arp; 1333 1334 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1335 ol_txrx_rx_mon_fp osif_rx_mon; 1336 1337 ol_txrx_mcast_me_fp me_convert; 1338 1339 /* completion function used by this vdev*/ 1340 ol_txrx_completion_fp tx_comp; 1341 1342 /* deferred vdev deletion state */ 1343 struct { 1344 /* VDEV delete pending */ 1345 int pending; 1346 /* 1347 * callback and a context argument to provide a 1348 * notification for when the vdev is deleted. 1349 */ 1350 ol_txrx_vdev_delete_cb callback; 1351 void *context; 1352 } delete; 1353 1354 /* tx data delivery notification callback function */ 1355 struct { 1356 ol_txrx_data_tx_cb func; 1357 void *ctxt; 1358 } tx_non_std_data_callback; 1359 1360 1361 /* safe mode control to bypass the encrypt and decipher process*/ 1362 uint32_t safemode; 1363 1364 /* rx filter related */ 1365 uint32_t drop_unenc; 1366 #ifdef notyet 1367 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1368 uint32_t filters_num; 1369 #endif 1370 /* TDLS Link status */ 1371 bool tdls_link_connected; 1372 bool is_tdls_frame; 1373 1374 1375 /* VDEV operating mode */ 1376 enum wlan_op_mode opmode; 1377 1378 /* Tx encapsulation type for this VAP */ 1379 enum htt_cmn_pkt_type tx_encap_type; 1380 /* Rx Decapsulation type for this VAP */ 1381 enum htt_cmn_pkt_type rx_decap_type; 1382 1383 /* BSS peer */ 1384 struct dp_peer *vap_bss_peer; 1385 1386 /* WDS enabled */ 1387 bool wds_enabled; 1388 1389 /* WDS Aging timer period */ 1390 uint32_t wds_aging_timer_val; 1391 1392 /* NAWDS enabled */ 1393 bool nawds_enabled; 1394 1395 /* Default HTT meta data for this VDEV */ 1396 /* TBD: check alignment constraints */ 1397 uint16_t htt_tcl_metadata; 1398 1399 /* Mesh mode vdev */ 1400 uint32_t mesh_vdev; 1401 1402 /* Mesh mode rx filter setting */ 1403 uint32_t mesh_rx_filter; 1404 1405 /* DSCP-TID mapping table ID */ 1406 uint8_t dscp_tid_map_id; 1407 1408 /* Multicast enhancement enabled */ 1409 uint8_t mcast_enhancement_en; 1410 1411 /* per vdev rx nbuf queue */ 1412 qdf_nbuf_queue_t rxq; 1413 1414 uint8_t tx_ring_id; 1415 struct dp_tx_desc_pool_s *tx_desc; 1416 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1417 1418 /* VDEV Stats */ 1419 struct cdp_vdev_stats stats; 1420 bool lro_enable; 1421 1422 /* Is this a proxySTA VAP */ 1423 bool proxysta_vdev; 1424 /* Is isolation mode enabled */ 1425 bool isolation_vdev; 1426 1427 /* Address search flags to be configured in HAL descriptor */ 1428 uint8_t hal_desc_addr_search_flags; 1429 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1430 struct dp_tx_desc_pool_s *pool; 1431 #endif 1432 /* AP BRIDGE enabled */ 1433 uint32_t ap_bridge_enabled; 1434 1435 enum cdp_sec_type sec_type; 1436 1437 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1438 bool raw_mode_war; 1439 1440 /* Address search type to be set in TX descriptor */ 1441 uint8_t search_type; 1442 1443 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1444 uint16_t bss_ast_hash; 1445 }; 1446 1447 1448 enum { 1449 dp_sec_mcast = 0, 1450 dp_sec_ucast 1451 }; 1452 1453 #ifdef WDS_VENDOR_EXTENSION 1454 typedef struct { 1455 uint8_t wds_tx_mcast_4addr:1, 1456 wds_tx_ucast_4addr:1, 1457 wds_rx_filter:1, /* enforce rx filter */ 1458 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1459 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1460 1461 } dp_ecm_policy; 1462 #endif 1463 1464 /* Peer structure for data path state */ 1465 struct dp_peer { 1466 /* VDEV to which this peer is associated */ 1467 struct dp_vdev *vdev; 1468 1469 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1470 1471 struct dp_ast_entry *self_ast_entry; 1472 1473 qdf_atomic_t ref_cnt; 1474 1475 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1476 /* peer ID(s) for this peer */ 1477 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1478 1479 union dp_align_mac_addr mac_addr; 1480 1481 /* node in the vdev's list of peers */ 1482 TAILQ_ENTRY(dp_peer) peer_list_elem; 1483 /* node in the hash table bin's list of peers */ 1484 TAILQ_ENTRY(dp_peer) hash_list_elem; 1485 1486 /* TID structures */ 1487 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1488 1489 /* TBD: No transmit TID state required? */ 1490 1491 struct { 1492 enum cdp_sec_type sec_type; 1493 u_int32_t michael_key[2]; /* relevant for TKIP */ 1494 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1495 1496 /* 1497 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1498 * regular rx processing, or has been redirected to a /dev/null discard 1499 * function when peer deletion is in progress. 1500 */ 1501 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1502 unsigned tid, qdf_nbuf_t msdu_list); 1503 1504 /* set when node is authorized */ 1505 uint8_t authorize:1; 1506 1507 u_int8_t nac; 1508 1509 /* Band steering: Set when node is inactive */ 1510 uint8_t peer_bs_inact_flag:1; 1511 u_int16_t peer_bs_inact; /* inactivity mark count */ 1512 1513 /* NAWDS Flag and Bss Peer bit */ 1514 uint8_t nawds_enabled:1, 1515 bss_peer:1, 1516 wapi:1, 1517 wds_enabled:1; 1518 1519 /* MCL specific peer local id */ 1520 uint16_t local_id; 1521 enum ol_txrx_peer_state state; 1522 qdf_spinlock_t peer_info_lock; 1523 1524 qdf_time_t last_assoc_rcvd; 1525 qdf_time_t last_disassoc_rcvd; 1526 qdf_time_t last_deauth_rcvd; 1527 /* Peer Stats */ 1528 struct cdp_peer_stats stats; 1529 1530 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1531 /* TBD */ 1532 1533 #ifdef WDS_VENDOR_EXTENSION 1534 dp_ecm_policy wds_ecm; 1535 #endif 1536 bool delete_in_progress; 1537 1538 /* Active Block ack sessions */ 1539 uint16_t active_ba_session_cnt; 1540 1541 /* Current HW buffersize setting */ 1542 uint16_t hw_buffer_size; 1543 1544 /* 1545 * Flag to check if sessions with 256 buffersize 1546 * should be terminated. 1547 */ 1548 uint8_t kill_256_sessions; 1549 qdf_atomic_t is_default_route_set; 1550 }; 1551 1552 #ifdef CONFIG_WIN 1553 /* 1554 * dp_invalid_peer_msg 1555 * @nbuf: data buffer 1556 * @wh: 802.11 header 1557 * @vdev_id: id of vdev 1558 */ 1559 struct dp_invalid_peer_msg { 1560 qdf_nbuf_t nbuf; 1561 struct ieee80211_frame *wh; 1562 uint8_t vdev_id; 1563 }; 1564 #endif 1565 1566 /* 1567 * dp_tx_me_buf_t: ME buffer 1568 * next: pointer to next buffer 1569 * data: Destination Mac address 1570 */ 1571 struct dp_tx_me_buf_t { 1572 /* Note: ME buf pool initialization logic expects next pointer to 1573 * be the first element. Dont add anything before next */ 1574 struct dp_tx_me_buf_t *next; 1575 uint8_t data[DP_MAC_ADDR_LEN]; 1576 }; 1577 1578 #endif /* _DP_TYPES_H_ */ 1579