1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 64 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 65 #define DSCP_TID_MAP_MAX (64) 66 #define DP_IP_DSCP_SHIFT 2 67 #define DP_IP_DSCP_MASK 0x3f 68 #define DP_FC0_SUBTYPE_QOS 0x80 69 #define DP_QOS_TID 0x0f 70 #define DP_IPV6_PRIORITY_SHIFT 20 71 #define MAX_MON_LINK_DESC_BANKS 2 72 #define DP_VDEV_ALL 0xff 73 74 #if defined(CONFIG_MCL) 75 #define MAX_PDEV_CNT 1 76 #else 77 #define MAX_PDEV_CNT 3 78 #endif 79 80 #define MAX_LINK_DESC_BANKS 8 81 #define MAX_TXDESC_POOLS 4 82 #define MAX_RXDESC_POOLS 4 83 #define MAX_REO_DEST_RINGS 4 84 #define MAX_TCL_DATA_RINGS 4 85 #define MAX_IDLE_SCATTER_BUFS 16 86 #define DP_MAX_IRQ_PER_CONTEXT 12 87 #define DEFAULT_HW_PEER_ID 0xffff 88 89 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 90 91 92 /* Maximum retries for Delba per tid per peer */ 93 #define DP_MAX_DELBA_RETRY 3 94 95 #ifndef REMOVE_PKT_LOG 96 enum rx_pktlog_mode { 97 DP_RX_PKTLOG_DISABLED = 0, 98 DP_RX_PKTLOG_FULL, 99 DP_RX_PKTLOG_LITE, 100 }; 101 #endif 102 103 struct dp_soc_cmn; 104 struct dp_pdev; 105 struct dp_vdev; 106 struct dp_tx_desc_s; 107 struct dp_soc; 108 union dp_rx_desc_list_elem_t; 109 110 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 111 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 112 113 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 114 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 115 116 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 117 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 118 119 #define DP_MUTEX_TYPE qdf_spinlock_t 120 121 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 122 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 123 124 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 125 ((_a)[0] == 0x33 && \ 126 (_a)[1] == 0x33) 127 128 #define DP_FRAME_IS_BROADCAST(_a) \ 129 ((_a)[0] == 0xff && \ 130 (_a)[1] == 0xff && \ 131 (_a)[2] == 0xff && \ 132 (_a)[3] == 0xff && \ 133 (_a)[4] == 0xff && \ 134 (_a)[5] == 0xff) 135 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 136 (_llc)->llc_ssap == 0xaa && \ 137 (_llc)->llc_un.type_snap.control == 0x3) 138 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 139 #define DP_FRAME_FC0_TYPE_MASK 0x0c 140 #define DP_FRAME_FC0_TYPE_DATA 0x08 141 #define DP_FRAME_IS_DATA(_frame) \ 142 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 143 144 /** 145 * macros to convert hw mac id to sw mac id: 146 * mac ids used by hardware start from a value of 1 while 147 * those in host software start from a value of 0. Use the 148 * macros below to convert between mac ids used by software and 149 * hardware 150 */ 151 #define DP_SW2HW_MACID(id) ((id) + 1) 152 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 153 #define DP_MAC_ADDR_LEN 6 154 155 /** 156 * Number of Tx Queues 157 * enum and macro to define how many threshold levels is used 158 * for the AC based flow control 159 */ 160 #ifdef QCA_AC_BASED_FLOW_CONTROL 161 enum dp_fl_ctrl_threshold { 162 DP_TH_BE_BK = 0, 163 DP_TH_VI, 164 DP_TH_VO, 165 DP_TH_HI, 166 }; 167 168 #define FL_TH_MAX (4) 169 #define FL_TH_VI_PERCENTAGE (80) 170 #define FL_TH_VO_PERCENTAGE (60) 171 #define FL_TH_HI_PERCENTAGE (40) 172 #endif 173 174 /** 175 * enum dp_intr_mode 176 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 177 * @DP_INTR_MSI: MSI interrupts, for MCL 178 * @DP_INTR_POLL: Polling 179 */ 180 enum dp_intr_mode { 181 DP_INTR_LEGACY = 0, 182 DP_INTR_MSI, 183 DP_INTR_POLL, 184 }; 185 186 /** 187 * enum dp_tx_frm_type 188 * @dp_tx_frm_std: Regular frame, no added header fragments 189 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 190 * @dp_tx_frm_sg: SG segment 191 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 192 * @dp_tx_frm_me: Multicast to Unicast Converted frame 193 * @dp_tx_frm_raw: Raw Frame 194 */ 195 enum dp_tx_frm_type { 196 dp_tx_frm_std = 0, 197 dp_tx_frm_tso, 198 dp_tx_frm_sg, 199 dp_tx_frm_audio, 200 dp_tx_frm_me, 201 dp_tx_frm_raw, 202 }; 203 204 /** 205 * enum dp_ast_type 206 * @dp_ast_type_wds: WDS peer AST type 207 * @dp_ast_type_static: static ast entry type 208 * @dp_ast_type_mec: Multicast echo ast entry type 209 */ 210 enum dp_ast_type { 211 dp_ast_type_wds = 0, 212 dp_ast_type_static, 213 dp_ast_type_mec, 214 }; 215 216 /** 217 * enum dp_nss_cfg 218 * @dp_nss_cfg_default: No radios are offloaded 219 * @dp_nss_cfg_first_radio: First radio offloaded 220 * @dp_nss_cfg_second_radio: Second radio offloaded 221 * @dp_nss_cfg_dbdc: Dual radios offloaded 222 * @dp_nss_cfg_dbtc: Three radios offloaded 223 */ 224 enum dp_nss_cfg { 225 dp_nss_cfg_default = 0x0, 226 dp_nss_cfg_first_radio = 0x1, 227 dp_nss_cfg_second_radio = 0x2, 228 dp_nss_cfg_dbdc = 0x3, 229 dp_nss_cfg_dbtc = 0x7, 230 dp_nss_cfg_max 231 }; 232 233 /** 234 * struct rx_desc_pool 235 * @pool_size: number of RX descriptor in the pool 236 * @array: pointer to array of RX descriptor 237 * @freelist: pointer to free RX descriptor link list 238 * @lock: Protection for the RX descriptor pool 239 * @owner: owner for nbuf 240 */ 241 struct rx_desc_pool { 242 uint32_t pool_size; 243 union dp_rx_desc_list_elem_t *array; 244 union dp_rx_desc_list_elem_t *freelist; 245 qdf_spinlock_t lock; 246 uint8_t owner; 247 }; 248 249 /** 250 * struct dp_tx_ext_desc_elem_s 251 * @next: next extension descriptor pointer 252 * @vaddr: hlos virtual address pointer 253 * @paddr: physical address pointer for descriptor 254 */ 255 struct dp_tx_ext_desc_elem_s { 256 struct dp_tx_ext_desc_elem_s *next; 257 void *vaddr; 258 qdf_dma_addr_t paddr; 259 }; 260 261 /** 262 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 263 * @elem_count: Number of descriptors in the pool 264 * @elem_size: Size of each descriptor 265 * @num_free: Number of free descriptors 266 * @msdu_ext_desc: MSDU extension descriptor 267 * @desc_pages: multiple page allocation information for actual descriptors 268 * @link_elem_size: size of the link descriptor in cacheable memory used for 269 * chaining the extension descriptors 270 * @desc_link_pages: multiple page allocation information for link descriptors 271 */ 272 struct dp_tx_ext_desc_pool_s { 273 uint16_t elem_count; 274 int elem_size; 275 uint16_t num_free; 276 struct qdf_mem_multi_page_t desc_pages; 277 int link_elem_size; 278 struct qdf_mem_multi_page_t desc_link_pages; 279 struct dp_tx_ext_desc_elem_s *freelist; 280 qdf_spinlock_t lock; 281 qdf_dma_mem_context(memctx); 282 }; 283 284 /** 285 * struct dp_tx_desc_s - Tx Descriptor 286 * @next: Next in the chain of descriptors in freelist or in the completion list 287 * @nbuf: Buffer Address 288 * @msdu_ext_desc: MSDU extension descriptor 289 * @id: Descriptor ID 290 * @vdev: vdev over which the packet was transmitted 291 * @pdev: Handle to pdev 292 * @pool_id: Pool ID - used when releasing the descriptor 293 * @flags: Flags to track the state of descriptor and special frame handling 294 * @comp: Pool ID - used when releasing the descriptor 295 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 296 * This is maintained in descriptor to allow more efficient 297 * processing in completion event processing code. 298 * This field is filled in with the htt_pkt_type enum. 299 * @frm_type: Frame Type - ToDo check if this is redundant 300 * @pkt_offset: Offset from which the actual packet data starts 301 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 302 * Tx completion of ME packet 303 * @pool: handle to flow_pool this descriptor belongs to. 304 */ 305 struct dp_tx_desc_s { 306 struct dp_tx_desc_s *next; 307 qdf_nbuf_t nbuf; 308 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 309 uint32_t id; 310 struct dp_vdev *vdev; 311 struct dp_pdev *pdev; 312 uint8_t pool_id; 313 uint16_t flags; 314 struct hal_tx_desc_comp_s comp; 315 uint16_t tx_encap_type; 316 uint8_t frm_type; 317 uint8_t pkt_offset; 318 void *me_buffer; 319 void *tso_desc; 320 void *tso_num_desc; 321 uint64_t timestamp; 322 }; 323 324 /** 325 * enum flow_pool_status - flow pool status 326 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 327 * and network queues are unpaused 328 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 329 * and network queues are paused 330 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 331 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 332 */ 333 enum flow_pool_status { 334 FLOW_POOL_ACTIVE_UNPAUSED = 0, 335 FLOW_POOL_ACTIVE_PAUSED = 1, 336 FLOW_POOL_BE_BK_PAUSED = 2, 337 FLOW_POOL_VI_PAUSED = 3, 338 FLOW_POOL_VO_PAUSED = 4, 339 FLOW_POOL_INVALID = 5, 340 FLOW_POOL_INACTIVE = 6, 341 }; 342 343 /** 344 * struct dp_tx_tso_seg_pool_s 345 * @pool_size: total number of pool elements 346 * @num_free: free element count 347 * @freelist: first free element pointer 348 * @desc_pages: multiple page allocation information for actual descriptors 349 * @lock: lock for accessing the pool 350 */ 351 struct dp_tx_tso_seg_pool_s { 352 uint16_t pool_size; 353 uint16_t num_free; 354 struct qdf_tso_seg_elem_t *freelist; 355 struct qdf_mem_multi_page_t desc_pages; 356 qdf_spinlock_t lock; 357 }; 358 359 /** 360 * struct dp_tx_tso_num_seg_pool_s { 361 * @num_seg_pool_size: total number of pool elements 362 * @num_free: free element count 363 * @freelist: first free element pointer 364 * @desc_pages: multiple page allocation information for actual descriptors 365 * @lock: lock for accessing the pool 366 */ 367 368 struct dp_tx_tso_num_seg_pool_s { 369 uint16_t num_seg_pool_size; 370 uint16_t num_free; 371 struct qdf_tso_num_seg_elem_t *freelist; 372 struct qdf_mem_multi_page_t desc_pages; 373 /*tso mutex */ 374 qdf_spinlock_t lock; 375 }; 376 377 /** 378 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 379 * @elem_size: Size of each descriptor in the pool 380 * @pool_size: Total number of descriptors in the pool 381 * @num_free: Number of free descriptors 382 * @num_allocated: Number of used descriptors 383 * @freelist: Chain of free descriptors 384 * @desc_pages: multiple page allocation information for actual descriptors 385 * @num_invalid_bin: Deleted pool with pending Tx completions. 386 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 387 * @flow_pool_array: List of allocated flow pools 388 * @lock- Lock for descriptor allocation/free from/to the pool 389 */ 390 struct dp_tx_desc_pool_s { 391 uint16_t elem_size; 392 uint32_t num_allocated; 393 struct dp_tx_desc_s *freelist; 394 struct qdf_mem_multi_page_t desc_pages; 395 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 396 uint16_t pool_size; 397 uint8_t flow_pool_id; 398 uint8_t num_invalid_bin; 399 uint16_t avail_desc; 400 enum flow_pool_status status; 401 enum htt_flow_type flow_type; 402 #ifdef QCA_AC_BASED_FLOW_CONTROL 403 uint16_t stop_th[FL_TH_MAX]; 404 uint16_t start_th[FL_TH_MAX]; 405 qdf_time_t max_pause_time[FL_TH_MAX]; 406 qdf_time_t latest_pause_time[FL_TH_MAX]; 407 #else 408 uint16_t stop_th; 409 uint16_t start_th; 410 #endif 411 uint16_t pkt_drop_no_desc; 412 qdf_spinlock_t flow_pool_lock; 413 uint8_t pool_create_cnt; 414 void *pool_owner_ctx; 415 #else 416 uint16_t elem_count; 417 uint32_t num_free; 418 qdf_spinlock_t lock; 419 #endif 420 }; 421 422 /** 423 * struct dp_txrx_pool_stats - flow pool related statistics 424 * @pool_map_count: flow pool map received 425 * @pool_unmap_count: flow pool unmap received 426 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 427 */ 428 struct dp_txrx_pool_stats { 429 uint16_t pool_map_count; 430 uint16_t pool_unmap_count; 431 uint16_t pkt_drop_no_pool; 432 }; 433 434 struct dp_srng { 435 void *hal_srng; 436 void *base_vaddr_unaligned; 437 qdf_dma_addr_t base_paddr_unaligned; 438 uint32_t alloc_size; 439 int irq; 440 uint32_t num_entries; 441 }; 442 443 struct dp_rx_reorder_array_elem { 444 qdf_nbuf_t head; 445 qdf_nbuf_t tail; 446 }; 447 448 #define DP_RX_BA_INACTIVE 0 449 #define DP_RX_BA_ACTIVE 1 450 #define DP_RX_BA_IN_PROGRESS 2 451 struct dp_reo_cmd_info { 452 uint16_t cmd; 453 enum hal_reo_cmd_type cmd_type; 454 void *data; 455 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 456 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 457 }; 458 459 /* Rx TID */ 460 struct dp_rx_tid { 461 /* TID */ 462 int tid; 463 464 /* Num of addba requests */ 465 uint32_t num_of_addba_req; 466 467 /* Num of addba responses */ 468 uint32_t num_of_addba_resp; 469 470 /* Num of delba requests */ 471 uint32_t num_of_delba_req; 472 473 /* Num of addba responses successful */ 474 uint32_t num_addba_rsp_success; 475 476 /* Num of addba responses failed */ 477 uint32_t num_addba_rsp_failed; 478 479 /* pn size */ 480 uint8_t pn_size; 481 /* REO TID queue descriptors */ 482 void *hw_qdesc_vaddr_unaligned; 483 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 484 qdf_dma_addr_t hw_qdesc_paddr; 485 uint32_t hw_qdesc_alloc_size; 486 487 /* RX ADDBA session state */ 488 int ba_status; 489 490 /* RX BA window size */ 491 uint16_t ba_win_size; 492 493 /* Starting sequence number in Addba request */ 494 uint16_t startseqnum; 495 496 /* TODO: Check the following while adding defragmentation support */ 497 struct dp_rx_reorder_array_elem *array; 498 /* base - single rx reorder element used for non-aggr cases */ 499 struct dp_rx_reorder_array_elem base; 500 501 /* only used for defrag right now */ 502 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 503 504 /* Store dst desc for reinjection */ 505 void *dst_ring_desc; 506 struct dp_rx_desc *head_frag_desc; 507 508 /* rx_tid lock */ 509 qdf_spinlock_t tid_lock; 510 511 /* Sequence and fragments that are being processed currently */ 512 uint32_t curr_seq_num; 513 uint32_t curr_frag_num; 514 515 uint32_t defrag_timeout_ms; 516 uint16_t dialogtoken; 517 uint16_t statuscode; 518 /* user defined ADDBA response status code */ 519 uint16_t userstatuscode; 520 521 /* Store ppdu_id when 2k exception is received */ 522 uint32_t ppdu_id_2k; 523 524 /* Delba Tx completion status */ 525 uint8_t delba_tx_status; 526 527 /* Delba Tx retry count */ 528 uint8_t delba_tx_retry; 529 530 /* Delba stats */ 531 uint32_t delba_tx_success_cnt; 532 uint32_t delba_tx_fail_cnt; 533 534 /* Delba reason code for retries */ 535 uint8_t delba_rcode; 536 537 }; 538 539 /* per interrupt context */ 540 struct dp_intr { 541 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 542 associated with this napi context */ 543 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 544 with this interrupt context */ 545 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 546 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 547 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 548 uint8_t reo_status_ring_mask; /* REO command response ring */ 549 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 550 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 551 /* Host to RXDMA monitor buffer ring */ 552 uint8_t host2rxdma_mon_ring_mask; 553 struct dp_soc *soc; /* Reference to SoC structure , 554 to get DMA ring handles */ 555 qdf_lro_ctx_t lro_ctx; 556 uint8_t dp_intr_id; 557 }; 558 559 #define REO_DESC_FREELIST_SIZE 64 560 #define REO_DESC_FREE_DEFER_MS 1000 561 struct reo_desc_list_node { 562 qdf_list_node_t node; 563 unsigned long free_ts; 564 struct dp_rx_tid rx_tid; 565 }; 566 567 /* SoC level data path statistics */ 568 struct dp_soc_stats { 569 struct { 570 uint32_t added; 571 uint32_t deleted; 572 uint32_t aged_out; 573 } ast; 574 575 /* SOC level TX stats */ 576 struct { 577 /* packets dropped on tx because of no peer */ 578 struct cdp_pkt_info tx_invalid_peer; 579 /* descriptors in each tcl ring */ 580 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 581 /* Descriptors in use at soc */ 582 uint32_t desc_in_use; 583 /* tqm_release_reason == FW removed */ 584 uint32_t dropped_fw_removed; 585 586 } tx; 587 588 /* SOC level RX stats */ 589 struct { 590 /* Rx errors */ 591 /* Total Packets in Rx Error ring */ 592 uint32_t err_ring_pkts; 593 /* No of Fragments */ 594 uint32_t rx_frags; 595 /* No of incomplete fragments in waitlist */ 596 uint32_t rx_frag_wait; 597 /* Fragments dropped due to errors */ 598 uint32_t rx_frag_err; 599 /* No of reinjected packets */ 600 uint32_t reo_reinject; 601 /* Head pointer Out of sync */ 602 uint32_t hp_oos; 603 struct { 604 /* Invalid RBM error count */ 605 uint32_t invalid_rbm; 606 /* Invalid VDEV Error count */ 607 uint32_t invalid_vdev; 608 /* Invalid PDEV error count */ 609 uint32_t invalid_pdev; 610 /* Invalid PEER Error count */ 611 struct cdp_pkt_info rx_invalid_peer; 612 /* HAL ring access Fail error count */ 613 uint32_t hal_ring_access_fail; 614 /* RX DMA error count */ 615 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 616 /* REO Error count */ 617 uint32_t reo_error[HAL_REO_ERR_MAX]; 618 /* HAL REO ERR Count */ 619 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 620 /* HAL REO DEST Duplicate count */ 621 uint32_t hal_reo_dest_dup; 622 /* HAL WBM RELEASE Duplicate count */ 623 uint32_t hal_wbm_rel_dup; 624 } err; 625 626 /* packet count per core - per ring */ 627 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 628 } rx; 629 }; 630 631 #define DP_MAC_ADDR_LEN 6 632 union dp_align_mac_addr { 633 uint8_t raw[DP_MAC_ADDR_LEN]; 634 struct { 635 uint16_t bytes_ab; 636 uint16_t bytes_cd; 637 uint16_t bytes_ef; 638 } align2; 639 struct { 640 uint32_t bytes_abcd; 641 uint16_t bytes_ef; 642 } align4; 643 struct __attribute__((__packed__)) { 644 uint16_t bytes_ab; 645 uint32_t bytes_cdef; 646 } align4_2; 647 }; 648 649 /** 650 * struct dp_ast_free_cb_params - HMWDS free callback cookie 651 * @mac_addr: ast mac address 652 * @peer_mac_addr: mac address of peer 653 * @type: ast entry type 654 * @vdev_id: vdev_id 655 * @flags: ast flags 656 */ 657 struct dp_ast_free_cb_params { 658 union dp_align_mac_addr mac_addr; 659 union dp_align_mac_addr peer_mac_addr; 660 enum cdp_txrx_ast_entry_type type; 661 uint8_t vdev_id; 662 uint32_t flags; 663 }; 664 665 /* 666 * dp_ast_entry 667 * 668 * @ast_idx: Hardware AST Index 669 * @mac_addr: MAC Address for this AST entry 670 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 671 * associated peer with this MAC address) 672 * @next_hop: Set to 1 if this is for a WDS node 673 * @is_active: flag to indicate active data traffic on this node 674 * (used for aging out/expiry) 675 * @ase_list_elem: node in peer AST list 676 * @is_bss: flag to indicate if entry corresponds to bss peer 677 * @is_mapped: flag to indicate that we have mapped the AST entry 678 * in ast_table 679 * @pdev_id: pdev ID 680 * @vdev_id: vdev ID 681 * @ast_hash_value: hast value in HW 682 * @ref_cnt: reference count 683 * @type: flag to indicate type of the entry(static/WDS/MEC) 684 * @delete_in_progress: Flag to indicate that delete commands send to FW 685 * and host is waiting for response from FW 686 * @callback: ast free/unmap callback 687 * @cookie: argument to callback 688 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 689 */ 690 struct dp_ast_entry { 691 uint16_t ast_idx; 692 union dp_align_mac_addr mac_addr; 693 struct dp_peer *peer; 694 bool next_hop; 695 bool is_active; 696 bool is_bss; 697 bool is_mapped; 698 uint8_t pdev_id; 699 uint8_t vdev_id; 700 uint16_t ast_hash_value; 701 qdf_atomic_t ref_cnt; 702 enum cdp_txrx_ast_entry_type type; 703 bool delete_in_progress; 704 txrx_ast_free_cb callback; 705 void *cookie; 706 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 707 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 708 }; 709 710 /* SOC level htt stats */ 711 struct htt_t2h_stats { 712 /* lock to protect htt_stats_msg update */ 713 qdf_spinlock_t lock; 714 715 /* work queue to process htt stats */ 716 qdf_work_t work; 717 718 /* T2H Ext stats message queue */ 719 qdf_nbuf_queue_t msg; 720 721 /* number of completed stats in htt_stats_msg */ 722 uint32_t num_stats; 723 }; 724 725 /* SOC level structure for data path */ 726 struct dp_soc { 727 /** 728 * re-use memory section starts 729 */ 730 731 /* Common base structure - Should be the first member */ 732 struct cdp_soc_t cdp_soc; 733 734 /* SoC Obj */ 735 void *ctrl_psoc; 736 737 /* OS device abstraction */ 738 qdf_device_t osdev; 739 740 /* WLAN config context */ 741 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 742 743 /* HTT handle for host-fw interaction */ 744 void *htt_handle; 745 746 /* Commint init done */ 747 qdf_atomic_t cmn_init_done; 748 749 /* Opaque hif handle */ 750 struct hif_opaque_softc *hif_handle; 751 752 /* PDEVs on this SOC */ 753 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 754 755 /* Number of PDEVs */ 756 uint8_t pdev_count; 757 758 /*cce disable*/ 759 bool cce_disable; 760 761 /*ast override support in HW*/ 762 bool ast_override_support; 763 764 /*number of hw dscp tid map*/ 765 uint8_t num_hw_dscp_tid_map; 766 767 /* HAL SOC handle */ 768 void *hal_soc; 769 770 /* Device ID coming from Bus sub-system */ 771 uint32_t device_id; 772 773 /* Link descriptor memory banks */ 774 struct { 775 void *base_vaddr_unaligned; 776 void *base_vaddr; 777 qdf_dma_addr_t base_paddr_unaligned; 778 qdf_dma_addr_t base_paddr; 779 uint32_t size; 780 } link_desc_banks[MAX_LINK_DESC_BANKS]; 781 782 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 783 struct dp_srng wbm_idle_link_ring; 784 785 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 786 */ 787 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 788 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 789 790 /* Tx SW descriptor pool */ 791 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 792 793 /* Tx MSDU Extension descriptor pool */ 794 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 795 796 /* Tx TSO descriptor pool */ 797 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 798 799 /* Tx TSO Num of segments pool */ 800 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 801 802 /* REO destination rings */ 803 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 804 805 /* REO exception ring - See if should combine this with reo_dest_ring */ 806 struct dp_srng reo_exception_ring; 807 808 /* REO reinjection ring */ 809 struct dp_srng reo_reinject_ring; 810 811 /* REO command ring */ 812 struct dp_srng reo_cmd_ring; 813 814 /* REO command status ring */ 815 struct dp_srng reo_status_ring; 816 817 /* WBM Rx release ring */ 818 struct dp_srng rx_rel_ring; 819 820 /* TCL data ring */ 821 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 822 823 /* Number of TCL data rings */ 824 uint8_t num_tcl_data_rings; 825 826 /* TCL command ring */ 827 struct dp_srng tcl_cmd_ring; 828 829 /* TCL command status ring */ 830 struct dp_srng tcl_status_ring; 831 832 /* WBM Tx completion rings */ 833 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 834 835 /* Common WBM link descriptor release ring (SW to WBM) */ 836 struct dp_srng wbm_desc_rel_ring; 837 838 /* DP Interrupts */ 839 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 840 841 /* Rx SW descriptor pool for RXDMA monitor buffer */ 842 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 843 844 /* Rx SW descriptor pool for RXDMA status buffer */ 845 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 846 847 /* Rx SW descriptor pool for RXDMA buffer */ 848 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 849 850 /* Number of REO destination rings */ 851 uint8_t num_reo_dest_rings; 852 853 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 854 /* lock to control access to soc TX descriptors */ 855 qdf_spinlock_t flow_pool_array_lock; 856 857 /* pause callback to pause TX queues as per flow control */ 858 tx_pause_callback pause_cb; 859 860 /* flow pool related statistics */ 861 struct dp_txrx_pool_stats pool_stats; 862 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 863 864 /* 865 * Re-use memory section ends. reuse memory indicator. 866 * Everything above this variable "dp_soc_reinit" is retained across 867 * WiFi up/down for AP use-cases. 868 * Everything below this variable "dp_soc_reinit" is reset during 869 * dp_soc_deinit. 870 */ 871 bool dp_soc_reinit; 872 873 uint32_t wbm_idle_scatter_buf_size; 874 875 /* Tx H/W queues lock */ 876 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 877 878 /* Tx ring map for interrupt processing */ 879 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 880 881 /* Rx ring map for interrupt processing */ 882 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 883 884 /* peer ID to peer object map (array of pointers to peer objects) */ 885 struct dp_peer **peer_id_to_obj_map; 886 887 struct { 888 unsigned mask; 889 unsigned idx_bits; 890 TAILQ_HEAD(, dp_peer) * bins; 891 } peer_hash; 892 893 /* rx defrag state – TBD: do we need this per radio? */ 894 struct { 895 struct { 896 TAILQ_HEAD(, dp_rx_tid) waitlist; 897 uint32_t timeout_ms; 898 qdf_spinlock_t defrag_lock; 899 } defrag; 900 struct { 901 int defrag_timeout_check; 902 int dup_check; 903 } flags; 904 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 905 qdf_spinlock_t reo_cmd_lock; 906 } rx; 907 908 /* optional rx processing function */ 909 void (*rx_opt_proc)( 910 struct dp_vdev *vdev, 911 struct dp_peer *peer, 912 unsigned tid, 913 qdf_nbuf_t msdu_list); 914 915 /* pool addr for mcast enhance buff */ 916 struct { 917 int size; 918 uint32_t paddr; 919 uint32_t *vaddr; 920 struct dp_tx_me_buf_t *freelist; 921 int buf_in_use; 922 qdf_dma_mem_context(memctx); 923 } me_buf; 924 925 /** 926 * peer ref mutex: 927 * 1. Protect peer object lookups until the returned peer object's 928 * reference count is incremented. 929 * 2. Provide mutex when accessing peer object lookup structures. 930 */ 931 DP_MUTEX_TYPE peer_ref_mutex; 932 933 /* maximum value for peer_id */ 934 uint32_t max_peers; 935 936 /* SoC level data path statistics */ 937 struct dp_soc_stats stats; 938 939 /* Enable processing of Tx completion status words */ 940 bool process_tx_status; 941 bool process_rx_status; 942 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 943 struct { 944 unsigned mask; 945 unsigned idx_bits; 946 TAILQ_HEAD(, dp_ast_entry) * bins; 947 } ast_hash; 948 949 qdf_spinlock_t ast_lock; 950 /*Timer for AST entry ageout maintainance */ 951 qdf_timer_t ast_aging_timer; 952 953 /*Timer counter for WDS AST entry ageout*/ 954 uint8_t wds_ast_aging_timer_cnt; 955 956 /*interrupt timer*/ 957 qdf_timer_t mon_reap_timer; 958 uint8_t reap_timer_init; 959 qdf_timer_t int_timer; 960 uint8_t intr_mode; 961 962 qdf_list_t reo_desc_freelist; 963 qdf_spinlock_t reo_desc_freelist_lock; 964 965 /* htt stats */ 966 struct htt_t2h_stats htt_stats; 967 968 void *external_txrx_handle; /* External data path handle */ 969 #ifdef IPA_OFFLOAD 970 /* IPA uC datapath offload Wlan Tx resources */ 971 struct { 972 /* Resource info to be passed to IPA */ 973 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 974 void *ipa_tcl_ring_base_vaddr; 975 uint32_t ipa_tcl_ring_size; 976 qdf_dma_addr_t ipa_tcl_hp_paddr; 977 uint32_t alloc_tx_buf_cnt; 978 979 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 980 void *ipa_wbm_ring_base_vaddr; 981 uint32_t ipa_wbm_ring_size; 982 qdf_dma_addr_t ipa_wbm_tp_paddr; 983 984 /* TX buffers populated into the WBM ring */ 985 void **tx_buf_pool_vaddr_unaligned; 986 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 987 } ipa_uc_tx_rsc; 988 989 /* IPA uC datapath offload Wlan Rx resources */ 990 struct { 991 /* Resource info to be passed to IPA */ 992 qdf_dma_addr_t ipa_reo_ring_base_paddr; 993 void *ipa_reo_ring_base_vaddr; 994 uint32_t ipa_reo_ring_size; 995 qdf_dma_addr_t ipa_reo_tp_paddr; 996 997 /* Resource info to be passed to firmware and IPA */ 998 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 999 void *ipa_rx_refill_buf_ring_base_vaddr; 1000 uint32_t ipa_rx_refill_buf_ring_size; 1001 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 1002 } ipa_uc_rx_rsc; 1003 #endif 1004 1005 /* Smart monitor capability for HKv2 */ 1006 uint8_t hw_nac_monitor_support; 1007 /* Flag to indicate if HTT v2 is enabled*/ 1008 bool is_peer_map_unmap_v2; 1009 /* Per peer per Tid ba window size support */ 1010 uint8_t per_tid_basize_max_tid; 1011 }; 1012 1013 #ifdef IPA_OFFLOAD 1014 /** 1015 * dp_ipa_resources - Resources needed for IPA 1016 */ 1017 struct dp_ipa_resources { 1018 qdf_dma_addr_t tx_ring_base_paddr; 1019 uint32_t tx_ring_size; 1020 uint32_t tx_num_alloc_buffer; 1021 1022 qdf_dma_addr_t tx_comp_ring_base_paddr; 1023 uint32_t tx_comp_ring_size; 1024 1025 qdf_dma_addr_t rx_rdy_ring_base_paddr; 1026 uint32_t rx_rdy_ring_size; 1027 1028 qdf_dma_addr_t rx_refill_ring_base_paddr; 1029 uint32_t rx_refill_ring_size; 1030 1031 /* IPA UC doorbell registers paddr */ 1032 qdf_dma_addr_t tx_comp_doorbell_paddr; 1033 uint32_t *tx_comp_doorbell_vaddr; 1034 qdf_dma_addr_t rx_ready_doorbell_paddr; 1035 }; 1036 #endif 1037 1038 #define MAX_RX_MAC_RINGS 2 1039 /* Same as NAC_MAX_CLENT */ 1040 #define DP_NAC_MAX_CLIENT 24 1041 1042 /* 1043 * Macros to setup link descriptor cookies - for link descriptors, we just 1044 * need first 3 bits to store bank ID. The remaining bytes will be used set a 1045 * unique ID, which will be useful in debugging 1046 */ 1047 #define LINK_DESC_BANK_ID_MASK 0x7 1048 #define LINK_DESC_ID_SHIFT 3 1049 #define LINK_DESC_ID_START 0x8000 1050 1051 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 1052 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 1053 1054 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 1055 ((_cookie) & LINK_DESC_BANK_ID_MASK) 1056 1057 /* same as ieee80211_nac_param */ 1058 enum dp_nac_param_cmd { 1059 /* IEEE80211_NAC_PARAM_ADD */ 1060 DP_NAC_PARAM_ADD = 1, 1061 /* IEEE80211_NAC_PARAM_DEL */ 1062 DP_NAC_PARAM_DEL, 1063 /* IEEE80211_NAC_PARAM_LIST */ 1064 DP_NAC_PARAM_LIST, 1065 }; 1066 1067 /** 1068 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1069 * @neighbour_peers_macaddr: neighbour peer's mac address 1070 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1071 * @ast_entry: ast_entry for neighbour peer 1072 * @rssi: rssi value 1073 */ 1074 struct dp_neighbour_peer { 1075 /* MAC address of neighbour's peer */ 1076 union dp_align_mac_addr neighbour_peers_macaddr; 1077 struct dp_vdev *vdev; 1078 struct dp_ast_entry *ast_entry; 1079 uint8_t rssi; 1080 /* node in the list of neighbour's peer */ 1081 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1082 }; 1083 1084 /** 1085 * struct ppdu_info - PPDU Status info descriptor 1086 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1087 * @max_ppdu_id - wrap around for ppdu id 1088 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1089 * @last_user - last ppdu processed for user 1090 * @is_ampdu - set if Ampdu aggregate 1091 * @nbuf - ppdu descriptor payload 1092 * @ppdu_desc - ppdu descriptor 1093 * @ppdu_info_list_elem - linked list of ppdu tlvs 1094 */ 1095 struct ppdu_info { 1096 uint32_t ppdu_id; 1097 uint32_t max_ppdu_id; 1098 uint16_t tlv_bitmap; 1099 uint16_t last_tlv_cnt; 1100 uint16_t last_user:8, 1101 is_ampdu:1; 1102 qdf_nbuf_t nbuf; 1103 struct cdp_tx_completion_ppdu *ppdu_desc; 1104 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1105 }; 1106 1107 /* PDEV level structure for data path */ 1108 struct dp_pdev { 1109 /** 1110 * Re-use Memory Section Starts 1111 */ 1112 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1113 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1114 1115 /* PDEV Id */ 1116 int pdev_id; 1117 1118 /* LMAC Id */ 1119 int lmac_id; 1120 1121 /* TXRX SOC handle */ 1122 struct dp_soc *soc; 1123 1124 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1125 struct dp_srng rx_refill_buf_ring; 1126 1127 /* RXDMA error destination ring */ 1128 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1129 1130 /* Link descriptor memory banks */ 1131 struct { 1132 void *base_vaddr_unaligned; 1133 void *base_vaddr; 1134 qdf_dma_addr_t base_paddr_unaligned; 1135 qdf_dma_addr_t base_paddr; 1136 uint32_t size; 1137 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1138 1139 /* RXDMA monitor buffer replenish ring */ 1140 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1141 1142 /* RXDMA monitor destination ring */ 1143 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1144 1145 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1146 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1147 1148 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1149 1150 /* 1151 * re-use memory section ends 1152 * reuse memory/deinit indicator 1153 * 1154 * DO NOT CHANGE NAME OR MOVE THIS VARIABLE 1155 */ 1156 bool pdev_deinit; 1157 1158 /* Second ring used to replenish rx buffers */ 1159 struct dp_srng rx_refill_buf_ring2; 1160 1161 /* Empty ring used by firmware to post rx buffers to the MAC */ 1162 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1163 1164 /* wlan_cfg pdev ctxt*/ 1165 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1166 1167 /** 1168 * TODO: See if we need a ring map here for LMAC rings. 1169 * 1. Monitor rings are currently planning to be processed on receiving 1170 * PPDU end interrupts and hence wont need ring based interrupts. 1171 * 2. Rx buffer rings will be replenished during REO destination 1172 * processing and doesn't require regular interrupt handling - we will 1173 * only handle low water mark interrupts which is not expected 1174 * frequently 1175 */ 1176 1177 /* VDEV list */ 1178 TAILQ_HEAD(, dp_vdev) vdev_list; 1179 1180 /* vdev list lock */ 1181 qdf_spinlock_t vdev_list_lock; 1182 1183 /* Number of vdevs this device have */ 1184 uint16_t vdev_count; 1185 1186 /* PDEV transmit lock */ 1187 qdf_spinlock_t tx_lock; 1188 1189 #ifndef REMOVE_PKT_LOG 1190 bool pkt_log_init; 1191 /* Pktlog pdev */ 1192 struct pktlog_dev_t *pl_dev; 1193 #endif /* #ifndef REMOVE_PKT_LOG */ 1194 1195 /* Monitor mode interface and status storage */ 1196 struct dp_vdev *monitor_vdev; 1197 1198 /* monitor mode lock */ 1199 qdf_spinlock_t mon_lock; 1200 1201 /*tx_mutex for me*/ 1202 DP_MUTEX_TYPE tx_mutex; 1203 1204 /* Smart Mesh */ 1205 bool filter_neighbour_peers; 1206 1207 /*flag to indicate neighbour_peers_list not empty */ 1208 bool neighbour_peers_added; 1209 /* smart mesh mutex */ 1210 qdf_spinlock_t neighbour_peer_mutex; 1211 /* Neighnour peer list */ 1212 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1213 /* msdu chain head & tail */ 1214 qdf_nbuf_t invalid_peer_head_msdu; 1215 qdf_nbuf_t invalid_peer_tail_msdu; 1216 1217 /* Band steering */ 1218 /* TBD */ 1219 1220 /* PDEV level data path statistics */ 1221 struct cdp_pdev_stats stats; 1222 1223 /* Global RX decap mode for the device */ 1224 enum htt_pkt_type rx_decap_mode; 1225 1226 /* Enhanced Stats is enabled */ 1227 bool enhanced_stats_en; 1228 1229 /* advance filter mode and type*/ 1230 uint8_t mon_filter_mode; 1231 uint16_t fp_mgmt_filter; 1232 uint16_t fp_ctrl_filter; 1233 uint16_t fp_data_filter; 1234 uint16_t mo_mgmt_filter; 1235 uint16_t mo_ctrl_filter; 1236 uint16_t mo_data_filter; 1237 uint16_t md_data_filter; 1238 1239 qdf_atomic_t num_tx_outstanding; 1240 1241 qdf_atomic_t num_tx_exception; 1242 1243 /* MCL specific local peer handle */ 1244 struct { 1245 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1246 uint8_t freelist; 1247 qdf_spinlock_t lock; 1248 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1249 } local_peer_ids; 1250 1251 /* dscp_tid_map_*/ 1252 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1253 1254 struct hal_rx_ppdu_info ppdu_info; 1255 1256 /* operating channel */ 1257 uint8_t operating_channel; 1258 1259 qdf_nbuf_queue_t rx_status_q; 1260 uint32_t mon_ppdu_status; 1261 struct cdp_mon_status rx_mon_recv_status; 1262 /* monitor mode status/destination ring PPDU and MPDU count */ 1263 struct cdp_pdev_mon_stats rx_mon_stats; 1264 /* to track duplicate link descriptor indications by HW for a WAR */ 1265 uint64_t mon_last_linkdesc_paddr; 1266 /* to track duplicate buffer indications by HW for a WAR */ 1267 uint32_t mon_last_buf_cookie; 1268 1269 /* pool addr for mcast enhance buff */ 1270 struct { 1271 int size; 1272 uint32_t paddr; 1273 char *vaddr; 1274 struct dp_tx_me_buf_t *freelist; 1275 int buf_in_use; 1276 qdf_dma_mem_context(memctx); 1277 } me_buf; 1278 1279 bool hmmc_tid_override_en; 1280 uint8_t hmmc_tid; 1281 1282 /* Number of VAPs with mcast enhancement enabled */ 1283 qdf_atomic_t mc_num_vap_attached; 1284 1285 qdf_atomic_t stats_cmd_complete; 1286 1287 #ifdef IPA_OFFLOAD 1288 ipa_uc_op_cb_type ipa_uc_op_cb; 1289 void *usr_ctxt; 1290 struct dp_ipa_resources ipa_resource; 1291 #endif 1292 1293 /* TBD */ 1294 1295 /* map this pdev to a particular Reo Destination ring */ 1296 enum cdp_host_reo_dest_ring reo_dest; 1297 1298 #ifndef REMOVE_PKT_LOG 1299 /* Packet log mode */ 1300 uint8_t rx_pktlog_mode; 1301 #endif 1302 1303 /* WDI event handlers */ 1304 struct wdi_event_subscribe_t **wdi_event_list; 1305 1306 /* ppdu_id of last received HTT TX stats */ 1307 uint32_t last_ppdu_id; 1308 struct { 1309 uint8_t last_user; 1310 qdf_nbuf_t buf; 1311 } tx_ppdu_info; 1312 1313 bool tx_sniffer_enable; 1314 /* mirror copy mode */ 1315 bool mcopy_mode; 1316 bool bpr_enable; 1317 struct { 1318 uint16_t tx_ppdu_id; 1319 uint16_t tx_peer_id; 1320 uint16_t rx_ppdu_id; 1321 } m_copy_id; 1322 1323 /* To check if PPDU Tx stats are enabled for Pktlog */ 1324 bool pktlog_ppdu_stats; 1325 1326 void *dp_txrx_handle; /* Advanced data path handle */ 1327 1328 #ifdef ATH_SUPPORT_NAC_RSSI 1329 bool nac_rssi_filtering; 1330 #endif 1331 /* list of ppdu tlvs */ 1332 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1333 uint32_t tlv_count; 1334 uint32_t list_depth; 1335 uint32_t ppdu_id; 1336 bool first_nbuf; 1337 struct { 1338 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1339 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1340 uint32_t ppdu_id; 1341 } mgmtctrl_frm_info; 1342 1343 /* Current noise-floor reading for the pdev channel */ 1344 int16_t chan_noise_floor; 1345 1346 /* 1347 * For multiradio device, this flag indicates if 1348 * this radio is primary or secondary. 1349 * 1350 * For HK 1.0, this is used for WAR for the AST issue. 1351 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1352 * across 2 radios. is_primary indicates the radio on which DP should 1353 * install HW AST entry if there is a request to add 2 AST entries 1354 * with same MAC address across 2 radios 1355 */ 1356 uint8_t is_primary; 1357 /* Context of cal client timer */ 1358 void *cal_client_ctx; 1359 struct cdp_tx_sojourn_stats sojourn_stats; 1360 qdf_nbuf_t sojourn_buf; 1361 1362 /* peer pointer for collecting invalid peer stats */ 1363 struct dp_peer *invalid_peer; 1364 1365 union dp_rx_desc_list_elem_t *free_list_head; 1366 union dp_rx_desc_list_elem_t *free_list_tail; 1367 /* Pdev level flag to check peer based pktlog enabled or 1368 * disabled 1369 */ 1370 uint8_t dp_peer_based_pktlog; 1371 }; 1372 1373 struct dp_peer; 1374 1375 /* VDEV structure for data path state */ 1376 struct dp_vdev { 1377 /* OS device abstraction */ 1378 qdf_device_t osdev; 1379 /* physical device that is the parent of this virtual device */ 1380 struct dp_pdev *pdev; 1381 1382 /* Handle to the OS shim SW's virtual device */ 1383 ol_osif_vdev_handle osif_vdev; 1384 1385 /* Handle to the UMAC handle */ 1386 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1387 /* vdev_id - ID used to specify a particular vdev to the target */ 1388 uint8_t vdev_id; 1389 1390 /* MAC address */ 1391 union dp_align_mac_addr mac_addr; 1392 1393 /* node in the pdev's list of vdevs */ 1394 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1395 1396 /* dp_peer list */ 1397 TAILQ_HEAD(, dp_peer) peer_list; 1398 1399 /* default RX call back function called by dp */ 1400 ol_txrx_rx_fp osif_rx; 1401 /* callback to deliver rx frames to the OS */ 1402 ol_txrx_rx_fp osif_rx_stack; 1403 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1404 ol_txrx_get_key_fp osif_get_key; 1405 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1406 1407 #ifdef notyet 1408 /* callback to check if the msdu is an WAI (WAPI) frame */ 1409 ol_rx_check_wai_fp osif_check_wai; 1410 #endif 1411 1412 /* proxy arp function */ 1413 ol_txrx_proxy_arp_fp osif_proxy_arp; 1414 1415 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1416 ol_txrx_rx_mon_fp osif_rx_mon; 1417 1418 ol_txrx_mcast_me_fp me_convert; 1419 1420 /* completion function used by this vdev*/ 1421 ol_txrx_completion_fp tx_comp; 1422 1423 /* deferred vdev deletion state */ 1424 struct { 1425 /* VDEV delete pending */ 1426 int pending; 1427 /* 1428 * callback and a context argument to provide a 1429 * notification for when the vdev is deleted. 1430 */ 1431 ol_txrx_vdev_delete_cb callback; 1432 void *context; 1433 } delete; 1434 1435 /* tx data delivery notification callback function */ 1436 struct { 1437 ol_txrx_data_tx_cb func; 1438 void *ctxt; 1439 } tx_non_std_data_callback; 1440 1441 1442 /* safe mode control to bypass the encrypt and decipher process*/ 1443 uint32_t safemode; 1444 1445 /* rx filter related */ 1446 uint32_t drop_unenc; 1447 #ifdef notyet 1448 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1449 uint32_t filters_num; 1450 #endif 1451 /* TDLS Link status */ 1452 bool tdls_link_connected; 1453 bool is_tdls_frame; 1454 1455 1456 /* VDEV operating mode */ 1457 enum wlan_op_mode opmode; 1458 1459 /* Tx encapsulation type for this VAP */ 1460 enum htt_cmn_pkt_type tx_encap_type; 1461 /* Rx Decapsulation type for this VAP */ 1462 enum htt_cmn_pkt_type rx_decap_type; 1463 1464 /* BSS peer */ 1465 struct dp_peer *vap_bss_peer; 1466 1467 /* WDS enabled */ 1468 bool wds_enabled; 1469 1470 /* MEC enabled */ 1471 bool mec_enabled; 1472 1473 /* DA WAR enable flag */ 1474 bool da_war_enabled; 1475 1476 /* WDS Aging timer period */ 1477 uint32_t wds_aging_timer_val; 1478 1479 /* NAWDS enabled */ 1480 bool nawds_enabled; 1481 1482 /* Default HTT meta data for this VDEV */ 1483 /* TBD: check alignment constraints */ 1484 uint16_t htt_tcl_metadata; 1485 1486 /* Mesh mode vdev */ 1487 uint32_t mesh_vdev; 1488 1489 /* Mesh mode rx filter setting */ 1490 uint32_t mesh_rx_filter; 1491 1492 /* DSCP-TID mapping table ID */ 1493 uint8_t dscp_tid_map_id; 1494 1495 /* Multicast enhancement enabled */ 1496 uint8_t mcast_enhancement_en; 1497 1498 /* per vdev rx nbuf queue */ 1499 qdf_nbuf_queue_t rxq; 1500 1501 uint8_t tx_ring_id; 1502 struct dp_tx_desc_pool_s *tx_desc; 1503 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1504 1505 /* VDEV Stats */ 1506 struct cdp_vdev_stats stats; 1507 1508 /* Is this a proxySTA VAP */ 1509 bool proxysta_vdev; 1510 /* Is isolation mode enabled */ 1511 bool isolation_vdev; 1512 1513 /* Address search flags to be configured in HAL descriptor */ 1514 uint8_t hal_desc_addr_search_flags; 1515 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1516 struct dp_tx_desc_pool_s *pool; 1517 #endif 1518 /* AP BRIDGE enabled */ 1519 uint32_t ap_bridge_enabled; 1520 1521 enum cdp_sec_type sec_type; 1522 1523 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1524 bool raw_mode_war; 1525 1526 /* Address search type to be set in TX descriptor */ 1527 uint8_t search_type; 1528 1529 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1530 uint16_t bss_ast_hash; 1531 }; 1532 1533 1534 enum { 1535 dp_sec_mcast = 0, 1536 dp_sec_ucast 1537 }; 1538 1539 #ifdef WDS_VENDOR_EXTENSION 1540 typedef struct { 1541 uint8_t wds_tx_mcast_4addr:1, 1542 wds_tx_ucast_4addr:1, 1543 wds_rx_filter:1, /* enforce rx filter */ 1544 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1545 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1546 1547 } dp_ecm_policy; 1548 #endif 1549 1550 /* Peer structure for data path state */ 1551 struct dp_peer { 1552 /* VDEV to which this peer is associated */ 1553 struct dp_vdev *vdev; 1554 1555 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1556 1557 struct dp_ast_entry *self_ast_entry; 1558 1559 qdf_atomic_t ref_cnt; 1560 1561 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1562 /* peer ID(s) for this peer */ 1563 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1564 1565 union dp_align_mac_addr mac_addr; 1566 1567 /* node in the vdev's list of peers */ 1568 TAILQ_ENTRY(dp_peer) peer_list_elem; 1569 /* node in the hash table bin's list of peers */ 1570 TAILQ_ENTRY(dp_peer) hash_list_elem; 1571 1572 /* TID structures */ 1573 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1574 1575 /* TBD: No transmit TID state required? */ 1576 1577 struct { 1578 enum cdp_sec_type sec_type; 1579 u_int32_t michael_key[2]; /* relevant for TKIP */ 1580 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1581 1582 /* 1583 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1584 * regular rx processing, or has been redirected to a /dev/null discard 1585 * function when peer deletion is in progress. 1586 */ 1587 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1588 unsigned tid, qdf_nbuf_t msdu_list); 1589 1590 /* set when node is authorized */ 1591 uint8_t authorize:1; 1592 1593 u_int8_t nac; 1594 1595 /* Band steering: Set when node is inactive */ 1596 uint8_t peer_bs_inact_flag:1; 1597 u_int16_t peer_bs_inact; /* inactivity mark count */ 1598 1599 /* NAWDS Flag and Bss Peer bit */ 1600 uint8_t nawds_enabled:1, 1601 bss_peer:1, 1602 wapi:1, 1603 wds_enabled:1; 1604 1605 /* MCL specific peer local id */ 1606 uint16_t local_id; 1607 enum ol_txrx_peer_state state; 1608 qdf_spinlock_t peer_info_lock; 1609 1610 qdf_time_t last_assoc_rcvd; 1611 qdf_time_t last_disassoc_rcvd; 1612 qdf_time_t last_deauth_rcvd; 1613 /* Peer Stats */ 1614 struct cdp_peer_stats stats; 1615 1616 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1617 /* TBD */ 1618 1619 #ifdef WDS_VENDOR_EXTENSION 1620 dp_ecm_policy wds_ecm; 1621 #endif 1622 bool delete_in_progress; 1623 1624 /* Active Block ack sessions */ 1625 uint16_t active_ba_session_cnt; 1626 1627 /* Current HW buffersize setting */ 1628 uint16_t hw_buffer_size; 1629 1630 /* 1631 * Flag to check if sessions with 256 buffersize 1632 * should be terminated. 1633 */ 1634 uint8_t kill_256_sessions; 1635 qdf_atomic_t is_default_route_set; 1636 /* Peer level flag to check peer based pktlog enabled or 1637 * disabled 1638 */ 1639 uint8_t peer_based_pktlog_filter; 1640 }; 1641 1642 #ifdef CONFIG_WIN 1643 /* 1644 * dp_invalid_peer_msg 1645 * @nbuf: data buffer 1646 * @wh: 802.11 header 1647 * @vdev_id: id of vdev 1648 */ 1649 struct dp_invalid_peer_msg { 1650 qdf_nbuf_t nbuf; 1651 struct ieee80211_frame *wh; 1652 uint8_t vdev_id; 1653 }; 1654 #endif 1655 1656 /* 1657 * dp_tx_me_buf_t: ME buffer 1658 * next: pointer to next buffer 1659 * data: Destination Mac address 1660 */ 1661 struct dp_tx_me_buf_t { 1662 /* Note: ME buf pool initialization logic expects next pointer to 1663 * be the first element. Dont add anything before next */ 1664 struct dp_tx_me_buf_t *next; 1665 uint8_t data[DP_MAC_ADDR_LEN]; 1666 }; 1667 1668 #endif /* _DP_TYPES_H_ */ 1669