1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 64 #define DP_MAX_INTERRUPT_CONTEXTS 8 65 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 66 #define DSCP_TID_MAP_MAX (64) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(CONFIG_MCL) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 #define MAX_LINK_DESC_BANKS 8 82 #define MAX_TXDESC_POOLS 4 83 #define MAX_RXDESC_POOLS 4 84 #define MAX_REO_DEST_RINGS 4 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DP_MAX_INTERRUPT_CONTEXTS 8 89 #define DEFAULT_HW_PEER_ID 0xffff 90 91 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 92 93 #define DP_MAX_INTERRUPT_CONTEXTS 8 94 95 #ifndef REMOVE_PKT_LOG 96 enum rx_pktlog_mode { 97 DP_RX_PKTLOG_DISABLED = 0, 98 DP_RX_PKTLOG_FULL, 99 DP_RX_PKTLOG_LITE, 100 }; 101 #endif 102 103 struct dp_soc_cmn; 104 struct dp_pdev; 105 struct dp_vdev; 106 struct dp_tx_desc_s; 107 struct dp_soc; 108 union dp_rx_desc_list_elem_t; 109 110 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 111 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 112 113 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 114 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 115 116 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 117 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 118 119 #define DP_MUTEX_TYPE qdf_spinlock_t 120 121 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 122 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 123 124 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 125 ((_a)[0] == 0x33 && \ 126 (_a)[1] == 0x33) 127 128 #define DP_FRAME_IS_BROADCAST(_a) \ 129 ((_a)[0] == 0xff && \ 130 (_a)[1] == 0xff && \ 131 (_a)[2] == 0xff && \ 132 (_a)[3] == 0xff && \ 133 (_a)[4] == 0xff && \ 134 (_a)[5] == 0xff) 135 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 136 (_llc)->llc_ssap == 0xaa && \ 137 (_llc)->llc_un.type_snap.control == 0x3) 138 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 139 #define DP_FRAME_FC0_TYPE_MASK 0x0c 140 #define DP_FRAME_FC0_TYPE_DATA 0x08 141 #define DP_FRAME_IS_DATA(_frame) \ 142 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 143 144 /** 145 * macros to convert hw mac id to sw mac id: 146 * mac ids used by hardware start from a value of 1 while 147 * those in host software start from a value of 0. Use the 148 * macros below to convert between mac ids used by software and 149 * hardware 150 */ 151 #define DP_SW2HW_MACID(id) ((id) + 1) 152 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 153 #define DP_MAC_ADDR_LEN 6 154 155 /** 156 * enum dp_intr_mode 157 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 158 * @DP_INTR_MSI: MSI interrupts, for MCL 159 * @DP_INTR_POLL: Polling 160 */ 161 enum dp_intr_mode { 162 DP_INTR_LEGACY = 0, 163 DP_INTR_MSI, 164 DP_INTR_POLL, 165 }; 166 167 /** 168 * enum dp_tx_frm_type 169 * @dp_tx_frm_std: Regular frame, no added header fragments 170 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 171 * @dp_tx_frm_sg: SG segment 172 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 173 * @dp_tx_frm_me: Multicast to Unicast Converted frame 174 * @dp_tx_frm_raw: Raw Frame 175 */ 176 enum dp_tx_frm_type { 177 dp_tx_frm_std = 0, 178 dp_tx_frm_tso, 179 dp_tx_frm_sg, 180 dp_tx_frm_audio, 181 dp_tx_frm_me, 182 dp_tx_frm_raw, 183 }; 184 185 /** 186 * enum dp_ast_type 187 * @dp_ast_type_wds: WDS peer AST type 188 * @dp_ast_type_static: static ast entry type 189 * @dp_ast_type_mec: Multicast echo ast entry type 190 */ 191 enum dp_ast_type { 192 dp_ast_type_wds = 0, 193 dp_ast_type_static, 194 dp_ast_type_mec, 195 }; 196 197 /** 198 * enum dp_nss_cfg 199 * @dp_nss_cfg_default: No radios are offloaded 200 * @dp_nss_cfg_first_radio: First radio offloaded 201 * @dp_nss_cfg_second_radio: Second radio offloaded 202 * @dp_nss_cfg_dbdc: Dual radios offloaded 203 */ 204 enum dp_nss_cfg { 205 dp_nss_cfg_default, 206 dp_nss_cfg_first_radio, 207 dp_nss_cfg_second_radio, 208 dp_nss_cfg_dbdc, 209 }; 210 211 /** 212 * struct rx_desc_pool 213 * @pool_size: number of RX descriptor in the pool 214 * @array: pointer to array of RX descriptor 215 * @freelist: pointer to free RX descriptor link list 216 * @lock: Protection for the RX descriptor pool 217 * @owner: owner for nbuf 218 */ 219 struct rx_desc_pool { 220 uint32_t pool_size; 221 union dp_rx_desc_list_elem_t *array; 222 union dp_rx_desc_list_elem_t *freelist; 223 qdf_spinlock_t lock; 224 uint8_t owner; 225 }; 226 227 /** 228 * struct dp_tx_ext_desc_elem_s 229 * @next: next extension descriptor pointer 230 * @vaddr: hlos virtual address pointer 231 * @paddr: physical address pointer for descriptor 232 */ 233 struct dp_tx_ext_desc_elem_s { 234 struct dp_tx_ext_desc_elem_s *next; 235 void *vaddr; 236 qdf_dma_addr_t paddr; 237 }; 238 239 /** 240 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 241 * @elem_count: Number of descriptors in the pool 242 * @elem_size: Size of each descriptor 243 * @num_free: Number of free descriptors 244 * @msdu_ext_desc: MSDU extension descriptor 245 * @desc_pages: multiple page allocation information for actual descriptors 246 * @link_elem_size: size of the link descriptor in cacheable memory used for 247 * chaining the extension descriptors 248 * @desc_link_pages: multiple page allocation information for link descriptors 249 */ 250 struct dp_tx_ext_desc_pool_s { 251 uint16_t elem_count; 252 int elem_size; 253 uint16_t num_free; 254 struct qdf_mem_multi_page_t desc_pages; 255 int link_elem_size; 256 struct qdf_mem_multi_page_t desc_link_pages; 257 struct dp_tx_ext_desc_elem_s *freelist; 258 qdf_spinlock_t lock; 259 qdf_dma_mem_context(memctx); 260 }; 261 262 /** 263 * struct dp_tx_desc_s - Tx Descriptor 264 * @next: Next in the chain of descriptors in freelist or in the completion list 265 * @nbuf: Buffer Address 266 * @msdu_ext_desc: MSDU extension descriptor 267 * @id: Descriptor ID 268 * @vdev: vdev over which the packet was transmitted 269 * @pdev: Handle to pdev 270 * @pool_id: Pool ID - used when releasing the descriptor 271 * @flags: Flags to track the state of descriptor and special frame handling 272 * @comp: Pool ID - used when releasing the descriptor 273 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 274 * This is maintained in descriptor to allow more efficient 275 * processing in completion event processing code. 276 * This field is filled in with the htt_pkt_type enum. 277 * @frm_type: Frame Type - ToDo check if this is redundant 278 * @pkt_offset: Offset from which the actual packet data starts 279 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 280 * Tx completion of ME packet 281 * @pool: handle to flow_pool this descriptor belongs to. 282 */ 283 struct dp_tx_desc_s { 284 struct dp_tx_desc_s *next; 285 qdf_nbuf_t nbuf; 286 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 287 uint32_t id; 288 struct dp_vdev *vdev; 289 struct dp_pdev *pdev; 290 uint8_t pool_id; 291 uint16_t flags; 292 struct hal_tx_desc_comp_s comp; 293 uint16_t tx_encap_type; 294 uint8_t frm_type; 295 uint8_t pkt_offset; 296 void *me_buffer; 297 void *tso_desc; 298 void *tso_num_desc; 299 }; 300 301 /** 302 * enum flow_pool_status - flow pool status 303 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 304 * and network queues are unpaused 305 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 306 * and network queues are paused 307 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 308 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 309 */ 310 enum flow_pool_status { 311 FLOW_POOL_ACTIVE_UNPAUSED = 0, 312 FLOW_POOL_ACTIVE_PAUSED = 1, 313 FLOW_POOL_INVALID = 2, 314 FLOW_POOL_INACTIVE = 3, 315 }; 316 317 /** 318 * struct dp_tx_tso_seg_pool_s 319 * @pool_size: total number of pool elements 320 * @num_free: free element count 321 * @freelist: first free element pointer 322 * @lock: lock for accessing the pool 323 */ 324 struct dp_tx_tso_seg_pool_s { 325 uint16_t pool_size; 326 uint16_t num_free; 327 struct qdf_tso_seg_elem_t *freelist; 328 qdf_spinlock_t lock; 329 }; 330 331 /** 332 * struct dp_tx_tso_num_seg_pool_s { 333 * @num_seg_pool_size: total number of pool elements 334 * @num_free: free element count 335 * @freelist: first free element pointer 336 * @lock: lock for accessing the pool 337 */ 338 339 struct dp_tx_tso_num_seg_pool_s { 340 uint16_t num_seg_pool_size; 341 uint16_t num_free; 342 struct qdf_tso_num_seg_elem_t *freelist; 343 /*tso mutex */ 344 qdf_spinlock_t lock; 345 }; 346 347 /** 348 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 349 * @elem_size: Size of each descriptor in the pool 350 * @pool_size: Total number of descriptors in the pool 351 * @num_free: Number of free descriptors 352 * @num_allocated: Number of used descriptors 353 * @freelist: Chain of free descriptors 354 * @desc_pages: multiple page allocation information for actual descriptors 355 * @num_invalid_bin: Deleted pool with pending Tx completions. 356 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 357 * @flow_pool_array: List of allocated flow pools 358 * @lock- Lock for descriptor allocation/free from/to the pool 359 */ 360 struct dp_tx_desc_pool_s { 361 uint16_t elem_size; 362 uint32_t num_allocated; 363 struct dp_tx_desc_s *freelist; 364 struct qdf_mem_multi_page_t desc_pages; 365 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 366 uint16_t pool_size; 367 uint8_t flow_pool_id; 368 uint8_t num_invalid_bin; 369 uint16_t avail_desc; 370 enum flow_pool_status status; 371 enum htt_flow_type flow_type; 372 uint16_t stop_th; 373 uint16_t start_th; 374 uint16_t pkt_drop_no_desc; 375 qdf_spinlock_t flow_pool_lock; 376 uint8_t pool_create_cnt; 377 void *pool_owner_ctx; 378 #else 379 uint16_t elem_count; 380 uint32_t num_free; 381 qdf_spinlock_t lock; 382 #endif 383 }; 384 385 /** 386 * struct dp_txrx_pool_stats - flow pool related statistics 387 * @pool_map_count: flow pool map received 388 * @pool_unmap_count: flow pool unmap received 389 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 390 */ 391 struct dp_txrx_pool_stats { 392 uint16_t pool_map_count; 393 uint16_t pool_unmap_count; 394 uint16_t pkt_drop_no_pool; 395 }; 396 397 struct dp_srng { 398 void *hal_srng; 399 void *base_vaddr_unaligned; 400 qdf_dma_addr_t base_paddr_unaligned; 401 uint32_t alloc_size; 402 int irq; 403 uint32_t num_entries; 404 }; 405 406 struct dp_rx_reorder_array_elem { 407 qdf_nbuf_t head; 408 qdf_nbuf_t tail; 409 }; 410 411 #define DP_RX_BA_INACTIVE 0 412 #define DP_RX_BA_ACTIVE 1 413 #define DP_RX_BA_IN_PROGRESS 2 414 struct dp_reo_cmd_info { 415 uint16_t cmd; 416 enum hal_reo_cmd_type cmd_type; 417 void *data; 418 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 419 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 420 }; 421 422 /* Rx TID */ 423 struct dp_rx_tid { 424 /* TID */ 425 int tid; 426 427 /* Num of addba requests */ 428 uint32_t num_of_addba_req; 429 430 /* Num of addba responses */ 431 uint32_t num_of_addba_resp; 432 433 /* Num of delba requests */ 434 uint32_t num_of_delba_req; 435 436 /* Num of addba responses successful */ 437 uint32_t num_addba_rsp_success; 438 439 /* Num of addba responses failed */ 440 uint32_t num_addba_rsp_failed; 441 442 /* pn size */ 443 uint8_t pn_size; 444 /* REO TID queue descriptors */ 445 void *hw_qdesc_vaddr_unaligned; 446 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 447 qdf_dma_addr_t hw_qdesc_paddr; 448 uint32_t hw_qdesc_alloc_size; 449 450 /* RX ADDBA session state */ 451 int ba_status; 452 453 /* RX BA window size */ 454 uint16_t ba_win_size; 455 456 /* Starting sequence number in Addba request */ 457 uint16_t startseqnum; 458 459 /* TODO: Check the following while adding defragmentation support */ 460 struct dp_rx_reorder_array_elem *array; 461 /* base - single rx reorder element used for non-aggr cases */ 462 struct dp_rx_reorder_array_elem base; 463 464 /* only used for defrag right now */ 465 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 466 467 /* Store dst desc for reinjection */ 468 void *dst_ring_desc; 469 struct dp_rx_desc *head_frag_desc; 470 471 /* rx_tid lock */ 472 qdf_spinlock_t tid_lock; 473 474 /* Sequence and fragments that are being processed currently */ 475 uint32_t curr_seq_num; 476 uint32_t curr_frag_num; 477 478 uint32_t defrag_timeout_ms; 479 uint16_t dialogtoken; 480 uint16_t statuscode; 481 /* user defined ADDBA response status code */ 482 uint16_t userstatuscode; 483 }; 484 485 /* per interrupt context */ 486 struct dp_intr { 487 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 488 associated with this napi context */ 489 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 490 with this interrupt context */ 491 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 492 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 493 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 494 uint8_t reo_status_ring_mask; /* REO command response ring */ 495 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 496 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 497 struct dp_soc *soc; /* Reference to SoC structure , 498 to get DMA ring handles */ 499 qdf_lro_ctx_t lro_ctx; 500 uint8_t dp_intr_id; 501 }; 502 503 #define REO_DESC_FREELIST_SIZE 64 504 #define REO_DESC_FREE_DEFER_MS 1000 505 struct reo_desc_list_node { 506 qdf_list_node_t node; 507 unsigned long free_ts; 508 struct dp_rx_tid rx_tid; 509 }; 510 511 /* SoC level data path statistics */ 512 struct dp_soc_stats { 513 struct { 514 uint32_t added; 515 uint32_t deleted; 516 uint32_t aged_out; 517 } ast; 518 519 /* SOC level TX stats */ 520 struct { 521 /* packets dropped on tx because of no peer */ 522 struct cdp_pkt_info tx_invalid_peer; 523 /* descriptors in each tcl ring */ 524 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 525 /* Descriptors in use at soc */ 526 uint32_t desc_in_use; 527 /* tqm_release_reason == FW removed */ 528 uint32_t dropped_fw_removed; 529 530 } tx; 531 532 /* SOC level RX stats */ 533 struct { 534 /* Rx errors */ 535 /* Total Packets in Rx Error ring */ 536 uint32_t err_ring_pkts; 537 /* No of Fragments */ 538 uint32_t rx_frags; 539 struct { 540 /* Invalid RBM error count */ 541 uint32_t invalid_rbm; 542 /* Invalid VDEV Error count */ 543 uint32_t invalid_vdev; 544 /* Invalid PDEV error count */ 545 uint32_t invalid_pdev; 546 /* Invalid PEER Error count */ 547 struct cdp_pkt_info rx_invalid_peer; 548 /* HAL ring access Fail error count */ 549 uint32_t hal_ring_access_fail; 550 /* RX DMA error count */ 551 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 552 /* REO Error count */ 553 uint32_t reo_error[HAL_REO_ERR_MAX]; 554 /* HAL REO ERR Count */ 555 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 556 } err; 557 558 /* packet count per core - per ring */ 559 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 560 } rx; 561 }; 562 563 #define DP_MAC_ADDR_LEN 6 564 union dp_align_mac_addr { 565 uint8_t raw[DP_MAC_ADDR_LEN]; 566 struct { 567 uint16_t bytes_ab; 568 uint16_t bytes_cd; 569 uint16_t bytes_ef; 570 } align2; 571 struct { 572 uint32_t bytes_abcd; 573 uint16_t bytes_ef; 574 } align4; 575 struct { 576 uint16_t bytes_ab; 577 uint32_t bytes_cdef; 578 } align4_2; 579 }; 580 581 /* 582 * dp_ast_entry 583 * 584 * @ast_idx: Hardware AST Index 585 * @mac_addr: MAC Address for this AST entry 586 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 587 * associated peer with this MAC address) 588 * @next_hop: Set to 1 if this is for a WDS node 589 * @is_active: flag to indicate active data traffic on this node 590 * (used for aging out/expiry) 591 * @ase_list_elem: node in peer AST list 592 * @is_bss: flag to indicate if entry corresponds to bss peer 593 * @pdev_id: pdev ID 594 * @vdev_id: vdev ID 595 * @type: flag to indicate type of the entry(static/WDS/MEC) 596 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 597 */ 598 struct dp_ast_entry { 599 uint16_t ast_idx; 600 /* MAC address */ 601 union dp_align_mac_addr mac_addr; 602 struct dp_peer *peer; 603 bool next_hop; 604 bool is_active; 605 bool is_bss; 606 uint8_t pdev_id; 607 uint8_t vdev_id; 608 enum cdp_txrx_ast_entry_type type; 609 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 610 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 611 }; 612 613 /* SOC level htt stats */ 614 struct htt_t2h_stats { 615 /* lock to protect htt_stats_msg update */ 616 qdf_spinlock_t lock; 617 618 /* work queue to process htt stats */ 619 qdf_work_t work; 620 621 /* T2H Ext stats message queue */ 622 qdf_nbuf_queue_t msg; 623 624 /* number of completed stats in htt_stats_msg */ 625 uint32_t num_stats; 626 }; 627 628 /* SOC level structure for data path */ 629 struct dp_soc { 630 /* Common base structure - Should be the first member */ 631 struct cdp_soc_t cdp_soc; 632 633 /* SoC Obj */ 634 void *ctrl_psoc; 635 636 /* OS device abstraction */ 637 qdf_device_t osdev; 638 639 /* WLAN config context */ 640 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 641 642 /* HTT handle for host-fw interaction */ 643 void *htt_handle; 644 645 /* Commint init done */ 646 qdf_atomic_t cmn_init_done; 647 648 /* Opaque hif handle */ 649 struct hif_opaque_softc *hif_handle; 650 651 /* PDEVs on this SOC */ 652 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 653 654 /* Number of PDEVs */ 655 uint8_t pdev_count; 656 657 /*cce disable*/ 658 bool cce_disable; 659 660 /* Link descriptor memory banks */ 661 struct { 662 void *base_vaddr_unaligned; 663 void *base_vaddr; 664 qdf_dma_addr_t base_paddr_unaligned; 665 qdf_dma_addr_t base_paddr; 666 uint32_t size; 667 } link_desc_banks[MAX_LINK_DESC_BANKS]; 668 669 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 670 struct dp_srng wbm_idle_link_ring; 671 672 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 673 */ 674 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 675 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 676 uint32_t wbm_idle_scatter_buf_size; 677 678 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 679 qdf_spinlock_t flow_pool_array_lock; 680 tx_pause_callback pause_cb; 681 struct dp_txrx_pool_stats pool_stats; 682 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 683 /* Tx SW descriptor pool */ 684 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 685 686 /* Tx MSDU Extension descriptor pool */ 687 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 688 689 /* Tx TSO descriptor pool */ 690 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 691 692 /* Tx TSO Num of segments pool */ 693 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 694 695 /* Tx H/W queues lock */ 696 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 697 698 /* Rx SW descriptor pool for RXDMA buffer */ 699 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 700 701 /* Rx SW descriptor pool for RXDMA monitor buffer */ 702 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 703 704 /* Rx SW descriptor pool for RXDMA status buffer */ 705 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 706 707 /* HAL SOC handle */ 708 void *hal_soc; 709 710 /* DP Interrupts */ 711 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 712 713 /* REO destination rings */ 714 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 715 716 /* Number of REO destination rings */ 717 uint8_t num_reo_dest_rings; 718 719 /* REO exception ring - See if should combine this with reo_dest_ring */ 720 struct dp_srng reo_exception_ring; 721 722 /* REO reinjection ring */ 723 struct dp_srng reo_reinject_ring; 724 725 /* REO command ring */ 726 struct dp_srng reo_cmd_ring; 727 728 /* REO command status ring */ 729 struct dp_srng reo_status_ring; 730 731 /* WBM Rx release ring */ 732 struct dp_srng rx_rel_ring; 733 734 /* Number of TCL data rings */ 735 uint8_t num_tcl_data_rings; 736 737 /* TCL data ring */ 738 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 739 740 /* TCL command ring */ 741 struct dp_srng tcl_cmd_ring; 742 743 /* TCL command status ring */ 744 struct dp_srng tcl_status_ring; 745 746 /* WBM Tx completion rings */ 747 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 748 749 /* Common WBM link descriptor release ring (SW to WBM) */ 750 struct dp_srng wbm_desc_rel_ring; 751 752 /* Tx ring map for interrupt processing */ 753 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 754 755 /* Rx ring map for interrupt processing */ 756 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 757 758 /* peer ID to peer object map (array of pointers to peer objects) */ 759 struct dp_peer **peer_id_to_obj_map; 760 761 struct { 762 unsigned mask; 763 unsigned idx_bits; 764 TAILQ_HEAD(, dp_peer) * bins; 765 } peer_hash; 766 767 /* rx defrag state – TBD: do we need this per radio? */ 768 struct { 769 struct { 770 TAILQ_HEAD(, dp_rx_tid) waitlist; 771 uint32_t timeout_ms; 772 qdf_spinlock_t defrag_lock; 773 } defrag; 774 struct { 775 int defrag_timeout_check; 776 int dup_check; 777 } flags; 778 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 779 qdf_spinlock_t reo_cmd_lock; 780 } rx; 781 782 /* optional rx processing function */ 783 void (*rx_opt_proc)( 784 struct dp_vdev *vdev, 785 struct dp_peer *peer, 786 unsigned tid, 787 qdf_nbuf_t msdu_list); 788 789 /* pool addr for mcast enhance buff */ 790 struct { 791 int size; 792 uint32_t paddr; 793 uint32_t *vaddr; 794 struct dp_tx_me_buf_t *freelist; 795 int buf_in_use; 796 qdf_dma_mem_context(memctx); 797 } me_buf; 798 799 /** 800 * peer ref mutex: 801 * 1. Protect peer object lookups until the returned peer object's 802 * reference count is incremented. 803 * 2. Provide mutex when accessing peer object lookup structures. 804 */ 805 DP_MUTEX_TYPE peer_ref_mutex; 806 807 /* maximum value for peer_id */ 808 uint32_t max_peers; 809 810 /* SoC level data path statistics */ 811 struct dp_soc_stats stats; 812 813 /* Enable processing of Tx completion status words */ 814 bool process_tx_status; 815 bool process_rx_status; 816 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 817 struct { 818 unsigned mask; 819 unsigned idx_bits; 820 TAILQ_HEAD(, dp_ast_entry) * bins; 821 } ast_hash; 822 823 qdf_spinlock_t ast_lock; 824 qdf_timer_t wds_aging_timer; 825 826 /*interrupt timer*/ 827 qdf_timer_t mon_reap_timer; 828 uint8_t reap_timer_init; 829 qdf_timer_t int_timer; 830 uint8_t intr_mode; 831 832 qdf_list_t reo_desc_freelist; 833 qdf_spinlock_t reo_desc_freelist_lock; 834 835 #ifdef QCA_SUPPORT_SON 836 /* The timer to check station's inactivity status */ 837 os_timer_t pdev_bs_inact_timer; 838 /* The current inactivity count reload value 839 based on overload condition */ 840 u_int16_t pdev_bs_inact_reload; 841 842 /* The inactivity timer value when not overloaded */ 843 u_int16_t pdev_bs_inact_normal; 844 845 /* The inactivity timer value when overloaded */ 846 u_int16_t pdev_bs_inact_overload; 847 848 /* The inactivity timer check interval */ 849 u_int16_t pdev_bs_inact_interval; 850 /* Inactivity timer */ 851 #endif /* QCA_SUPPORT_SON */ 852 853 /* htt stats */ 854 struct htt_t2h_stats htt_stats; 855 856 void *external_txrx_handle; /* External data path handle */ 857 #ifdef IPA_OFFLOAD 858 /* IPA uC datapath offload Wlan Tx resources */ 859 struct { 860 /* Resource info to be passed to IPA */ 861 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 862 void *ipa_tcl_ring_base_vaddr; 863 uint32_t ipa_tcl_ring_size; 864 qdf_dma_addr_t ipa_tcl_hp_paddr; 865 uint32_t alloc_tx_buf_cnt; 866 867 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 868 void *ipa_wbm_ring_base_vaddr; 869 uint32_t ipa_wbm_ring_size; 870 qdf_dma_addr_t ipa_wbm_tp_paddr; 871 872 /* TX buffers populated into the WBM ring */ 873 void **tx_buf_pool_vaddr_unaligned; 874 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 875 } ipa_uc_tx_rsc; 876 877 /* IPA uC datapath offload Wlan Rx resources */ 878 struct { 879 /* Resource info to be passed to IPA */ 880 qdf_dma_addr_t ipa_reo_ring_base_paddr; 881 void *ipa_reo_ring_base_vaddr; 882 uint32_t ipa_reo_ring_size; 883 qdf_dma_addr_t ipa_reo_tp_paddr; 884 885 /* Resource info to be passed to firmware and IPA */ 886 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 887 void *ipa_rx_refill_buf_ring_base_vaddr; 888 uint32_t ipa_rx_refill_buf_ring_size; 889 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 890 } ipa_uc_rx_rsc; 891 #endif 892 /* Device ID coming from Bus sub-system */ 893 uint32_t device_id; 894 }; 895 896 #ifdef IPA_OFFLOAD 897 /** 898 * dp_ipa_resources - Resources needed for IPA 899 */ 900 struct dp_ipa_resources { 901 qdf_dma_addr_t tx_ring_base_paddr; 902 uint32_t tx_ring_size; 903 uint32_t tx_num_alloc_buffer; 904 905 qdf_dma_addr_t tx_comp_ring_base_paddr; 906 uint32_t tx_comp_ring_size; 907 908 qdf_dma_addr_t rx_rdy_ring_base_paddr; 909 uint32_t rx_rdy_ring_size; 910 911 qdf_dma_addr_t rx_refill_ring_base_paddr; 912 uint32_t rx_refill_ring_size; 913 914 /* IPA UC doorbell registers paddr */ 915 qdf_dma_addr_t tx_comp_doorbell_paddr; 916 uint32_t *tx_comp_doorbell_vaddr; 917 qdf_dma_addr_t rx_ready_doorbell_paddr; 918 }; 919 #endif 920 921 #define MAX_RX_MAC_RINGS 2 922 /* Same as NAC_MAX_CLENT */ 923 #define DP_NAC_MAX_CLIENT 24 924 925 /* 926 * Macros to setup link descriptor cookies - for link descriptors, we just 927 * need first 3 bits to store bank ID. The remaining bytes will be used set a 928 * unique ID, which will be useful in debugging 929 */ 930 #define LINK_DESC_BANK_ID_MASK 0x7 931 #define LINK_DESC_ID_SHIFT 3 932 #define LINK_DESC_ID_START 0x8000 933 934 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 935 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 936 937 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 938 ((_cookie) & LINK_DESC_BANK_ID_MASK) 939 940 /* same as ieee80211_nac_param */ 941 enum dp_nac_param_cmd { 942 /* IEEE80211_NAC_PARAM_ADD */ 943 DP_NAC_PARAM_ADD = 1, 944 /* IEEE80211_NAC_PARAM_DEL */ 945 DP_NAC_PARAM_DEL, 946 /* IEEE80211_NAC_PARAM_LIST */ 947 DP_NAC_PARAM_LIST, 948 }; 949 950 /** 951 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 952 * @neighbour_peers_macaddr: neighbour peer's mac address 953 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 954 * @ast_entry: ast_entry for neighbour peer 955 * @rssi: rssi value 956 */ 957 struct dp_neighbour_peer { 958 /* MAC address of neighbour's peer */ 959 union dp_align_mac_addr neighbour_peers_macaddr; 960 struct dp_vdev *vdev; 961 struct dp_ast_entry *ast_entry; 962 uint8_t rssi; 963 /* node in the list of neighbour's peer */ 964 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 965 }; 966 967 /** 968 * struct ppdu_info - PPDU Status info descriptor 969 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 970 * @max_ppdu_id - wrap around for ppdu id 971 * @last_tlv_cnt - Keep track for missing ppdu tlvs 972 * @last_user - last ppdu processed for user 973 * @is_ampdu - set if Ampdu aggregate 974 * @nbuf - ppdu descriptor payload 975 * @ppdu_desc - ppdu descriptor 976 * @ppdu_info_list_elem - linked list of ppdu tlvs 977 */ 978 struct ppdu_info { 979 uint32_t ppdu_id; 980 uint32_t max_ppdu_id; 981 uint16_t tlv_bitmap; 982 uint16_t last_tlv_cnt; 983 uint16_t last_user:8, 984 is_ampdu:1; 985 qdf_nbuf_t nbuf; 986 struct cdp_tx_completion_ppdu *ppdu_desc; 987 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 988 }; 989 990 /* PDEV level structure for data path */ 991 struct dp_pdev { 992 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 993 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 994 995 /* PDEV Id */ 996 int pdev_id; 997 998 /* TXRX SOC handle */ 999 struct dp_soc *soc; 1000 1001 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1002 struct dp_srng rx_refill_buf_ring; 1003 1004 /* Second ring used to replenish rx buffers */ 1005 struct dp_srng rx_refill_buf_ring2; 1006 1007 /* Empty ring used by firmware to post rx buffers to the MAC */ 1008 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1009 1010 /* wlan_cfg pdev ctxt*/ 1011 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1012 1013 /* RXDMA monitor buffer replenish ring */ 1014 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1015 1016 /* RXDMA monitor destination ring */ 1017 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1018 1019 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1020 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1021 1022 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1023 1024 /* RXDMA error destination ring */ 1025 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1026 1027 /* Link descriptor memory banks */ 1028 struct { 1029 void *base_vaddr_unaligned; 1030 void *base_vaddr; 1031 qdf_dma_addr_t base_paddr_unaligned; 1032 qdf_dma_addr_t base_paddr; 1033 uint32_t size; 1034 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1035 1036 1037 /** 1038 * TODO: See if we need a ring map here for LMAC rings. 1039 * 1. Monitor rings are currently planning to be processed on receiving 1040 * PPDU end interrupts and hence wont need ring based interrupts. 1041 * 2. Rx buffer rings will be replenished during REO destination 1042 * processing and doesn't require regular interrupt handling - we will 1043 * only handle low water mark interrupts which is not expected 1044 * frequently 1045 */ 1046 1047 /* VDEV list */ 1048 TAILQ_HEAD(, dp_vdev) vdev_list; 1049 1050 /* vdev list lock */ 1051 qdf_spinlock_t vdev_list_lock; 1052 1053 /* Number of vdevs this device have */ 1054 uint16_t vdev_count; 1055 1056 /* PDEV transmit lock */ 1057 qdf_spinlock_t tx_lock; 1058 1059 #ifndef REMOVE_PKT_LOG 1060 bool pkt_log_init; 1061 /* Pktlog pdev */ 1062 struct pktlog_dev_t *pl_dev; 1063 #endif /* #ifndef REMOVE_PKT_LOG */ 1064 1065 /* Monitor mode interface and status storage */ 1066 struct dp_vdev *monitor_vdev; 1067 1068 /* monitor mode lock */ 1069 qdf_spinlock_t mon_lock; 1070 1071 /*tx_mutex for me*/ 1072 DP_MUTEX_TYPE tx_mutex; 1073 1074 /* Smart Mesh */ 1075 bool filter_neighbour_peers; 1076 1077 /*flag to indicate neighbour_peers_list not empty */ 1078 bool neighbour_peers_added; 1079 /* smart mesh mutex */ 1080 qdf_spinlock_t neighbour_peer_mutex; 1081 /* Neighnour peer list */ 1082 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1083 /* msdu chain head & tail */ 1084 qdf_nbuf_t invalid_peer_head_msdu; 1085 qdf_nbuf_t invalid_peer_tail_msdu; 1086 1087 /* Band steering */ 1088 /* TBD */ 1089 1090 /* PDEV level data path statistics */ 1091 struct cdp_pdev_stats stats; 1092 1093 /* Global RX decap mode for the device */ 1094 enum htt_pkt_type rx_decap_mode; 1095 1096 /* Enhanced Stats is enabled */ 1097 bool enhanced_stats_en; 1098 1099 /* advance filter mode and type*/ 1100 uint8_t mon_filter_mode; 1101 uint16_t fp_mgmt_filter; 1102 uint16_t fp_ctrl_filter; 1103 uint16_t fp_data_filter; 1104 uint16_t mo_mgmt_filter; 1105 uint16_t mo_ctrl_filter; 1106 uint16_t mo_data_filter; 1107 1108 qdf_atomic_t num_tx_outstanding; 1109 1110 qdf_atomic_t num_tx_exception; 1111 1112 /* MCL specific local peer handle */ 1113 struct { 1114 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1115 uint8_t freelist; 1116 qdf_spinlock_t lock; 1117 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1118 } local_peer_ids; 1119 1120 /* dscp_tid_map_*/ 1121 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1122 1123 struct hal_rx_ppdu_info ppdu_info; 1124 1125 /* operating channel */ 1126 uint8_t operating_channel; 1127 1128 qdf_nbuf_queue_t rx_status_q; 1129 uint32_t mon_ppdu_status; 1130 struct cdp_mon_status rx_mon_recv_status; 1131 /* monitor mode status/destination ring PPDU and MPDU count */ 1132 struct cdp_pdev_mon_stats rx_mon_stats; 1133 1134 /* pool addr for mcast enhance buff */ 1135 struct { 1136 int size; 1137 uint32_t paddr; 1138 char *vaddr; 1139 struct dp_tx_me_buf_t *freelist; 1140 int buf_in_use; 1141 qdf_dma_mem_context(memctx); 1142 } me_buf; 1143 1144 /* Number of VAPs with mcast enhancement enabled */ 1145 qdf_atomic_t mc_num_vap_attached; 1146 1147 qdf_atomic_t stats_cmd_complete; 1148 1149 #ifdef IPA_OFFLOAD 1150 ipa_uc_op_cb_type ipa_uc_op_cb; 1151 void *usr_ctxt; 1152 struct dp_ipa_resources ipa_resource; 1153 #endif 1154 1155 /* TBD */ 1156 1157 /* map this pdev to a particular Reo Destination ring */ 1158 enum cdp_host_reo_dest_ring reo_dest; 1159 1160 #ifndef REMOVE_PKT_LOG 1161 /* Packet log mode */ 1162 uint8_t rx_pktlog_mode; 1163 #endif 1164 1165 /* WDI event handlers */ 1166 struct wdi_event_subscribe_t **wdi_event_list; 1167 1168 /* ppdu_id of last received HTT TX stats */ 1169 uint32_t last_ppdu_id; 1170 struct { 1171 uint8_t last_user; 1172 qdf_nbuf_t buf; 1173 } tx_ppdu_info; 1174 1175 bool tx_sniffer_enable; 1176 /* mirror copy mode */ 1177 bool mcopy_mode; 1178 bool bpr_enable; 1179 struct { 1180 uint16_t tx_ppdu_id; 1181 uint16_t tx_peer_id; 1182 uint16_t rx_ppdu_id; 1183 } m_copy_id; 1184 1185 /* To check if PPDU Tx stats are enabled for Pktlog */ 1186 bool pktlog_ppdu_stats; 1187 1188 void *dp_txrx_handle; /* Advanced data path handle */ 1189 1190 #ifdef ATH_SUPPORT_NAC_RSSI 1191 bool nac_rssi_filtering; 1192 #endif 1193 /* list of ppdu tlvs */ 1194 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1195 uint32_t tlv_count; 1196 uint32_t list_depth; 1197 uint32_t ppdu_id; 1198 bool first_nbuf; 1199 struct { 1200 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1201 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1202 uint32_t ppdu_id; 1203 } mgmtctrl_frm_info; 1204 /* Current noise-floor reading for the pdev channel */ 1205 int16_t chan_noise_floor; 1206 }; 1207 1208 struct dp_peer; 1209 1210 /* VDEV structure for data path state */ 1211 struct dp_vdev { 1212 /* OS device abstraction */ 1213 qdf_device_t osdev; 1214 /* physical device that is the parent of this virtual device */ 1215 struct dp_pdev *pdev; 1216 1217 /* Handle to the OS shim SW's virtual device */ 1218 ol_osif_vdev_handle osif_vdev; 1219 1220 /* Handle to the UMAC handle */ 1221 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1222 /* vdev_id - ID used to specify a particular vdev to the target */ 1223 uint8_t vdev_id; 1224 1225 /* MAC address */ 1226 union dp_align_mac_addr mac_addr; 1227 1228 /* node in the pdev's list of vdevs */ 1229 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1230 1231 /* dp_peer list */ 1232 TAILQ_HEAD(, dp_peer) peer_list; 1233 1234 /* callback to hand rx frames to the OS shim */ 1235 ol_txrx_rx_fp osif_rx; 1236 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1237 ol_txrx_get_key_fp osif_get_key; 1238 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1239 1240 #ifdef notyet 1241 /* callback to check if the msdu is an WAI (WAPI) frame */ 1242 ol_rx_check_wai_fp osif_check_wai; 1243 #endif 1244 1245 /* proxy arp function */ 1246 ol_txrx_proxy_arp_fp osif_proxy_arp; 1247 1248 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1249 ol_txrx_rx_mon_fp osif_rx_mon; 1250 1251 ol_txrx_mcast_me_fp me_convert; 1252 1253 /* completion function used by this vdev*/ 1254 ol_txrx_completion_fp tx_comp; 1255 1256 /* deferred vdev deletion state */ 1257 struct { 1258 /* VDEV delete pending */ 1259 int pending; 1260 /* 1261 * callback and a context argument to provide a 1262 * notification for when the vdev is deleted. 1263 */ 1264 ol_txrx_vdev_delete_cb callback; 1265 void *context; 1266 } delete; 1267 1268 /* tx data delivery notification callback function */ 1269 struct { 1270 ol_txrx_data_tx_cb func; 1271 void *ctxt; 1272 } tx_non_std_data_callback; 1273 1274 1275 /* safe mode control to bypass the encrypt and decipher process*/ 1276 uint32_t safemode; 1277 1278 /* rx filter related */ 1279 uint32_t drop_unenc; 1280 #ifdef notyet 1281 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1282 uint32_t filters_num; 1283 #endif 1284 /* TDLS Link status */ 1285 bool tdls_link_connected; 1286 bool is_tdls_frame; 1287 1288 1289 /* VDEV operating mode */ 1290 enum wlan_op_mode opmode; 1291 1292 /* Tx encapsulation type for this VAP */ 1293 enum htt_cmn_pkt_type tx_encap_type; 1294 /* Rx Decapsulation type for this VAP */ 1295 enum htt_cmn_pkt_type rx_decap_type; 1296 1297 /* BSS peer */ 1298 struct dp_peer *vap_bss_peer; 1299 1300 /* WDS enabled */ 1301 bool wds_enabled; 1302 1303 /* WDS Aging timer period */ 1304 uint32_t wds_aging_timer_val; 1305 1306 /* NAWDS enabled */ 1307 bool nawds_enabled; 1308 1309 /* Default HTT meta data for this VDEV */ 1310 /* TBD: check alignment constraints */ 1311 uint16_t htt_tcl_metadata; 1312 1313 /* Mesh mode vdev */ 1314 uint32_t mesh_vdev; 1315 1316 /* Mesh mode rx filter setting */ 1317 uint32_t mesh_rx_filter; 1318 1319 /* DSCP-TID mapping table ID */ 1320 uint8_t dscp_tid_map_id; 1321 1322 /* Multicast enhancement enabled */ 1323 uint8_t mcast_enhancement_en; 1324 1325 /* per vdev rx nbuf queue */ 1326 qdf_nbuf_queue_t rxq; 1327 1328 uint8_t tx_ring_id; 1329 struct dp_tx_desc_pool_s *tx_desc; 1330 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1331 1332 /* VDEV Stats */ 1333 struct cdp_vdev_stats stats; 1334 bool lro_enable; 1335 1336 /* Is this a proxySTA VAP */ 1337 bool proxysta_vdev; 1338 /* Is isolation mode enabled */ 1339 bool isolation_vdev; 1340 1341 /* Address search flags to be configured in HAL descriptor */ 1342 uint8_t hal_desc_addr_search_flags; 1343 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1344 struct dp_tx_desc_pool_s *pool; 1345 #endif 1346 /* AP BRIDGE enabled */ 1347 uint32_t ap_bridge_enabled; 1348 1349 enum cdp_sec_type sec_type; 1350 }; 1351 1352 1353 enum { 1354 dp_sec_mcast = 0, 1355 dp_sec_ucast 1356 }; 1357 1358 #ifdef WDS_VENDOR_EXTENSION 1359 typedef struct { 1360 uint8_t wds_tx_mcast_4addr:1, 1361 wds_tx_ucast_4addr:1, 1362 wds_rx_filter:1, /* enforce rx filter */ 1363 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1364 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1365 1366 } dp_ecm_policy; 1367 #endif 1368 1369 /* Peer structure for data path state */ 1370 struct dp_peer { 1371 /* VDEV to which this peer is associated */ 1372 struct dp_vdev *vdev; 1373 1374 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1375 1376 struct dp_ast_entry *self_ast_entry; 1377 1378 qdf_atomic_t ref_cnt; 1379 1380 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1381 /* peer ID(s) for this peer */ 1382 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1383 1384 union dp_align_mac_addr mac_addr; 1385 1386 /* node in the vdev's list of peers */ 1387 TAILQ_ENTRY(dp_peer) peer_list_elem; 1388 /* node in the hash table bin's list of peers */ 1389 TAILQ_ENTRY(dp_peer) hash_list_elem; 1390 1391 /* TID structures */ 1392 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1393 1394 /* TBD: No transmit TID state required? */ 1395 1396 struct { 1397 enum htt_sec_type sec_type; 1398 u_int32_t michael_key[2]; /* relevant for TKIP */ 1399 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1400 1401 /* 1402 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1403 * regular rx processing, or has been redirected to a /dev/null discard 1404 * function when peer deletion is in progress. 1405 */ 1406 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1407 unsigned tid, qdf_nbuf_t msdu_list); 1408 1409 /* set when node is authorized */ 1410 uint8_t authorize:1; 1411 1412 u_int8_t nac; 1413 1414 /* Band steering: Set when node is inactive */ 1415 uint8_t peer_bs_inact_flag:1; 1416 u_int16_t peer_bs_inact; /* inactivity mark count */ 1417 1418 /* NAWDS Flag and Bss Peer bit */ 1419 uint8_t nawds_enabled:1, 1420 bss_peer:1, 1421 wapi:1, 1422 wds_enabled:1; 1423 1424 /* MCL specific peer local id */ 1425 uint16_t local_id; 1426 enum ol_txrx_peer_state state; 1427 qdf_spinlock_t peer_info_lock; 1428 1429 qdf_time_t last_assoc_rcvd; 1430 qdf_time_t last_disassoc_rcvd; 1431 qdf_time_t last_deauth_rcvd; 1432 /* Peer Stats */ 1433 struct cdp_peer_stats stats; 1434 1435 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1436 /* TBD */ 1437 1438 #ifdef WDS_VENDOR_EXTENSION 1439 dp_ecm_policy wds_ecm; 1440 #endif 1441 bool delete_in_progress; 1442 }; 1443 1444 #ifdef CONFIG_WIN 1445 /* 1446 * dp_invalid_peer_msg 1447 * @nbuf: data buffer 1448 * @wh: 802.11 header 1449 * @vdev_id: id of vdev 1450 */ 1451 struct dp_invalid_peer_msg { 1452 qdf_nbuf_t nbuf; 1453 struct ieee80211_frame *wh; 1454 uint8_t vdev_id; 1455 }; 1456 #endif 1457 1458 /* 1459 * dp_tx_me_buf_t: ME buffer 1460 * next: pointer to next buffer 1461 * data: Destination Mac address 1462 */ 1463 struct dp_tx_me_buf_t { 1464 /* Note: ME buf pool initialization logic expects next pointer to 1465 * be the first element. Dont add anything before next */ 1466 struct dp_tx_me_buf_t *next; 1467 uint8_t data[DP_MAC_ADDR_LEN]; 1468 }; 1469 1470 #endif /* _DP_TYPES_H_ */ 1471