1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DP_TYPES_H_ 20 #define _DP_TYPES_H_ 21 22 #include <qdf_types.h> 23 #include <qdf_nbuf.h> 24 #include <qdf_lock.h> 25 #include <qdf_atomic.h> 26 #include <qdf_util.h> 27 #include <qdf_list.h> 28 #include <qdf_lro.h> 29 #include <queue.h> 30 #include <htt_common.h> 31 32 #include <cdp_txrx_cmn.h> 33 #ifdef CONFIG_MCL 34 #include <cds_ieee80211_common.h> 35 #else 36 #include <linux/ieee80211.h> 37 #endif 38 39 #ifndef CONFIG_WIN 40 #include <wdi_event_api.h> /* WDI subscriber event list */ 41 #endif 42 43 #include "hal_hw_headers.h" 44 #include <hal_tx.h> 45 #include <hal_reo.h> 46 #include "wlan_cfg.h" 47 #include "hal_rx.h" 48 #include <hal_api.h> 49 #include <hal_api_mon.h> 50 #include "hal_rx.h" 51 52 #define MAX_BW 7 53 #define MAX_RETRIES 4 54 #define MAX_RECEPTION_TYPES 4 55 56 #ifndef REMOVE_PKT_LOG 57 #include <pktlog.h> 58 #endif 59 60 #define REPT_MU_MIMO 1 61 #define REPT_MU_OFDMA_MIMO 3 62 #define DP_VO_TID 6 63 64 #define DP_MAX_INTERRUPT_CONTEXTS 8 65 #define DP_MAX_TID_MAPS 16 /* MAX TID MAPS AVAILABLE PER PDEV*/ 66 #define DSCP_TID_MAP_MAX (64) 67 #define DP_IP_DSCP_SHIFT 2 68 #define DP_IP_DSCP_MASK 0x3f 69 #define DP_FC0_SUBTYPE_QOS 0x80 70 #define DP_QOS_TID 0x0f 71 #define DP_IPV6_PRIORITY_SHIFT 20 72 #define MAX_MON_LINK_DESC_BANKS 2 73 #define DP_VDEV_ALL 0xff 74 75 #if defined(CONFIG_MCL) 76 #define MAX_PDEV_CNT 1 77 #else 78 #define MAX_PDEV_CNT 3 79 #endif 80 81 #define MAX_LINK_DESC_BANKS 8 82 #define MAX_TXDESC_POOLS 4 83 #define MAX_RXDESC_POOLS 4 84 #define MAX_REO_DEST_RINGS 4 85 #define MAX_TCL_DATA_RINGS 4 86 #define MAX_IDLE_SCATTER_BUFS 16 87 #define DP_MAX_IRQ_PER_CONTEXT 12 88 #define DP_MAX_INTERRUPT_CONTEXTS 8 89 #define DEFAULT_HW_PEER_ID 0xffff 90 91 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 92 93 #define DP_MAX_INTERRUPT_CONTEXTS 8 94 95 /* Maximum retries for Delba per tid per peer */ 96 #define DP_MAX_DELBA_RETRY 3 97 98 #ifndef REMOVE_PKT_LOG 99 enum rx_pktlog_mode { 100 DP_RX_PKTLOG_DISABLED = 0, 101 DP_RX_PKTLOG_FULL, 102 DP_RX_PKTLOG_LITE, 103 }; 104 #endif 105 106 struct dp_soc_cmn; 107 struct dp_pdev; 108 struct dp_vdev; 109 struct dp_tx_desc_s; 110 struct dp_soc; 111 union dp_rx_desc_list_elem_t; 112 113 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 114 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 115 116 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 117 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 118 119 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 120 TAILQ_FOREACH_SAFE((_ase), &peer->ast_entry_list, ase_list_elem, (_temp_ase)) 121 122 #define DP_MUTEX_TYPE qdf_spinlock_t 123 124 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 125 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 126 127 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 128 ((_a)[0] == 0x33 && \ 129 (_a)[1] == 0x33) 130 131 #define DP_FRAME_IS_BROADCAST(_a) \ 132 ((_a)[0] == 0xff && \ 133 (_a)[1] == 0xff && \ 134 (_a)[2] == 0xff && \ 135 (_a)[3] == 0xff && \ 136 (_a)[4] == 0xff && \ 137 (_a)[5] == 0xff) 138 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 139 (_llc)->llc_ssap == 0xaa && \ 140 (_llc)->llc_un.type_snap.control == 0x3) 141 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 142 #define DP_FRAME_FC0_TYPE_MASK 0x0c 143 #define DP_FRAME_FC0_TYPE_DATA 0x08 144 #define DP_FRAME_IS_DATA(_frame) \ 145 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 146 147 /** 148 * macros to convert hw mac id to sw mac id: 149 * mac ids used by hardware start from a value of 1 while 150 * those in host software start from a value of 0. Use the 151 * macros below to convert between mac ids used by software and 152 * hardware 153 */ 154 #define DP_SW2HW_MACID(id) ((id) + 1) 155 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 156 #define DP_MAC_ADDR_LEN 6 157 158 /** 159 * enum dp_intr_mode 160 * @DP_INTR_LEGACY: Legacy/Line interrupts, for WIN 161 * @DP_INTR_MSI: MSI interrupts, for MCL 162 * @DP_INTR_POLL: Polling 163 */ 164 enum dp_intr_mode { 165 DP_INTR_LEGACY = 0, 166 DP_INTR_MSI, 167 DP_INTR_POLL, 168 }; 169 170 /** 171 * enum dp_tx_frm_type 172 * @dp_tx_frm_std: Regular frame, no added header fragments 173 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 174 * @dp_tx_frm_sg: SG segment 175 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 176 * @dp_tx_frm_me: Multicast to Unicast Converted frame 177 * @dp_tx_frm_raw: Raw Frame 178 */ 179 enum dp_tx_frm_type { 180 dp_tx_frm_std = 0, 181 dp_tx_frm_tso, 182 dp_tx_frm_sg, 183 dp_tx_frm_audio, 184 dp_tx_frm_me, 185 dp_tx_frm_raw, 186 }; 187 188 /** 189 * enum dp_ast_type 190 * @dp_ast_type_wds: WDS peer AST type 191 * @dp_ast_type_static: static ast entry type 192 * @dp_ast_type_mec: Multicast echo ast entry type 193 */ 194 enum dp_ast_type { 195 dp_ast_type_wds = 0, 196 dp_ast_type_static, 197 dp_ast_type_mec, 198 }; 199 200 /** 201 * enum dp_nss_cfg 202 * @dp_nss_cfg_default: No radios are offloaded 203 * @dp_nss_cfg_first_radio: First radio offloaded 204 * @dp_nss_cfg_second_radio: Second radio offloaded 205 * @dp_nss_cfg_dbdc: Dual radios offloaded 206 */ 207 enum dp_nss_cfg { 208 dp_nss_cfg_default, 209 dp_nss_cfg_first_radio, 210 dp_nss_cfg_second_radio, 211 dp_nss_cfg_dbdc, 212 }; 213 214 /** 215 * struct rx_desc_pool 216 * @pool_size: number of RX descriptor in the pool 217 * @array: pointer to array of RX descriptor 218 * @freelist: pointer to free RX descriptor link list 219 * @lock: Protection for the RX descriptor pool 220 * @owner: owner for nbuf 221 */ 222 struct rx_desc_pool { 223 uint32_t pool_size; 224 union dp_rx_desc_list_elem_t *array; 225 union dp_rx_desc_list_elem_t *freelist; 226 qdf_spinlock_t lock; 227 uint8_t owner; 228 }; 229 230 /** 231 * struct dp_tx_ext_desc_elem_s 232 * @next: next extension descriptor pointer 233 * @vaddr: hlos virtual address pointer 234 * @paddr: physical address pointer for descriptor 235 */ 236 struct dp_tx_ext_desc_elem_s { 237 struct dp_tx_ext_desc_elem_s *next; 238 void *vaddr; 239 qdf_dma_addr_t paddr; 240 }; 241 242 /** 243 * struct dp_tx_ext_desc_s - Tx Extension Descriptor Pool 244 * @elem_count: Number of descriptors in the pool 245 * @elem_size: Size of each descriptor 246 * @num_free: Number of free descriptors 247 * @msdu_ext_desc: MSDU extension descriptor 248 * @desc_pages: multiple page allocation information for actual descriptors 249 * @link_elem_size: size of the link descriptor in cacheable memory used for 250 * chaining the extension descriptors 251 * @desc_link_pages: multiple page allocation information for link descriptors 252 */ 253 struct dp_tx_ext_desc_pool_s { 254 uint16_t elem_count; 255 int elem_size; 256 uint16_t num_free; 257 struct qdf_mem_multi_page_t desc_pages; 258 int link_elem_size; 259 struct qdf_mem_multi_page_t desc_link_pages; 260 struct dp_tx_ext_desc_elem_s *freelist; 261 qdf_spinlock_t lock; 262 qdf_dma_mem_context(memctx); 263 }; 264 265 /** 266 * struct dp_tx_desc_s - Tx Descriptor 267 * @next: Next in the chain of descriptors in freelist or in the completion list 268 * @nbuf: Buffer Address 269 * @msdu_ext_desc: MSDU extension descriptor 270 * @id: Descriptor ID 271 * @vdev: vdev over which the packet was transmitted 272 * @pdev: Handle to pdev 273 * @pool_id: Pool ID - used when releasing the descriptor 274 * @flags: Flags to track the state of descriptor and special frame handling 275 * @comp: Pool ID - used when releasing the descriptor 276 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 277 * This is maintained in descriptor to allow more efficient 278 * processing in completion event processing code. 279 * This field is filled in with the htt_pkt_type enum. 280 * @frm_type: Frame Type - ToDo check if this is redundant 281 * @pkt_offset: Offset from which the actual packet data starts 282 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 283 * Tx completion of ME packet 284 * @pool: handle to flow_pool this descriptor belongs to. 285 */ 286 struct dp_tx_desc_s { 287 struct dp_tx_desc_s *next; 288 qdf_nbuf_t nbuf; 289 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 290 uint32_t id; 291 struct dp_vdev *vdev; 292 struct dp_pdev *pdev; 293 uint8_t pool_id; 294 uint16_t flags; 295 struct hal_tx_desc_comp_s comp; 296 uint16_t tx_encap_type; 297 uint8_t frm_type; 298 uint8_t pkt_offset; 299 void *me_buffer; 300 void *tso_desc; 301 void *tso_num_desc; 302 uint64_t timestamp; 303 }; 304 305 /** 306 * enum flow_pool_status - flow pool status 307 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 308 * and network queues are unpaused 309 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 310 * and network queues are paused 311 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 312 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 313 */ 314 enum flow_pool_status { 315 FLOW_POOL_ACTIVE_UNPAUSED = 0, 316 FLOW_POOL_ACTIVE_PAUSED = 1, 317 FLOW_POOL_INVALID = 2, 318 FLOW_POOL_INACTIVE = 3, 319 }; 320 321 /** 322 * struct dp_tx_tso_seg_pool_s 323 * @pool_size: total number of pool elements 324 * @num_free: free element count 325 * @freelist: first free element pointer 326 * @desc_pages: multiple page allocation information for actual descriptors 327 * @lock: lock for accessing the pool 328 */ 329 struct dp_tx_tso_seg_pool_s { 330 uint16_t pool_size; 331 uint16_t num_free; 332 struct qdf_tso_seg_elem_t *freelist; 333 struct qdf_mem_multi_page_t desc_pages; 334 qdf_spinlock_t lock; 335 }; 336 337 /** 338 * struct dp_tx_tso_num_seg_pool_s { 339 * @num_seg_pool_size: total number of pool elements 340 * @num_free: free element count 341 * @freelist: first free element pointer 342 * @desc_pages: multiple page allocation information for actual descriptors 343 * @lock: lock for accessing the pool 344 */ 345 346 struct dp_tx_tso_num_seg_pool_s { 347 uint16_t num_seg_pool_size; 348 uint16_t num_free; 349 struct qdf_tso_num_seg_elem_t *freelist; 350 struct qdf_mem_multi_page_t desc_pages; 351 /*tso mutex */ 352 qdf_spinlock_t lock; 353 }; 354 355 /** 356 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 357 * @elem_size: Size of each descriptor in the pool 358 * @pool_size: Total number of descriptors in the pool 359 * @num_free: Number of free descriptors 360 * @num_allocated: Number of used descriptors 361 * @freelist: Chain of free descriptors 362 * @desc_pages: multiple page allocation information for actual descriptors 363 * @num_invalid_bin: Deleted pool with pending Tx completions. 364 * @flow_pool_array_lock: Lock when operating on flow_pool_array. 365 * @flow_pool_array: List of allocated flow pools 366 * @lock- Lock for descriptor allocation/free from/to the pool 367 */ 368 struct dp_tx_desc_pool_s { 369 uint16_t elem_size; 370 uint32_t num_allocated; 371 struct dp_tx_desc_s *freelist; 372 struct qdf_mem_multi_page_t desc_pages; 373 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 374 uint16_t pool_size; 375 uint8_t flow_pool_id; 376 uint8_t num_invalid_bin; 377 uint16_t avail_desc; 378 enum flow_pool_status status; 379 enum htt_flow_type flow_type; 380 uint16_t stop_th; 381 uint16_t start_th; 382 uint16_t pkt_drop_no_desc; 383 qdf_spinlock_t flow_pool_lock; 384 uint8_t pool_create_cnt; 385 void *pool_owner_ctx; 386 #else 387 uint16_t elem_count; 388 uint32_t num_free; 389 qdf_spinlock_t lock; 390 #endif 391 }; 392 393 /** 394 * struct dp_txrx_pool_stats - flow pool related statistics 395 * @pool_map_count: flow pool map received 396 * @pool_unmap_count: flow pool unmap received 397 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 398 */ 399 struct dp_txrx_pool_stats { 400 uint16_t pool_map_count; 401 uint16_t pool_unmap_count; 402 uint16_t pkt_drop_no_pool; 403 }; 404 405 struct dp_srng { 406 void *hal_srng; 407 void *base_vaddr_unaligned; 408 qdf_dma_addr_t base_paddr_unaligned; 409 uint32_t alloc_size; 410 int irq; 411 uint32_t num_entries; 412 }; 413 414 struct dp_rx_reorder_array_elem { 415 qdf_nbuf_t head; 416 qdf_nbuf_t tail; 417 }; 418 419 #define DP_RX_BA_INACTIVE 0 420 #define DP_RX_BA_ACTIVE 1 421 #define DP_RX_BA_IN_PROGRESS 2 422 struct dp_reo_cmd_info { 423 uint16_t cmd; 424 enum hal_reo_cmd_type cmd_type; 425 void *data; 426 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 427 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 428 }; 429 430 /* Rx TID */ 431 struct dp_rx_tid { 432 /* TID */ 433 int tid; 434 435 /* Num of addba requests */ 436 uint32_t num_of_addba_req; 437 438 /* Num of addba responses */ 439 uint32_t num_of_addba_resp; 440 441 /* Num of delba requests */ 442 uint32_t num_of_delba_req; 443 444 /* Num of addba responses successful */ 445 uint32_t num_addba_rsp_success; 446 447 /* Num of addba responses failed */ 448 uint32_t num_addba_rsp_failed; 449 450 /* pn size */ 451 uint8_t pn_size; 452 /* REO TID queue descriptors */ 453 void *hw_qdesc_vaddr_unaligned; 454 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 455 qdf_dma_addr_t hw_qdesc_paddr; 456 uint32_t hw_qdesc_alloc_size; 457 458 /* RX ADDBA session state */ 459 int ba_status; 460 461 /* RX BA window size */ 462 uint16_t ba_win_size; 463 464 /* Starting sequence number in Addba request */ 465 uint16_t startseqnum; 466 467 /* TODO: Check the following while adding defragmentation support */ 468 struct dp_rx_reorder_array_elem *array; 469 /* base - single rx reorder element used for non-aggr cases */ 470 struct dp_rx_reorder_array_elem base; 471 472 /* only used for defrag right now */ 473 TAILQ_ENTRY(dp_rx_tid) defrag_waitlist_elem; 474 475 /* Store dst desc for reinjection */ 476 void *dst_ring_desc; 477 struct dp_rx_desc *head_frag_desc; 478 479 /* rx_tid lock */ 480 qdf_spinlock_t tid_lock; 481 482 /* Sequence and fragments that are being processed currently */ 483 uint32_t curr_seq_num; 484 uint32_t curr_frag_num; 485 486 uint32_t defrag_timeout_ms; 487 uint16_t dialogtoken; 488 uint16_t statuscode; 489 /* user defined ADDBA response status code */ 490 uint16_t userstatuscode; 491 492 /* Store ppdu_id when 2k exception is received */ 493 uint32_t ppdu_id_2k; 494 495 /* Delba Tx completion status */ 496 uint8_t delba_tx_status; 497 498 /* Delba Tx retry count */ 499 uint8_t delba_tx_retry; 500 501 /* Delba stats */ 502 uint32_t delba_tx_success_cnt; 503 uint32_t delba_tx_fail_cnt; 504 505 /* Delba reason code for retries */ 506 uint8_t delba_rcode; 507 508 }; 509 510 /* per interrupt context */ 511 struct dp_intr { 512 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 513 associated with this napi context */ 514 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 515 with this interrupt context */ 516 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 517 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 518 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 519 uint8_t reo_status_ring_mask; /* REO command response ring */ 520 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 521 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 522 struct dp_soc *soc; /* Reference to SoC structure , 523 to get DMA ring handles */ 524 qdf_lro_ctx_t lro_ctx; 525 uint8_t dp_intr_id; 526 }; 527 528 #define REO_DESC_FREELIST_SIZE 64 529 #define REO_DESC_FREE_DEFER_MS 1000 530 struct reo_desc_list_node { 531 qdf_list_node_t node; 532 unsigned long free_ts; 533 struct dp_rx_tid rx_tid; 534 }; 535 536 /* SoC level data path statistics */ 537 struct dp_soc_stats { 538 struct { 539 uint32_t added; 540 uint32_t deleted; 541 uint32_t aged_out; 542 } ast; 543 544 /* SOC level TX stats */ 545 struct { 546 /* packets dropped on tx because of no peer */ 547 struct cdp_pkt_info tx_invalid_peer; 548 /* descriptors in each tcl ring */ 549 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 550 /* Descriptors in use at soc */ 551 uint32_t desc_in_use; 552 /* tqm_release_reason == FW removed */ 553 uint32_t dropped_fw_removed; 554 555 } tx; 556 557 /* SOC level RX stats */ 558 struct { 559 /* Rx errors */ 560 /* Total Packets in Rx Error ring */ 561 uint32_t err_ring_pkts; 562 /* No of Fragments */ 563 uint32_t rx_frags; 564 /* No of reinjected packets */ 565 uint32_t reo_reinject; 566 struct { 567 /* Invalid RBM error count */ 568 uint32_t invalid_rbm; 569 /* Invalid VDEV Error count */ 570 uint32_t invalid_vdev; 571 /* Invalid PDEV error count */ 572 uint32_t invalid_pdev; 573 /* Invalid PEER Error count */ 574 struct cdp_pkt_info rx_invalid_peer; 575 /* HAL ring access Fail error count */ 576 uint32_t hal_ring_access_fail; 577 /* RX DMA error count */ 578 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 579 /* REO Error count */ 580 uint32_t reo_error[HAL_REO_ERR_MAX]; 581 /* HAL REO ERR Count */ 582 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 583 } err; 584 585 /* packet count per core - per ring */ 586 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 587 } rx; 588 }; 589 590 #define DP_MAC_ADDR_LEN 6 591 union dp_align_mac_addr { 592 uint8_t raw[DP_MAC_ADDR_LEN]; 593 struct { 594 uint16_t bytes_ab; 595 uint16_t bytes_cd; 596 uint16_t bytes_ef; 597 } align2; 598 struct { 599 uint32_t bytes_abcd; 600 uint16_t bytes_ef; 601 } align4; 602 struct __attribute__((__packed__)) { 603 uint16_t bytes_ab; 604 uint32_t bytes_cdef; 605 } align4_2; 606 }; 607 608 /* 609 * dp_ast_entry 610 * 611 * @ast_idx: Hardware AST Index 612 * @mac_addr: MAC Address for this AST entry 613 * @peer: Next Hop peer (for non-WDS nodes, this will be point to 614 * associated peer with this MAC address) 615 * @next_hop: Set to 1 if this is for a WDS node 616 * @is_active: flag to indicate active data traffic on this node 617 * (used for aging out/expiry) 618 * @ase_list_elem: node in peer AST list 619 * @is_bss: flag to indicate if entry corresponds to bss peer 620 * @pdev_id: pdev ID 621 * @vdev_id: vdev ID 622 * @ast_hash_value: hast value in HW 623 * @ref_cnt: reference count 624 * @type: flag to indicate type of the entry(static/WDS/MEC) 625 * @wmi_sent: Flag to identify of WMI to del ast is sent (AST_HKV1_WORKAROUND) 626 * @cp_ctx: Opaque context used by control path (AST_HKV1_WORKAROUND) 627 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 628 */ 629 struct dp_ast_entry { 630 uint16_t ast_idx; 631 /* MAC address */ 632 union dp_align_mac_addr mac_addr; 633 struct dp_peer *peer; 634 bool next_hop; 635 bool is_active; 636 bool is_bss; 637 uint8_t pdev_id; 638 uint8_t vdev_id; 639 uint16_t ast_hash_value; 640 qdf_atomic_t ref_cnt; 641 enum cdp_txrx_ast_entry_type type; 642 #ifdef AST_HKV1_WORKAROUND 643 bool wmi_sent; 644 void *cp_ctx; 645 #endif 646 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 647 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 648 }; 649 650 /* SOC level htt stats */ 651 struct htt_t2h_stats { 652 /* lock to protect htt_stats_msg update */ 653 qdf_spinlock_t lock; 654 655 /* work queue to process htt stats */ 656 qdf_work_t work; 657 658 /* T2H Ext stats message queue */ 659 qdf_nbuf_queue_t msg; 660 661 /* number of completed stats in htt_stats_msg */ 662 uint32_t num_stats; 663 }; 664 665 /* SOC level structure for data path */ 666 struct dp_soc { 667 /* Common base structure - Should be the first member */ 668 struct cdp_soc_t cdp_soc; 669 670 /* SoC Obj */ 671 void *ctrl_psoc; 672 673 /* OS device abstraction */ 674 qdf_device_t osdev; 675 676 /* WLAN config context */ 677 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 678 679 /* HTT handle for host-fw interaction */ 680 void *htt_handle; 681 682 /* Commint init done */ 683 qdf_atomic_t cmn_init_done; 684 685 /* Opaque hif handle */ 686 struct hif_opaque_softc *hif_handle; 687 688 /* PDEVs on this SOC */ 689 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 690 691 /* Number of PDEVs */ 692 uint8_t pdev_count; 693 694 /*cce disable*/ 695 bool cce_disable; 696 697 /*ast override support in HW*/ 698 bool ast_override_support; 699 700 /*number of hw dscp tid map*/ 701 uint8_t num_hw_dscp_tid_map; 702 703 /* Link descriptor memory banks */ 704 struct { 705 void *base_vaddr_unaligned; 706 void *base_vaddr; 707 qdf_dma_addr_t base_paddr_unaligned; 708 qdf_dma_addr_t base_paddr; 709 uint32_t size; 710 } link_desc_banks[MAX_LINK_DESC_BANKS]; 711 712 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 713 struct dp_srng wbm_idle_link_ring; 714 715 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 716 */ 717 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 718 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 719 uint32_t wbm_idle_scatter_buf_size; 720 721 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 722 qdf_spinlock_t flow_pool_array_lock; 723 tx_pause_callback pause_cb; 724 struct dp_txrx_pool_stats pool_stats; 725 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 726 /* Tx SW descriptor pool */ 727 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 728 729 /* Tx MSDU Extension descriptor pool */ 730 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 731 732 /* Tx TSO descriptor pool */ 733 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 734 735 /* Tx TSO Num of segments pool */ 736 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 737 738 /* Tx H/W queues lock */ 739 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 740 741 /* Rx SW descriptor pool for RXDMA buffer */ 742 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 743 744 /* Rx SW descriptor pool for RXDMA monitor buffer */ 745 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 746 747 /* Rx SW descriptor pool for RXDMA status buffer */ 748 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 749 750 /* HAL SOC handle */ 751 void *hal_soc; 752 753 /* DP Interrupts */ 754 struct dp_intr intr_ctx[DP_MAX_INTERRUPT_CONTEXTS]; 755 756 /* REO destination rings */ 757 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 758 759 /* Number of REO destination rings */ 760 uint8_t num_reo_dest_rings; 761 762 /* REO exception ring - See if should combine this with reo_dest_ring */ 763 struct dp_srng reo_exception_ring; 764 765 /* REO reinjection ring */ 766 struct dp_srng reo_reinject_ring; 767 768 /* REO command ring */ 769 struct dp_srng reo_cmd_ring; 770 771 /* REO command status ring */ 772 struct dp_srng reo_status_ring; 773 774 /* WBM Rx release ring */ 775 struct dp_srng rx_rel_ring; 776 777 /* Number of TCL data rings */ 778 uint8_t num_tcl_data_rings; 779 780 /* TCL data ring */ 781 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 782 783 /* TCL command ring */ 784 struct dp_srng tcl_cmd_ring; 785 786 /* TCL command status ring */ 787 struct dp_srng tcl_status_ring; 788 789 /* WBM Tx completion rings */ 790 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 791 792 /* Common WBM link descriptor release ring (SW to WBM) */ 793 struct dp_srng wbm_desc_rel_ring; 794 795 /* Tx ring map for interrupt processing */ 796 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 797 798 /* Rx ring map for interrupt processing */ 799 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 800 801 /* peer ID to peer object map (array of pointers to peer objects) */ 802 struct dp_peer **peer_id_to_obj_map; 803 804 struct { 805 unsigned mask; 806 unsigned idx_bits; 807 TAILQ_HEAD(, dp_peer) * bins; 808 } peer_hash; 809 810 /* rx defrag state – TBD: do we need this per radio? */ 811 struct { 812 struct { 813 TAILQ_HEAD(, dp_rx_tid) waitlist; 814 uint32_t timeout_ms; 815 qdf_spinlock_t defrag_lock; 816 } defrag; 817 struct { 818 int defrag_timeout_check; 819 int dup_check; 820 } flags; 821 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 822 qdf_spinlock_t reo_cmd_lock; 823 } rx; 824 825 /* optional rx processing function */ 826 void (*rx_opt_proc)( 827 struct dp_vdev *vdev, 828 struct dp_peer *peer, 829 unsigned tid, 830 qdf_nbuf_t msdu_list); 831 832 /* pool addr for mcast enhance buff */ 833 struct { 834 int size; 835 uint32_t paddr; 836 uint32_t *vaddr; 837 struct dp_tx_me_buf_t *freelist; 838 int buf_in_use; 839 qdf_dma_mem_context(memctx); 840 } me_buf; 841 842 /** 843 * peer ref mutex: 844 * 1. Protect peer object lookups until the returned peer object's 845 * reference count is incremented. 846 * 2. Provide mutex when accessing peer object lookup structures. 847 */ 848 DP_MUTEX_TYPE peer_ref_mutex; 849 850 /* maximum value for peer_id */ 851 uint32_t max_peers; 852 853 /* SoC level data path statistics */ 854 struct dp_soc_stats stats; 855 856 /* Enable processing of Tx completion status words */ 857 bool process_tx_status; 858 bool process_rx_status; 859 struct dp_ast_entry *ast_table[WLAN_UMAC_PSOC_MAX_PEERS * 2]; 860 struct { 861 unsigned mask; 862 unsigned idx_bits; 863 TAILQ_HEAD(, dp_ast_entry) * bins; 864 } ast_hash; 865 866 qdf_spinlock_t ast_lock; 867 qdf_timer_t wds_aging_timer; 868 869 /*interrupt timer*/ 870 qdf_timer_t mon_reap_timer; 871 uint8_t reap_timer_init; 872 qdf_timer_t int_timer; 873 uint8_t intr_mode; 874 875 qdf_list_t reo_desc_freelist; 876 qdf_spinlock_t reo_desc_freelist_lock; 877 878 #ifdef QCA_SUPPORT_SON 879 /* The timer to check station's inactivity status */ 880 os_timer_t pdev_bs_inact_timer; 881 /* The current inactivity count reload value 882 based on overload condition */ 883 u_int16_t pdev_bs_inact_reload; 884 885 /* The inactivity timer value when not overloaded */ 886 u_int16_t pdev_bs_inact_normal; 887 888 /* The inactivity timer value when overloaded */ 889 u_int16_t pdev_bs_inact_overload; 890 891 /* The inactivity timer check interval */ 892 u_int16_t pdev_bs_inact_interval; 893 /* Inactivity timer */ 894 #endif /* QCA_SUPPORT_SON */ 895 896 /* htt stats */ 897 struct htt_t2h_stats htt_stats; 898 899 void *external_txrx_handle; /* External data path handle */ 900 #ifdef IPA_OFFLOAD 901 /* IPA uC datapath offload Wlan Tx resources */ 902 struct { 903 /* Resource info to be passed to IPA */ 904 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 905 void *ipa_tcl_ring_base_vaddr; 906 uint32_t ipa_tcl_ring_size; 907 qdf_dma_addr_t ipa_tcl_hp_paddr; 908 uint32_t alloc_tx_buf_cnt; 909 910 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 911 void *ipa_wbm_ring_base_vaddr; 912 uint32_t ipa_wbm_ring_size; 913 qdf_dma_addr_t ipa_wbm_tp_paddr; 914 915 /* TX buffers populated into the WBM ring */ 916 void **tx_buf_pool_vaddr_unaligned; 917 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 918 } ipa_uc_tx_rsc; 919 920 /* IPA uC datapath offload Wlan Rx resources */ 921 struct { 922 /* Resource info to be passed to IPA */ 923 qdf_dma_addr_t ipa_reo_ring_base_paddr; 924 void *ipa_reo_ring_base_vaddr; 925 uint32_t ipa_reo_ring_size; 926 qdf_dma_addr_t ipa_reo_tp_paddr; 927 928 /* Resource info to be passed to firmware and IPA */ 929 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 930 void *ipa_rx_refill_buf_ring_base_vaddr; 931 uint32_t ipa_rx_refill_buf_ring_size; 932 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 933 } ipa_uc_rx_rsc; 934 #endif 935 /* Device ID coming from Bus sub-system */ 936 uint32_t device_id; 937 938 /* Smart monitor capability for HKv2 */ 939 uint8_t hw_nac_monitor_support; 940 /* Flag to indicate if HTT v2 is enabled*/ 941 bool is_peer_map_unmap_v2; 942 }; 943 944 #ifdef IPA_OFFLOAD 945 /** 946 * dp_ipa_resources - Resources needed for IPA 947 */ 948 struct dp_ipa_resources { 949 qdf_dma_addr_t tx_ring_base_paddr; 950 uint32_t tx_ring_size; 951 uint32_t tx_num_alloc_buffer; 952 953 qdf_dma_addr_t tx_comp_ring_base_paddr; 954 uint32_t tx_comp_ring_size; 955 956 qdf_dma_addr_t rx_rdy_ring_base_paddr; 957 uint32_t rx_rdy_ring_size; 958 959 qdf_dma_addr_t rx_refill_ring_base_paddr; 960 uint32_t rx_refill_ring_size; 961 962 /* IPA UC doorbell registers paddr */ 963 qdf_dma_addr_t tx_comp_doorbell_paddr; 964 uint32_t *tx_comp_doorbell_vaddr; 965 qdf_dma_addr_t rx_ready_doorbell_paddr; 966 }; 967 #endif 968 969 #define MAX_RX_MAC_RINGS 2 970 /* Same as NAC_MAX_CLENT */ 971 #define DP_NAC_MAX_CLIENT 24 972 973 /* 974 * Macros to setup link descriptor cookies - for link descriptors, we just 975 * need first 3 bits to store bank ID. The remaining bytes will be used set a 976 * unique ID, which will be useful in debugging 977 */ 978 #define LINK_DESC_BANK_ID_MASK 0x7 979 #define LINK_DESC_ID_SHIFT 3 980 #define LINK_DESC_ID_START 0x8000 981 982 #define LINK_DESC_COOKIE(_desc_id, _bank_id) \ 983 ((((_desc_id) + LINK_DESC_ID_START) << LINK_DESC_ID_SHIFT) | (_bank_id)) 984 985 #define LINK_DESC_COOKIE_BANK_ID(_cookie) \ 986 ((_cookie) & LINK_DESC_BANK_ID_MASK) 987 988 /* same as ieee80211_nac_param */ 989 enum dp_nac_param_cmd { 990 /* IEEE80211_NAC_PARAM_ADD */ 991 DP_NAC_PARAM_ADD = 1, 992 /* IEEE80211_NAC_PARAM_DEL */ 993 DP_NAC_PARAM_DEL, 994 /* IEEE80211_NAC_PARAM_LIST */ 995 DP_NAC_PARAM_LIST, 996 }; 997 998 /** 999 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 1000 * @neighbour_peers_macaddr: neighbour peer's mac address 1001 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 1002 * @ast_entry: ast_entry for neighbour peer 1003 * @rssi: rssi value 1004 */ 1005 struct dp_neighbour_peer { 1006 /* MAC address of neighbour's peer */ 1007 union dp_align_mac_addr neighbour_peers_macaddr; 1008 struct dp_vdev *vdev; 1009 struct dp_ast_entry *ast_entry; 1010 uint8_t rssi; 1011 /* node in the list of neighbour's peer */ 1012 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 1013 }; 1014 1015 /** 1016 * struct ppdu_info - PPDU Status info descriptor 1017 * @ppdu_id - Unique ppduid assigned by firmware for every tx packet 1018 * @max_ppdu_id - wrap around for ppdu id 1019 * @last_tlv_cnt - Keep track for missing ppdu tlvs 1020 * @last_user - last ppdu processed for user 1021 * @is_ampdu - set if Ampdu aggregate 1022 * @nbuf - ppdu descriptor payload 1023 * @ppdu_desc - ppdu descriptor 1024 * @ppdu_info_list_elem - linked list of ppdu tlvs 1025 */ 1026 struct ppdu_info { 1027 uint32_t ppdu_id; 1028 uint32_t max_ppdu_id; 1029 uint16_t tlv_bitmap; 1030 uint16_t last_tlv_cnt; 1031 uint16_t last_user:8, 1032 is_ampdu:1; 1033 qdf_nbuf_t nbuf; 1034 struct cdp_tx_completion_ppdu *ppdu_desc; 1035 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 1036 }; 1037 1038 /* PDEV level structure for data path */ 1039 struct dp_pdev { 1040 /* PDEV handle from OSIF layer TBD: see if we really need osif_pdev */ 1041 struct cdp_ctrl_objmgr_pdev *ctrl_pdev; 1042 1043 /* PDEV Id */ 1044 int pdev_id; 1045 1046 /* LMAC Id */ 1047 int lmac_id; 1048 1049 /* TXRX SOC handle */ 1050 struct dp_soc *soc; 1051 1052 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 1053 struct dp_srng rx_refill_buf_ring; 1054 1055 /* Second ring used to replenish rx buffers */ 1056 struct dp_srng rx_refill_buf_ring2; 1057 1058 /* Empty ring used by firmware to post rx buffers to the MAC */ 1059 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 1060 1061 /* wlan_cfg pdev ctxt*/ 1062 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 1063 1064 /* RXDMA monitor buffer replenish ring */ 1065 struct dp_srng rxdma_mon_buf_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1066 1067 /* RXDMA monitor destination ring */ 1068 struct dp_srng rxdma_mon_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1069 1070 /* RXDMA monitor status ring. TBD: Check format of this ring */ 1071 struct dp_srng rxdma_mon_status_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1072 1073 struct dp_srng rxdma_mon_desc_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1074 1075 /* RXDMA error destination ring */ 1076 struct dp_srng rxdma_err_dst_ring[NUM_RXDMA_RINGS_PER_PDEV]; 1077 1078 /* Link descriptor memory banks */ 1079 struct { 1080 void *base_vaddr_unaligned; 1081 void *base_vaddr; 1082 qdf_dma_addr_t base_paddr_unaligned; 1083 qdf_dma_addr_t base_paddr; 1084 uint32_t size; 1085 } link_desc_banks[NUM_RXDMA_RINGS_PER_PDEV][MAX_MON_LINK_DESC_BANKS]; 1086 1087 1088 /** 1089 * TODO: See if we need a ring map here for LMAC rings. 1090 * 1. Monitor rings are currently planning to be processed on receiving 1091 * PPDU end interrupts and hence wont need ring based interrupts. 1092 * 2. Rx buffer rings will be replenished during REO destination 1093 * processing and doesn't require regular interrupt handling - we will 1094 * only handle low water mark interrupts which is not expected 1095 * frequently 1096 */ 1097 1098 /* VDEV list */ 1099 TAILQ_HEAD(, dp_vdev) vdev_list; 1100 1101 /* vdev list lock */ 1102 qdf_spinlock_t vdev_list_lock; 1103 1104 /* Number of vdevs this device have */ 1105 uint16_t vdev_count; 1106 1107 /* PDEV transmit lock */ 1108 qdf_spinlock_t tx_lock; 1109 1110 #ifndef REMOVE_PKT_LOG 1111 bool pkt_log_init; 1112 /* Pktlog pdev */ 1113 struct pktlog_dev_t *pl_dev; 1114 #endif /* #ifndef REMOVE_PKT_LOG */ 1115 1116 /* Monitor mode interface and status storage */ 1117 struct dp_vdev *monitor_vdev; 1118 1119 /* monitor mode lock */ 1120 qdf_spinlock_t mon_lock; 1121 1122 /*tx_mutex for me*/ 1123 DP_MUTEX_TYPE tx_mutex; 1124 1125 /* Smart Mesh */ 1126 bool filter_neighbour_peers; 1127 1128 /*flag to indicate neighbour_peers_list not empty */ 1129 bool neighbour_peers_added; 1130 /* smart mesh mutex */ 1131 qdf_spinlock_t neighbour_peer_mutex; 1132 /* Neighnour peer list */ 1133 TAILQ_HEAD(, dp_neighbour_peer) neighbour_peers_list; 1134 /* msdu chain head & tail */ 1135 qdf_nbuf_t invalid_peer_head_msdu; 1136 qdf_nbuf_t invalid_peer_tail_msdu; 1137 1138 /* Band steering */ 1139 /* TBD */ 1140 1141 /* PDEV level data path statistics */ 1142 struct cdp_pdev_stats stats; 1143 1144 /* Global RX decap mode for the device */ 1145 enum htt_pkt_type rx_decap_mode; 1146 1147 /* Enhanced Stats is enabled */ 1148 bool enhanced_stats_en; 1149 1150 /* advance filter mode and type*/ 1151 uint8_t mon_filter_mode; 1152 uint16_t fp_mgmt_filter; 1153 uint16_t fp_ctrl_filter; 1154 uint16_t fp_data_filter; 1155 uint16_t mo_mgmt_filter; 1156 uint16_t mo_ctrl_filter; 1157 uint16_t mo_data_filter; 1158 uint16_t md_data_filter; 1159 1160 qdf_atomic_t num_tx_outstanding; 1161 1162 qdf_atomic_t num_tx_exception; 1163 1164 /* MCL specific local peer handle */ 1165 struct { 1166 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 1167 uint8_t freelist; 1168 qdf_spinlock_t lock; 1169 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 1170 } local_peer_ids; 1171 1172 /* dscp_tid_map_*/ 1173 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 1174 1175 struct hal_rx_ppdu_info ppdu_info; 1176 1177 /* operating channel */ 1178 uint8_t operating_channel; 1179 1180 qdf_nbuf_queue_t rx_status_q; 1181 uint32_t mon_ppdu_status; 1182 struct cdp_mon_status rx_mon_recv_status; 1183 /* monitor mode status/destination ring PPDU and MPDU count */ 1184 struct cdp_pdev_mon_stats rx_mon_stats; 1185 1186 /* pool addr for mcast enhance buff */ 1187 struct { 1188 int size; 1189 uint32_t paddr; 1190 char *vaddr; 1191 struct dp_tx_me_buf_t *freelist; 1192 int buf_in_use; 1193 qdf_dma_mem_context(memctx); 1194 } me_buf; 1195 1196 /* Number of VAPs with mcast enhancement enabled */ 1197 qdf_atomic_t mc_num_vap_attached; 1198 1199 qdf_atomic_t stats_cmd_complete; 1200 1201 #ifdef IPA_OFFLOAD 1202 ipa_uc_op_cb_type ipa_uc_op_cb; 1203 void *usr_ctxt; 1204 struct dp_ipa_resources ipa_resource; 1205 #endif 1206 1207 /* TBD */ 1208 1209 /* map this pdev to a particular Reo Destination ring */ 1210 enum cdp_host_reo_dest_ring reo_dest; 1211 1212 #ifndef REMOVE_PKT_LOG 1213 /* Packet log mode */ 1214 uint8_t rx_pktlog_mode; 1215 #endif 1216 1217 /* WDI event handlers */ 1218 struct wdi_event_subscribe_t **wdi_event_list; 1219 1220 /* ppdu_id of last received HTT TX stats */ 1221 uint32_t last_ppdu_id; 1222 struct { 1223 uint8_t last_user; 1224 qdf_nbuf_t buf; 1225 } tx_ppdu_info; 1226 1227 bool tx_sniffer_enable; 1228 /* mirror copy mode */ 1229 bool mcopy_mode; 1230 bool bpr_enable; 1231 struct { 1232 uint16_t tx_ppdu_id; 1233 uint16_t tx_peer_id; 1234 uint16_t rx_ppdu_id; 1235 } m_copy_id; 1236 1237 /* To check if PPDU Tx stats are enabled for Pktlog */ 1238 bool pktlog_ppdu_stats; 1239 1240 void *dp_txrx_handle; /* Advanced data path handle */ 1241 1242 #ifdef ATH_SUPPORT_NAC_RSSI 1243 bool nac_rssi_filtering; 1244 #endif 1245 /* list of ppdu tlvs */ 1246 TAILQ_HEAD(, ppdu_info) ppdu_info_list; 1247 uint32_t tlv_count; 1248 uint32_t list_depth; 1249 uint32_t ppdu_id; 1250 bool first_nbuf; 1251 struct { 1252 uint8_t *mgmt_buf; /* Ptr to mgmt. payload in HTT ppdu stats */ 1253 uint32_t mgmt_buf_len; /* Len of mgmt. payload in ppdu stats */ 1254 uint32_t ppdu_id; 1255 } mgmtctrl_frm_info; 1256 1257 /* Current noise-floor reading for the pdev channel */ 1258 int16_t chan_noise_floor; 1259 1260 /* 1261 * For multiradio device, this flag indicates if 1262 * this radio is primary or secondary. 1263 * 1264 * For HK 1.0, this is used for WAR for the AST issue. 1265 * HK 1.x mandates creation of only 1 AST entry with same MAC address 1266 * across 2 radios. is_primary indicates the radio on which DP should 1267 * install HW AST entry if there is a request to add 2 AST entries 1268 * with same MAC address across 2 radios 1269 */ 1270 uint8_t is_primary; 1271 /* Context of cal client timer */ 1272 void *cal_client_ctx; 1273 struct cdp_tx_sojourn_stats sojourn_stats; 1274 qdf_nbuf_t sojourn_buf; 1275 1276 }; 1277 1278 struct dp_peer; 1279 1280 /* VDEV structure for data path state */ 1281 struct dp_vdev { 1282 /* OS device abstraction */ 1283 qdf_device_t osdev; 1284 /* physical device that is the parent of this virtual device */ 1285 struct dp_pdev *pdev; 1286 1287 /* Handle to the OS shim SW's virtual device */ 1288 ol_osif_vdev_handle osif_vdev; 1289 1290 /* Handle to the UMAC handle */ 1291 struct cdp_ctrl_objmgr_vdev *ctrl_vdev; 1292 /* vdev_id - ID used to specify a particular vdev to the target */ 1293 uint8_t vdev_id; 1294 1295 /* MAC address */ 1296 union dp_align_mac_addr mac_addr; 1297 1298 /* node in the pdev's list of vdevs */ 1299 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 1300 1301 /* dp_peer list */ 1302 TAILQ_HEAD(, dp_peer) peer_list; 1303 1304 /* default RX call back function called by dp */ 1305 ol_txrx_rx_fp osif_rx; 1306 /* callback to deliver rx frames to the OS */ 1307 ol_txrx_rx_fp osif_rx_stack; 1308 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 1309 ol_txrx_get_key_fp osif_get_key; 1310 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 1311 1312 #ifdef notyet 1313 /* callback to check if the msdu is an WAI (WAPI) frame */ 1314 ol_rx_check_wai_fp osif_check_wai; 1315 #endif 1316 1317 /* proxy arp function */ 1318 ol_txrx_proxy_arp_fp osif_proxy_arp; 1319 1320 /* callback to hand rx monitor 802.11 MPDU to the OS shim */ 1321 ol_txrx_rx_mon_fp osif_rx_mon; 1322 1323 ol_txrx_mcast_me_fp me_convert; 1324 1325 /* completion function used by this vdev*/ 1326 ol_txrx_completion_fp tx_comp; 1327 1328 /* deferred vdev deletion state */ 1329 struct { 1330 /* VDEV delete pending */ 1331 int pending; 1332 /* 1333 * callback and a context argument to provide a 1334 * notification for when the vdev is deleted. 1335 */ 1336 ol_txrx_vdev_delete_cb callback; 1337 void *context; 1338 } delete; 1339 1340 /* tx data delivery notification callback function */ 1341 struct { 1342 ol_txrx_data_tx_cb func; 1343 void *ctxt; 1344 } tx_non_std_data_callback; 1345 1346 1347 /* safe mode control to bypass the encrypt and decipher process*/ 1348 uint32_t safemode; 1349 1350 /* rx filter related */ 1351 uint32_t drop_unenc; 1352 #ifdef notyet 1353 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 1354 uint32_t filters_num; 1355 #endif 1356 /* TDLS Link status */ 1357 bool tdls_link_connected; 1358 bool is_tdls_frame; 1359 1360 1361 /* VDEV operating mode */ 1362 enum wlan_op_mode opmode; 1363 1364 /* Tx encapsulation type for this VAP */ 1365 enum htt_cmn_pkt_type tx_encap_type; 1366 /* Rx Decapsulation type for this VAP */ 1367 enum htt_cmn_pkt_type rx_decap_type; 1368 1369 /* BSS peer */ 1370 struct dp_peer *vap_bss_peer; 1371 1372 /* WDS enabled */ 1373 bool wds_enabled; 1374 1375 /* WDS Aging timer period */ 1376 uint32_t wds_aging_timer_val; 1377 1378 /* NAWDS enabled */ 1379 bool nawds_enabled; 1380 1381 /* Default HTT meta data for this VDEV */ 1382 /* TBD: check alignment constraints */ 1383 uint16_t htt_tcl_metadata; 1384 1385 /* Mesh mode vdev */ 1386 uint32_t mesh_vdev; 1387 1388 /* Mesh mode rx filter setting */ 1389 uint32_t mesh_rx_filter; 1390 1391 /* DSCP-TID mapping table ID */ 1392 uint8_t dscp_tid_map_id; 1393 1394 /* Multicast enhancement enabled */ 1395 uint8_t mcast_enhancement_en; 1396 1397 /* per vdev rx nbuf queue */ 1398 qdf_nbuf_queue_t rxq; 1399 1400 uint8_t tx_ring_id; 1401 struct dp_tx_desc_pool_s *tx_desc; 1402 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 1403 1404 /* VDEV Stats */ 1405 struct cdp_vdev_stats stats; 1406 bool lro_enable; 1407 1408 /* Is this a proxySTA VAP */ 1409 bool proxysta_vdev; 1410 /* Is isolation mode enabled */ 1411 bool isolation_vdev; 1412 1413 /* Address search flags to be configured in HAL descriptor */ 1414 uint8_t hal_desc_addr_search_flags; 1415 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 1416 struct dp_tx_desc_pool_s *pool; 1417 #endif 1418 /* AP BRIDGE enabled */ 1419 uint32_t ap_bridge_enabled; 1420 1421 enum cdp_sec_type sec_type; 1422 1423 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 1424 bool raw_mode_war; 1425 1426 /* Address search type to be set in TX descriptor */ 1427 uint8_t search_type; 1428 1429 /* AST hash value for BSS peer in HW valid for STA VAP*/ 1430 uint16_t bss_ast_hash; 1431 }; 1432 1433 1434 enum { 1435 dp_sec_mcast = 0, 1436 dp_sec_ucast 1437 }; 1438 1439 #ifdef WDS_VENDOR_EXTENSION 1440 typedef struct { 1441 uint8_t wds_tx_mcast_4addr:1, 1442 wds_tx_ucast_4addr:1, 1443 wds_rx_filter:1, /* enforce rx filter */ 1444 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 1445 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 1446 1447 } dp_ecm_policy; 1448 #endif 1449 1450 /* Peer structure for data path state */ 1451 struct dp_peer { 1452 /* VDEV to which this peer is associated */ 1453 struct dp_vdev *vdev; 1454 1455 struct cdp_ctrl_objmgr_peer *ctrl_peer; 1456 1457 struct dp_ast_entry *self_ast_entry; 1458 1459 qdf_atomic_t ref_cnt; 1460 1461 /* TODO: See if multiple peer IDs are required in wifi3.0 */ 1462 /* peer ID(s) for this peer */ 1463 uint16_t peer_ids[MAX_NUM_PEER_ID_PER_PEER]; 1464 1465 union dp_align_mac_addr mac_addr; 1466 1467 /* node in the vdev's list of peers */ 1468 TAILQ_ENTRY(dp_peer) peer_list_elem; 1469 /* node in the hash table bin's list of peers */ 1470 TAILQ_ENTRY(dp_peer) hash_list_elem; 1471 1472 /* TID structures */ 1473 struct dp_rx_tid rx_tid[DP_MAX_TIDS]; 1474 1475 /* TBD: No transmit TID state required? */ 1476 1477 struct { 1478 enum htt_sec_type sec_type; 1479 u_int32_t michael_key[2]; /* relevant for TKIP */ 1480 } security[2]; /* 0 -> multicast, 1 -> unicast */ 1481 1482 /* 1483 * rx proc function: this either is a copy of pdev's rx_opt_proc for 1484 * regular rx processing, or has been redirected to a /dev/null discard 1485 * function when peer deletion is in progress. 1486 */ 1487 void (*rx_opt_proc)(struct dp_vdev *vdev, struct dp_peer *peer, 1488 unsigned tid, qdf_nbuf_t msdu_list); 1489 1490 /* set when node is authorized */ 1491 uint8_t authorize:1; 1492 1493 u_int8_t nac; 1494 1495 /* Band steering: Set when node is inactive */ 1496 uint8_t peer_bs_inact_flag:1; 1497 u_int16_t peer_bs_inact; /* inactivity mark count */ 1498 1499 /* NAWDS Flag and Bss Peer bit */ 1500 uint8_t nawds_enabled:1, 1501 bss_peer:1, 1502 wapi:1, 1503 wds_enabled:1; 1504 1505 /* MCL specific peer local id */ 1506 uint16_t local_id; 1507 enum ol_txrx_peer_state state; 1508 qdf_spinlock_t peer_info_lock; 1509 1510 qdf_time_t last_assoc_rcvd; 1511 qdf_time_t last_disassoc_rcvd; 1512 qdf_time_t last_deauth_rcvd; 1513 /* Peer Stats */ 1514 struct cdp_peer_stats stats; 1515 1516 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 1517 /* TBD */ 1518 1519 #ifdef WDS_VENDOR_EXTENSION 1520 dp_ecm_policy wds_ecm; 1521 #endif 1522 bool delete_in_progress; 1523 1524 /* Active Block ack sessions */ 1525 uint16_t active_ba_session_cnt; 1526 1527 /* Current HW buffersize setting */ 1528 uint16_t hw_buffer_size; 1529 1530 /* 1531 * Flag to check if sessions with 256 buffersize 1532 * should be terminated. 1533 */ 1534 uint8_t kill_256_sessions; 1535 }; 1536 1537 #ifdef CONFIG_WIN 1538 /* 1539 * dp_invalid_peer_msg 1540 * @nbuf: data buffer 1541 * @wh: 802.11 header 1542 * @vdev_id: id of vdev 1543 */ 1544 struct dp_invalid_peer_msg { 1545 qdf_nbuf_t nbuf; 1546 struct ieee80211_frame *wh; 1547 uint8_t vdev_id; 1548 }; 1549 #endif 1550 1551 /* 1552 * dp_tx_me_buf_t: ME buffer 1553 * next: pointer to next buffer 1554 * data: Destination Mac address 1555 */ 1556 struct dp_tx_me_buf_t { 1557 /* Note: ME buf pool initialization logic expects next pointer to 1558 * be the first element. Dont add anything before next */ 1559 struct dp_tx_me_buf_t *next; 1560 uint8_t data[DP_MAC_ADDR_LEN]; 1561 }; 1562 1563 #endif /* _DP_TYPES_H_ */ 1564