1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_HTT_H_ 21 #define _DP_HTT_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_lock.h> 25 #include <qdf_nbuf.h> 26 #include <htc_api.h> 27 28 #include "cdp_txrx_cmn_struct.h" 29 #include "dp_types.h" 30 #ifdef HTT_LOGGER 31 #include "dp_htt_logger.h" 32 #else 33 struct htt_logger; 34 static inline 35 void htt_interface_logging_init(struct htt_logger **htt_logger_handle, 36 struct cdp_ctrl_objmgr_psoc *ctrl_psoc) 37 { 38 } 39 40 static inline 41 void htt_interface_logging_deinit(struct htt_logger *htt_logger_handle) 42 { 43 } 44 45 static inline 46 int htt_command_record(struct htt_logger *h, uint8_t msg_type, 47 uint8_t *msg_data) 48 { 49 return 0; 50 } 51 52 static inline 53 int htt_event_record(struct htt_logger *h, uint8_t msg_type, 54 uint8_t *msg_data) 55 { 56 return 0; 57 } 58 59 static inline 60 int htt_wbm_event_record(struct htt_logger *h, uint8_t tx_status, 61 uint8_t *msg_data) 62 { 63 return 0; 64 } 65 66 #endif 67 68 #define HTT_MGMT_CTRL_TLV_HDR_RESERVERD_LEN 16 69 #define HTT_TLV_HDR_LEN HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 70 #define HTT_SHIFT_UPPER_TIMESTAMP 32 71 #define HTT_MASK_UPPER_TIMESTAMP 0xFFFFFFFF00000000 72 73 void htt_htc_pkt_pool_free(struct htt_soc *soc); 74 75 #define HTT_TX_MUTEX_TYPE qdf_spinlock_t 76 77 #define HTT_TX_MUTEX_INIT(_mutex) \ 78 qdf_spinlock_create(_mutex) 79 80 #define HTT_TX_MUTEX_ACQUIRE(_mutex) \ 81 qdf_spin_lock_bh(_mutex) 82 83 #define HTT_TX_MUTEX_RELEASE(_mutex) \ 84 qdf_spin_unlock_bh(_mutex) 85 86 #define HTT_TX_MUTEX_DESTROY(_mutex) \ 87 qdf_spinlock_destroy(_mutex) 88 89 #define DP_HTT_MAX_SEND_QUEUE_DEPTH 64 90 91 #ifndef HTT_MAC_ADDR_LEN 92 #define HTT_MAC_ADDR_LEN 6 93 #endif 94 95 #define HTT_FRAMECTRL_TYPE_MASK 0x0C 96 #define HTT_GET_FRAME_CTRL_TYPE(_val) \ 97 (((_val) & HTT_FRAMECTRL_TYPE_MASK) >> 2) 98 #define FRAME_CTRL_TYPE_MGMT 0x0 99 #define FRAME_CTRL_TYPE_CTRL 0x1 100 #define FRAME_CTRL_TYPE_DATA 0x2 101 #define FRAME_CTRL_TYPE_RESV 0x3 102 103 #define HTT_FRAMECTRL_DATATYPE 0x08 104 #define HTT_PPDU_DESC_MAX_DEPTH 16 105 #define DP_SCAN_PEER_ID 0xFFFF 106 107 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 108 #define HTT_RX_DELBA_WIN_SIZE_S 10 109 110 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 111 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 112 113 /* 114 * Set the base misclist size to HTT copy engine source ring size 115 * to guarantee that a packet on the misclist wont be freed while it 116 * is sitting in the copy engine. 117 */ 118 #define DP_HTT_HTC_PKT_MISCLIST_SIZE 2048 119 #define HTT_T2H_MAX_MSG_SIZE 2048 120 121 #define HTT_T2H_EXT_STATS_TLV_START_OFFSET 3 122 123 /* 124 * Below offset are based on htt_ppdu_stats_common_tlv 125 * defined in htt_ppdu_stats.h 126 */ 127 #define HTT_PPDU_STATS_COMMON_TLV_TLV_HDR_OFFSET 0 128 #define HTT_PPDU_STATS_COMMON_TLV_PPDU_ID_OFFSET 1 129 #define HTT_PPDU_STATS_COMMON_TLV_RING_ID_SCH_CMD_ID_OFFSET 2 130 #define HTT_PPDU_STATS_COMMON_TLV_QTYPE_FRM_TYPE_OFFSET 3 131 #define HTT_PPDU_STATS_COMMON_TLV_CHAIN_MASK_OFFSET 4 132 #define HTT_PPDU_STATS_COMMON_TLV_FES_DUR_US_OFFSET 5 133 #define HTT_PPDU_STATS_COMMON_TLV_SCH_EVAL_START_TSTMP_L32_US_OFFSET 6 134 #define HTT_PPDU_STATS_COMMON_TLV_SCH_END_TSTMP_US_OFFSET 7 135 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_L32_US_OFFSET 8 136 #define HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_PHY_MODE_OFFSET 9 137 #define HTT_PPDU_STATS_COMMON_TLV_CCA_DELTA_TIME_US_OFFSET 10 138 #define HTT_PPDU_STATS_COMMON_TLV_RXFRM_DELTA_TIME_US_OFFSET 11 139 #define HTT_PPDU_STATS_COMMON_TLV_TXFRM_DELTA_TIME_US_OFFSET 12 140 #define HTT_PPDU_STATS_COMMON_TLV_RESV_NUM_UL_BEAM_OFFSET 13 141 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_U32_US_OFFSET 14 142 #define HTT_PPDU_STATS_COMMON_TLV_BSSCOLOR_OBSS_PSR_OFFSET 15 143 144 /* get index for field in htt_ppdu_stats_common_tlv */ 145 #define HTT_GET_STATS_CMN_INDEX(index) \ 146 HTT_PPDU_STATS_COMMON_TLV_##index##_OFFSET 147 148 #define HTT_VDEV_STATS_TLV_SOC_DROP_CNT_OFFSET 1 149 150 #define HTT_VDEV_STATS_TLV_HDR_OFFSET 0 151 #define HTT_VDEV_STATS_TLV_VDEV_ID_OFFSET 1 152 #define HTT_VDEV_STATS_TLV_RX_BYTE_CNT_OFFSET 2 153 #define HTT_VDEV_STATS_TLV_RX_PKT_CNT_OFFSET 4 154 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_BYTE_CNT_OFFSET 6 155 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_PKT_CNT_OFFSET 8 156 #define HTT_VDEV_STATS_TLV_TX_RETRY_PKT_CNT_OFFSET 10 157 #define HTT_VDEV_STATS_TLV_TX_DROP_PKT_CNT_OFFSET 12 158 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_PKT_CNT_OFFSET 14 159 #define HTT_VDEV_STATS_TLV_TX_RETRY_BYTE_CNT_OFFSET 16 160 #define HTT_VDEV_STATS_TLV_TX_DROP_BYTE_CNT_OFFSET 18 161 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_BYTE_CNT_OFFSET 20 162 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_PKT_CNT_OFFSET 22 163 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_BYTE_CNT_OFFSET 24 164 165 #define HTT_VDEV_STATS_GET_INDEX(index) \ 166 HTT_VDEV_STATS_TLV_##index##_OFFSET 167 168 #define HTT_VDEV_STATS_U32_SHIFT 0x20 169 #define HTT_VDEV_STATS_U32_MASK 0xFFFFFFFF00000000 170 #define HTT_VDEV_STATS_L32_MASK 0x00000000FFFFFFFF 171 172 #define HTT_VDEV_GET_STATS_U64(msg_word) \ 173 (((((uint64_t)(*(((uint32_t *)msg_word) + 1))) & HTT_VDEV_STATS_L32_MASK) << \ 174 HTT_VDEV_STATS_U32_SHIFT) | ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK)) 175 176 #define HTT_VDEV_GET_STATS_U32(msg_word) \ 177 ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK) 178 179 #define MAX_SCHED_STARVE 100000 180 #define WRAP_DROP_TSF_DELTA 10000 181 #define MAX_TSF_32 0xFFFFFFFF 182 183 #define dp_htt_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT, params) 184 #define dp_htt_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT, params) 185 #define dp_htt_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT, params) 186 #define dp_htt_info(params...) \ 187 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT, ## params) 188 #define dp_htt_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT, params) 189 190 #define dp_htt_tx_stats_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 191 #define dp_htt_tx_stats_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 192 #define dp_htt_tx_stats_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 193 #define dp_htt_tx_stats_info(params...) \ 194 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT_TX_STATS, ## params) 195 #define dp_htt_tx_stats_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 196 197 #define RXMON_GLOBAL_EN_SHIFT 28 198 /** 199 * enum dp_full_mon_config - enum to enable/disable full monitor mode 200 * 201 * @DP_FULL_MON_DISABLE: Disable full monitor mode 202 * @DP_FULL_MON_ENABLE: Enable full monitor mode 203 */ 204 enum dp_full_mon_config { 205 DP_FULL_MON_DISABLE, 206 DP_FULL_MON_ENABLE, 207 }; 208 209 struct dp_htt_htc_pkt { 210 void *soc_ctxt; 211 qdf_dma_addr_t nbuf_paddr; 212 HTC_PACKET htc_pkt; 213 }; 214 215 struct dp_htt_htc_pkt_union { 216 union { 217 struct dp_htt_htc_pkt pkt; 218 struct dp_htt_htc_pkt_union *next; 219 } u; 220 }; 221 222 struct dp_htt_timestamp { 223 long *umac_ttt; 224 long *lmac_ttt; 225 }; 226 227 struct htt_soc { 228 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 229 struct dp_soc *dp_soc; 230 hal_soc_handle_t hal_soc; 231 struct dp_htt_timestamp pdevid_tt[MAX_PDEV_CNT]; 232 /* htt_logger handle */ 233 struct htt_logger *htt_logger_handle; 234 HTC_HANDLE htc_soc; 235 qdf_device_t osdev; 236 HTC_ENDPOINT_ID htc_endpoint; 237 struct dp_htt_htc_pkt_union *htt_htc_pkt_freelist; 238 struct dp_htt_htc_pkt_union *htt_htc_pkt_misclist; 239 struct { 240 u_int8_t major; 241 u_int8_t minor; 242 } tgt_ver; 243 struct { 244 u_int8_t major; 245 u_int8_t minor; 246 } wifi_ip_ver; 247 248 struct { 249 int htc_err_cnt; 250 int htc_pkt_free; 251 int skip_count; 252 int fail_count; 253 /* rtpm put skip count for ver req msg */ 254 int htt_ver_req_put_skip; 255 } stats; 256 257 HTT_TX_MUTEX_TYPE htt_tx_mutex; 258 }; 259 260 #ifdef QCA_MONITOR_2_0_SUPPORT 261 /** 262 * struct dp_tx_mon_downstream_tlv_config - Enable/Disable TxMon 263 * downstream TLVs 264 * tx_fes_setup: TX_FES_SETUP TLV 265 * tx_peer_entry: TX_PEER_ENTRY TLV 266 * tx_queue_extension: TX_QUEUE_EXTENSION TLV 267 * tx_last_mpdu_end: TX_LAST_MPDU_END TLV 268 * tx_last_mpdu_fetched: TX_LAST_MPDU_FETCHED TLV 269 * tx_data_sync: TX_DATA_SYNC TLV 270 * pcu_ppdu_setup_init: PCU_PPDU_SETUP_INIT TLV 271 * fw2s_mon: FW2S_MON TLV 272 * tx_loopback_setup: TX_LOOPBACK_SETUP TLV 273 * sch_critical_tlv_ref: SCH_CRITICAL_TLV_REF TLV 274 * ndp_preamble_done: NDP_PREAMBLE_DONE TLV 275 * tx_raw_frame_setup: TX_RAW_OR_NATIVE_FRAME_SETUP TLV 276 * txpcu_user_setup: TXPCU_USER_SETUP TLV 277 * rxpcu_setup: RXPCU_SETUP TLV 278 * rxpcu_setup_complete: RXPCU_SETUP_COMPLETE TLV 279 * coex_tx_req: COEX_TX_REQ TLV 280 * rxpcu_user_setup: RXPCU_USER_SETUP TLV 281 * rxpcu_user_setup_ext: RXPCU_USER_SETUP_EXT TLV 282 * wur_data: WUR_DATA TLV 283 * tqm_mpdu_global_start: TQM_MPDU_GLOBAL_START 284 * tx_fes_setup_complete: TX_FES_SETUP_COMPLETE TLV 285 * scheduler_end: SCHEDULER_END TLV 286 * sch_wait_instr_tx_path: SCH_WAIT_INSTR_TX_PATH TLV 287 * 288 */ 289 struct dp_tx_mon_downstream_tlv_config { 290 uint32_t tx_fes_setup:1, 291 tx_peer_entry:1, 292 tx_queue_extension:1, 293 tx_last_mpdu_end:1, 294 tx_last_mpdu_fetched:1, 295 tx_data_sync:1, 296 pcu_ppdu_setup_init:1, 297 fw2s_mon:1, 298 tx_loopback_setup:1, 299 sch_critical_tlv_ref:1, 300 ndp_preamble_done:1, 301 tx_raw_frame_setup:1, 302 txpcu_user_setup:1, 303 rxpcu_setup:1, 304 rxpcu_setup_complete:1, 305 coex_tx_req:1, 306 rxpcu_user_setup:1, 307 rxpcu_user_setup_ext:1, 308 wur_data:1, 309 tqm_mpdu_global_start:1, 310 tx_fes_setup_complete:1, 311 scheduler_end:1, 312 sch_wait_instr_tx_path:1; 313 }; 314 315 /** 316 * struct dp_tx_mon_upstream_tlv_config - Enable/Disable TxMon 317 * upstream TLVs 318 * rx_response_required_info: RX_RESPONSE_REQUIRED_INFO 319 * TLV 320 * response_start_status: RESPONSE_START_STATUS TLV 321 * response_end_status: RESPONSE_END_STATUS TLV 322 * tx_fes_status_start: TX_FES_STATUS_START TLV 323 * tx_fes_status_start_ppdu: TX_FES_STATUS_START_PPDU TLV 324 * tx_fes_status_user_ppdu: TX_FES_STATUS_USER_PPDU TLV 325 * tx_fes_status_ack_or_ba: TX_FES_STATUS_ACK_OR_BA TLV 326 * tx_fes_status_1k_ba: TX_FES_STATUS_1K_BA TLV 327 * tx_fes_status_start_prot: TX_FES_STATUS_START_PROTO TLV 328 * tx_fes_status_user_response: TX_FES_STATUS_USER_RESPONSE TLV 329 * rx_frame_bitmap_ack: RX_FRAME_BITMAP_ACK TLV 330 * rx_frame_1k_bitmap_ack: RX_FRAME_1K_BITMAP_ACK TLV 331 * coex_tx_status: COEX_TX_STATUS TLV 332 * recevied_response_info: RECEIVED_RESPONSE_INFO TLV 333 * recevied_response_info_p2: RECEIVED_RESPONSE_INFO_PART2 TLV 334 * ofdma_trigger_details: OFDMA_TRIGGER_DETAILS 335 * recevied_trigger_info: RECEIVED_TRIGGER_INFO 336 * pdg_tx_request: PDG_TX_REQUEST 337 * pdg_response: PDG_RESPONSE 338 * pdg_trig_response: PDG_TRIG_RESPONSE 339 * trigger_response_tx_done: TRIGGER_RESPONSE_TX_DONE 340 * prot_tx_end: PROT_TX_END 341 * ppdu_tx_end: PPDU_TX_END 342 * r2r_status_end: R2R_STATUS_END 343 * flush_req: FLUSH_REQ 344 * mactx_phy_desc: MACTX_PHY_DESC 345 * mactx_user_desc_cmn: MACTX_USER_DESC_COMMON 346 * mactx_user_desc_per_usr: MACTX_USER_DESC_PER_USER 347 * tqm_acked_1k_mpdu: TQM_ACKED_1K_MPDU 348 * tqm_acked_mpdu: TQM_ACKED_MPDU 349 * tqm_update_tx_mpdu_count: TQM_UPDATE_TX_MPDU_COUNT 350 * phytx_ppdu_header_info_request: PHYTX_PPDU_HEADER_INFO_REQUEST 351 * u_sig_eht_su_mu: U_SIG_EHT_SU_MU 352 * u_sig_eht_su: U_SIG_EHT_SU 353 * eht_sig_usr_su: EHT_SIG_USR_SU 354 * eht_sig_usr_mu_mimo: EHT_SIG_USR_MU_MIMO 355 * eht_sig_usr_ofdma: EHT_SIG_USR_MU_MIMO 356 * he_sig_a_su: HE_SIG_A_SU 357 * he_sig_a_mu_dl: HE_SIG_A_MU_DL 358 * he_sig_a_mu_ul: HE_SIG_A_MU_UL 359 * he_sig_b1_mu: HE_SIG_B1_MU 360 * he_sig_b2_mu: HE_SIG_B2_MU 361 * he_sig_b2_ofdma: HE_SIG_B2_OFDMA 362 * vht_sig_b_mu160: VHT_SIG_B_MU160 363 * vht_sig_b_mu80: VHT_SIG_B_MU80 364 * vht_sig_b_mu40: VHT_SIG_B_MU40 365 * vht_sig_b_mu20: VHT_SIG_B_MU20 366 * vht_sig_b_su160: VHT_SIG_B_SU160 367 * vht_sig_b_su80: VHT_SIG_B_SU80 368 * vht_sig_b_su40: VHT_SIG_B_SU40 369 * vht_sig_b_su20: VHT_SIG_B_SU20 370 * vht_sig_a: VHT_SIG_A 371 * ht_sig: HT_SIG 372 * l_sig_b: L_SIG_B 373 * l_sig_a: L_SIG_A 374 * tx_service: TX_SERVICE 375 * txpcu_buf_status: TXPCU_BUFFER_STATUS 376 * txpcu_user_buf_status: TXPCU_USER_BUFFER_STATUS 377 * txdma_stop_request: TXDMA_STOP_REQUEST 378 * expected_response: EXPECTED_RESPONSE 379 * tx_mpdu_count_transfer_end: TX_MPDU_COUNT_TRANSFER_END 380 * rx_trig_info: RX_TRIG_INFO 381 * rxpcu_tx_setup_clear: RXPCU_TX_SETUP_CLEAR 382 * rx_frame_bitmap_req: RX_FRAME_BITMAP_REQ 383 * rx_phy_sleep: RX_PHY_SLEEP 384 * txpcu_preamble_done: TXPCU_PREAMBLE_DONE 385 * txpcu_phytx_debug32: TXPCU_PHYTX_DEBUG32 386 * txpcu_phytx_other_transmit_info32: TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 387 * rx_ppdu_noack_report: RX_PPDU_NO_ACK_REPORT 388 * rx_ppdu_ack_report: RX_PPDU_ACK_REPORT 389 * coex_rx_status: COEX_RX_STATUS 390 * rx_start_param: RX_START_PARAM 391 * tx_cbf_info: TX_CBF_INFO 392 * rxpcu_early_rx_indication: RXPCU_EARLY_RX_INDICATION 393 * received_response_user_7_0: RECEIVED_RESPONSE_USER_7_0 394 * received_response_user_15_8: RECEIVED_RESPONSE_USER_15_8 395 * received_response_user_23_16: RECEIVED_RESPONSE_USER_23_16 396 * received_response_user_31_24: RECEIVED_RESPONSE_USER_31_24 397 * received_response_user_36_32: RECEIVED_RESPONSE_USER_36_32 398 * rx_pm_info: RX_PM_INFO 399 * rx_preamble: RX_PREAMBLE 400 * others: OTHERS 401 * mactx_pre_phy_desc: MACTX_PRE_PHY_DESC 402 * 403 */ 404 struct dp_tx_mon_upstream_tlv_config { 405 uint32_t rx_response_required_info:1, 406 response_start_status:1, 407 response_end_status:1, 408 tx_fes_status_start:1, 409 tx_fes_status_end:1, 410 tx_fes_status_start_ppdu:1, 411 tx_fes_status_user_ppdu:1, 412 tx_fes_status_ack_or_ba:1, 413 tx_fes_status_1k_ba:1, 414 tx_fes_status_start_prot:1, 415 tx_fes_status_prot:1, 416 tx_fes_status_user_response:1, 417 rx_frame_bitmap_ack:1, 418 rx_frame_1k_bitmap_ack:1, 419 coex_tx_status:1, 420 recevied_response_info:1, 421 recevied_response_info_p2:1, 422 ofdma_trigger_details:1, 423 recevied_trigger_info:1, 424 pdg_tx_request:1, 425 pdg_response:1, 426 pdg_trig_response:1, 427 trigger_response_tx_done:1, 428 prot_tx_end:1, 429 ppdu_tx_end:1, 430 r2r_status_end:1, 431 flush_req:1, 432 mactx_phy_desc:1, 433 mactx_user_desc_cmn:1, 434 mactx_user_desc_per_usr:1; 435 uint32_t tqm_acked_1k_mpdu:1, 436 tqm_acked_mpdu:1, 437 tqm_update_tx_mpdu_count:1, 438 phytx_ppdu_header_info_request:1, 439 u_sig_eht_su_mu:1, 440 u_sig_eht_su:1, 441 u_sig_eht_tb:1, 442 eht_sig_usr_su:1, 443 eht_sig_usr_mu_mimo:1, 444 eht_sig_usr_ofdma:1, 445 he_sig_a_su:1, 446 he_sig_a_mu_dl:1, 447 he_sig_a_mu_ul:1, 448 he_sig_b1_mu:1, 449 he_sig_b2_mu:1, 450 he_sig_b2_ofdma:1, 451 vht_sig_b_mu160:1, 452 vht_sig_b_mu80:1, 453 vht_sig_b_mu40:1, 454 vht_sig_b_mu20:1, 455 vht_sig_b_su160:1, 456 vht_sig_b_su80:1, 457 vht_sig_b_su40:1, 458 vht_sig_b_su20:1, 459 vht_sig_a:1, 460 ht_sig:1, 461 l_sig_b:1, 462 l_sig_a:1, 463 tx_service:1; 464 uint32_t txpcu_buf_status:1, 465 txpcu_user_buf_status:1, 466 txdma_stop_request:1, 467 expected_response:1, 468 tx_mpdu_count_transfer_end:1, 469 rx_trig_info:1, 470 rxpcu_tx_setup_clear:1, 471 rx_frame_bitmap_req:1, 472 rx_phy_sleep:1, 473 txpcu_preamble_done:1, 474 txpcu_phytx_debug32:1, 475 txpcu_phytx_other_transmit_info32:1, 476 rx_ppdu_noack_report:1, 477 rx_ppdu_ack_report:1, 478 coex_rx_status:1, 479 rx_start_param:1, 480 tx_cbf_info:1, 481 rxpcu_early_rx_indication:1, 482 received_response_user_7_0:1, 483 received_response_user_15_8:1, 484 received_response_user_23_16:1, 485 received_response_user_31_24:1, 486 received_response_user_36_32:1, 487 rx_pm_info:1, 488 rx_preamble:1, 489 others:1, 490 mactx_pre_phy_desc:1; 491 }; 492 493 /** 494 * struct dp_tx_mon_wordmask_config - Tx monitor word mask 495 * tx_fes_setup: TX_FES_SETUP TLV word mask 496 * tx_peer_entry: TX_PEER_ENTRY TLV word mask 497 * tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask 498 * tx_msdu_start: TX_MSDU_START TLV word mask 499 * tx_mpdu_start: TX_MPDU_START TLV word mask 500 * pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask 501 * rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask 502 */ 503 struct dp_tx_mon_wordmask_config { 504 uint16_t tx_fes_setup; 505 uint16_t tx_peer_entry; 506 uint16_t tx_queue_ext; 507 uint16_t tx_msdu_start; 508 uint16_t tx_mpdu_start; 509 uint32_t pcu_ppdu_setup_init; 510 uint16_t rxpcu_user_setup; 511 }; 512 513 /** 514 * struct htt_tx_ring_tlv_filter - Tx ring TLV filter 515 * enable/disable. 516 * @dtlvs: enable/disable downstream TLVs 517 * @utlvs: enable/disable upstream TLVs 518 * @wmask: enable/disbale word mask subscription 519 * @mgmt_filter: enable/disable mgmt packets 520 * @data_filter: enable/disable data packets 521 * @ctrl_filter: enable/disable ctrl packets 522 * @mgmt_dma_length: configure length for mgmt packet 523 * @ctrl_dma_length: configure length for ctrl packet 524 * @data_dma_length: configure length for data packet 525 * @mgmt_mpdu_end: enable mpdu end tlv for mgmt 526 * @mgmt_msdu_end: enable msdu end tlv for mgmt 527 * @mgmt_msdu_start: enable msdu start tlv for mgmt 528 * @mgmt_mpdu_start: enable mpdu start tlv for mgmt 529 * @ctrl_mpdu_end: enable mpdu end tlv for ctrl 530 * @ctrl_msdu_end: enable msdu end tlv for ctrl 531 * @ctrl_msdu_start: enable msdu start tlv for ctrl 532 * @ctrl_mpdu_start: enable mpdu start tlv for ctrl 533 * @data_mpdu_end: enable mpdu end tlv for data 534 * @data_msdu_end: enable msdu end tlv for data 535 * @data_msdu_start: enable msdu start tlv for data 536 * @data_mpdu_start: enable mpdu start tlv for data 537 * @mgmt_mpdu_log: enable mgmt mpdu level logging 538 * @ctrl_mpdu_log: enable ctrl mpdu level logging 539 * @data_mpdu_log: enable data mpdu level logging 540 * @enable: enable tx monitor 541 * 542 * NOTE: Do not change the layout of this structure 543 */ 544 struct htt_tx_ring_tlv_filter { 545 struct dp_tx_mon_downstream_tlv_config dtlvs; 546 struct dp_tx_mon_upstream_tlv_config utlvs; 547 struct dp_tx_mon_wordmask_config wmask; 548 uint16_t mgmt_filter; 549 uint16_t data_filter; 550 uint16_t ctrl_filter; 551 uint16_t mgmt_dma_length:3, 552 ctrl_dma_length:3, 553 data_dma_length:3; 554 uint16_t mgmt_mpdu_end:1, 555 mgmt_msdu_end:1, 556 mgmt_msdu_start:1, 557 mgmt_mpdu_start:1, 558 ctrl_mpdu_end:1, 559 ctrl_msdu_end:1, 560 ctrl_msdu_start:1, 561 ctrl_mpdu_start:1, 562 data_mpdu_end:1, 563 data_msdu_end:1, 564 data_msdu_start:1, 565 data_mpdu_start:1; 566 uint8_t mgmt_mpdu_log:1, 567 ctrl_mpdu_log:1, 568 data_mpdu_log:1; 569 uint8_t enable:1; 570 }; 571 #endif /* QCA_MONITOR_2_0_SUPPORT */ 572 573 /** 574 * struct htt_rx_ring_tlv_filter - Rx ring TLV filter 575 * enable/disable. 576 * @mpdu_start: enable/disable MPDU start TLV 577 * @msdu_start: enable/disable MSDU start TLV 578 * @packet: enable/disable PACKET TLV 579 * @msdu_end: enable/disable MSDU end TLV 580 * @mpdu_end: enable/disable MPDU end TLV 581 * @packet_header: enable/disable PACKET header TLV 582 * @attention: enable/disable ATTENTION TLV 583 * @ppdu_start: enable/disable PPDU start TLV 584 * @ppdu_end: enable/disable PPDU end TLV 585 * @ppdu_end_user_stats: enable/disable PPDU user stats TLV 586 * @ppdu_end_user_stats_ext: enable/disable PPDU user stats ext TLV 587 * @ppdu_end_status_done: enable/disable PPDU end status done TLV 588 * @enable_fp: enable/disable FP packet 589 * @enable_md: enable/disable MD packet 590 * @enable_mo: enable/disable MO packet 591 * @enable_mgmt: enable/disable MGMT packet 592 * @enable_ctrl: enable/disable CTRL packet 593 * @enable_data: enable/disable DATA packet 594 * @offset_valid: Flag to indicate if below offsets are valid 595 * @rx_packet_offset: Offset of packet payload 596 * @rx_header_offset: Offset of rx_header tlv 597 * @rx_mpdu_end_offset: Offset of rx_mpdu_end tlv 598 * @rx_mpdu_start_offset: Offset of rx_mpdu_start tlv 599 * @rx_msdu_end_offset: Offset of rx_msdu_end tlv 600 * @rx_msdu_start_offset: Offset of rx_msdu_start tlv 601 * @rx_attn_offset: Offset of rx_attention tlv 602 * @fp_phy_err: Flag to indicate FP PHY status tlv 603 * @fp_phy_err_buf_src: source ring selection for the FP PHY ERR status tlv 604 * @fp_phy_err_buf_dest: dest ring selection for the FP PHY ERR status tlv 605 * @phy_err_mask: select the phy errors defined in phyrx_abort_request_reason 606 * enums 0 to 31. 607 * @phy_err_mask_cont: select the fp phy errors defined in 608 * phyrx_abort_request_reason enums 32 to 63 609 * @rx_mpdu_start_wmask: word mask for mpdu start tlv 610 * @rx_mpdu_end_wmask: word mask for mpdu end tlv 611 * @rx_msdu_end_tlv: word mask for msdu end tlv 612 * @rx_pkt_tlv_offset: rx pkt tlv offset 613 * @mgmt_dma_length: configure length for mgmt packet 614 * @ctrl_dma_length: configure length for ctrl packet 615 * @data_dma_length: configure length for data packet 616 * @rx_hdr_length: configure length for rx header tlv 617 * @mgmt_mpdu_log: enable mgmt mpdu level logging 618 * @ctrl_mpdu_log: enable ctrl mpdu level logging 619 * @data_mpdu_log: enable data mpdu level logging 620 * @enable: enable rx monitor 621 * @enable_fpmo: enable/disable FPMO packet 622 * @fpmo_data_filter: FPMO mode data filter 623 * @fpmo_mgmt_filter: FPMO mode mgmt filter 624 * @fpmo_ctrl_filter: FPMO mode ctrl filter 625 * 626 * NOTE: Do not change the layout of this structure 627 */ 628 struct htt_rx_ring_tlv_filter { 629 u_int32_t mpdu_start:1, 630 msdu_start:1, 631 packet:1, 632 msdu_end:1, 633 mpdu_end:1, 634 packet_header:1, 635 attention:1, 636 ppdu_start:1, 637 ppdu_end:1, 638 ppdu_end_user_stats:1, 639 ppdu_end_user_stats_ext:1, 640 ppdu_end_status_done:1, 641 ppdu_start_user_info:1, 642 header_per_msdu:1, 643 enable_fp:1, 644 enable_md:1, 645 enable_mo:1; 646 u_int32_t fp_mgmt_filter:16, 647 mo_mgmt_filter:16; 648 u_int32_t fp_ctrl_filter:16, 649 mo_ctrl_filter:16; 650 u_int32_t fp_data_filter:16, 651 mo_data_filter:16; 652 u_int16_t md_data_filter; 653 u_int16_t md_mgmt_filter; 654 u_int16_t md_ctrl_filter; 655 bool offset_valid; 656 uint16_t rx_packet_offset; 657 uint16_t rx_header_offset; 658 uint16_t rx_mpdu_end_offset; 659 uint16_t rx_mpdu_start_offset; 660 uint16_t rx_msdu_end_offset; 661 uint16_t rx_msdu_start_offset; 662 uint16_t rx_attn_offset; 663 #ifdef QCA_UNDECODED_METADATA_SUPPORT 664 u_int32_t fp_phy_err:1, 665 fp_phy_err_buf_src:2, 666 fp_phy_err_buf_dest:2, 667 phy_err_filter_valid:1; 668 u_int32_t phy_err_mask; 669 u_int32_t phy_err_mask_cont; 670 #endif 671 #ifdef QCA_MONITOR_2_0_SUPPORT 672 uint16_t rx_mpdu_start_wmask; 673 uint16_t rx_mpdu_end_wmask; 674 uint16_t rx_msdu_end_wmask; 675 uint16_t rx_pkt_tlv_offset; 676 uint16_t mgmt_dma_length:3, 677 ctrl_dma_length:3, 678 data_dma_length:3, 679 rx_hdr_length:3, 680 mgmt_mpdu_log:1, 681 ctrl_mpdu_log:1, 682 data_mpdu_log:1, 683 enable:1; 684 u_int16_t enable_fpmo:1; 685 u_int16_t fpmo_data_filter; 686 u_int16_t fpmo_mgmt_filter; 687 u_int16_t fpmo_ctrl_filter; 688 #endif 689 }; 690 691 /** 692 * struct dp_htt_rx_flow_fst_setup - Rx FST setup message 693 * @pdev_id: DP Pdev identifier 694 * @max_entries: Size of Rx FST in number of entries 695 * @max_search: Number of collisions allowed 696 * @base_addr_lo: lower 32-bit physical address 697 * @base_addr_hi: upper 32-bit physical address 698 * @ip_da_sa_prefix: IPv4 prefix to map to IPv6 address scheme 699 * @hash_key_len: Rx FST hash key size 700 * @hash_key: Rx FST Toeplitz hash key 701 */ 702 struct dp_htt_rx_flow_fst_setup { 703 uint8_t pdev_id; 704 uint32_t max_entries; 705 uint32_t max_search; 706 uint32_t base_addr_lo; 707 uint32_t base_addr_hi; 708 uint32_t ip_da_sa_prefix; 709 uint32_t hash_key_len; 710 uint8_t *hash_key; 711 }; 712 713 /** 714 * enum dp_htt_flow_fst_operation - FST related operations allowed 715 * @DP_HTT_FST_CACHE_OP_NONE: Cache no-op 716 * @DP_HTT_FST_CACHE_INVALIDATE_ENTRY: Invalidate single cache entry 717 * @DP_HTT_FST_CACHE_INVALIDATE_FULL: Invalidate entire cache 718 * @DP_HTT_FST_ENABLE: Bypass FST is enabled 719 * @DP_HTT_FST_DISABLE: Disable bypass FST 720 */ 721 enum dp_htt_flow_fst_operation { 722 DP_HTT_FST_CACHE_OP_NONE, 723 DP_HTT_FST_CACHE_INVALIDATE_ENTRY, 724 DP_HTT_FST_CACHE_INVALIDATE_FULL, 725 DP_HTT_FST_ENABLE, 726 DP_HTT_FST_DISABLE 727 }; 728 729 /** 730 * struct dp_htt_rx_flow_fst_setup - Rx FST setup message 731 * @pdev_id: DP Pdev identifier 732 * @op_code: FST operation to be performed by FW/HW 733 * @rx_flow: Rx Flow information on which operation is to be performed 734 */ 735 struct dp_htt_rx_flow_fst_operation { 736 uint8_t pdev_id; 737 enum dp_htt_flow_fst_operation op_code; 738 struct cdp_rx_flow_info *rx_flow; 739 }; 740 741 /** 742 * struct dp_htt_rx_fisa_config - Rx fisa config 743 * @pdev_id: DP Pdev identifier 744 * @fisa_timeout: fisa aggregation timeout 745 */ 746 struct dp_htt_rx_fisa_cfg { 747 uint8_t pdev_id; 748 uint32_t fisa_timeout; 749 }; 750 751 /* 752 * htt_htc_pkt_alloc() - Allocate HTC packet buffer 753 * @htt_soc: HTT SOC handle 754 * 755 * Return: Pointer to htc packet buffer 756 */ 757 struct dp_htt_htc_pkt *htt_htc_pkt_alloc(struct htt_soc *soc); 758 759 /* 760 * htt_htc_pkt_free() - Free HTC packet buffer 761 * @htt_soc: HTT SOC handle 762 */ 763 void 764 htt_htc_pkt_free(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 765 766 #define HTT_HTC_PKT_STATUS_SUCCESS \ 767 ((pkt->htc_pkt.Status != QDF_STATUS_E_CANCELED) && \ 768 (pkt->htc_pkt.Status != QDF_STATUS_E_RESOURCES)) 769 770 #ifdef ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST 771 772 static void 773 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt) 774 { 775 } 776 777 #else /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 778 779 /* 780 * htt_htc_misc_pkt_list_add() - Add pkt to misc list 781 * @htt_soc: HTT SOC handle 782 * @dp_htt_htc_pkt: pkt to be added to list 783 */ 784 void 785 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 786 787 #endif /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 788 789 /** 790 * DP_HTT_SEND_HTC_PKT() - Send htt packet from host 791 * @soc : HTT SOC handle 792 * @pkt: pkt to be send 793 * @cmd : command to be recorded in dp htt logger 794 * @buf : Pointer to buffer needs to be recored for above cmd 795 * 796 * Return: None 797 */ 798 static inline QDF_STATUS DP_HTT_SEND_HTC_PKT(struct htt_soc *soc, 799 struct dp_htt_htc_pkt *pkt, 800 uint8_t cmd, uint8_t *buf) 801 { 802 QDF_STATUS status; 803 804 htt_command_record(soc->htt_logger_handle, cmd, buf); 805 806 status = htc_send_pkt(soc->htc_soc, &pkt->htc_pkt); 807 if (status == QDF_STATUS_SUCCESS && HTT_HTC_PKT_STATUS_SUCCESS) 808 htt_htc_misc_pkt_list_add(soc, pkt); 809 else 810 soc->stats.fail_count++; 811 return status; 812 } 813 814 QDF_STATUS dp_htt_rx_fisa_config(struct dp_pdev *pdev, 815 struct dp_htt_rx_fisa_cfg *fisa_config); 816 817 #ifdef WLAN_SUPPORT_PPEDS 818 819 /** 820 * dp_htt_rxdma_rxole_ppe_config: Rx DMA and RxOLE PPE config 821 * @override: RxDMA override to override the reo_destinatoin_indication 822 * @reo_destination_indication: REO destination indication value 823 * @multi_buffer_msdu_override_en: Override the indicatio for SG 824 * @intra_bss_override: Rx OLE IntraBSS override 825 * @decap_raw_override: Rx Decap Raw override 826 * @decap_nwifi_override: Rx Native override 827 * @ip_frag_override: IP fragments override 828 * @reserved: Reserved 829 */ 830 struct dp_htt_rxdma_rxole_ppe_config { 831 uint32_t override:1, 832 reo_destination_indication:5, 833 multi_buffer_msdu_override_en:1, 834 intra_bss_override:1, 835 decap_raw_override:1, 836 decap_nwifi_override:1, 837 ip_frag_override:1, 838 reserved:21; 839 }; 840 841 QDF_STATUS 842 dp_htt_rxdma_rxole_ppe_cfg_set(struct dp_soc *soc, 843 struct dp_htt_rxdma_rxole_ppe_config *cfg); 844 #endif /* WLAN_SUPPORT_PPEDS */ 845 846 /* 847 * htt_soc_initialize() - SOC level HTT initialization 848 * @htt_soc: Opaque htt SOC handle 849 * @ctrl_psoc: Opaque ctrl SOC handle 850 * @htc_soc: SOC level HTC handle 851 * @hal_soc: Opaque HAL SOC handle 852 * @osdev: QDF device 853 * 854 * Return: HTT handle on success; NULL on failure 855 */ 856 void * 857 htt_soc_initialize(struct htt_soc *htt_soc, 858 struct cdp_ctrl_objmgr_psoc *ctrl_psoc, 859 HTC_HANDLE htc_soc, 860 hal_soc_handle_t hal_soc_hdl, qdf_device_t osdev); 861 862 /* 863 * htt_soc_attach() - attach DP and HTT SOC 864 * @soc: DP SOC handle 865 * @htc_hdl: HTC handle 866 * 867 * Return: htt_soc handle on Success, NULL on Failure 868 */ 869 struct htt_soc *htt_soc_attach(struct dp_soc *soc, HTC_HANDLE htc_hdl); 870 871 /* 872 * htt_set_htc_handle_() - set HTC handle 873 * @htt_hdl: HTT handle/SOC 874 * @htc_soc: HTC handle 875 * 876 * Return: None 877 */ 878 void htt_set_htc_handle(struct htt_soc *htt_hdl, HTC_HANDLE htc_soc); 879 880 /* 881 * htt_get_htc_handle_() - set HTC handle 882 * @htt_hdl: HTT handle/SOC 883 * 884 * Return: HTC_HANDLE 885 */ 886 HTC_HANDLE htt_get_htc_handle(struct htt_soc *htt_hdl); 887 888 /* 889 * htt_soc_htc_dealloc() - HTC memory de-alloc 890 * @htt_soc: SOC level HTT handle 891 * 892 * Return: None 893 */ 894 void htt_soc_htc_dealloc(struct htt_soc *htt_handle); 895 896 /* 897 * htt_soc_htc_prealloc() - HTC memory prealloc 898 * @htt_soc: SOC level HTT handle 899 * 900 * Return: QDF_STATUS_SUCCESS on success or 901 * QDF_STATUS_E_NO_MEM on allocation failure 902 */ 903 QDF_STATUS htt_soc_htc_prealloc(struct htt_soc *htt_soc); 904 905 void htt_soc_detach(struct htt_soc *soc); 906 907 int htt_srng_setup(struct htt_soc *htt_soc, int pdev_id, 908 hal_ring_handle_t hal_ring_hdl, 909 int hal_ring_type); 910 911 int htt_soc_attach_target(struct htt_soc *htt_soc); 912 913 /* 914 * htt_h2t_rx_ring_cfg() - Send SRNG packet and TLV filter 915 * config message to target 916 * @htt_soc: HTT SOC handle 917 * @pdev_id: PDEV Id 918 * @hal_srng: Opaque HAL SRNG pointer 919 * @hal_ring_type: SRNG ring type 920 * @ring_buf_size: SRNG buffer size 921 * @htt_tlv_filter: Rx SRNG TLV and filter setting 922 * 923 * Return: 0 on success; error code on failure 924 */ 925 int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id, 926 hal_ring_handle_t hal_ring_hdl, 927 int hal_ring_type, int ring_buf_size, 928 struct htt_rx_ring_tlv_filter *htt_tlv_filter); 929 930 /* 931 * htt_t2h_stats_handler() - target to host stats work handler 932 * @context: context (dp soc context) 933 * 934 * Return: void 935 */ 936 void htt_t2h_stats_handler(void *context); 937 938 /** 939 * struct htt_stats_context - htt stats information 940 * @soc: Size of each descriptor in the pool 941 * @msg: T2H Ext stats message queue 942 * @msg_len: T2H Ext stats message length 943 */ 944 struct htt_stats_context { 945 struct dp_soc *soc; 946 qdf_nbuf_queue_t msg; 947 uint32_t msg_len; 948 }; 949 950 #ifdef DP_UMAC_HW_RESET_SUPPORT 951 /** 952 * struct dp_htt_umac_reset_setup_cmd_params - Params for UMAC reset setup cmd 953 * @msi_data: MSI data to be used for raising the UMAC reset interrupt 954 * @shmem_addr_low: Lower 32-bits of shared memory 955 * @shmem_addr_high: Higher 32-bits of shared memory 956 */ 957 struct dp_htt_umac_reset_setup_cmd_params { 958 uint32_t msi_data; 959 uint32_t shmem_addr_low; 960 uint32_t shmem_addr_high; 961 }; 962 963 /** 964 * dp_htt_umac_reset_send_setup_cmd(): Send the HTT UMAC reset setup command 965 * @soc: dp soc object 966 * @setup_params: parameters required by this command 967 * 968 * Return: Success when HTT message is sent, error on failure 969 */ 970 QDF_STATUS dp_htt_umac_reset_send_setup_cmd( 971 struct dp_soc *soc, 972 const struct dp_htt_umac_reset_setup_cmd_params *setup_params); 973 #endif 974 975 /** 976 * dp_htt_rx_flow_fst_setup(): Send HTT Rx FST setup message to FW 977 * @pdev: DP pdev handle 978 * @fse_setup_info: FST setup parameters 979 * 980 * Return: Success when HTT message is sent, error on failure 981 */ 982 QDF_STATUS 983 dp_htt_rx_flow_fst_setup(struct dp_pdev *pdev, 984 struct dp_htt_rx_flow_fst_setup *setup_info); 985 986 /** 987 * dp_htt_rx_flow_fse_operation(): Send HTT Flow Search Entry msg to 988 * add/del a flow in HW 989 * @pdev: DP pdev handle 990 * @fse_op_info: Flow entry parameters 991 * 992 * Return: Success when HTT message is sent, error on failure 993 */ 994 QDF_STATUS 995 dp_htt_rx_flow_fse_operation(struct dp_pdev *pdev, 996 struct dp_htt_rx_flow_fst_operation *op_info); 997 998 /** 999 * htt_h2t_full_mon_cfg() - Send full monitor configuarion msg to FW 1000 * 1001 * @htt_soc: HTT Soc handle 1002 * @pdev_id: Radio id 1003 * @dp_full_mon_config: enabled/disable configuration 1004 * 1005 * Return: Success when HTT message is sent, error on failure 1006 */ 1007 int htt_h2t_full_mon_cfg(struct htt_soc *htt_soc, 1008 uint8_t pdev_id, 1009 enum dp_full_mon_config); 1010 1011 /** 1012 * dp_h2t_hw_vdev_stats_config_send: Send HTT command to FW for config 1013 of HW vdev stats 1014 * @dpsoc: Datapath soc handle 1015 * @pdev_id: INVALID_PDEV_ID for all pdevs or 0,1,2 for individual pdev 1016 * @enable: flag to specify enable/disable of stats 1017 * @reset: flag to specify if command is for reset of stats 1018 * @reset_bitmask: bitmask of vdev_id(s) for reset of HW stats 1019 * 1020 * Return: QDF_STATUS 1021 */ 1022 QDF_STATUS dp_h2t_hw_vdev_stats_config_send(struct dp_soc *dpsoc, 1023 uint8_t pdev_id, bool enable, 1024 bool reset, uint64_t reset_bitmask); 1025 1026 static inline enum htt_srng_ring_id 1027 dp_htt_get_mon_htt_ring_id(struct dp_soc *soc, 1028 enum hal_ring_type hal_ring_type) 1029 { 1030 enum htt_srng_ring_id htt_srng_id = 0; 1031 1032 if (wlan_cfg_get_txmon_hw_support(soc->wlan_cfg_ctx)) { 1033 switch (hal_ring_type) { 1034 case RXDMA_MONITOR_BUF: 1035 htt_srng_id = HTT_RX_MON_HOST2MON_BUF_RING; 1036 break; 1037 case RXDMA_MONITOR_DST: 1038 htt_srng_id = HTT_RX_MON_MON2HOST_DEST_RING; 1039 break; 1040 default: 1041 dp_err("Invalid ring type %d ", hal_ring_type); 1042 break; 1043 } 1044 } else { 1045 switch (hal_ring_type) { 1046 case RXDMA_MONITOR_BUF: 1047 htt_srng_id = HTT_RXDMA_MONITOR_BUF_RING; 1048 break; 1049 case RXDMA_MONITOR_DST: 1050 htt_srng_id = HTT_RXDMA_MONITOR_DEST_RING; 1051 break; 1052 default: 1053 dp_err("Invalid ring type %d ", hal_ring_type); 1054 break; 1055 } 1056 } 1057 1058 return htt_srng_id; 1059 } 1060 #endif /* _DP_HTT_H_ */ 1061