1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_HTT_H_ 21 #define _DP_HTT_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_lock.h> 25 #include <qdf_nbuf.h> 26 #include <htc_api.h> 27 28 #include "cdp_txrx_cmn_struct.h" 29 #include "dp_types.h" 30 #ifdef HTT_LOGGER 31 #include "dp_htt_logger.h" 32 #else 33 struct htt_logger; 34 static inline 35 void htt_interface_logging_init(struct htt_logger **htt_logger_handle, 36 struct cdp_ctrl_objmgr_psoc *ctrl_psoc) 37 { 38 } 39 40 static inline 41 void htt_interface_logging_deinit(struct htt_logger *htt_logger_handle) 42 { 43 } 44 45 static inline 46 int htt_command_record(struct htt_logger *h, uint8_t msg_type, 47 uint8_t *msg_data) 48 { 49 return 0; 50 } 51 52 static inline 53 int htt_event_record(struct htt_logger *h, uint8_t msg_type, 54 uint8_t *msg_data) 55 { 56 return 0; 57 } 58 59 static inline 60 int htt_wbm_event_record(struct htt_logger *h, uint8_t tx_status, 61 uint8_t *msg_data) 62 { 63 return 0; 64 } 65 66 #endif 67 68 #define HTT_MGMT_CTRL_TLV_HDR_RESERVERD_LEN 16 69 #define HTT_TLV_HDR_LEN HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 70 #define HTT_SHIFT_UPPER_TIMESTAMP 32 71 #define HTT_MASK_UPPER_TIMESTAMP 0xFFFFFFFF00000000 72 73 /** 74 * htt_htc_pkt_pool_free() - Free HTC packet pool 75 * @soc: HTT SOC handle 76 */ 77 void htt_htc_pkt_pool_free(struct htt_soc *soc); 78 79 #define HTT_TX_MUTEX_TYPE qdf_spinlock_t 80 81 #define HTT_TX_MUTEX_INIT(_mutex) \ 82 qdf_spinlock_create(_mutex) 83 84 #define HTT_TX_MUTEX_ACQUIRE(_mutex) \ 85 qdf_spin_lock_bh(_mutex) 86 87 #define HTT_TX_MUTEX_RELEASE(_mutex) \ 88 qdf_spin_unlock_bh(_mutex) 89 90 #define HTT_TX_MUTEX_DESTROY(_mutex) \ 91 qdf_spinlock_destroy(_mutex) 92 93 #define DP_HTT_MAX_SEND_QUEUE_DEPTH 64 94 95 #ifndef HTT_MAC_ADDR_LEN 96 #define HTT_MAC_ADDR_LEN 6 97 #endif 98 99 #define HTT_FRAMECTRL_TYPE_MASK 0x0C 100 #define HTT_GET_FRAME_CTRL_TYPE(_val) \ 101 (((_val) & HTT_FRAMECTRL_TYPE_MASK) >> 2) 102 #define FRAME_CTRL_TYPE_MGMT 0x0 103 #define FRAME_CTRL_TYPE_CTRL 0x1 104 #define FRAME_CTRL_TYPE_DATA 0x2 105 #define FRAME_CTRL_TYPE_RESV 0x3 106 107 #define HTT_FRAMECTRL_DATATYPE 0x08 108 #define HTT_PPDU_DESC_MAX_DEPTH 16 109 #define DP_SCAN_PEER_ID 0xFFFF 110 111 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 112 #define HTT_RX_DELBA_WIN_SIZE_S 10 113 114 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 115 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 116 117 /* 118 * Set the base misclist size to HTT copy engine source ring size 119 * to guarantee that a packet on the misclist won't be freed while it 120 * is sitting in the copy engine. 121 */ 122 #define DP_HTT_HTC_PKT_MISCLIST_SIZE 2048 123 #define HTT_T2H_MAX_MSG_SIZE 2048 124 125 #define HTT_T2H_EXT_STATS_TLV_START_OFFSET 3 126 127 /* 128 * Below offset are based on htt_ppdu_stats_common_tlv 129 * defined in htt_ppdu_stats.h 130 */ 131 #define HTT_PPDU_STATS_COMMON_TLV_TLV_HDR_OFFSET 0 132 #define HTT_PPDU_STATS_COMMON_TLV_PPDU_ID_OFFSET 1 133 #define HTT_PPDU_STATS_COMMON_TLV_RING_ID_SCH_CMD_ID_OFFSET 2 134 #define HTT_PPDU_STATS_COMMON_TLV_QTYPE_FRM_TYPE_OFFSET 3 135 #define HTT_PPDU_STATS_COMMON_TLV_CHAIN_MASK_OFFSET 4 136 #define HTT_PPDU_STATS_COMMON_TLV_FES_DUR_US_OFFSET 5 137 #define HTT_PPDU_STATS_COMMON_TLV_SCH_EVAL_START_TSTMP_L32_US_OFFSET 6 138 #define HTT_PPDU_STATS_COMMON_TLV_SCH_END_TSTMP_US_OFFSET 7 139 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_L32_US_OFFSET 8 140 #define HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_PHY_MODE_OFFSET 9 141 #define HTT_PPDU_STATS_COMMON_TLV_CCA_DELTA_TIME_US_OFFSET 10 142 #define HTT_PPDU_STATS_COMMON_TLV_RXFRM_DELTA_TIME_US_OFFSET 11 143 #define HTT_PPDU_STATS_COMMON_TLV_TXFRM_DELTA_TIME_US_OFFSET 12 144 #define HTT_PPDU_STATS_COMMON_TLV_RESV_NUM_UL_BEAM_OFFSET 13 145 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_U32_US_OFFSET 14 146 #define HTT_PPDU_STATS_COMMON_TLV_BSSCOLOR_OBSS_PSR_OFFSET 15 147 148 /* get index for field in htt_ppdu_stats_common_tlv */ 149 #define HTT_GET_STATS_CMN_INDEX(index) \ 150 HTT_PPDU_STATS_COMMON_TLV_##index##_OFFSET 151 152 #define HTT_VDEV_STATS_TLV_SOC_DROP_CNT_OFFSET 1 153 154 #define HTT_VDEV_STATS_TLV_HDR_OFFSET 0 155 #define HTT_VDEV_STATS_TLV_VDEV_ID_OFFSET 1 156 #define HTT_VDEV_STATS_TLV_RX_BYTE_CNT_OFFSET 2 157 #define HTT_VDEV_STATS_TLV_RX_PKT_CNT_OFFSET 4 158 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_BYTE_CNT_OFFSET 6 159 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_PKT_CNT_OFFSET 8 160 #define HTT_VDEV_STATS_TLV_TX_RETRY_PKT_CNT_OFFSET 10 161 #define HTT_VDEV_STATS_TLV_TX_DROP_PKT_CNT_OFFSET 12 162 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_PKT_CNT_OFFSET 14 163 #define HTT_VDEV_STATS_TLV_TX_RETRY_BYTE_CNT_OFFSET 16 164 #define HTT_VDEV_STATS_TLV_TX_DROP_BYTE_CNT_OFFSET 18 165 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_BYTE_CNT_OFFSET 20 166 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_PKT_CNT_OFFSET 22 167 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_BYTE_CNT_OFFSET 24 168 169 #define HTT_VDEV_STATS_GET_INDEX(index) \ 170 HTT_VDEV_STATS_TLV_##index##_OFFSET 171 172 #define HTT_VDEV_STATS_U32_SHIFT 0x20 173 #define HTT_VDEV_STATS_U32_MASK 0xFFFFFFFF00000000 174 #define HTT_VDEV_STATS_L32_MASK 0x00000000FFFFFFFF 175 176 #define HTT_VDEV_GET_STATS_U64(msg_word) \ 177 (((((uint64_t)(*(((uint32_t *)msg_word) + 1))) & HTT_VDEV_STATS_L32_MASK) << \ 178 HTT_VDEV_STATS_U32_SHIFT) | ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK)) 179 180 #define HTT_VDEV_GET_STATS_U32(msg_word) \ 181 ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK) 182 183 #define MAX_SCHED_STARVE 100000 184 #define WRAP_DROP_TSF_DELTA 10000 185 #define MAX_TSF_32 0xFFFFFFFF 186 187 #define dp_htt_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT, params) 188 #define dp_htt_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT, params) 189 #define dp_htt_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT, params) 190 #define dp_htt_info(params...) \ 191 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT, ## params) 192 #define dp_htt_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT, params) 193 194 #define dp_htt_tx_stats_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 195 #define dp_htt_tx_stats_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 196 #define dp_htt_tx_stats_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 197 #define dp_htt_tx_stats_info(params...) \ 198 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT_TX_STATS, ## params) 199 #define dp_htt_tx_stats_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 200 201 #define RXMON_GLOBAL_EN_SHIFT 28 202 #ifdef IPA_OPT_WIFI_DP 203 #define MAX_RESERVE_FAIL_ATTEMPT 5 204 #endif 205 206 /** 207 * enum dp_full_mon_config - enum to enable/disable full monitor mode 208 * 209 * @DP_FULL_MON_DISABLE: Disable full monitor mode 210 * @DP_FULL_MON_ENABLE: Enable full monitor mode 211 */ 212 enum dp_full_mon_config { 213 DP_FULL_MON_DISABLE, 214 DP_FULL_MON_ENABLE, 215 }; 216 217 struct dp_htt_htc_pkt { 218 void *soc_ctxt; 219 qdf_dma_addr_t nbuf_paddr; 220 HTC_PACKET htc_pkt; 221 }; 222 223 struct dp_htt_htc_pkt_union { 224 union { 225 struct dp_htt_htc_pkt pkt; 226 struct dp_htt_htc_pkt_union *next; 227 } u; 228 }; 229 230 struct bp_handler { 231 unsigned long bp_start_tt; 232 unsigned long bp_last_tt; 233 unsigned long bp_duration; 234 unsigned long bp_counter; 235 }; 236 237 struct dp_htt_timestamp { 238 struct bp_handler *umac_path; 239 struct bp_handler *lmac_path; 240 }; 241 242 struct htt_soc { 243 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 244 struct dp_soc *dp_soc; 245 hal_soc_handle_t hal_soc; 246 struct dp_htt_timestamp pdevid_tt[MAX_PDEV_CNT]; 247 /* htt_logger handle */ 248 struct htt_logger *htt_logger_handle; 249 HTC_HANDLE htc_soc; 250 qdf_device_t osdev; 251 HTC_ENDPOINT_ID htc_endpoint; 252 struct dp_htt_htc_pkt_union *htt_htc_pkt_freelist; 253 struct dp_htt_htc_pkt_union *htt_htc_pkt_misclist; 254 struct { 255 u_int8_t major; 256 u_int8_t minor; 257 } tgt_ver; 258 struct { 259 u_int8_t major; 260 u_int8_t minor; 261 } wifi_ip_ver; 262 263 struct { 264 int htc_err_cnt; 265 int htc_pkt_free; 266 int skip_count; 267 int fail_count; 268 /* rtpm put skip count for ver req msg */ 269 int htt_ver_req_put_skip; 270 int reserve_fail_cnt; 271 int abort_count; 272 } stats; 273 274 HTT_TX_MUTEX_TYPE htt_tx_mutex; 275 }; 276 277 #ifdef WLAN_PKT_CAPTURE_TX_2_0 278 /** 279 * struct dp_tx_mon_downstream_tlv_config - Enable/Disable TxMon 280 * downstream TLVs 281 * @tx_fes_setup: TX_FES_SETUP TLV 282 * @tx_peer_entry: TX_PEER_ENTRY TLV 283 * @tx_queue_extension: TX_QUEUE_EXTENSION TLV 284 * @tx_last_mpdu_end: TX_LAST_MPDU_END TLV 285 * @tx_last_mpdu_fetched: TX_LAST_MPDU_FETCHED TLV 286 * @tx_data_sync: TX_DATA_SYNC TLV 287 * @pcu_ppdu_setup_init: PCU_PPDU_SETUP_INIT TLV 288 * @fw2s_mon: FW2S_MON TLV 289 * @tx_loopback_setup: TX_LOOPBACK_SETUP TLV 290 * @sch_critical_tlv_ref: SCH_CRITICAL_TLV_REF TLV 291 * @ndp_preamble_done: NDP_PREAMBLE_DONE TLV 292 * @tx_raw_frame_setup: TX_RAW_OR_NATIVE_FRAME_SETUP TLV 293 * @txpcu_user_setup: TXPCU_USER_SETUP TLV 294 * @rxpcu_setup: RXPCU_SETUP TLV 295 * @rxpcu_setup_complete: RXPCU_SETUP_COMPLETE TLV 296 * @coex_tx_req: COEX_TX_REQ TLV 297 * @rxpcu_user_setup: RXPCU_USER_SETUP TLV 298 * @rxpcu_user_setup_ext: RXPCU_USER_SETUP_EXT TLV 299 * @wur_data: WUR_DATA TLV 300 * @tqm_mpdu_global_start: TQM_MPDU_GLOBAL_START 301 * @tx_fes_setup_complete: TX_FES_SETUP_COMPLETE TLV 302 * @scheduler_end: SCHEDULER_END TLV 303 * @sch_wait_instr_tx_path: SCH_WAIT_INSTR_TX_PATH TLV 304 * 305 */ 306 struct dp_tx_mon_downstream_tlv_config { 307 uint32_t tx_fes_setup:1, 308 tx_peer_entry:1, 309 tx_queue_extension:1, 310 tx_last_mpdu_end:1, 311 tx_last_mpdu_fetched:1, 312 tx_data_sync:1, 313 pcu_ppdu_setup_init:1, 314 fw2s_mon:1, 315 tx_loopback_setup:1, 316 sch_critical_tlv_ref:1, 317 ndp_preamble_done:1, 318 tx_raw_frame_setup:1, 319 txpcu_user_setup:1, 320 rxpcu_setup:1, 321 rxpcu_setup_complete:1, 322 coex_tx_req:1, 323 rxpcu_user_setup:1, 324 rxpcu_user_setup_ext:1, 325 wur_data:1, 326 tqm_mpdu_global_start:1, 327 tx_fes_setup_complete:1, 328 scheduler_end:1, 329 sch_wait_instr_tx_path:1; 330 }; 331 332 /** 333 * struct dp_tx_mon_upstream_tlv_config - Enable/Disable TxMon 334 * upstream TLVs 335 * @rx_response_required_info: RX_RESPONSE_REQUIRED_INFO 336 * TLV 337 * @response_start_status: RESPONSE_START_STATUS TLV 338 * @response_end_status: RESPONSE_END_STATUS TLV 339 * @tx_fes_status_start: TX_FES_STATUS_START TLV 340 * @tx_fes_status_end: TX_FES_STATUS_END TLV 341 * @tx_fes_status_start_ppdu: TX_FES_STATUS_START_PPDU TLV 342 * @tx_fes_status_user_ppdu: TX_FES_STATUS_USER_PPDU TLV 343 * @tx_fes_status_ack_or_ba: TX_FES_STATUS_ACK_OR_BA TLV 344 * @tx_fes_status_1k_ba: TX_FES_STATUS_1K_BA TLV 345 * @tx_fes_status_start_prot: TX_FES_STATUS_START_PROTO TLV 346 * @tx_fes_status_prot: TX_FES_STATUS_PROTO TLV 347 * @tx_fes_status_user_response: TX_FES_STATUS_USER_RESPONSE TLV 348 * @rx_frame_bitmap_ack: RX_FRAME_BITMAP_ACK TLV 349 * @rx_frame_1k_bitmap_ack: RX_FRAME_1K_BITMAP_ACK TLV 350 * @coex_tx_status: COEX_TX_STATUS TLV 351 * @received_response_info: RECEIVED_RESPONSE_INFO TLV 352 * @received_response_info_p2: RECEIVED_RESPONSE_INFO_PART2 TLV 353 * @ofdma_trigger_details: OFDMA_TRIGGER_DETAILS 354 * @received_trigger_info: RECEIVED_TRIGGER_INFO 355 * @pdg_tx_request: PDG_TX_REQUEST 356 * @pdg_response: PDG_RESPONSE 357 * @pdg_trig_response: PDG_TRIG_RESPONSE 358 * @trigger_response_tx_done: TRIGGER_RESPONSE_TX_DONE 359 * @prot_tx_end: PROT_TX_END 360 * @ppdu_tx_end: PPDU_TX_END 361 * @r2r_status_end: R2R_STATUS_END 362 * @flush_req: FLUSH_REQ 363 * @mactx_phy_desc: MACTX_PHY_DESC 364 * @mactx_user_desc_cmn: MACTX_USER_DESC_COMMON 365 * @mactx_user_desc_per_usr: MACTX_USER_DESC_PER_USER 366 * @tqm_acked_1k_mpdu: TQM_ACKED_1K_MPDU 367 * @tqm_acked_mpdu: TQM_ACKED_MPDU 368 * @tqm_update_tx_mpdu_count: TQM_UPDATE_TX_MPDU_COUNT 369 * @phytx_ppdu_header_info_request: PHYTX_PPDU_HEADER_INFO_REQUEST 370 * @u_sig_eht_su_mu: U_SIG_EHT_SU_MU 371 * @u_sig_eht_su: U_SIG_EHT_SU 372 * @u_sig_eht_tb: U_SIG_EHT_TB 373 * @eht_sig_usr_su: EHT_SIG_USR_SU 374 * @eht_sig_usr_mu_mimo: EHT_SIG_USR_MU_MIMO 375 * @eht_sig_usr_ofdma: EHT_SIG_USR_MU_MIMO 376 * @he_sig_a_su: HE_SIG_A_SU 377 * @he_sig_a_mu_dl: HE_SIG_A_MU_DL 378 * @he_sig_a_mu_ul: HE_SIG_A_MU_UL 379 * @he_sig_b1_mu: HE_SIG_B1_MU 380 * @he_sig_b2_mu: HE_SIG_B2_MU 381 * @he_sig_b2_ofdma: HE_SIG_B2_OFDMA 382 * @vht_sig_b_mu160: VHT_SIG_B_MU160 383 * @vht_sig_b_mu80: VHT_SIG_B_MU80 384 * @vht_sig_b_mu40: VHT_SIG_B_MU40 385 * @vht_sig_b_mu20: VHT_SIG_B_MU20 386 * @vht_sig_b_su160: VHT_SIG_B_SU160 387 * @vht_sig_b_su80: VHT_SIG_B_SU80 388 * @vht_sig_b_su40: VHT_SIG_B_SU40 389 * @vht_sig_b_su20: VHT_SIG_B_SU20 390 * @vht_sig_a: VHT_SIG_A 391 * @ht_sig: HT_SIG 392 * @l_sig_b: L_SIG_B 393 * @l_sig_a: L_SIG_A 394 * @tx_service: TX_SERVICE 395 * @txpcu_buf_status: TXPCU_BUFFER_STATUS 396 * @txpcu_user_buf_status: TXPCU_USER_BUFFER_STATUS 397 * @txdma_stop_request: TXDMA_STOP_REQUEST 398 * @expected_response: EXPECTED_RESPONSE 399 * @tx_mpdu_count_transfer_end: TX_MPDU_COUNT_TRANSFER_END 400 * @rx_trig_info: RX_TRIG_INFO 401 * @rxpcu_tx_setup_clear: RXPCU_TX_SETUP_CLEAR 402 * @rx_frame_bitmap_req: RX_FRAME_BITMAP_REQ 403 * @rx_phy_sleep: RX_PHY_SLEEP 404 * @txpcu_preamble_done: TXPCU_PREAMBLE_DONE 405 * @txpcu_phytx_debug32: TXPCU_PHYTX_DEBUG32 406 * @txpcu_phytx_other_transmit_info32: TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 407 * @rx_ppdu_noack_report: RX_PPDU_NO_ACK_REPORT 408 * @rx_ppdu_ack_report: RX_PPDU_ACK_REPORT 409 * @coex_rx_status: COEX_RX_STATUS 410 * @rx_start_param: RX_START_PARAM 411 * @tx_cbf_info: TX_CBF_INFO 412 * @rxpcu_early_rx_indication: RXPCU_EARLY_RX_INDICATION 413 * @received_response_user_7_0: RECEIVED_RESPONSE_USER_7_0 414 * @received_response_user_15_8: RECEIVED_RESPONSE_USER_15_8 415 * @received_response_user_23_16: RECEIVED_RESPONSE_USER_23_16 416 * @received_response_user_31_24: RECEIVED_RESPONSE_USER_31_24 417 * @received_response_user_36_32: RECEIVED_RESPONSE_USER_36_32 418 * @rx_pm_info: RX_PM_INFO 419 * @rx_preamble: RX_PREAMBLE 420 * @others: OTHERS 421 * @mactx_pre_phy_desc: MACTX_PRE_PHY_DESC 422 * 423 */ 424 struct dp_tx_mon_upstream_tlv_config { 425 uint32_t rx_response_required_info:1, 426 response_start_status:1, 427 response_end_status:1, 428 tx_fes_status_start:1, 429 tx_fes_status_end:1, 430 tx_fes_status_start_ppdu:1, 431 tx_fes_status_user_ppdu:1, 432 tx_fes_status_ack_or_ba:1, 433 tx_fes_status_1k_ba:1, 434 tx_fes_status_start_prot:1, 435 tx_fes_status_prot:1, 436 tx_fes_status_user_response:1, 437 rx_frame_bitmap_ack:1, 438 rx_frame_1k_bitmap_ack:1, 439 coex_tx_status:1, 440 received_response_info:1, 441 received_response_info_p2:1, 442 ofdma_trigger_details:1, 443 received_trigger_info:1, 444 pdg_tx_request:1, 445 pdg_response:1, 446 pdg_trig_response:1, 447 trigger_response_tx_done:1, 448 prot_tx_end:1, 449 ppdu_tx_end:1, 450 r2r_status_end:1, 451 flush_req:1, 452 mactx_phy_desc:1, 453 mactx_user_desc_cmn:1, 454 mactx_user_desc_per_usr:1; 455 uint32_t tqm_acked_1k_mpdu:1, 456 tqm_acked_mpdu:1, 457 tqm_update_tx_mpdu_count:1, 458 phytx_ppdu_header_info_request:1, 459 u_sig_eht_su_mu:1, 460 u_sig_eht_su:1, 461 u_sig_eht_tb:1, 462 eht_sig_usr_su:1, 463 eht_sig_usr_mu_mimo:1, 464 eht_sig_usr_ofdma:1, 465 he_sig_a_su:1, 466 he_sig_a_mu_dl:1, 467 he_sig_a_mu_ul:1, 468 he_sig_b1_mu:1, 469 he_sig_b2_mu:1, 470 he_sig_b2_ofdma:1, 471 vht_sig_b_mu160:1, 472 vht_sig_b_mu80:1, 473 vht_sig_b_mu40:1, 474 vht_sig_b_mu20:1, 475 vht_sig_b_su160:1, 476 vht_sig_b_su80:1, 477 vht_sig_b_su40:1, 478 vht_sig_b_su20:1, 479 vht_sig_a:1, 480 ht_sig:1, 481 l_sig_b:1, 482 l_sig_a:1, 483 tx_service:1; 484 uint32_t txpcu_buf_status:1, 485 txpcu_user_buf_status:1, 486 txdma_stop_request:1, 487 expected_response:1, 488 tx_mpdu_count_transfer_end:1, 489 rx_trig_info:1, 490 rxpcu_tx_setup_clear:1, 491 rx_frame_bitmap_req:1, 492 rx_phy_sleep:1, 493 txpcu_preamble_done:1, 494 txpcu_phytx_debug32:1, 495 txpcu_phytx_other_transmit_info32:1, 496 rx_ppdu_noack_report:1, 497 rx_ppdu_ack_report:1, 498 coex_rx_status:1, 499 rx_start_param:1, 500 tx_cbf_info:1, 501 rxpcu_early_rx_indication:1, 502 received_response_user_7_0:1, 503 received_response_user_15_8:1, 504 received_response_user_23_16:1, 505 received_response_user_31_24:1, 506 received_response_user_36_32:1, 507 rx_pm_info:1, 508 rx_preamble:1, 509 others:1, 510 mactx_pre_phy_desc:1; 511 }; 512 513 /** 514 * struct dp_tx_mon_wordmask_config - Tx monitor word mask 515 * @pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask 516 * @tx_peer_entry: TX_PEER_ENTRY TLV word mask 517 * @tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask 518 * @tx_fes_status_end: TX_FES_STATUS_END TLV word mask 519 * @response_end_status: RESPONSE_END_STATUS TLV word mask 520 * @tx_fes_status_prot: TX_FES_STATUS_PROT TLV word mask 521 * @tx_fes_setup: TX_FES_SETUP TLV word mask 522 * @tx_msdu_start: TX_MSDU_START TLV word mask 523 * @tx_mpdu_start: TX_MPDU_START TLV word mask 524 * @rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask 525 */ 526 struct dp_tx_mon_wordmask_config { 527 uint32_t pcu_ppdu_setup_init; 528 uint16_t tx_peer_entry; 529 uint16_t tx_queue_ext; 530 uint16_t tx_fes_status_end; 531 uint16_t response_end_status; 532 uint16_t tx_fes_status_prot; 533 uint8_t tx_fes_setup; 534 uint8_t tx_msdu_start; 535 uint8_t tx_mpdu_start; 536 uint8_t rxpcu_user_setup; 537 }; 538 539 /** 540 * struct htt_tx_ring_tlv_filter - Tx ring TLV filter 541 * enable/disable. 542 * @dtlvs: enable/disable downstream TLVs 543 * @utlvs: enable/disable upstream TLVs 544 * @wmask: enable/disable word mask subscription 545 * @compaction_enable: word mask compaction enable 546 * @mgmt_filter: enable/disable mgmt packets 547 * @data_filter: enable/disable data packets 548 * @ctrl_filter: enable/disable ctrl packets 549 * @mgmt_dma_length: configure length for mgmt packet 550 * @ctrl_dma_length: configure length for ctrl packet 551 * @data_dma_length: configure length for data packet 552 * @mgmt_mpdu_end: enable mpdu end tlv for mgmt 553 * @mgmt_msdu_end: enable msdu end tlv for mgmt 554 * @mgmt_msdu_start: enable msdu start tlv for mgmt 555 * @mgmt_mpdu_start: enable mpdu start tlv for mgmt 556 * @ctrl_mpdu_end: enable mpdu end tlv for ctrl 557 * @ctrl_msdu_end: enable msdu end tlv for ctrl 558 * @ctrl_msdu_start: enable msdu start tlv for ctrl 559 * @ctrl_mpdu_start: enable mpdu start tlv for ctrl 560 * @data_mpdu_end: enable mpdu end tlv for data 561 * @data_msdu_end: enable msdu end tlv for data 562 * @data_msdu_start: enable msdu start tlv for data 563 * @data_mpdu_start: enable mpdu start tlv for data 564 * @mgmt_mpdu_log: enable mgmt mpdu level logging 565 * @ctrl_mpdu_log: enable ctrl mpdu level logging 566 * @data_mpdu_log: enable data mpdu level logging 567 * @enable: enable tx monitor 568 * 569 * NOTE: Do not change the layout of this structure 570 */ 571 struct htt_tx_ring_tlv_filter { 572 struct dp_tx_mon_downstream_tlv_config dtlvs; 573 struct dp_tx_mon_upstream_tlv_config utlvs; 574 struct dp_tx_mon_wordmask_config wmask; 575 uint8_t compaction_enable; 576 uint16_t mgmt_filter; 577 uint16_t data_filter; 578 uint16_t ctrl_filter; 579 uint16_t mgmt_dma_length:3, 580 ctrl_dma_length:3, 581 data_dma_length:3; 582 uint16_t mgmt_mpdu_end:1, 583 mgmt_msdu_end:1, 584 mgmt_msdu_start:1, 585 mgmt_mpdu_start:1, 586 ctrl_mpdu_end:1, 587 ctrl_msdu_end:1, 588 ctrl_msdu_start:1, 589 ctrl_mpdu_start:1, 590 data_mpdu_end:1, 591 data_msdu_end:1, 592 data_msdu_start:1, 593 data_mpdu_start:1; 594 uint8_t mgmt_mpdu_log:1, 595 ctrl_mpdu_log:1, 596 data_mpdu_log:1; 597 uint8_t enable:1; 598 }; 599 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 600 601 /** 602 * struct htt_rx_ring_tlv_filter - Rx ring TLV filter 603 * enable/disable. 604 * @mpdu_start: enable/disable MPDU start TLV 605 * @msdu_start: enable/disable MSDU start TLV 606 * @packet: enable/disable PACKET TLV 607 * @msdu_end: enable/disable MSDU end TLV 608 * @mpdu_end: enable/disable MPDU end TLV 609 * @packet_header: enable/disable PACKET header TLV 610 * @attention: enable/disable ATTENTION TLV 611 * @ppdu_start: enable/disable PPDU start TLV 612 * @ppdu_end: enable/disable PPDU end TLV 613 * @ppdu_end_user_stats: enable/disable PPDU user stats TLV 614 * @ppdu_end_user_stats_ext: enable/disable PPDU user stats ext TLV 615 * @ppdu_end_status_done: enable/disable PPDU end status done TLV 616 * @ppdu_start_user_info: 617 * @header_per_msdu: 618 * @enable_fp: enable/disable FP packet 619 * @enable_md: enable/disable MD packet 620 * @enable_mo: enable/disable MO packet 621 * @fp_mgmt_filter: 622 * @mo_mgmt_filter: 623 * @fp_ctrl_filter: 624 * @mo_ctrl_filter: 625 * @fp_data_filter: 626 * @mo_data_filter: 627 * @md_data_filter: 628 * @md_mgmt_filter: 629 * @md_ctrl_filter: 630 * @offset_valid: Flag to indicate if below offsets are valid 631 * @rx_packet_offset: Offset of packet payload 632 * @rx_header_offset: Offset of rx_header tlv 633 * @rx_mpdu_end_offset: Offset of rx_mpdu_end tlv 634 * @rx_mpdu_start_offset: Offset of rx_mpdu_start tlv 635 * @rx_msdu_end_offset: Offset of rx_msdu_end tlv 636 * @rx_msdu_start_offset: Offset of rx_msdu_start tlv 637 * @rx_attn_offset: Offset of rx_attention tlv 638 * @fp_phy_err: Flag to indicate FP PHY status tlv 639 * @fp_phy_err_buf_src: source ring selection for the FP PHY ERR status tlv 640 * @fp_phy_err_buf_dest: dest ring selection for the FP PHY ERR status tlv 641 * @phy_err_filter_valid: 642 * @phy_err_mask: select the phy errors defined in phyrx_abort_request_reason 643 * enums 0 to 31. 644 * @phy_err_mask_cont: select the fp phy errors defined in 645 * phyrx_abort_request_reason enums 32 to 63 646 * @rx_mpdu_start_wmask: word mask for mpdu start tlv 647 * @rx_mpdu_end_wmask: word mask for mpdu end tlv 648 * @rx_msdu_end_wmask: word mask for msdu end tlv 649 * @rx_pkt_tlv_offset: rx pkt tlv offset 650 * @mgmt_dma_length: configure length for mgmt packet 651 * @ctrl_dma_length: configure length for ctrl packet 652 * @data_dma_length: configure length for data packet 653 * @rx_hdr_length: configure length for rx header tlv 654 * @mgmt_mpdu_log: enable mgmt mpdu level logging 655 * @ctrl_mpdu_log: enable ctrl mpdu level logging 656 * @data_mpdu_log: enable data mpdu level logging 657 * @enable: enable rx monitor 658 * @enable_fpmo: enable/disable FPMO packet 659 * @fpmo_data_filter: FPMO mode data filter 660 * @fpmo_mgmt_filter: FPMO mode mgmt filter 661 * @fpmo_ctrl_filter: FPMO mode ctrl filter 662 * @enable_mon_mac_filter: enable/disable mac based filter on scan radio 663 * 664 * NOTE: Do not change the layout of this structure 665 */ 666 struct htt_rx_ring_tlv_filter { 667 u_int32_t mpdu_start:1, 668 msdu_start:1, 669 packet:1, 670 msdu_end:1, 671 mpdu_end:1, 672 packet_header:1, 673 attention:1, 674 ppdu_start:1, 675 ppdu_end:1, 676 ppdu_end_user_stats:1, 677 ppdu_end_user_stats_ext:1, 678 ppdu_end_status_done:1, 679 ppdu_start_user_info:1, 680 header_per_msdu:1, 681 enable_fp:1, 682 enable_md:1, 683 enable_mo:1; 684 u_int32_t fp_mgmt_filter:16, 685 mo_mgmt_filter:16; 686 u_int32_t fp_ctrl_filter:16, 687 mo_ctrl_filter:16; 688 u_int32_t fp_data_filter:16, 689 mo_data_filter:16; 690 u_int16_t md_data_filter; 691 u_int16_t md_mgmt_filter; 692 u_int16_t md_ctrl_filter; 693 bool offset_valid; 694 uint16_t rx_packet_offset; 695 uint16_t rx_header_offset; 696 uint16_t rx_mpdu_end_offset; 697 uint16_t rx_mpdu_start_offset; 698 uint16_t rx_msdu_end_offset; 699 uint16_t rx_msdu_start_offset; 700 uint16_t rx_attn_offset; 701 #ifdef QCA_UNDECODED_METADATA_SUPPORT 702 u_int32_t fp_phy_err:1, 703 fp_phy_err_buf_src:2, 704 fp_phy_err_buf_dest:2, 705 phy_err_filter_valid:1; 706 u_int32_t phy_err_mask; 707 u_int32_t phy_err_mask_cont; 708 #endif 709 #if defined(WLAN_PKT_CAPTURE_RX_2_0) || defined(CONFIG_WORD_BASED_TLV) || \ 710 defined(CONFIG_MON_WORD_BASED_TLV) || \ 711 defined(WLAN_FEATURE_LOCAL_PKT_CAPTURE) 712 uint32_t rx_mpdu_start_wmask; 713 uint16_t rx_mpdu_end_wmask; 714 uint32_t rx_msdu_end_wmask; 715 uint16_t rx_pkt_tlv_offset; 716 uint16_t mgmt_dma_length:3, 717 ctrl_dma_length:3, 718 data_dma_length:3, 719 rx_hdr_length:3, 720 mgmt_mpdu_log:1, 721 ctrl_mpdu_log:1, 722 data_mpdu_log:1, 723 enable:1; 724 u_int16_t enable_fpmo:1; 725 u_int16_t fpmo_data_filter; 726 u_int16_t fpmo_mgmt_filter; 727 u_int16_t fpmo_ctrl_filter; 728 #endif 729 bool enable_mon_mac_filter; 730 }; 731 732 /** 733 * struct dp_htt_rx_flow_fst_setup - Rx FST setup message 734 * @pdev_id: DP Pdev identifier 735 * @max_entries: Size of Rx FST in number of entries 736 * @max_search: Number of collisions allowed 737 * @base_addr_lo: lower 32-bit physical address 738 * @base_addr_hi: upper 32-bit physical address 739 * @ip_da_sa_prefix: IPv4 prefix to map to IPv6 address scheme 740 * @hash_key_len: Rx FST hash key size 741 * @hash_key: Rx FST Toeplitz hash key 742 */ 743 struct dp_htt_rx_flow_fst_setup { 744 uint8_t pdev_id; 745 uint32_t max_entries; 746 uint32_t max_search; 747 uint32_t base_addr_lo; 748 uint32_t base_addr_hi; 749 uint32_t ip_da_sa_prefix; 750 uint32_t hash_key_len; 751 uint8_t *hash_key; 752 }; 753 754 /** 755 * enum dp_htt_flow_fst_operation - FST related operations allowed 756 * @DP_HTT_FST_CACHE_OP_NONE: Cache no-op 757 * @DP_HTT_FST_CACHE_INVALIDATE_ENTRY: Invalidate single cache entry 758 * @DP_HTT_FST_CACHE_INVALIDATE_FULL: Invalidate entire cache 759 * @DP_HTT_FST_ENABLE: Bypass FST is enabled 760 * @DP_HTT_FST_DISABLE: Disable bypass FST 761 */ 762 enum dp_htt_flow_fst_operation { 763 DP_HTT_FST_CACHE_OP_NONE, 764 DP_HTT_FST_CACHE_INVALIDATE_ENTRY, 765 DP_HTT_FST_CACHE_INVALIDATE_FULL, 766 DP_HTT_FST_ENABLE, 767 DP_HTT_FST_DISABLE 768 }; 769 770 /** 771 * struct dp_htt_rx_flow_fst_operation - Rx FST operation message 772 * @pdev_id: DP Pdev identifier 773 * @op_code: FST operation to be performed by FW/HW 774 * @rx_flow: Rx Flow information on which operation is to be performed 775 */ 776 struct dp_htt_rx_flow_fst_operation { 777 uint8_t pdev_id; 778 enum dp_htt_flow_fst_operation op_code; 779 struct cdp_rx_flow_info *rx_flow; 780 }; 781 782 /** 783 * struct dp_htt_rx_fisa_cfg - Rx fisa config 784 * @pdev_id: DP Pdev identifier 785 * @fisa_timeout: fisa aggregation timeout 786 * @max_aggr_supported: FISA max MSDU aggregation supported 787 */ 788 struct dp_htt_rx_fisa_cfg { 789 uint8_t pdev_id; 790 uint32_t fisa_timeout; 791 uint8_t max_aggr_supported; 792 }; 793 794 /** 795 * htt_htc_pkt_alloc() - Allocate HTC packet buffer 796 * @soc: HTT SOC handle 797 * 798 * Return: Pointer to htc packet buffer 799 */ 800 struct dp_htt_htc_pkt *htt_htc_pkt_alloc(struct htt_soc *soc); 801 802 /** 803 * htt_htc_pkt_free() - Free HTC packet buffer 804 * @soc: HTT SOC handle 805 * @pkt: packet to free 806 */ 807 void 808 htt_htc_pkt_free(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 809 810 #define HTT_HTC_PKT_STATUS_SUCCESS \ 811 ((pkt->htc_pkt.Status != QDF_STATUS_E_CANCELED) && \ 812 (pkt->htc_pkt.Status != QDF_STATUS_E_RESOURCES)) 813 814 #ifdef ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST 815 816 static void 817 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt) 818 { 819 } 820 821 #else /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 822 823 /** 824 * htt_htc_misc_pkt_list_add() - Add pkt to misc list 825 * @soc: HTT SOC handle 826 * @pkt: pkt to be added to list 827 */ 828 void 829 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 830 831 #endif /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 832 833 /** 834 * DP_HTT_SEND_HTC_PKT() - Send htt packet from host 835 * @soc : HTT SOC handle 836 * @pkt: pkt to be send 837 * @cmd : command to be recorded in dp htt logger 838 * @buf : Pointer to buffer needs to be recorded for above cmd 839 * 840 * Return: None 841 */ 842 static inline QDF_STATUS DP_HTT_SEND_HTC_PKT(struct htt_soc *soc, 843 struct dp_htt_htc_pkt *pkt, 844 uint8_t cmd, uint8_t *buf) 845 { 846 QDF_STATUS status; 847 848 htt_command_record(soc->htt_logger_handle, cmd, buf); 849 850 status = htc_send_pkt(soc->htc_soc, &pkt->htc_pkt); 851 if (status == QDF_STATUS_SUCCESS && HTT_HTC_PKT_STATUS_SUCCESS) 852 htt_htc_misc_pkt_list_add(soc, pkt); 853 else 854 soc->stats.fail_count++; 855 return status; 856 } 857 858 /** 859 * dp_htt_rx_fisa_config(): Send HTT msg to configure FISA 860 * @pdev: DP pdev handle 861 * @fisa_config: Flow entry parameters 862 * 863 * Return: Success when HTT message is sent, error on failure 864 */ 865 QDF_STATUS dp_htt_rx_fisa_config(struct dp_pdev *pdev, 866 struct dp_htt_rx_fisa_cfg *fisa_config); 867 868 #ifdef WLAN_SUPPORT_PPEDS 869 870 /** 871 * struct dp_htt_rxdma_rxole_ppe_config - Rx DMA and RxOLE PPE config 872 * @override: RxDMA override to override the reo_destinatoin_indication 873 * @reo_destination_indication: REO destination indication value 874 * @multi_buffer_msdu_override_en: Override the indicatio for SG 875 * @intra_bss_override: Rx OLE IntraBSS override 876 * @decap_raw_override: Rx Decap Raw override 877 * @decap_nwifi_override: Rx Native override 878 * @ip_frag_override: IP fragments override 879 * @reserved: Reserved 880 */ 881 struct dp_htt_rxdma_rxole_ppe_config { 882 uint32_t override:1, 883 reo_destination_indication:5, 884 multi_buffer_msdu_override_en:1, 885 intra_bss_override:1, 886 decap_raw_override:1, 887 decap_nwifi_override:1, 888 ip_frag_override:1, 889 reserved:21; 890 }; 891 892 /** 893 * dp_htt_rxdma_rxole_ppe_cfg_set() - Send RxOLE and RxDMA PPE config 894 * @soc: Data path SoC handle 895 * @cfg: RxDMA and RxOLE PPE config 896 * 897 * Return: Success when HTT message is sent, error on failure 898 */ 899 QDF_STATUS 900 dp_htt_rxdma_rxole_ppe_cfg_set(struct dp_soc *soc, 901 struct dp_htt_rxdma_rxole_ppe_config *cfg); 902 #endif /* WLAN_SUPPORT_PPEDS */ 903 904 /** 905 * htt_soc_initialize() - SOC level HTT initialization 906 * @htt_soc: Opaque htt SOC handle 907 * @ctrl_psoc: Opaque ctrl SOC handle 908 * @htc_soc: SOC level HTC handle 909 * @hal_soc_hdl: Opaque HAL SOC handle 910 * @osdev: QDF device 911 * 912 * Return: HTT handle on success; NULL on failure 913 */ 914 void * 915 htt_soc_initialize(struct htt_soc *htt_soc, 916 struct cdp_ctrl_objmgr_psoc *ctrl_psoc, 917 HTC_HANDLE htc_soc, 918 hal_soc_handle_t hal_soc_hdl, qdf_device_t osdev); 919 920 /** 921 * dp_htt_h2t_full() - Send full handler (called from HTC) 922 * @context: Opaque context (HTT SOC handle) 923 * @pkt: HTC packet 924 * 925 * Return: enum htc_send_full_action 926 */ 927 enum htc_send_full_action 928 dp_htt_h2t_full(void *context, HTC_PACKET *pkt); 929 930 /** 931 * dp_htt_h2t_send_complete() - H2T completion handler 932 * @context: Opaque context (HTT SOC handle) 933 * @htc_pkt: HTC packet 934 */ 935 void 936 dp_htt_h2t_send_complete(void *context, HTC_PACKET *htc_pkt); 937 938 /** 939 * dp_htt_hif_t2h_hp_callback() - HIF callback for high priority T2H messages 940 * @context: Opaque context (HTT SOC handle) 941 * @nbuf: nbuf containing T2H message 942 * @pipe_id: HIF pipe ID 943 * 944 * Return: QDF_STATUS 945 * 946 * TODO: Temporary change to bypass HTC connection for this new HIF pipe, which 947 * will be used for packet log and other high-priority HTT messages. Proper 948 * HTC connection to be added later once required FW changes are available 949 */ 950 QDF_STATUS 951 dp_htt_hif_t2h_hp_callback(void *context, qdf_nbuf_t nbuf, uint8_t pipe_id); 952 953 /** 954 * htt_soc_attach() - attach DP and HTT SOC 955 * @soc: DP SOC handle 956 * @htc_hdl: HTC handle 957 * 958 * Return: htt_soc handle on Success, NULL on Failure 959 */ 960 struct htt_soc *htt_soc_attach(struct dp_soc *soc, HTC_HANDLE htc_hdl); 961 962 /** 963 * htt_set_htc_handle() - set HTC handle 964 * @htt_hdl: HTT handle/SOC 965 * @htc_soc: HTC handle 966 * 967 * Return: None 968 */ 969 void htt_set_htc_handle(struct htt_soc *htt_hdl, HTC_HANDLE htc_soc); 970 971 /** 972 * htt_get_htc_handle() - set HTC handle 973 * @htt_hdl: HTT handle/SOC 974 * 975 * Return: HTC_HANDLE 976 */ 977 HTC_HANDLE htt_get_htc_handle(struct htt_soc *htt_hdl); 978 979 /** 980 * htt_soc_htc_dealloc() - HTC memory de-alloc 981 * @htt_handle: SOC level HTT handle 982 * 983 * Return: None 984 */ 985 void htt_soc_htc_dealloc(struct htt_soc *htt_handle); 986 987 /** 988 * htt_soc_htc_prealloc() - HTC memory prealloc 989 * @htt_soc: SOC level HTT handle 990 * 991 * Return: QDF_STATUS_SUCCESS on success or 992 * QDF_STATUS_E_NO_MEM on allocation failure 993 */ 994 QDF_STATUS htt_soc_htc_prealloc(struct htt_soc *htt_soc); 995 996 /** 997 * htt_soc_detach() - Free SOC level HTT handle 998 * @htt_hdl: HTT SOC handle 999 */ 1000 void htt_soc_detach(struct htt_soc *htt_hdl); 1001 1002 /** 1003 * htt_srng_setup() - Send SRNG setup message to target 1004 * @htt_soc: HTT SOC handle 1005 * @pdev_id: pdev Id 1006 * @hal_ring_hdl: Opaque HAL SRNG pointer 1007 * @hal_ring_type: SRNG ring type 1008 * 1009 * Return: 0 on success; error code on failure 1010 */ 1011 int htt_srng_setup(struct htt_soc *htt_soc, int pdev_id, 1012 hal_ring_handle_t hal_ring_hdl, 1013 int hal_ring_type); 1014 1015 /** 1016 * htt_soc_attach_target() - SOC level HTT setup 1017 * @htt_soc: HTT SOC handle 1018 * 1019 * Return: 0 on success; error code on failure 1020 */ 1021 int htt_soc_attach_target(struct htt_soc *htt_soc); 1022 1023 /** 1024 * htt_h2t_rx_ring_cfg() - Send SRNG packet and TLV filter 1025 * config message to target 1026 * @htt_soc: HTT SOC handle 1027 * @pdev_id: PDEV Id 1028 * @hal_ring_hdl: Opaque HAL SRNG pointer 1029 * @hal_ring_type: SRNG ring type 1030 * @ring_buf_size: SRNG buffer size 1031 * @htt_tlv_filter: Rx SRNG TLV and filter setting 1032 * 1033 * Return: 0 on success; error code on failure 1034 */ 1035 int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id, 1036 hal_ring_handle_t hal_ring_hdl, 1037 int hal_ring_type, int ring_buf_size, 1038 struct htt_rx_ring_tlv_filter *htt_tlv_filter); 1039 1040 /** 1041 * dp_htt_t2h_msg_handler() - Generic Target to host Msg/event handler 1042 * @context: Opaque context (HTT SOC handle) 1043 * @pkt: HTC packet 1044 */ 1045 void dp_htt_t2h_msg_handler(void *context, HTC_PACKET *pkt); 1046 1047 /** 1048 * htt_t2h_stats_handler() - target to host stats work handler 1049 * @context: context (dp soc context) 1050 * 1051 * Return: void 1052 */ 1053 void htt_t2h_stats_handler(void *context); 1054 1055 /** 1056 * struct htt_stats_context - htt stats information 1057 * @soc: Size of each descriptor in the pool 1058 * @msg: T2H Ext stats message queue 1059 * @msg_len: T2H Ext stats message length 1060 */ 1061 struct htt_stats_context { 1062 struct dp_soc *soc; 1063 qdf_nbuf_queue_t msg; 1064 uint32_t msg_len; 1065 }; 1066 1067 #ifdef DP_UMAC_HW_RESET_SUPPORT 1068 /** 1069 * struct dp_htt_umac_reset_setup_cmd_params - Params for UMAC reset setup cmd 1070 * @msi_data: MSI data to be used for raising the UMAC reset interrupt 1071 * @shmem_addr_low: Lower 32-bits of shared memory 1072 * @shmem_addr_high: Higher 32-bits of shared memory 1073 */ 1074 struct dp_htt_umac_reset_setup_cmd_params { 1075 uint32_t msi_data; 1076 uint32_t shmem_addr_low; 1077 uint32_t shmem_addr_high; 1078 }; 1079 1080 /** 1081 * dp_htt_umac_reset_send_setup_cmd(): Send the HTT UMAC reset setup command 1082 * @soc: dp soc object 1083 * @setup_params: parameters required by this command 1084 * 1085 * Return: Success when HTT message is sent, error on failure 1086 */ 1087 QDF_STATUS dp_htt_umac_reset_send_setup_cmd( 1088 struct dp_soc *soc, 1089 const struct dp_htt_umac_reset_setup_cmd_params *setup_params); 1090 1091 /** 1092 * dp_htt_umac_reset_send_start_pre_reset_cmd() - Send the HTT UMAC reset start 1093 * pre reset command 1094 * @soc: dp soc object 1095 * @is_initiator: Indicates whether the target needs to execute the 1096 * UMAC-recovery in context of the Initiator or Non-Initiator. The value zero 1097 * indicates this target is Non-Initiator. 1098 * @is_umac_hang: Indicates whether MLO UMAC recovery executed in context of 1099 * UMAC hang or Target recovery. 1100 * 1101 * Return: Success when HTT message is sent, error on failure 1102 */ 1103 QDF_STATUS dp_htt_umac_reset_send_start_pre_reset_cmd( 1104 struct dp_soc *soc, bool is_initiator, bool is_umac_hang); 1105 #endif 1106 1107 /** 1108 * dp_htt_rx_flow_fst_setup() - Send HTT Rx FST setup message to FW 1109 * @pdev: DP pdev handle 1110 * @fse_setup_info: FST setup parameters 1111 * 1112 * Return: Success when HTT message is sent, error on failure 1113 */ 1114 QDF_STATUS 1115 dp_htt_rx_flow_fst_setup(struct dp_pdev *pdev, 1116 struct dp_htt_rx_flow_fst_setup *fse_setup_info); 1117 1118 /** 1119 * dp_htt_rx_flow_fse_operation(): Send HTT Flow Search Entry msg to 1120 * add/del a flow in HW 1121 * @pdev: DP pdev handle 1122 * @fse_op_info: Flow entry parameters 1123 * 1124 * Return: Success when HTT message is sent, error on failure 1125 */ 1126 QDF_STATUS 1127 dp_htt_rx_flow_fse_operation(struct dp_pdev *pdev, 1128 struct dp_htt_rx_flow_fst_operation *fse_op_info); 1129 1130 /** 1131 * htt_h2t_full_mon_cfg() - Send full monitor configuration msg to FW 1132 * 1133 * @htt_soc: HTT Soc handle 1134 * @pdev_id: Radio id 1135 * @dp_full_mon_config: enabled/disable configuration 1136 * 1137 * Return: Success when HTT message is sent, error on failure 1138 */ 1139 int htt_h2t_full_mon_cfg(struct htt_soc *htt_soc, 1140 uint8_t pdev_id, 1141 enum dp_full_mon_config); 1142 1143 /** 1144 * dp_h2t_hw_vdev_stats_config_send: Send HTT command to FW for config 1145 * of HW vdev stats 1146 * @dpsoc: Datapath soc handle 1147 * @pdev_id: INVALID_PDEV_ID for all pdevs or 0,1,2 for individual pdev 1148 * @enable: flag to specify enable/disable of stats 1149 * @reset: flag to specify if command is for reset of stats 1150 * @reset_bitmask: bitmask of vdev_id(s) for reset of HW stats 1151 * 1152 * Return: QDF_STATUS 1153 */ 1154 QDF_STATUS dp_h2t_hw_vdev_stats_config_send(struct dp_soc *dpsoc, 1155 uint8_t pdev_id, bool enable, 1156 bool reset, uint64_t reset_bitmask); 1157 1158 static inline enum htt_srng_ring_id 1159 dp_htt_get_mon_htt_ring_id(struct dp_soc *soc, 1160 enum hal_ring_type hal_ring_type) 1161 { 1162 enum htt_srng_ring_id htt_srng_id = 0; 1163 1164 if (wlan_cfg_get_txmon_hw_support(soc->wlan_cfg_ctx)) { 1165 switch (hal_ring_type) { 1166 case RXDMA_MONITOR_BUF: 1167 htt_srng_id = HTT_RX_MON_HOST2MON_BUF_RING; 1168 break; 1169 case RXDMA_MONITOR_DST: 1170 htt_srng_id = HTT_RX_MON_MON2HOST_DEST_RING; 1171 break; 1172 default: 1173 dp_err("Invalid ring type %d ", hal_ring_type); 1174 break; 1175 } 1176 } else { 1177 switch (hal_ring_type) { 1178 case RXDMA_MONITOR_BUF: 1179 htt_srng_id = HTT_RXDMA_MONITOR_BUF_RING; 1180 break; 1181 case RXDMA_MONITOR_DST: 1182 htt_srng_id = HTT_RXDMA_MONITOR_DEST_RING; 1183 break; 1184 default: 1185 dp_err("Invalid ring type %d ", hal_ring_type); 1186 break; 1187 } 1188 } 1189 1190 return htt_srng_id; 1191 } 1192 1193 #ifdef IPA_OPT_WIFI_DP 1194 /** 1195 * htt_h2t_rx_cce_super_rule_setup() - htt message to set cce super rules 1196 * 1197 * @htt_soc: HTT Soc handle 1198 * @flt_params: Filter tuple 1199 * 1200 * Return: QDF_STATUS 1201 */ 1202 QDF_STATUS htt_h2t_rx_cce_super_rule_setup(struct htt_soc *htt_soc, 1203 void *flt_params); 1204 #endif 1205 1206 #ifdef QCA_SUPPORT_PRIMARY_LINK_MIGRATE 1207 /** 1208 * struct dp_peer_info - Primary Peer information 1209 * @primary_peer_id: Primary peer id 1210 * @chip_id: Chip id of primary peer 1211 * @hw_peer_id: ast hash index 1212 * @ast_hash: ast hash value 1213 */ 1214 struct dp_peer_info { 1215 uint16_t primary_peer_id; 1216 uint8_t chip_id; 1217 uint16_t hw_peer_id; 1218 uint16_t ast_hash; 1219 }; 1220 1221 /** 1222 * dp_h2t_ptqm_migration_msg_send() - Send H2T PTQM message to FW 1223 * @dp_soc: DP SOC handle 1224 * @vdev_id: Vdev id of primary peer 1225 * @pdev_id: Pdev id of primary peer 1226 * @chip_id: Chip id of primary peer 1227 * @peer_id: Peer id of primary peer 1228 * @ml_peer_id: Peer id of MLD peer 1229 * @src_info: source info for DS 1230 * @status: success or failure status of PTQM migration 1231 * 1232 * Return: Success when HTT message is sent, error on failure 1233 */ 1234 QDF_STATUS 1235 dp_h2t_ptqm_migration_msg_send(struct dp_soc *dp_soc, uint16_t vdev_id, 1236 uint8_t pdev_id, 1237 uint8_t chip_id, uint16_t peer_id, 1238 uint16_t ml_peer_id, uint16_t src_info, 1239 QDF_STATUS status); 1240 1241 /** 1242 * dp_htt_reo_migration() - Reo migration API 1243 * @soc: DP SOC handle 1244 * @peer_id: Peer id of primary peer 1245 * @ml_peer_id: Peer id of MLD peer 1246 * @vdev_id: Vdev id of primary peer 1247 * @pdev_id: Pdev id of primary peer 1248 * @chip_id: Chip id of primary peer 1249 * 1250 * Return: Success if migration completes, error on failure 1251 */ 1252 QDF_STATUS dp_htt_reo_migration(struct dp_soc *soc, uint16_t peer_id, 1253 uint16_t ml_peer_id, uint16_t vdev_id, 1254 uint8_t pdev_id, uint8_t chip_id); 1255 #endif 1256 #endif /* _DP_HTT_H_ */ 1257