1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_HTT_H_ 21 #define _DP_HTT_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_lock.h> 25 #include <qdf_nbuf.h> 26 #include <htc_api.h> 27 28 #include "cdp_txrx_cmn_struct.h" 29 #include "dp_types.h" 30 #ifdef HTT_LOGGER 31 #include "dp_htt_logger.h" 32 #else 33 struct htt_logger; 34 static inline 35 void htt_interface_logging_init(struct htt_logger **htt_logger_handle, 36 struct cdp_ctrl_objmgr_psoc *ctrl_psoc) 37 { 38 } 39 40 static inline 41 void htt_interface_logging_deinit(struct htt_logger *htt_logger_handle) 42 { 43 } 44 45 static inline 46 int htt_command_record(struct htt_logger *h, uint8_t msg_type, 47 uint8_t *msg_data) 48 { 49 return 0; 50 } 51 52 static inline 53 int htt_event_record(struct htt_logger *h, uint8_t msg_type, 54 uint8_t *msg_data) 55 { 56 return 0; 57 } 58 59 static inline 60 int htt_wbm_event_record(struct htt_logger *h, uint8_t tx_status, 61 uint8_t *msg_data) 62 { 63 return 0; 64 } 65 66 #endif 67 68 #define HTT_MGMT_CTRL_TLV_HDR_RESERVERD_LEN 16 69 #define HTT_TLV_HDR_LEN HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 70 #define HTT_SHIFT_UPPER_TIMESTAMP 32 71 #define HTT_MASK_UPPER_TIMESTAMP 0xFFFFFFFF00000000 72 73 void htt_htc_pkt_pool_free(struct htt_soc *soc); 74 75 #define HTT_TX_MUTEX_TYPE qdf_spinlock_t 76 77 #define HTT_TX_MUTEX_INIT(_mutex) \ 78 qdf_spinlock_create(_mutex) 79 80 #define HTT_TX_MUTEX_ACQUIRE(_mutex) \ 81 qdf_spin_lock_bh(_mutex) 82 83 #define HTT_TX_MUTEX_RELEASE(_mutex) \ 84 qdf_spin_unlock_bh(_mutex) 85 86 #define HTT_TX_MUTEX_DESTROY(_mutex) \ 87 qdf_spinlock_destroy(_mutex) 88 89 #define DP_HTT_MAX_SEND_QUEUE_DEPTH 64 90 91 #ifndef HTT_MAC_ADDR_LEN 92 #define HTT_MAC_ADDR_LEN 6 93 #endif 94 95 #define HTT_FRAMECTRL_TYPE_MASK 0x0C 96 #define HTT_GET_FRAME_CTRL_TYPE(_val) \ 97 (((_val) & HTT_FRAMECTRL_TYPE_MASK) >> 2) 98 #define FRAME_CTRL_TYPE_MGMT 0x0 99 #define FRAME_CTRL_TYPE_CTRL 0x1 100 #define FRAME_CTRL_TYPE_DATA 0x2 101 #define FRAME_CTRL_TYPE_RESV 0x3 102 103 #define HTT_FRAMECTRL_DATATYPE 0x08 104 #define HTT_PPDU_DESC_MAX_DEPTH 16 105 #define DP_SCAN_PEER_ID 0xFFFF 106 107 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 108 #define HTT_RX_DELBA_WIN_SIZE_S 10 109 110 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 111 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 112 113 /* 114 * Set the base misclist size to HTT copy engine source ring size 115 * to guarantee that a packet on the misclist wont be freed while it 116 * is sitting in the copy engine. 117 */ 118 #define DP_HTT_HTC_PKT_MISCLIST_SIZE 2048 119 #define HTT_T2H_MAX_MSG_SIZE 2048 120 121 #define HTT_T2H_EXT_STATS_TLV_START_OFFSET 3 122 123 /* 124 * Below offset are based on htt_ppdu_stats_common_tlv 125 * defined in htt_ppdu_stats.h 126 */ 127 #define HTT_PPDU_STATS_COMMON_TLV_TLV_HDR_OFFSET 0 128 #define HTT_PPDU_STATS_COMMON_TLV_PPDU_ID_OFFSET 1 129 #define HTT_PPDU_STATS_COMMON_TLV_RING_ID_SCH_CMD_ID_OFFSET 2 130 #define HTT_PPDU_STATS_COMMON_TLV_QTYPE_FRM_TYPE_OFFSET 3 131 #define HTT_PPDU_STATS_COMMON_TLV_CHAIN_MASK_OFFSET 4 132 #define HTT_PPDU_STATS_COMMON_TLV_FES_DUR_US_OFFSET 5 133 #define HTT_PPDU_STATS_COMMON_TLV_SCH_EVAL_START_TSTMP_L32_US_OFFSET 6 134 #define HTT_PPDU_STATS_COMMON_TLV_SCH_END_TSTMP_US_OFFSET 7 135 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_L32_US_OFFSET 8 136 #define HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_PHY_MODE_OFFSET 9 137 #define HTT_PPDU_STATS_COMMON_TLV_CCA_DELTA_TIME_US_OFFSET 10 138 #define HTT_PPDU_STATS_COMMON_TLV_RXFRM_DELTA_TIME_US_OFFSET 11 139 #define HTT_PPDU_STATS_COMMON_TLV_TXFRM_DELTA_TIME_US_OFFSET 12 140 #define HTT_PPDU_STATS_COMMON_TLV_RESV_NUM_UL_BEAM_OFFSET 13 141 #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_U32_US_OFFSET 14 142 #define HTT_PPDU_STATS_COMMON_TLV_BSSCOLOR_OBSS_PSR_OFFSET 15 143 144 /* get index for field in htt_ppdu_stats_common_tlv */ 145 #define HTT_GET_STATS_CMN_INDEX(index) \ 146 HTT_PPDU_STATS_COMMON_TLV_##index##_OFFSET 147 148 #define HTT_VDEV_STATS_TLV_SOC_DROP_CNT_OFFSET 1 149 150 #define HTT_VDEV_STATS_TLV_HDR_OFFSET 0 151 #define HTT_VDEV_STATS_TLV_VDEV_ID_OFFSET 1 152 #define HTT_VDEV_STATS_TLV_RX_BYTE_CNT_OFFSET 2 153 #define HTT_VDEV_STATS_TLV_RX_PKT_CNT_OFFSET 4 154 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_BYTE_CNT_OFFSET 6 155 #define HTT_VDEV_STATS_TLV_TX_SUCCESS_PKT_CNT_OFFSET 8 156 #define HTT_VDEV_STATS_TLV_TX_RETRY_PKT_CNT_OFFSET 10 157 #define HTT_VDEV_STATS_TLV_TX_DROP_PKT_CNT_OFFSET 12 158 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_PKT_CNT_OFFSET 14 159 #define HTT_VDEV_STATS_TLV_TX_RETRY_BYTE_CNT_OFFSET 16 160 #define HTT_VDEV_STATS_TLV_TX_DROP_BYTE_CNT_OFFSET 18 161 #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_BYTE_CNT_OFFSET 20 162 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_PKT_CNT_OFFSET 22 163 #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_BYTE_CNT_OFFSET 24 164 165 #define HTT_VDEV_STATS_GET_INDEX(index) \ 166 HTT_VDEV_STATS_TLV_##index##_OFFSET 167 168 #define HTT_VDEV_STATS_U32_SHIFT 0x20 169 #define HTT_VDEV_STATS_U32_MASK 0xFFFFFFFF00000000 170 #define HTT_VDEV_STATS_L32_MASK 0x00000000FFFFFFFF 171 172 #define HTT_VDEV_GET_STATS_U64(msg_word) \ 173 (((((uint64_t)(*(((uint32_t *)msg_word) + 1))) & HTT_VDEV_STATS_L32_MASK) << \ 174 HTT_VDEV_STATS_U32_SHIFT) | ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK)) 175 176 #define HTT_VDEV_GET_STATS_U32(msg_word) \ 177 ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK) 178 179 #define MAX_SCHED_STARVE 100000 180 #define WRAP_DROP_TSF_DELTA 10000 181 #define MAX_TSF_32 0xFFFFFFFF 182 183 #define dp_htt_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT, params) 184 #define dp_htt_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT, params) 185 #define dp_htt_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT, params) 186 #define dp_htt_info(params...) \ 187 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT, ## params) 188 #define dp_htt_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT, params) 189 190 #define dp_htt_tx_stats_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 191 #define dp_htt_tx_stats_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 192 #define dp_htt_tx_stats_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 193 #define dp_htt_tx_stats_info(params...) \ 194 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT_TX_STATS, ## params) 195 #define dp_htt_tx_stats_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT_TX_STATS, params) 196 197 #define RXMON_GLOBAL_EN_SHIFT 28 198 /** 199 * enum dp_full_mon_config - enum to enable/disable full monitor mode 200 * 201 * @DP_FULL_MON_DISABLE: Disable full monitor mode 202 * @DP_FULL_MON_ENABLE: Enable full monitor mode 203 */ 204 enum dp_full_mon_config { 205 DP_FULL_MON_DISABLE, 206 DP_FULL_MON_ENABLE, 207 }; 208 209 struct dp_htt_htc_pkt { 210 void *soc_ctxt; 211 qdf_dma_addr_t nbuf_paddr; 212 HTC_PACKET htc_pkt; 213 }; 214 215 struct dp_htt_htc_pkt_union { 216 union { 217 struct dp_htt_htc_pkt pkt; 218 struct dp_htt_htc_pkt_union *next; 219 } u; 220 }; 221 222 struct bp_handler { 223 unsigned long bp_start_tt; 224 unsigned long bp_last_tt; 225 unsigned long bp_duration; 226 unsigned long bp_counter; 227 }; 228 229 struct dp_htt_timestamp { 230 struct bp_handler *umac_path; 231 struct bp_handler *lmac_path; 232 }; 233 234 struct htt_soc { 235 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 236 struct dp_soc *dp_soc; 237 hal_soc_handle_t hal_soc; 238 struct dp_htt_timestamp pdevid_tt[MAX_PDEV_CNT]; 239 /* htt_logger handle */ 240 struct htt_logger *htt_logger_handle; 241 HTC_HANDLE htc_soc; 242 qdf_device_t osdev; 243 HTC_ENDPOINT_ID htc_endpoint; 244 struct dp_htt_htc_pkt_union *htt_htc_pkt_freelist; 245 struct dp_htt_htc_pkt_union *htt_htc_pkt_misclist; 246 struct { 247 u_int8_t major; 248 u_int8_t minor; 249 } tgt_ver; 250 struct { 251 u_int8_t major; 252 u_int8_t minor; 253 } wifi_ip_ver; 254 255 struct { 256 int htc_err_cnt; 257 int htc_pkt_free; 258 int skip_count; 259 int fail_count; 260 /* rtpm put skip count for ver req msg */ 261 int htt_ver_req_put_skip; 262 } stats; 263 264 HTT_TX_MUTEX_TYPE htt_tx_mutex; 265 }; 266 267 #ifdef QCA_MONITOR_2_0_SUPPORT 268 /** 269 * struct dp_tx_mon_downstream_tlv_config - Enable/Disable TxMon 270 * downstream TLVs 271 * tx_fes_setup: TX_FES_SETUP TLV 272 * tx_peer_entry: TX_PEER_ENTRY TLV 273 * tx_queue_extension: TX_QUEUE_EXTENSION TLV 274 * tx_last_mpdu_end: TX_LAST_MPDU_END TLV 275 * tx_last_mpdu_fetched: TX_LAST_MPDU_FETCHED TLV 276 * tx_data_sync: TX_DATA_SYNC TLV 277 * pcu_ppdu_setup_init: PCU_PPDU_SETUP_INIT TLV 278 * fw2s_mon: FW2S_MON TLV 279 * tx_loopback_setup: TX_LOOPBACK_SETUP TLV 280 * sch_critical_tlv_ref: SCH_CRITICAL_TLV_REF TLV 281 * ndp_preamble_done: NDP_PREAMBLE_DONE TLV 282 * tx_raw_frame_setup: TX_RAW_OR_NATIVE_FRAME_SETUP TLV 283 * txpcu_user_setup: TXPCU_USER_SETUP TLV 284 * rxpcu_setup: RXPCU_SETUP TLV 285 * rxpcu_setup_complete: RXPCU_SETUP_COMPLETE TLV 286 * coex_tx_req: COEX_TX_REQ TLV 287 * rxpcu_user_setup: RXPCU_USER_SETUP TLV 288 * rxpcu_user_setup_ext: RXPCU_USER_SETUP_EXT TLV 289 * wur_data: WUR_DATA TLV 290 * tqm_mpdu_global_start: TQM_MPDU_GLOBAL_START 291 * tx_fes_setup_complete: TX_FES_SETUP_COMPLETE TLV 292 * scheduler_end: SCHEDULER_END TLV 293 * sch_wait_instr_tx_path: SCH_WAIT_INSTR_TX_PATH TLV 294 * 295 */ 296 struct dp_tx_mon_downstream_tlv_config { 297 uint32_t tx_fes_setup:1, 298 tx_peer_entry:1, 299 tx_queue_extension:1, 300 tx_last_mpdu_end:1, 301 tx_last_mpdu_fetched:1, 302 tx_data_sync:1, 303 pcu_ppdu_setup_init:1, 304 fw2s_mon:1, 305 tx_loopback_setup:1, 306 sch_critical_tlv_ref:1, 307 ndp_preamble_done:1, 308 tx_raw_frame_setup:1, 309 txpcu_user_setup:1, 310 rxpcu_setup:1, 311 rxpcu_setup_complete:1, 312 coex_tx_req:1, 313 rxpcu_user_setup:1, 314 rxpcu_user_setup_ext:1, 315 wur_data:1, 316 tqm_mpdu_global_start:1, 317 tx_fes_setup_complete:1, 318 scheduler_end:1, 319 sch_wait_instr_tx_path:1; 320 }; 321 322 /** 323 * struct dp_tx_mon_upstream_tlv_config - Enable/Disable TxMon 324 * upstream TLVs 325 * rx_response_required_info: RX_RESPONSE_REQUIRED_INFO 326 * TLV 327 * response_start_status: RESPONSE_START_STATUS TLV 328 * response_end_status: RESPONSE_END_STATUS TLV 329 * tx_fes_status_start: TX_FES_STATUS_START TLV 330 * tx_fes_status_start_ppdu: TX_FES_STATUS_START_PPDU TLV 331 * tx_fes_status_user_ppdu: TX_FES_STATUS_USER_PPDU TLV 332 * tx_fes_status_ack_or_ba: TX_FES_STATUS_ACK_OR_BA TLV 333 * tx_fes_status_1k_ba: TX_FES_STATUS_1K_BA TLV 334 * tx_fes_status_start_prot: TX_FES_STATUS_START_PROTO TLV 335 * tx_fes_status_user_response: TX_FES_STATUS_USER_RESPONSE TLV 336 * rx_frame_bitmap_ack: RX_FRAME_BITMAP_ACK TLV 337 * rx_frame_1k_bitmap_ack: RX_FRAME_1K_BITMAP_ACK TLV 338 * coex_tx_status: COEX_TX_STATUS TLV 339 * received_response_info: RECEIVED_RESPONSE_INFO TLV 340 * received_response_info_p2: RECEIVED_RESPONSE_INFO_PART2 TLV 341 * ofdma_trigger_details: OFDMA_TRIGGER_DETAILS 342 * received_trigger_info: RECEIVED_TRIGGER_INFO 343 * pdg_tx_request: PDG_TX_REQUEST 344 * pdg_response: PDG_RESPONSE 345 * pdg_trig_response: PDG_TRIG_RESPONSE 346 * trigger_response_tx_done: TRIGGER_RESPONSE_TX_DONE 347 * prot_tx_end: PROT_TX_END 348 * ppdu_tx_end: PPDU_TX_END 349 * r2r_status_end: R2R_STATUS_END 350 * flush_req: FLUSH_REQ 351 * mactx_phy_desc: MACTX_PHY_DESC 352 * mactx_user_desc_cmn: MACTX_USER_DESC_COMMON 353 * mactx_user_desc_per_usr: MACTX_USER_DESC_PER_USER 354 * tqm_acked_1k_mpdu: TQM_ACKED_1K_MPDU 355 * tqm_acked_mpdu: TQM_ACKED_MPDU 356 * tqm_update_tx_mpdu_count: TQM_UPDATE_TX_MPDU_COUNT 357 * phytx_ppdu_header_info_request: PHYTX_PPDU_HEADER_INFO_REQUEST 358 * u_sig_eht_su_mu: U_SIG_EHT_SU_MU 359 * u_sig_eht_su: U_SIG_EHT_SU 360 * eht_sig_usr_su: EHT_SIG_USR_SU 361 * eht_sig_usr_mu_mimo: EHT_SIG_USR_MU_MIMO 362 * eht_sig_usr_ofdma: EHT_SIG_USR_MU_MIMO 363 * he_sig_a_su: HE_SIG_A_SU 364 * he_sig_a_mu_dl: HE_SIG_A_MU_DL 365 * he_sig_a_mu_ul: HE_SIG_A_MU_UL 366 * he_sig_b1_mu: HE_SIG_B1_MU 367 * he_sig_b2_mu: HE_SIG_B2_MU 368 * he_sig_b2_ofdma: HE_SIG_B2_OFDMA 369 * vht_sig_b_mu160: VHT_SIG_B_MU160 370 * vht_sig_b_mu80: VHT_SIG_B_MU80 371 * vht_sig_b_mu40: VHT_SIG_B_MU40 372 * vht_sig_b_mu20: VHT_SIG_B_MU20 373 * vht_sig_b_su160: VHT_SIG_B_SU160 374 * vht_sig_b_su80: VHT_SIG_B_SU80 375 * vht_sig_b_su40: VHT_SIG_B_SU40 376 * vht_sig_b_su20: VHT_SIG_B_SU20 377 * vht_sig_a: VHT_SIG_A 378 * ht_sig: HT_SIG 379 * l_sig_b: L_SIG_B 380 * l_sig_a: L_SIG_A 381 * tx_service: TX_SERVICE 382 * txpcu_buf_status: TXPCU_BUFFER_STATUS 383 * txpcu_user_buf_status: TXPCU_USER_BUFFER_STATUS 384 * txdma_stop_request: TXDMA_STOP_REQUEST 385 * expected_response: EXPECTED_RESPONSE 386 * tx_mpdu_count_transfer_end: TX_MPDU_COUNT_TRANSFER_END 387 * rx_trig_info: RX_TRIG_INFO 388 * rxpcu_tx_setup_clear: RXPCU_TX_SETUP_CLEAR 389 * rx_frame_bitmap_req: RX_FRAME_BITMAP_REQ 390 * rx_phy_sleep: RX_PHY_SLEEP 391 * txpcu_preamble_done: TXPCU_PREAMBLE_DONE 392 * txpcu_phytx_debug32: TXPCU_PHYTX_DEBUG32 393 * txpcu_phytx_other_transmit_info32: TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 394 * rx_ppdu_noack_report: RX_PPDU_NO_ACK_REPORT 395 * rx_ppdu_ack_report: RX_PPDU_ACK_REPORT 396 * coex_rx_status: COEX_RX_STATUS 397 * rx_start_param: RX_START_PARAM 398 * tx_cbf_info: TX_CBF_INFO 399 * rxpcu_early_rx_indication: RXPCU_EARLY_RX_INDICATION 400 * received_response_user_7_0: RECEIVED_RESPONSE_USER_7_0 401 * received_response_user_15_8: RECEIVED_RESPONSE_USER_15_8 402 * received_response_user_23_16: RECEIVED_RESPONSE_USER_23_16 403 * received_response_user_31_24: RECEIVED_RESPONSE_USER_31_24 404 * received_response_user_36_32: RECEIVED_RESPONSE_USER_36_32 405 * rx_pm_info: RX_PM_INFO 406 * rx_preamble: RX_PREAMBLE 407 * others: OTHERS 408 * mactx_pre_phy_desc: MACTX_PRE_PHY_DESC 409 * 410 */ 411 struct dp_tx_mon_upstream_tlv_config { 412 uint32_t rx_response_required_info:1, 413 response_start_status:1, 414 response_end_status:1, 415 tx_fes_status_start:1, 416 tx_fes_status_end:1, 417 tx_fes_status_start_ppdu:1, 418 tx_fes_status_user_ppdu:1, 419 tx_fes_status_ack_or_ba:1, 420 tx_fes_status_1k_ba:1, 421 tx_fes_status_start_prot:1, 422 tx_fes_status_prot:1, 423 tx_fes_status_user_response:1, 424 rx_frame_bitmap_ack:1, 425 rx_frame_1k_bitmap_ack:1, 426 coex_tx_status:1, 427 received_response_info:1, 428 received_response_info_p2:1, 429 ofdma_trigger_details:1, 430 received_trigger_info:1, 431 pdg_tx_request:1, 432 pdg_response:1, 433 pdg_trig_response:1, 434 trigger_response_tx_done:1, 435 prot_tx_end:1, 436 ppdu_tx_end:1, 437 r2r_status_end:1, 438 flush_req:1, 439 mactx_phy_desc:1, 440 mactx_user_desc_cmn:1, 441 mactx_user_desc_per_usr:1; 442 uint32_t tqm_acked_1k_mpdu:1, 443 tqm_acked_mpdu:1, 444 tqm_update_tx_mpdu_count:1, 445 phytx_ppdu_header_info_request:1, 446 u_sig_eht_su_mu:1, 447 u_sig_eht_su:1, 448 u_sig_eht_tb:1, 449 eht_sig_usr_su:1, 450 eht_sig_usr_mu_mimo:1, 451 eht_sig_usr_ofdma:1, 452 he_sig_a_su:1, 453 he_sig_a_mu_dl:1, 454 he_sig_a_mu_ul:1, 455 he_sig_b1_mu:1, 456 he_sig_b2_mu:1, 457 he_sig_b2_ofdma:1, 458 vht_sig_b_mu160:1, 459 vht_sig_b_mu80:1, 460 vht_sig_b_mu40:1, 461 vht_sig_b_mu20:1, 462 vht_sig_b_su160:1, 463 vht_sig_b_su80:1, 464 vht_sig_b_su40:1, 465 vht_sig_b_su20:1, 466 vht_sig_a:1, 467 ht_sig:1, 468 l_sig_b:1, 469 l_sig_a:1, 470 tx_service:1; 471 uint32_t txpcu_buf_status:1, 472 txpcu_user_buf_status:1, 473 txdma_stop_request:1, 474 expected_response:1, 475 tx_mpdu_count_transfer_end:1, 476 rx_trig_info:1, 477 rxpcu_tx_setup_clear:1, 478 rx_frame_bitmap_req:1, 479 rx_phy_sleep:1, 480 txpcu_preamble_done:1, 481 txpcu_phytx_debug32:1, 482 txpcu_phytx_other_transmit_info32:1, 483 rx_ppdu_noack_report:1, 484 rx_ppdu_ack_report:1, 485 coex_rx_status:1, 486 rx_start_param:1, 487 tx_cbf_info:1, 488 rxpcu_early_rx_indication:1, 489 received_response_user_7_0:1, 490 received_response_user_15_8:1, 491 received_response_user_23_16:1, 492 received_response_user_31_24:1, 493 received_response_user_36_32:1, 494 rx_pm_info:1, 495 rx_preamble:1, 496 others:1, 497 mactx_pre_phy_desc:1; 498 }; 499 500 /** 501 * struct dp_tx_mon_wordmask_config - Tx monitor word mask 502 * tx_fes_setup: TX_FES_SETUP TLV word mask 503 * tx_peer_entry: TX_PEER_ENTRY TLV word mask 504 * tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask 505 * tx_msdu_start: TX_MSDU_START TLV word mask 506 * tx_mpdu_start: TX_MPDU_START TLV word mask 507 * pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask 508 * rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask 509 */ 510 struct dp_tx_mon_wordmask_config { 511 uint16_t tx_fes_setup; 512 uint16_t tx_peer_entry; 513 uint16_t tx_queue_ext; 514 uint16_t tx_msdu_start; 515 uint16_t tx_mpdu_start; 516 uint32_t pcu_ppdu_setup_init; 517 uint16_t rxpcu_user_setup; 518 }; 519 520 /** 521 * struct htt_tx_ring_tlv_filter - Tx ring TLV filter 522 * enable/disable. 523 * @dtlvs: enable/disable downstream TLVs 524 * @utlvs: enable/disable upstream TLVs 525 * @wmask: enable/disbale word mask subscription 526 * @mgmt_filter: enable/disable mgmt packets 527 * @data_filter: enable/disable data packets 528 * @ctrl_filter: enable/disable ctrl packets 529 * @mgmt_dma_length: configure length for mgmt packet 530 * @ctrl_dma_length: configure length for ctrl packet 531 * @data_dma_length: configure length for data packet 532 * @mgmt_mpdu_end: enable mpdu end tlv for mgmt 533 * @mgmt_msdu_end: enable msdu end tlv for mgmt 534 * @mgmt_msdu_start: enable msdu start tlv for mgmt 535 * @mgmt_mpdu_start: enable mpdu start tlv for mgmt 536 * @ctrl_mpdu_end: enable mpdu end tlv for ctrl 537 * @ctrl_msdu_end: enable msdu end tlv for ctrl 538 * @ctrl_msdu_start: enable msdu start tlv for ctrl 539 * @ctrl_mpdu_start: enable mpdu start tlv for ctrl 540 * @data_mpdu_end: enable mpdu end tlv for data 541 * @data_msdu_end: enable msdu end tlv for data 542 * @data_msdu_start: enable msdu start tlv for data 543 * @data_mpdu_start: enable mpdu start tlv for data 544 * @mgmt_mpdu_log: enable mgmt mpdu level logging 545 * @ctrl_mpdu_log: enable ctrl mpdu level logging 546 * @data_mpdu_log: enable data mpdu level logging 547 * @enable: enable tx monitor 548 * 549 * NOTE: Do not change the layout of this structure 550 */ 551 struct htt_tx_ring_tlv_filter { 552 struct dp_tx_mon_downstream_tlv_config dtlvs; 553 struct dp_tx_mon_upstream_tlv_config utlvs; 554 struct dp_tx_mon_wordmask_config wmask; 555 uint16_t mgmt_filter; 556 uint16_t data_filter; 557 uint16_t ctrl_filter; 558 uint16_t mgmt_dma_length:3, 559 ctrl_dma_length:3, 560 data_dma_length:3; 561 uint16_t mgmt_mpdu_end:1, 562 mgmt_msdu_end:1, 563 mgmt_msdu_start:1, 564 mgmt_mpdu_start:1, 565 ctrl_mpdu_end:1, 566 ctrl_msdu_end:1, 567 ctrl_msdu_start:1, 568 ctrl_mpdu_start:1, 569 data_mpdu_end:1, 570 data_msdu_end:1, 571 data_msdu_start:1, 572 data_mpdu_start:1; 573 uint8_t mgmt_mpdu_log:1, 574 ctrl_mpdu_log:1, 575 data_mpdu_log:1; 576 uint8_t enable:1; 577 }; 578 #endif /* QCA_MONITOR_2_0_SUPPORT */ 579 580 /** 581 * struct htt_rx_ring_tlv_filter - Rx ring TLV filter 582 * enable/disable. 583 * @mpdu_start: enable/disable MPDU start TLV 584 * @msdu_start: enable/disable MSDU start TLV 585 * @packet: enable/disable PACKET TLV 586 * @msdu_end: enable/disable MSDU end TLV 587 * @mpdu_end: enable/disable MPDU end TLV 588 * @packet_header: enable/disable PACKET header TLV 589 * @attention: enable/disable ATTENTION TLV 590 * @ppdu_start: enable/disable PPDU start TLV 591 * @ppdu_end: enable/disable PPDU end TLV 592 * @ppdu_end_user_stats: enable/disable PPDU user stats TLV 593 * @ppdu_end_user_stats_ext: enable/disable PPDU user stats ext TLV 594 * @ppdu_end_status_done: enable/disable PPDU end status done TLV 595 * @enable_fp: enable/disable FP packet 596 * @enable_md: enable/disable MD packet 597 * @enable_mo: enable/disable MO packet 598 * @enable_mgmt: enable/disable MGMT packet 599 * @enable_ctrl: enable/disable CTRL packet 600 * @enable_data: enable/disable DATA packet 601 * @offset_valid: Flag to indicate if below offsets are valid 602 * @rx_packet_offset: Offset of packet payload 603 * @rx_header_offset: Offset of rx_header tlv 604 * @rx_mpdu_end_offset: Offset of rx_mpdu_end tlv 605 * @rx_mpdu_start_offset: Offset of rx_mpdu_start tlv 606 * @rx_msdu_end_offset: Offset of rx_msdu_end tlv 607 * @rx_msdu_start_offset: Offset of rx_msdu_start tlv 608 * @rx_attn_offset: Offset of rx_attention tlv 609 * @fp_phy_err: Flag to indicate FP PHY status tlv 610 * @fp_phy_err_buf_src: source ring selection for the FP PHY ERR status tlv 611 * @fp_phy_err_buf_dest: dest ring selection for the FP PHY ERR status tlv 612 * @phy_err_mask: select the phy errors defined in phyrx_abort_request_reason 613 * enums 0 to 31. 614 * @phy_err_mask_cont: select the fp phy errors defined in 615 * phyrx_abort_request_reason enums 32 to 63 616 * @rx_mpdu_start_wmask: word mask for mpdu start tlv 617 * @rx_mpdu_end_wmask: word mask for mpdu end tlv 618 * @rx_msdu_end_tlv: word mask for msdu end tlv 619 * @rx_pkt_tlv_offset: rx pkt tlv offset 620 * @mgmt_dma_length: configure length for mgmt packet 621 * @ctrl_dma_length: configure length for ctrl packet 622 * @data_dma_length: configure length for data packet 623 * @rx_hdr_length: configure length for rx header tlv 624 * @mgmt_mpdu_log: enable mgmt mpdu level logging 625 * @ctrl_mpdu_log: enable ctrl mpdu level logging 626 * @data_mpdu_log: enable data mpdu level logging 627 * @enable: enable rx monitor 628 * @enable_fpmo: enable/disable FPMO packet 629 * @fpmo_data_filter: FPMO mode data filter 630 * @fpmo_mgmt_filter: FPMO mode mgmt filter 631 * @fpmo_ctrl_filter: FPMO mode ctrl filter 632 * 633 * NOTE: Do not change the layout of this structure 634 */ 635 struct htt_rx_ring_tlv_filter { 636 u_int32_t mpdu_start:1, 637 msdu_start:1, 638 packet:1, 639 msdu_end:1, 640 mpdu_end:1, 641 packet_header:1, 642 attention:1, 643 ppdu_start:1, 644 ppdu_end:1, 645 ppdu_end_user_stats:1, 646 ppdu_end_user_stats_ext:1, 647 ppdu_end_status_done:1, 648 ppdu_start_user_info:1, 649 header_per_msdu:1, 650 enable_fp:1, 651 enable_md:1, 652 enable_mo:1; 653 u_int32_t fp_mgmt_filter:16, 654 mo_mgmt_filter:16; 655 u_int32_t fp_ctrl_filter:16, 656 mo_ctrl_filter:16; 657 u_int32_t fp_data_filter:16, 658 mo_data_filter:16; 659 u_int16_t md_data_filter; 660 u_int16_t md_mgmt_filter; 661 u_int16_t md_ctrl_filter; 662 bool offset_valid; 663 uint16_t rx_packet_offset; 664 uint16_t rx_header_offset; 665 uint16_t rx_mpdu_end_offset; 666 uint16_t rx_mpdu_start_offset; 667 uint16_t rx_msdu_end_offset; 668 uint16_t rx_msdu_start_offset; 669 uint16_t rx_attn_offset; 670 #ifdef QCA_UNDECODED_METADATA_SUPPORT 671 u_int32_t fp_phy_err:1, 672 fp_phy_err_buf_src:2, 673 fp_phy_err_buf_dest:2, 674 phy_err_filter_valid:1; 675 u_int32_t phy_err_mask; 676 u_int32_t phy_err_mask_cont; 677 #endif 678 #ifdef QCA_MONITOR_2_0_SUPPORT 679 uint16_t rx_mpdu_start_wmask; 680 uint16_t rx_mpdu_end_wmask; 681 uint16_t rx_msdu_end_wmask; 682 uint16_t rx_pkt_tlv_offset; 683 uint16_t mgmt_dma_length:3, 684 ctrl_dma_length:3, 685 data_dma_length:3, 686 rx_hdr_length:3, 687 mgmt_mpdu_log:1, 688 ctrl_mpdu_log:1, 689 data_mpdu_log:1, 690 enable:1; 691 u_int16_t enable_fpmo:1; 692 u_int16_t fpmo_data_filter; 693 u_int16_t fpmo_mgmt_filter; 694 u_int16_t fpmo_ctrl_filter; 695 #endif 696 }; 697 698 /** 699 * struct dp_htt_rx_flow_fst_setup - Rx FST setup message 700 * @pdev_id: DP Pdev identifier 701 * @max_entries: Size of Rx FST in number of entries 702 * @max_search: Number of collisions allowed 703 * @base_addr_lo: lower 32-bit physical address 704 * @base_addr_hi: upper 32-bit physical address 705 * @ip_da_sa_prefix: IPv4 prefix to map to IPv6 address scheme 706 * @hash_key_len: Rx FST hash key size 707 * @hash_key: Rx FST Toeplitz hash key 708 */ 709 struct dp_htt_rx_flow_fst_setup { 710 uint8_t pdev_id; 711 uint32_t max_entries; 712 uint32_t max_search; 713 uint32_t base_addr_lo; 714 uint32_t base_addr_hi; 715 uint32_t ip_da_sa_prefix; 716 uint32_t hash_key_len; 717 uint8_t *hash_key; 718 }; 719 720 /** 721 * enum dp_htt_flow_fst_operation - FST related operations allowed 722 * @DP_HTT_FST_CACHE_OP_NONE: Cache no-op 723 * @DP_HTT_FST_CACHE_INVALIDATE_ENTRY: Invalidate single cache entry 724 * @DP_HTT_FST_CACHE_INVALIDATE_FULL: Invalidate entire cache 725 * @DP_HTT_FST_ENABLE: Bypass FST is enabled 726 * @DP_HTT_FST_DISABLE: Disable bypass FST 727 */ 728 enum dp_htt_flow_fst_operation { 729 DP_HTT_FST_CACHE_OP_NONE, 730 DP_HTT_FST_CACHE_INVALIDATE_ENTRY, 731 DP_HTT_FST_CACHE_INVALIDATE_FULL, 732 DP_HTT_FST_ENABLE, 733 DP_HTT_FST_DISABLE 734 }; 735 736 /** 737 * struct dp_htt_rx_flow_fst_setup - Rx FST setup message 738 * @pdev_id: DP Pdev identifier 739 * @op_code: FST operation to be performed by FW/HW 740 * @rx_flow: Rx Flow information on which operation is to be performed 741 */ 742 struct dp_htt_rx_flow_fst_operation { 743 uint8_t pdev_id; 744 enum dp_htt_flow_fst_operation op_code; 745 struct cdp_rx_flow_info *rx_flow; 746 }; 747 748 /** 749 * struct dp_htt_rx_fisa_config - Rx fisa config 750 * @pdev_id: DP Pdev identifier 751 * @fisa_timeout: fisa aggregation timeout 752 */ 753 struct dp_htt_rx_fisa_cfg { 754 uint8_t pdev_id; 755 uint32_t fisa_timeout; 756 }; 757 758 /* 759 * htt_htc_pkt_alloc() - Allocate HTC packet buffer 760 * @htt_soc: HTT SOC handle 761 * 762 * Return: Pointer to htc packet buffer 763 */ 764 struct dp_htt_htc_pkt *htt_htc_pkt_alloc(struct htt_soc *soc); 765 766 /* 767 * htt_htc_pkt_free() - Free HTC packet buffer 768 * @htt_soc: HTT SOC handle 769 */ 770 void 771 htt_htc_pkt_free(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 772 773 #define HTT_HTC_PKT_STATUS_SUCCESS \ 774 ((pkt->htc_pkt.Status != QDF_STATUS_E_CANCELED) && \ 775 (pkt->htc_pkt.Status != QDF_STATUS_E_RESOURCES)) 776 777 #ifdef ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST 778 779 static void 780 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt) 781 { 782 } 783 784 #else /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 785 786 /* 787 * htt_htc_misc_pkt_list_add() - Add pkt to misc list 788 * @htt_soc: HTT SOC handle 789 * @dp_htt_htc_pkt: pkt to be added to list 790 */ 791 void 792 htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt); 793 794 #endif /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */ 795 796 /** 797 * DP_HTT_SEND_HTC_PKT() - Send htt packet from host 798 * @soc : HTT SOC handle 799 * @pkt: pkt to be send 800 * @cmd : command to be recorded in dp htt logger 801 * @buf : Pointer to buffer needs to be recored for above cmd 802 * 803 * Return: None 804 */ 805 static inline QDF_STATUS DP_HTT_SEND_HTC_PKT(struct htt_soc *soc, 806 struct dp_htt_htc_pkt *pkt, 807 uint8_t cmd, uint8_t *buf) 808 { 809 QDF_STATUS status; 810 811 htt_command_record(soc->htt_logger_handle, cmd, buf); 812 813 status = htc_send_pkt(soc->htc_soc, &pkt->htc_pkt); 814 if (status == QDF_STATUS_SUCCESS && HTT_HTC_PKT_STATUS_SUCCESS) 815 htt_htc_misc_pkt_list_add(soc, pkt); 816 else 817 soc->stats.fail_count++; 818 return status; 819 } 820 821 QDF_STATUS dp_htt_rx_fisa_config(struct dp_pdev *pdev, 822 struct dp_htt_rx_fisa_cfg *fisa_config); 823 824 #ifdef WLAN_SUPPORT_PPEDS 825 826 /** 827 * dp_htt_rxdma_rxole_ppe_config: Rx DMA and RxOLE PPE config 828 * @override: RxDMA override to override the reo_destinatoin_indication 829 * @reo_destination_indication: REO destination indication value 830 * @multi_buffer_msdu_override_en: Override the indicatio for SG 831 * @intra_bss_override: Rx OLE IntraBSS override 832 * @decap_raw_override: Rx Decap Raw override 833 * @decap_nwifi_override: Rx Native override 834 * @ip_frag_override: IP fragments override 835 * @reserved: Reserved 836 */ 837 struct dp_htt_rxdma_rxole_ppe_config { 838 uint32_t override:1, 839 reo_destination_indication:5, 840 multi_buffer_msdu_override_en:1, 841 intra_bss_override:1, 842 decap_raw_override:1, 843 decap_nwifi_override:1, 844 ip_frag_override:1, 845 reserved:21; 846 }; 847 848 QDF_STATUS 849 dp_htt_rxdma_rxole_ppe_cfg_set(struct dp_soc *soc, 850 struct dp_htt_rxdma_rxole_ppe_config *cfg); 851 #endif /* WLAN_SUPPORT_PPEDS */ 852 853 /* 854 * htt_soc_initialize() - SOC level HTT initialization 855 * @htt_soc: Opaque htt SOC handle 856 * @ctrl_psoc: Opaque ctrl SOC handle 857 * @htc_soc: SOC level HTC handle 858 * @hal_soc: Opaque HAL SOC handle 859 * @osdev: QDF device 860 * 861 * Return: HTT handle on success; NULL on failure 862 */ 863 void * 864 htt_soc_initialize(struct htt_soc *htt_soc, 865 struct cdp_ctrl_objmgr_psoc *ctrl_psoc, 866 HTC_HANDLE htc_soc, 867 hal_soc_handle_t hal_soc_hdl, qdf_device_t osdev); 868 869 /* 870 * htt_soc_attach() - attach DP and HTT SOC 871 * @soc: DP SOC handle 872 * @htc_hdl: HTC handle 873 * 874 * Return: htt_soc handle on Success, NULL on Failure 875 */ 876 struct htt_soc *htt_soc_attach(struct dp_soc *soc, HTC_HANDLE htc_hdl); 877 878 /* 879 * htt_set_htc_handle_() - set HTC handle 880 * @htt_hdl: HTT handle/SOC 881 * @htc_soc: HTC handle 882 * 883 * Return: None 884 */ 885 void htt_set_htc_handle(struct htt_soc *htt_hdl, HTC_HANDLE htc_soc); 886 887 /* 888 * htt_get_htc_handle_() - set HTC handle 889 * @htt_hdl: HTT handle/SOC 890 * 891 * Return: HTC_HANDLE 892 */ 893 HTC_HANDLE htt_get_htc_handle(struct htt_soc *htt_hdl); 894 895 /* 896 * htt_soc_htc_dealloc() - HTC memory de-alloc 897 * @htt_soc: SOC level HTT handle 898 * 899 * Return: None 900 */ 901 void htt_soc_htc_dealloc(struct htt_soc *htt_handle); 902 903 /* 904 * htt_soc_htc_prealloc() - HTC memory prealloc 905 * @htt_soc: SOC level HTT handle 906 * 907 * Return: QDF_STATUS_SUCCESS on success or 908 * QDF_STATUS_E_NO_MEM on allocation failure 909 */ 910 QDF_STATUS htt_soc_htc_prealloc(struct htt_soc *htt_soc); 911 912 void htt_soc_detach(struct htt_soc *soc); 913 914 int htt_srng_setup(struct htt_soc *htt_soc, int pdev_id, 915 hal_ring_handle_t hal_ring_hdl, 916 int hal_ring_type); 917 918 int htt_soc_attach_target(struct htt_soc *htt_soc); 919 920 /* 921 * htt_h2t_rx_ring_cfg() - Send SRNG packet and TLV filter 922 * config message to target 923 * @htt_soc: HTT SOC handle 924 * @pdev_id: PDEV Id 925 * @hal_srng: Opaque HAL SRNG pointer 926 * @hal_ring_type: SRNG ring type 927 * @ring_buf_size: SRNG buffer size 928 * @htt_tlv_filter: Rx SRNG TLV and filter setting 929 * 930 * Return: 0 on success; error code on failure 931 */ 932 int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id, 933 hal_ring_handle_t hal_ring_hdl, 934 int hal_ring_type, int ring_buf_size, 935 struct htt_rx_ring_tlv_filter *htt_tlv_filter); 936 937 /* 938 * htt_t2h_stats_handler() - target to host stats work handler 939 * @context: context (dp soc context) 940 * 941 * Return: void 942 */ 943 void htt_t2h_stats_handler(void *context); 944 945 /** 946 * struct htt_stats_context - htt stats information 947 * @soc: Size of each descriptor in the pool 948 * @msg: T2H Ext stats message queue 949 * @msg_len: T2H Ext stats message length 950 */ 951 struct htt_stats_context { 952 struct dp_soc *soc; 953 qdf_nbuf_queue_t msg; 954 uint32_t msg_len; 955 }; 956 957 #ifdef DP_UMAC_HW_RESET_SUPPORT 958 /** 959 * struct dp_htt_umac_reset_setup_cmd_params - Params for UMAC reset setup cmd 960 * @msi_data: MSI data to be used for raising the UMAC reset interrupt 961 * @shmem_addr_low: Lower 32-bits of shared memory 962 * @shmem_addr_high: Higher 32-bits of shared memory 963 */ 964 struct dp_htt_umac_reset_setup_cmd_params { 965 uint32_t msi_data; 966 uint32_t shmem_addr_low; 967 uint32_t shmem_addr_high; 968 }; 969 970 /** 971 * dp_htt_umac_reset_send_setup_cmd(): Send the HTT UMAC reset setup command 972 * @soc: dp soc object 973 * @setup_params: parameters required by this command 974 * 975 * Return: Success when HTT message is sent, error on failure 976 */ 977 QDF_STATUS dp_htt_umac_reset_send_setup_cmd( 978 struct dp_soc *soc, 979 const struct dp_htt_umac_reset_setup_cmd_params *setup_params); 980 #endif 981 982 /** 983 * dp_htt_rx_flow_fst_setup(): Send HTT Rx FST setup message to FW 984 * @pdev: DP pdev handle 985 * @fse_setup_info: FST setup parameters 986 * 987 * Return: Success when HTT message is sent, error on failure 988 */ 989 QDF_STATUS 990 dp_htt_rx_flow_fst_setup(struct dp_pdev *pdev, 991 struct dp_htt_rx_flow_fst_setup *setup_info); 992 993 /** 994 * dp_htt_rx_flow_fse_operation(): Send HTT Flow Search Entry msg to 995 * add/del a flow in HW 996 * @pdev: DP pdev handle 997 * @fse_op_info: Flow entry parameters 998 * 999 * Return: Success when HTT message is sent, error on failure 1000 */ 1001 QDF_STATUS 1002 dp_htt_rx_flow_fse_operation(struct dp_pdev *pdev, 1003 struct dp_htt_rx_flow_fst_operation *op_info); 1004 1005 /** 1006 * htt_h2t_full_mon_cfg() - Send full monitor configuarion msg to FW 1007 * 1008 * @htt_soc: HTT Soc handle 1009 * @pdev_id: Radio id 1010 * @dp_full_mon_config: enabled/disable configuration 1011 * 1012 * Return: Success when HTT message is sent, error on failure 1013 */ 1014 int htt_h2t_full_mon_cfg(struct htt_soc *htt_soc, 1015 uint8_t pdev_id, 1016 enum dp_full_mon_config); 1017 1018 /** 1019 * dp_h2t_hw_vdev_stats_config_send: Send HTT command to FW for config 1020 of HW vdev stats 1021 * @dpsoc: Datapath soc handle 1022 * @pdev_id: INVALID_PDEV_ID for all pdevs or 0,1,2 for individual pdev 1023 * @enable: flag to specify enable/disable of stats 1024 * @reset: flag to specify if command is for reset of stats 1025 * @reset_bitmask: bitmask of vdev_id(s) for reset of HW stats 1026 * 1027 * Return: QDF_STATUS 1028 */ 1029 QDF_STATUS dp_h2t_hw_vdev_stats_config_send(struct dp_soc *dpsoc, 1030 uint8_t pdev_id, bool enable, 1031 bool reset, uint64_t reset_bitmask); 1032 1033 static inline enum htt_srng_ring_id 1034 dp_htt_get_mon_htt_ring_id(struct dp_soc *soc, 1035 enum hal_ring_type hal_ring_type) 1036 { 1037 enum htt_srng_ring_id htt_srng_id = 0; 1038 1039 if (wlan_cfg_get_txmon_hw_support(soc->wlan_cfg_ctx)) { 1040 switch (hal_ring_type) { 1041 case RXDMA_MONITOR_BUF: 1042 htt_srng_id = HTT_RX_MON_HOST2MON_BUF_RING; 1043 break; 1044 case RXDMA_MONITOR_DST: 1045 htt_srng_id = HTT_RX_MON_MON2HOST_DEST_RING; 1046 break; 1047 default: 1048 dp_err("Invalid ring type %d ", hal_ring_type); 1049 break; 1050 } 1051 } else { 1052 switch (hal_ring_type) { 1053 case RXDMA_MONITOR_BUF: 1054 htt_srng_id = HTT_RXDMA_MONITOR_BUF_RING; 1055 break; 1056 case RXDMA_MONITOR_DST: 1057 htt_srng_id = HTT_RXDMA_MONITOR_DEST_RING; 1058 break; 1059 default: 1060 dp_err("Invalid ring type %d ", hal_ring_type); 1061 break; 1062 } 1063 } 1064 1065 return htt_srng_id; 1066 } 1067 #endif /* _DP_HTT_H_ */ 1068