1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef __DP_BE_H 20 #define __DP_BE_H 21 22 #include <dp_types.h> 23 #include <hal_be_tx.h> 24 #ifdef WLAN_MLO_MULTI_CHIP 25 #include "mlo/dp_mlo.h" 26 #else 27 #include <dp_peer.h> 28 #endif 29 #ifdef WIFI_MONITOR_SUPPORT 30 #include <dp_mon.h> 31 #endif 32 33 enum CMEM_MEM_CLIENTS { 34 COOKIE_CONVERSION, 35 FISA_FST, 36 }; 37 38 /* maximum number of entries in one page of secondary page table */ 39 #define DP_CC_SPT_PAGE_MAX_ENTRIES 512 40 41 /* maximum number of entries in one page of secondary page table */ 42 #define DP_CC_SPT_PAGE_MAX_ENTRIES_MASK (DP_CC_SPT_PAGE_MAX_ENTRIES - 1) 43 44 /* maximum number of entries in primary page table */ 45 #define DP_CC_PPT_MAX_ENTRIES 1024 46 47 /* cookie conversion required CMEM offset from CMEM pool */ 48 #define DP_CC_MEM_OFFSET_IN_CMEM 0 49 50 /* cookie conversion primary page table size 4K */ 51 #define DP_CC_PPT_MEM_SIZE 4096 52 53 /* FST required CMEM offset from CMEM pool */ 54 #define DP_FST_MEM_OFFSET_IN_CMEM \ 55 (DP_CC_MEM_OFFSET_IN_CMEM + DP_CC_PPT_MEM_SIZE) 56 57 /* CMEM size for FISA FST 16K */ 58 #define DP_CMEM_FST_SIZE 16384 59 60 /* lower 9 bits in Desc ID for offset in page of SPT */ 61 #define DP_CC_DESC_ID_SPT_VA_OS_SHIFT 0 62 63 #define DP_CC_DESC_ID_SPT_VA_OS_MASK 0x1FF 64 65 #define DP_CC_DESC_ID_SPT_VA_OS_LSB 0 66 67 #define DP_CC_DESC_ID_SPT_VA_OS_MSB 8 68 69 /* higher 11 bits in Desc ID for offset in CMEM of PPT */ 70 #define DP_CC_DESC_ID_PPT_PAGE_OS_LSB 9 71 72 #define DP_CC_DESC_ID_PPT_PAGE_OS_MSB 19 73 74 #define DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT 9 75 76 #define DP_CC_DESC_ID_PPT_PAGE_OS_MASK 0xFFE00 77 78 /* 79 * page 4K unaligned case, single SPT page physical address 80 * need 8 bytes in PPT 81 */ 82 #define DP_CC_PPT_ENTRY_SIZE_4K_UNALIGNED 8 83 /* 84 * page 4K aligned case, single SPT page physical address 85 * need 4 bytes in PPT 86 */ 87 #define DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED 4 88 89 /* 4K aligned case, number of bits HW append for one PPT entry value */ 90 #define DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED 12 91 92 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 93 /* WBM2SW ring id for rx release */ 94 #define WBM2SW_REL_ERR_RING_NUM 3 95 #else 96 /* WBM2SW ring id for rx release */ 97 #define WBM2SW_REL_ERR_RING_NUM 5 98 #endif 99 100 /* tx descriptor are programmed at start of CMEM region*/ 101 #define DP_TX_DESC_CMEM_OFFSET 0 102 103 /* size of CMEM needed for a tx desc pool*/ 104 #define DP_TX_DESC_POOL_CMEM_SIZE \ 105 ((WLAN_CFG_NUM_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \ 106 DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED) 107 108 /* Offset of rx descripotor pool */ 109 #define DP_RX_DESC_CMEM_OFFSET \ 110 DP_TX_DESC_CMEM_OFFSET + (MAX_TXDESC_POOLS * DP_TX_DESC_POOL_CMEM_SIZE) 111 112 /* size of CMEM needed for a rx desc pool */ 113 #define DP_RX_DESC_POOL_CMEM_SIZE \ 114 ((WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \ 115 DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED) 116 117 /* get ppt_id from CMEM_OFFSET */ 118 #define DP_CMEM_OFFSET_TO_PPT_ID(offset) \ 119 ((offset) / DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED) 120 121 /* The MAX PPE PRI2TID */ 122 #ifdef WLAN_SUPPORT_PPEDS 123 #define DP_TX_INT_PRI2TID_MAX 15 124 #endif 125 126 /** 127 * struct dp_spt_page_desc - secondary page table page descriptors 128 * @next: pointer to next linked SPT page Desc 129 * @page_v_addr: page virtual address 130 * @page_p_addr: page physical address 131 * @ppt_index: entry index in primary page table where this page physical 132 address stored 133 * @avail_entry_index: index for available entry that store TX/RX Desc VA 134 */ 135 struct dp_spt_page_desc { 136 uint8_t *page_v_addr; 137 qdf_dma_addr_t page_p_addr; 138 uint32_t ppt_index; 139 }; 140 141 /** 142 * struct dp_hw_cookie_conversion_t - main context for HW cookie conversion 143 * @cmem_offset: CMEM offset from base address for primary page table setup 144 * @total_page_num: total DDR page allocated 145 * @page_desc_freelist: available page Desc list 146 * @page_desc_base: page Desc buffer base address. 147 * @page_pool: DDR pages pool 148 * @cc_lock: locks for page acquiring/free 149 */ 150 struct dp_hw_cookie_conversion_t { 151 uint32_t cmem_offset; 152 uint32_t total_page_num; 153 struct dp_spt_page_desc *page_desc_base; 154 struct qdf_mem_multi_page_t page_pool; 155 qdf_spinlock_t cc_lock; 156 }; 157 158 /** 159 * struct dp_spt_page_desc_list - containor of SPT page desc list info 160 * @spt_page_list_head: head of SPT page descriptor list 161 * @spt_page_list_tail: tail of SPT page descriptor list 162 * @num_spt_pages: number of SPT page descriptor allocated 163 */ 164 struct dp_spt_page_desc_list { 165 struct dp_spt_page_desc *spt_page_list_head; 166 struct dp_spt_page_desc *spt_page_list_tail; 167 uint16_t num_spt_pages; 168 }; 169 170 /* HW reading 8 bytes for VA */ 171 #define DP_CC_HW_READ_BYTES 8 172 #define DP_CC_SPT_PAGE_UPDATE_VA(_page_base_va, _index, _desc_va) \ 173 { *((uintptr_t *)((_page_base_va) + (_index) * DP_CC_HW_READ_BYTES)) \ 174 = (uintptr_t)(_desc_va); } 175 176 /** 177 * struct dp_tx_bank_profile - DP wrapper for TCL banks 178 * @is_configured: flag indicating if this bank is configured 179 * @ref_count: ref count indicating number of users of the bank 180 * @bank_config: HAL TX bank configuration 181 */ 182 struct dp_tx_bank_profile { 183 uint8_t is_configured; 184 qdf_atomic_t ref_count; 185 union hal_tx_bank_config bank_config; 186 }; 187 188 #ifdef WLAN_SUPPORT_PPEDS 189 /** 190 * struct dp_ppe_vp_tbl_entry - PPE Virtual table entry 191 * @is_configured: Boolean that the entry is configured. 192 */ 193 struct dp_ppe_vp_tbl_entry { 194 bool is_configured; 195 }; 196 197 /** 198 * struct dp_ppe_vp_profile - PPE direct switch profiler per vdev 199 * @vp_num: Virtual port number 200 * @ppe_vp_num_idx: Index to the PPE VP table entry 201 * @search_idx_reg_num: Address search Index register number 202 * @drop_prec_enable: Drop precedance enable 203 * @to_fw: To FW exception enable/disable. 204 * @use_ppe_int_pri: Use PPE INT_PRI to TID mapping table 205 */ 206 struct dp_ppe_vp_profile { 207 uint8_t vp_num; 208 uint8_t ppe_vp_num_idx; 209 uint8_t search_idx_reg_num; 210 uint8_t drop_prec_enable; 211 uint8_t to_fw; 212 uint8_t use_ppe_int_pri; 213 }; 214 #endif 215 216 /** 217 * struct dp_soc_be - Extended DP soc for BE targets 218 * @soc: dp soc structure 219 * @num_bank_profiles: num TX bank profiles 220 * @bank_profiles: bank profiles for various TX banks 221 * @cc_cmem_base: cmem offset reserved for CC 222 * @tx_cc_ctx: Cookie conversion context for tx desc pools 223 * @rx_cc_ctx: Cookie conversion context for rx desc pools 224 * @monitor_soc_be: BE specific monitor object 225 * @mlo_enabled: Flag to indicate MLO is enabled or not 226 * @mlo_chip_id: MLO chip_id 227 * @ml_ctxt: pointer to global ml_context 228 * @delta_tqm: delta_tqm 229 * @mlo_tstamp_offset: mlo timestamp offset 230 * @mld_peer_hash: peer hash table for ML peers 231 * Associated peer with this MAC address) 232 * @mld_peer_hash_lock: lock to protect mld_peer_hash 233 * @reo2ppe_ring: REO2PPE ring 234 * @ppe2tcl_ring: PPE2TCL ring 235 * @ppe_release_ring: PPE release ring 236 * @ppe_vp_tbl: PPE VP table 237 * @ppe_vp_tbl_lock: PPE VP table lock 238 * @num_ppe_vp_entries : Number of PPE VP entries 239 */ 240 struct dp_soc_be { 241 struct dp_soc soc; 242 uint8_t num_bank_profiles; 243 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 244 qdf_mutex_t tx_bank_lock; 245 #else 246 qdf_spinlock_t tx_bank_lock; 247 #endif 248 struct dp_tx_bank_profile *bank_profiles; 249 struct dp_spt_page_desc *page_desc_base; 250 uint32_t cc_cmem_base; 251 struct dp_hw_cookie_conversion_t tx_cc_ctx[MAX_TXDESC_POOLS]; 252 struct dp_hw_cookie_conversion_t rx_cc_ctx[MAX_RXDESC_POOLS]; 253 #ifdef WLAN_SUPPORT_PPEDS 254 struct dp_srng reo2ppe_ring; 255 struct dp_srng ppe2tcl_ring; 256 struct dp_srng ppe_release_ring; 257 struct dp_ppe_vp_tbl_entry *ppe_vp_tbl; 258 qdf_mutex_t ppe_vp_tbl_lock; 259 uint8_t num_ppe_vp_entries; 260 #endif 261 #ifdef WLAN_FEATURE_11BE_MLO 262 #ifdef WLAN_MLO_MULTI_CHIP 263 uint8_t mlo_enabled; 264 uint8_t mlo_chip_id; 265 struct dp_mlo_ctxt *ml_ctxt; 266 uint64_t delta_tqm; 267 uint64_t mlo_tstamp_offset; 268 #else 269 /* Protect mld peer hash table */ 270 DP_MUTEX_TYPE mld_peer_hash_lock; 271 struct { 272 uint32_t mask; 273 uint32_t idx_bits; 274 275 TAILQ_HEAD(, dp_peer) * bins; 276 } mld_peer_hash; 277 #endif 278 #endif 279 }; 280 281 /* convert struct dp_soc_be pointer to struct dp_soc pointer */ 282 #define DP_SOC_BE_GET_SOC(be_soc) ((struct dp_soc *)be_soc) 283 284 /** 285 * struct dp_pdev_be - Extended DP pdev for BE targets 286 * @pdev: dp pdev structure 287 * @monitor_pdev_be: BE specific monitor object 288 * @mlo_link_id: MLO link id for PDEV 289 * @delta_tsf2: delta_tsf2 290 */ 291 struct dp_pdev_be { 292 struct dp_pdev pdev; 293 #ifdef WLAN_MLO_MULTI_CHIP 294 uint8_t mlo_link_id; 295 uint64_t delta_tsf2; 296 #endif 297 }; 298 299 /** 300 * struct dp_vdev_be - Extended DP vdev for BE targets 301 * @vdev: dp vdev structure 302 * @bank_id: bank_id to be used for TX 303 * @vdev_id_check_en: flag if HW vdev_id check is enabled for vdev 304 * @ppe_vp_enabled: flag to check if PPE VP is enabled for vdev 305 * @ppe_vp_profile: PPE VP profile 306 */ 307 struct dp_vdev_be { 308 struct dp_vdev vdev; 309 int8_t bank_id; 310 uint8_t vdev_id_check_en; 311 #ifdef WLAN_MLO_MULTI_CHIP 312 /* partner list used for Intra-BSS */ 313 uint8_t partner_vdev_list[WLAN_MAX_MLO_CHIPS][WLAN_MAX_MLO_LINKS_PER_SOC]; 314 #ifdef WLAN_FEATURE_11BE_MLO 315 #ifdef WLAN_MCAST_MLO 316 /* DP MLO seq number */ 317 uint16_t seq_num; 318 /* MLO Mcast primary vdev */ 319 bool mcast_primary; 320 #endif 321 #endif 322 #endif 323 unsigned long ppe_vp_enabled; 324 #ifdef WLAN_SUPPORT_PPEDS 325 struct dp_ppe_vp_profile ppe_vp_profile; 326 #endif 327 }; 328 329 /** 330 * struct dp_peer_be - Extended DP peer for BE targets 331 * @dp_peer: dp peer structure 332 */ 333 struct dp_peer_be { 334 struct dp_peer peer; 335 }; 336 337 /** 338 * dp_get_soc_context_size_be() - get context size for target specific DP soc 339 * 340 * Return: value in bytes for BE specific soc structure 341 */ 342 qdf_size_t dp_get_soc_context_size_be(void); 343 344 /** 345 * dp_initialize_arch_ops_be() - initialize BE specific arch ops 346 * @arch_ops: arch ops pointer 347 * 348 * Return: none 349 */ 350 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops); 351 352 /** 353 * dp_get_context_size_be() - get BE specific size for peer/vdev/pdev/soc 354 * @arch_ops: arch ops pointer 355 * 356 * Return: size in bytes for the context_type 357 */ 358 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type); 359 360 /** 361 * dp_get_be_soc_from_dp_soc() - get dp_soc_be from dp_soc 362 * @soc: dp_soc pointer 363 * 364 * Return: dp_soc_be pointer 365 */ 366 static inline struct dp_soc_be *dp_get_be_soc_from_dp_soc(struct dp_soc *soc) 367 { 368 return (struct dp_soc_be *)soc; 369 } 370 371 #ifdef WLAN_MLO_MULTI_CHIP 372 typedef struct dp_mlo_ctxt *dp_mld_peer_hash_obj_t; 373 374 /* 375 * dp_mlo_get_peer_hash_obj() - return the container struct of MLO hash table 376 * 377 * @soc: soc handle 378 * 379 * return: MLD peer hash object 380 */ 381 static inline dp_mld_peer_hash_obj_t 382 dp_mlo_get_peer_hash_obj(struct dp_soc *soc) 383 { 384 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 385 386 return be_soc->ml_ctxt; 387 } 388 389 void dp_clr_mlo_ptnr_list(struct dp_soc *soc, struct dp_vdev *vdev); 390 391 #if defined(WLAN_FEATURE_11BE_MLO) 392 /** 393 * dp_mlo_partner_chips_map() - Map MLO peers to partner SOCs 394 * @soc: Soc handle 395 * @peer: DP peer handle for ML peer 396 * @peer_id: peer_id 397 * Return: None 398 */ 399 void dp_mlo_partner_chips_map(struct dp_soc *soc, 400 struct dp_peer *peer, 401 uint16_t peer_id); 402 403 /** 404 * dp_mlo_partner_chips_unmap() - Unmap MLO peers to partner SOCs 405 * @soc: Soc handle 406 * @peer_id: peer_id 407 * Return: None 408 */ 409 void dp_mlo_partner_chips_unmap(struct dp_soc *soc, 410 uint16_t peer_id); 411 412 #ifdef WLAN_MCAST_MLO 413 typedef void dp_ptnr_vdev_iter_func(struct dp_vdev_be *be_vdev, 414 struct dp_vdev *ptnr_vdev, 415 void *arg); 416 typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc, 417 void *arg); 418 /* 419 * dp_mcast_mlo_iter_ptnr_vdev - API to iterate through ptnr vdev list 420 * @be_soc: dp_soc_be pointer 421 * @be_vdev: dp_vdev_be pointer 422 * @func : function to be called for each peer 423 * @arg : argument need to be passed to func 424 * @mod_id: module id 425 * 426 * Return: None 427 */ 428 void dp_mcast_mlo_iter_ptnr_vdev(struct dp_soc_be *be_soc, 429 struct dp_vdev_be *be_vdev, 430 dp_ptnr_vdev_iter_func func, 431 void *arg, 432 enum dp_mod_id mod_id); 433 /* 434 * dp_mcast_mlo_iter_ptnr_soc - API to iterate through ptnr soc list 435 * @be_soc: dp_soc_be pointer 436 * @func : function to be called for each peer 437 * @arg : argument need to be passed to func 438 * 439 * Return: None 440 */ 441 void dp_mcast_mlo_iter_ptnr_soc(struct dp_soc_be *be_soc, 442 dp_ptnr_soc_iter_func func, 443 void *arg); 444 /* 445 * dp_mlo_get_mcast_primary_vdev- get ref to mcast primary vdev 446 * @be_soc: dp_soc_be pointer 447 * @be_vdev: dp_vdev_be pointer 448 * @mod_id: module id 449 * 450 * Return: mcast primary DP VDEV handle on success, NULL on failure 451 */ 452 struct dp_vdev *dp_mlo_get_mcast_primary_vdev(struct dp_soc_be *be_soc, 453 struct dp_vdev_be *be_vdev, 454 enum dp_mod_id mod_id); 455 #endif 456 #endif 457 458 #else 459 typedef struct dp_soc_be *dp_mld_peer_hash_obj_t; 460 461 static inline dp_mld_peer_hash_obj_t 462 dp_mlo_get_peer_hash_obj(struct dp_soc *soc) 463 { 464 return dp_get_be_soc_from_dp_soc(soc); 465 } 466 467 static inline void dp_clr_mlo_ptnr_list(struct dp_soc *soc, 468 struct dp_vdev *vdev) 469 { 470 } 471 #endif 472 473 /* 474 * dp_mlo_peer_find_hash_attach_be() - API to initialize ML peer hash table 475 * 476 * @mld_hash_obj: Peer has object 477 * @hash_elems: number of entries in hash table 478 * 479 * return: QDF_STATUS_SUCCESS when attach is success else QDF_STATUS_FAILURE 480 */ 481 QDF_STATUS 482 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj, 483 int hash_elems); 484 485 /* 486 * dp_mlo_peer_find_hash_detach_be() - API to de-initialize ML peer hash table 487 * 488 * @mld_hash_obj: Peer has object 489 * 490 * return: void 491 */ 492 void dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj); 493 494 /** 495 * dp_get_be_pdev_from_dp_pdev() - get dp_pdev_be from dp_pdev 496 * @pdev: dp_pdev pointer 497 * 498 * Return: dp_pdev_be pointer 499 */ 500 static inline 501 struct dp_pdev_be *dp_get_be_pdev_from_dp_pdev(struct dp_pdev *pdev) 502 { 503 return (struct dp_pdev_be *)pdev; 504 } 505 506 /** 507 * dp_get_be_vdev_from_dp_vdev() - get dp_vdev_be from dp_vdev 508 * @vdev: dp_vdev pointer 509 * 510 * Return: dp_vdev_be pointer 511 */ 512 static inline 513 struct dp_vdev_be *dp_get_be_vdev_from_dp_vdev(struct dp_vdev *vdev) 514 { 515 return (struct dp_vdev_be *)vdev; 516 } 517 518 /** 519 * dp_get_be_peer_from_dp_peer() - get dp_peer_be from dp_peer 520 * @peer: dp_peer pointer 521 * 522 * Return: dp_peer_be pointer 523 */ 524 static inline 525 struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer) 526 { 527 return (struct dp_peer_be *)peer; 528 } 529 530 QDF_STATUS 531 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc, 532 struct dp_hw_cookie_conversion_t *cc_ctx, 533 uint32_t num_descs, 534 enum dp_desc_type desc_type, 535 uint8_t desc_pool_id); 536 537 QDF_STATUS 538 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc, 539 struct dp_hw_cookie_conversion_t *cc_ctx); 540 QDF_STATUS 541 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc, 542 struct dp_hw_cookie_conversion_t *cc_ctx); 543 QDF_STATUS 544 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 545 struct dp_hw_cookie_conversion_t *cc_ctx); 546 /** 547 * dp_cc_spt_page_desc_alloc() - allocate SPT DDR page descriptor from pool 548 * @be_soc: beryllium soc handler 549 * @list_head: pointer to page desc head 550 * @list_tail: pointer to page desc tail 551 * @num_desc: number of TX/RX Descs required for SPT pages 552 * 553 * Return: number of SPT page Desc allocated 554 */ 555 uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc, 556 struct dp_spt_page_desc **list_head, 557 struct dp_spt_page_desc **list_tail, 558 uint16_t num_desc); 559 /** 560 * dp_cc_spt_page_desc_free() - free SPT DDR page descriptor to pool 561 * @be_soc: beryllium soc handler 562 * @list_head: pointer to page desc head 563 * @list_tail: pointer to page desc tail 564 * @page_nums: number of page desc freed back to pool 565 */ 566 void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc, 567 struct dp_spt_page_desc **list_head, 568 struct dp_spt_page_desc **list_tail, 569 uint16_t page_nums); 570 571 /** 572 * dp_cc_desc_id_generate() - generate SW cookie ID according to 573 DDR page 4K aligned or not 574 * @ppt_index: offset index in primary page table 575 * @spt_index: offset index in sceondary DDR page 576 * 577 * Generate SW cookie ID to match as HW expected 578 * 579 * Return: cookie ID 580 */ 581 static inline uint32_t dp_cc_desc_id_generate(uint32_t ppt_index, 582 uint16_t spt_index) 583 { 584 /* 585 * for 4k aligned case, cmem entry size is 4 bytes, 586 * HW index from bit19~bit10 value = ppt_index / 2, high 32bits flag 587 * from bit9 value = ppt_index % 2, then bit 19 ~ bit9 value is 588 * exactly same with original ppt_index value. 589 * for 4k un-aligned case, cmem entry size is 8 bytes. 590 * bit19 ~ bit9 will be HW index value, same as ppt_index value. 591 */ 592 return ((((uint32_t)ppt_index) << DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT) | 593 spt_index); 594 } 595 596 /** 597 * dp_cc_desc_va_find() - find TX/RX Descs virtual address by ID 598 * @be_soc: be soc handle 599 * @desc_id: TX/RX Dess ID 600 * 601 * Return: TX/RX Desc virtual address 602 */ 603 static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc, 604 uint32_t desc_id) 605 { 606 struct dp_soc_be *be_soc; 607 uint16_t ppt_page_id, spt_va_id; 608 uint8_t *spt_page_va; 609 610 be_soc = dp_get_be_soc_from_dp_soc(soc); 611 ppt_page_id = (desc_id & DP_CC_DESC_ID_PPT_PAGE_OS_MASK) >> 612 DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT; 613 614 spt_va_id = (desc_id & DP_CC_DESC_ID_SPT_VA_OS_MASK) >> 615 DP_CC_DESC_ID_SPT_VA_OS_SHIFT; 616 617 /* 618 * ppt index in cmem is same order where the page in the 619 * page desc array during initialization. 620 * entry size in DDR page is 64 bits, for 32 bits system, 621 * only lower 32 bits VA value is needed. 622 */ 623 spt_page_va = be_soc->page_desc_base[ppt_page_id].page_v_addr; 624 625 return (*((uintptr_t *)(spt_page_va + 626 spt_va_id * DP_CC_HW_READ_BYTES))); 627 } 628 629 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 630 /** 631 * enum dp_srng_near_full_levels - SRNG Near FULL levels 632 * @DP_SRNG_THRESH_SAFE: SRNG level safe for yielding the near full mode 633 * of processing the entries in SRNG 634 * @DP_SRNG_THRESH_NEAR_FULL: SRNG level enters the near full mode 635 * of processing the entries in SRNG 636 * @DP_SRNG_THRESH_CRITICAL: SRNG level enters the critical level of full 637 * condition and drastic steps need to be taken for processing 638 * the entries in SRNG 639 */ 640 enum dp_srng_near_full_levels { 641 DP_SRNG_THRESH_SAFE, 642 DP_SRNG_THRESH_NEAR_FULL, 643 DP_SRNG_THRESH_CRITICAL, 644 }; 645 646 /** 647 * dp_srng_check_ring_near_full() - Check if SRNG is marked as near-full from 648 * its corresponding near-full irq handler 649 * @soc: Datapath SoC handle 650 * @dp_srng: datapath handle for this SRNG 651 * 652 * Return: 1, if the srng was marked as near-full 653 * 0, if the srng was not marked as near-full 654 */ 655 static inline int dp_srng_check_ring_near_full(struct dp_soc *soc, 656 struct dp_srng *dp_srng) 657 { 658 return qdf_atomic_read(&dp_srng->near_full); 659 } 660 661 /** 662 * dp_srng_get_near_full_level() - Check the num available entries in the 663 * consumer srng and return the level of the srng 664 * near full state. 665 * @soc: Datapath SoC Handle [To be validated by the caller] 666 * @hal_ring_hdl: SRNG handle 667 * 668 * Return: near-full level 669 */ 670 static inline int 671 dp_srng_get_near_full_level(struct dp_soc *soc, struct dp_srng *dp_srng) 672 { 673 uint32_t num_valid; 674 675 num_valid = hal_srng_dst_num_valid_nolock(soc->hal_soc, 676 dp_srng->hal_srng, 677 true); 678 679 if (num_valid > dp_srng->crit_thresh) 680 return DP_SRNG_THRESH_CRITICAL; 681 else if (num_valid < dp_srng->safe_thresh) 682 return DP_SRNG_THRESH_SAFE; 683 else 684 return DP_SRNG_THRESH_NEAR_FULL; 685 } 686 687 #define DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER 2 688 689 /** 690 * dp_srng_test_and_update_nf_params() - Test the near full level and update 691 * the reap_limit and flags to reflect the state. 692 * @soc: Datapath soc handle 693 * @srng: Datapath handle for the srng 694 * @max_reap_limit: [Output Param] Buffer to set the map_reap_limit as 695 * per the near-full state 696 * 697 * Return: 1, if the srng is near full 698 * 0, if the srng is not near full 699 */ 700 static inline int 701 _dp_srng_test_and_update_nf_params(struct dp_soc *soc, 702 struct dp_srng *srng, 703 int *max_reap_limit) 704 { 705 int ring_near_full = 0, near_full_level; 706 707 if (dp_srng_check_ring_near_full(soc, srng)) { 708 near_full_level = dp_srng_get_near_full_level(soc, srng); 709 switch (near_full_level) { 710 case DP_SRNG_THRESH_CRITICAL: 711 /* Currently not doing anything special here */ 712 fallthrough; 713 case DP_SRNG_THRESH_NEAR_FULL: 714 ring_near_full = 1; 715 *max_reap_limit *= DP_SRNG_PER_LOOP_NF_REAP_MULTIPLIER; 716 break; 717 case DP_SRNG_THRESH_SAFE: 718 qdf_atomic_set(&srng->near_full, 0); 719 ring_near_full = 0; 720 break; 721 default: 722 qdf_assert(0); 723 break; 724 } 725 } 726 727 return ring_near_full; 728 } 729 #else 730 static inline int 731 _dp_srng_test_and_update_nf_params(struct dp_soc *soc, 732 struct dp_srng *srng, 733 int *max_reap_limit) 734 { 735 return 0; 736 } 737 #endif 738 739 static inline 740 uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id, 741 enum dp_desc_type desc_type) 742 { 743 switch (desc_type) { 744 case DP_TX_DESC_TYPE: 745 return (DP_TX_DESC_CMEM_OFFSET + 746 (desc_pool_id * DP_TX_DESC_POOL_CMEM_SIZE)); 747 case DP_RX_DESC_BUF_TYPE: 748 return (DP_RX_DESC_CMEM_OFFSET + 749 ((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) * 750 DP_RX_DESC_POOL_CMEM_SIZE); 751 default: 752 QDF_BUG(0); 753 } 754 return 0; 755 } 756 757 #ifndef WLAN_MLO_MULTI_CHIP 758 static inline 759 void dp_soc_mlo_fill_params(struct dp_soc *soc, 760 struct cdp_soc_attach_params *params) 761 { 762 } 763 764 static inline 765 void dp_pdev_mlo_fill_params(struct dp_pdev *pdev, 766 struct cdp_pdev_attach_params *params) 767 { 768 } 769 770 static inline 771 void dp_mlo_update_link_to_pdev_map(struct dp_soc *soc, struct dp_pdev *pdev) 772 { 773 } 774 775 static inline 776 void dp_mlo_update_link_to_pdev_unmap(struct dp_soc *soc, struct dp_pdev *pdev) 777 { 778 } 779 #endif 780 781 /* 782 * dp_txrx_set_vdev_param_be: target specific ops while setting vdev params 783 * @soc : DP soc handle 784 * @vdev: pointer to vdev structure 785 * @param: parameter type to get value 786 * @val: value 787 * 788 * return: QDF_STATUS 789 */ 790 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc, 791 struct dp_vdev *vdev, 792 enum cdp_vdev_param_type param, 793 cdp_config_param_type val); 794 795 #endif 796