1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <wlan_utility.h> 21 #include <dp_internal.h> 22 #include <dp_htt.h> 23 #include "dp_be.h" 24 #include "dp_be_tx.h" 25 #include "dp_be_rx.h" 26 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT) 27 #include "dp_mon_2.0.h" 28 #endif 29 #include <hal_be_api.h> 30 31 /* Generic AST entry aging timer value */ 32 #define DP_AST_AGING_TIMER_DEFAULT_MS 5000 33 34 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 35 #define DP_TX_VDEV_ID_CHECK_ENABLE 0 36 37 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 38 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 39 {1, 4, HAL_BE_WBM_SW4_BM_ID, 0}, 40 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 41 {3, 6, HAL_BE_WBM_SW5_BM_ID, 0}, 42 {4, 7, HAL_BE_WBM_SW6_BM_ID, 0} 43 }; 44 #else 45 #define DP_TX_VDEV_ID_CHECK_ENABLE 1 46 47 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 48 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 49 {1, 1, HAL_BE_WBM_SW1_BM_ID, 0}, 50 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 51 {3, 3, HAL_BE_WBM_SW3_BM_ID, 0}, 52 {4, 4, HAL_BE_WBM_SW4_BM_ID, 0} 53 }; 54 #endif 55 56 static void dp_soc_cfg_attach_be(struct dp_soc *soc) 57 { 58 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx; 59 60 wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM); 61 62 soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array; 63 64 /* this is used only when dmac mode is enabled */ 65 soc->num_rx_refill_buf_rings = 1; 66 67 soc->wlan_cfg_ctx->notify_frame_support = 68 DP_MARK_NOTIFY_FRAME_SUPPORT; 69 } 70 71 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type) 72 { 73 switch (context_type) { 74 case DP_CONTEXT_TYPE_SOC: 75 return sizeof(struct dp_soc_be); 76 case DP_CONTEXT_TYPE_PDEV: 77 return sizeof(struct dp_pdev_be); 78 case DP_CONTEXT_TYPE_VDEV: 79 return sizeof(struct dp_vdev_be); 80 case DP_CONTEXT_TYPE_PEER: 81 return sizeof(struct dp_peer_be); 82 default: 83 return 0; 84 } 85 } 86 87 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT) 88 qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type) 89 { 90 switch (context_type) { 91 case DP_CONTEXT_TYPE_MON_SOC: 92 return sizeof(struct dp_mon_soc_be); 93 case DP_CONTEXT_TYPE_MON_PDEV: 94 return sizeof(struct dp_mon_pdev_be); 95 default: 96 return 0; 97 } 98 } 99 #else 100 qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type) 101 { 102 switch (context_type) { 103 case DP_CONTEXT_TYPE_MON_SOC: 104 return sizeof(struct dp_mon_soc); 105 case DP_CONTEXT_TYPE_MON_PDEV: 106 return sizeof(struct dp_mon_pdev); 107 default: 108 return 0; 109 } 110 } 111 #endif 112 113 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION 114 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 115 /** 116 * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement 117 per wbm2sw ring 118 * @cc_cfg: HAL HW cookie conversion configuration structure pointer 119 * 120 * Return: None 121 */ 122 static inline 123 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 124 { 125 cc_cfg->wbm2sw6_cc_en = 1; 126 cc_cfg->wbm2sw5_cc_en = 1; 127 cc_cfg->wbm2sw4_cc_en = 1; 128 cc_cfg->wbm2sw3_cc_en = 1; 129 cc_cfg->wbm2sw2_cc_en = 1; 130 /* disable wbm2sw1 hw cc as it's for FW */ 131 cc_cfg->wbm2sw1_cc_en = 0; 132 cc_cfg->wbm2sw0_cc_en = 1; 133 cc_cfg->wbm2fw_cc_en = 0; 134 } 135 #else 136 static inline 137 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 138 { 139 cc_cfg->wbm2sw6_cc_en = 1; 140 cc_cfg->wbm2sw5_cc_en = 1; 141 cc_cfg->wbm2sw4_cc_en = 1; 142 cc_cfg->wbm2sw3_cc_en = 1; 143 cc_cfg->wbm2sw2_cc_en = 1; 144 cc_cfg->wbm2sw1_cc_en = 1; 145 cc_cfg->wbm2sw0_cc_en = 1; 146 cc_cfg->wbm2fw_cc_en = 0; 147 } 148 #endif 149 150 #if defined(WLAN_SUPPORT_RX_FISA) 151 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 152 { 153 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 154 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 155 /* get CMEM for cookie conversion */ 156 if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) { 157 dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size); 158 return QDF_STATUS_E_NOMEM; 159 } 160 161 soc->fst_cmem_size = DP_CMEM_FST_SIZE; 162 163 soc->fst_cmem_base = soc->cmem_base + 164 (soc->cmem_total_size - soc->cmem_avail_size); 165 soc->cmem_avail_size -= soc->fst_cmem_size; 166 167 dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx", 168 soc->fst_cmem_base, soc->fst_cmem_size); 169 170 return QDF_STATUS_SUCCESS; 171 } 172 #else /* !WLAN_SUPPORT_RX_FISA */ 173 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 174 { 175 return QDF_STATUS_SUCCESS; 176 } 177 #endif 178 179 /** 180 * dp_cc_reg_cfg_init() - initialize and configure HW cookie 181 conversion register 182 * @soc: SOC handle 183 * @is_4k_align: page address 4k alignd 184 * 185 * Return: None 186 */ 187 static void dp_cc_reg_cfg_init(struct dp_soc *soc, 188 bool is_4k_align) 189 { 190 struct hal_hw_cc_config cc_cfg = { 0 }; 191 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 192 193 if (soc->cdp_soc.ol_ops->get_con_mode && 194 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE) 195 return; 196 197 if (!soc->wlan_cfg_ctx->hw_cc_enabled) { 198 dp_info("INI skip HW CC register setting"); 199 return; 200 } 201 202 cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base; 203 cc_cfg.cc_global_en = true; 204 cc_cfg.page_4k_align = is_4k_align; 205 cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB; 206 cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB; 207 /* 36th bit should be 1 then HW know this is CMEM address */ 208 cc_cfg.lut_base_addr_39_32 = 0x10; 209 210 cc_cfg.error_path_cookie_conv_en = true; 211 cc_cfg.release_path_cookie_conv_en = true; 212 dp_cc_wbm_sw_en_cfg(&cc_cfg); 213 214 hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg); 215 } 216 217 /** 218 * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing 219 * @hal_soc_hdl: HAL SOC handle 220 * @offset: CMEM address 221 * @value: value to write 222 * 223 * Return: None. 224 */ 225 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 226 uint32_t offset, 227 uint32_t value) 228 { 229 hal_cmem_write(hal_soc_hdl, offset, value); 230 } 231 232 /** 233 * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for 234 HW cookie conversion 235 * @soc: SOC handle 236 * @cc_ctx: cookie conversion context pointer 237 * 238 * Return: 0 in case of success, else error value 239 */ 240 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 241 { 242 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 243 244 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 245 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 246 /* get CMEM for cookie conversion */ 247 if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) { 248 dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size); 249 return QDF_STATUS_E_RESOURCES; 250 } 251 be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base + 252 DP_CC_MEM_OFFSET_IN_CMEM); 253 254 soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE; 255 256 dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx", 257 be_soc->cc_cmem_base, soc->cmem_avail_size); 258 return QDF_STATUS_SUCCESS; 259 } 260 261 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 262 uint8_t for_feature) 263 { 264 QDF_STATUS status = QDF_STATUS_E_NOMEM; 265 266 switch (for_feature) { 267 case COOKIE_CONVERSION: 268 status = dp_hw_cc_cmem_addr_init(soc); 269 break; 270 case FISA_FST: 271 status = dp_fisa_fst_cmem_addr_init(soc); 272 break; 273 default: 274 dp_err("Invalid CMEM request"); 275 } 276 277 return status; 278 } 279 280 #else 281 282 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc, 283 bool is_4k_align) {} 284 285 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 286 uint32_t offset, 287 uint32_t value) 288 { } 289 290 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 291 { 292 return QDF_STATUS_SUCCESS; 293 } 294 295 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 296 uint8_t for_feature) 297 { 298 return QDF_STATUS_SUCCESS; 299 } 300 301 #endif 302 303 QDF_STATUS 304 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc, 305 struct dp_hw_cookie_conversion_t *cc_ctx, 306 uint32_t num_descs, 307 enum dp_desc_type desc_type, 308 uint8_t desc_pool_id) 309 { 310 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 311 uint32_t num_spt_pages, i = 0; 312 struct dp_spt_page_desc *spt_desc; 313 struct qdf_mem_dma_page_t *dma_page; 314 uint8_t chip_id; 315 316 /* estimate how many SPT DDR pages needed */ 317 num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES; 318 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 319 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 320 dp_info("num_spt_pages needed %d", num_spt_pages); 321 322 dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE, 323 &cc_ctx->page_pool, qdf_page_size, 324 num_spt_pages, 0, false); 325 if (!cc_ctx->page_pool.dma_pages) { 326 dp_err("spt ddr pages allocation failed"); 327 return QDF_STATUS_E_RESOURCES; 328 } 329 cc_ctx->page_desc_base = qdf_mem_malloc( 330 num_spt_pages * sizeof(struct dp_spt_page_desc)); 331 if (!cc_ctx->page_desc_base) { 332 dp_err("spt page descs allocation failed"); 333 goto fail_0; 334 } 335 336 chip_id = dp_mlo_get_chip_id(soc); 337 cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id, 338 desc_type); 339 340 /* initial page desc */ 341 spt_desc = cc_ctx->page_desc_base; 342 dma_page = cc_ctx->page_pool.dma_pages; 343 while (i < num_spt_pages) { 344 /* check if page address 4K aligned */ 345 if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) { 346 dp_err("non-4k aligned pages addr %pK", 347 (void *)dma_page[i].page_p_addr); 348 goto fail_1; 349 } 350 351 spt_desc[i].page_v_addr = 352 dma_page[i].page_v_addr_start; 353 spt_desc[i].page_p_addr = 354 dma_page[i].page_p_addr; 355 i++; 356 } 357 358 cc_ctx->total_page_num = num_spt_pages; 359 qdf_spinlock_create(&cc_ctx->cc_lock); 360 361 return QDF_STATUS_SUCCESS; 362 fail_1: 363 qdf_mem_free(cc_ctx->page_desc_base); 364 fail_0: 365 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 366 &cc_ctx->page_pool, 0, false); 367 368 return QDF_STATUS_E_FAILURE; 369 } 370 371 QDF_STATUS 372 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc, 373 struct dp_hw_cookie_conversion_t *cc_ctx) 374 { 375 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 376 377 qdf_mem_free(cc_ctx->page_desc_base); 378 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 379 &cc_ctx->page_pool, 0, false); 380 qdf_spinlock_destroy(&cc_ctx->cc_lock); 381 382 return QDF_STATUS_SUCCESS; 383 } 384 385 QDF_STATUS 386 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc, 387 struct dp_hw_cookie_conversion_t *cc_ctx) 388 { 389 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 390 uint32_t i = 0; 391 struct dp_spt_page_desc *spt_desc; 392 uint32_t ppt_index; 393 uint32_t ppt_id_start; 394 395 if (!cc_ctx->total_page_num) { 396 dp_err("total page num is 0"); 397 return QDF_STATUS_E_INVAL; 398 } 399 400 ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset); 401 spt_desc = cc_ctx->page_desc_base; 402 while (i < cc_ctx->total_page_num) { 403 /* write page PA to CMEM */ 404 dp_hw_cc_cmem_write(soc->hal_soc, 405 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 406 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 407 (spt_desc[i].page_p_addr >> 408 DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED)); 409 410 ppt_index = ppt_id_start + i; 411 412 if (ppt_index >= DP_CC_PPT_MAX_ENTRIES) 413 qdf_assert_always(0); 414 415 spt_desc[i].ppt_index = ppt_index; 416 417 be_soc->page_desc_base[ppt_index].page_v_addr = 418 spt_desc[i].page_v_addr; 419 i++; 420 } 421 return QDF_STATUS_SUCCESS; 422 } 423 424 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 425 QDF_STATUS 426 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 427 struct dp_hw_cookie_conversion_t *cc_ctx) 428 { 429 uint32_t ppt_index; 430 struct dp_spt_page_desc *spt_desc; 431 int i = 0; 432 433 spt_desc = cc_ctx->page_desc_base; 434 while (i < cc_ctx->total_page_num) { 435 ppt_index = spt_desc[i].ppt_index; 436 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 437 i++; 438 } 439 return QDF_STATUS_SUCCESS; 440 } 441 #else 442 QDF_STATUS 443 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 444 struct dp_hw_cookie_conversion_t *cc_ctx) 445 { 446 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 447 uint32_t ppt_index; 448 struct dp_spt_page_desc *spt_desc; 449 int i = 0; 450 451 spt_desc = cc_ctx->page_desc_base; 452 while (i < cc_ctx->total_page_num) { 453 /* reset PA in CMEM to NULL */ 454 dp_hw_cc_cmem_write(soc->hal_soc, 455 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 456 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 457 0); 458 459 ppt_index = spt_desc[i].ppt_index; 460 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 461 i++; 462 } 463 return QDF_STATUS_SUCCESS; 464 } 465 #endif 466 467 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc) 468 { 469 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 470 int i = 0; 471 472 473 for (i = 0; i < MAX_TXDESC_POOLS; i++) 474 dp_hw_cookie_conversion_detach(be_soc, 475 &be_soc->tx_cc_ctx[i]); 476 477 for (i = 0; i < MAX_RXDESC_POOLS; i++) 478 dp_hw_cookie_conversion_detach(be_soc, 479 &be_soc->rx_cc_ctx[i]); 480 481 qdf_mem_free(be_soc->page_desc_base); 482 be_soc->page_desc_base = NULL; 483 484 return QDF_STATUS_SUCCESS; 485 } 486 487 #ifdef WLAN_MLO_MULTI_CHIP 488 #ifdef WLAN_MCAST_MLO 489 static inline void 490 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 491 { 492 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 493 494 be_vdev->mcast_primary = false; 495 be_vdev->seq_num = 0; 496 dp_tx_mcast_mlo_reinject_routing_set(soc, 497 (void *)&be_vdev->mcast_primary); 498 if (vdev->opmode == wlan_op_mode_ap) { 499 if (vdev->mlo_vdev) 500 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 501 vdev->vdev_id, 502 HAL_TX_MCAST_CTRL_DROP); 503 else 504 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 505 vdev->vdev_id, 506 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 507 } 508 } 509 510 static inline void 511 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 512 { 513 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 514 515 be_vdev->seq_num = 0; 516 be_vdev->mcast_primary = false; 517 vdev->mlo_vdev = false; 518 } 519 #else 520 static inline void 521 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 522 { 523 } 524 525 static inline void 526 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 527 { 528 } 529 #endif 530 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 531 { 532 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 533 534 qdf_mem_set(be_vdev->partner_vdev_list, 535 WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC, 536 CDP_INVALID_VDEV_ID); 537 } 538 539 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 540 struct cdp_lro_hash_config *lro_hash) 541 { 542 dp_mlo_get_rx_hash_key(soc, lro_hash); 543 } 544 #else 545 static inline void 546 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 547 { 548 } 549 550 static inline void 551 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 552 { 553 } 554 555 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 556 { 557 } 558 559 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 560 struct cdp_lro_hash_config *lro_hash) 561 { 562 dp_get_rx_hash_key_bytes(lro_hash); 563 } 564 #endif 565 566 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc, 567 struct cdp_soc_attach_params *params) 568 { 569 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 570 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 571 uint32_t max_tx_rx_desc_num, num_spt_pages; 572 uint32_t num_entries; 573 int i = 0; 574 575 max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS + 576 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS; 577 /* estimate how many SPT DDR pages needed */ 578 num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES; 579 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 580 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 581 582 be_soc->page_desc_base = qdf_mem_malloc( 583 DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc)); 584 if (!be_soc->page_desc_base) { 585 dp_err("spt page descs allocation failed"); 586 return QDF_STATUS_E_NOMEM; 587 } 588 589 soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id(); 590 591 qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION); 592 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 593 goto fail; 594 595 dp_soc_mlo_fill_params(soc, params); 596 597 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 598 num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx); 599 qdf_status = 600 dp_hw_cookie_conversion_attach(be_soc, 601 &be_soc->tx_cc_ctx[i], 602 num_entries, 603 DP_TX_DESC_TYPE, i); 604 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 605 goto fail; 606 } 607 608 qdf_status = dp_get_cmem_allocation(soc, FISA_FST); 609 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 610 goto fail; 611 612 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 613 num_entries = 614 wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx); 615 qdf_status = 616 dp_hw_cookie_conversion_attach(be_soc, 617 &be_soc->rx_cc_ctx[i], 618 num_entries, 619 DP_RX_DESC_BUF_TYPE, i); 620 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 621 goto fail; 622 } 623 624 return qdf_status; 625 fail: 626 dp_soc_detach_be(soc); 627 return qdf_status; 628 } 629 630 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc) 631 { 632 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 633 int i = 0; 634 635 dp_tx_deinit_bank_profiles(be_soc); 636 for (i = 0; i < MAX_TXDESC_POOLS; i++) 637 dp_hw_cookie_conversion_deinit(be_soc, 638 &be_soc->tx_cc_ctx[i]); 639 640 for (i = 0; i < MAX_RXDESC_POOLS; i++) 641 dp_hw_cookie_conversion_deinit(be_soc, 642 &be_soc->rx_cc_ctx[i]); 643 644 return QDF_STATUS_SUCCESS; 645 } 646 647 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc) 648 { 649 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 650 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 651 int i = 0; 652 653 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 654 qdf_status = 655 dp_hw_cookie_conversion_init(be_soc, 656 &be_soc->tx_cc_ctx[i]); 657 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 658 goto fail; 659 } 660 661 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 662 qdf_status = 663 dp_hw_cookie_conversion_init(be_soc, 664 &be_soc->rx_cc_ctx[i]); 665 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 666 goto fail; 667 } 668 669 /* route vdev_id mismatch notification via FW completion */ 670 hal_tx_vdev_mismatch_routing_set(soc->hal_soc, 671 HAL_TX_VDEV_MISMATCH_FW_NOTIFY); 672 673 qdf_status = dp_tx_init_bank_profiles(be_soc); 674 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 675 goto fail; 676 677 /* write WBM/REO cookie conversion CFG register */ 678 dp_cc_reg_cfg_init(soc, true); 679 680 return qdf_status; 681 fail: 682 dp_soc_deinit_be(soc); 683 return qdf_status; 684 } 685 686 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev, 687 struct cdp_pdev_attach_params *params) 688 { 689 dp_pdev_mlo_fill_params(pdev, params); 690 dp_mlo_update_link_to_pdev_map(pdev->soc, pdev); 691 692 return QDF_STATUS_SUCCESS; 693 } 694 695 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev) 696 { 697 dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev); 698 699 return QDF_STATUS_SUCCESS; 700 } 701 702 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev) 703 { 704 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 705 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 706 struct dp_pdev *pdev = vdev->pdev; 707 708 if (vdev->opmode == wlan_op_mode_monitor) 709 return QDF_STATUS_SUCCESS; 710 711 be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE; 712 713 be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev); 714 715 if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) { 716 QDF_BUG(0); 717 return QDF_STATUS_E_FAULT; 718 } 719 720 if (vdev->opmode == wlan_op_mode_sta) { 721 if (soc->cdp_soc.ol_ops->set_mec_timer) 722 soc->cdp_soc.ol_ops->set_mec_timer( 723 soc->ctrl_psoc, 724 vdev->vdev_id, 725 DP_AST_AGING_TIMER_DEFAULT_MS); 726 727 if (pdev->isolation) 728 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 729 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 730 else 731 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 732 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 733 } 734 735 dp_mlo_mcast_init(soc, vdev); 736 dp_mlo_init_ptnr_list(vdev); 737 738 return QDF_STATUS_SUCCESS; 739 } 740 741 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev) 742 { 743 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 744 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 745 746 if (vdev->opmode == wlan_op_mode_monitor) 747 return QDF_STATUS_SUCCESS; 748 749 if (vdev->opmode == wlan_op_mode_ap) 750 dp_mlo_mcast_deinit(soc, vdev); 751 752 dp_tx_put_bank_profile(be_soc, be_vdev); 753 dp_clr_mlo_ptnr_list(soc, vdev); 754 755 return QDF_STATUS_SUCCESS; 756 } 757 758 qdf_size_t dp_get_soc_context_size_be(void) 759 { 760 return sizeof(struct dp_soc_be); 761 } 762 763 #ifdef NO_RX_PKT_HDR_TLV 764 /** 765 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 766 * @soc: Common DP soc handle 767 * 768 * Return: QDF_STATUS 769 */ 770 static QDF_STATUS 771 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 772 { 773 int i; 774 int mac_id; 775 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 776 struct dp_srng *rx_mac_srng; 777 QDF_STATUS status = QDF_STATUS_SUCCESS; 778 779 /* 780 * In Beryllium chipset msdu_start, mpdu_end 781 * and rx_attn are part of msdu_end/mpdu_start 782 */ 783 htt_tlv_filter.msdu_start = 0; 784 htt_tlv_filter.mpdu_end = 0; 785 htt_tlv_filter.attention = 0; 786 htt_tlv_filter.mpdu_start = 1; 787 htt_tlv_filter.msdu_end = 1; 788 htt_tlv_filter.packet = 1; 789 htt_tlv_filter.packet_header = 1; 790 791 htt_tlv_filter.ppdu_start = 0; 792 htt_tlv_filter.ppdu_end = 0; 793 htt_tlv_filter.ppdu_end_user_stats = 0; 794 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 795 htt_tlv_filter.ppdu_end_status_done = 0; 796 htt_tlv_filter.enable_fp = 1; 797 htt_tlv_filter.enable_md = 0; 798 htt_tlv_filter.enable_md = 0; 799 htt_tlv_filter.enable_mo = 0; 800 801 htt_tlv_filter.fp_mgmt_filter = 0; 802 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 803 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 804 FILTER_DATA_MCAST | 805 FILTER_DATA_DATA); 806 htt_tlv_filter.mo_mgmt_filter = 0; 807 htt_tlv_filter.mo_ctrl_filter = 0; 808 htt_tlv_filter.mo_data_filter = 0; 809 htt_tlv_filter.md_data_filter = 0; 810 811 htt_tlv_filter.offset_valid = true; 812 813 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 814 htt_tlv_filter.rx_mpdu_end_offset = 0; 815 htt_tlv_filter.rx_msdu_start_offset = 0; 816 htt_tlv_filter.rx_attn_offset = 0; 817 818 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 819 /*Not subscribing rx_pkt_header*/ 820 htt_tlv_filter.rx_header_offset = 0; 821 htt_tlv_filter.rx_mpdu_start_offset = 822 hal_rx_mpdu_start_offset_get(soc->hal_soc); 823 htt_tlv_filter.rx_msdu_end_offset = 824 hal_rx_msdu_end_offset_get(soc->hal_soc); 825 826 for (i = 0; i < MAX_PDEV_CNT; i++) { 827 struct dp_pdev *pdev = soc->pdev_list[i]; 828 829 if (!pdev) 830 continue; 831 832 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 833 int mac_for_pdev = 834 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 835 /* 836 * Obtain lmac id from pdev to access the LMAC ring 837 * in soc context 838 */ 839 int lmac_id = 840 dp_get_lmac_id_for_pdev_id(soc, mac_id, 841 pdev->pdev_id); 842 843 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 844 845 if (!rx_mac_srng->hal_srng) 846 continue; 847 848 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 849 rx_mac_srng->hal_srng, 850 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 851 &htt_tlv_filter); 852 } 853 } 854 return status; 855 } 856 #else 857 /** 858 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 859 * @soc: Common DP soc handle 860 * 861 * Return: QDF_STATUS 862 */ 863 static QDF_STATUS 864 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 865 { 866 int i; 867 int mac_id; 868 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 869 struct dp_srng *rx_mac_srng; 870 QDF_STATUS status = QDF_STATUS_SUCCESS; 871 872 /* 873 * In Beryllium chipset msdu_start, mpdu_end 874 * and rx_attn are part of msdu_end/mpdu_start 875 */ 876 htt_tlv_filter.msdu_start = 0; 877 htt_tlv_filter.mpdu_end = 0; 878 htt_tlv_filter.attention = 0; 879 htt_tlv_filter.mpdu_start = 1; 880 htt_tlv_filter.msdu_end = 1; 881 htt_tlv_filter.packet = 1; 882 htt_tlv_filter.packet_header = 1; 883 884 htt_tlv_filter.ppdu_start = 0; 885 htt_tlv_filter.ppdu_end = 0; 886 htt_tlv_filter.ppdu_end_user_stats = 0; 887 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 888 htt_tlv_filter.ppdu_end_status_done = 0; 889 htt_tlv_filter.enable_fp = 1; 890 htt_tlv_filter.enable_md = 0; 891 htt_tlv_filter.enable_md = 0; 892 htt_tlv_filter.enable_mo = 0; 893 894 htt_tlv_filter.fp_mgmt_filter = 0; 895 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 896 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 897 FILTER_DATA_MCAST | 898 FILTER_DATA_DATA); 899 htt_tlv_filter.mo_mgmt_filter = 0; 900 htt_tlv_filter.mo_ctrl_filter = 0; 901 htt_tlv_filter.mo_data_filter = 0; 902 htt_tlv_filter.md_data_filter = 0; 903 904 htt_tlv_filter.offset_valid = true; 905 906 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 907 htt_tlv_filter.rx_mpdu_end_offset = 0; 908 htt_tlv_filter.rx_msdu_start_offset = 0; 909 htt_tlv_filter.rx_attn_offset = 0; 910 911 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 912 htt_tlv_filter.rx_header_offset = 913 hal_rx_pkt_tlv_offset_get(soc->hal_soc); 914 htt_tlv_filter.rx_mpdu_start_offset = 915 hal_rx_mpdu_start_offset_get(soc->hal_soc); 916 htt_tlv_filter.rx_msdu_end_offset = 917 hal_rx_msdu_end_offset_get(soc->hal_soc); 918 919 dp_info("TLV subscription\n" 920 "msdu_start %d, mpdu_end %d, attention %d" 921 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n" 922 "TLV offsets\n" 923 "msdu_start %d, mpdu_end %d, attention %d" 924 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n", 925 htt_tlv_filter.msdu_start, 926 htt_tlv_filter.mpdu_end, 927 htt_tlv_filter.attention, 928 htt_tlv_filter.mpdu_start, 929 htt_tlv_filter.msdu_end, 930 htt_tlv_filter.packet_header, 931 htt_tlv_filter.packet, 932 htt_tlv_filter.rx_msdu_start_offset, 933 htt_tlv_filter.rx_mpdu_end_offset, 934 htt_tlv_filter.rx_attn_offset, 935 htt_tlv_filter.rx_mpdu_start_offset, 936 htt_tlv_filter.rx_msdu_end_offset, 937 htt_tlv_filter.rx_header_offset, 938 htt_tlv_filter.rx_packet_offset); 939 940 for (i = 0; i < MAX_PDEV_CNT; i++) { 941 struct dp_pdev *pdev = soc->pdev_list[i]; 942 943 if (!pdev) 944 continue; 945 946 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 947 int mac_for_pdev = 948 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 949 /* 950 * Obtain lmac id from pdev to access the LMAC ring 951 * in soc context 952 */ 953 int lmac_id = 954 dp_get_lmac_id_for_pdev_id(soc, mac_id, 955 pdev->pdev_id); 956 957 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 958 959 if (!rx_mac_srng->hal_srng) 960 continue; 961 962 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 963 rx_mac_srng->hal_srng, 964 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 965 &htt_tlv_filter); 966 } 967 } 968 return status; 969 970 } 971 #endif 972 973 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 974 /** 975 * dp_service_near_full_srngs_be() - Main bottom half callback for the 976 * near-full IRQs. 977 * @soc: Datapath SoC handle 978 * @int_ctx: Interrupt context 979 * @dp_budget: Budget of the work that can be done in the bottom half 980 * 981 * Return: work done in the handler 982 */ 983 static uint32_t 984 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx, 985 uint32_t dp_budget) 986 { 987 int ring = 0; 988 int budget = dp_budget; 989 uint32_t work_done = 0; 990 uint32_t remaining_quota = dp_budget; 991 struct dp_intr_stats *intr_stats = &int_ctx->intr_stats; 992 int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask; 993 int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask; 994 int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask; 995 int rx_near_full_mask = rx_near_full_grp_1_mask | 996 rx_near_full_grp_2_mask; 997 998 dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x", 999 rx_near_full_mask, 1000 tx_ring_near_full_mask); 1001 1002 if (rx_near_full_mask) { 1003 for (ring = 0; ring < soc->num_reo_dest_rings; ring++) { 1004 if (!(rx_near_full_mask & (1 << ring))) 1005 continue; 1006 1007 work_done = dp_rx_nf_process(int_ctx, 1008 soc->reo_dest_ring[ring].hal_srng, 1009 ring, remaining_quota); 1010 if (work_done) { 1011 intr_stats->num_rx_ring_near_full_masks[ring]++; 1012 dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d", 1013 rx_near_full_mask, ring, 1014 work_done, 1015 budget); 1016 budget -= work_done; 1017 if (budget <= 0) 1018 goto budget_done; 1019 remaining_quota = budget; 1020 } 1021 } 1022 } 1023 1024 if (tx_ring_near_full_mask) { 1025 for (ring = 0; ring < soc->num_tcl_data_rings; ring++) { 1026 if (!(tx_ring_near_full_mask & (1 << ring))) 1027 continue; 1028 1029 work_done = dp_tx_comp_nf_handler(int_ctx, soc, 1030 soc->tx_comp_ring[ring].hal_srng, 1031 ring, remaining_quota); 1032 if (work_done) { 1033 intr_stats->num_tx_comp_ring_near_full_masks[ring]++; 1034 dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d", 1035 tx_ring_near_full_mask, ring, 1036 work_done, budget); 1037 budget -= work_done; 1038 if (budget <= 0) 1039 break; 1040 remaining_quota = budget; 1041 } 1042 } 1043 } 1044 1045 intr_stats->num_near_full_masks++; 1046 1047 budget_done: 1048 return dp_budget - budget; 1049 } 1050 1051 /** 1052 * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full 1053 * state and set the reap_limit appropriately 1054 * as per the near full state 1055 * @soc: Datapath soc handle 1056 * @dp_srng: Datapath handle for SRNG 1057 * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per 1058 * the srng near-full state 1059 * 1060 * Return: 1, if the srng is in near-full state 1061 * 0, if the srng is not in near-full state 1062 */ 1063 static int 1064 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc, 1065 struct dp_srng *dp_srng, 1066 int *max_reap_limit) 1067 { 1068 return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit); 1069 } 1070 1071 /** 1072 * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the 1073 * near full IRQ handling operations. 1074 * @arch_ops: arch ops handle 1075 * 1076 * Return: none 1077 */ 1078 static inline void 1079 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1080 { 1081 arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be; 1082 arch_ops->dp_srng_test_and_update_nf_params = 1083 dp_srng_test_and_update_nf_params_be; 1084 } 1085 1086 #else 1087 static inline void 1088 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1089 { 1090 } 1091 #endif 1092 1093 #ifdef WLAN_SUPPORT_PPEDS 1094 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1095 { 1096 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1097 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1098 1099 soc_cfg_ctx = soc->wlan_cfg_ctx; 1100 1101 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1102 return; 1103 1104 dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0); 1105 wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned, 1106 be_soc->ppe_release_ring.alloc_size, 1107 soc->ctrl_psoc, 1108 WLAN_MD_DP_SRNG_PPE_RELEASE, 1109 "ppe_release_ring"); 1110 1111 dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0); 1112 wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1113 be_soc->ppe2tcl_ring.alloc_size, 1114 soc->ctrl_psoc, 1115 WLAN_MD_DP_SRNG_PPE2TCL, 1116 "ppe2tcl_ring"); 1117 1118 dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0); 1119 wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1120 be_soc->reo2ppe_ring.alloc_size, 1121 soc->ctrl_psoc, 1122 WLAN_MD_DP_SRNG_REO2PPE, 1123 "reo2ppe_ring"); 1124 } 1125 1126 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1127 { 1128 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1129 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1130 1131 soc_cfg_ctx = soc->wlan_cfg_ctx; 1132 1133 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1134 return; 1135 1136 dp_srng_free(soc, &be_soc->ppe_release_ring); 1137 1138 dp_srng_free(soc, &be_soc->ppe2tcl_ring); 1139 1140 dp_srng_free(soc, &be_soc->reo2ppe_ring); 1141 } 1142 1143 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1144 { 1145 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1146 uint32_t entries; 1147 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1148 1149 soc_cfg_ctx = soc->wlan_cfg_ctx; 1150 1151 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1152 return QDF_STATUS_SUCCESS; 1153 1154 entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx); 1155 1156 if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE, 1157 entries, 0)) { 1158 dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc); 1159 goto fail; 1160 } 1161 1162 entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx); 1163 if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 1164 entries, 0)) { 1165 dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc); 1166 goto fail; 1167 } 1168 1169 entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx); 1170 if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 1171 entries, 0)) { 1172 dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc); 1173 goto fail; 1174 } 1175 1176 return QDF_STATUS_SUCCESS; 1177 fail: 1178 dp_soc_ppe_srng_free(soc); 1179 return QDF_STATUS_E_NOMEM; 1180 } 1181 1182 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1183 { 1184 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1185 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1186 1187 soc_cfg_ctx = soc->wlan_cfg_ctx; 1188 1189 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1190 return QDF_STATUS_SUCCESS; 1191 1192 if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) { 1193 dp_err("%pK: dp_srng_init failed for reo2ppe", soc); 1194 goto fail; 1195 } 1196 1197 wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1198 be_soc->reo2ppe_ring.alloc_size, 1199 soc->ctrl_psoc, 1200 WLAN_MD_DP_SRNG_REO2PPE, 1201 "reo2ppe_ring"); 1202 1203 if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) { 1204 dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc); 1205 goto fail; 1206 } 1207 1208 wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1209 be_soc->ppe2tcl_ring.alloc_size, 1210 soc->ctrl_psoc, 1211 WLAN_MD_DP_SRNG_PPE2TCL, 1212 "ppe2tcl_ring"); 1213 1214 if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) { 1215 dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc); 1216 goto fail; 1217 } 1218 1219 wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned, 1220 be_soc->ppe_release_ring.alloc_size, 1221 soc->ctrl_psoc, 1222 WLAN_MD_DP_SRNG_PPE_RELEASE, 1223 "ppe_release_ring"); 1224 1225 return QDF_STATUS_SUCCESS; 1226 fail: 1227 dp_soc_ppe_srng_deinit(soc); 1228 return QDF_STATUS_E_NOMEM; 1229 } 1230 #else 1231 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1232 { 1233 } 1234 1235 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1236 { 1237 } 1238 1239 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1240 { 1241 return QDF_STATUS_SUCCESS; 1242 } 1243 1244 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1245 { 1246 return QDF_STATUS_SUCCESS; 1247 } 1248 #endif 1249 1250 static void dp_soc_srng_deinit_be(struct dp_soc *soc) 1251 { 1252 uint32_t i; 1253 1254 dp_soc_ppe_srng_deinit(soc); 1255 1256 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1257 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1258 dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i], 1259 RXDMA_BUF, 0); 1260 } 1261 } 1262 } 1263 1264 static void dp_soc_srng_free_be(struct dp_soc *soc) 1265 { 1266 uint32_t i; 1267 1268 dp_soc_ppe_srng_free(soc); 1269 1270 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1271 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) 1272 dp_srng_free(soc, &soc->rx_refill_buf_ring[i]); 1273 } 1274 } 1275 1276 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc) 1277 { 1278 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1279 uint32_t ring_size; 1280 uint32_t i; 1281 1282 soc_cfg_ctx = soc->wlan_cfg_ctx; 1283 1284 ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx); 1285 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1286 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1287 if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i], 1288 RXDMA_BUF, ring_size, 0)) { 1289 dp_err("%pK: dp_srng_alloc failed refill ring", 1290 soc); 1291 goto fail; 1292 } 1293 } 1294 } 1295 1296 if (dp_soc_ppe_srng_alloc(soc)) { 1297 dp_err("%pK: ppe rings alloc failed", 1298 soc); 1299 goto fail; 1300 } 1301 1302 return QDF_STATUS_SUCCESS; 1303 fail: 1304 dp_soc_srng_free_be(soc); 1305 return QDF_STATUS_E_NOMEM; 1306 } 1307 1308 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc) 1309 { 1310 int i = 0; 1311 1312 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1313 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1314 if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i], 1315 RXDMA_BUF, 0, 0)) { 1316 dp_err("%pK: dp_srng_init failed refill ring", 1317 soc); 1318 goto fail; 1319 } 1320 } 1321 } 1322 1323 if (dp_soc_ppe_srng_init(soc)) { 1324 dp_err("%pK: ppe rings init failed", 1325 soc); 1326 goto fail; 1327 } 1328 1329 return QDF_STATUS_SUCCESS; 1330 fail: 1331 dp_soc_srng_deinit_be(soc); 1332 return QDF_STATUS_E_NOMEM; 1333 } 1334 1335 #ifdef WLAN_FEATURE_11BE_MLO 1336 static inline unsigned 1337 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj, 1338 union dp_align_mac_addr *mac_addr) 1339 { 1340 uint32_t index; 1341 1342 index = 1343 mac_addr->align2.bytes_ab ^ 1344 mac_addr->align2.bytes_cd ^ 1345 mac_addr->align2.bytes_ef; 1346 1347 index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits; 1348 index &= mld_hash_obj->mld_peer_hash.mask; 1349 1350 return index; 1351 } 1352 1353 QDF_STATUS 1354 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj, 1355 int hash_elems) 1356 { 1357 int i, log2; 1358 1359 if (!mld_hash_obj) 1360 return QDF_STATUS_E_FAILURE; 1361 1362 hash_elems *= DP_PEER_HASH_LOAD_MULT; 1363 hash_elems >>= DP_PEER_HASH_LOAD_SHIFT; 1364 log2 = dp_log2_ceil(hash_elems); 1365 hash_elems = 1 << log2; 1366 1367 mld_hash_obj->mld_peer_hash.mask = hash_elems - 1; 1368 mld_hash_obj->mld_peer_hash.idx_bits = log2; 1369 /* allocate an array of TAILQ peer object lists */ 1370 mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc( 1371 hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer))); 1372 if (!mld_hash_obj->mld_peer_hash.bins) 1373 return QDF_STATUS_E_NOMEM; 1374 1375 for (i = 0; i < hash_elems; i++) 1376 TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]); 1377 1378 qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock); 1379 1380 return QDF_STATUS_SUCCESS; 1381 } 1382 1383 void 1384 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj) 1385 { 1386 if (!mld_hash_obj) 1387 return; 1388 1389 if (mld_hash_obj->mld_peer_hash.bins) { 1390 qdf_mem_free(mld_hash_obj->mld_peer_hash.bins); 1391 mld_hash_obj->mld_peer_hash.bins = NULL; 1392 qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock); 1393 } 1394 } 1395 1396 #ifdef WLAN_MLO_MULTI_CHIP 1397 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1398 { 1399 /* In case of MULTI chip MLO peer hash table when MLO global object 1400 * is created, avoid from SOC attach path 1401 */ 1402 return QDF_STATUS_SUCCESS; 1403 } 1404 1405 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1406 { 1407 } 1408 #else 1409 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1410 { 1411 dp_mld_peer_hash_obj_t mld_hash_obj; 1412 1413 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1414 1415 if (!mld_hash_obj) 1416 return QDF_STATUS_E_FAILURE; 1417 1418 return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers); 1419 } 1420 1421 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1422 { 1423 dp_mld_peer_hash_obj_t mld_hash_obj; 1424 1425 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1426 1427 if (!mld_hash_obj) 1428 return; 1429 1430 return dp_mlo_peer_find_hash_detach_be(mld_hash_obj); 1431 } 1432 #endif 1433 1434 static struct dp_peer * 1435 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc, 1436 uint8_t *peer_mac_addr, 1437 int mac_addr_is_aligned, 1438 enum dp_mod_id mod_id, 1439 uint8_t vdev_id) 1440 { 1441 union dp_align_mac_addr local_mac_addr_aligned, *mac_addr; 1442 uint32_t index; 1443 struct dp_peer *peer; 1444 struct dp_vdev *vdev; 1445 dp_mld_peer_hash_obj_t mld_hash_obj; 1446 1447 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1448 if (!mld_hash_obj) 1449 return NULL; 1450 1451 if (!mld_hash_obj->mld_peer_hash.bins) 1452 return NULL; 1453 1454 if (mac_addr_is_aligned) { 1455 mac_addr = (union dp_align_mac_addr *)peer_mac_addr; 1456 } else { 1457 qdf_mem_copy( 1458 &local_mac_addr_aligned.raw[0], 1459 peer_mac_addr, QDF_MAC_ADDR_SIZE); 1460 mac_addr = &local_mac_addr_aligned; 1461 } 1462 1463 if (vdev_id != DP_VDEV_ALL) { 1464 vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id); 1465 if (!vdev) { 1466 dp_err("vdev is null\n"); 1467 return NULL; 1468 } 1469 } else { 1470 vdev = NULL; 1471 } 1472 /* search mld peer table if no link peer for given mac address */ 1473 index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr); 1474 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1475 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1476 hash_list_elem) { 1477 if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) { 1478 if ((vdev_id == DP_VDEV_ALL) || ( 1479 dp_peer_find_mac_addr_cmp( 1480 &peer->vdev->mld_mac_addr, 1481 &vdev->mld_mac_addr) == 0)) { 1482 /* take peer reference before returning */ 1483 if (dp_peer_get_ref(NULL, peer, mod_id) != 1484 QDF_STATUS_SUCCESS) 1485 peer = NULL; 1486 1487 if (vdev) 1488 dp_vdev_unref_delete(soc, vdev, mod_id); 1489 1490 qdf_spin_unlock_bh( 1491 &mld_hash_obj->mld_peer_hash_lock); 1492 return peer; 1493 } 1494 } 1495 } 1496 1497 if (vdev) 1498 dp_vdev_unref_delete(soc, vdev, mod_id); 1499 1500 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1501 1502 return NULL; /* failure */ 1503 } 1504 1505 static void 1506 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer) 1507 { 1508 uint32_t index; 1509 struct dp_peer *tmppeer = NULL; 1510 int found = 0; 1511 dp_mld_peer_hash_obj_t mld_hash_obj; 1512 1513 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1514 1515 if (!mld_hash_obj) 1516 return; 1517 1518 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1519 QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index])); 1520 1521 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1522 TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index], 1523 hash_list_elem) { 1524 if (tmppeer == peer) { 1525 found = 1; 1526 break; 1527 } 1528 } 1529 QDF_ASSERT(found); 1530 TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1531 hash_list_elem); 1532 1533 dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG); 1534 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1535 } 1536 1537 static void 1538 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer) 1539 { 1540 uint32_t index; 1541 dp_mld_peer_hash_obj_t mld_hash_obj; 1542 1543 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1544 1545 if (!mld_hash_obj) 1546 return; 1547 1548 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1549 1550 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1551 1552 if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer, 1553 DP_MOD_ID_CONFIG))) { 1554 dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT, 1555 QDF_MAC_ADDR_REF(peer->mac_addr.raw)); 1556 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1557 return; 1558 } 1559 TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1560 hash_list_elem); 1561 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1562 } 1563 #endif 1564 1565 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \ 1566 defined(WLAN_MCAST_MLO) 1567 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1568 struct dp_vdev_be *be_vdev, 1569 cdp_config_param_type val) 1570 { 1571 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc( 1572 be_vdev->vdev.pdev->soc); 1573 hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc; 1574 uint8_t vdev_id = be_vdev->vdev.vdev_id; 1575 1576 be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev; 1577 1578 if (be_vdev->mcast_primary) { 1579 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1580 HAL_TX_MCAST_CTRL_NO_SPECIAL); 1581 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128, 1582 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1583 dp_mcast_mlo_iter_ptnr_soc(be_soc, 1584 dp_tx_mcast_mlo_reinject_routing_set, 1585 (void *)&be_vdev->mcast_primary); 1586 } else { 1587 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1588 HAL_TX_MCAST_CTRL_DROP); 1589 } 1590 } 1591 #else 1592 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1593 struct dp_vdev_be *be_vdev, 1594 cdp_config_param_type val) 1595 { 1596 } 1597 #endif 1598 1599 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 1600 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1601 uint8_t tx_ring_id, 1602 uint8_t bm_id) 1603 { 1604 hal_tx_config_rbm_mapping_be(soc->hal_soc, 1605 soc->tcl_data_ring[tx_ring_id].hal_srng, 1606 bm_id); 1607 } 1608 #else 1609 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1610 uint8_t tx_ring_id, 1611 uint8_t bm_id) 1612 { 1613 } 1614 #endif 1615 1616 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc, 1617 struct dp_vdev *vdev, 1618 enum cdp_vdev_param_type param, 1619 cdp_config_param_type val) 1620 { 1621 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1622 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1623 1624 switch (param) { 1625 case CDP_TX_ENCAP_TYPE: 1626 case CDP_UPDATE_DSCP_TO_TID_MAP: 1627 case CDP_UPDATE_TDLS_FLAGS: 1628 dp_tx_update_bank_profile(be_soc, be_vdev); 1629 break; 1630 case CDP_ENABLE_CIPHER: 1631 if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) 1632 dp_tx_update_bank_profile(be_soc, be_vdev); 1633 break; 1634 case CDP_SET_MCAST_VDEV: 1635 dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val); 1636 break; 1637 default: 1638 dp_warn("invalid param %d", param); 1639 break; 1640 } 1641 1642 return QDF_STATUS_SUCCESS; 1643 } 1644 1645 #ifdef WLAN_FEATURE_11BE_MLO 1646 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 1647 static inline void 1648 dp_soc_max_peer_id_set(struct dp_soc *soc) 1649 { 1650 soc->peer_id_shift = dp_log2_ceil(soc->max_peers); 1651 soc->peer_id_mask = (1 << soc->peer_id_shift) - 1; 1652 /* 1653 * Double the peers since we use ML indication bit 1654 * alongwith peer_id to find peers. 1655 */ 1656 soc->max_peer_id = 1 << (soc->peer_id_shift + 1); 1657 } 1658 #else 1659 static inline void 1660 dp_soc_max_peer_id_set(struct dp_soc *soc) 1661 { 1662 soc->max_peer_id = 1663 (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1; 1664 } 1665 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */ 1666 #else 1667 static inline void 1668 dp_soc_max_peer_id_set(struct dp_soc *soc) 1669 { 1670 soc->max_peer_id = soc->max_peers; 1671 } 1672 #endif /* WLAN_FEATURE_11BE_MLO */ 1673 1674 static void dp_peer_map_detach_be(struct dp_soc *soc) 1675 { 1676 } 1677 1678 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc) 1679 { 1680 dp_soc_max_peer_id_set(soc); 1681 1682 return QDF_STATUS_SUCCESS; 1683 } 1684 1685 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc, 1686 uint8_t *dest_mac, 1687 uint8_t vdev_id) 1688 { 1689 struct dp_peer *peer = NULL; 1690 1691 peer = dp_peer_find_hash_find(soc, dest_mac, 0, 1692 vdev_id, DP_MOD_ID_SAWF); 1693 if (!peer) { 1694 dp_err("Invalid peer"); 1695 return NULL; 1696 } 1697 1698 return peer; 1699 } 1700 1701 #ifdef WLAN_FEATURE_11BE_MLO 1702 #ifdef WLAN_MCAST_MLO 1703 static inline void 1704 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1705 { 1706 arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be; 1707 arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler; 1708 } 1709 #else /* WLAN_MCAST_MLO */ 1710 static inline void 1711 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1712 { 1713 } 1714 #endif /* WLAN_MCAST_MLO */ 1715 1716 static inline void 1717 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1718 { 1719 dp_initialize_arch_ops_be_mcast_mlo(arch_ops); 1720 arch_ops->mlo_peer_find_hash_detach = 1721 dp_mlo_peer_find_hash_detach_wrapper; 1722 arch_ops->mlo_peer_find_hash_attach = 1723 dp_mlo_peer_find_hash_attach_wrapper; 1724 arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be; 1725 arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be; 1726 arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be; 1727 } 1728 #else /* WLAN_FEATURE_11BE_MLO */ 1729 static inline void 1730 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1731 { 1732 } 1733 #endif /* WLAN_FEATURE_11BE_MLO */ 1734 1735 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops) 1736 { 1737 #ifndef QCA_HOST_MODE_WIFI_DISABLED 1738 arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be; 1739 arch_ops->dp_rx_process = dp_rx_process_be; 1740 arch_ops->tx_comp_get_params_from_hal_desc = 1741 dp_tx_comp_get_params_from_hal_desc_be; 1742 arch_ops->dp_tx_process_htt_completion = 1743 dp_tx_process_htt_completion_be; 1744 arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be; 1745 arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be; 1746 arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be; 1747 arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be; 1748 arch_ops->dp_wbm_get_rx_desc_from_hal_desc = 1749 dp_wbm_get_rx_desc_from_hal_desc_be; 1750 #endif 1751 arch_ops->txrx_get_context_size = dp_get_context_size_be; 1752 arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be; 1753 arch_ops->dp_rx_desc_cookie_2_va = 1754 dp_rx_desc_cookie_2_va_be; 1755 arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be; 1756 1757 arch_ops->txrx_soc_attach = dp_soc_attach_be; 1758 arch_ops->txrx_soc_detach = dp_soc_detach_be; 1759 arch_ops->txrx_soc_init = dp_soc_init_be; 1760 arch_ops->txrx_soc_deinit = dp_soc_deinit_be; 1761 arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be; 1762 arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be; 1763 arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be; 1764 arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be; 1765 arch_ops->txrx_pdev_attach = dp_pdev_attach_be; 1766 arch_ops->txrx_pdev_detach = dp_pdev_detach_be; 1767 arch_ops->txrx_vdev_attach = dp_vdev_attach_be; 1768 arch_ops->txrx_vdev_detach = dp_vdev_detach_be; 1769 arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be; 1770 arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be; 1771 arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be; 1772 arch_ops->dp_rx_peer_metadata_peer_id_get = 1773 dp_rx_peer_metadata_peer_id_get_be; 1774 arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be; 1775 arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be; 1776 arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be; 1777 dp_initialize_arch_ops_be_mlo(arch_ops); 1778 arch_ops->dp_peer_rx_reorder_queue_setup = 1779 dp_peer_rx_reorder_queue_setup_be; 1780 arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be; 1781 arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be; 1782 arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be; 1783 dp_init_near_full_arch_ops_be(arch_ops); 1784 arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be; 1785 } 1786