1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <wlan_utility.h> 21 #include <dp_internal.h> 22 #include <dp_htt.h> 23 #include "dp_be.h" 24 #include "dp_be_tx.h" 25 #include "dp_be_rx.h" 26 #ifdef WIFI_MONITOR_SUPPORT 27 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT) 28 #include "dp_mon_2.0.h" 29 #endif 30 #include "dp_mon.h" 31 #endif 32 #include <hal_be_api.h> 33 #ifdef WLAN_SUPPORT_PPEDS 34 #include "be/dp_ppeds.h" 35 #include <ppe_vp_public.h> 36 #include <ppe_drv_sc.h> 37 #endif 38 39 /* Generic AST entry aging timer value */ 40 #define DP_AST_AGING_TIMER_DEFAULT_MS 5000 41 42 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 43 #define DP_TX_VDEV_ID_CHECK_ENABLE 0 44 45 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 46 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 47 {1, 4, HAL_BE_WBM_SW4_BM_ID, 0}, 48 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 49 #ifdef QCA_WIFI_KIWI_V2 50 {3, 5, HAL_BE_WBM_SW5_BM_ID, 0}, 51 {4, 6, HAL_BE_WBM_SW6_BM_ID, 0} 52 #else 53 {3, 6, HAL_BE_WBM_SW5_BM_ID, 0}, 54 {4, 7, HAL_BE_WBM_SW6_BM_ID, 0} 55 #endif 56 }; 57 #else 58 #define DP_TX_VDEV_ID_CHECK_ENABLE 1 59 60 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 61 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 62 {1, 1, HAL_BE_WBM_SW1_BM_ID, 0}, 63 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 64 {3, 3, HAL_BE_WBM_SW3_BM_ID, 0}, 65 {4, 4, HAL_BE_WBM_SW4_BM_ID, 0} 66 }; 67 #endif 68 69 #ifdef WLAN_SUPPORT_PPEDS 70 static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = { 71 .ppeds_entry_attach = dp_ppeds_attach_vdev_be, 72 .ppeds_entry_detach = dp_ppeds_detach_vdev_be, 73 .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be, 74 .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be, 75 .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be, 76 .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be, 77 }; 78 79 static void dp_ppeds_rings_status(struct dp_soc *soc) 80 { 81 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 82 83 dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE); 84 dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL); 85 dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring, 86 WBM2SW_RELEASE); 87 } 88 89 static void dp_ppeds_inuse_desc(struct dp_soc *soc) 90 { 91 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 92 93 DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u", 94 be_soc->ppeds_tx_desc.num_allocated, 95 be_soc->ppeds_tx_desc.num_free); 96 } 97 #endif 98 99 static void dp_soc_cfg_attach_be(struct dp_soc *soc) 100 { 101 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx; 102 103 wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM); 104 105 soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array; 106 107 /* this is used only when dmac mode is enabled */ 108 soc->num_rx_refill_buf_rings = 1; 109 110 soc->wlan_cfg_ctx->notify_frame_support = 111 DP_MARK_NOTIFY_FRAME_SUPPORT; 112 } 113 114 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type) 115 { 116 switch (context_type) { 117 case DP_CONTEXT_TYPE_SOC: 118 return sizeof(struct dp_soc_be); 119 case DP_CONTEXT_TYPE_PDEV: 120 return sizeof(struct dp_pdev_be); 121 case DP_CONTEXT_TYPE_VDEV: 122 return sizeof(struct dp_vdev_be); 123 case DP_CONTEXT_TYPE_PEER: 124 return sizeof(struct dp_peer_be); 125 default: 126 return 0; 127 } 128 } 129 130 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION 131 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 132 /** 133 * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement 134 * per wbm2sw ring 135 * 136 * @cc_cfg: HAL HW cookie conversion configuration structure pointer 137 * 138 * Return: None 139 */ 140 static inline 141 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 142 { 143 cc_cfg->wbm2sw6_cc_en = 1; 144 cc_cfg->wbm2sw5_cc_en = 1; 145 cc_cfg->wbm2sw4_cc_en = 1; 146 cc_cfg->wbm2sw3_cc_en = 1; 147 cc_cfg->wbm2sw2_cc_en = 1; 148 /* disable wbm2sw1 hw cc as it's for FW */ 149 cc_cfg->wbm2sw1_cc_en = 0; 150 cc_cfg->wbm2sw0_cc_en = 1; 151 cc_cfg->wbm2fw_cc_en = 0; 152 } 153 #else 154 static inline 155 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 156 { 157 cc_cfg->wbm2sw6_cc_en = 1; 158 cc_cfg->wbm2sw5_cc_en = 1; 159 cc_cfg->wbm2sw4_cc_en = 1; 160 cc_cfg->wbm2sw3_cc_en = 1; 161 cc_cfg->wbm2sw2_cc_en = 1; 162 cc_cfg->wbm2sw1_cc_en = 1; 163 cc_cfg->wbm2sw0_cc_en = 1; 164 cc_cfg->wbm2fw_cc_en = 0; 165 } 166 #endif 167 168 #if defined(WLAN_SUPPORT_RX_FISA) 169 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 170 { 171 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 172 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 173 /* get CMEM for cookie conversion */ 174 if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) { 175 dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size); 176 return QDF_STATUS_E_NOMEM; 177 } 178 179 soc->fst_cmem_size = DP_CMEM_FST_SIZE; 180 181 soc->fst_cmem_base = soc->cmem_base + 182 (soc->cmem_total_size - soc->cmem_avail_size); 183 soc->cmem_avail_size -= soc->fst_cmem_size; 184 185 dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx", 186 soc->fst_cmem_base, soc->fst_cmem_size); 187 188 return QDF_STATUS_SUCCESS; 189 } 190 #else /* !WLAN_SUPPORT_RX_FISA */ 191 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 192 { 193 return QDF_STATUS_SUCCESS; 194 } 195 #endif 196 197 /** 198 * dp_cc_reg_cfg_init() - initialize and configure HW cookie 199 * conversion register 200 * 201 * @soc: SOC handle 202 * @is_4k_align: page address 4k aligned 203 * 204 * Return: None 205 */ 206 static void dp_cc_reg_cfg_init(struct dp_soc *soc, 207 bool is_4k_align) 208 { 209 struct hal_hw_cc_config cc_cfg = { 0 }; 210 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 211 212 if (soc->cdp_soc.ol_ops->get_con_mode && 213 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE) 214 return; 215 216 if (!soc->wlan_cfg_ctx->hw_cc_enabled) { 217 dp_info("INI skip HW CC register setting"); 218 return; 219 } 220 221 cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base; 222 cc_cfg.cc_global_en = true; 223 cc_cfg.page_4k_align = is_4k_align; 224 cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB; 225 cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB; 226 /* 36th bit should be 1 then HW know this is CMEM address */ 227 cc_cfg.lut_base_addr_39_32 = 0x10; 228 229 cc_cfg.error_path_cookie_conv_en = true; 230 cc_cfg.release_path_cookie_conv_en = true; 231 dp_cc_wbm_sw_en_cfg(&cc_cfg); 232 233 hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg); 234 } 235 236 /** 237 * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing 238 * @hal_soc_hdl: HAL SOC handle 239 * @offset: CMEM address 240 * @value: value to write 241 * 242 * Return: None. 243 */ 244 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 245 uint32_t offset, 246 uint32_t value) 247 { 248 hal_cmem_write(hal_soc_hdl, offset, value); 249 } 250 251 /** 252 * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for 253 * HW cookie conversion 254 * 255 * @soc: SOC handle 256 * 257 * Return: 0 in case of success, else error value 258 */ 259 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 260 { 261 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 262 263 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 264 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 265 /* get CMEM for cookie conversion */ 266 if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) { 267 dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size); 268 return QDF_STATUS_E_RESOURCES; 269 } 270 be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base + 271 DP_CC_MEM_OFFSET_IN_CMEM); 272 273 soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE; 274 275 dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx", 276 be_soc->cc_cmem_base, soc->cmem_avail_size); 277 return QDF_STATUS_SUCCESS; 278 } 279 280 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 281 uint8_t for_feature) 282 { 283 QDF_STATUS status = QDF_STATUS_E_NOMEM; 284 285 switch (for_feature) { 286 case COOKIE_CONVERSION: 287 status = dp_hw_cc_cmem_addr_init(soc); 288 break; 289 case FISA_FST: 290 status = dp_fisa_fst_cmem_addr_init(soc); 291 break; 292 default: 293 dp_err("Invalid CMEM request"); 294 } 295 296 return status; 297 } 298 299 #else 300 301 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc, 302 bool is_4k_align) {} 303 304 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 305 uint32_t offset, 306 uint32_t value) 307 { } 308 309 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 310 { 311 return QDF_STATUS_SUCCESS; 312 } 313 314 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 315 uint8_t for_feature) 316 { 317 return QDF_STATUS_SUCCESS; 318 } 319 320 #endif 321 322 QDF_STATUS 323 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc, 324 struct dp_hw_cookie_conversion_t *cc_ctx, 325 uint32_t num_descs, 326 enum dp_desc_type desc_type, 327 uint8_t desc_pool_id) 328 { 329 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 330 uint32_t num_spt_pages, i = 0; 331 struct dp_spt_page_desc *spt_desc; 332 struct qdf_mem_dma_page_t *dma_page; 333 uint8_t chip_id; 334 335 /* estimate how many SPT DDR pages needed */ 336 num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES; 337 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 338 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 339 dp_info("num_spt_pages needed %d", num_spt_pages); 340 341 dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE, 342 &cc_ctx->page_pool, qdf_page_size, 343 num_spt_pages, 0, false); 344 if (!cc_ctx->page_pool.dma_pages) { 345 dp_err("spt ddr pages allocation failed"); 346 return QDF_STATUS_E_RESOURCES; 347 } 348 cc_ctx->page_desc_base = qdf_mem_malloc( 349 num_spt_pages * sizeof(struct dp_spt_page_desc)); 350 if (!cc_ctx->page_desc_base) { 351 dp_err("spt page descs allocation failed"); 352 goto fail_0; 353 } 354 355 chip_id = dp_mlo_get_chip_id(soc); 356 cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id, 357 desc_type); 358 359 /* initial page desc */ 360 spt_desc = cc_ctx->page_desc_base; 361 dma_page = cc_ctx->page_pool.dma_pages; 362 while (i < num_spt_pages) { 363 /* check if page address 4K aligned */ 364 if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) { 365 dp_err("non-4k aligned pages addr %pK", 366 (void *)dma_page[i].page_p_addr); 367 goto fail_1; 368 } 369 370 spt_desc[i].page_v_addr = 371 dma_page[i].page_v_addr_start; 372 spt_desc[i].page_p_addr = 373 dma_page[i].page_p_addr; 374 i++; 375 } 376 377 cc_ctx->total_page_num = num_spt_pages; 378 qdf_spinlock_create(&cc_ctx->cc_lock); 379 380 return QDF_STATUS_SUCCESS; 381 fail_1: 382 qdf_mem_free(cc_ctx->page_desc_base); 383 fail_0: 384 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 385 &cc_ctx->page_pool, 0, false); 386 387 return QDF_STATUS_E_FAILURE; 388 } 389 390 QDF_STATUS 391 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc, 392 struct dp_hw_cookie_conversion_t *cc_ctx) 393 { 394 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 395 396 qdf_mem_free(cc_ctx->page_desc_base); 397 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 398 &cc_ctx->page_pool, 0, false); 399 qdf_spinlock_destroy(&cc_ctx->cc_lock); 400 401 return QDF_STATUS_SUCCESS; 402 } 403 404 QDF_STATUS 405 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc, 406 struct dp_hw_cookie_conversion_t *cc_ctx) 407 { 408 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 409 uint32_t i = 0; 410 struct dp_spt_page_desc *spt_desc; 411 uint32_t ppt_index; 412 uint32_t ppt_id_start; 413 414 if (!cc_ctx->total_page_num) { 415 dp_err("total page num is 0"); 416 return QDF_STATUS_E_INVAL; 417 } 418 419 ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset); 420 spt_desc = cc_ctx->page_desc_base; 421 while (i < cc_ctx->total_page_num) { 422 /* write page PA to CMEM */ 423 dp_hw_cc_cmem_write(soc->hal_soc, 424 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 425 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 426 (spt_desc[i].page_p_addr >> 427 DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED)); 428 429 ppt_index = ppt_id_start + i; 430 431 if (ppt_index >= DP_CC_PPT_MAX_ENTRIES) 432 qdf_assert_always(0); 433 434 spt_desc[i].ppt_index = ppt_index; 435 436 be_soc->page_desc_base[ppt_index].page_v_addr = 437 spt_desc[i].page_v_addr; 438 i++; 439 } 440 return QDF_STATUS_SUCCESS; 441 } 442 443 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 444 QDF_STATUS 445 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 446 struct dp_hw_cookie_conversion_t *cc_ctx) 447 { 448 uint32_t ppt_index; 449 struct dp_spt_page_desc *spt_desc; 450 int i = 0; 451 452 spt_desc = cc_ctx->page_desc_base; 453 while (i < cc_ctx->total_page_num) { 454 ppt_index = spt_desc[i].ppt_index; 455 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 456 i++; 457 } 458 return QDF_STATUS_SUCCESS; 459 } 460 #else 461 QDF_STATUS 462 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 463 struct dp_hw_cookie_conversion_t *cc_ctx) 464 { 465 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 466 uint32_t ppt_index; 467 struct dp_spt_page_desc *spt_desc; 468 int i = 0; 469 470 spt_desc = cc_ctx->page_desc_base; 471 while (i < cc_ctx->total_page_num) { 472 /* reset PA in CMEM to NULL */ 473 dp_hw_cc_cmem_write(soc->hal_soc, 474 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 475 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 476 0); 477 478 ppt_index = spt_desc[i].ppt_index; 479 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 480 i++; 481 } 482 return QDF_STATUS_SUCCESS; 483 } 484 #endif 485 486 #ifdef WLAN_SUPPORT_PPEDS 487 static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc) 488 { 489 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 490 struct cdp_ops *cdp_ops = soc->cdp_soc.ops; 491 492 /* 493 * Check if PPE DS is enabled. 494 */ 495 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx)) 496 return QDF_STATUS_SUCCESS; 497 498 if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS) 499 return QDF_STATUS_SUCCESS; 500 501 cdp_ops->ppeds_ops = &dp_ops_ppeds_be; 502 503 return QDF_STATUS_SUCCESS; 504 } 505 506 static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc) 507 { 508 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 509 struct cdp_ops *cdp_ops = soc->cdp_soc.ops; 510 511 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx)) 512 return QDF_STATUS_E_FAILURE; 513 514 dp_ppeds_detach_soc_be(be_soc); 515 516 cdp_ops->ppeds_ops = NULL; 517 518 return QDF_STATUS_SUCCESS; 519 } 520 521 static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc, 522 struct dp_peer_be *be_peer, 523 uint8_t vdev_id, 524 uint16_t src_info) 525 { 526 uint16_t service_code; 527 uint8_t priority_valid; 528 uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE; 529 uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED; 530 QDF_STATUS status = QDF_STATUS_SUCCESS; 531 struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx; 532 struct dp_vdev_be *be_vdev; 533 534 be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev); 535 536 /* 537 * Program service code bypass to avoid L2 new mac address 538 * learning exception when fdb learning is disabled. 539 */ 540 service_code = PPE_DRV_SC_SPF_BYPASS; 541 priority_valid = be_peer->priority_valid; 542 543 /* 544 * if FST is enabled then let flow rule take the decision of 545 * routing the pkt to DS or host 546 */ 547 if (wlan_cfg_is_rx_flow_tag_enabled(cfg)) 548 use_ppe_ds = 0; 549 550 if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) { 551 status = 552 soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing 553 (soc->ctrl_psoc, 554 be_peer->peer.mac_addr.raw, 555 service_code, priority_valid, 556 src_info, vdev_id, use_ppe_ds, 557 peer_routing_enabled); 558 if (status != QDF_STATUS_SUCCESS) { 559 dp_err("vdev_id: %d, PPE peer routing mac:" 560 QDF_MAC_ADDR_FMT, vdev_id, 561 QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw)); 562 563 return QDF_STATUS_E_FAILURE; 564 } 565 } 566 567 return QDF_STATUS_SUCCESS; 568 } 569 570 #ifdef WLAN_FEATURE_11BE_MLO 571 static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, 572 struct dp_peer *peer, 573 struct dp_vdev_be *be_vdev) 574 { 575 struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile; 576 uint16_t src_info = ppe_vp_profile->vp_num; 577 uint8_t vdev_id = be_vdev->vdev.vdev_id; 578 struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer); 579 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 580 581 if (!be_peer) { 582 dp_err("BE peer is null"); 583 return QDF_STATUS_E_NULL_VALUE; 584 } 585 586 if (IS_DP_LEGACY_PEER(peer)) { 587 qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer, 588 vdev_id, src_info); 589 } else if (IS_MLO_DP_MLD_PEER(peer)) { 590 int i; 591 struct dp_peer *link_peer = NULL; 592 struct dp_mld_link_peers link_peers_info; 593 594 /* get link peers with reference */ 595 dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info, 596 DP_MOD_ID_DS); 597 598 for (i = 0; i < link_peers_info.num_links; i++) { 599 link_peer = link_peers_info.link_peers[i]; 600 be_peer = dp_get_be_peer_from_dp_peer(link_peer); 601 if (!be_peer) { 602 dp_err("BE peer is null"); 603 continue; 604 } 605 606 be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev); 607 if (!be_vdev) { 608 dp_err("BE vap is null for peer id %d ", 609 link_peer->peer_id); 610 continue; 611 } 612 613 vdev_id = be_vdev->vdev.vdev_id; 614 qdf_status = dp_peer_ppeds_default_route_be(soc, 615 be_peer, 616 vdev_id, 617 src_info); 618 } 619 620 dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS); 621 } else { 622 struct dp_peer *mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer); 623 624 if (!mld_peer) 625 return qdf_status; 626 627 be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev); 628 if (!be_vdev) { 629 dp_err("BE vap is null"); 630 return QDF_STATUS_E_NULL_VALUE; 631 } 632 633 ppe_vp_profile = &be_vdev->ppe_vp_profile; 634 src_info = ppe_vp_profile->vp_num; 635 qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer, 636 vdev_id, src_info); 637 } 638 639 return qdf_status; 640 } 641 #else 642 static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, 643 struct dp_peer *peer, 644 struct dp_vdev_be *be_vdev) 645 { 646 struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile; 647 struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer); 648 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 649 650 if (!be_peer) { 651 dp_err("BE peer is null"); 652 return QDF_STATUS_E_NULL_VALUE; 653 } 654 655 qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer, 656 be_vdev->vdev.vdev_id, 657 ppe_vp_profile->vp_num); 658 659 return qdf_status; 660 } 661 #endif 662 #else 663 static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc) 664 { 665 return QDF_STATUS_SUCCESS; 666 } 667 668 static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc) 669 { 670 return QDF_STATUS_SUCCESS; 671 } 672 673 static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc) 674 { 675 return QDF_STATUS_SUCCESS; 676 } 677 678 static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc) 679 { 680 return QDF_STATUS_SUCCESS; 681 } 682 683 static inline 684 QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer, 685 struct dp_vdev_be *be_vdev) 686 { 687 return QDF_STATUS_SUCCESS; 688 } 689 #endif /* WLAN_SUPPORT_PPEDS */ 690 691 void dp_reo_shared_qaddr_detach(struct dp_soc *soc) 692 { 693 qdf_mem_free_consistent(soc->osdev, soc->osdev->dev, 694 REO_QUEUE_REF_ML_TABLE_SIZE, 695 soc->reo_qref.mlo_reo_qref_table_vaddr, 696 soc->reo_qref.mlo_reo_qref_table_paddr, 0); 697 qdf_mem_free_consistent(soc->osdev, soc->osdev->dev, 698 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 699 soc->reo_qref.non_mlo_reo_qref_table_vaddr, 700 soc->reo_qref.non_mlo_reo_qref_table_paddr, 0); 701 } 702 703 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc) 704 { 705 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 706 int i = 0; 707 708 dp_soc_ppeds_detach_be(soc); 709 dp_reo_shared_qaddr_detach(soc); 710 711 for (i = 0; i < MAX_TXDESC_POOLS; i++) 712 dp_hw_cookie_conversion_detach(be_soc, 713 &be_soc->tx_cc_ctx[i]); 714 715 for (i = 0; i < MAX_RXDESC_POOLS; i++) 716 dp_hw_cookie_conversion_detach(be_soc, 717 &be_soc->rx_cc_ctx[i]); 718 719 qdf_mem_free(be_soc->page_desc_base); 720 be_soc->page_desc_base = NULL; 721 722 return QDF_STATUS_SUCCESS; 723 } 724 725 #ifdef WLAN_MLO_MULTI_CHIP 726 #ifdef WLAN_MCAST_MLO 727 static inline void 728 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 729 { 730 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 731 732 be_vdev->mcast_primary = false; 733 be_vdev->seq_num = 0; 734 735 hal_tx_mcast_mlo_reinject_routing_set( 736 soc->hal_soc, 737 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY); 738 739 if (vdev->opmode == wlan_op_mode_ap) { 740 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 741 vdev->vdev_id, 742 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 743 } 744 } 745 746 static inline void 747 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 748 { 749 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 750 751 be_vdev->seq_num = 0; 752 be_vdev->mcast_primary = false; 753 vdev->mlo_vdev = false; 754 } 755 756 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst) 757 { 758 dp_mlo_set_rx_fst(soc, fst); 759 } 760 761 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc) 762 { 763 return dp_mlo_get_rx_fst(soc); 764 } 765 766 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc) 767 { 768 return dp_mlo_rx_fst_deref(soc); 769 } 770 771 static void dp_rx_fst_ref_be(struct dp_soc *soc) 772 { 773 dp_mlo_rx_fst_ref(soc); 774 } 775 #else 776 static inline void 777 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 778 { 779 } 780 781 static inline void 782 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 783 { 784 } 785 786 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst) 787 { 788 } 789 790 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc) 791 { 792 return NULL; 793 } 794 795 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc) 796 { 797 return 1; 798 } 799 800 static void dp_rx_fst_ref_be(struct dp_soc *soc) 801 { 802 } 803 #endif 804 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 805 { 806 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 807 808 qdf_mem_set(be_vdev->partner_vdev_list, 809 WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC, 810 CDP_INVALID_VDEV_ID); 811 } 812 813 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 814 struct cdp_lro_hash_config *lro_hash) 815 { 816 dp_mlo_get_rx_hash_key(soc, lro_hash); 817 } 818 #else 819 static inline void 820 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 821 { 822 } 823 824 static inline void 825 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 826 { 827 } 828 829 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 830 { 831 } 832 833 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 834 struct cdp_lro_hash_config *lro_hash) 835 { 836 dp_get_rx_hash_key_bytes(lro_hash); 837 } 838 839 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst) 840 { 841 } 842 843 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc) 844 { 845 return NULL; 846 } 847 848 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc) 849 { 850 return 1; 851 } 852 853 static void dp_rx_fst_ref_be(struct dp_soc *soc) 854 { 855 } 856 #endif 857 858 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc, 859 struct cdp_soc_attach_params *params) 860 { 861 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 862 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 863 uint32_t max_tx_rx_desc_num, num_spt_pages; 864 uint32_t num_entries; 865 int i = 0; 866 867 max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS + 868 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS + 869 WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS; 870 /* estimate how many SPT DDR pages needed */ 871 num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES; 872 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 873 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 874 875 be_soc->page_desc_base = qdf_mem_malloc( 876 DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc)); 877 if (!be_soc->page_desc_base) { 878 dp_err("spt page descs allocation failed"); 879 return QDF_STATUS_E_NOMEM; 880 } 881 882 soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id(); 883 884 qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION); 885 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 886 goto fail; 887 888 dp_soc_mlo_fill_params(soc, params); 889 890 qdf_status = dp_soc_ppeds_attach_be(soc); 891 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 892 goto fail; 893 894 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 895 num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx); 896 qdf_status = 897 dp_hw_cookie_conversion_attach(be_soc, 898 &be_soc->tx_cc_ctx[i], 899 num_entries, 900 DP_TX_DESC_TYPE, i); 901 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 902 goto fail; 903 } 904 905 qdf_status = dp_get_cmem_allocation(soc, FISA_FST); 906 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 907 goto fail; 908 909 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 910 num_entries = 911 wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx); 912 qdf_status = 913 dp_hw_cookie_conversion_attach(be_soc, 914 &be_soc->rx_cc_ctx[i], 915 num_entries, 916 DP_RX_DESC_BUF_TYPE, i); 917 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 918 goto fail; 919 } 920 921 return qdf_status; 922 fail: 923 dp_soc_detach_be(soc); 924 return qdf_status; 925 } 926 927 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc) 928 { 929 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 930 int i = 0; 931 932 dp_tx_deinit_bank_profiles(be_soc); 933 for (i = 0; i < MAX_TXDESC_POOLS; i++) 934 dp_hw_cookie_conversion_deinit(be_soc, 935 &be_soc->tx_cc_ctx[i]); 936 937 for (i = 0; i < MAX_RXDESC_POOLS; i++) 938 dp_hw_cookie_conversion_deinit(be_soc, 939 &be_soc->rx_cc_ctx[i]); 940 941 dp_ppeds_deinit_soc_be(soc); 942 943 return QDF_STATUS_SUCCESS; 944 } 945 946 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc) 947 { 948 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 949 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 950 int i = 0; 951 952 dp_ppeds_init_soc_be(soc); 953 954 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 955 qdf_status = 956 dp_hw_cookie_conversion_init(be_soc, 957 &be_soc->tx_cc_ctx[i]); 958 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 959 goto fail; 960 } 961 962 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 963 qdf_status = 964 dp_hw_cookie_conversion_init(be_soc, 965 &be_soc->rx_cc_ctx[i]); 966 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 967 goto fail; 968 } 969 970 /* route vdev_id mismatch notification via FW completion */ 971 hal_tx_vdev_mismatch_routing_set(soc->hal_soc, 972 HAL_TX_VDEV_MISMATCH_FW_NOTIFY); 973 974 qdf_status = dp_tx_init_bank_profiles(be_soc); 975 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 976 goto fail; 977 978 /* write WBM/REO cookie conversion CFG register */ 979 dp_cc_reg_cfg_init(soc, true); 980 981 return qdf_status; 982 fail: 983 dp_soc_deinit_be(soc); 984 return qdf_status; 985 } 986 987 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev, 988 struct cdp_pdev_attach_params *params) 989 { 990 dp_pdev_mlo_fill_params(pdev, params); 991 992 return QDF_STATUS_SUCCESS; 993 } 994 995 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev) 996 { 997 dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev); 998 999 return QDF_STATUS_SUCCESS; 1000 } 1001 1002 #ifdef INTRA_BSS_FWD_OFFLOAD 1003 static 1004 void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable) 1005 { 1006 soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id, 1007 enable); 1008 } 1009 #else 1010 static 1011 void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable) 1012 { 1013 } 1014 #endif 1015 1016 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev) 1017 { 1018 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1019 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1020 struct dp_pdev *pdev = vdev->pdev; 1021 1022 if (vdev->opmode == wlan_op_mode_monitor) 1023 return QDF_STATUS_SUCCESS; 1024 1025 be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE; 1026 1027 be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev); 1028 vdev->bank_id = be_vdev->bank_id; 1029 1030 if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) { 1031 QDF_BUG(0); 1032 return QDF_STATUS_E_FAULT; 1033 } 1034 1035 if (vdev->opmode == wlan_op_mode_sta) { 1036 if (soc->cdp_soc.ol_ops->set_mec_timer) 1037 soc->cdp_soc.ol_ops->set_mec_timer( 1038 soc->ctrl_psoc, 1039 vdev->vdev_id, 1040 DP_AST_AGING_TIMER_DEFAULT_MS); 1041 1042 if (pdev->isolation) 1043 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 1044 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1045 else 1046 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 1047 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 1048 } else if (vdev->ap_bridge_enabled) { 1049 dp_vdev_set_intra_bss(soc, vdev->vdev_id, true); 1050 } 1051 1052 dp_mlo_mcast_init(soc, vdev); 1053 dp_mlo_init_ptnr_list(vdev); 1054 1055 return QDF_STATUS_SUCCESS; 1056 } 1057 1058 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev) 1059 { 1060 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1061 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1062 1063 if (vdev->opmode == wlan_op_mode_monitor) 1064 return QDF_STATUS_SUCCESS; 1065 1066 if (vdev->opmode == wlan_op_mode_ap) 1067 dp_mlo_mcast_deinit(soc, vdev); 1068 1069 dp_tx_put_bank_profile(be_soc, be_vdev); 1070 dp_clr_mlo_ptnr_list(soc, vdev); 1071 1072 return QDF_STATUS_SUCCESS; 1073 } 1074 1075 #ifdef WLAN_SUPPORT_PPEDS 1076 static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer) 1077 { 1078 struct dp_vdev_be *be_vdev; 1079 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 1080 1081 be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev); 1082 if (!be_vdev) { 1083 qdf_err("BE vap is null"); 1084 return QDF_STATUS_E_NULL_VALUE; 1085 } 1086 1087 /* 1088 * Check if PPE DS routing is enabled on the associated vap. 1089 */ 1090 if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS) 1091 qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev); 1092 1093 return qdf_status; 1094 } 1095 #else 1096 static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer) 1097 { 1098 return QDF_STATUS_SUCCESS; 1099 } 1100 #endif 1101 1102 qdf_size_t dp_get_soc_context_size_be(void) 1103 { 1104 return sizeof(struct dp_soc_be); 1105 } 1106 1107 #ifdef CONFIG_WORD_BASED_TLV 1108 /** 1109 * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config 1110 * @soc: Common DP soc handle 1111 * @htt_tlv_filter: Rx SRNG TLV and filter setting 1112 * 1113 * Return: none 1114 */ 1115 static inline void 1116 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc, 1117 struct htt_rx_ring_tlv_filter *htt_tlv_filter) 1118 { 1119 htt_tlv_filter->rx_msdu_end_wmask = 1120 hal_rx_msdu_end_wmask_get(soc->hal_soc); 1121 htt_tlv_filter->rx_mpdu_start_wmask = 1122 hal_rx_mpdu_start_wmask_get(soc->hal_soc); 1123 } 1124 #else 1125 static inline void 1126 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc, 1127 struct htt_rx_ring_tlv_filter *htt_tlv_filter) 1128 { 1129 } 1130 #endif 1131 #ifdef WLAN_SUPPORT_PPEDS 1132 static 1133 void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng, 1134 int ring_type, int ring_num) 1135 { 1136 if (srng->irq >= 0) { 1137 if (ring_type == WBM2SW_RELEASE && 1138 ring_num == WBM2_SW_PPE_REL_RING_ID) 1139 pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc); 1140 else if (ring_type == REO2PPE || ring_type == PPE2TCL) 1141 pld_pfrm_free_irq(soc->osdev->dev, srng->irq, 1142 dp_get_ppe_ds_ctxt(soc)); 1143 } 1144 } 1145 1146 static 1147 int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng, 1148 int vector, int ring_type, int ring_num) 1149 { 1150 int irq = -1, ret = 0; 1151 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1152 int pci_slot = pld_get_pci_slot(soc->osdev->dev); 1153 1154 srng->irq = -1; 1155 irq = pld_get_msi_irq(soc->osdev->dev, vector); 1156 1157 if (ring_type == WBM2SW_RELEASE && 1158 ring_num == WBM2_SW_PPE_REL_RING_ID) { 1159 snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN, 1160 "pci%d_ppe_wbm_rel", pci_slot); 1161 1162 ret = pld_pfrm_request_irq(soc->osdev->dev, irq, 1163 dp_ppeds_handle_tx_comp, 1164 IRQF_SHARED | IRQF_NO_SUSPEND, 1165 be_soc->irq_name[2], (void *)soc); 1166 1167 if (ret) 1168 goto fail; 1169 } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) { 1170 snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN, 1171 "pci%d_reo2ppe", pci_slot); 1172 ret = pld_pfrm_request_irq(soc->osdev->dev, irq, 1173 dp_ppe_ds_reo2ppe_irq_handler, 1174 IRQF_SHARED | IRQF_NO_SUSPEND, 1175 be_soc->irq_name[0], 1176 dp_get_ppe_ds_ctxt(soc)); 1177 1178 if (ret) 1179 goto fail; 1180 } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) { 1181 snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN, 1182 "pci%d_ppe2tcl", pci_slot); 1183 ret = pld_pfrm_request_irq(soc->osdev->dev, irq, 1184 dp_ppe_ds_ppe2tcl_irq_handler, 1185 IRQF_SHARED | IRQF_NO_SUSPEND, 1186 be_soc->irq_name[1], 1187 dp_get_ppe_ds_ctxt(soc)); 1188 if (ret) 1189 goto fail; 1190 1191 pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq); 1192 } else { 1193 return 0; 1194 } 1195 1196 srng->irq = irq; 1197 1198 dp_info("Registered irq %d for soc %pK ring type %d", 1199 irq, soc, ring_type); 1200 1201 return 0; 1202 fail: 1203 dp_err("Unable to config irq : ring type %d irq %d vector %d", 1204 ring_type, irq, vector); 1205 1206 return ret; 1207 } 1208 1209 void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng) 1210 { 1211 if (srng->irq >= 0) 1212 pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq); 1213 } 1214 1215 void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng) 1216 { 1217 if (srng->irq >= 0) 1218 pld_pfrm_enable_irq(soc->osdev->dev, srng->irq); 1219 } 1220 #endif 1221 1222 #ifdef NO_RX_PKT_HDR_TLV 1223 /** 1224 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 1225 * @soc: Common DP soc handle 1226 * 1227 * Return: QDF_STATUS 1228 */ 1229 static QDF_STATUS 1230 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 1231 { 1232 int i; 1233 int mac_id; 1234 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 1235 struct dp_srng *rx_mac_srng; 1236 QDF_STATUS status = QDF_STATUS_SUCCESS; 1237 1238 /* 1239 * In Beryllium chipset msdu_start, mpdu_end 1240 * and rx_attn are part of msdu_end/mpdu_start 1241 */ 1242 htt_tlv_filter.msdu_start = 0; 1243 htt_tlv_filter.mpdu_end = 0; 1244 htt_tlv_filter.attention = 0; 1245 htt_tlv_filter.mpdu_start = 1; 1246 htt_tlv_filter.msdu_end = 1; 1247 htt_tlv_filter.packet = 1; 1248 htt_tlv_filter.packet_header = 0; 1249 1250 htt_tlv_filter.ppdu_start = 0; 1251 htt_tlv_filter.ppdu_end = 0; 1252 htt_tlv_filter.ppdu_end_user_stats = 0; 1253 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 1254 htt_tlv_filter.ppdu_end_status_done = 0; 1255 htt_tlv_filter.enable_fp = 1; 1256 htt_tlv_filter.enable_md = 0; 1257 htt_tlv_filter.enable_md = 0; 1258 htt_tlv_filter.enable_mo = 0; 1259 1260 htt_tlv_filter.fp_mgmt_filter = 0; 1261 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 1262 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 1263 FILTER_DATA_MCAST | 1264 FILTER_DATA_DATA); 1265 htt_tlv_filter.mo_mgmt_filter = 0; 1266 htt_tlv_filter.mo_ctrl_filter = 0; 1267 htt_tlv_filter.mo_data_filter = 0; 1268 htt_tlv_filter.md_data_filter = 0; 1269 1270 htt_tlv_filter.offset_valid = true; 1271 1272 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 1273 htt_tlv_filter.rx_mpdu_end_offset = 0; 1274 htt_tlv_filter.rx_msdu_start_offset = 0; 1275 htt_tlv_filter.rx_attn_offset = 0; 1276 1277 /* 1278 * For monitor mode, the packet hdr tlv is enabled later during 1279 * filter update 1280 */ 1281 if (soc->cdp_soc.ol_ops->get_con_mode && 1282 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) 1283 htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size; 1284 else 1285 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 1286 1287 /*Not subscribing rx_pkt_header*/ 1288 htt_tlv_filter.rx_header_offset = 0; 1289 htt_tlv_filter.rx_mpdu_start_offset = 1290 hal_rx_mpdu_start_offset_get(soc->hal_soc); 1291 htt_tlv_filter.rx_msdu_end_offset = 1292 hal_rx_msdu_end_offset_get(soc->hal_soc); 1293 1294 dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter); 1295 1296 for (i = 0; i < MAX_PDEV_CNT; i++) { 1297 struct dp_pdev *pdev = soc->pdev_list[i]; 1298 1299 if (!pdev) 1300 continue; 1301 1302 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 1303 int mac_for_pdev = 1304 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 1305 /* 1306 * Obtain lmac id from pdev to access the LMAC ring 1307 * in soc context 1308 */ 1309 int lmac_id = 1310 dp_get_lmac_id_for_pdev_id(soc, mac_id, 1311 pdev->pdev_id); 1312 1313 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 1314 1315 if (!rx_mac_srng->hal_srng) 1316 continue; 1317 1318 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 1319 rx_mac_srng->hal_srng, 1320 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 1321 &htt_tlv_filter); 1322 } 1323 } 1324 return status; 1325 } 1326 #else 1327 /** 1328 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 1329 * @soc: Common DP soc handle 1330 * 1331 * Return: QDF_STATUS 1332 */ 1333 static QDF_STATUS 1334 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 1335 { 1336 int i; 1337 int mac_id; 1338 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 1339 struct dp_srng *rx_mac_srng; 1340 QDF_STATUS status = QDF_STATUS_SUCCESS; 1341 1342 /* 1343 * In Beryllium chipset msdu_start, mpdu_end 1344 * and rx_attn are part of msdu_end/mpdu_start 1345 */ 1346 htt_tlv_filter.msdu_start = 0; 1347 htt_tlv_filter.mpdu_end = 0; 1348 htt_tlv_filter.attention = 0; 1349 htt_tlv_filter.mpdu_start = 1; 1350 htt_tlv_filter.msdu_end = 1; 1351 htt_tlv_filter.packet = 1; 1352 htt_tlv_filter.packet_header = 1; 1353 1354 htt_tlv_filter.ppdu_start = 0; 1355 htt_tlv_filter.ppdu_end = 0; 1356 htt_tlv_filter.ppdu_end_user_stats = 0; 1357 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 1358 htt_tlv_filter.ppdu_end_status_done = 0; 1359 htt_tlv_filter.enable_fp = 1; 1360 htt_tlv_filter.enable_md = 0; 1361 htt_tlv_filter.enable_md = 0; 1362 htt_tlv_filter.enable_mo = 0; 1363 1364 htt_tlv_filter.fp_mgmt_filter = 0; 1365 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 1366 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 1367 FILTER_DATA_MCAST | 1368 FILTER_DATA_DATA); 1369 htt_tlv_filter.mo_mgmt_filter = 0; 1370 htt_tlv_filter.mo_ctrl_filter = 0; 1371 htt_tlv_filter.mo_data_filter = 0; 1372 htt_tlv_filter.md_data_filter = 0; 1373 1374 htt_tlv_filter.offset_valid = true; 1375 1376 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 1377 htt_tlv_filter.rx_mpdu_end_offset = 0; 1378 htt_tlv_filter.rx_msdu_start_offset = 0; 1379 htt_tlv_filter.rx_attn_offset = 0; 1380 1381 /* 1382 * For monitor mode, the packet hdr tlv is enabled later during 1383 * filter update 1384 */ 1385 if (soc->cdp_soc.ol_ops->get_con_mode && 1386 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) 1387 htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size; 1388 else 1389 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 1390 1391 htt_tlv_filter.rx_header_offset = 1392 hal_rx_pkt_tlv_offset_get(soc->hal_soc); 1393 htt_tlv_filter.rx_mpdu_start_offset = 1394 hal_rx_mpdu_start_offset_get(soc->hal_soc); 1395 htt_tlv_filter.rx_msdu_end_offset = 1396 hal_rx_msdu_end_offset_get(soc->hal_soc); 1397 1398 dp_info("TLV subscription\n" 1399 "msdu_start %d, mpdu_end %d, attention %d" 1400 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n" 1401 "TLV offsets\n" 1402 "msdu_start %d, mpdu_end %d, attention %d" 1403 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n", 1404 htt_tlv_filter.msdu_start, 1405 htt_tlv_filter.mpdu_end, 1406 htt_tlv_filter.attention, 1407 htt_tlv_filter.mpdu_start, 1408 htt_tlv_filter.msdu_end, 1409 htt_tlv_filter.packet_header, 1410 htt_tlv_filter.packet, 1411 htt_tlv_filter.rx_msdu_start_offset, 1412 htt_tlv_filter.rx_mpdu_end_offset, 1413 htt_tlv_filter.rx_attn_offset, 1414 htt_tlv_filter.rx_mpdu_start_offset, 1415 htt_tlv_filter.rx_msdu_end_offset, 1416 htt_tlv_filter.rx_header_offset, 1417 htt_tlv_filter.rx_packet_offset); 1418 1419 for (i = 0; i < MAX_PDEV_CNT; i++) { 1420 struct dp_pdev *pdev = soc->pdev_list[i]; 1421 1422 if (!pdev) 1423 continue; 1424 1425 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 1426 int mac_for_pdev = 1427 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 1428 /* 1429 * Obtain lmac id from pdev to access the LMAC ring 1430 * in soc context 1431 */ 1432 int lmac_id = 1433 dp_get_lmac_id_for_pdev_id(soc, mac_id, 1434 pdev->pdev_id); 1435 1436 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 1437 1438 if (!rx_mac_srng->hal_srng) 1439 continue; 1440 1441 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 1442 rx_mac_srng->hal_srng, 1443 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 1444 &htt_tlv_filter); 1445 } 1446 } 1447 return status; 1448 1449 } 1450 #endif 1451 1452 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 1453 /** 1454 * dp_service_near_full_srngs_be() - Main bottom half callback for the 1455 * near-full IRQs. 1456 * @soc: Datapath SoC handle 1457 * @int_ctx: Interrupt context 1458 * @dp_budget: Budget of the work that can be done in the bottom half 1459 * 1460 * Return: work done in the handler 1461 */ 1462 static uint32_t 1463 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx, 1464 uint32_t dp_budget) 1465 { 1466 int ring = 0; 1467 int budget = dp_budget; 1468 uint32_t work_done = 0; 1469 uint32_t remaining_quota = dp_budget; 1470 struct dp_intr_stats *intr_stats = &int_ctx->intr_stats; 1471 int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask; 1472 int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask; 1473 int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask; 1474 int rx_near_full_mask = rx_near_full_grp_1_mask | 1475 rx_near_full_grp_2_mask; 1476 1477 dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x", 1478 rx_near_full_mask, 1479 tx_ring_near_full_mask); 1480 1481 if (rx_near_full_mask) { 1482 for (ring = 0; ring < soc->num_reo_dest_rings; ring++) { 1483 if (!(rx_near_full_mask & (1 << ring))) 1484 continue; 1485 1486 work_done = dp_rx_nf_process(int_ctx, 1487 soc->reo_dest_ring[ring].hal_srng, 1488 ring, remaining_quota); 1489 if (work_done) { 1490 intr_stats->num_rx_ring_near_full_masks[ring]++; 1491 dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d", 1492 rx_near_full_mask, ring, 1493 work_done, 1494 budget); 1495 budget -= work_done; 1496 if (budget <= 0) 1497 goto budget_done; 1498 remaining_quota = budget; 1499 } 1500 } 1501 } 1502 1503 if (tx_ring_near_full_mask) { 1504 for (ring = 0; ring < soc->num_tcl_data_rings; ring++) { 1505 if (!(tx_ring_near_full_mask & (1 << ring))) 1506 continue; 1507 1508 work_done = dp_tx_comp_nf_handler(int_ctx, soc, 1509 soc->tx_comp_ring[ring].hal_srng, 1510 ring, remaining_quota); 1511 if (work_done) { 1512 intr_stats->num_tx_comp_ring_near_full_masks[ring]++; 1513 dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d", 1514 tx_ring_near_full_mask, ring, 1515 work_done, budget); 1516 budget -= work_done; 1517 if (budget <= 0) 1518 break; 1519 remaining_quota = budget; 1520 } 1521 } 1522 } 1523 1524 intr_stats->num_near_full_masks++; 1525 1526 budget_done: 1527 return dp_budget - budget; 1528 } 1529 1530 /** 1531 * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full 1532 * state and set the reap_limit appropriately 1533 * as per the near full state 1534 * @soc: Datapath soc handle 1535 * @dp_srng: Datapath handle for SRNG 1536 * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per 1537 * the srng near-full state 1538 * 1539 * Return: 1, if the srng is in near-full state 1540 * 0, if the srng is not in near-full state 1541 */ 1542 static int 1543 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc, 1544 struct dp_srng *dp_srng, 1545 int *max_reap_limit) 1546 { 1547 return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit); 1548 } 1549 1550 /** 1551 * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the 1552 * near full IRQ handling operations. 1553 * @arch_ops: arch ops handle 1554 * 1555 * Return: none 1556 */ 1557 static inline void 1558 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1559 { 1560 arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be; 1561 arch_ops->dp_srng_test_and_update_nf_params = 1562 dp_srng_test_and_update_nf_params_be; 1563 } 1564 1565 #else 1566 static inline void 1567 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1568 { 1569 } 1570 #endif 1571 1572 #ifdef WLAN_SUPPORT_PPEDS 1573 static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc) 1574 { 1575 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1576 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1577 1578 soc_cfg_ctx = soc->wlan_cfg_ctx; 1579 1580 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx)) 1581 return; 1582 1583 dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0); 1584 wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1585 be_soc->ppe2tcl_ring.alloc_size, 1586 soc->ctrl_psoc, 1587 WLAN_MD_DP_SRNG_PPE2TCL, 1588 "ppe2tcl_ring"); 1589 1590 dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0); 1591 wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1592 be_soc->reo2ppe_ring.alloc_size, 1593 soc->ctrl_psoc, 1594 WLAN_MD_DP_SRNG_REO2PPE, 1595 "reo2ppe_ring"); 1596 1597 dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE, 1598 WBM2_SW_PPE_REL_RING_ID); 1599 wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned, 1600 be_soc->ppeds_wbm_release_ring.alloc_size, 1601 soc->ctrl_psoc, 1602 WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE, 1603 "ppeds_wbm_release_ring"); 1604 1605 } 1606 1607 static void dp_soc_ppeds_srng_free(struct dp_soc *soc) 1608 { 1609 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1610 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1611 1612 soc_cfg_ctx = soc->wlan_cfg_ctx; 1613 1614 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx)) 1615 return; 1616 1617 dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring); 1618 1619 dp_srng_free(soc, &be_soc->ppe2tcl_ring); 1620 1621 dp_srng_free(soc, &be_soc->reo2ppe_ring); 1622 } 1623 1624 static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc) 1625 { 1626 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1627 uint32_t entries; 1628 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1629 1630 soc_cfg_ctx = soc->wlan_cfg_ctx; 1631 1632 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx)) 1633 return QDF_STATUS_SUCCESS; 1634 1635 entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx); 1636 1637 if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE, 1638 entries, 0)) { 1639 dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc); 1640 goto fail; 1641 } 1642 1643 entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx); 1644 if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 1645 entries, 0)) { 1646 dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc); 1647 goto fail; 1648 } 1649 1650 entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx); 1651 if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE, 1652 entries, 1)) { 1653 dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring", 1654 soc); 1655 goto fail; 1656 } 1657 1658 return QDF_STATUS_SUCCESS; 1659 fail: 1660 dp_soc_ppeds_srng_free(soc); 1661 return QDF_STATUS_E_NOMEM; 1662 } 1663 1664 static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc) 1665 { 1666 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1667 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1668 hal_soc_handle_t hal_soc = soc->hal_soc; 1669 1670 struct dp_ppe_ds_idxs idx = {0}; 1671 1672 soc_cfg_ctx = soc->wlan_cfg_ctx; 1673 1674 if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx)) 1675 return QDF_STATUS_SUCCESS; 1676 1677 if (dp_ppeds_register_soc_be(be_soc, &idx)) { 1678 dp_err("%pK: ppeds registration failed", soc); 1679 goto fail; 1680 } 1681 1682 if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0, 1683 idx.reo2ppe_start_idx)) { 1684 dp_err("%pK: dp_srng_init failed for reo2ppe", soc); 1685 goto fail; 1686 } 1687 1688 wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1689 be_soc->reo2ppe_ring.alloc_size, 1690 soc->ctrl_psoc, 1691 WLAN_MD_DP_SRNG_REO2PPE, 1692 "reo2ppe_ring"); 1693 1694 hal_reo_config_reo2ppe_dest_info(hal_soc); 1695 1696 if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0, 1697 idx.ppe2tcl_start_idx)) { 1698 dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc); 1699 goto fail; 1700 } 1701 1702 wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1703 be_soc->ppe2tcl_ring.alloc_size, 1704 soc->ctrl_psoc, 1705 WLAN_MD_DP_SRNG_PPE2TCL, 1706 "ppe2tcl_ring"); 1707 1708 hal_tx_config_rbm_mapping_be(soc->hal_soc, 1709 be_soc->ppe2tcl_ring.hal_srng, 1710 WBM2_SW_PPE_REL_MAP_ID); 1711 1712 if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE, 1713 WBM2_SW_PPE_REL_RING_ID, 0)) { 1714 dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring", 1715 soc); 1716 goto fail; 1717 } 1718 1719 wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned, 1720 be_soc->ppeds_wbm_release_ring.alloc_size, 1721 soc->ctrl_psoc, 1722 WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE, 1723 "ppeds_wbm_release_ring"); 1724 1725 return QDF_STATUS_SUCCESS; 1726 fail: 1727 dp_soc_ppeds_srng_deinit(soc); 1728 return QDF_STATUS_E_NOMEM; 1729 } 1730 #else 1731 static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc) 1732 { 1733 } 1734 1735 static void dp_soc_ppeds_srng_free(struct dp_soc *soc) 1736 { 1737 } 1738 1739 static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc) 1740 { 1741 return QDF_STATUS_SUCCESS; 1742 } 1743 1744 static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc) 1745 { 1746 return QDF_STATUS_SUCCESS; 1747 } 1748 #endif 1749 1750 static void dp_soc_srng_deinit_be(struct dp_soc *soc) 1751 { 1752 uint32_t i; 1753 1754 dp_soc_ppeds_srng_deinit(soc); 1755 1756 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1757 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1758 dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i], 1759 RXDMA_BUF, 0); 1760 } 1761 } 1762 } 1763 1764 static void dp_soc_srng_free_be(struct dp_soc *soc) 1765 { 1766 uint32_t i; 1767 1768 dp_soc_ppeds_srng_free(soc); 1769 1770 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1771 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) 1772 dp_srng_free(soc, &soc->rx_refill_buf_ring[i]); 1773 } 1774 } 1775 1776 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc) 1777 { 1778 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1779 uint32_t ring_size; 1780 uint32_t i; 1781 1782 soc_cfg_ctx = soc->wlan_cfg_ctx; 1783 1784 ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx); 1785 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1786 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1787 if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i], 1788 RXDMA_BUF, ring_size, 0)) { 1789 dp_err("%pK: dp_srng_alloc failed refill ring", 1790 soc); 1791 goto fail; 1792 } 1793 } 1794 } 1795 1796 if (dp_soc_ppeds_srng_alloc(soc)) { 1797 dp_err("%pK: ppe rings alloc failed", 1798 soc); 1799 goto fail; 1800 } 1801 1802 return QDF_STATUS_SUCCESS; 1803 fail: 1804 dp_soc_srng_free_be(soc); 1805 return QDF_STATUS_E_NOMEM; 1806 } 1807 1808 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc) 1809 { 1810 int i = 0; 1811 1812 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1813 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1814 if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i], 1815 RXDMA_BUF, 0, 0)) { 1816 dp_err("%pK: dp_srng_init failed refill ring", 1817 soc); 1818 goto fail; 1819 } 1820 } 1821 } 1822 1823 if (dp_soc_ppeds_srng_init(soc)) { 1824 dp_err("%pK: ppe ds rings init failed", 1825 soc); 1826 goto fail; 1827 } 1828 1829 return QDF_STATUS_SUCCESS; 1830 fail: 1831 dp_soc_srng_deinit_be(soc); 1832 return QDF_STATUS_E_NOMEM; 1833 } 1834 1835 #ifdef WLAN_FEATURE_11BE_MLO 1836 static inline unsigned 1837 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj, 1838 union dp_align_mac_addr *mac_addr) 1839 { 1840 uint32_t index; 1841 1842 index = 1843 mac_addr->align2.bytes_ab ^ 1844 mac_addr->align2.bytes_cd ^ 1845 mac_addr->align2.bytes_ef; 1846 1847 index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits; 1848 index &= mld_hash_obj->mld_peer_hash.mask; 1849 1850 return index; 1851 } 1852 1853 QDF_STATUS 1854 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj, 1855 int hash_elems) 1856 { 1857 int i, log2; 1858 1859 if (!mld_hash_obj) 1860 return QDF_STATUS_E_FAILURE; 1861 1862 hash_elems *= DP_PEER_HASH_LOAD_MULT; 1863 hash_elems >>= DP_PEER_HASH_LOAD_SHIFT; 1864 log2 = dp_log2_ceil(hash_elems); 1865 hash_elems = 1 << log2; 1866 1867 mld_hash_obj->mld_peer_hash.mask = hash_elems - 1; 1868 mld_hash_obj->mld_peer_hash.idx_bits = log2; 1869 /* allocate an array of TAILQ peer object lists */ 1870 mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc( 1871 hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer))); 1872 if (!mld_hash_obj->mld_peer_hash.bins) 1873 return QDF_STATUS_E_NOMEM; 1874 1875 for (i = 0; i < hash_elems; i++) 1876 TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]); 1877 1878 qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock); 1879 1880 return QDF_STATUS_SUCCESS; 1881 } 1882 1883 void 1884 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj) 1885 { 1886 if (!mld_hash_obj) 1887 return; 1888 1889 if (mld_hash_obj->mld_peer_hash.bins) { 1890 qdf_mem_free(mld_hash_obj->mld_peer_hash.bins); 1891 mld_hash_obj->mld_peer_hash.bins = NULL; 1892 qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock); 1893 } 1894 } 1895 1896 #ifdef WLAN_MLO_MULTI_CHIP 1897 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1898 { 1899 /* In case of MULTI chip MLO peer hash table when MLO global object 1900 * is created, avoid from SOC attach path 1901 */ 1902 return QDF_STATUS_SUCCESS; 1903 } 1904 1905 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1906 { 1907 } 1908 #else 1909 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1910 { 1911 dp_mld_peer_hash_obj_t mld_hash_obj; 1912 1913 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1914 1915 if (!mld_hash_obj) 1916 return QDF_STATUS_E_FAILURE; 1917 1918 return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers); 1919 } 1920 1921 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1922 { 1923 dp_mld_peer_hash_obj_t mld_hash_obj; 1924 1925 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1926 1927 if (!mld_hash_obj) 1928 return; 1929 1930 return dp_mlo_peer_find_hash_detach_be(mld_hash_obj); 1931 } 1932 #endif 1933 1934 static struct dp_peer * 1935 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc, 1936 uint8_t *peer_mac_addr, 1937 int mac_addr_is_aligned, 1938 enum dp_mod_id mod_id, 1939 uint8_t vdev_id) 1940 { 1941 union dp_align_mac_addr local_mac_addr_aligned, *mac_addr; 1942 uint32_t index; 1943 struct dp_peer *peer; 1944 struct dp_vdev *vdev; 1945 dp_mld_peer_hash_obj_t mld_hash_obj; 1946 1947 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1948 if (!mld_hash_obj) 1949 return NULL; 1950 1951 if (!mld_hash_obj->mld_peer_hash.bins) 1952 return NULL; 1953 1954 if (mac_addr_is_aligned) { 1955 mac_addr = (union dp_align_mac_addr *)peer_mac_addr; 1956 } else { 1957 qdf_mem_copy( 1958 &local_mac_addr_aligned.raw[0], 1959 peer_mac_addr, QDF_MAC_ADDR_SIZE); 1960 mac_addr = &local_mac_addr_aligned; 1961 } 1962 1963 if (vdev_id != DP_VDEV_ALL) { 1964 vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id); 1965 if (!vdev) { 1966 dp_err("vdev is null\n"); 1967 return NULL; 1968 } 1969 } else { 1970 vdev = NULL; 1971 } 1972 1973 /* search mld peer table if no link peer for given mac address */ 1974 index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr); 1975 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1976 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1977 hash_list_elem) { 1978 if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) { 1979 if ((vdev_id == DP_VDEV_ALL) || ( 1980 dp_peer_find_mac_addr_cmp( 1981 &peer->vdev->mld_mac_addr, 1982 &vdev->mld_mac_addr) == 0)) { 1983 /* take peer reference before returning */ 1984 if (dp_peer_get_ref(NULL, peer, mod_id) != 1985 QDF_STATUS_SUCCESS) 1986 peer = NULL; 1987 1988 if (vdev) 1989 dp_vdev_unref_delete(soc, vdev, mod_id); 1990 1991 qdf_spin_unlock_bh( 1992 &mld_hash_obj->mld_peer_hash_lock); 1993 return peer; 1994 } 1995 } 1996 } 1997 1998 if (vdev) 1999 dp_vdev_unref_delete(soc, vdev, mod_id); 2000 2001 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 2002 2003 return NULL; /* failure */ 2004 } 2005 2006 static void 2007 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer) 2008 { 2009 uint32_t index; 2010 struct dp_peer *tmppeer = NULL; 2011 int found = 0; 2012 dp_mld_peer_hash_obj_t mld_hash_obj; 2013 2014 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 2015 2016 if (!mld_hash_obj) 2017 return; 2018 2019 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 2020 QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index])); 2021 2022 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 2023 TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index], 2024 hash_list_elem) { 2025 if (tmppeer == peer) { 2026 found = 1; 2027 break; 2028 } 2029 } 2030 QDF_ASSERT(found); 2031 TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer, 2032 hash_list_elem); 2033 2034 dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)", 2035 peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found); 2036 dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG); 2037 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 2038 2039 } 2040 2041 static void 2042 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer) 2043 { 2044 uint32_t index; 2045 dp_mld_peer_hash_obj_t mld_hash_obj; 2046 2047 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 2048 2049 if (!mld_hash_obj) 2050 return; 2051 2052 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 2053 2054 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 2055 2056 if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer, 2057 DP_MOD_ID_CONFIG))) { 2058 dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT, 2059 QDF_MAC_ADDR_REF(peer->mac_addr.raw)); 2060 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 2061 return; 2062 } 2063 TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer, 2064 hash_list_elem); 2065 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 2066 2067 dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added", 2068 peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw)); 2069 } 2070 2071 void dp_print_mlo_ast_stats_be(struct dp_soc *soc) 2072 { 2073 uint32_t index; 2074 struct dp_peer *peer; 2075 dp_mld_peer_hash_obj_t mld_hash_obj; 2076 2077 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 2078 2079 if (!mld_hash_obj) 2080 return; 2081 2082 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 2083 for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) { 2084 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 2085 hash_list_elem) { 2086 dp_print_peer_ast_entries(soc, peer, NULL); 2087 } 2088 } 2089 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 2090 } 2091 2092 #endif 2093 2094 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 2095 static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc, 2096 struct dp_vdev *vdev) 2097 { 2098 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2099 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2100 hal_soc_handle_t hal_soc = soc->hal_soc; 2101 uint8_t vdev_id = vdev->vdev_id; 2102 2103 if (vdev->opmode == wlan_op_mode_sta) { 2104 if (vdev->pdev->isolation) 2105 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 2106 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 2107 else 2108 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 2109 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 2110 } else if (vdev->opmode == wlan_op_mode_ap) { 2111 hal_tx_mcast_mlo_reinject_routing_set( 2112 hal_soc, 2113 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY); 2114 if (vdev->mlo_vdev) { 2115 hal_tx_vdev_mcast_ctrl_set( 2116 hal_soc, 2117 vdev_id, 2118 HAL_TX_MCAST_CTRL_NO_SPECIAL); 2119 } else { 2120 hal_tx_vdev_mcast_ctrl_set(hal_soc, 2121 vdev_id, 2122 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 2123 } 2124 } 2125 } 2126 2127 static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev) 2128 { 2129 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2130 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2131 union hal_tx_bank_config *bank_config; 2132 2133 if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID) 2134 return; 2135 2136 bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config; 2137 2138 hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config, 2139 be_vdev->bank_id); 2140 } 2141 2142 #endif 2143 2144 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \ 2145 defined(WLAN_MCAST_MLO) 2146 static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev, 2147 struct dp_vdev *ptnr_vdev, 2148 void *arg) 2149 { 2150 struct dp_vdev_be *be_ptnr_vdev = 2151 dp_get_be_vdev_from_dp_vdev(ptnr_vdev); 2152 2153 be_ptnr_vdev->mcast_primary = false; 2154 } 2155 2156 #if defined(CONFIG_MLO_SINGLE_DEV) 2157 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 2158 struct dp_vdev *vdev, 2159 cdp_config_param_type val) 2160 { 2161 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2162 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc( 2163 be_vdev->vdev.pdev->soc); 2164 2165 be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev; 2166 vdev->mlo_vdev = true; 2167 2168 if (be_vdev->mcast_primary) { 2169 struct cdp_txrx_peer_params_update params = {0}; 2170 2171 params.chip_id = be_soc->mlo_chip_id; 2172 params.pdev_id = be_vdev->vdev.pdev->pdev_id; 2173 params.osif_vdev = be_vdev->vdev.osif_vdev; 2174 dp_wdi_event_handler( 2175 WDI_EVENT_MCAST_PRIMARY_UPDATE, 2176 be_vdev->vdev.pdev->soc, 2177 (void *)¶ms, CDP_INVALID_PEER, 2178 WDI_NO_VAL, params.pdev_id); 2179 } 2180 } 2181 #else 2182 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 2183 struct dp_vdev *vdev, 2184 cdp_config_param_type val) 2185 { 2186 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2187 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc( 2188 be_vdev->vdev.pdev->soc); 2189 2190 be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev; 2191 vdev->mlo_vdev = true; 2192 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 2193 vdev->vdev_id, 2194 HAL_TX_MCAST_CTRL_NO_SPECIAL); 2195 2196 if (be_vdev->mcast_primary) { 2197 struct cdp_txrx_peer_params_update params = {0}; 2198 2199 dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev, 2200 dp_mlo_mcast_reset_pri_mcast, 2201 (void *)&be_vdev->mcast_primary, 2202 DP_MOD_ID_TX_MCAST); 2203 2204 params.chip_id = be_soc->mlo_chip_id; 2205 params.pdev_id = vdev->pdev->pdev_id; 2206 params.osif_vdev = vdev->osif_vdev; 2207 dp_wdi_event_handler( 2208 WDI_EVENT_MCAST_PRIMARY_UPDATE, 2209 vdev->pdev->soc, 2210 (void *)¶ms, CDP_INVALID_PEER, 2211 WDI_NO_VAL, params.pdev_id); 2212 } 2213 } 2214 #endif 2215 2216 static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be( 2217 struct dp_vdev *vdev, 2218 cdp_config_param_type val) 2219 { 2220 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2221 2222 be_vdev->mcast_primary = false; 2223 vdev->mlo_vdev = false; 2224 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 2225 vdev->vdev_id, 2226 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 2227 } 2228 2229 /** 2230 * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev 2231 * params related to multicast 2232 * @soc: DP soc handle 2233 * @vdev: pointer to vdev structure 2234 * @val: buffer address 2235 * 2236 * Return: QDF_STATUS 2237 */ 2238 static 2239 QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc, 2240 struct dp_vdev *vdev, 2241 cdp_config_param_type *val) 2242 { 2243 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2244 2245 if (be_vdev->mcast_primary) 2246 val->cdp_vdev_param_mcast_vdev = true; 2247 else 2248 val->cdp_vdev_param_mcast_vdev = false; 2249 2250 return QDF_STATUS_SUCCESS; 2251 } 2252 #else 2253 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 2254 struct dp_vdev *vdev, 2255 cdp_config_param_type val) 2256 { 2257 } 2258 2259 static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be( 2260 struct dp_vdev *vdev, 2261 cdp_config_param_type val) 2262 { 2263 } 2264 2265 static 2266 QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc, 2267 struct dp_vdev *vdev, 2268 cdp_config_param_type *val) 2269 { 2270 return QDF_STATUS_SUCCESS; 2271 } 2272 #endif 2273 2274 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 2275 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 2276 uint8_t tx_ring_id, 2277 uint8_t bm_id) 2278 { 2279 hal_tx_config_rbm_mapping_be(soc->hal_soc, 2280 soc->tcl_data_ring[tx_ring_id].hal_srng, 2281 bm_id); 2282 } 2283 #else 2284 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 2285 uint8_t tx_ring_id, 2286 uint8_t bm_id) 2287 { 2288 } 2289 #endif 2290 2291 /** 2292 * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params 2293 * @soc: DP soc handle 2294 * @vdev: pointer to vdev structure 2295 * @param: parameter type to get value 2296 * @val: value 2297 * 2298 * Return: QDF_STATUS 2299 */ 2300 static 2301 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc, 2302 struct dp_vdev *vdev, 2303 enum cdp_vdev_param_type param, 2304 cdp_config_param_type val) 2305 { 2306 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2307 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 2308 2309 switch (param) { 2310 case CDP_TX_ENCAP_TYPE: 2311 case CDP_UPDATE_DSCP_TO_TID_MAP: 2312 case CDP_UPDATE_TDLS_FLAGS: 2313 dp_tx_update_bank_profile(be_soc, be_vdev); 2314 break; 2315 case CDP_ENABLE_CIPHER: 2316 if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) 2317 dp_tx_update_bank_profile(be_soc, be_vdev); 2318 break; 2319 case CDP_SET_MCAST_VDEV: 2320 dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val); 2321 break; 2322 case CDP_RESET_MLO_MCAST_VDEV: 2323 dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val); 2324 break; 2325 default: 2326 dp_warn("invalid param %d", param); 2327 break; 2328 } 2329 2330 return QDF_STATUS_SUCCESS; 2331 } 2332 2333 #ifdef WLAN_FEATURE_11BE_MLO 2334 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2335 static inline void 2336 dp_soc_max_peer_id_set(struct dp_soc *soc) 2337 { 2338 soc->peer_id_shift = dp_log2_ceil(soc->max_peers); 2339 soc->peer_id_mask = (1 << soc->peer_id_shift) - 1; 2340 /* 2341 * Double the peers since we use ML indication bit 2342 * alongwith peer_id to find peers. 2343 */ 2344 soc->max_peer_id = 1 << (soc->peer_id_shift + 1); 2345 } 2346 #else 2347 static inline void 2348 dp_soc_max_peer_id_set(struct dp_soc *soc) 2349 { 2350 soc->max_peer_id = 2351 (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1; 2352 } 2353 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */ 2354 #else 2355 static inline void 2356 dp_soc_max_peer_id_set(struct dp_soc *soc) 2357 { 2358 soc->max_peer_id = soc->max_peers; 2359 } 2360 #endif /* WLAN_FEATURE_11BE_MLO */ 2361 2362 static void dp_peer_map_detach_be(struct dp_soc *soc) 2363 { 2364 if (soc->host_ast_db_enable) 2365 dp_peer_ast_hash_detach(soc); 2366 } 2367 2368 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc) 2369 { 2370 QDF_STATUS status; 2371 2372 if (soc->host_ast_db_enable) { 2373 status = dp_peer_ast_hash_attach(soc); 2374 if (QDF_IS_STATUS_ERROR(status)) 2375 return status; 2376 } 2377 2378 dp_soc_max_peer_id_set(soc); 2379 2380 return QDF_STATUS_SUCCESS; 2381 } 2382 2383 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc, 2384 uint8_t *dest_mac, 2385 uint8_t vdev_id) 2386 { 2387 struct dp_peer *peer = NULL; 2388 struct dp_peer *tgt_peer = NULL; 2389 struct dp_ast_entry *ast_entry = NULL; 2390 uint16_t peer_id; 2391 2392 qdf_spin_lock_bh(&soc->ast_lock); 2393 ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac); 2394 if (!ast_entry) { 2395 qdf_spin_unlock_bh(&soc->ast_lock); 2396 dp_err("NULL ast entry"); 2397 return NULL; 2398 } 2399 2400 peer_id = ast_entry->peer_id; 2401 qdf_spin_unlock_bh(&soc->ast_lock); 2402 2403 if (peer_id == HTT_INVALID_PEER) 2404 return NULL; 2405 2406 peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF); 2407 if (!peer) { 2408 dp_err("NULL peer for peer_id:%d", peer_id); 2409 return NULL; 2410 } 2411 2412 tgt_peer = dp_get_tgt_peer_from_peer(peer); 2413 2414 /* 2415 * Once tgt_peer is obtained, 2416 * release the ref taken for original peer. 2417 */ 2418 dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF); 2419 dp_peer_unref_delete(peer, DP_MOD_ID_SAWF); 2420 2421 return tgt_peer; 2422 } 2423 2424 #ifdef WLAN_FEATURE_11BE_MLO 2425 #ifdef WLAN_MCAST_MLO 2426 static inline void 2427 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 2428 { 2429 arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be; 2430 arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler; 2431 arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be; 2432 } 2433 #else /* WLAN_MCAST_MLO */ 2434 static inline void 2435 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 2436 { 2437 } 2438 #endif /* WLAN_MCAST_MLO */ 2439 2440 #ifdef WLAN_MLO_MULTI_CHIP 2441 static inline void 2442 dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops) 2443 { 2444 arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map; 2445 arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap; 2446 arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id; 2447 } 2448 #else 2449 static inline void 2450 dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops) 2451 { 2452 } 2453 #endif 2454 2455 static inline void 2456 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 2457 { 2458 dp_initialize_arch_ops_be_mcast_mlo(arch_ops); 2459 dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops); 2460 arch_ops->mlo_peer_find_hash_detach = 2461 dp_mlo_peer_find_hash_detach_wrapper; 2462 arch_ops->mlo_peer_find_hash_attach = 2463 dp_mlo_peer_find_hash_attach_wrapper; 2464 arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be; 2465 arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be; 2466 arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be; 2467 } 2468 #else /* WLAN_FEATURE_11BE_MLO */ 2469 static inline void 2470 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 2471 { 2472 } 2473 #endif /* WLAN_FEATURE_11BE_MLO */ 2474 2475 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 2476 #define DP_LMAC_PEER_ID_MSB_LEGACY 2 2477 #define DP_LMAC_PEER_ID_MSB_MLO 3 2478 2479 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 2480 struct cdp_peer_setup_info *setup_info, 2481 enum cdp_host_reo_dest_ring *reo_dest, 2482 bool *hash_based, 2483 uint8_t *lmac_peer_id_msb) 2484 { 2485 struct dp_soc *soc = vdev->pdev->soc; 2486 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2487 2488 if (!be_soc->mlo_enabled) 2489 return dp_vdev_get_default_reo_hash(vdev, reo_dest, 2490 hash_based); 2491 2492 *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx); 2493 *reo_dest = vdev->pdev->reo_dest; 2494 2495 /* Not a ML link peer use non-mlo */ 2496 if (!setup_info) { 2497 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 2498 return; 2499 } 2500 2501 /* For STA ML VAP we do not have num links info at this point 2502 * use MLO case always 2503 */ 2504 if (vdev->opmode == wlan_op_mode_sta) { 2505 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 2506 return; 2507 } 2508 2509 /* For AP ML VAP consider the peer as ML only it associates with 2510 * multiple links 2511 */ 2512 if (setup_info->num_links == 1) { 2513 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 2514 return; 2515 } 2516 2517 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 2518 } 2519 2520 static bool dp_reo_remap_config_be(struct dp_soc *soc, 2521 uint32_t *remap0, 2522 uint32_t *remap1, 2523 uint32_t *remap2) 2524 { 2525 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2526 uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx); 2527 uint32_t reo_mlo_config = 2528 wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx); 2529 2530 if (!be_soc->mlo_enabled) 2531 return dp_reo_remap_config(soc, remap0, remap1, remap2); 2532 2533 *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 2534 *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config); 2535 *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 2536 2537 return true; 2538 } 2539 #else 2540 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 2541 struct cdp_peer_setup_info *setup_info, 2542 enum cdp_host_reo_dest_ring *reo_dest, 2543 bool *hash_based, 2544 uint8_t *lmac_peer_id_msb) 2545 { 2546 dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based); 2547 } 2548 2549 static bool dp_reo_remap_config_be(struct dp_soc *soc, 2550 uint32_t *remap0, 2551 uint32_t *remap1, 2552 uint32_t *remap2) 2553 { 2554 return dp_reo_remap_config(soc, remap0, remap1, remap2); 2555 } 2556 #endif 2557 2558 #ifdef CONFIG_MLO_SINGLE_DEV 2559 static inline 2560 void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops) 2561 { 2562 arch_ops->dp_tx_mlo_mcast_send = dp_tx_mlo_mcast_send_be; 2563 } 2564 #else 2565 static inline 2566 void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops) 2567 { 2568 } 2569 #endif 2570 2571 #ifdef IPA_OFFLOAD 2572 static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc) 2573 { 2574 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 2575 2576 return be_soc->ipa_bank_id; 2577 } 2578 2579 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops) 2580 { 2581 arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be; 2582 } 2583 #else /* !IPA_OFFLOAD */ 2584 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops) 2585 { 2586 } 2587 #endif /* IPA_OFFLOAD */ 2588 2589 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops) 2590 { 2591 #ifndef QCA_HOST_MODE_WIFI_DISABLED 2592 arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be; 2593 arch_ops->dp_rx_process = dp_rx_process_be; 2594 arch_ops->dp_tx_send_fast = dp_tx_fast_send_be; 2595 arch_ops->tx_comp_get_params_from_hal_desc = 2596 dp_tx_comp_get_params_from_hal_desc_be; 2597 arch_ops->dp_tx_process_htt_completion = 2598 dp_tx_process_htt_completion_be; 2599 arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be; 2600 arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be; 2601 arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be; 2602 arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be; 2603 arch_ops->dp_wbm_get_rx_desc_from_hal_desc = 2604 dp_wbm_get_rx_desc_from_hal_desc_be; 2605 arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be; 2606 arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be; 2607 arch_ops->dp_rx_wbm_err_reap_desc = dp_rx_wbm_err_reap_desc_be; 2608 arch_ops->dp_rx_null_q_desc_handle = dp_rx_null_q_desc_handle_be; 2609 #endif 2610 arch_ops->txrx_get_context_size = dp_get_context_size_be; 2611 #ifdef WIFI_MONITOR_SUPPORT 2612 arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be; 2613 #endif 2614 arch_ops->dp_rx_desc_cookie_2_va = 2615 dp_rx_desc_cookie_2_va_be; 2616 arch_ops->dp_rx_intrabss_mcast_handler = 2617 dp_rx_intrabss_mcast_handler_be; 2618 arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be; 2619 2620 arch_ops->txrx_soc_attach = dp_soc_attach_be; 2621 arch_ops->txrx_soc_detach = dp_soc_detach_be; 2622 arch_ops->txrx_soc_init = dp_soc_init_be; 2623 arch_ops->txrx_soc_deinit = dp_soc_deinit_be; 2624 arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be; 2625 arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be; 2626 arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be; 2627 arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be; 2628 arch_ops->txrx_pdev_attach = dp_pdev_attach_be; 2629 arch_ops->txrx_pdev_detach = dp_pdev_detach_be; 2630 arch_ops->txrx_vdev_attach = dp_vdev_attach_be; 2631 arch_ops->txrx_vdev_detach = dp_vdev_detach_be; 2632 arch_ops->txrx_peer_setup = dp_peer_setup_be; 2633 arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be; 2634 arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be; 2635 arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be; 2636 arch_ops->dp_rx_peer_metadata_peer_id_get = 2637 dp_rx_peer_metadata_peer_id_get_be; 2638 arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be; 2639 arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be; 2640 arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be; 2641 dp_initialize_arch_ops_be_mlo(arch_ops); 2642 arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get; 2643 arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be; 2644 arch_ops->dp_peer_rx_reorder_queue_setup = 2645 dp_peer_rx_reorder_queue_setup_be; 2646 arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be; 2647 arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be; 2648 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 2649 arch_ops->dp_bank_reconfig = dp_bank_reconfig_be; 2650 arch_ops->dp_reconfig_tx_vdev_mcast_ctrl = 2651 dp_reconfig_tx_vdev_mcast_ctrl_be; 2652 arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init; 2653 #endif 2654 2655 #ifdef WLAN_SUPPORT_PPEDS 2656 arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status; 2657 arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be; 2658 arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be; 2659 arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts; 2660 arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts; 2661 arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc; 2662 arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping = 2663 dp_tx_ppeds_cfg_astidx_cache_mapping; 2664 #endif 2665 dp_init_near_full_arch_ops_be(arch_ops); 2666 arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be; 2667 arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be; 2668 arch_ops->dp_set_rx_fst = dp_set_rx_fst_be; 2669 arch_ops->dp_get_rx_fst = dp_get_rx_fst_be; 2670 arch_ops->dp_rx_fst_deref = dp_rx_fst_deref_be; 2671 arch_ops->dp_rx_fst_ref = dp_rx_fst_ref_be; 2672 arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be; 2673 arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be; 2674 arch_ops->reo_remap_config = dp_reo_remap_config_be; 2675 arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be; 2676 dp_initialize_arch_ops_be_ipa(arch_ops); 2677 dp_initialize_arch_ops_be_single_dev(arch_ops); 2678 } 2679