xref: /wlan-dirver/qca-wifi-host-cmn/dp/wifi3.0/be/dp_be.c (revision 8b3dca18206e1a0461492f082fa6e270b092c035)
1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <wlan_utility.h>
21 #include <dp_internal.h>
22 #include <dp_htt.h>
23 #include "dp_be.h"
24 #include "dp_be_tx.h"
25 #include "dp_be_rx.h"
26 #ifdef WIFI_MONITOR_SUPPORT
27 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
28 #include "dp_mon_2.0.h"
29 #endif
30 #include "dp_mon.h"
31 #endif
32 #include <hal_be_api.h>
33 
34 /* Generic AST entry aging timer value */
35 #define DP_AST_AGING_TIMER_DEFAULT_MS	5000
36 
37 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
38 #define DP_TX_VDEV_ID_CHECK_ENABLE 0
39 
40 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
41 	{.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
42 	{1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
43 	{2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
44 #ifdef QCA_WIFI_KIWI_V2
45 	{3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
46 	{4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
47 #else
48 	{3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
49 	{4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
50 #endif
51 };
52 #else
53 #define DP_TX_VDEV_ID_CHECK_ENABLE 1
54 
55 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
56 	{.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
57 	{1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
58 	{2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
59 	{3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
60 	{4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
61 };
62 #endif
63 
64 #ifdef WLAN_SUPPORT_PPEDS
65 static void dp_ppeds_rings_status(struct dp_soc *soc)
66 {
67 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
68 
69 	dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
70 	dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
71 }
72 #endif
73 
74 static void dp_soc_cfg_attach_be(struct dp_soc *soc)
75 {
76 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
77 
78 	wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
79 
80 	soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
81 
82 	/* this is used only when dmac mode is enabled */
83 	soc->num_rx_refill_buf_rings = 1;
84 
85 	soc->wlan_cfg_ctx->notify_frame_support =
86 				DP_MARK_NOTIFY_FRAME_SUPPORT;
87 }
88 
89 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
90 {
91 	switch (context_type) {
92 	case DP_CONTEXT_TYPE_SOC:
93 		return sizeof(struct dp_soc_be);
94 	case DP_CONTEXT_TYPE_PDEV:
95 		return sizeof(struct dp_pdev_be);
96 	case DP_CONTEXT_TYPE_VDEV:
97 		return sizeof(struct dp_vdev_be);
98 	case DP_CONTEXT_TYPE_PEER:
99 		return sizeof(struct dp_peer_be);
100 	default:
101 		return 0;
102 	}
103 }
104 
105 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
106 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
107 /**
108  * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
109 			   per wbm2sw ring
110  * @cc_cfg: HAL HW cookie conversion configuration structure pointer
111  *
112  * Return: None
113  */
114 static inline
115 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
116 {
117 	cc_cfg->wbm2sw6_cc_en = 1;
118 	cc_cfg->wbm2sw5_cc_en = 1;
119 	cc_cfg->wbm2sw4_cc_en = 1;
120 	cc_cfg->wbm2sw3_cc_en = 1;
121 	cc_cfg->wbm2sw2_cc_en = 1;
122 	/* disable wbm2sw1 hw cc as it's for FW */
123 	cc_cfg->wbm2sw1_cc_en = 0;
124 	cc_cfg->wbm2sw0_cc_en = 1;
125 	cc_cfg->wbm2fw_cc_en = 0;
126 }
127 #else
128 static inline
129 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
130 {
131 	cc_cfg->wbm2sw6_cc_en = 1;
132 	cc_cfg->wbm2sw5_cc_en = 1;
133 	cc_cfg->wbm2sw4_cc_en = 1;
134 	cc_cfg->wbm2sw3_cc_en = 1;
135 	cc_cfg->wbm2sw2_cc_en = 1;
136 	cc_cfg->wbm2sw1_cc_en = 1;
137 	cc_cfg->wbm2sw0_cc_en = 1;
138 	cc_cfg->wbm2fw_cc_en = 0;
139 }
140 #endif
141 
142 #if defined(WLAN_SUPPORT_RX_FISA)
143 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
144 {
145 	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
146 		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
147 	/* get CMEM for cookie conversion */
148 	if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
149 		dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
150 		return QDF_STATUS_E_NOMEM;
151 	}
152 
153 	soc->fst_cmem_size = DP_CMEM_FST_SIZE;
154 
155 	soc->fst_cmem_base = soc->cmem_base +
156 			     (soc->cmem_total_size - soc->cmem_avail_size);
157 	soc->cmem_avail_size -= soc->fst_cmem_size;
158 
159 	dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
160 		soc->fst_cmem_base, soc->fst_cmem_size);
161 
162 	return QDF_STATUS_SUCCESS;
163 }
164 #else /* !WLAN_SUPPORT_RX_FISA */
165 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
166 {
167 	return QDF_STATUS_SUCCESS;
168 }
169 #endif
170 
171 /**
172  * dp_cc_reg_cfg_init() - initialize and configure HW cookie
173 			  conversion register
174  * @soc: SOC handle
175  * @is_4k_align: page address 4k alignd
176  *
177  * Return: None
178  */
179 static void dp_cc_reg_cfg_init(struct dp_soc *soc,
180 			       bool is_4k_align)
181 {
182 	struct hal_hw_cc_config cc_cfg = { 0 };
183 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
184 
185 	if (soc->cdp_soc.ol_ops->get_con_mode &&
186 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
187 		return;
188 
189 	if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
190 		dp_info("INI skip HW CC register setting");
191 		return;
192 	}
193 
194 	cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
195 	cc_cfg.cc_global_en = true;
196 	cc_cfg.page_4k_align = is_4k_align;
197 	cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
198 	cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
199 	/* 36th bit should be 1 then HW know this is CMEM address */
200 	cc_cfg.lut_base_addr_39_32 = 0x10;
201 
202 	cc_cfg.error_path_cookie_conv_en = true;
203 	cc_cfg.release_path_cookie_conv_en = true;
204 	dp_cc_wbm_sw_en_cfg(&cc_cfg);
205 
206 	hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
207 }
208 
209 /**
210  * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
211  * @hal_soc_hdl: HAL SOC handle
212  * @offset: CMEM address
213  * @value: value to write
214  *
215  * Return: None.
216  */
217 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
218 				       uint32_t offset,
219 				       uint32_t value)
220 {
221 	hal_cmem_write(hal_soc_hdl, offset, value);
222 }
223 
224 /**
225  * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
226 			       HW cookie conversion
227  * @soc: SOC handle
228  * @cc_ctx: cookie conversion context pointer
229  *
230  * Return: 0 in case of success, else error value
231  */
232 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
233 {
234 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
235 
236 	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
237 		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
238 	/* get CMEM for cookie conversion */
239 	if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
240 		dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
241 		return QDF_STATUS_E_RESOURCES;
242 	}
243 	be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
244 					  DP_CC_MEM_OFFSET_IN_CMEM);
245 
246 	soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
247 
248 	dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
249 		be_soc->cc_cmem_base, soc->cmem_avail_size);
250 	return QDF_STATUS_SUCCESS;
251 }
252 
253 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
254 					 uint8_t for_feature)
255 {
256 	QDF_STATUS status = QDF_STATUS_E_NOMEM;
257 
258 	switch (for_feature) {
259 	case COOKIE_CONVERSION:
260 		status = dp_hw_cc_cmem_addr_init(soc);
261 		break;
262 	case FISA_FST:
263 		status = dp_fisa_fst_cmem_addr_init(soc);
264 		break;
265 	default:
266 		dp_err("Invalid CMEM request");
267 	}
268 
269 	return status;
270 }
271 
272 #else
273 
274 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
275 				      bool is_4k_align) {}
276 
277 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
278 				       uint32_t offset,
279 				       uint32_t value)
280 { }
281 
282 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
283 {
284 	return QDF_STATUS_SUCCESS;
285 }
286 
287 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
288 					 uint8_t for_feature)
289 {
290 	return QDF_STATUS_SUCCESS;
291 }
292 
293 #endif
294 
295 QDF_STATUS
296 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
297 			       struct dp_hw_cookie_conversion_t *cc_ctx,
298 			       uint32_t num_descs,
299 			       enum dp_desc_type desc_type,
300 			       uint8_t desc_pool_id)
301 {
302 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
303 	uint32_t num_spt_pages, i = 0;
304 	struct dp_spt_page_desc *spt_desc;
305 	struct qdf_mem_dma_page_t *dma_page;
306 	uint8_t chip_id;
307 
308 	/* estimate how many SPT DDR pages needed */
309 	num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
310 	num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
311 					num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
312 	dp_info("num_spt_pages needed %d", num_spt_pages);
313 
314 	dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
315 				      &cc_ctx->page_pool, qdf_page_size,
316 				      num_spt_pages, 0, false);
317 	if (!cc_ctx->page_pool.dma_pages) {
318 		dp_err("spt ddr pages allocation failed");
319 		return QDF_STATUS_E_RESOURCES;
320 	}
321 	cc_ctx->page_desc_base = qdf_mem_malloc(
322 			num_spt_pages * sizeof(struct dp_spt_page_desc));
323 	if (!cc_ctx->page_desc_base) {
324 		dp_err("spt page descs allocation failed");
325 		goto fail_0;
326 	}
327 
328 	chip_id = dp_mlo_get_chip_id(soc);
329 	cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
330 							 desc_type);
331 
332 	/* initial page desc */
333 	spt_desc = cc_ctx->page_desc_base;
334 	dma_page = cc_ctx->page_pool.dma_pages;
335 	while (i < num_spt_pages) {
336 		/* check if page address 4K aligned */
337 		if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
338 			dp_err("non-4k aligned pages addr %pK",
339 			       (void *)dma_page[i].page_p_addr);
340 			goto fail_1;
341 		}
342 
343 		spt_desc[i].page_v_addr =
344 					dma_page[i].page_v_addr_start;
345 		spt_desc[i].page_p_addr =
346 					dma_page[i].page_p_addr;
347 		i++;
348 	}
349 
350 	cc_ctx->total_page_num = num_spt_pages;
351 	qdf_spinlock_create(&cc_ctx->cc_lock);
352 
353 	return QDF_STATUS_SUCCESS;
354 fail_1:
355 	qdf_mem_free(cc_ctx->page_desc_base);
356 fail_0:
357 	dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
358 				     &cc_ctx->page_pool, 0, false);
359 
360 	return QDF_STATUS_E_FAILURE;
361 }
362 
363 QDF_STATUS
364 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
365 			       struct dp_hw_cookie_conversion_t *cc_ctx)
366 {
367 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
368 
369 	qdf_mem_free(cc_ctx->page_desc_base);
370 	dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
371 				     &cc_ctx->page_pool, 0, false);
372 	qdf_spinlock_destroy(&cc_ctx->cc_lock);
373 
374 	return QDF_STATUS_SUCCESS;
375 }
376 
377 QDF_STATUS
378 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
379 			     struct dp_hw_cookie_conversion_t *cc_ctx)
380 {
381 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
382 	uint32_t i = 0;
383 	struct dp_spt_page_desc *spt_desc;
384 	uint32_t ppt_index;
385 	uint32_t ppt_id_start;
386 
387 	if (!cc_ctx->total_page_num) {
388 		dp_err("total page num is 0");
389 		return QDF_STATUS_E_INVAL;
390 	}
391 
392 	ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
393 	spt_desc = cc_ctx->page_desc_base;
394 	while (i < cc_ctx->total_page_num) {
395 		/* write page PA to CMEM */
396 		dp_hw_cc_cmem_write(soc->hal_soc,
397 				    (cc_ctx->cmem_offset + be_soc->cc_cmem_base
398 				     + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
399 				    (spt_desc[i].page_p_addr >>
400 				     DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
401 
402 		ppt_index = ppt_id_start + i;
403 
404 		if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
405 			qdf_assert_always(0);
406 
407 		spt_desc[i].ppt_index = ppt_index;
408 
409 		be_soc->page_desc_base[ppt_index].page_v_addr =
410 				spt_desc[i].page_v_addr;
411 		i++;
412 	}
413 	return QDF_STATUS_SUCCESS;
414 }
415 
416 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
417 QDF_STATUS
418 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
419 			       struct dp_hw_cookie_conversion_t *cc_ctx)
420 {
421 	uint32_t ppt_index;
422 	struct dp_spt_page_desc *spt_desc;
423 	int i = 0;
424 
425 	spt_desc = cc_ctx->page_desc_base;
426 	while (i < cc_ctx->total_page_num) {
427 		ppt_index = spt_desc[i].ppt_index;
428 		be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
429 		i++;
430 	}
431 	return QDF_STATUS_SUCCESS;
432 }
433 #else
434 QDF_STATUS
435 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
436 			       struct dp_hw_cookie_conversion_t *cc_ctx)
437 {
438 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
439 	uint32_t ppt_index;
440 	struct dp_spt_page_desc *spt_desc;
441 	int i = 0;
442 
443 	spt_desc = cc_ctx->page_desc_base;
444 	while (i < cc_ctx->total_page_num) {
445 		/* reset PA in CMEM to NULL */
446 		dp_hw_cc_cmem_write(soc->hal_soc,
447 				    (cc_ctx->cmem_offset + be_soc->cc_cmem_base
448 				     + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
449 				    0);
450 
451 		ppt_index = spt_desc[i].ppt_index;
452 		be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
453 		i++;
454 	}
455 	return QDF_STATUS_SUCCESS;
456 }
457 #endif
458 
459 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
460 {
461 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
462 	int i = 0;
463 
464 
465 	for (i = 0; i < MAX_TXDESC_POOLS; i++)
466 		dp_hw_cookie_conversion_detach(be_soc,
467 					       &be_soc->tx_cc_ctx[i]);
468 
469 	for (i = 0; i < MAX_RXDESC_POOLS; i++)
470 		dp_hw_cookie_conversion_detach(be_soc,
471 					       &be_soc->rx_cc_ctx[i]);
472 
473 	qdf_mem_free(be_soc->page_desc_base);
474 	be_soc->page_desc_base = NULL;
475 
476 	return QDF_STATUS_SUCCESS;
477 }
478 
479 #ifdef WLAN_MLO_MULTI_CHIP
480 #ifdef WLAN_MCAST_MLO
481 static inline void
482 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
483 {
484 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
485 
486 	be_vdev->mcast_primary = false;
487 	be_vdev->seq_num = 0;
488 	dp_tx_mcast_mlo_reinject_routing_set(soc,
489 					     (void *)&be_vdev->mcast_primary);
490 	if (vdev->opmode == wlan_op_mode_ap) {
491 		if (vdev->mlo_vdev)
492 			hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
493 						   vdev->vdev_id,
494 						   HAL_TX_MCAST_CTRL_DROP);
495 		else
496 			hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
497 						   vdev->vdev_id,
498 						   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
499 	}
500 }
501 
502 static inline void
503 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
504 {
505 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
506 
507 	be_vdev->seq_num = 0;
508 	be_vdev->mcast_primary = false;
509 	vdev->mlo_vdev = false;
510 }
511 #else
512 static inline void
513 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
514 {
515 }
516 
517 static inline void
518 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
519 {
520 }
521 #endif
522 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
523 {
524 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
525 
526 	qdf_mem_set(be_vdev->partner_vdev_list,
527 		    WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
528 		    CDP_INVALID_VDEV_ID);
529 }
530 
531 static void dp_get_rx_hash_key_be(struct dp_soc *soc,
532 				  struct cdp_lro_hash_config *lro_hash)
533 {
534 	dp_mlo_get_rx_hash_key(soc, lro_hash);
535 }
536 #else
537 static inline void
538 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
539 {
540 }
541 
542 static inline void
543 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
544 {
545 }
546 
547 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
548 {
549 }
550 
551 static void dp_get_rx_hash_key_be(struct dp_soc *soc,
552 				  struct cdp_lro_hash_config *lro_hash)
553 {
554 	dp_get_rx_hash_key_bytes(lro_hash);
555 }
556 #endif
557 
558 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
559 				   struct cdp_soc_attach_params *params)
560 {
561 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
562 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
563 	uint32_t max_tx_rx_desc_num, num_spt_pages;
564 	uint32_t num_entries;
565 	int i = 0;
566 
567 	max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
568 		WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
569 	/* estimate how many SPT DDR pages needed */
570 	num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
571 	num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
572 					num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
573 
574 	be_soc->page_desc_base = qdf_mem_malloc(
575 		DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
576 	if (!be_soc->page_desc_base) {
577 		dp_err("spt page descs allocation failed");
578 		return QDF_STATUS_E_NOMEM;
579 	}
580 
581 	soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
582 
583 	qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
584 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
585 		goto fail;
586 
587 	dp_soc_mlo_fill_params(soc, params);
588 
589 	for (i = 0; i < MAX_TXDESC_POOLS; i++) {
590 		num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
591 		qdf_status =
592 			dp_hw_cookie_conversion_attach(be_soc,
593 						       &be_soc->tx_cc_ctx[i],
594 						       num_entries,
595 						       DP_TX_DESC_TYPE, i);
596 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
597 			goto fail;
598 	}
599 
600 	qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
601 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
602 		goto fail;
603 
604 	for (i = 0; i < MAX_RXDESC_POOLS; i++) {
605 		num_entries =
606 			wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
607 		qdf_status =
608 			dp_hw_cookie_conversion_attach(be_soc,
609 						       &be_soc->rx_cc_ctx[i],
610 						       num_entries,
611 						       DP_RX_DESC_BUF_TYPE, i);
612 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
613 			goto fail;
614 	}
615 
616 	return qdf_status;
617 fail:
618 	dp_soc_detach_be(soc);
619 	return qdf_status;
620 }
621 
622 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
623 {
624 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
625 	int i = 0;
626 
627 	dp_tx_deinit_bank_profiles(be_soc);
628 	for (i = 0; i < MAX_TXDESC_POOLS; i++)
629 		dp_hw_cookie_conversion_deinit(be_soc,
630 					       &be_soc->tx_cc_ctx[i]);
631 
632 	for (i = 0; i < MAX_RXDESC_POOLS; i++)
633 		dp_hw_cookie_conversion_deinit(be_soc,
634 					       &be_soc->rx_cc_ctx[i]);
635 
636 	return QDF_STATUS_SUCCESS;
637 }
638 
639 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
640 {
641 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
642 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
643 	int i = 0;
644 
645 	for (i = 0; i < MAX_TXDESC_POOLS; i++) {
646 		qdf_status =
647 			dp_hw_cookie_conversion_init(be_soc,
648 						     &be_soc->tx_cc_ctx[i]);
649 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
650 			goto fail;
651 	}
652 
653 	for (i = 0; i < MAX_RXDESC_POOLS; i++) {
654 		qdf_status =
655 			dp_hw_cookie_conversion_init(be_soc,
656 						     &be_soc->rx_cc_ctx[i]);
657 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
658 			goto fail;
659 	}
660 
661 	/* route vdev_id mismatch notification via FW completion */
662 	hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
663 					 HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
664 
665 	qdf_status = dp_tx_init_bank_profiles(be_soc);
666 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
667 		goto fail;
668 
669 	/* write WBM/REO cookie conversion CFG register */
670 	dp_cc_reg_cfg_init(soc, true);
671 
672 	return qdf_status;
673 fail:
674 	dp_soc_deinit_be(soc);
675 	return qdf_status;
676 }
677 
678 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
679 				    struct cdp_pdev_attach_params *params)
680 {
681 	dp_pdev_mlo_fill_params(pdev, params);
682 	dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
683 
684 	return QDF_STATUS_SUCCESS;
685 }
686 
687 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
688 {
689 	dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
690 
691 	return QDF_STATUS_SUCCESS;
692 }
693 
694 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
695 {
696 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
697 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
698 	struct dp_pdev *pdev = vdev->pdev;
699 
700 	if (vdev->opmode == wlan_op_mode_monitor)
701 		return QDF_STATUS_SUCCESS;
702 
703 	be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
704 
705 	be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
706 	vdev->bank_id = be_vdev->bank_id;
707 
708 	if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
709 		QDF_BUG(0);
710 		return QDF_STATUS_E_FAULT;
711 	}
712 
713 	if (vdev->opmode == wlan_op_mode_sta) {
714 		if (soc->cdp_soc.ol_ops->set_mec_timer)
715 			soc->cdp_soc.ol_ops->set_mec_timer(
716 					soc->ctrl_psoc,
717 					vdev->vdev_id,
718 					DP_AST_AGING_TIMER_DEFAULT_MS);
719 
720 		if (pdev->isolation)
721 			hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
722 						   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
723 		else
724 			hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
725 						   HAL_TX_MCAST_CTRL_MEC_NOTIFY);
726 	}
727 
728 	dp_mlo_mcast_init(soc, vdev);
729 	dp_mlo_init_ptnr_list(vdev);
730 
731 	return QDF_STATUS_SUCCESS;
732 }
733 
734 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
735 {
736 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
737 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
738 
739 	if (vdev->opmode == wlan_op_mode_monitor)
740 		return QDF_STATUS_SUCCESS;
741 
742 	if (vdev->opmode == wlan_op_mode_ap)
743 		dp_mlo_mcast_deinit(soc, vdev);
744 
745 	dp_tx_put_bank_profile(be_soc, be_vdev);
746 	dp_clr_mlo_ptnr_list(soc, vdev);
747 
748 	return QDF_STATUS_SUCCESS;
749 }
750 
751 qdf_size_t dp_get_soc_context_size_be(void)
752 {
753 	return sizeof(struct dp_soc_be);
754 }
755 
756 #ifdef NO_RX_PKT_HDR_TLV
757 /**
758  * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
759  * @soc: Common DP soc handle
760  *
761  * Return: QDF_STATUS
762  */
763 static QDF_STATUS
764 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
765 {
766 	int i;
767 	int mac_id;
768 	struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
769 	struct dp_srng *rx_mac_srng;
770 	QDF_STATUS status = QDF_STATUS_SUCCESS;
771 
772 	/*
773 	 * In Beryllium chipset msdu_start, mpdu_end
774 	 * and rx_attn are part of msdu_end/mpdu_start
775 	 */
776 	htt_tlv_filter.msdu_start = 0;
777 	htt_tlv_filter.mpdu_end = 0;
778 	htt_tlv_filter.attention = 0;
779 	htt_tlv_filter.mpdu_start = 1;
780 	htt_tlv_filter.msdu_end = 1;
781 	htt_tlv_filter.packet = 1;
782 	htt_tlv_filter.packet_header = 0;
783 
784 	htt_tlv_filter.ppdu_start = 0;
785 	htt_tlv_filter.ppdu_end = 0;
786 	htt_tlv_filter.ppdu_end_user_stats = 0;
787 	htt_tlv_filter.ppdu_end_user_stats_ext = 0;
788 	htt_tlv_filter.ppdu_end_status_done = 0;
789 	htt_tlv_filter.enable_fp = 1;
790 	htt_tlv_filter.enable_md = 0;
791 	htt_tlv_filter.enable_md = 0;
792 	htt_tlv_filter.enable_mo = 0;
793 
794 	htt_tlv_filter.fp_mgmt_filter = 0;
795 	htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
796 	htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
797 					 FILTER_DATA_MCAST |
798 					 FILTER_DATA_DATA);
799 	htt_tlv_filter.mo_mgmt_filter = 0;
800 	htt_tlv_filter.mo_ctrl_filter = 0;
801 	htt_tlv_filter.mo_data_filter = 0;
802 	htt_tlv_filter.md_data_filter = 0;
803 
804 	htt_tlv_filter.offset_valid = true;
805 
806 	/* Not subscribing to mpdu_end, msdu_start and rx_attn */
807 	htt_tlv_filter.rx_mpdu_end_offset = 0;
808 	htt_tlv_filter.rx_msdu_start_offset = 0;
809 	htt_tlv_filter.rx_attn_offset = 0;
810 
811 	/*
812 	 * For monitor mode, the packet hdr tlv is enabled later during
813 	 * filter update
814 	 */
815 	if (soc->cdp_soc.ol_ops->get_con_mode &&
816 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
817 		htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
818 	else
819 		htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
820 
821 	/*Not subscribing rx_pkt_header*/
822 	htt_tlv_filter.rx_header_offset = 0;
823 	htt_tlv_filter.rx_mpdu_start_offset =
824 				hal_rx_mpdu_start_offset_get(soc->hal_soc);
825 	htt_tlv_filter.rx_msdu_end_offset =
826 				hal_rx_msdu_end_offset_get(soc->hal_soc);
827 
828 	for (i = 0; i < MAX_PDEV_CNT; i++) {
829 		struct dp_pdev *pdev = soc->pdev_list[i];
830 
831 		if (!pdev)
832 			continue;
833 
834 		for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
835 			int mac_for_pdev =
836 				dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
837 			/*
838 			 * Obtain lmac id from pdev to access the LMAC ring
839 			 * in soc context
840 			 */
841 			int lmac_id =
842 				dp_get_lmac_id_for_pdev_id(soc, mac_id,
843 							   pdev->pdev_id);
844 
845 			rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
846 
847 			if (!rx_mac_srng->hal_srng)
848 				continue;
849 
850 			htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
851 					    rx_mac_srng->hal_srng,
852 					    RXDMA_BUF, RX_DATA_BUFFER_SIZE,
853 					    &htt_tlv_filter);
854 		}
855 	}
856 	return status;
857 }
858 #else
859 /**
860  * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
861  * @soc: Common DP soc handle
862  *
863  * Return: QDF_STATUS
864  */
865 static QDF_STATUS
866 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
867 {
868 	int i;
869 	int mac_id;
870 	struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
871 	struct dp_srng *rx_mac_srng;
872 	QDF_STATUS status = QDF_STATUS_SUCCESS;
873 
874 	/*
875 	 * In Beryllium chipset msdu_start, mpdu_end
876 	 * and rx_attn are part of msdu_end/mpdu_start
877 	 */
878 	htt_tlv_filter.msdu_start = 0;
879 	htt_tlv_filter.mpdu_end = 0;
880 	htt_tlv_filter.attention = 0;
881 	htt_tlv_filter.mpdu_start = 1;
882 	htt_tlv_filter.msdu_end = 1;
883 	htt_tlv_filter.packet = 1;
884 	htt_tlv_filter.packet_header = 1;
885 
886 	htt_tlv_filter.ppdu_start = 0;
887 	htt_tlv_filter.ppdu_end = 0;
888 	htt_tlv_filter.ppdu_end_user_stats = 0;
889 	htt_tlv_filter.ppdu_end_user_stats_ext = 0;
890 	htt_tlv_filter.ppdu_end_status_done = 0;
891 	htt_tlv_filter.enable_fp = 1;
892 	htt_tlv_filter.enable_md = 0;
893 	htt_tlv_filter.enable_md = 0;
894 	htt_tlv_filter.enable_mo = 0;
895 
896 	htt_tlv_filter.fp_mgmt_filter = 0;
897 	htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
898 	htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
899 					 FILTER_DATA_MCAST |
900 					 FILTER_DATA_DATA);
901 	htt_tlv_filter.mo_mgmt_filter = 0;
902 	htt_tlv_filter.mo_ctrl_filter = 0;
903 	htt_tlv_filter.mo_data_filter = 0;
904 	htt_tlv_filter.md_data_filter = 0;
905 
906 	htt_tlv_filter.offset_valid = true;
907 
908 	/* Not subscribing to mpdu_end, msdu_start and rx_attn */
909 	htt_tlv_filter.rx_mpdu_end_offset = 0;
910 	htt_tlv_filter.rx_msdu_start_offset = 0;
911 	htt_tlv_filter.rx_attn_offset = 0;
912 
913 	/*
914 	 * For monitor mode, the packet hdr tlv is enabled later during
915 	 * filter update
916 	 */
917 	if (soc->cdp_soc.ol_ops->get_con_mode &&
918 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
919 		htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
920 	else
921 		htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
922 
923 	htt_tlv_filter.rx_header_offset =
924 				hal_rx_pkt_tlv_offset_get(soc->hal_soc);
925 	htt_tlv_filter.rx_mpdu_start_offset =
926 				hal_rx_mpdu_start_offset_get(soc->hal_soc);
927 	htt_tlv_filter.rx_msdu_end_offset =
928 				hal_rx_msdu_end_offset_get(soc->hal_soc);
929 
930 	dp_info("TLV subscription\n"
931 		"msdu_start %d, mpdu_end %d, attention %d"
932 		"mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
933 		"TLV offsets\n"
934 		"msdu_start %d, mpdu_end %d, attention %d"
935 		"mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
936 		htt_tlv_filter.msdu_start,
937 		htt_tlv_filter.mpdu_end,
938 		htt_tlv_filter.attention,
939 		htt_tlv_filter.mpdu_start,
940 		htt_tlv_filter.msdu_end,
941 		htt_tlv_filter.packet_header,
942 		htt_tlv_filter.packet,
943 		htt_tlv_filter.rx_msdu_start_offset,
944 		htt_tlv_filter.rx_mpdu_end_offset,
945 		htt_tlv_filter.rx_attn_offset,
946 		htt_tlv_filter.rx_mpdu_start_offset,
947 		htt_tlv_filter.rx_msdu_end_offset,
948 		htt_tlv_filter.rx_header_offset,
949 		htt_tlv_filter.rx_packet_offset);
950 
951 	for (i = 0; i < MAX_PDEV_CNT; i++) {
952 		struct dp_pdev *pdev = soc->pdev_list[i];
953 
954 		if (!pdev)
955 			continue;
956 
957 		for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
958 			int mac_for_pdev =
959 				dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
960 			/*
961 			 * Obtain lmac id from pdev to access the LMAC ring
962 			 * in soc context
963 			 */
964 			int lmac_id =
965 				dp_get_lmac_id_for_pdev_id(soc, mac_id,
966 							   pdev->pdev_id);
967 
968 			rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
969 
970 			if (!rx_mac_srng->hal_srng)
971 				continue;
972 
973 			htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
974 					    rx_mac_srng->hal_srng,
975 					    RXDMA_BUF, RX_DATA_BUFFER_SIZE,
976 					    &htt_tlv_filter);
977 		}
978 	}
979 	return status;
980 
981 }
982 #endif
983 
984 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
985 /**
986  * dp_service_near_full_srngs_be() - Main bottom half callback for the
987  *				near-full IRQs.
988  * @soc: Datapath SoC handle
989  * @int_ctx: Interrupt context
990  * @dp_budget: Budget of the work that can be done in the bottom half
991  *
992  * Return: work done in the handler
993  */
994 static uint32_t
995 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
996 			      uint32_t dp_budget)
997 {
998 	int ring = 0;
999 	int budget = dp_budget;
1000 	uint32_t work_done  = 0;
1001 	uint32_t remaining_quota = dp_budget;
1002 	struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
1003 	int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
1004 	int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
1005 	int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
1006 	int rx_near_full_mask = rx_near_full_grp_1_mask |
1007 				rx_near_full_grp_2_mask;
1008 
1009 	dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
1010 			 rx_near_full_mask,
1011 			 tx_ring_near_full_mask);
1012 
1013 	if (rx_near_full_mask) {
1014 		for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
1015 			if (!(rx_near_full_mask & (1 << ring)))
1016 				continue;
1017 
1018 			work_done = dp_rx_nf_process(int_ctx,
1019 					soc->reo_dest_ring[ring].hal_srng,
1020 					ring, remaining_quota);
1021 			if (work_done) {
1022 				intr_stats->num_rx_ring_near_full_masks[ring]++;
1023 				dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
1024 						 rx_near_full_mask, ring,
1025 						 work_done,
1026 						 budget);
1027 				budget -=  work_done;
1028 				if (budget <= 0)
1029 					goto budget_done;
1030 				remaining_quota = budget;
1031 			}
1032 		}
1033 	}
1034 
1035 	if (tx_ring_near_full_mask) {
1036 		for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
1037 			if (!(tx_ring_near_full_mask & (1 << ring)))
1038 				continue;
1039 
1040 			work_done = dp_tx_comp_nf_handler(int_ctx, soc,
1041 					soc->tx_comp_ring[ring].hal_srng,
1042 					ring, remaining_quota);
1043 			if (work_done) {
1044 				intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
1045 				dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
1046 						 tx_ring_near_full_mask, ring,
1047 						 work_done, budget);
1048 				budget -=  work_done;
1049 				if (budget <= 0)
1050 					break;
1051 				remaining_quota = budget;
1052 			}
1053 		}
1054 	}
1055 
1056 	intr_stats->num_near_full_masks++;
1057 
1058 budget_done:
1059 	return dp_budget - budget;
1060 }
1061 
1062 /**
1063  * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
1064  *				state and set the reap_limit appropriately
1065  *				as per the near full state
1066  * @soc: Datapath soc handle
1067  * @dp_srng: Datapath handle for SRNG
1068  * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
1069  *			the srng near-full state
1070  *
1071  * Return: 1, if the srng is in near-full state
1072  *	   0, if the srng is not in near-full state
1073  */
1074 static int
1075 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
1076 				     struct dp_srng *dp_srng,
1077 				     int *max_reap_limit)
1078 {
1079 	return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
1080 }
1081 
1082 /**
1083  * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
1084  *			near full IRQ handling operations.
1085  * @arch_ops: arch ops handle
1086  *
1087  * Return: none
1088  */
1089 static inline void
1090 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
1091 {
1092 	arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
1093 	arch_ops->dp_srng_test_and_update_nf_params =
1094 					dp_srng_test_and_update_nf_params_be;
1095 }
1096 
1097 #else
1098 static inline void
1099 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
1100 {
1101 }
1102 #endif
1103 
1104 #ifdef WLAN_SUPPORT_PPEDS
1105 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
1106 {
1107 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1108 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1109 
1110 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1111 
1112 	if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
1113 		return;
1114 
1115 	dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
1116 	wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
1117 			     be_soc->ppe_release_ring.alloc_size,
1118 			     soc->ctrl_psoc,
1119 			     WLAN_MD_DP_SRNG_PPE_RELEASE,
1120 			     "ppe_release_ring");
1121 
1122 	dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
1123 	wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
1124 			     be_soc->ppe2tcl_ring.alloc_size,
1125 			     soc->ctrl_psoc,
1126 			     WLAN_MD_DP_SRNG_PPE2TCL,
1127 			     "ppe2tcl_ring");
1128 
1129 	dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
1130 	wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
1131 			     be_soc->reo2ppe_ring.alloc_size,
1132 			     soc->ctrl_psoc,
1133 			     WLAN_MD_DP_SRNG_REO2PPE,
1134 			     "reo2ppe_ring");
1135 }
1136 
1137 static void dp_soc_ppe_srng_free(struct dp_soc *soc)
1138 {
1139 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1140 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1141 
1142 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1143 
1144 	if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
1145 		return;
1146 
1147 	dp_srng_free(soc, &be_soc->ppe_release_ring);
1148 
1149 	dp_srng_free(soc, &be_soc->ppe2tcl_ring);
1150 
1151 	dp_srng_free(soc, &be_soc->reo2ppe_ring);
1152 }
1153 
1154 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
1155 {
1156 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1157 	uint32_t entries;
1158 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1159 
1160 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1161 
1162 	if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
1163 		return QDF_STATUS_SUCCESS;
1164 
1165 	entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
1166 
1167 	if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
1168 			  entries, 0)) {
1169 		dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
1170 		goto fail;
1171 	}
1172 
1173 	entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
1174 	if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
1175 			  entries, 0)) {
1176 		dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
1177 		goto fail;
1178 	}
1179 
1180 	entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
1181 	if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
1182 			  entries, 0)) {
1183 		dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
1184 		goto fail;
1185 	}
1186 
1187 	return QDF_STATUS_SUCCESS;
1188 fail:
1189 	dp_soc_ppe_srng_free(soc);
1190 	return QDF_STATUS_E_NOMEM;
1191 }
1192 
1193 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
1194 {
1195 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1196 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1197 	hal_soc_handle_t hal_soc = soc->hal_soc;
1198 
1199 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1200 
1201 	if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
1202 		return QDF_STATUS_SUCCESS;
1203 
1204 	if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
1205 		dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
1206 		goto fail;
1207 	}
1208 
1209 	wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
1210 			  be_soc->reo2ppe_ring.alloc_size,
1211 			  soc->ctrl_psoc,
1212 			  WLAN_MD_DP_SRNG_REO2PPE,
1213 			  "reo2ppe_ring");
1214 
1215 	hal_reo_config_reo2ppe_dest_info(hal_soc);
1216 
1217 	if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
1218 		dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
1219 		goto fail;
1220 	}
1221 
1222 	wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
1223 			  be_soc->ppe2tcl_ring.alloc_size,
1224 			  soc->ctrl_psoc,
1225 			  WLAN_MD_DP_SRNG_PPE2TCL,
1226 			  "ppe2tcl_ring");
1227 
1228 	if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
1229 		dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
1230 		goto fail;
1231 	}
1232 
1233 	wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
1234 			  be_soc->ppe_release_ring.alloc_size,
1235 			  soc->ctrl_psoc,
1236 			  WLAN_MD_DP_SRNG_PPE_RELEASE,
1237 			  "ppe_release_ring");
1238 
1239 	return QDF_STATUS_SUCCESS;
1240 fail:
1241 	dp_soc_ppe_srng_deinit(soc);
1242 	return QDF_STATUS_E_NOMEM;
1243 }
1244 #else
1245 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
1246 {
1247 }
1248 
1249 static void dp_soc_ppe_srng_free(struct dp_soc *soc)
1250 {
1251 }
1252 
1253 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
1254 {
1255 	return QDF_STATUS_SUCCESS;
1256 }
1257 
1258 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
1259 {
1260 	return QDF_STATUS_SUCCESS;
1261 }
1262 #endif
1263 
1264 static void dp_soc_srng_deinit_be(struct dp_soc *soc)
1265 {
1266 	uint32_t i;
1267 
1268 	dp_soc_ppe_srng_deinit(soc);
1269 
1270 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1271 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1272 			dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
1273 				       RXDMA_BUF, 0);
1274 		}
1275 	}
1276 }
1277 
1278 static void dp_soc_srng_free_be(struct dp_soc *soc)
1279 {
1280 	uint32_t i;
1281 
1282 	dp_soc_ppe_srng_free(soc);
1283 
1284 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1285 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
1286 			dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
1287 	}
1288 }
1289 
1290 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
1291 {
1292 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1293 	uint32_t ring_size;
1294 	uint32_t i;
1295 
1296 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1297 
1298 	ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
1299 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1300 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1301 			if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
1302 					  RXDMA_BUF, ring_size, 0)) {
1303 				dp_err("%pK: dp_srng_alloc failed refill ring",
1304 				       soc);
1305 				goto fail;
1306 			}
1307 		}
1308 	}
1309 
1310 	if (dp_soc_ppe_srng_alloc(soc)) {
1311 		dp_err("%pK: ppe rings alloc failed",
1312 		       soc);
1313 		goto fail;
1314 	}
1315 
1316 	return QDF_STATUS_SUCCESS;
1317 fail:
1318 	dp_soc_srng_free_be(soc);
1319 	return QDF_STATUS_E_NOMEM;
1320 }
1321 
1322 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
1323 {
1324 	int i = 0;
1325 
1326 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1327 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1328 			if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
1329 					 RXDMA_BUF, 0, 0)) {
1330 				dp_err("%pK: dp_srng_init failed refill ring",
1331 				       soc);
1332 				goto fail;
1333 			}
1334 		}
1335 	}
1336 
1337 	if (dp_soc_ppe_srng_init(soc)) {
1338 		dp_err("%pK: ppe rings init failed",
1339 		       soc);
1340 		goto fail;
1341 	}
1342 
1343 	return QDF_STATUS_SUCCESS;
1344 fail:
1345 	dp_soc_srng_deinit_be(soc);
1346 	return QDF_STATUS_E_NOMEM;
1347 }
1348 
1349 #ifdef WLAN_FEATURE_11BE_MLO
1350 static inline unsigned
1351 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
1352 			    union dp_align_mac_addr *mac_addr)
1353 {
1354 	uint32_t index;
1355 
1356 	index =
1357 		mac_addr->align2.bytes_ab ^
1358 		mac_addr->align2.bytes_cd ^
1359 		mac_addr->align2.bytes_ef;
1360 
1361 	index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
1362 	index &= mld_hash_obj->mld_peer_hash.mask;
1363 
1364 	return index;
1365 }
1366 
1367 QDF_STATUS
1368 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
1369 				int hash_elems)
1370 {
1371 	int i, log2;
1372 
1373 	if (!mld_hash_obj)
1374 		return QDF_STATUS_E_FAILURE;
1375 
1376 	hash_elems *= DP_PEER_HASH_LOAD_MULT;
1377 	hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
1378 	log2 = dp_log2_ceil(hash_elems);
1379 	hash_elems = 1 << log2;
1380 
1381 	mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
1382 	mld_hash_obj->mld_peer_hash.idx_bits = log2;
1383 	/* allocate an array of TAILQ peer object lists */
1384 	mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
1385 		hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
1386 	if (!mld_hash_obj->mld_peer_hash.bins)
1387 		return QDF_STATUS_E_NOMEM;
1388 
1389 	for (i = 0; i < hash_elems; i++)
1390 		TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
1391 
1392 	qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
1393 
1394 	return QDF_STATUS_SUCCESS;
1395 }
1396 
1397 void
1398 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
1399 {
1400 	if (!mld_hash_obj)
1401 		return;
1402 
1403 	if (mld_hash_obj->mld_peer_hash.bins) {
1404 		qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
1405 		mld_hash_obj->mld_peer_hash.bins = NULL;
1406 		qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
1407 	}
1408 }
1409 
1410 #ifdef WLAN_MLO_MULTI_CHIP
1411 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
1412 {
1413 	/* In case of MULTI chip MLO peer hash table when MLO global object
1414 	 * is created, avoid from SOC attach path
1415 	 */
1416 	return QDF_STATUS_SUCCESS;
1417 }
1418 
1419 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
1420 {
1421 }
1422 #else
1423 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
1424 {
1425 	dp_mld_peer_hash_obj_t mld_hash_obj;
1426 
1427 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1428 
1429 	if (!mld_hash_obj)
1430 		return QDF_STATUS_E_FAILURE;
1431 
1432 	return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
1433 }
1434 
1435 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
1436 {
1437 	dp_mld_peer_hash_obj_t mld_hash_obj;
1438 
1439 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1440 
1441 	if (!mld_hash_obj)
1442 		return;
1443 
1444 	return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
1445 }
1446 #endif
1447 
1448 static struct dp_peer *
1449 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
1450 			      uint8_t *peer_mac_addr,
1451 			      int mac_addr_is_aligned,
1452 			      enum dp_mod_id mod_id,
1453 			      uint8_t vdev_id)
1454 {
1455 	union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
1456 	uint32_t index;
1457 	struct dp_peer *peer;
1458 	struct dp_vdev *vdev;
1459 	dp_mld_peer_hash_obj_t mld_hash_obj;
1460 
1461 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1462 	if (!mld_hash_obj)
1463 		return NULL;
1464 
1465 	if (!mld_hash_obj->mld_peer_hash.bins)
1466 		return NULL;
1467 
1468 	if (mac_addr_is_aligned) {
1469 		mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
1470 	} else {
1471 		qdf_mem_copy(
1472 			&local_mac_addr_aligned.raw[0],
1473 			peer_mac_addr, QDF_MAC_ADDR_SIZE);
1474 		mac_addr = &local_mac_addr_aligned;
1475 	}
1476 
1477 	if (vdev_id != DP_VDEV_ALL) {
1478 		vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
1479 		if (!vdev) {
1480 			dp_err("vdev is null\n");
1481 			return NULL;
1482 		}
1483 	} else {
1484 		vdev = NULL;
1485 	}
1486 	/* search mld peer table if no link peer for given mac address */
1487 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
1488 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
1489 	TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
1490 		      hash_list_elem) {
1491 		if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
1492 			if ((vdev_id == DP_VDEV_ALL) || (
1493 				dp_peer_find_mac_addr_cmp(
1494 						&peer->vdev->mld_mac_addr,
1495 						&vdev->mld_mac_addr) == 0)) {
1496 				/* take peer reference before returning */
1497 				if (dp_peer_get_ref(NULL, peer, mod_id) !=
1498 						QDF_STATUS_SUCCESS)
1499 					peer = NULL;
1500 
1501 				if (vdev)
1502 					dp_vdev_unref_delete(soc, vdev, mod_id);
1503 
1504 				qdf_spin_unlock_bh(
1505 					&mld_hash_obj->mld_peer_hash_lock);
1506 				return peer;
1507 			}
1508 		}
1509 	}
1510 
1511 	if (vdev)
1512 		dp_vdev_unref_delete(soc, vdev, mod_id);
1513 
1514 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1515 
1516 	return NULL; /* failure */
1517 }
1518 
1519 static void
1520 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
1521 {
1522 	uint32_t index;
1523 	struct dp_peer *tmppeer = NULL;
1524 	int found = 0;
1525 	dp_mld_peer_hash_obj_t mld_hash_obj;
1526 
1527 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1528 
1529 	if (!mld_hash_obj)
1530 		return;
1531 
1532 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
1533 	QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
1534 
1535 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
1536 	TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
1537 		      hash_list_elem) {
1538 		if (tmppeer == peer) {
1539 			found = 1;
1540 			break;
1541 		}
1542 	}
1543 	QDF_ASSERT(found);
1544 	TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
1545 		     hash_list_elem);
1546 
1547 	dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
1548 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1549 }
1550 
1551 static void
1552 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
1553 {
1554 	uint32_t index;
1555 	dp_mld_peer_hash_obj_t mld_hash_obj;
1556 
1557 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1558 
1559 	if (!mld_hash_obj)
1560 		return;
1561 
1562 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
1563 
1564 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
1565 
1566 	if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
1567 						DP_MOD_ID_CONFIG))) {
1568 		dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
1569 		       QDF_MAC_ADDR_REF(peer->mac_addr.raw));
1570 		qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1571 		return;
1572 	}
1573 	TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
1574 			  hash_list_elem);
1575 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1576 }
1577 
1578 void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
1579 {
1580 	uint32_t index;
1581 	struct dp_peer *peer;
1582 	dp_mld_peer_hash_obj_t mld_hash_obj;
1583 
1584 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1585 
1586 	if (!mld_hash_obj)
1587 		return;
1588 
1589 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
1590 	for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
1591 		TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
1592 			      hash_list_elem) {
1593 			dp_print_peer_ast_entries(soc, peer, NULL);
1594 		}
1595 	}
1596 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1597 }
1598 
1599 #endif
1600 
1601 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
1602 static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
1603 					      struct dp_vdev *vdev)
1604 {
1605 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1606 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
1607 	hal_soc_handle_t hal_soc = soc->hal_soc;
1608 	uint8_t vdev_id = vdev->vdev_id;
1609 
1610 	if (vdev->opmode == wlan_op_mode_sta) {
1611 		if (vdev->pdev->isolation)
1612 			hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1613 						HAL_TX_MCAST_CTRL_FW_EXCEPTION);
1614 		else
1615 			hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1616 						HAL_TX_MCAST_CTRL_MEC_NOTIFY);
1617 	} else if (vdev->opmode == wlan_op_mode_ap) {
1618 		if (vdev->mlo_vdev) {
1619 			if (be_vdev->mcast_primary) {
1620 				hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1621 					   HAL_TX_MCAST_CTRL_NO_SPECIAL);
1622 				hal_tx_vdev_mcast_ctrl_set(hal_soc,
1623 						vdev_id + 128,
1624 						HAL_TX_MCAST_CTRL_FW_EXCEPTION);
1625 				dp_mcast_mlo_iter_ptnr_soc(be_soc,
1626 					dp_tx_mcast_mlo_reinject_routing_set,
1627 					(void *)&be_vdev->mcast_primary);
1628 			} else {
1629 				hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1630 							HAL_TX_MCAST_CTRL_DROP);
1631 			}
1632 		} else {
1633 			hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
1634 						   vdev_id,
1635 						   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
1636 		}
1637 	}
1638 }
1639 
1640 static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
1641 {
1642 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1643 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
1644 	union hal_tx_bank_config *bank_config;
1645 
1646 	if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
1647 		return;
1648 
1649 	bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
1650 
1651 	hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
1652 				      be_vdev->bank_id);
1653 }
1654 
1655 #endif
1656 
1657 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
1658 	defined(WLAN_MCAST_MLO)
1659 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
1660 					struct dp_vdev_be *be_vdev,
1661 					cdp_config_param_type val)
1662 {
1663 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
1664 						be_vdev->vdev.pdev->soc);
1665 	hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
1666 	uint8_t vdev_id = be_vdev->vdev.vdev_id;
1667 
1668 	be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
1669 
1670 	if (be_vdev->mcast_primary) {
1671 		hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1672 					   HAL_TX_MCAST_CTRL_NO_SPECIAL);
1673 		hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
1674 					   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
1675 		dp_mcast_mlo_iter_ptnr_soc(be_soc,
1676 					   dp_tx_mcast_mlo_reinject_routing_set,
1677 					   (void *)&be_vdev->mcast_primary);
1678 	} else {
1679 		hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
1680 					   HAL_TX_MCAST_CTRL_DROP);
1681 	}
1682 }
1683 #else
1684 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
1685 					struct dp_vdev_be *be_vdev,
1686 					cdp_config_param_type val)
1687 {
1688 }
1689 #endif
1690 
1691 #ifdef DP_TX_IMPLICIT_RBM_MAPPING
1692 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
1693 				      uint8_t tx_ring_id,
1694 				      uint8_t bm_id)
1695 {
1696 	hal_tx_config_rbm_mapping_be(soc->hal_soc,
1697 				     soc->tcl_data_ring[tx_ring_id].hal_srng,
1698 				     bm_id);
1699 }
1700 #else
1701 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
1702 				      uint8_t tx_ring_id,
1703 				      uint8_t bm_id)
1704 {
1705 }
1706 #endif
1707 
1708 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
1709 				     struct dp_vdev *vdev,
1710 				     enum cdp_vdev_param_type param,
1711 				     cdp_config_param_type val)
1712 {
1713 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1714 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
1715 
1716 	switch (param) {
1717 	case CDP_TX_ENCAP_TYPE:
1718 	case CDP_UPDATE_DSCP_TO_TID_MAP:
1719 	case CDP_UPDATE_TDLS_FLAGS:
1720 		dp_tx_update_bank_profile(be_soc, be_vdev);
1721 		break;
1722 	case CDP_ENABLE_CIPHER:
1723 		if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
1724 			dp_tx_update_bank_profile(be_soc, be_vdev);
1725 		break;
1726 	case CDP_SET_MCAST_VDEV:
1727 		dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
1728 		break;
1729 	default:
1730 		dp_warn("invalid param %d", param);
1731 		break;
1732 	}
1733 
1734 	return QDF_STATUS_SUCCESS;
1735 }
1736 
1737 #ifdef WLAN_FEATURE_11BE_MLO
1738 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
1739 static inline void
1740 dp_soc_max_peer_id_set(struct dp_soc *soc)
1741 {
1742 	soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
1743 	soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
1744 	/*
1745 	 * Double the peers since we use ML indication bit
1746 	 * alongwith peer_id to find peers.
1747 	 */
1748 	soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
1749 }
1750 #else
1751 static inline void
1752 dp_soc_max_peer_id_set(struct dp_soc *soc)
1753 {
1754 	soc->max_peer_id =
1755 		(1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
1756 }
1757 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
1758 #else
1759 static inline void
1760 dp_soc_max_peer_id_set(struct dp_soc *soc)
1761 {
1762 	soc->max_peer_id = soc->max_peers;
1763 }
1764 #endif /* WLAN_FEATURE_11BE_MLO */
1765 
1766 static void dp_peer_map_detach_be(struct dp_soc *soc)
1767 {
1768 	if (soc->host_ast_db_enable)
1769 		dp_peer_ast_hash_detach(soc);
1770 }
1771 
1772 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
1773 {
1774 	QDF_STATUS status;
1775 
1776 	if (soc->host_ast_db_enable) {
1777 		status = dp_peer_ast_hash_attach(soc);
1778 		if (QDF_IS_STATUS_ERROR(status))
1779 			return status;
1780 	}
1781 
1782 	dp_soc_max_peer_id_set(soc);
1783 
1784 	return QDF_STATUS_SUCCESS;
1785 }
1786 
1787 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
1788 						  uint8_t *dest_mac,
1789 						  uint8_t vdev_id)
1790 {
1791 	struct dp_peer *peer = NULL;
1792 	struct dp_peer *tgt_peer = NULL;
1793 	struct dp_ast_entry *ast_entry = NULL;
1794 	uint16_t peer_id;
1795 
1796 	qdf_spin_lock_bh(&soc->ast_lock);
1797 	ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
1798 	if (!ast_entry) {
1799 		qdf_spin_unlock_bh(&soc->ast_lock);
1800 		dp_err("NULL ast entry");
1801 		return NULL;
1802 	}
1803 
1804 	peer_id = ast_entry->peer_id;
1805 	qdf_spin_unlock_bh(&soc->ast_lock);
1806 
1807 	if (peer_id == HTT_INVALID_PEER)
1808 		return NULL;
1809 
1810 	peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
1811 	if (!peer) {
1812 		dp_err("NULL peer for peer_id:%d", peer_id);
1813 		return NULL;
1814 	}
1815 
1816 	tgt_peer = dp_get_tgt_peer_from_peer(peer);
1817 
1818 	/*
1819 	 * Once tgt_peer is obtained,
1820 	 * release the ref taken for original peer.
1821 	 */
1822 	dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
1823 	dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
1824 
1825 	return tgt_peer;
1826 }
1827 
1828 #ifdef WLAN_FEATURE_11BE_MLO
1829 #ifdef WLAN_MCAST_MLO
1830 static inline void
1831 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
1832 {
1833 	arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
1834 	arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
1835 }
1836 #else /* WLAN_MCAST_MLO */
1837 static inline void
1838 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
1839 {
1840 }
1841 #endif /* WLAN_MCAST_MLO */
1842 
1843 #ifdef WLAN_MLO_MULTI_CHIP
1844 static inline void
1845 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
1846 {
1847 	arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
1848 	arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
1849 }
1850 #else
1851 static inline void
1852 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
1853 {
1854 }
1855 #endif
1856 
1857 static inline void
1858 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
1859 {
1860 	dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
1861 	dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops);
1862 	arch_ops->mlo_peer_find_hash_detach =
1863 	dp_mlo_peer_find_hash_detach_wrapper;
1864 	arch_ops->mlo_peer_find_hash_attach =
1865 	dp_mlo_peer_find_hash_attach_wrapper;
1866 	arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
1867 	arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
1868 	arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
1869 }
1870 #else /* WLAN_FEATURE_11BE_MLO */
1871 static inline void
1872 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
1873 {
1874 }
1875 #endif /* WLAN_FEATURE_11BE_MLO */
1876 
1877 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
1878 #define DP_LMAC_PEER_ID_MSB_LEGACY 2
1879 #define DP_LMAC_PEER_ID_MSB_MLO 3
1880 
1881 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
1882 				    struct cdp_peer_setup_info *setup_info,
1883 				    enum cdp_host_reo_dest_ring *reo_dest,
1884 				    bool *hash_based,
1885 				    uint8_t *lmac_peer_id_msb)
1886 {
1887 	struct dp_soc *soc = vdev->pdev->soc;
1888 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1889 
1890 	if (!be_soc->mlo_enabled)
1891 		return dp_vdev_get_default_reo_hash(vdev, reo_dest,
1892 						    hash_based);
1893 
1894 	*hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
1895 	*reo_dest = vdev->pdev->reo_dest;
1896 
1897 	/* Not a ML link peer use non-mlo */
1898 	if (!setup_info) {
1899 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
1900 		return;
1901 	}
1902 
1903 	/* For STA ML VAP we do not have num links info at this point
1904 	 * use MLO case always
1905 	 */
1906 	if (vdev->opmode == wlan_op_mode_sta) {
1907 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
1908 		return;
1909 	}
1910 
1911 	/* For AP ML VAP consider the peer as ML only it associates with
1912 	 * multiple links
1913 	 */
1914 	if (setup_info->num_links == 1) {
1915 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
1916 		return;
1917 	}
1918 
1919 	*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
1920 }
1921 
1922 static bool dp_reo_remap_config_be(struct dp_soc *soc,
1923 				   uint32_t *remap0,
1924 				   uint32_t *remap1,
1925 				   uint32_t *remap2)
1926 {
1927 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1928 	uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
1929 	uint32_t reo_mlo_config =
1930 		wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
1931 
1932 	if (!be_soc->mlo_enabled)
1933 		return dp_reo_remap_config(soc, remap0, remap1, remap2);
1934 
1935 	*remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
1936 	*remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
1937 	*remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
1938 
1939 	return true;
1940 }
1941 #else
1942 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
1943 				    struct cdp_peer_setup_info *setup_info,
1944 				    enum cdp_host_reo_dest_ring *reo_dest,
1945 				    bool *hash_based,
1946 				    uint8_t *lmac_peer_id_msb)
1947 {
1948 	dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
1949 }
1950 
1951 static bool dp_reo_remap_config_be(struct dp_soc *soc,
1952 				   uint32_t *remap0,
1953 				   uint32_t *remap1,
1954 				   uint32_t *remap2)
1955 {
1956 	return dp_reo_remap_config(soc, remap0, remap1, remap2);
1957 }
1958 #endif
1959 
1960 #ifdef IPA_OFFLOAD
1961 static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
1962 {
1963 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1964 
1965 	return be_soc->ipa_bank_id;
1966 }
1967 
1968 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
1969 {
1970 	arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
1971 }
1972 #else /* !IPA_OFFLOAD */
1973 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
1974 {
1975 }
1976 #endif /* IPA_OFFLOAD */
1977 
1978 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
1979 {
1980 #ifndef QCA_HOST_MODE_WIFI_DISABLED
1981 	arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
1982 	arch_ops->dp_rx_process = dp_rx_process_be;
1983 	arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
1984 	arch_ops->tx_comp_get_params_from_hal_desc =
1985 		dp_tx_comp_get_params_from_hal_desc_be;
1986 	arch_ops->dp_tx_process_htt_completion =
1987 				dp_tx_process_htt_completion_be;
1988 	arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
1989 	arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
1990 	arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
1991 	arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
1992 	arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
1993 				dp_wbm_get_rx_desc_from_hal_desc_be;
1994 	arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
1995 #endif
1996 	arch_ops->txrx_get_context_size = dp_get_context_size_be;
1997 #ifdef WIFI_MONITOR_SUPPORT
1998 	arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
1999 #endif
2000 	arch_ops->dp_rx_desc_cookie_2_va =
2001 			dp_rx_desc_cookie_2_va_be;
2002 	arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
2003 
2004 	arch_ops->txrx_soc_attach = dp_soc_attach_be;
2005 	arch_ops->txrx_soc_detach = dp_soc_detach_be;
2006 	arch_ops->txrx_soc_init = dp_soc_init_be;
2007 	arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
2008 	arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
2009 	arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
2010 	arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
2011 	arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
2012 	arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
2013 	arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
2014 	arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
2015 	arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
2016 	arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
2017 	arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
2018 	arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
2019 	arch_ops->dp_rx_peer_metadata_peer_id_get =
2020 					dp_rx_peer_metadata_peer_id_get_be;
2021 	arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
2022 	arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
2023 	arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
2024 	dp_initialize_arch_ops_be_mlo(arch_ops);
2025 	arch_ops->dp_peer_rx_reorder_queue_setup =
2026 					dp_peer_rx_reorder_queue_setup_be;
2027 	arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
2028 	arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
2029 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
2030 	arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
2031 	arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
2032 					dp_reconfig_tx_vdev_mcast_ctrl_be;
2033 	arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
2034 #endif
2035 
2036 #ifdef WLAN_SUPPORT_PPEDS
2037 	arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
2038 #else
2039 	arch_ops->dp_txrx_ppeds_rings_status = NULL;
2040 #endif
2041 
2042 	dp_init_near_full_arch_ops_be(arch_ops);
2043 	arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
2044 	arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
2045 	arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
2046 	arch_ops->reo_remap_config = dp_reo_remap_config_be;
2047 	dp_initialize_arch_ops_be_ipa(arch_ops);
2048 }
2049