xref: /wlan-dirver/qca-wifi-host-cmn/dp/wifi3.0/be/dp_be.c (revision 70a19e16789e308182f63b15c75decec7bf0b342)
1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <wlan_utility.h>
21 #include <dp_internal.h>
22 #include <dp_htt.h>
23 #include "dp_be.h"
24 #include "dp_be_tx.h"
25 #include "dp_be_rx.h"
26 #ifdef WIFI_MONITOR_SUPPORT
27 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
28 #include "dp_mon_2.0.h"
29 #endif
30 #include "dp_mon.h"
31 #endif
32 #include <hal_be_api.h>
33 #ifdef WLAN_SUPPORT_PPEDS
34 #include "be/dp_ppeds.h"
35 #include <ppe_vp_public.h>
36 #include <ppe_drv_sc.h>
37 #endif
38 
39 /* Generic AST entry aging timer value */
40 #define DP_AST_AGING_TIMER_DEFAULT_MS	5000
41 
42 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
43 #define DP_TX_VDEV_ID_CHECK_ENABLE 0
44 
45 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
46 	{.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
47 	{1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
48 	{2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
49 #ifdef QCA_WIFI_KIWI_V2
50 	{3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
51 	{4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
52 #else
53 	{3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
54 	{4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
55 #endif
56 };
57 #else
58 #define DP_TX_VDEV_ID_CHECK_ENABLE 1
59 
60 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
61 	{.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
62 	{1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
63 	{2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
64 	{3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
65 	{4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
66 };
67 #endif
68 
69 #ifdef WLAN_SUPPORT_PPEDS
70 static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
71 	.ppeds_entry_attach = dp_ppeds_attach_vdev_be,
72 	.ppeds_entry_detach = dp_ppeds_detach_vdev_be,
73 	.ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
74 	.ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
75 	.ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
76 	.ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
77 };
78 
79 static void dp_ppeds_rings_status(struct dp_soc *soc)
80 {
81 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
82 
83 	dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
84 	dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
85 	dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
86 				    WBM2SW_RELEASE);
87 }
88 
89 static void dp_ppeds_inuse_desc(struct dp_soc *soc)
90 {
91 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
92 
93 	DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
94 		       be_soc->ppeds_tx_desc.num_allocated,
95 		       be_soc->ppeds_tx_desc.num_free);
96 }
97 #endif
98 
99 static void dp_soc_cfg_attach_be(struct dp_soc *soc)
100 {
101 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
102 
103 	wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
104 
105 	soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
106 
107 	/* this is used only when dmac mode is enabled */
108 	soc->num_rx_refill_buf_rings = 1;
109 
110 	soc->wlan_cfg_ctx->notify_frame_support =
111 				DP_MARK_NOTIFY_FRAME_SUPPORT;
112 }
113 
114 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
115 {
116 	switch (context_type) {
117 	case DP_CONTEXT_TYPE_SOC:
118 		return sizeof(struct dp_soc_be);
119 	case DP_CONTEXT_TYPE_PDEV:
120 		return sizeof(struct dp_pdev_be);
121 	case DP_CONTEXT_TYPE_VDEV:
122 		return sizeof(struct dp_vdev_be);
123 	case DP_CONTEXT_TYPE_PEER:
124 		return sizeof(struct dp_peer_be);
125 	default:
126 		return 0;
127 	}
128 }
129 
130 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
131 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
132 /**
133  * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
134  *			   per wbm2sw ring
135  *
136  * @cc_cfg: HAL HW cookie conversion configuration structure pointer
137  *
138  * Return: None
139  */
140 static inline
141 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
142 {
143 	cc_cfg->wbm2sw6_cc_en = 1;
144 	cc_cfg->wbm2sw5_cc_en = 1;
145 	cc_cfg->wbm2sw4_cc_en = 1;
146 	cc_cfg->wbm2sw3_cc_en = 1;
147 	cc_cfg->wbm2sw2_cc_en = 1;
148 	/* disable wbm2sw1 hw cc as it's for FW */
149 	cc_cfg->wbm2sw1_cc_en = 0;
150 	cc_cfg->wbm2sw0_cc_en = 1;
151 	cc_cfg->wbm2fw_cc_en = 0;
152 }
153 #else
154 static inline
155 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
156 {
157 	cc_cfg->wbm2sw6_cc_en = 1;
158 	cc_cfg->wbm2sw5_cc_en = 1;
159 	cc_cfg->wbm2sw4_cc_en = 1;
160 	cc_cfg->wbm2sw3_cc_en = 1;
161 	cc_cfg->wbm2sw2_cc_en = 1;
162 	cc_cfg->wbm2sw1_cc_en = 1;
163 	cc_cfg->wbm2sw0_cc_en = 1;
164 	cc_cfg->wbm2fw_cc_en = 0;
165 }
166 #endif
167 
168 #if defined(WLAN_SUPPORT_RX_FISA)
169 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
170 {
171 	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
172 		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
173 	/* get CMEM for cookie conversion */
174 	if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
175 		dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
176 		return QDF_STATUS_E_NOMEM;
177 	}
178 
179 	soc->fst_cmem_size = DP_CMEM_FST_SIZE;
180 
181 	soc->fst_cmem_base = soc->cmem_base +
182 			     (soc->cmem_total_size - soc->cmem_avail_size);
183 	soc->cmem_avail_size -= soc->fst_cmem_size;
184 
185 	dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
186 		soc->fst_cmem_base, soc->fst_cmem_size);
187 
188 	return QDF_STATUS_SUCCESS;
189 }
190 #else /* !WLAN_SUPPORT_RX_FISA */
191 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
192 {
193 	return QDF_STATUS_SUCCESS;
194 }
195 #endif
196 
197 /**
198  * dp_cc_reg_cfg_init() - initialize and configure HW cookie
199  *			  conversion register
200  *
201  * @soc: SOC handle
202  * @is_4k_align: page address 4k aligned
203  *
204  * Return: None
205  */
206 static void dp_cc_reg_cfg_init(struct dp_soc *soc,
207 			       bool is_4k_align)
208 {
209 	struct hal_hw_cc_config cc_cfg = { 0 };
210 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
211 
212 	if (soc->cdp_soc.ol_ops->get_con_mode &&
213 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
214 		return;
215 
216 	if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
217 		dp_info("INI skip HW CC register setting");
218 		return;
219 	}
220 
221 	cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
222 	cc_cfg.cc_global_en = true;
223 	cc_cfg.page_4k_align = is_4k_align;
224 	cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
225 	cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
226 	/* 36th bit should be 1 then HW know this is CMEM address */
227 	cc_cfg.lut_base_addr_39_32 = 0x10;
228 
229 	cc_cfg.error_path_cookie_conv_en = true;
230 	cc_cfg.release_path_cookie_conv_en = true;
231 	dp_cc_wbm_sw_en_cfg(&cc_cfg);
232 
233 	hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
234 }
235 
236 /**
237  * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
238  * @hal_soc_hdl: HAL SOC handle
239  * @offset: CMEM address
240  * @value: value to write
241  *
242  * Return: None.
243  */
244 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
245 				       uint32_t offset,
246 				       uint32_t value)
247 {
248 	hal_cmem_write(hal_soc_hdl, offset, value);
249 }
250 
251 /**
252  * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
253  *			       HW cookie conversion
254  *
255  * @soc: SOC handle
256  *
257  * Return: 0 in case of success, else error value
258  */
259 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
260 {
261 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
262 
263 	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
264 		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
265 	/* get CMEM for cookie conversion */
266 	if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
267 		dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
268 		return QDF_STATUS_E_RESOURCES;
269 	}
270 	be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
271 					  DP_CC_MEM_OFFSET_IN_CMEM);
272 
273 	soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
274 
275 	dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
276 		be_soc->cc_cmem_base, soc->cmem_avail_size);
277 	return QDF_STATUS_SUCCESS;
278 }
279 
280 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
281 					 uint8_t for_feature)
282 {
283 	QDF_STATUS status = QDF_STATUS_E_NOMEM;
284 
285 	switch (for_feature) {
286 	case COOKIE_CONVERSION:
287 		status = dp_hw_cc_cmem_addr_init(soc);
288 		break;
289 	case FISA_FST:
290 		status = dp_fisa_fst_cmem_addr_init(soc);
291 		break;
292 	default:
293 		dp_err("Invalid CMEM request");
294 	}
295 
296 	return status;
297 }
298 
299 #else
300 
301 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
302 				      bool is_4k_align) {}
303 
304 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
305 				       uint32_t offset,
306 				       uint32_t value)
307 { }
308 
309 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
310 {
311 	return QDF_STATUS_SUCCESS;
312 }
313 
314 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
315 					 uint8_t for_feature)
316 {
317 	return QDF_STATUS_SUCCESS;
318 }
319 
320 #endif
321 
322 QDF_STATUS
323 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
324 			       struct dp_hw_cookie_conversion_t *cc_ctx,
325 			       uint32_t num_descs,
326 			       enum dp_desc_type desc_type,
327 			       uint8_t desc_pool_id)
328 {
329 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
330 	uint32_t num_spt_pages, i = 0;
331 	struct dp_spt_page_desc *spt_desc;
332 	struct qdf_mem_dma_page_t *dma_page;
333 	uint8_t chip_id;
334 
335 	/* estimate how many SPT DDR pages needed */
336 	num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
337 	num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
338 					num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
339 	dp_info("num_spt_pages needed %d", num_spt_pages);
340 
341 	dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
342 				      &cc_ctx->page_pool, qdf_page_size,
343 				      num_spt_pages, 0, false);
344 	if (!cc_ctx->page_pool.dma_pages) {
345 		dp_err("spt ddr pages allocation failed");
346 		return QDF_STATUS_E_RESOURCES;
347 	}
348 	cc_ctx->page_desc_base = qdf_mem_malloc(
349 			num_spt_pages * sizeof(struct dp_spt_page_desc));
350 	if (!cc_ctx->page_desc_base) {
351 		dp_err("spt page descs allocation failed");
352 		goto fail_0;
353 	}
354 
355 	chip_id = dp_mlo_get_chip_id(soc);
356 	cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
357 							 desc_type);
358 
359 	/* initial page desc */
360 	spt_desc = cc_ctx->page_desc_base;
361 	dma_page = cc_ctx->page_pool.dma_pages;
362 	while (i < num_spt_pages) {
363 		/* check if page address 4K aligned */
364 		if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
365 			dp_err("non-4k aligned pages addr %pK",
366 			       (void *)dma_page[i].page_p_addr);
367 			goto fail_1;
368 		}
369 
370 		spt_desc[i].page_v_addr =
371 					dma_page[i].page_v_addr_start;
372 		spt_desc[i].page_p_addr =
373 					dma_page[i].page_p_addr;
374 		i++;
375 	}
376 
377 	cc_ctx->total_page_num = num_spt_pages;
378 	qdf_spinlock_create(&cc_ctx->cc_lock);
379 
380 	return QDF_STATUS_SUCCESS;
381 fail_1:
382 	qdf_mem_free(cc_ctx->page_desc_base);
383 fail_0:
384 	dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
385 				     &cc_ctx->page_pool, 0, false);
386 
387 	return QDF_STATUS_E_FAILURE;
388 }
389 
390 QDF_STATUS
391 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
392 			       struct dp_hw_cookie_conversion_t *cc_ctx)
393 {
394 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
395 
396 	qdf_mem_free(cc_ctx->page_desc_base);
397 	dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
398 				     &cc_ctx->page_pool, 0, false);
399 	qdf_spinlock_destroy(&cc_ctx->cc_lock);
400 
401 	return QDF_STATUS_SUCCESS;
402 }
403 
404 QDF_STATUS
405 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
406 			     struct dp_hw_cookie_conversion_t *cc_ctx)
407 {
408 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
409 	uint32_t i = 0;
410 	struct dp_spt_page_desc *spt_desc;
411 	uint32_t ppt_index;
412 	uint32_t ppt_id_start;
413 
414 	if (!cc_ctx->total_page_num) {
415 		dp_err("total page num is 0");
416 		return QDF_STATUS_E_INVAL;
417 	}
418 
419 	ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
420 	spt_desc = cc_ctx->page_desc_base;
421 	while (i < cc_ctx->total_page_num) {
422 		/* write page PA to CMEM */
423 		dp_hw_cc_cmem_write(soc->hal_soc,
424 				    (cc_ctx->cmem_offset + be_soc->cc_cmem_base
425 				     + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
426 				    (spt_desc[i].page_p_addr >>
427 				     DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
428 
429 		ppt_index = ppt_id_start + i;
430 
431 		if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
432 			qdf_assert_always(0);
433 
434 		spt_desc[i].ppt_index = ppt_index;
435 
436 		be_soc->page_desc_base[ppt_index].page_v_addr =
437 				spt_desc[i].page_v_addr;
438 		i++;
439 	}
440 	return QDF_STATUS_SUCCESS;
441 }
442 
443 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
444 QDF_STATUS
445 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
446 			       struct dp_hw_cookie_conversion_t *cc_ctx)
447 {
448 	uint32_t ppt_index;
449 	struct dp_spt_page_desc *spt_desc;
450 	int i = 0;
451 
452 	spt_desc = cc_ctx->page_desc_base;
453 	while (i < cc_ctx->total_page_num) {
454 		ppt_index = spt_desc[i].ppt_index;
455 		be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
456 		i++;
457 	}
458 	return QDF_STATUS_SUCCESS;
459 }
460 #else
461 QDF_STATUS
462 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
463 			       struct dp_hw_cookie_conversion_t *cc_ctx)
464 {
465 	struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
466 	uint32_t ppt_index;
467 	struct dp_spt_page_desc *spt_desc;
468 	int i = 0;
469 
470 	spt_desc = cc_ctx->page_desc_base;
471 	while (i < cc_ctx->total_page_num) {
472 		/* reset PA in CMEM to NULL */
473 		dp_hw_cc_cmem_write(soc->hal_soc,
474 				    (cc_ctx->cmem_offset + be_soc->cc_cmem_base
475 				     + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
476 				    0);
477 
478 		ppt_index = spt_desc[i].ppt_index;
479 		be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
480 		i++;
481 	}
482 	return QDF_STATUS_SUCCESS;
483 }
484 #endif
485 
486 #ifdef WLAN_SUPPORT_PPEDS
487 static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
488 {
489 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
490 	struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
491 
492 	/*
493 	 * Check if PPE DS is enabled.
494 	 */
495 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
496 		return QDF_STATUS_SUCCESS;
497 
498 	if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
499 		return QDF_STATUS_SUCCESS;
500 
501 	cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
502 
503 	return QDF_STATUS_SUCCESS;
504 }
505 
506 static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
507 {
508 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
509 	struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
510 
511 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx))
512 		return QDF_STATUS_E_FAILURE;
513 
514 	dp_ppeds_detach_soc_be(be_soc);
515 
516 	cdp_ops->ppeds_ops = NULL;
517 
518 	return QDF_STATUS_SUCCESS;
519 }
520 
521 static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
522 						 struct dp_peer_be *be_peer,
523 						 uint8_t vdev_id,
524 						 uint16_t src_info)
525 {
526 	uint16_t service_code;
527 	uint8_t priority_valid;
528 	uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
529 	uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
530 	QDF_STATUS status = QDF_STATUS_SUCCESS;
531 	struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
532 	struct dp_vdev_be *be_vdev;
533 
534 	be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
535 
536 	/*
537 	 * Program service code bypass to avoid L2 new mac address
538 	 * learning exception when fdb learning is disabled.
539 	 */
540 	service_code = PPE_DRV_SC_SPF_BYPASS;
541 	priority_valid = be_peer->priority_valid;
542 
543 	/*
544 	 * if FST is enabled then let flow rule take the decision of
545 	 * routing the pkt to DS or host
546 	 */
547 	if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
548 		use_ppe_ds = 0;
549 
550 	if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
551 		status =
552 		soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
553 				(soc->ctrl_psoc,
554 				be_peer->peer.mac_addr.raw,
555 				service_code, priority_valid,
556 				src_info, vdev_id, use_ppe_ds,
557 				peer_routing_enabled);
558 		if (status != QDF_STATUS_SUCCESS) {
559 			dp_err("vdev_id: %d, PPE peer routing mac:"
560 			       QDF_MAC_ADDR_FMT, vdev_id,
561 			       QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
562 
563 			return QDF_STATUS_E_FAILURE;
564 		}
565 	}
566 
567 	return QDF_STATUS_SUCCESS;
568 }
569 
570 #ifdef WLAN_FEATURE_11BE_MLO
571 static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
572 					 struct dp_peer *peer,
573 					 struct dp_vdev_be *be_vdev)
574 {
575 	struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
576 	uint16_t src_info = ppe_vp_profile->vp_num;
577 	uint8_t vdev_id = be_vdev->vdev.vdev_id;
578 	struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
579 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
580 
581 	if (!be_peer) {
582 		dp_err("BE peer is null");
583 		return QDF_STATUS_E_NULL_VALUE;
584 	}
585 
586 	if (IS_DP_LEGACY_PEER(peer)) {
587 		qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
588 							    vdev_id, src_info);
589 	} else if (IS_MLO_DP_MLD_PEER(peer)) {
590 		int i;
591 		struct dp_peer *link_peer = NULL;
592 		struct dp_mld_link_peers link_peers_info;
593 
594 		/* get link peers with reference */
595 		dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
596 						    DP_MOD_ID_DS);
597 
598 		for (i = 0; i < link_peers_info.num_links; i++) {
599 			link_peer = link_peers_info.link_peers[i];
600 			be_peer = dp_get_be_peer_from_dp_peer(link_peer);
601 			if (!be_peer) {
602 				dp_err("BE peer is null");
603 				continue;
604 			}
605 
606 			be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
607 			if (!be_vdev) {
608 				dp_err("BE vap is null for peer id %d ",
609 				       link_peer->peer_id);
610 				continue;
611 			}
612 
613 			vdev_id = be_vdev->vdev.vdev_id;
614 			qdf_status = dp_peer_ppeds_default_route_be(soc,
615 								    be_peer,
616 								    vdev_id,
617 								    src_info);
618 		}
619 
620 		dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
621 	} else {
622 		struct dp_peer *mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
623 
624 		if (!mld_peer)
625 			return qdf_status;
626 
627 		be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
628 		if (!be_vdev) {
629 			dp_err("BE vap is null");
630 			return QDF_STATUS_E_NULL_VALUE;
631 		}
632 
633 		ppe_vp_profile = &be_vdev->ppe_vp_profile;
634 		src_info = ppe_vp_profile->vp_num;
635 		qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
636 							    vdev_id, src_info);
637 	}
638 
639 	return qdf_status;
640 }
641 #else
642 static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
643 					 struct dp_peer *peer,
644 					 struct dp_vdev_be *be_vdev)
645 {
646 	struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
647 	struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
648 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
649 
650 	if (!be_peer) {
651 		dp_err("BE peer is null");
652 		return QDF_STATUS_E_NULL_VALUE;
653 	}
654 
655 	qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
656 						    be_vdev->vdev.vdev_id,
657 						    ppe_vp_profile->vp_num);
658 
659 	return qdf_status;
660 }
661 #endif
662 #else
663 static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
664 {
665 	return QDF_STATUS_SUCCESS;
666 }
667 
668 static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
669 {
670 	return QDF_STATUS_SUCCESS;
671 }
672 
673 static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
674 {
675 	return QDF_STATUS_SUCCESS;
676 }
677 
678 static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
679 {
680 	return QDF_STATUS_SUCCESS;
681 }
682 
683 static inline
684 QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
685 				  struct dp_vdev_be *be_vdev)
686 {
687 	return QDF_STATUS_SUCCESS;
688 }
689 #endif /* WLAN_SUPPORT_PPEDS */
690 
691 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
692 {
693 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
694 	int i = 0;
695 
696 	dp_soc_ppeds_detach_be(soc);
697 
698 	for (i = 0; i < MAX_TXDESC_POOLS; i++)
699 		dp_hw_cookie_conversion_detach(be_soc,
700 					       &be_soc->tx_cc_ctx[i]);
701 
702 	for (i = 0; i < MAX_RXDESC_POOLS; i++)
703 		dp_hw_cookie_conversion_detach(be_soc,
704 					       &be_soc->rx_cc_ctx[i]);
705 
706 	qdf_mem_free(be_soc->page_desc_base);
707 	be_soc->page_desc_base = NULL;
708 
709 	return QDF_STATUS_SUCCESS;
710 }
711 
712 #ifdef WLAN_MLO_MULTI_CHIP
713 #ifdef WLAN_MCAST_MLO
714 static inline void
715 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
716 {
717 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
718 
719 	be_vdev->mcast_primary = false;
720 	be_vdev->seq_num = 0;
721 
722 	hal_tx_mcast_mlo_reinject_routing_set(
723 				soc->hal_soc,
724 				HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
725 
726 	if (vdev->opmode == wlan_op_mode_ap) {
727 		hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
728 					   vdev->vdev_id,
729 					   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
730 	}
731 }
732 
733 static inline void
734 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
735 {
736 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
737 
738 	be_vdev->seq_num = 0;
739 	be_vdev->mcast_primary = false;
740 	vdev->mlo_vdev = false;
741 }
742 
743 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
744 {
745 	dp_mlo_set_rx_fst(soc, fst);
746 }
747 
748 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
749 {
750 	return dp_mlo_get_rx_fst(soc);
751 }
752 
753 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
754 {
755 	return dp_mlo_rx_fst_deref(soc);
756 }
757 
758 static void dp_rx_fst_ref_be(struct dp_soc *soc)
759 {
760 	dp_mlo_rx_fst_ref(soc);
761 }
762 #else
763 static inline void
764 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
765 {
766 }
767 
768 static inline void
769 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
770 {
771 }
772 
773 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
774 {
775 }
776 
777 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
778 {
779 	return NULL;
780 }
781 
782 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
783 {
784 	return 1;
785 }
786 
787 static void dp_rx_fst_ref_be(struct dp_soc *soc)
788 {
789 }
790 #endif
791 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
792 {
793 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
794 
795 	qdf_mem_set(be_vdev->partner_vdev_list,
796 		    WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
797 		    CDP_INVALID_VDEV_ID);
798 }
799 
800 static void dp_get_rx_hash_key_be(struct dp_soc *soc,
801 				  struct cdp_lro_hash_config *lro_hash)
802 {
803 	dp_mlo_get_rx_hash_key(soc, lro_hash);
804 }
805 #else
806 static inline void
807 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
808 {
809 }
810 
811 static inline void
812 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
813 {
814 }
815 
816 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
817 {
818 }
819 
820 static void dp_get_rx_hash_key_be(struct dp_soc *soc,
821 				  struct cdp_lro_hash_config *lro_hash)
822 {
823 	dp_get_rx_hash_key_bytes(lro_hash);
824 }
825 
826 static void dp_set_rx_fst_be(struct dp_soc *soc, struct dp_rx_fst *fst)
827 {
828 }
829 
830 static struct dp_rx_fst *dp_get_rx_fst_be(struct dp_soc *soc)
831 {
832 	return NULL;
833 }
834 
835 static uint8_t dp_rx_fst_deref_be(struct dp_soc *soc)
836 {
837 	return 1;
838 }
839 
840 static void dp_rx_fst_ref_be(struct dp_soc *soc)
841 {
842 }
843 #endif
844 
845 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
846 				   struct cdp_soc_attach_params *params)
847 {
848 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
849 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
850 	uint32_t max_tx_rx_desc_num, num_spt_pages;
851 	uint32_t num_entries;
852 	int i = 0;
853 
854 	max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
855 		WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
856 		WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
857 	/* estimate how many SPT DDR pages needed */
858 	num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
859 	num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
860 					num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
861 
862 	be_soc->page_desc_base = qdf_mem_malloc(
863 		DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
864 	if (!be_soc->page_desc_base) {
865 		dp_err("spt page descs allocation failed");
866 		return QDF_STATUS_E_NOMEM;
867 	}
868 
869 	soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
870 
871 	qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
872 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
873 		goto fail;
874 
875 	dp_soc_mlo_fill_params(soc, params);
876 
877 	qdf_status = dp_soc_ppeds_attach_be(soc);
878 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
879 		goto fail;
880 
881 	for (i = 0; i < MAX_TXDESC_POOLS; i++) {
882 		num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
883 		qdf_status =
884 			dp_hw_cookie_conversion_attach(be_soc,
885 						       &be_soc->tx_cc_ctx[i],
886 						       num_entries,
887 						       DP_TX_DESC_TYPE, i);
888 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
889 			goto fail;
890 	}
891 
892 	qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
893 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
894 		goto fail;
895 
896 	for (i = 0; i < MAX_RXDESC_POOLS; i++) {
897 		num_entries =
898 			wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
899 		qdf_status =
900 			dp_hw_cookie_conversion_attach(be_soc,
901 						       &be_soc->rx_cc_ctx[i],
902 						       num_entries,
903 						       DP_RX_DESC_BUF_TYPE, i);
904 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
905 			goto fail;
906 	}
907 
908 	return qdf_status;
909 fail:
910 	dp_soc_detach_be(soc);
911 	return qdf_status;
912 }
913 
914 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
915 {
916 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
917 	int i = 0;
918 
919 	dp_tx_deinit_bank_profiles(be_soc);
920 	for (i = 0; i < MAX_TXDESC_POOLS; i++)
921 		dp_hw_cookie_conversion_deinit(be_soc,
922 					       &be_soc->tx_cc_ctx[i]);
923 
924 	for (i = 0; i < MAX_RXDESC_POOLS; i++)
925 		dp_hw_cookie_conversion_deinit(be_soc,
926 					       &be_soc->rx_cc_ctx[i]);
927 
928 	dp_ppeds_deinit_soc_be(soc);
929 
930 	return QDF_STATUS_SUCCESS;
931 }
932 
933 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
934 {
935 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
936 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
937 	int i = 0;
938 
939 	dp_ppeds_init_soc_be(soc);
940 
941 	for (i = 0; i < MAX_TXDESC_POOLS; i++) {
942 		qdf_status =
943 			dp_hw_cookie_conversion_init(be_soc,
944 						     &be_soc->tx_cc_ctx[i]);
945 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
946 			goto fail;
947 	}
948 
949 	for (i = 0; i < MAX_RXDESC_POOLS; i++) {
950 		qdf_status =
951 			dp_hw_cookie_conversion_init(be_soc,
952 						     &be_soc->rx_cc_ctx[i]);
953 		if (!QDF_IS_STATUS_SUCCESS(qdf_status))
954 			goto fail;
955 	}
956 
957 	/* route vdev_id mismatch notification via FW completion */
958 	hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
959 					 HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
960 
961 	qdf_status = dp_tx_init_bank_profiles(be_soc);
962 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
963 		goto fail;
964 
965 	/* write WBM/REO cookie conversion CFG register */
966 	dp_cc_reg_cfg_init(soc, true);
967 
968 	return qdf_status;
969 fail:
970 	dp_soc_deinit_be(soc);
971 	return qdf_status;
972 }
973 
974 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
975 				    struct cdp_pdev_attach_params *params)
976 {
977 	dp_pdev_mlo_fill_params(pdev, params);
978 
979 	return QDF_STATUS_SUCCESS;
980 }
981 
982 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
983 {
984 	dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
985 
986 	return QDF_STATUS_SUCCESS;
987 }
988 
989 #ifdef INTRA_BSS_FWD_OFFLOAD
990 static
991 void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
992 {
993 	soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
994 						enable);
995 }
996 #else
997 static
998 void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
999 {
1000 }
1001 #endif
1002 
1003 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
1004 {
1005 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1006 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
1007 	struct dp_pdev *pdev = vdev->pdev;
1008 
1009 	if (vdev->opmode == wlan_op_mode_monitor)
1010 		return QDF_STATUS_SUCCESS;
1011 
1012 	be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
1013 
1014 	be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
1015 	vdev->bank_id = be_vdev->bank_id;
1016 
1017 	if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
1018 		QDF_BUG(0);
1019 		return QDF_STATUS_E_FAULT;
1020 	}
1021 
1022 	if (vdev->opmode == wlan_op_mode_sta) {
1023 		if (soc->cdp_soc.ol_ops->set_mec_timer)
1024 			soc->cdp_soc.ol_ops->set_mec_timer(
1025 					soc->ctrl_psoc,
1026 					vdev->vdev_id,
1027 					DP_AST_AGING_TIMER_DEFAULT_MS);
1028 
1029 		if (pdev->isolation)
1030 			hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
1031 						   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
1032 		else
1033 			hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
1034 						   HAL_TX_MCAST_CTRL_MEC_NOTIFY);
1035 	} else if (vdev->ap_bridge_enabled) {
1036 		dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
1037 	}
1038 
1039 	dp_mlo_mcast_init(soc, vdev);
1040 	dp_mlo_init_ptnr_list(vdev);
1041 
1042 	return QDF_STATUS_SUCCESS;
1043 }
1044 
1045 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
1046 {
1047 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1048 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
1049 
1050 	if (vdev->opmode == wlan_op_mode_monitor)
1051 		return QDF_STATUS_SUCCESS;
1052 
1053 	if (vdev->opmode == wlan_op_mode_ap)
1054 		dp_mlo_mcast_deinit(soc, vdev);
1055 
1056 	dp_tx_put_bank_profile(be_soc, be_vdev);
1057 	dp_clr_mlo_ptnr_list(soc, vdev);
1058 
1059 	return QDF_STATUS_SUCCESS;
1060 }
1061 
1062 #ifdef WLAN_SUPPORT_PPEDS
1063 static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
1064 {
1065 	struct dp_vdev_be *be_vdev;
1066 	QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
1067 
1068 	be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
1069 	if (!be_vdev) {
1070 		qdf_err("BE vap is null");
1071 		return QDF_STATUS_E_NULL_VALUE;
1072 	}
1073 
1074 	/*
1075 	 * Check if PPE DS routing is enabled on the associated vap.
1076 	 */
1077 	if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS)
1078 		qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev);
1079 
1080 	return qdf_status;
1081 }
1082 #else
1083 static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
1084 {
1085 	return QDF_STATUS_SUCCESS;
1086 }
1087 #endif
1088 
1089 qdf_size_t dp_get_soc_context_size_be(void)
1090 {
1091 	return sizeof(struct dp_soc_be);
1092 }
1093 
1094 #ifdef CONFIG_WORD_BASED_TLV
1095 /**
1096  * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
1097  * @soc: Common DP soc handle
1098  * @htt_tlv_filter: Rx SRNG TLV and filter setting
1099  *
1100  * Return: none
1101  */
1102 static inline void
1103 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
1104 			   struct htt_rx_ring_tlv_filter *htt_tlv_filter)
1105 {
1106 	htt_tlv_filter->rx_msdu_end_wmask =
1107 				 hal_rx_msdu_end_wmask_get(soc->hal_soc);
1108 	htt_tlv_filter->rx_mpdu_start_wmask =
1109 				 hal_rx_mpdu_start_wmask_get(soc->hal_soc);
1110 }
1111 #else
1112 static inline void
1113 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
1114 			   struct htt_rx_ring_tlv_filter *htt_tlv_filter)
1115 {
1116 }
1117 #endif
1118 #ifdef WLAN_SUPPORT_PPEDS
1119 static
1120 void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
1121 			      int ring_type, int ring_num)
1122 {
1123 	if (srng->irq >= 0) {
1124 		if (ring_type == WBM2SW_RELEASE &&
1125 		    ring_num == WBM2_SW_PPE_REL_RING_ID)
1126 			pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
1127 		else if (ring_type == REO2PPE || ring_type == PPE2TCL)
1128 			pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
1129 					  dp_get_ppe_ds_ctxt(soc));
1130 	}
1131 }
1132 
1133 static
1134 int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
1135 				 int vector, int ring_type, int ring_num)
1136 {
1137 	int irq = -1, ret = 0;
1138 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1139 	int pci_slot = pld_get_pci_slot(soc->osdev->dev);
1140 
1141 	srng->irq = -1;
1142 	irq = pld_get_msi_irq(soc->osdev->dev, vector);
1143 
1144 	if (ring_type == WBM2SW_RELEASE &&
1145 	    ring_num == WBM2_SW_PPE_REL_RING_ID) {
1146 		snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
1147 			 "pci%d_ppe_wbm_rel", pci_slot);
1148 
1149 		ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
1150 					   dp_ppeds_handle_tx_comp,
1151 					   IRQF_SHARED | IRQF_NO_SUSPEND,
1152 					   be_soc->irq_name[2], (void *)soc);
1153 
1154 		if (ret)
1155 			goto fail;
1156 	} else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
1157 		snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
1158 			 "pci%d_reo2ppe", pci_slot);
1159 		ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
1160 					   dp_ppe_ds_reo2ppe_irq_handler,
1161 					   IRQF_SHARED | IRQF_NO_SUSPEND,
1162 					   be_soc->irq_name[0],
1163 					   dp_get_ppe_ds_ctxt(soc));
1164 
1165 		if (ret)
1166 			goto fail;
1167 	} else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
1168 		snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
1169 			 "pci%d_ppe2tcl", pci_slot);
1170 		ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
1171 					   dp_ppe_ds_ppe2tcl_irq_handler,
1172 					   IRQF_SHARED | IRQF_NO_SUSPEND,
1173 					   be_soc->irq_name[1],
1174 					   dp_get_ppe_ds_ctxt(soc));
1175 		if (ret)
1176 			goto fail;
1177 
1178 		pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
1179 	} else {
1180 		return 0;
1181 	}
1182 
1183 	srng->irq = irq;
1184 
1185 	dp_info("Registered irq %d for soc %pK ring type %d",
1186 		irq, soc, ring_type);
1187 
1188 	return 0;
1189 fail:
1190 	dp_err("Unable to config irq : ring type %d irq %d vector %d",
1191 	       ring_type, irq, vector);
1192 
1193 	return ret;
1194 }
1195 
1196 void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
1197 {
1198 	if (srng->irq >= 0)
1199 		pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
1200 }
1201 
1202 void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
1203 {
1204 	if (srng->irq >= 0)
1205 		pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
1206 }
1207 #endif
1208 
1209 #ifdef NO_RX_PKT_HDR_TLV
1210 /**
1211  * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
1212  * @soc: Common DP soc handle
1213  *
1214  * Return: QDF_STATUS
1215  */
1216 static QDF_STATUS
1217 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
1218 {
1219 	int i;
1220 	int mac_id;
1221 	struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
1222 	struct dp_srng *rx_mac_srng;
1223 	QDF_STATUS status = QDF_STATUS_SUCCESS;
1224 
1225 	/*
1226 	 * In Beryllium chipset msdu_start, mpdu_end
1227 	 * and rx_attn are part of msdu_end/mpdu_start
1228 	 */
1229 	htt_tlv_filter.msdu_start = 0;
1230 	htt_tlv_filter.mpdu_end = 0;
1231 	htt_tlv_filter.attention = 0;
1232 	htt_tlv_filter.mpdu_start = 1;
1233 	htt_tlv_filter.msdu_end = 1;
1234 	htt_tlv_filter.packet = 1;
1235 	htt_tlv_filter.packet_header = 0;
1236 
1237 	htt_tlv_filter.ppdu_start = 0;
1238 	htt_tlv_filter.ppdu_end = 0;
1239 	htt_tlv_filter.ppdu_end_user_stats = 0;
1240 	htt_tlv_filter.ppdu_end_user_stats_ext = 0;
1241 	htt_tlv_filter.ppdu_end_status_done = 0;
1242 	htt_tlv_filter.enable_fp = 1;
1243 	htt_tlv_filter.enable_md = 0;
1244 	htt_tlv_filter.enable_md = 0;
1245 	htt_tlv_filter.enable_mo = 0;
1246 
1247 	htt_tlv_filter.fp_mgmt_filter = 0;
1248 	htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
1249 	htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
1250 					 FILTER_DATA_MCAST |
1251 					 FILTER_DATA_DATA);
1252 	htt_tlv_filter.mo_mgmt_filter = 0;
1253 	htt_tlv_filter.mo_ctrl_filter = 0;
1254 	htt_tlv_filter.mo_data_filter = 0;
1255 	htt_tlv_filter.md_data_filter = 0;
1256 
1257 	htt_tlv_filter.offset_valid = true;
1258 
1259 	/* Not subscribing to mpdu_end, msdu_start and rx_attn */
1260 	htt_tlv_filter.rx_mpdu_end_offset = 0;
1261 	htt_tlv_filter.rx_msdu_start_offset = 0;
1262 	htt_tlv_filter.rx_attn_offset = 0;
1263 
1264 	/*
1265 	 * For monitor mode, the packet hdr tlv is enabled later during
1266 	 * filter update
1267 	 */
1268 	if (soc->cdp_soc.ol_ops->get_con_mode &&
1269 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
1270 		htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
1271 	else
1272 		htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
1273 
1274 	/*Not subscribing rx_pkt_header*/
1275 	htt_tlv_filter.rx_header_offset = 0;
1276 	htt_tlv_filter.rx_mpdu_start_offset =
1277 				hal_rx_mpdu_start_offset_get(soc->hal_soc);
1278 	htt_tlv_filter.rx_msdu_end_offset =
1279 				hal_rx_msdu_end_offset_get(soc->hal_soc);
1280 
1281 	dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
1282 
1283 	for (i = 0; i < MAX_PDEV_CNT; i++) {
1284 		struct dp_pdev *pdev = soc->pdev_list[i];
1285 
1286 		if (!pdev)
1287 			continue;
1288 
1289 		for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
1290 			int mac_for_pdev =
1291 				dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
1292 			/*
1293 			 * Obtain lmac id from pdev to access the LMAC ring
1294 			 * in soc context
1295 			 */
1296 			int lmac_id =
1297 				dp_get_lmac_id_for_pdev_id(soc, mac_id,
1298 							   pdev->pdev_id);
1299 
1300 			rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
1301 
1302 			if (!rx_mac_srng->hal_srng)
1303 				continue;
1304 
1305 			htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
1306 					    rx_mac_srng->hal_srng,
1307 					    RXDMA_BUF, RX_DATA_BUFFER_SIZE,
1308 					    &htt_tlv_filter);
1309 		}
1310 	}
1311 	return status;
1312 }
1313 #else
1314 /**
1315  * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
1316  * @soc: Common DP soc handle
1317  *
1318  * Return: QDF_STATUS
1319  */
1320 static QDF_STATUS
1321 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
1322 {
1323 	int i;
1324 	int mac_id;
1325 	struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
1326 	struct dp_srng *rx_mac_srng;
1327 	QDF_STATUS status = QDF_STATUS_SUCCESS;
1328 
1329 	/*
1330 	 * In Beryllium chipset msdu_start, mpdu_end
1331 	 * and rx_attn are part of msdu_end/mpdu_start
1332 	 */
1333 	htt_tlv_filter.msdu_start = 0;
1334 	htt_tlv_filter.mpdu_end = 0;
1335 	htt_tlv_filter.attention = 0;
1336 	htt_tlv_filter.mpdu_start = 1;
1337 	htt_tlv_filter.msdu_end = 1;
1338 	htt_tlv_filter.packet = 1;
1339 	htt_tlv_filter.packet_header = 1;
1340 
1341 	htt_tlv_filter.ppdu_start = 0;
1342 	htt_tlv_filter.ppdu_end = 0;
1343 	htt_tlv_filter.ppdu_end_user_stats = 0;
1344 	htt_tlv_filter.ppdu_end_user_stats_ext = 0;
1345 	htt_tlv_filter.ppdu_end_status_done = 0;
1346 	htt_tlv_filter.enable_fp = 1;
1347 	htt_tlv_filter.enable_md = 0;
1348 	htt_tlv_filter.enable_md = 0;
1349 	htt_tlv_filter.enable_mo = 0;
1350 
1351 	htt_tlv_filter.fp_mgmt_filter = 0;
1352 	htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
1353 	htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
1354 					 FILTER_DATA_MCAST |
1355 					 FILTER_DATA_DATA);
1356 	htt_tlv_filter.mo_mgmt_filter = 0;
1357 	htt_tlv_filter.mo_ctrl_filter = 0;
1358 	htt_tlv_filter.mo_data_filter = 0;
1359 	htt_tlv_filter.md_data_filter = 0;
1360 
1361 	htt_tlv_filter.offset_valid = true;
1362 
1363 	/* Not subscribing to mpdu_end, msdu_start and rx_attn */
1364 	htt_tlv_filter.rx_mpdu_end_offset = 0;
1365 	htt_tlv_filter.rx_msdu_start_offset = 0;
1366 	htt_tlv_filter.rx_attn_offset = 0;
1367 
1368 	/*
1369 	 * For monitor mode, the packet hdr tlv is enabled later during
1370 	 * filter update
1371 	 */
1372 	if (soc->cdp_soc.ol_ops->get_con_mode &&
1373 	    soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
1374 		htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
1375 	else
1376 		htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
1377 
1378 	htt_tlv_filter.rx_header_offset =
1379 				hal_rx_pkt_tlv_offset_get(soc->hal_soc);
1380 	htt_tlv_filter.rx_mpdu_start_offset =
1381 				hal_rx_mpdu_start_offset_get(soc->hal_soc);
1382 	htt_tlv_filter.rx_msdu_end_offset =
1383 				hal_rx_msdu_end_offset_get(soc->hal_soc);
1384 
1385 	dp_info("TLV subscription\n"
1386 		"msdu_start %d, mpdu_end %d, attention %d"
1387 		"mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
1388 		"TLV offsets\n"
1389 		"msdu_start %d, mpdu_end %d, attention %d"
1390 		"mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
1391 		htt_tlv_filter.msdu_start,
1392 		htt_tlv_filter.mpdu_end,
1393 		htt_tlv_filter.attention,
1394 		htt_tlv_filter.mpdu_start,
1395 		htt_tlv_filter.msdu_end,
1396 		htt_tlv_filter.packet_header,
1397 		htt_tlv_filter.packet,
1398 		htt_tlv_filter.rx_msdu_start_offset,
1399 		htt_tlv_filter.rx_mpdu_end_offset,
1400 		htt_tlv_filter.rx_attn_offset,
1401 		htt_tlv_filter.rx_mpdu_start_offset,
1402 		htt_tlv_filter.rx_msdu_end_offset,
1403 		htt_tlv_filter.rx_header_offset,
1404 		htt_tlv_filter.rx_packet_offset);
1405 
1406 	for (i = 0; i < MAX_PDEV_CNT; i++) {
1407 		struct dp_pdev *pdev = soc->pdev_list[i];
1408 
1409 		if (!pdev)
1410 			continue;
1411 
1412 		for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
1413 			int mac_for_pdev =
1414 				dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
1415 			/*
1416 			 * Obtain lmac id from pdev to access the LMAC ring
1417 			 * in soc context
1418 			 */
1419 			int lmac_id =
1420 				dp_get_lmac_id_for_pdev_id(soc, mac_id,
1421 							   pdev->pdev_id);
1422 
1423 			rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
1424 
1425 			if (!rx_mac_srng->hal_srng)
1426 				continue;
1427 
1428 			htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
1429 					    rx_mac_srng->hal_srng,
1430 					    RXDMA_BUF, RX_DATA_BUFFER_SIZE,
1431 					    &htt_tlv_filter);
1432 		}
1433 	}
1434 	return status;
1435 
1436 }
1437 #endif
1438 
1439 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
1440 /**
1441  * dp_service_near_full_srngs_be() - Main bottom half callback for the
1442  *				near-full IRQs.
1443  * @soc: Datapath SoC handle
1444  * @int_ctx: Interrupt context
1445  * @dp_budget: Budget of the work that can be done in the bottom half
1446  *
1447  * Return: work done in the handler
1448  */
1449 static uint32_t
1450 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
1451 			      uint32_t dp_budget)
1452 {
1453 	int ring = 0;
1454 	int budget = dp_budget;
1455 	uint32_t work_done  = 0;
1456 	uint32_t remaining_quota = dp_budget;
1457 	struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
1458 	int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
1459 	int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
1460 	int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
1461 	int rx_near_full_mask = rx_near_full_grp_1_mask |
1462 				rx_near_full_grp_2_mask;
1463 
1464 	dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
1465 			 rx_near_full_mask,
1466 			 tx_ring_near_full_mask);
1467 
1468 	if (rx_near_full_mask) {
1469 		for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
1470 			if (!(rx_near_full_mask & (1 << ring)))
1471 				continue;
1472 
1473 			work_done = dp_rx_nf_process(int_ctx,
1474 					soc->reo_dest_ring[ring].hal_srng,
1475 					ring, remaining_quota);
1476 			if (work_done) {
1477 				intr_stats->num_rx_ring_near_full_masks[ring]++;
1478 				dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
1479 						 rx_near_full_mask, ring,
1480 						 work_done,
1481 						 budget);
1482 				budget -=  work_done;
1483 				if (budget <= 0)
1484 					goto budget_done;
1485 				remaining_quota = budget;
1486 			}
1487 		}
1488 	}
1489 
1490 	if (tx_ring_near_full_mask) {
1491 		for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
1492 			if (!(tx_ring_near_full_mask & (1 << ring)))
1493 				continue;
1494 
1495 			work_done = dp_tx_comp_nf_handler(int_ctx, soc,
1496 					soc->tx_comp_ring[ring].hal_srng,
1497 					ring, remaining_quota);
1498 			if (work_done) {
1499 				intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
1500 				dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
1501 						 tx_ring_near_full_mask, ring,
1502 						 work_done, budget);
1503 				budget -=  work_done;
1504 				if (budget <= 0)
1505 					break;
1506 				remaining_quota = budget;
1507 			}
1508 		}
1509 	}
1510 
1511 	intr_stats->num_near_full_masks++;
1512 
1513 budget_done:
1514 	return dp_budget - budget;
1515 }
1516 
1517 /**
1518  * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
1519  *				state and set the reap_limit appropriately
1520  *				as per the near full state
1521  * @soc: Datapath soc handle
1522  * @dp_srng: Datapath handle for SRNG
1523  * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
1524  *			the srng near-full state
1525  *
1526  * Return: 1, if the srng is in near-full state
1527  *	   0, if the srng is not in near-full state
1528  */
1529 static int
1530 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
1531 				     struct dp_srng *dp_srng,
1532 				     int *max_reap_limit)
1533 {
1534 	return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
1535 }
1536 
1537 /**
1538  * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
1539  *			near full IRQ handling operations.
1540  * @arch_ops: arch ops handle
1541  *
1542  * Return: none
1543  */
1544 static inline void
1545 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
1546 {
1547 	arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
1548 	arch_ops->dp_srng_test_and_update_nf_params =
1549 					dp_srng_test_and_update_nf_params_be;
1550 }
1551 
1552 #else
1553 static inline void
1554 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
1555 {
1556 }
1557 #endif
1558 
1559 #ifdef WLAN_SUPPORT_PPEDS
1560 static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
1561 {
1562 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1563 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1564 
1565 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1566 
1567 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
1568 		return;
1569 
1570 	dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
1571 	wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
1572 			     be_soc->ppe2tcl_ring.alloc_size,
1573 			     soc->ctrl_psoc,
1574 			     WLAN_MD_DP_SRNG_PPE2TCL,
1575 			     "ppe2tcl_ring");
1576 
1577 	dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
1578 	wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
1579 			     be_soc->reo2ppe_ring.alloc_size,
1580 			     soc->ctrl_psoc,
1581 			     WLAN_MD_DP_SRNG_REO2PPE,
1582 			     "reo2ppe_ring");
1583 
1584 	dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
1585 		       WBM2_SW_PPE_REL_RING_ID);
1586 	wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
1587 			     be_soc->ppeds_wbm_release_ring.alloc_size,
1588 			     soc->ctrl_psoc,
1589 			     WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
1590 			     "ppeds_wbm_release_ring");
1591 
1592 }
1593 
1594 static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
1595 {
1596 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1597 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1598 
1599 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1600 
1601 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
1602 		return;
1603 
1604 	dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
1605 
1606 	dp_srng_free(soc, &be_soc->ppe2tcl_ring);
1607 
1608 	dp_srng_free(soc, &be_soc->reo2ppe_ring);
1609 }
1610 
1611 static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
1612 {
1613 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1614 	uint32_t entries;
1615 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1616 
1617 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1618 
1619 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
1620 		return QDF_STATUS_SUCCESS;
1621 
1622 	entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
1623 
1624 	if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
1625 			  entries, 0)) {
1626 		dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
1627 		goto fail;
1628 	}
1629 
1630 	entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
1631 	if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
1632 			  entries, 0)) {
1633 		dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
1634 		goto fail;
1635 	}
1636 
1637 	entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
1638 	if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
1639 			  entries, 1)) {
1640 		dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
1641 		       soc);
1642 		goto fail;
1643 	}
1644 
1645 	return QDF_STATUS_SUCCESS;
1646 fail:
1647 	dp_soc_ppeds_srng_free(soc);
1648 	return QDF_STATUS_E_NOMEM;
1649 }
1650 
1651 static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
1652 {
1653 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
1654 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1655 	hal_soc_handle_t hal_soc = soc->hal_soc;
1656 
1657 	struct dp_ppe_ds_idxs idx = {0};
1658 
1659 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1660 
1661 	if (!wlan_cfg_get_dp_soc_is_ppeds_enabled(soc_cfg_ctx))
1662 		return QDF_STATUS_SUCCESS;
1663 
1664 	if (dp_ppeds_register_soc_be(be_soc, &idx)) {
1665 		dp_err("%pK: ppeds registration failed", soc);
1666 		goto fail;
1667 	}
1668 
1669 	if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
1670 			     idx.reo2ppe_start_idx)) {
1671 		dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
1672 		goto fail;
1673 	}
1674 
1675 	wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
1676 			  be_soc->reo2ppe_ring.alloc_size,
1677 			  soc->ctrl_psoc,
1678 			  WLAN_MD_DP_SRNG_REO2PPE,
1679 			  "reo2ppe_ring");
1680 
1681 	hal_reo_config_reo2ppe_dest_info(hal_soc);
1682 
1683 	if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
1684 			     idx.ppe2tcl_start_idx)) {
1685 		dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
1686 		goto fail;
1687 	}
1688 
1689 	wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
1690 			  be_soc->ppe2tcl_ring.alloc_size,
1691 			  soc->ctrl_psoc,
1692 			  WLAN_MD_DP_SRNG_PPE2TCL,
1693 			  "ppe2tcl_ring");
1694 
1695 	hal_tx_config_rbm_mapping_be(soc->hal_soc,
1696 				     be_soc->ppe2tcl_ring.hal_srng,
1697 				     WBM2_SW_PPE_REL_MAP_ID);
1698 
1699 	if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
1700 			 WBM2_SW_PPE_REL_RING_ID, 0)) {
1701 		dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
1702 		       soc);
1703 		goto fail;
1704 	}
1705 
1706 	wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
1707 			     be_soc->ppeds_wbm_release_ring.alloc_size,
1708 			     soc->ctrl_psoc,
1709 			     WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
1710 			     "ppeds_wbm_release_ring");
1711 
1712 	return QDF_STATUS_SUCCESS;
1713 fail:
1714 	dp_soc_ppeds_srng_deinit(soc);
1715 	return QDF_STATUS_E_NOMEM;
1716 }
1717 #else
1718 static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
1719 {
1720 }
1721 
1722 static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
1723 {
1724 }
1725 
1726 static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
1727 {
1728 	return QDF_STATUS_SUCCESS;
1729 }
1730 
1731 static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
1732 {
1733 	return QDF_STATUS_SUCCESS;
1734 }
1735 #endif
1736 
1737 static void dp_soc_srng_deinit_be(struct dp_soc *soc)
1738 {
1739 	uint32_t i;
1740 
1741 	dp_soc_ppeds_srng_deinit(soc);
1742 
1743 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1744 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1745 			dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
1746 				       RXDMA_BUF, 0);
1747 		}
1748 	}
1749 }
1750 
1751 static void dp_soc_srng_free_be(struct dp_soc *soc)
1752 {
1753 	uint32_t i;
1754 
1755 	dp_soc_ppeds_srng_free(soc);
1756 
1757 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1758 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
1759 			dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
1760 	}
1761 }
1762 
1763 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
1764 {
1765 	struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
1766 	uint32_t ring_size;
1767 	uint32_t i;
1768 
1769 	soc_cfg_ctx = soc->wlan_cfg_ctx;
1770 
1771 	ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
1772 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1773 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1774 			if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
1775 					  RXDMA_BUF, ring_size, 0)) {
1776 				dp_err("%pK: dp_srng_alloc failed refill ring",
1777 				       soc);
1778 				goto fail;
1779 			}
1780 		}
1781 	}
1782 
1783 	if (dp_soc_ppeds_srng_alloc(soc)) {
1784 		dp_err("%pK: ppe rings alloc failed",
1785 		       soc);
1786 		goto fail;
1787 	}
1788 
1789 	return QDF_STATUS_SUCCESS;
1790 fail:
1791 	dp_soc_srng_free_be(soc);
1792 	return QDF_STATUS_E_NOMEM;
1793 }
1794 
1795 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
1796 {
1797 	int i = 0;
1798 
1799 	if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
1800 		for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
1801 			if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
1802 					 RXDMA_BUF, 0, 0)) {
1803 				dp_err("%pK: dp_srng_init failed refill ring",
1804 				       soc);
1805 				goto fail;
1806 			}
1807 		}
1808 	}
1809 
1810 	if (dp_soc_ppeds_srng_init(soc)) {
1811 		dp_err("%pK: ppe ds rings init failed",
1812 		       soc);
1813 		goto fail;
1814 	}
1815 
1816 	return QDF_STATUS_SUCCESS;
1817 fail:
1818 	dp_soc_srng_deinit_be(soc);
1819 	return QDF_STATUS_E_NOMEM;
1820 }
1821 
1822 #ifdef WLAN_FEATURE_11BE_MLO
1823 static inline unsigned
1824 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
1825 			    union dp_align_mac_addr *mac_addr)
1826 {
1827 	uint32_t index;
1828 
1829 	index =
1830 		mac_addr->align2.bytes_ab ^
1831 		mac_addr->align2.bytes_cd ^
1832 		mac_addr->align2.bytes_ef;
1833 
1834 	index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
1835 	index &= mld_hash_obj->mld_peer_hash.mask;
1836 
1837 	return index;
1838 }
1839 
1840 QDF_STATUS
1841 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
1842 				int hash_elems)
1843 {
1844 	int i, log2;
1845 
1846 	if (!mld_hash_obj)
1847 		return QDF_STATUS_E_FAILURE;
1848 
1849 	hash_elems *= DP_PEER_HASH_LOAD_MULT;
1850 	hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
1851 	log2 = dp_log2_ceil(hash_elems);
1852 	hash_elems = 1 << log2;
1853 
1854 	mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
1855 	mld_hash_obj->mld_peer_hash.idx_bits = log2;
1856 	/* allocate an array of TAILQ peer object lists */
1857 	mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
1858 		hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
1859 	if (!mld_hash_obj->mld_peer_hash.bins)
1860 		return QDF_STATUS_E_NOMEM;
1861 
1862 	for (i = 0; i < hash_elems; i++)
1863 		TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
1864 
1865 	qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
1866 
1867 	return QDF_STATUS_SUCCESS;
1868 }
1869 
1870 void
1871 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
1872 {
1873 	if (!mld_hash_obj)
1874 		return;
1875 
1876 	if (mld_hash_obj->mld_peer_hash.bins) {
1877 		qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
1878 		mld_hash_obj->mld_peer_hash.bins = NULL;
1879 		qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
1880 	}
1881 }
1882 
1883 #ifdef WLAN_MLO_MULTI_CHIP
1884 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
1885 {
1886 	/* In case of MULTI chip MLO peer hash table when MLO global object
1887 	 * is created, avoid from SOC attach path
1888 	 */
1889 	return QDF_STATUS_SUCCESS;
1890 }
1891 
1892 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
1893 {
1894 }
1895 #else
1896 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
1897 {
1898 	dp_mld_peer_hash_obj_t mld_hash_obj;
1899 
1900 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1901 
1902 	if (!mld_hash_obj)
1903 		return QDF_STATUS_E_FAILURE;
1904 
1905 	return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
1906 }
1907 
1908 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
1909 {
1910 	dp_mld_peer_hash_obj_t mld_hash_obj;
1911 
1912 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1913 
1914 	if (!mld_hash_obj)
1915 		return;
1916 
1917 	return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
1918 }
1919 #endif
1920 
1921 static struct dp_peer *
1922 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
1923 			      uint8_t *peer_mac_addr,
1924 			      int mac_addr_is_aligned,
1925 			      enum dp_mod_id mod_id,
1926 			      uint8_t vdev_id)
1927 {
1928 	union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
1929 	uint32_t index;
1930 	struct dp_peer *peer;
1931 	struct dp_vdev *vdev;
1932 	dp_mld_peer_hash_obj_t mld_hash_obj;
1933 
1934 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
1935 	if (!mld_hash_obj)
1936 		return NULL;
1937 
1938 	if (!mld_hash_obj->mld_peer_hash.bins)
1939 		return NULL;
1940 
1941 	if (mac_addr_is_aligned) {
1942 		mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
1943 	} else {
1944 		qdf_mem_copy(
1945 			&local_mac_addr_aligned.raw[0],
1946 			peer_mac_addr, QDF_MAC_ADDR_SIZE);
1947 		mac_addr = &local_mac_addr_aligned;
1948 	}
1949 
1950 	if (vdev_id != DP_VDEV_ALL) {
1951 		vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
1952 		if (!vdev) {
1953 			dp_err("vdev is null\n");
1954 			return NULL;
1955 		}
1956 	} else {
1957 		vdev = NULL;
1958 	}
1959 
1960 	/* search mld peer table if no link peer for given mac address */
1961 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
1962 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
1963 	TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
1964 		      hash_list_elem) {
1965 		if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
1966 			if ((vdev_id == DP_VDEV_ALL) || (
1967 				dp_peer_find_mac_addr_cmp(
1968 						&peer->vdev->mld_mac_addr,
1969 						&vdev->mld_mac_addr) == 0)) {
1970 				/* take peer reference before returning */
1971 				if (dp_peer_get_ref(NULL, peer, mod_id) !=
1972 						QDF_STATUS_SUCCESS)
1973 					peer = NULL;
1974 
1975 				if (vdev)
1976 					dp_vdev_unref_delete(soc, vdev, mod_id);
1977 
1978 				qdf_spin_unlock_bh(
1979 					&mld_hash_obj->mld_peer_hash_lock);
1980 				return peer;
1981 			}
1982 		}
1983 	}
1984 
1985 	if (vdev)
1986 		dp_vdev_unref_delete(soc, vdev, mod_id);
1987 
1988 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
1989 
1990 	return NULL; /* failure */
1991 }
1992 
1993 static void
1994 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
1995 {
1996 	uint32_t index;
1997 	struct dp_peer *tmppeer = NULL;
1998 	int found = 0;
1999 	dp_mld_peer_hash_obj_t mld_hash_obj;
2000 
2001 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
2002 
2003 	if (!mld_hash_obj)
2004 		return;
2005 
2006 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
2007 	QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
2008 
2009 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
2010 	TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
2011 		      hash_list_elem) {
2012 		if (tmppeer == peer) {
2013 			found = 1;
2014 			break;
2015 		}
2016 	}
2017 	QDF_ASSERT(found);
2018 	TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
2019 		     hash_list_elem);
2020 
2021 	dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
2022 		peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
2023 	dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
2024 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
2025 
2026 }
2027 
2028 static void
2029 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
2030 {
2031 	uint32_t index;
2032 	dp_mld_peer_hash_obj_t mld_hash_obj;
2033 
2034 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
2035 
2036 	if (!mld_hash_obj)
2037 		return;
2038 
2039 	index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
2040 
2041 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
2042 
2043 	if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
2044 						DP_MOD_ID_CONFIG))) {
2045 		dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
2046 		       QDF_MAC_ADDR_REF(peer->mac_addr.raw));
2047 		qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
2048 		return;
2049 	}
2050 	TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
2051 			  hash_list_elem);
2052 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
2053 
2054 	dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
2055 		peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
2056 }
2057 
2058 void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
2059 {
2060 	uint32_t index;
2061 	struct dp_peer *peer;
2062 	dp_mld_peer_hash_obj_t mld_hash_obj;
2063 
2064 	mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
2065 
2066 	if (!mld_hash_obj)
2067 		return;
2068 
2069 	qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
2070 	for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
2071 		TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
2072 			      hash_list_elem) {
2073 			dp_print_peer_ast_entries(soc, peer, NULL);
2074 		}
2075 	}
2076 	qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
2077 }
2078 
2079 #endif
2080 
2081 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
2082 static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
2083 					      struct dp_vdev *vdev)
2084 {
2085 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2086 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2087 	hal_soc_handle_t hal_soc = soc->hal_soc;
2088 	uint8_t vdev_id = vdev->vdev_id;
2089 
2090 	if (vdev->opmode == wlan_op_mode_sta) {
2091 		if (vdev->pdev->isolation)
2092 			hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
2093 						HAL_TX_MCAST_CTRL_FW_EXCEPTION);
2094 		else
2095 			hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
2096 						HAL_TX_MCAST_CTRL_MEC_NOTIFY);
2097 	} else if (vdev->opmode == wlan_op_mode_ap) {
2098 		hal_tx_mcast_mlo_reinject_routing_set(
2099 					hal_soc,
2100 					HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
2101 		if (vdev->mlo_vdev) {
2102 			hal_tx_vdev_mcast_ctrl_set(
2103 						hal_soc,
2104 						vdev_id,
2105 						HAL_TX_MCAST_CTRL_NO_SPECIAL);
2106 		} else {
2107 			hal_tx_vdev_mcast_ctrl_set(hal_soc,
2108 						   vdev_id,
2109 						   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
2110 		}
2111 	}
2112 }
2113 
2114 static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
2115 {
2116 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2117 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2118 	union hal_tx_bank_config *bank_config;
2119 
2120 	if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
2121 		return;
2122 
2123 	bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
2124 
2125 	hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
2126 				      be_vdev->bank_id);
2127 }
2128 
2129 #endif
2130 
2131 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
2132 	defined(WLAN_MCAST_MLO)
2133 static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
2134 					 struct dp_vdev *ptnr_vdev,
2135 					 void *arg)
2136 {
2137 	struct dp_vdev_be *be_ptnr_vdev =
2138 				dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
2139 
2140 	be_ptnr_vdev->mcast_primary = false;
2141 }
2142 
2143 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
2144 					struct dp_vdev *vdev,
2145 					cdp_config_param_type val)
2146 {
2147 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2148 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
2149 						be_vdev->vdev.pdev->soc);
2150 
2151 	be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
2152 	vdev->mlo_vdev = true;
2153 	hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
2154 				   vdev->vdev_id,
2155 				   HAL_TX_MCAST_CTRL_NO_SPECIAL);
2156 
2157 	if (be_vdev->mcast_primary) {
2158 		dp_mcast_mlo_iter_ptnr_vdev(be_soc, be_vdev,
2159 					    dp_mlo_mcast_reset_pri_mcast,
2160 					    (void *)&be_vdev->mcast_primary,
2161 					    DP_MOD_ID_TX_MCAST);
2162 	}
2163 }
2164 
2165 static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
2166 					struct dp_vdev *vdev,
2167 					cdp_config_param_type val)
2168 {
2169 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2170 
2171 	be_vdev->mcast_primary = false;
2172 	vdev->mlo_vdev = false;
2173 	hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
2174 				   vdev->vdev_id,
2175 				   HAL_TX_MCAST_CTRL_FW_EXCEPTION);
2176 }
2177 
2178 /**
2179  * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
2180  *                                      params related to multicast
2181  * @soc: DP soc handle
2182  * @vdev: pointer to vdev structure
2183  * @val: buffer address
2184  *
2185  * Return: QDF_STATUS
2186  */
2187 static
2188 QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
2189 					   struct dp_vdev *vdev,
2190 					   cdp_config_param_type *val)
2191 {
2192 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2193 
2194 	if (be_vdev->mcast_primary)
2195 		val->cdp_vdev_param_mcast_vdev = true;
2196 	else
2197 		val->cdp_vdev_param_mcast_vdev = false;
2198 
2199 	return QDF_STATUS_SUCCESS;
2200 }
2201 #else
2202 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
2203 					struct dp_vdev *vdev,
2204 					cdp_config_param_type val)
2205 {
2206 }
2207 
2208 static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
2209 					struct dp_vdev *vdev,
2210 					cdp_config_param_type val)
2211 {
2212 }
2213 
2214 static
2215 QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
2216 					   struct dp_vdev *vdev,
2217 					   cdp_config_param_type *val)
2218 {
2219 	return QDF_STATUS_SUCCESS;
2220 }
2221 #endif
2222 
2223 #ifdef DP_TX_IMPLICIT_RBM_MAPPING
2224 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
2225 				      uint8_t tx_ring_id,
2226 				      uint8_t bm_id)
2227 {
2228 	hal_tx_config_rbm_mapping_be(soc->hal_soc,
2229 				     soc->tcl_data_ring[tx_ring_id].hal_srng,
2230 				     bm_id);
2231 }
2232 #else
2233 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
2234 				      uint8_t tx_ring_id,
2235 				      uint8_t bm_id)
2236 {
2237 }
2238 #endif
2239 
2240 /**
2241  * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
2242  * @soc: DP soc handle
2243  * @vdev: pointer to vdev structure
2244  * @param: parameter type to get value
2245  * @val: value
2246  *
2247  * Return: QDF_STATUS
2248  */
2249 static
2250 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
2251 				     struct dp_vdev *vdev,
2252 				     enum cdp_vdev_param_type param,
2253 				     cdp_config_param_type val)
2254 {
2255 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2256 	struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
2257 
2258 	switch (param) {
2259 	case CDP_TX_ENCAP_TYPE:
2260 	case CDP_UPDATE_DSCP_TO_TID_MAP:
2261 	case CDP_UPDATE_TDLS_FLAGS:
2262 		dp_tx_update_bank_profile(be_soc, be_vdev);
2263 		break;
2264 	case CDP_ENABLE_CIPHER:
2265 		if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
2266 			dp_tx_update_bank_profile(be_soc, be_vdev);
2267 		break;
2268 	case CDP_SET_MCAST_VDEV:
2269 		dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
2270 		break;
2271 	case CDP_RESET_MLO_MCAST_VDEV:
2272 		dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
2273 		break;
2274 	default:
2275 		dp_warn("invalid param %d", param);
2276 		break;
2277 	}
2278 
2279 	return QDF_STATUS_SUCCESS;
2280 }
2281 
2282 #ifdef WLAN_FEATURE_11BE_MLO
2283 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
2284 static inline void
2285 dp_soc_max_peer_id_set(struct dp_soc *soc)
2286 {
2287 	soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
2288 	soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
2289 	/*
2290 	 * Double the peers since we use ML indication bit
2291 	 * alongwith peer_id to find peers.
2292 	 */
2293 	soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
2294 }
2295 #else
2296 static inline void
2297 dp_soc_max_peer_id_set(struct dp_soc *soc)
2298 {
2299 	soc->max_peer_id =
2300 		(1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
2301 }
2302 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
2303 #else
2304 static inline void
2305 dp_soc_max_peer_id_set(struct dp_soc *soc)
2306 {
2307 	soc->max_peer_id = soc->max_peers;
2308 }
2309 #endif /* WLAN_FEATURE_11BE_MLO */
2310 
2311 static void dp_peer_map_detach_be(struct dp_soc *soc)
2312 {
2313 	if (soc->host_ast_db_enable)
2314 		dp_peer_ast_hash_detach(soc);
2315 }
2316 
2317 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
2318 {
2319 	QDF_STATUS status;
2320 
2321 	if (soc->host_ast_db_enable) {
2322 		status = dp_peer_ast_hash_attach(soc);
2323 		if (QDF_IS_STATUS_ERROR(status))
2324 			return status;
2325 	}
2326 
2327 	dp_soc_max_peer_id_set(soc);
2328 
2329 	return QDF_STATUS_SUCCESS;
2330 }
2331 
2332 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
2333 						  uint8_t *dest_mac,
2334 						  uint8_t vdev_id)
2335 {
2336 	struct dp_peer *peer = NULL;
2337 	struct dp_peer *tgt_peer = NULL;
2338 	struct dp_ast_entry *ast_entry = NULL;
2339 	uint16_t peer_id;
2340 
2341 	qdf_spin_lock_bh(&soc->ast_lock);
2342 	ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
2343 	if (!ast_entry) {
2344 		qdf_spin_unlock_bh(&soc->ast_lock);
2345 		dp_err("NULL ast entry");
2346 		return NULL;
2347 	}
2348 
2349 	peer_id = ast_entry->peer_id;
2350 	qdf_spin_unlock_bh(&soc->ast_lock);
2351 
2352 	if (peer_id == HTT_INVALID_PEER)
2353 		return NULL;
2354 
2355 	peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
2356 	if (!peer) {
2357 		dp_err("NULL peer for peer_id:%d", peer_id);
2358 		return NULL;
2359 	}
2360 
2361 	tgt_peer = dp_get_tgt_peer_from_peer(peer);
2362 
2363 	/*
2364 	 * Once tgt_peer is obtained,
2365 	 * release the ref taken for original peer.
2366 	 */
2367 	dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
2368 	dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
2369 
2370 	return tgt_peer;
2371 }
2372 
2373 #ifdef WLAN_FEATURE_11BE_MLO
2374 #ifdef WLAN_MCAST_MLO
2375 static inline void
2376 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
2377 {
2378 	arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
2379 	arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
2380 	arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
2381 }
2382 #else /* WLAN_MCAST_MLO */
2383 static inline void
2384 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
2385 {
2386 }
2387 #endif /* WLAN_MCAST_MLO */
2388 
2389 #ifdef WLAN_MLO_MULTI_CHIP
2390 static inline void
2391 dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
2392 {
2393 	arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
2394 	arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
2395 	arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
2396 }
2397 #else
2398 static inline void
2399 dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
2400 {
2401 }
2402 #endif
2403 
2404 static inline void
2405 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
2406 {
2407 	dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
2408 	dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
2409 	arch_ops->mlo_peer_find_hash_detach =
2410 	dp_mlo_peer_find_hash_detach_wrapper;
2411 	arch_ops->mlo_peer_find_hash_attach =
2412 	dp_mlo_peer_find_hash_attach_wrapper;
2413 	arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
2414 	arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
2415 	arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
2416 }
2417 #else /* WLAN_FEATURE_11BE_MLO */
2418 static inline void
2419 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
2420 {
2421 }
2422 #endif /* WLAN_FEATURE_11BE_MLO */
2423 
2424 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
2425 #define DP_LMAC_PEER_ID_MSB_LEGACY 2
2426 #define DP_LMAC_PEER_ID_MSB_MLO 3
2427 
2428 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
2429 				    struct cdp_peer_setup_info *setup_info,
2430 				    enum cdp_host_reo_dest_ring *reo_dest,
2431 				    bool *hash_based,
2432 				    uint8_t *lmac_peer_id_msb)
2433 {
2434 	struct dp_soc *soc = vdev->pdev->soc;
2435 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2436 
2437 	if (!be_soc->mlo_enabled)
2438 		return dp_vdev_get_default_reo_hash(vdev, reo_dest,
2439 						    hash_based);
2440 
2441 	*hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
2442 	*reo_dest = vdev->pdev->reo_dest;
2443 
2444 	/* Not a ML link peer use non-mlo */
2445 	if (!setup_info) {
2446 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
2447 		return;
2448 	}
2449 
2450 	/* For STA ML VAP we do not have num links info at this point
2451 	 * use MLO case always
2452 	 */
2453 	if (vdev->opmode == wlan_op_mode_sta) {
2454 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
2455 		return;
2456 	}
2457 
2458 	/* For AP ML VAP consider the peer as ML only it associates with
2459 	 * multiple links
2460 	 */
2461 	if (setup_info->num_links == 1) {
2462 		*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
2463 		return;
2464 	}
2465 
2466 	*lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
2467 }
2468 
2469 static bool dp_reo_remap_config_be(struct dp_soc *soc,
2470 				   uint32_t *remap0,
2471 				   uint32_t *remap1,
2472 				   uint32_t *remap2)
2473 {
2474 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2475 	uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
2476 	uint32_t reo_mlo_config =
2477 		wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
2478 
2479 	if (!be_soc->mlo_enabled)
2480 		return dp_reo_remap_config(soc, remap0, remap1, remap2);
2481 
2482 	*remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
2483 	*remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
2484 	*remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
2485 
2486 	return true;
2487 }
2488 #else
2489 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
2490 				    struct cdp_peer_setup_info *setup_info,
2491 				    enum cdp_host_reo_dest_ring *reo_dest,
2492 				    bool *hash_based,
2493 				    uint8_t *lmac_peer_id_msb)
2494 {
2495 	dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
2496 }
2497 
2498 static bool dp_reo_remap_config_be(struct dp_soc *soc,
2499 				   uint32_t *remap0,
2500 				   uint32_t *remap1,
2501 				   uint32_t *remap2)
2502 {
2503 	return dp_reo_remap_config(soc, remap0, remap1, remap2);
2504 }
2505 #endif
2506 
2507 #ifdef IPA_OFFLOAD
2508 static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
2509 {
2510 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
2511 
2512 	return be_soc->ipa_bank_id;
2513 }
2514 
2515 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
2516 {
2517 	arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
2518 }
2519 #else /* !IPA_OFFLOAD */
2520 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
2521 {
2522 }
2523 #endif /* IPA_OFFLOAD */
2524 
2525 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
2526 {
2527 #ifndef QCA_HOST_MODE_WIFI_DISABLED
2528 	arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
2529 	arch_ops->dp_rx_process = dp_rx_process_be;
2530 	arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
2531 	arch_ops->tx_comp_get_params_from_hal_desc =
2532 		dp_tx_comp_get_params_from_hal_desc_be;
2533 	arch_ops->dp_tx_process_htt_completion =
2534 				dp_tx_process_htt_completion_be;
2535 	arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
2536 	arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
2537 	arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
2538 	arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
2539 	arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
2540 				dp_wbm_get_rx_desc_from_hal_desc_be;
2541 	arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
2542 	arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
2543 #endif
2544 	arch_ops->txrx_get_context_size = dp_get_context_size_be;
2545 #ifdef WIFI_MONITOR_SUPPORT
2546 	arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
2547 #endif
2548 	arch_ops->dp_rx_desc_cookie_2_va =
2549 			dp_rx_desc_cookie_2_va_be;
2550 	arch_ops->dp_rx_intrabss_mcast_handler =
2551 				dp_rx_intrabss_mcast_handler_be;
2552 	arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
2553 
2554 	arch_ops->txrx_soc_attach = dp_soc_attach_be;
2555 	arch_ops->txrx_soc_detach = dp_soc_detach_be;
2556 	arch_ops->txrx_soc_init = dp_soc_init_be;
2557 	arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
2558 	arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
2559 	arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
2560 	arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
2561 	arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
2562 	arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
2563 	arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
2564 	arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
2565 	arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
2566 	arch_ops->txrx_peer_setup = dp_peer_setup_be;
2567 	arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
2568 	arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
2569 	arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
2570 	arch_ops->dp_rx_peer_metadata_peer_id_get =
2571 					dp_rx_peer_metadata_peer_id_get_be;
2572 	arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
2573 	arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
2574 	arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
2575 	dp_initialize_arch_ops_be_mlo(arch_ops);
2576 	arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
2577 	arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
2578 	arch_ops->dp_peer_rx_reorder_queue_setup =
2579 					dp_peer_rx_reorder_queue_setup_be;
2580 	arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
2581 	arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
2582 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
2583 	arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
2584 	arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
2585 					dp_reconfig_tx_vdev_mcast_ctrl_be;
2586 	arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
2587 #endif
2588 
2589 #ifdef WLAN_SUPPORT_PPEDS
2590 	arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
2591 	arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
2592 	arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
2593 	arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
2594 	arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
2595 	arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
2596 	arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
2597 				dp_tx_ppeds_cfg_astidx_cache_mapping;
2598 #endif
2599 	dp_init_near_full_arch_ops_be(arch_ops);
2600 	arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
2601 	arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
2602 	arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
2603 	arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
2604 	arch_ops->dp_rx_fst_deref = dp_rx_fst_deref_be;
2605 	arch_ops->dp_rx_fst_ref = dp_rx_fst_ref_be;
2606 	arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
2607 	arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
2608 	arch_ops->reo_remap_config = dp_reo_remap_config_be;
2609 	arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
2610 	dp_initialize_arch_ops_be_ipa(arch_ops);
2611 }
2612