1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <wlan_utility.h> 21 #include <dp_internal.h> 22 #include <dp_htt.h> 23 #include "dp_be.h" 24 #include "dp_be_tx.h" 25 #include "dp_be_rx.h" 26 #ifdef WIFI_MONITOR_SUPPORT 27 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT) 28 #include "dp_mon_2.0.h" 29 #endif 30 #include "dp_mon.h" 31 #endif 32 #include <hal_be_api.h> 33 34 /* Generic AST entry aging timer value */ 35 #define DP_AST_AGING_TIMER_DEFAULT_MS 5000 36 37 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 38 #define DP_TX_VDEV_ID_CHECK_ENABLE 0 39 40 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 41 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 42 {1, 4, HAL_BE_WBM_SW4_BM_ID, 0}, 43 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 44 #ifdef QCA_WIFI_KIWI_V2 45 {3, 5, HAL_BE_WBM_SW5_BM_ID, 0}, 46 {4, 6, HAL_BE_WBM_SW6_BM_ID, 0} 47 #else 48 {3, 6, HAL_BE_WBM_SW5_BM_ID, 0}, 49 {4, 7, HAL_BE_WBM_SW6_BM_ID, 0} 50 #endif 51 }; 52 #else 53 #define DP_TX_VDEV_ID_CHECK_ENABLE 1 54 55 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 56 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 57 {1, 1, HAL_BE_WBM_SW1_BM_ID, 0}, 58 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 59 {3, 3, HAL_BE_WBM_SW3_BM_ID, 0}, 60 {4, 4, HAL_BE_WBM_SW4_BM_ID, 0} 61 }; 62 #endif 63 64 #ifdef WLAN_SUPPORT_PPEDS 65 static void dp_ppeds_rings_status(struct dp_soc *soc) 66 { 67 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 68 69 dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE); 70 dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL); 71 } 72 #endif 73 74 static void dp_soc_cfg_attach_be(struct dp_soc *soc) 75 { 76 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx; 77 78 wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM); 79 80 soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array; 81 82 /* this is used only when dmac mode is enabled */ 83 soc->num_rx_refill_buf_rings = 1; 84 85 soc->wlan_cfg_ctx->notify_frame_support = 86 DP_MARK_NOTIFY_FRAME_SUPPORT; 87 } 88 89 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type) 90 { 91 switch (context_type) { 92 case DP_CONTEXT_TYPE_SOC: 93 return sizeof(struct dp_soc_be); 94 case DP_CONTEXT_TYPE_PDEV: 95 return sizeof(struct dp_pdev_be); 96 case DP_CONTEXT_TYPE_VDEV: 97 return sizeof(struct dp_vdev_be); 98 case DP_CONTEXT_TYPE_PEER: 99 return sizeof(struct dp_peer_be); 100 default: 101 return 0; 102 } 103 } 104 105 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION 106 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 107 /** 108 * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement 109 per wbm2sw ring 110 * @cc_cfg: HAL HW cookie conversion configuration structure pointer 111 * 112 * Return: None 113 */ 114 static inline 115 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 116 { 117 cc_cfg->wbm2sw6_cc_en = 1; 118 cc_cfg->wbm2sw5_cc_en = 1; 119 cc_cfg->wbm2sw4_cc_en = 1; 120 cc_cfg->wbm2sw3_cc_en = 1; 121 cc_cfg->wbm2sw2_cc_en = 1; 122 /* disable wbm2sw1 hw cc as it's for FW */ 123 cc_cfg->wbm2sw1_cc_en = 0; 124 cc_cfg->wbm2sw0_cc_en = 1; 125 cc_cfg->wbm2fw_cc_en = 0; 126 } 127 #else 128 static inline 129 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 130 { 131 cc_cfg->wbm2sw6_cc_en = 1; 132 cc_cfg->wbm2sw5_cc_en = 1; 133 cc_cfg->wbm2sw4_cc_en = 1; 134 cc_cfg->wbm2sw3_cc_en = 1; 135 cc_cfg->wbm2sw2_cc_en = 1; 136 cc_cfg->wbm2sw1_cc_en = 1; 137 cc_cfg->wbm2sw0_cc_en = 1; 138 cc_cfg->wbm2fw_cc_en = 0; 139 } 140 #endif 141 142 #if defined(WLAN_SUPPORT_RX_FISA) 143 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 144 { 145 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 146 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 147 /* get CMEM for cookie conversion */ 148 if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) { 149 dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size); 150 return QDF_STATUS_E_NOMEM; 151 } 152 153 soc->fst_cmem_size = DP_CMEM_FST_SIZE; 154 155 soc->fst_cmem_base = soc->cmem_base + 156 (soc->cmem_total_size - soc->cmem_avail_size); 157 soc->cmem_avail_size -= soc->fst_cmem_size; 158 159 dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx", 160 soc->fst_cmem_base, soc->fst_cmem_size); 161 162 return QDF_STATUS_SUCCESS; 163 } 164 #else /* !WLAN_SUPPORT_RX_FISA */ 165 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 166 { 167 return QDF_STATUS_SUCCESS; 168 } 169 #endif 170 171 /** 172 * dp_cc_reg_cfg_init() - initialize and configure HW cookie 173 conversion register 174 * @soc: SOC handle 175 * @is_4k_align: page address 4k aligned 176 * 177 * Return: None 178 */ 179 static void dp_cc_reg_cfg_init(struct dp_soc *soc, 180 bool is_4k_align) 181 { 182 struct hal_hw_cc_config cc_cfg = { 0 }; 183 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 184 185 if (soc->cdp_soc.ol_ops->get_con_mode && 186 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE) 187 return; 188 189 if (!soc->wlan_cfg_ctx->hw_cc_enabled) { 190 dp_info("INI skip HW CC register setting"); 191 return; 192 } 193 194 cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base; 195 cc_cfg.cc_global_en = true; 196 cc_cfg.page_4k_align = is_4k_align; 197 cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB; 198 cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB; 199 /* 36th bit should be 1 then HW know this is CMEM address */ 200 cc_cfg.lut_base_addr_39_32 = 0x10; 201 202 cc_cfg.error_path_cookie_conv_en = true; 203 cc_cfg.release_path_cookie_conv_en = true; 204 dp_cc_wbm_sw_en_cfg(&cc_cfg); 205 206 hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg); 207 } 208 209 /** 210 * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing 211 * @hal_soc_hdl: HAL SOC handle 212 * @offset: CMEM address 213 * @value: value to write 214 * 215 * Return: None. 216 */ 217 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 218 uint32_t offset, 219 uint32_t value) 220 { 221 hal_cmem_write(hal_soc_hdl, offset, value); 222 } 223 224 /** 225 * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for 226 HW cookie conversion 227 * @soc: SOC handle 228 * @cc_ctx: cookie conversion context pointer 229 * 230 * Return: 0 in case of success, else error value 231 */ 232 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 233 { 234 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 235 236 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 237 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 238 /* get CMEM for cookie conversion */ 239 if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) { 240 dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size); 241 return QDF_STATUS_E_RESOURCES; 242 } 243 be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base + 244 DP_CC_MEM_OFFSET_IN_CMEM); 245 246 soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE; 247 248 dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx", 249 be_soc->cc_cmem_base, soc->cmem_avail_size); 250 return QDF_STATUS_SUCCESS; 251 } 252 253 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 254 uint8_t for_feature) 255 { 256 QDF_STATUS status = QDF_STATUS_E_NOMEM; 257 258 switch (for_feature) { 259 case COOKIE_CONVERSION: 260 status = dp_hw_cc_cmem_addr_init(soc); 261 break; 262 case FISA_FST: 263 status = dp_fisa_fst_cmem_addr_init(soc); 264 break; 265 default: 266 dp_err("Invalid CMEM request"); 267 } 268 269 return status; 270 } 271 272 #else 273 274 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc, 275 bool is_4k_align) {} 276 277 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 278 uint32_t offset, 279 uint32_t value) 280 { } 281 282 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 283 { 284 return QDF_STATUS_SUCCESS; 285 } 286 287 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 288 uint8_t for_feature) 289 { 290 return QDF_STATUS_SUCCESS; 291 } 292 293 #endif 294 295 QDF_STATUS 296 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc, 297 struct dp_hw_cookie_conversion_t *cc_ctx, 298 uint32_t num_descs, 299 enum dp_desc_type desc_type, 300 uint8_t desc_pool_id) 301 { 302 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 303 uint32_t num_spt_pages, i = 0; 304 struct dp_spt_page_desc *spt_desc; 305 struct qdf_mem_dma_page_t *dma_page; 306 uint8_t chip_id; 307 308 /* estimate how many SPT DDR pages needed */ 309 num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES; 310 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 311 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 312 dp_info("num_spt_pages needed %d", num_spt_pages); 313 314 dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE, 315 &cc_ctx->page_pool, qdf_page_size, 316 num_spt_pages, 0, false); 317 if (!cc_ctx->page_pool.dma_pages) { 318 dp_err("spt ddr pages allocation failed"); 319 return QDF_STATUS_E_RESOURCES; 320 } 321 cc_ctx->page_desc_base = qdf_mem_malloc( 322 num_spt_pages * sizeof(struct dp_spt_page_desc)); 323 if (!cc_ctx->page_desc_base) { 324 dp_err("spt page descs allocation failed"); 325 goto fail_0; 326 } 327 328 chip_id = dp_mlo_get_chip_id(soc); 329 cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id, 330 desc_type); 331 332 /* initial page desc */ 333 spt_desc = cc_ctx->page_desc_base; 334 dma_page = cc_ctx->page_pool.dma_pages; 335 while (i < num_spt_pages) { 336 /* check if page address 4K aligned */ 337 if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) { 338 dp_err("non-4k aligned pages addr %pK", 339 (void *)dma_page[i].page_p_addr); 340 goto fail_1; 341 } 342 343 spt_desc[i].page_v_addr = 344 dma_page[i].page_v_addr_start; 345 spt_desc[i].page_p_addr = 346 dma_page[i].page_p_addr; 347 i++; 348 } 349 350 cc_ctx->total_page_num = num_spt_pages; 351 qdf_spinlock_create(&cc_ctx->cc_lock); 352 353 return QDF_STATUS_SUCCESS; 354 fail_1: 355 qdf_mem_free(cc_ctx->page_desc_base); 356 fail_0: 357 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 358 &cc_ctx->page_pool, 0, false); 359 360 return QDF_STATUS_E_FAILURE; 361 } 362 363 QDF_STATUS 364 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc, 365 struct dp_hw_cookie_conversion_t *cc_ctx) 366 { 367 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 368 369 qdf_mem_free(cc_ctx->page_desc_base); 370 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 371 &cc_ctx->page_pool, 0, false); 372 qdf_spinlock_destroy(&cc_ctx->cc_lock); 373 374 return QDF_STATUS_SUCCESS; 375 } 376 377 QDF_STATUS 378 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc, 379 struct dp_hw_cookie_conversion_t *cc_ctx) 380 { 381 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 382 uint32_t i = 0; 383 struct dp_spt_page_desc *spt_desc; 384 uint32_t ppt_index; 385 uint32_t ppt_id_start; 386 387 if (!cc_ctx->total_page_num) { 388 dp_err("total page num is 0"); 389 return QDF_STATUS_E_INVAL; 390 } 391 392 ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset); 393 spt_desc = cc_ctx->page_desc_base; 394 while (i < cc_ctx->total_page_num) { 395 /* write page PA to CMEM */ 396 dp_hw_cc_cmem_write(soc->hal_soc, 397 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 398 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 399 (spt_desc[i].page_p_addr >> 400 DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED)); 401 402 ppt_index = ppt_id_start + i; 403 404 if (ppt_index >= DP_CC_PPT_MAX_ENTRIES) 405 qdf_assert_always(0); 406 407 spt_desc[i].ppt_index = ppt_index; 408 409 be_soc->page_desc_base[ppt_index].page_v_addr = 410 spt_desc[i].page_v_addr; 411 i++; 412 } 413 return QDF_STATUS_SUCCESS; 414 } 415 416 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 417 QDF_STATUS 418 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 419 struct dp_hw_cookie_conversion_t *cc_ctx) 420 { 421 uint32_t ppt_index; 422 struct dp_spt_page_desc *spt_desc; 423 int i = 0; 424 425 spt_desc = cc_ctx->page_desc_base; 426 while (i < cc_ctx->total_page_num) { 427 ppt_index = spt_desc[i].ppt_index; 428 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 429 i++; 430 } 431 return QDF_STATUS_SUCCESS; 432 } 433 #else 434 QDF_STATUS 435 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 436 struct dp_hw_cookie_conversion_t *cc_ctx) 437 { 438 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 439 uint32_t ppt_index; 440 struct dp_spt_page_desc *spt_desc; 441 int i = 0; 442 443 spt_desc = cc_ctx->page_desc_base; 444 while (i < cc_ctx->total_page_num) { 445 /* reset PA in CMEM to NULL */ 446 dp_hw_cc_cmem_write(soc->hal_soc, 447 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 448 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 449 0); 450 451 ppt_index = spt_desc[i].ppt_index; 452 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 453 i++; 454 } 455 return QDF_STATUS_SUCCESS; 456 } 457 #endif 458 459 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc) 460 { 461 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 462 int i = 0; 463 464 465 for (i = 0; i < MAX_TXDESC_POOLS; i++) 466 dp_hw_cookie_conversion_detach(be_soc, 467 &be_soc->tx_cc_ctx[i]); 468 469 for (i = 0; i < MAX_RXDESC_POOLS; i++) 470 dp_hw_cookie_conversion_detach(be_soc, 471 &be_soc->rx_cc_ctx[i]); 472 473 qdf_mem_free(be_soc->page_desc_base); 474 be_soc->page_desc_base = NULL; 475 476 return QDF_STATUS_SUCCESS; 477 } 478 479 #ifdef WLAN_MLO_MULTI_CHIP 480 #ifdef WLAN_MCAST_MLO 481 static inline void 482 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 483 { 484 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 485 486 be_vdev->mcast_primary = false; 487 be_vdev->seq_num = 0; 488 dp_tx_mcast_mlo_reinject_routing_set(soc, 489 (void *)&be_vdev->mcast_primary); 490 if (vdev->opmode == wlan_op_mode_ap) { 491 if (vdev->mlo_vdev) 492 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 493 vdev->vdev_id, 494 HAL_TX_MCAST_CTRL_DROP); 495 else 496 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 497 vdev->vdev_id, 498 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 499 } 500 } 501 502 static inline void 503 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 504 { 505 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 506 507 be_vdev->seq_num = 0; 508 be_vdev->mcast_primary = false; 509 vdev->mlo_vdev = false; 510 } 511 #else 512 static inline void 513 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 514 { 515 } 516 517 static inline void 518 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 519 { 520 } 521 #endif 522 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 523 { 524 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 525 526 qdf_mem_set(be_vdev->partner_vdev_list, 527 WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC, 528 CDP_INVALID_VDEV_ID); 529 } 530 531 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 532 struct cdp_lro_hash_config *lro_hash) 533 { 534 dp_mlo_get_rx_hash_key(soc, lro_hash); 535 } 536 #else 537 static inline void 538 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 539 { 540 } 541 542 static inline void 543 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 544 { 545 } 546 547 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 548 { 549 } 550 551 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 552 struct cdp_lro_hash_config *lro_hash) 553 { 554 dp_get_rx_hash_key_bytes(lro_hash); 555 } 556 #endif 557 558 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc, 559 struct cdp_soc_attach_params *params) 560 { 561 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 562 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 563 uint32_t max_tx_rx_desc_num, num_spt_pages; 564 uint32_t num_entries; 565 int i = 0; 566 567 max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS + 568 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS; 569 /* estimate how many SPT DDR pages needed */ 570 num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES; 571 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 572 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 573 574 be_soc->page_desc_base = qdf_mem_malloc( 575 DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc)); 576 if (!be_soc->page_desc_base) { 577 dp_err("spt page descs allocation failed"); 578 return QDF_STATUS_E_NOMEM; 579 } 580 581 soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id(); 582 583 qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION); 584 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 585 goto fail; 586 587 dp_soc_mlo_fill_params(soc, params); 588 589 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 590 num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx); 591 qdf_status = 592 dp_hw_cookie_conversion_attach(be_soc, 593 &be_soc->tx_cc_ctx[i], 594 num_entries, 595 DP_TX_DESC_TYPE, i); 596 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 597 goto fail; 598 } 599 600 qdf_status = dp_get_cmem_allocation(soc, FISA_FST); 601 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 602 goto fail; 603 604 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 605 num_entries = 606 wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx); 607 qdf_status = 608 dp_hw_cookie_conversion_attach(be_soc, 609 &be_soc->rx_cc_ctx[i], 610 num_entries, 611 DP_RX_DESC_BUF_TYPE, i); 612 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 613 goto fail; 614 } 615 616 return qdf_status; 617 fail: 618 dp_soc_detach_be(soc); 619 return qdf_status; 620 } 621 622 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc) 623 { 624 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 625 int i = 0; 626 627 dp_tx_deinit_bank_profiles(be_soc); 628 for (i = 0; i < MAX_TXDESC_POOLS; i++) 629 dp_hw_cookie_conversion_deinit(be_soc, 630 &be_soc->tx_cc_ctx[i]); 631 632 for (i = 0; i < MAX_RXDESC_POOLS; i++) 633 dp_hw_cookie_conversion_deinit(be_soc, 634 &be_soc->rx_cc_ctx[i]); 635 636 return QDF_STATUS_SUCCESS; 637 } 638 639 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc) 640 { 641 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 642 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 643 int i = 0; 644 645 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 646 qdf_status = 647 dp_hw_cookie_conversion_init(be_soc, 648 &be_soc->tx_cc_ctx[i]); 649 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 650 goto fail; 651 } 652 653 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 654 qdf_status = 655 dp_hw_cookie_conversion_init(be_soc, 656 &be_soc->rx_cc_ctx[i]); 657 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 658 goto fail; 659 } 660 661 /* route vdev_id mismatch notification via FW completion */ 662 hal_tx_vdev_mismatch_routing_set(soc->hal_soc, 663 HAL_TX_VDEV_MISMATCH_FW_NOTIFY); 664 665 qdf_status = dp_tx_init_bank_profiles(be_soc); 666 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 667 goto fail; 668 669 /* write WBM/REO cookie conversion CFG register */ 670 dp_cc_reg_cfg_init(soc, true); 671 672 return qdf_status; 673 fail: 674 dp_soc_deinit_be(soc); 675 return qdf_status; 676 } 677 678 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev, 679 struct cdp_pdev_attach_params *params) 680 { 681 dp_pdev_mlo_fill_params(pdev, params); 682 dp_mlo_update_link_to_pdev_map(pdev->soc, pdev); 683 684 return QDF_STATUS_SUCCESS; 685 } 686 687 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev) 688 { 689 dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev); 690 691 return QDF_STATUS_SUCCESS; 692 } 693 694 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev) 695 { 696 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 697 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 698 struct dp_pdev *pdev = vdev->pdev; 699 700 if (vdev->opmode == wlan_op_mode_monitor) 701 return QDF_STATUS_SUCCESS; 702 703 be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE; 704 705 be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev); 706 vdev->bank_id = be_vdev->bank_id; 707 708 if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) { 709 QDF_BUG(0); 710 return QDF_STATUS_E_FAULT; 711 } 712 713 if (vdev->opmode == wlan_op_mode_sta) { 714 if (soc->cdp_soc.ol_ops->set_mec_timer) 715 soc->cdp_soc.ol_ops->set_mec_timer( 716 soc->ctrl_psoc, 717 vdev->vdev_id, 718 DP_AST_AGING_TIMER_DEFAULT_MS); 719 720 if (pdev->isolation) 721 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 722 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 723 else 724 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 725 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 726 } 727 728 dp_mlo_mcast_init(soc, vdev); 729 dp_mlo_init_ptnr_list(vdev); 730 731 return QDF_STATUS_SUCCESS; 732 } 733 734 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev) 735 { 736 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 737 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 738 739 if (vdev->opmode == wlan_op_mode_monitor) 740 return QDF_STATUS_SUCCESS; 741 742 if (vdev->opmode == wlan_op_mode_ap) 743 dp_mlo_mcast_deinit(soc, vdev); 744 745 dp_tx_put_bank_profile(be_soc, be_vdev); 746 dp_clr_mlo_ptnr_list(soc, vdev); 747 748 return QDF_STATUS_SUCCESS; 749 } 750 751 qdf_size_t dp_get_soc_context_size_be(void) 752 { 753 return sizeof(struct dp_soc_be); 754 } 755 756 #ifdef CONFIG_WORD_BASED_TLV 757 /** 758 * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config 759 * @soc: Common DP soc handle 760 * @htt_tlv_filter: Rx SRNG TLV and filter setting 761 * 762 * Return: none 763 */ 764 static inline void 765 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc, 766 struct htt_rx_ring_tlv_filter *htt_tlv_filter) 767 { 768 htt_tlv_filter->rx_msdu_end_wmask = 769 hal_rx_msdu_end_wmask_get(soc->hal_soc); 770 htt_tlv_filter->rx_mpdu_start_wmask = 771 hal_rx_mpdu_start_wmask_get(soc->hal_soc); 772 } 773 #else 774 static inline void 775 dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc, 776 struct htt_rx_ring_tlv_filter *htt_tlv_filter) 777 { 778 } 779 #endif 780 781 #ifdef NO_RX_PKT_HDR_TLV 782 /** 783 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 784 * @soc: Common DP soc handle 785 * 786 * Return: QDF_STATUS 787 */ 788 static QDF_STATUS 789 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 790 { 791 int i; 792 int mac_id; 793 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 794 struct dp_srng *rx_mac_srng; 795 QDF_STATUS status = QDF_STATUS_SUCCESS; 796 797 /* 798 * In Beryllium chipset msdu_start, mpdu_end 799 * and rx_attn are part of msdu_end/mpdu_start 800 */ 801 htt_tlv_filter.msdu_start = 0; 802 htt_tlv_filter.mpdu_end = 0; 803 htt_tlv_filter.attention = 0; 804 htt_tlv_filter.mpdu_start = 1; 805 htt_tlv_filter.msdu_end = 1; 806 htt_tlv_filter.packet = 1; 807 htt_tlv_filter.packet_header = 0; 808 809 htt_tlv_filter.ppdu_start = 0; 810 htt_tlv_filter.ppdu_end = 0; 811 htt_tlv_filter.ppdu_end_user_stats = 0; 812 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 813 htt_tlv_filter.ppdu_end_status_done = 0; 814 htt_tlv_filter.enable_fp = 1; 815 htt_tlv_filter.enable_md = 0; 816 htt_tlv_filter.enable_md = 0; 817 htt_tlv_filter.enable_mo = 0; 818 819 htt_tlv_filter.fp_mgmt_filter = 0; 820 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 821 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 822 FILTER_DATA_MCAST | 823 FILTER_DATA_DATA); 824 htt_tlv_filter.mo_mgmt_filter = 0; 825 htt_tlv_filter.mo_ctrl_filter = 0; 826 htt_tlv_filter.mo_data_filter = 0; 827 htt_tlv_filter.md_data_filter = 0; 828 829 htt_tlv_filter.offset_valid = true; 830 831 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 832 htt_tlv_filter.rx_mpdu_end_offset = 0; 833 htt_tlv_filter.rx_msdu_start_offset = 0; 834 htt_tlv_filter.rx_attn_offset = 0; 835 836 /* 837 * For monitor mode, the packet hdr tlv is enabled later during 838 * filter update 839 */ 840 if (soc->cdp_soc.ol_ops->get_con_mode && 841 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) 842 htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size; 843 else 844 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 845 846 /*Not subscribing rx_pkt_header*/ 847 htt_tlv_filter.rx_header_offset = 0; 848 htt_tlv_filter.rx_mpdu_start_offset = 849 hal_rx_mpdu_start_offset_get(soc->hal_soc); 850 htt_tlv_filter.rx_msdu_end_offset = 851 hal_rx_msdu_end_offset_get(soc->hal_soc); 852 853 dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter); 854 855 for (i = 0; i < MAX_PDEV_CNT; i++) { 856 struct dp_pdev *pdev = soc->pdev_list[i]; 857 858 if (!pdev) 859 continue; 860 861 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 862 int mac_for_pdev = 863 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 864 /* 865 * Obtain lmac id from pdev to access the LMAC ring 866 * in soc context 867 */ 868 int lmac_id = 869 dp_get_lmac_id_for_pdev_id(soc, mac_id, 870 pdev->pdev_id); 871 872 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 873 874 if (!rx_mac_srng->hal_srng) 875 continue; 876 877 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 878 rx_mac_srng->hal_srng, 879 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 880 &htt_tlv_filter); 881 } 882 } 883 return status; 884 } 885 #else 886 /** 887 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 888 * @soc: Common DP soc handle 889 * 890 * Return: QDF_STATUS 891 */ 892 static QDF_STATUS 893 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 894 { 895 int i; 896 int mac_id; 897 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 898 struct dp_srng *rx_mac_srng; 899 QDF_STATUS status = QDF_STATUS_SUCCESS; 900 901 /* 902 * In Beryllium chipset msdu_start, mpdu_end 903 * and rx_attn are part of msdu_end/mpdu_start 904 */ 905 htt_tlv_filter.msdu_start = 0; 906 htt_tlv_filter.mpdu_end = 0; 907 htt_tlv_filter.attention = 0; 908 htt_tlv_filter.mpdu_start = 1; 909 htt_tlv_filter.msdu_end = 1; 910 htt_tlv_filter.packet = 1; 911 htt_tlv_filter.packet_header = 1; 912 913 htt_tlv_filter.ppdu_start = 0; 914 htt_tlv_filter.ppdu_end = 0; 915 htt_tlv_filter.ppdu_end_user_stats = 0; 916 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 917 htt_tlv_filter.ppdu_end_status_done = 0; 918 htt_tlv_filter.enable_fp = 1; 919 htt_tlv_filter.enable_md = 0; 920 htt_tlv_filter.enable_md = 0; 921 htt_tlv_filter.enable_mo = 0; 922 923 htt_tlv_filter.fp_mgmt_filter = 0; 924 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 925 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 926 FILTER_DATA_MCAST | 927 FILTER_DATA_DATA); 928 htt_tlv_filter.mo_mgmt_filter = 0; 929 htt_tlv_filter.mo_ctrl_filter = 0; 930 htt_tlv_filter.mo_data_filter = 0; 931 htt_tlv_filter.md_data_filter = 0; 932 933 htt_tlv_filter.offset_valid = true; 934 935 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 936 htt_tlv_filter.rx_mpdu_end_offset = 0; 937 htt_tlv_filter.rx_msdu_start_offset = 0; 938 htt_tlv_filter.rx_attn_offset = 0; 939 940 /* 941 * For monitor mode, the packet hdr tlv is enabled later during 942 * filter update 943 */ 944 if (soc->cdp_soc.ol_ops->get_con_mode && 945 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) 946 htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size; 947 else 948 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 949 950 htt_tlv_filter.rx_header_offset = 951 hal_rx_pkt_tlv_offset_get(soc->hal_soc); 952 htt_tlv_filter.rx_mpdu_start_offset = 953 hal_rx_mpdu_start_offset_get(soc->hal_soc); 954 htt_tlv_filter.rx_msdu_end_offset = 955 hal_rx_msdu_end_offset_get(soc->hal_soc); 956 957 dp_info("TLV subscription\n" 958 "msdu_start %d, mpdu_end %d, attention %d" 959 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n" 960 "TLV offsets\n" 961 "msdu_start %d, mpdu_end %d, attention %d" 962 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n", 963 htt_tlv_filter.msdu_start, 964 htt_tlv_filter.mpdu_end, 965 htt_tlv_filter.attention, 966 htt_tlv_filter.mpdu_start, 967 htt_tlv_filter.msdu_end, 968 htt_tlv_filter.packet_header, 969 htt_tlv_filter.packet, 970 htt_tlv_filter.rx_msdu_start_offset, 971 htt_tlv_filter.rx_mpdu_end_offset, 972 htt_tlv_filter.rx_attn_offset, 973 htt_tlv_filter.rx_mpdu_start_offset, 974 htt_tlv_filter.rx_msdu_end_offset, 975 htt_tlv_filter.rx_header_offset, 976 htt_tlv_filter.rx_packet_offset); 977 978 for (i = 0; i < MAX_PDEV_CNT; i++) { 979 struct dp_pdev *pdev = soc->pdev_list[i]; 980 981 if (!pdev) 982 continue; 983 984 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 985 int mac_for_pdev = 986 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 987 /* 988 * Obtain lmac id from pdev to access the LMAC ring 989 * in soc context 990 */ 991 int lmac_id = 992 dp_get_lmac_id_for_pdev_id(soc, mac_id, 993 pdev->pdev_id); 994 995 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 996 997 if (!rx_mac_srng->hal_srng) 998 continue; 999 1000 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 1001 rx_mac_srng->hal_srng, 1002 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 1003 &htt_tlv_filter); 1004 } 1005 } 1006 return status; 1007 1008 } 1009 #endif 1010 1011 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 1012 /** 1013 * dp_service_near_full_srngs_be() - Main bottom half callback for the 1014 * near-full IRQs. 1015 * @soc: Datapath SoC handle 1016 * @int_ctx: Interrupt context 1017 * @dp_budget: Budget of the work that can be done in the bottom half 1018 * 1019 * Return: work done in the handler 1020 */ 1021 static uint32_t 1022 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx, 1023 uint32_t dp_budget) 1024 { 1025 int ring = 0; 1026 int budget = dp_budget; 1027 uint32_t work_done = 0; 1028 uint32_t remaining_quota = dp_budget; 1029 struct dp_intr_stats *intr_stats = &int_ctx->intr_stats; 1030 int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask; 1031 int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask; 1032 int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask; 1033 int rx_near_full_mask = rx_near_full_grp_1_mask | 1034 rx_near_full_grp_2_mask; 1035 1036 dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x", 1037 rx_near_full_mask, 1038 tx_ring_near_full_mask); 1039 1040 if (rx_near_full_mask) { 1041 for (ring = 0; ring < soc->num_reo_dest_rings; ring++) { 1042 if (!(rx_near_full_mask & (1 << ring))) 1043 continue; 1044 1045 work_done = dp_rx_nf_process(int_ctx, 1046 soc->reo_dest_ring[ring].hal_srng, 1047 ring, remaining_quota); 1048 if (work_done) { 1049 intr_stats->num_rx_ring_near_full_masks[ring]++; 1050 dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d", 1051 rx_near_full_mask, ring, 1052 work_done, 1053 budget); 1054 budget -= work_done; 1055 if (budget <= 0) 1056 goto budget_done; 1057 remaining_quota = budget; 1058 } 1059 } 1060 } 1061 1062 if (tx_ring_near_full_mask) { 1063 for (ring = 0; ring < soc->num_tcl_data_rings; ring++) { 1064 if (!(tx_ring_near_full_mask & (1 << ring))) 1065 continue; 1066 1067 work_done = dp_tx_comp_nf_handler(int_ctx, soc, 1068 soc->tx_comp_ring[ring].hal_srng, 1069 ring, remaining_quota); 1070 if (work_done) { 1071 intr_stats->num_tx_comp_ring_near_full_masks[ring]++; 1072 dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d", 1073 tx_ring_near_full_mask, ring, 1074 work_done, budget); 1075 budget -= work_done; 1076 if (budget <= 0) 1077 break; 1078 remaining_quota = budget; 1079 } 1080 } 1081 } 1082 1083 intr_stats->num_near_full_masks++; 1084 1085 budget_done: 1086 return dp_budget - budget; 1087 } 1088 1089 /** 1090 * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full 1091 * state and set the reap_limit appropriately 1092 * as per the near full state 1093 * @soc: Datapath soc handle 1094 * @dp_srng: Datapath handle for SRNG 1095 * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per 1096 * the srng near-full state 1097 * 1098 * Return: 1, if the srng is in near-full state 1099 * 0, if the srng is not in near-full state 1100 */ 1101 static int 1102 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc, 1103 struct dp_srng *dp_srng, 1104 int *max_reap_limit) 1105 { 1106 return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit); 1107 } 1108 1109 /** 1110 * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the 1111 * near full IRQ handling operations. 1112 * @arch_ops: arch ops handle 1113 * 1114 * Return: none 1115 */ 1116 static inline void 1117 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1118 { 1119 arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be; 1120 arch_ops->dp_srng_test_and_update_nf_params = 1121 dp_srng_test_and_update_nf_params_be; 1122 } 1123 1124 #else 1125 static inline void 1126 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1127 { 1128 } 1129 #endif 1130 1131 #ifdef WLAN_SUPPORT_PPEDS 1132 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1133 { 1134 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1135 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1136 1137 soc_cfg_ctx = soc->wlan_cfg_ctx; 1138 1139 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1140 return; 1141 1142 dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0); 1143 wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned, 1144 be_soc->ppe_release_ring.alloc_size, 1145 soc->ctrl_psoc, 1146 WLAN_MD_DP_SRNG_PPE_RELEASE, 1147 "ppe_release_ring"); 1148 1149 dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0); 1150 wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1151 be_soc->ppe2tcl_ring.alloc_size, 1152 soc->ctrl_psoc, 1153 WLAN_MD_DP_SRNG_PPE2TCL, 1154 "ppe2tcl_ring"); 1155 1156 dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0); 1157 wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1158 be_soc->reo2ppe_ring.alloc_size, 1159 soc->ctrl_psoc, 1160 WLAN_MD_DP_SRNG_REO2PPE, 1161 "reo2ppe_ring"); 1162 } 1163 1164 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1165 { 1166 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1167 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1168 1169 soc_cfg_ctx = soc->wlan_cfg_ctx; 1170 1171 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1172 return; 1173 1174 dp_srng_free(soc, &be_soc->ppe_release_ring); 1175 1176 dp_srng_free(soc, &be_soc->ppe2tcl_ring); 1177 1178 dp_srng_free(soc, &be_soc->reo2ppe_ring); 1179 } 1180 1181 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1182 { 1183 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1184 uint32_t entries; 1185 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1186 1187 soc_cfg_ctx = soc->wlan_cfg_ctx; 1188 1189 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1190 return QDF_STATUS_SUCCESS; 1191 1192 entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx); 1193 1194 if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE, 1195 entries, 0)) { 1196 dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc); 1197 goto fail; 1198 } 1199 1200 entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx); 1201 if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 1202 entries, 0)) { 1203 dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc); 1204 goto fail; 1205 } 1206 1207 entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx); 1208 if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 1209 entries, 0)) { 1210 dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc); 1211 goto fail; 1212 } 1213 1214 return QDF_STATUS_SUCCESS; 1215 fail: 1216 dp_soc_ppe_srng_free(soc); 1217 return QDF_STATUS_E_NOMEM; 1218 } 1219 1220 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1221 { 1222 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1223 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1224 hal_soc_handle_t hal_soc = soc->hal_soc; 1225 1226 soc_cfg_ctx = soc->wlan_cfg_ctx; 1227 1228 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1229 return QDF_STATUS_SUCCESS; 1230 1231 if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) { 1232 dp_err("%pK: dp_srng_init failed for reo2ppe", soc); 1233 goto fail; 1234 } 1235 1236 wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1237 be_soc->reo2ppe_ring.alloc_size, 1238 soc->ctrl_psoc, 1239 WLAN_MD_DP_SRNG_REO2PPE, 1240 "reo2ppe_ring"); 1241 1242 hal_reo_config_reo2ppe_dest_info(hal_soc); 1243 1244 if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) { 1245 dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc); 1246 goto fail; 1247 } 1248 1249 wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1250 be_soc->ppe2tcl_ring.alloc_size, 1251 soc->ctrl_psoc, 1252 WLAN_MD_DP_SRNG_PPE2TCL, 1253 "ppe2tcl_ring"); 1254 1255 if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) { 1256 dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc); 1257 goto fail; 1258 } 1259 1260 wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned, 1261 be_soc->ppe_release_ring.alloc_size, 1262 soc->ctrl_psoc, 1263 WLAN_MD_DP_SRNG_PPE_RELEASE, 1264 "ppe_release_ring"); 1265 1266 return QDF_STATUS_SUCCESS; 1267 fail: 1268 dp_soc_ppe_srng_deinit(soc); 1269 return QDF_STATUS_E_NOMEM; 1270 } 1271 #else 1272 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1273 { 1274 } 1275 1276 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1277 { 1278 } 1279 1280 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1281 { 1282 return QDF_STATUS_SUCCESS; 1283 } 1284 1285 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1286 { 1287 return QDF_STATUS_SUCCESS; 1288 } 1289 #endif 1290 1291 static void dp_soc_srng_deinit_be(struct dp_soc *soc) 1292 { 1293 uint32_t i; 1294 1295 dp_soc_ppe_srng_deinit(soc); 1296 1297 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1298 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1299 dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i], 1300 RXDMA_BUF, 0); 1301 } 1302 } 1303 } 1304 1305 static void dp_soc_srng_free_be(struct dp_soc *soc) 1306 { 1307 uint32_t i; 1308 1309 dp_soc_ppe_srng_free(soc); 1310 1311 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1312 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) 1313 dp_srng_free(soc, &soc->rx_refill_buf_ring[i]); 1314 } 1315 } 1316 1317 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc) 1318 { 1319 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1320 uint32_t ring_size; 1321 uint32_t i; 1322 1323 soc_cfg_ctx = soc->wlan_cfg_ctx; 1324 1325 ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx); 1326 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1327 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1328 if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i], 1329 RXDMA_BUF, ring_size, 0)) { 1330 dp_err("%pK: dp_srng_alloc failed refill ring", 1331 soc); 1332 goto fail; 1333 } 1334 } 1335 } 1336 1337 if (dp_soc_ppe_srng_alloc(soc)) { 1338 dp_err("%pK: ppe rings alloc failed", 1339 soc); 1340 goto fail; 1341 } 1342 1343 return QDF_STATUS_SUCCESS; 1344 fail: 1345 dp_soc_srng_free_be(soc); 1346 return QDF_STATUS_E_NOMEM; 1347 } 1348 1349 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc) 1350 { 1351 int i = 0; 1352 1353 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1354 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1355 if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i], 1356 RXDMA_BUF, 0, 0)) { 1357 dp_err("%pK: dp_srng_init failed refill ring", 1358 soc); 1359 goto fail; 1360 } 1361 } 1362 } 1363 1364 if (dp_soc_ppe_srng_init(soc)) { 1365 dp_err("%pK: ppe rings init failed", 1366 soc); 1367 goto fail; 1368 } 1369 1370 return QDF_STATUS_SUCCESS; 1371 fail: 1372 dp_soc_srng_deinit_be(soc); 1373 return QDF_STATUS_E_NOMEM; 1374 } 1375 1376 #ifdef WLAN_FEATURE_11BE_MLO 1377 static inline unsigned 1378 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj, 1379 union dp_align_mac_addr *mac_addr) 1380 { 1381 uint32_t index; 1382 1383 index = 1384 mac_addr->align2.bytes_ab ^ 1385 mac_addr->align2.bytes_cd ^ 1386 mac_addr->align2.bytes_ef; 1387 1388 index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits; 1389 index &= mld_hash_obj->mld_peer_hash.mask; 1390 1391 return index; 1392 } 1393 1394 QDF_STATUS 1395 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj, 1396 int hash_elems) 1397 { 1398 int i, log2; 1399 1400 if (!mld_hash_obj) 1401 return QDF_STATUS_E_FAILURE; 1402 1403 hash_elems *= DP_PEER_HASH_LOAD_MULT; 1404 hash_elems >>= DP_PEER_HASH_LOAD_SHIFT; 1405 log2 = dp_log2_ceil(hash_elems); 1406 hash_elems = 1 << log2; 1407 1408 mld_hash_obj->mld_peer_hash.mask = hash_elems - 1; 1409 mld_hash_obj->mld_peer_hash.idx_bits = log2; 1410 /* allocate an array of TAILQ peer object lists */ 1411 mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc( 1412 hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer))); 1413 if (!mld_hash_obj->mld_peer_hash.bins) 1414 return QDF_STATUS_E_NOMEM; 1415 1416 for (i = 0; i < hash_elems; i++) 1417 TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]); 1418 1419 qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock); 1420 1421 return QDF_STATUS_SUCCESS; 1422 } 1423 1424 void 1425 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj) 1426 { 1427 if (!mld_hash_obj) 1428 return; 1429 1430 if (mld_hash_obj->mld_peer_hash.bins) { 1431 qdf_mem_free(mld_hash_obj->mld_peer_hash.bins); 1432 mld_hash_obj->mld_peer_hash.bins = NULL; 1433 qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock); 1434 } 1435 } 1436 1437 #ifdef WLAN_MLO_MULTI_CHIP 1438 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1439 { 1440 /* In case of MULTI chip MLO peer hash table when MLO global object 1441 * is created, avoid from SOC attach path 1442 */ 1443 return QDF_STATUS_SUCCESS; 1444 } 1445 1446 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1447 { 1448 } 1449 #else 1450 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1451 { 1452 dp_mld_peer_hash_obj_t mld_hash_obj; 1453 1454 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1455 1456 if (!mld_hash_obj) 1457 return QDF_STATUS_E_FAILURE; 1458 1459 return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers); 1460 } 1461 1462 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1463 { 1464 dp_mld_peer_hash_obj_t mld_hash_obj; 1465 1466 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1467 1468 if (!mld_hash_obj) 1469 return; 1470 1471 return dp_mlo_peer_find_hash_detach_be(mld_hash_obj); 1472 } 1473 #endif 1474 1475 static struct dp_peer * 1476 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc, 1477 uint8_t *peer_mac_addr, 1478 int mac_addr_is_aligned, 1479 enum dp_mod_id mod_id, 1480 uint8_t vdev_id) 1481 { 1482 union dp_align_mac_addr local_mac_addr_aligned, *mac_addr; 1483 uint32_t index; 1484 struct dp_peer *peer; 1485 struct dp_vdev *vdev; 1486 dp_mld_peer_hash_obj_t mld_hash_obj; 1487 1488 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1489 if (!mld_hash_obj) 1490 return NULL; 1491 1492 if (!mld_hash_obj->mld_peer_hash.bins) 1493 return NULL; 1494 1495 if (mac_addr_is_aligned) { 1496 mac_addr = (union dp_align_mac_addr *)peer_mac_addr; 1497 } else { 1498 qdf_mem_copy( 1499 &local_mac_addr_aligned.raw[0], 1500 peer_mac_addr, QDF_MAC_ADDR_SIZE); 1501 mac_addr = &local_mac_addr_aligned; 1502 } 1503 1504 if (vdev_id != DP_VDEV_ALL) { 1505 vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id); 1506 if (!vdev) { 1507 dp_err("vdev is null\n"); 1508 return NULL; 1509 } 1510 } else { 1511 vdev = NULL; 1512 } 1513 /* search mld peer table if no link peer for given mac address */ 1514 index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr); 1515 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1516 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1517 hash_list_elem) { 1518 if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) { 1519 if ((vdev_id == DP_VDEV_ALL) || ( 1520 dp_peer_find_mac_addr_cmp( 1521 &peer->vdev->mld_mac_addr, 1522 &vdev->mld_mac_addr) == 0)) { 1523 /* take peer reference before returning */ 1524 if (dp_peer_get_ref(NULL, peer, mod_id) != 1525 QDF_STATUS_SUCCESS) 1526 peer = NULL; 1527 1528 if (vdev) 1529 dp_vdev_unref_delete(soc, vdev, mod_id); 1530 1531 qdf_spin_unlock_bh( 1532 &mld_hash_obj->mld_peer_hash_lock); 1533 return peer; 1534 } 1535 } 1536 } 1537 1538 if (vdev) 1539 dp_vdev_unref_delete(soc, vdev, mod_id); 1540 1541 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1542 1543 return NULL; /* failure */ 1544 } 1545 1546 static void 1547 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer) 1548 { 1549 uint32_t index; 1550 struct dp_peer *tmppeer = NULL; 1551 int found = 0; 1552 dp_mld_peer_hash_obj_t mld_hash_obj; 1553 1554 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1555 1556 if (!mld_hash_obj) 1557 return; 1558 1559 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1560 QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index])); 1561 1562 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1563 TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index], 1564 hash_list_elem) { 1565 if (tmppeer == peer) { 1566 found = 1; 1567 break; 1568 } 1569 } 1570 QDF_ASSERT(found); 1571 TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1572 hash_list_elem); 1573 1574 dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG); 1575 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1576 } 1577 1578 static void 1579 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer) 1580 { 1581 uint32_t index; 1582 dp_mld_peer_hash_obj_t mld_hash_obj; 1583 1584 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1585 1586 if (!mld_hash_obj) 1587 return; 1588 1589 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1590 1591 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1592 1593 if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer, 1594 DP_MOD_ID_CONFIG))) { 1595 dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT, 1596 QDF_MAC_ADDR_REF(peer->mac_addr.raw)); 1597 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1598 return; 1599 } 1600 TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1601 hash_list_elem); 1602 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1603 } 1604 1605 void dp_print_mlo_ast_stats_be(struct dp_soc *soc) 1606 { 1607 uint32_t index; 1608 struct dp_peer *peer; 1609 dp_mld_peer_hash_obj_t mld_hash_obj; 1610 1611 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1612 1613 if (!mld_hash_obj) 1614 return; 1615 1616 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1617 for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) { 1618 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1619 hash_list_elem) { 1620 dp_print_peer_ast_entries(soc, peer, NULL); 1621 } 1622 } 1623 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1624 } 1625 1626 #endif 1627 1628 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 1629 static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc, 1630 struct dp_vdev *vdev) 1631 { 1632 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1633 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1634 hal_soc_handle_t hal_soc = soc->hal_soc; 1635 uint8_t vdev_id = vdev->vdev_id; 1636 1637 if (vdev->opmode == wlan_op_mode_sta) { 1638 if (vdev->pdev->isolation) 1639 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1640 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1641 else 1642 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1643 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 1644 } else if (vdev->opmode == wlan_op_mode_ap) { 1645 if (vdev->mlo_vdev) { 1646 if (be_vdev->mcast_primary) { 1647 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1648 HAL_TX_MCAST_CTRL_NO_SPECIAL); 1649 hal_tx_vdev_mcast_ctrl_set(hal_soc, 1650 vdev_id + 128, 1651 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1652 dp_mcast_mlo_iter_ptnr_soc(be_soc, 1653 dp_tx_mcast_mlo_reinject_routing_set, 1654 (void *)&be_vdev->mcast_primary); 1655 } else { 1656 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1657 HAL_TX_MCAST_CTRL_DROP); 1658 } 1659 } else { 1660 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 1661 vdev_id, 1662 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1663 } 1664 } 1665 } 1666 1667 static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev) 1668 { 1669 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1670 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1671 union hal_tx_bank_config *bank_config; 1672 1673 if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID) 1674 return; 1675 1676 bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config; 1677 1678 hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config, 1679 be_vdev->bank_id); 1680 } 1681 1682 #endif 1683 1684 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \ 1685 defined(WLAN_MCAST_MLO) 1686 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1687 struct dp_vdev_be *be_vdev, 1688 cdp_config_param_type val) 1689 { 1690 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc( 1691 be_vdev->vdev.pdev->soc); 1692 hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc; 1693 uint8_t vdev_id = be_vdev->vdev.vdev_id; 1694 1695 be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev; 1696 1697 if (be_vdev->mcast_primary) { 1698 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1699 HAL_TX_MCAST_CTRL_NO_SPECIAL); 1700 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128, 1701 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1702 dp_mcast_mlo_iter_ptnr_soc(be_soc, 1703 dp_tx_mcast_mlo_reinject_routing_set, 1704 (void *)&be_vdev->mcast_primary); 1705 } else { 1706 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1707 HAL_TX_MCAST_CTRL_DROP); 1708 } 1709 } 1710 #else 1711 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1712 struct dp_vdev_be *be_vdev, 1713 cdp_config_param_type val) 1714 { 1715 } 1716 #endif 1717 1718 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 1719 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1720 uint8_t tx_ring_id, 1721 uint8_t bm_id) 1722 { 1723 hal_tx_config_rbm_mapping_be(soc->hal_soc, 1724 soc->tcl_data_ring[tx_ring_id].hal_srng, 1725 bm_id); 1726 } 1727 #else 1728 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1729 uint8_t tx_ring_id, 1730 uint8_t bm_id) 1731 { 1732 } 1733 #endif 1734 1735 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc, 1736 struct dp_vdev *vdev, 1737 enum cdp_vdev_param_type param, 1738 cdp_config_param_type val) 1739 { 1740 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1741 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1742 1743 switch (param) { 1744 case CDP_TX_ENCAP_TYPE: 1745 case CDP_UPDATE_DSCP_TO_TID_MAP: 1746 case CDP_UPDATE_TDLS_FLAGS: 1747 dp_tx_update_bank_profile(be_soc, be_vdev); 1748 break; 1749 case CDP_ENABLE_CIPHER: 1750 if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) 1751 dp_tx_update_bank_profile(be_soc, be_vdev); 1752 break; 1753 case CDP_SET_MCAST_VDEV: 1754 dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val); 1755 break; 1756 default: 1757 dp_warn("invalid param %d", param); 1758 break; 1759 } 1760 1761 return QDF_STATUS_SUCCESS; 1762 } 1763 1764 #ifdef WLAN_FEATURE_11BE_MLO 1765 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 1766 static inline void 1767 dp_soc_max_peer_id_set(struct dp_soc *soc) 1768 { 1769 soc->peer_id_shift = dp_log2_ceil(soc->max_peers); 1770 soc->peer_id_mask = (1 << soc->peer_id_shift) - 1; 1771 /* 1772 * Double the peers since we use ML indication bit 1773 * alongwith peer_id to find peers. 1774 */ 1775 soc->max_peer_id = 1 << (soc->peer_id_shift + 1); 1776 } 1777 #else 1778 static inline void 1779 dp_soc_max_peer_id_set(struct dp_soc *soc) 1780 { 1781 soc->max_peer_id = 1782 (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1; 1783 } 1784 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */ 1785 #else 1786 static inline void 1787 dp_soc_max_peer_id_set(struct dp_soc *soc) 1788 { 1789 soc->max_peer_id = soc->max_peers; 1790 } 1791 #endif /* WLAN_FEATURE_11BE_MLO */ 1792 1793 static void dp_peer_map_detach_be(struct dp_soc *soc) 1794 { 1795 if (soc->host_ast_db_enable) 1796 dp_peer_ast_hash_detach(soc); 1797 } 1798 1799 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc) 1800 { 1801 QDF_STATUS status; 1802 1803 if (soc->host_ast_db_enable) { 1804 status = dp_peer_ast_hash_attach(soc); 1805 if (QDF_IS_STATUS_ERROR(status)) 1806 return status; 1807 } 1808 1809 dp_soc_max_peer_id_set(soc); 1810 1811 return QDF_STATUS_SUCCESS; 1812 } 1813 1814 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc, 1815 uint8_t *dest_mac, 1816 uint8_t vdev_id) 1817 { 1818 struct dp_peer *peer = NULL; 1819 struct dp_peer *tgt_peer = NULL; 1820 struct dp_ast_entry *ast_entry = NULL; 1821 uint16_t peer_id; 1822 1823 qdf_spin_lock_bh(&soc->ast_lock); 1824 ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac); 1825 if (!ast_entry) { 1826 qdf_spin_unlock_bh(&soc->ast_lock); 1827 dp_err("NULL ast entry"); 1828 return NULL; 1829 } 1830 1831 peer_id = ast_entry->peer_id; 1832 qdf_spin_unlock_bh(&soc->ast_lock); 1833 1834 if (peer_id == HTT_INVALID_PEER) 1835 return NULL; 1836 1837 peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF); 1838 if (!peer) { 1839 dp_err("NULL peer for peer_id:%d", peer_id); 1840 return NULL; 1841 } 1842 1843 tgt_peer = dp_get_tgt_peer_from_peer(peer); 1844 1845 /* 1846 * Once tgt_peer is obtained, 1847 * release the ref taken for original peer. 1848 */ 1849 dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF); 1850 dp_peer_unref_delete(peer, DP_MOD_ID_SAWF); 1851 1852 return tgt_peer; 1853 } 1854 1855 #ifdef WLAN_FEATURE_11BE_MLO 1856 #ifdef WLAN_MCAST_MLO 1857 static inline void 1858 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1859 { 1860 arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be; 1861 arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler; 1862 } 1863 #else /* WLAN_MCAST_MLO */ 1864 static inline void 1865 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1866 { 1867 } 1868 #endif /* WLAN_MCAST_MLO */ 1869 1870 #ifdef WLAN_MLO_MULTI_CHIP 1871 static inline void 1872 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops) 1873 { 1874 arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map; 1875 arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap; 1876 } 1877 #else 1878 static inline void 1879 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops) 1880 { 1881 } 1882 #endif 1883 1884 static inline void 1885 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1886 { 1887 dp_initialize_arch_ops_be_mcast_mlo(arch_ops); 1888 dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops); 1889 arch_ops->mlo_peer_find_hash_detach = 1890 dp_mlo_peer_find_hash_detach_wrapper; 1891 arch_ops->mlo_peer_find_hash_attach = 1892 dp_mlo_peer_find_hash_attach_wrapper; 1893 arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be; 1894 arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be; 1895 arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be; 1896 } 1897 #else /* WLAN_FEATURE_11BE_MLO */ 1898 static inline void 1899 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1900 { 1901 } 1902 #endif /* WLAN_FEATURE_11BE_MLO */ 1903 1904 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1905 #define DP_LMAC_PEER_ID_MSB_LEGACY 2 1906 #define DP_LMAC_PEER_ID_MSB_MLO 3 1907 1908 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 1909 struct cdp_peer_setup_info *setup_info, 1910 enum cdp_host_reo_dest_ring *reo_dest, 1911 bool *hash_based, 1912 uint8_t *lmac_peer_id_msb) 1913 { 1914 struct dp_soc *soc = vdev->pdev->soc; 1915 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1916 1917 if (!be_soc->mlo_enabled) 1918 return dp_vdev_get_default_reo_hash(vdev, reo_dest, 1919 hash_based); 1920 1921 *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx); 1922 *reo_dest = vdev->pdev->reo_dest; 1923 1924 /* Not a ML link peer use non-mlo */ 1925 if (!setup_info) { 1926 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 1927 return; 1928 } 1929 1930 /* For STA ML VAP we do not have num links info at this point 1931 * use MLO case always 1932 */ 1933 if (vdev->opmode == wlan_op_mode_sta) { 1934 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 1935 return; 1936 } 1937 1938 /* For AP ML VAP consider the peer as ML only it associates with 1939 * multiple links 1940 */ 1941 if (setup_info->num_links == 1) { 1942 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 1943 return; 1944 } 1945 1946 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 1947 } 1948 1949 static bool dp_reo_remap_config_be(struct dp_soc *soc, 1950 uint32_t *remap0, 1951 uint32_t *remap1, 1952 uint32_t *remap2) 1953 { 1954 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1955 uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx); 1956 uint32_t reo_mlo_config = 1957 wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx); 1958 1959 if (!be_soc->mlo_enabled) 1960 return dp_reo_remap_config(soc, remap0, remap1, remap2); 1961 1962 *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 1963 *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config); 1964 *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 1965 1966 return true; 1967 } 1968 #else 1969 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 1970 struct cdp_peer_setup_info *setup_info, 1971 enum cdp_host_reo_dest_ring *reo_dest, 1972 bool *hash_based, 1973 uint8_t *lmac_peer_id_msb) 1974 { 1975 dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based); 1976 } 1977 1978 static bool dp_reo_remap_config_be(struct dp_soc *soc, 1979 uint32_t *remap0, 1980 uint32_t *remap1, 1981 uint32_t *remap2) 1982 { 1983 return dp_reo_remap_config(soc, remap0, remap1, remap2); 1984 } 1985 #endif 1986 1987 #ifdef IPA_OFFLOAD 1988 static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc) 1989 { 1990 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1991 1992 return be_soc->ipa_bank_id; 1993 } 1994 1995 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops) 1996 { 1997 arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be; 1998 } 1999 #else /* !IPA_OFFLOAD */ 2000 static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops) 2001 { 2002 } 2003 #endif /* IPA_OFFLOAD */ 2004 2005 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops) 2006 { 2007 #ifndef QCA_HOST_MODE_WIFI_DISABLED 2008 arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be; 2009 arch_ops->dp_rx_process = dp_rx_process_be; 2010 arch_ops->dp_tx_send_fast = dp_tx_fast_send_be; 2011 arch_ops->tx_comp_get_params_from_hal_desc = 2012 dp_tx_comp_get_params_from_hal_desc_be; 2013 arch_ops->dp_tx_process_htt_completion = 2014 dp_tx_process_htt_completion_be; 2015 arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be; 2016 arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be; 2017 arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be; 2018 arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be; 2019 arch_ops->dp_wbm_get_rx_desc_from_hal_desc = 2020 dp_wbm_get_rx_desc_from_hal_desc_be; 2021 arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be; 2022 #endif 2023 arch_ops->txrx_get_context_size = dp_get_context_size_be; 2024 #ifdef WIFI_MONITOR_SUPPORT 2025 arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be; 2026 #endif 2027 arch_ops->dp_rx_desc_cookie_2_va = 2028 dp_rx_desc_cookie_2_va_be; 2029 arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be; 2030 arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be; 2031 2032 arch_ops->txrx_soc_attach = dp_soc_attach_be; 2033 arch_ops->txrx_soc_detach = dp_soc_detach_be; 2034 arch_ops->txrx_soc_init = dp_soc_init_be; 2035 arch_ops->txrx_soc_deinit = dp_soc_deinit_be; 2036 arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be; 2037 arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be; 2038 arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be; 2039 arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be; 2040 arch_ops->txrx_pdev_attach = dp_pdev_attach_be; 2041 arch_ops->txrx_pdev_detach = dp_pdev_detach_be; 2042 arch_ops->txrx_vdev_attach = dp_vdev_attach_be; 2043 arch_ops->txrx_vdev_detach = dp_vdev_detach_be; 2044 arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be; 2045 arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be; 2046 arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be; 2047 arch_ops->dp_rx_peer_metadata_peer_id_get = 2048 dp_rx_peer_metadata_peer_id_get_be; 2049 arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be; 2050 arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be; 2051 arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be; 2052 dp_initialize_arch_ops_be_mlo(arch_ops); 2053 arch_ops->dp_peer_rx_reorder_queue_setup = 2054 dp_peer_rx_reorder_queue_setup_be; 2055 arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be; 2056 arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be; 2057 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 2058 arch_ops->dp_bank_reconfig = dp_bank_reconfig_be; 2059 arch_ops->dp_reconfig_tx_vdev_mcast_ctrl = 2060 dp_reconfig_tx_vdev_mcast_ctrl_be; 2061 arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init; 2062 #endif 2063 2064 #ifdef WLAN_SUPPORT_PPEDS 2065 arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status; 2066 #else 2067 arch_ops->dp_txrx_ppeds_rings_status = NULL; 2068 #endif 2069 2070 dp_init_near_full_arch_ops_be(arch_ops); 2071 arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be; 2072 arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be; 2073 arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be; 2074 arch_ops->reo_remap_config = dp_reo_remap_config_be; 2075 dp_initialize_arch_ops_be_ipa(arch_ops); 2076 } 2077