1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <wlan_utility.h> 21 #include <dp_internal.h> 22 #include <dp_htt.h> 23 #include "dp_be.h" 24 #include "dp_be_tx.h" 25 #include "dp_be_rx.h" 26 #ifdef WIFI_MONITOR_SUPPORT 27 #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT) 28 #include "dp_mon_2.0.h" 29 #endif 30 #include "dp_mon.h" 31 #endif 32 #include <hal_be_api.h> 33 34 /* Generic AST entry aging timer value */ 35 #define DP_AST_AGING_TIMER_DEFAULT_MS 5000 36 37 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 38 #define DP_TX_VDEV_ID_CHECK_ENABLE 0 39 40 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 41 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 42 {1, 4, HAL_BE_WBM_SW4_BM_ID, 0}, 43 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 44 #ifdef QCA_WIFI_KIWI_V2 45 {3, 5, HAL_BE_WBM_SW5_BM_ID, 0}, 46 {4, 6, HAL_BE_WBM_SW6_BM_ID, 0} 47 #else 48 {3, 6, HAL_BE_WBM_SW5_BM_ID, 0}, 49 {4, 7, HAL_BE_WBM_SW6_BM_ID, 0} 50 #endif 51 }; 52 #else 53 #define DP_TX_VDEV_ID_CHECK_ENABLE 1 54 55 static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { 56 {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, 57 {1, 1, HAL_BE_WBM_SW1_BM_ID, 0}, 58 {2, 2, HAL_BE_WBM_SW2_BM_ID, 0}, 59 {3, 3, HAL_BE_WBM_SW3_BM_ID, 0}, 60 {4, 4, HAL_BE_WBM_SW4_BM_ID, 0} 61 }; 62 #endif 63 64 static void dp_soc_cfg_attach_be(struct dp_soc *soc) 65 { 66 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx; 67 68 wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM); 69 70 soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array; 71 72 /* this is used only when dmac mode is enabled */ 73 soc->num_rx_refill_buf_rings = 1; 74 75 soc->wlan_cfg_ctx->notify_frame_support = 76 DP_MARK_NOTIFY_FRAME_SUPPORT; 77 } 78 79 qdf_size_t dp_get_context_size_be(enum dp_context_type context_type) 80 { 81 switch (context_type) { 82 case DP_CONTEXT_TYPE_SOC: 83 return sizeof(struct dp_soc_be); 84 case DP_CONTEXT_TYPE_PDEV: 85 return sizeof(struct dp_pdev_be); 86 case DP_CONTEXT_TYPE_VDEV: 87 return sizeof(struct dp_vdev_be); 88 case DP_CONTEXT_TYPE_PEER: 89 return sizeof(struct dp_peer_be); 90 default: 91 return 0; 92 } 93 } 94 95 #ifdef DP_FEATURE_HW_COOKIE_CONVERSION 96 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 97 /** 98 * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement 99 per wbm2sw ring 100 * @cc_cfg: HAL HW cookie conversion configuration structure pointer 101 * 102 * Return: None 103 */ 104 static inline 105 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 106 { 107 cc_cfg->wbm2sw6_cc_en = 1; 108 cc_cfg->wbm2sw5_cc_en = 1; 109 cc_cfg->wbm2sw4_cc_en = 1; 110 cc_cfg->wbm2sw3_cc_en = 1; 111 cc_cfg->wbm2sw2_cc_en = 1; 112 /* disable wbm2sw1 hw cc as it's for FW */ 113 cc_cfg->wbm2sw1_cc_en = 0; 114 cc_cfg->wbm2sw0_cc_en = 1; 115 cc_cfg->wbm2fw_cc_en = 0; 116 } 117 #else 118 static inline 119 void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg) 120 { 121 cc_cfg->wbm2sw6_cc_en = 1; 122 cc_cfg->wbm2sw5_cc_en = 1; 123 cc_cfg->wbm2sw4_cc_en = 1; 124 cc_cfg->wbm2sw3_cc_en = 1; 125 cc_cfg->wbm2sw2_cc_en = 1; 126 cc_cfg->wbm2sw1_cc_en = 1; 127 cc_cfg->wbm2sw0_cc_en = 1; 128 cc_cfg->wbm2fw_cc_en = 0; 129 } 130 #endif 131 132 #if defined(WLAN_SUPPORT_RX_FISA) 133 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 134 { 135 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 136 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 137 /* get CMEM for cookie conversion */ 138 if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) { 139 dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size); 140 return QDF_STATUS_E_NOMEM; 141 } 142 143 soc->fst_cmem_size = DP_CMEM_FST_SIZE; 144 145 soc->fst_cmem_base = soc->cmem_base + 146 (soc->cmem_total_size - soc->cmem_avail_size); 147 soc->cmem_avail_size -= soc->fst_cmem_size; 148 149 dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx", 150 soc->fst_cmem_base, soc->fst_cmem_size); 151 152 return QDF_STATUS_SUCCESS; 153 } 154 #else /* !WLAN_SUPPORT_RX_FISA */ 155 static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc) 156 { 157 return QDF_STATUS_SUCCESS; 158 } 159 #endif 160 161 /** 162 * dp_cc_reg_cfg_init() - initialize and configure HW cookie 163 conversion register 164 * @soc: SOC handle 165 * @is_4k_align: page address 4k alignd 166 * 167 * Return: None 168 */ 169 static void dp_cc_reg_cfg_init(struct dp_soc *soc, 170 bool is_4k_align) 171 { 172 struct hal_hw_cc_config cc_cfg = { 0 }; 173 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 174 175 if (soc->cdp_soc.ol_ops->get_con_mode && 176 soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE) 177 return; 178 179 if (!soc->wlan_cfg_ctx->hw_cc_enabled) { 180 dp_info("INI skip HW CC register setting"); 181 return; 182 } 183 184 cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base; 185 cc_cfg.cc_global_en = true; 186 cc_cfg.page_4k_align = is_4k_align; 187 cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB; 188 cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB; 189 /* 36th bit should be 1 then HW know this is CMEM address */ 190 cc_cfg.lut_base_addr_39_32 = 0x10; 191 192 cc_cfg.error_path_cookie_conv_en = true; 193 cc_cfg.release_path_cookie_conv_en = true; 194 dp_cc_wbm_sw_en_cfg(&cc_cfg); 195 196 hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg); 197 } 198 199 /** 200 * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing 201 * @hal_soc_hdl: HAL SOC handle 202 * @offset: CMEM address 203 * @value: value to write 204 * 205 * Return: None. 206 */ 207 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 208 uint32_t offset, 209 uint32_t value) 210 { 211 hal_cmem_write(hal_soc_hdl, offset, value); 212 } 213 214 /** 215 * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for 216 HW cookie conversion 217 * @soc: SOC handle 218 * @cc_ctx: cookie conversion context pointer 219 * 220 * Return: 0 in case of success, else error value 221 */ 222 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 223 { 224 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 225 226 dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx", 227 soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size); 228 /* get CMEM for cookie conversion */ 229 if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) { 230 dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size); 231 return QDF_STATUS_E_RESOURCES; 232 } 233 be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base + 234 DP_CC_MEM_OFFSET_IN_CMEM); 235 236 soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE; 237 238 dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx", 239 be_soc->cc_cmem_base, soc->cmem_avail_size); 240 return QDF_STATUS_SUCCESS; 241 } 242 243 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 244 uint8_t for_feature) 245 { 246 QDF_STATUS status = QDF_STATUS_E_NOMEM; 247 248 switch (for_feature) { 249 case COOKIE_CONVERSION: 250 status = dp_hw_cc_cmem_addr_init(soc); 251 break; 252 case FISA_FST: 253 status = dp_fisa_fst_cmem_addr_init(soc); 254 break; 255 default: 256 dp_err("Invalid CMEM request"); 257 } 258 259 return status; 260 } 261 262 #else 263 264 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc, 265 bool is_4k_align) {} 266 267 static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl, 268 uint32_t offset, 269 uint32_t value) 270 { } 271 272 static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc) 273 { 274 return QDF_STATUS_SUCCESS; 275 } 276 277 static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc, 278 uint8_t for_feature) 279 { 280 return QDF_STATUS_SUCCESS; 281 } 282 283 #endif 284 285 QDF_STATUS 286 dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc, 287 struct dp_hw_cookie_conversion_t *cc_ctx, 288 uint32_t num_descs, 289 enum dp_desc_type desc_type, 290 uint8_t desc_pool_id) 291 { 292 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 293 uint32_t num_spt_pages, i = 0; 294 struct dp_spt_page_desc *spt_desc; 295 struct qdf_mem_dma_page_t *dma_page; 296 uint8_t chip_id; 297 298 /* estimate how many SPT DDR pages needed */ 299 num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES; 300 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 301 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 302 dp_info("num_spt_pages needed %d", num_spt_pages); 303 304 dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE, 305 &cc_ctx->page_pool, qdf_page_size, 306 num_spt_pages, 0, false); 307 if (!cc_ctx->page_pool.dma_pages) { 308 dp_err("spt ddr pages allocation failed"); 309 return QDF_STATUS_E_RESOURCES; 310 } 311 cc_ctx->page_desc_base = qdf_mem_malloc( 312 num_spt_pages * sizeof(struct dp_spt_page_desc)); 313 if (!cc_ctx->page_desc_base) { 314 dp_err("spt page descs allocation failed"); 315 goto fail_0; 316 } 317 318 chip_id = dp_mlo_get_chip_id(soc); 319 cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id, 320 desc_type); 321 322 /* initial page desc */ 323 spt_desc = cc_ctx->page_desc_base; 324 dma_page = cc_ctx->page_pool.dma_pages; 325 while (i < num_spt_pages) { 326 /* check if page address 4K aligned */ 327 if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) { 328 dp_err("non-4k aligned pages addr %pK", 329 (void *)dma_page[i].page_p_addr); 330 goto fail_1; 331 } 332 333 spt_desc[i].page_v_addr = 334 dma_page[i].page_v_addr_start; 335 spt_desc[i].page_p_addr = 336 dma_page[i].page_p_addr; 337 i++; 338 } 339 340 cc_ctx->total_page_num = num_spt_pages; 341 qdf_spinlock_create(&cc_ctx->cc_lock); 342 343 return QDF_STATUS_SUCCESS; 344 fail_1: 345 qdf_mem_free(cc_ctx->page_desc_base); 346 fail_0: 347 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 348 &cc_ctx->page_pool, 0, false); 349 350 return QDF_STATUS_E_FAILURE; 351 } 352 353 QDF_STATUS 354 dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc, 355 struct dp_hw_cookie_conversion_t *cc_ctx) 356 { 357 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 358 359 qdf_mem_free(cc_ctx->page_desc_base); 360 dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE, 361 &cc_ctx->page_pool, 0, false); 362 qdf_spinlock_destroy(&cc_ctx->cc_lock); 363 364 return QDF_STATUS_SUCCESS; 365 } 366 367 QDF_STATUS 368 dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc, 369 struct dp_hw_cookie_conversion_t *cc_ctx) 370 { 371 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 372 uint32_t i = 0; 373 struct dp_spt_page_desc *spt_desc; 374 uint32_t ppt_index; 375 uint32_t ppt_id_start; 376 377 if (!cc_ctx->total_page_num) { 378 dp_err("total page num is 0"); 379 return QDF_STATUS_E_INVAL; 380 } 381 382 ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset); 383 spt_desc = cc_ctx->page_desc_base; 384 while (i < cc_ctx->total_page_num) { 385 /* write page PA to CMEM */ 386 dp_hw_cc_cmem_write(soc->hal_soc, 387 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 388 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 389 (spt_desc[i].page_p_addr >> 390 DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED)); 391 392 ppt_index = ppt_id_start + i; 393 394 if (ppt_index >= DP_CC_PPT_MAX_ENTRIES) 395 qdf_assert_always(0); 396 397 spt_desc[i].ppt_index = ppt_index; 398 399 be_soc->page_desc_base[ppt_index].page_v_addr = 400 spt_desc[i].page_v_addr; 401 i++; 402 } 403 return QDF_STATUS_SUCCESS; 404 } 405 406 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 407 QDF_STATUS 408 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 409 struct dp_hw_cookie_conversion_t *cc_ctx) 410 { 411 uint32_t ppt_index; 412 struct dp_spt_page_desc *spt_desc; 413 int i = 0; 414 415 spt_desc = cc_ctx->page_desc_base; 416 while (i < cc_ctx->total_page_num) { 417 ppt_index = spt_desc[i].ppt_index; 418 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 419 i++; 420 } 421 return QDF_STATUS_SUCCESS; 422 } 423 #else 424 QDF_STATUS 425 dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc, 426 struct dp_hw_cookie_conversion_t *cc_ctx) 427 { 428 struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc); 429 uint32_t ppt_index; 430 struct dp_spt_page_desc *spt_desc; 431 int i = 0; 432 433 spt_desc = cc_ctx->page_desc_base; 434 while (i < cc_ctx->total_page_num) { 435 /* reset PA in CMEM to NULL */ 436 dp_hw_cc_cmem_write(soc->hal_soc, 437 (cc_ctx->cmem_offset + be_soc->cc_cmem_base 438 + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)), 439 0); 440 441 ppt_index = spt_desc[i].ppt_index; 442 be_soc->page_desc_base[ppt_index].page_v_addr = NULL; 443 i++; 444 } 445 return QDF_STATUS_SUCCESS; 446 } 447 #endif 448 449 static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc) 450 { 451 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 452 int i = 0; 453 454 455 for (i = 0; i < MAX_TXDESC_POOLS; i++) 456 dp_hw_cookie_conversion_detach(be_soc, 457 &be_soc->tx_cc_ctx[i]); 458 459 for (i = 0; i < MAX_RXDESC_POOLS; i++) 460 dp_hw_cookie_conversion_detach(be_soc, 461 &be_soc->rx_cc_ctx[i]); 462 463 qdf_mem_free(be_soc->page_desc_base); 464 be_soc->page_desc_base = NULL; 465 466 return QDF_STATUS_SUCCESS; 467 } 468 469 #ifdef WLAN_MLO_MULTI_CHIP 470 #ifdef WLAN_MCAST_MLO 471 static inline void 472 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 473 { 474 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 475 476 be_vdev->mcast_primary = false; 477 be_vdev->seq_num = 0; 478 dp_tx_mcast_mlo_reinject_routing_set(soc, 479 (void *)&be_vdev->mcast_primary); 480 if (vdev->opmode == wlan_op_mode_ap) { 481 if (vdev->mlo_vdev) 482 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 483 vdev->vdev_id, 484 HAL_TX_MCAST_CTRL_DROP); 485 else 486 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 487 vdev->vdev_id, 488 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 489 } 490 } 491 492 static inline void 493 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 494 { 495 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 496 497 be_vdev->seq_num = 0; 498 be_vdev->mcast_primary = false; 499 vdev->mlo_vdev = false; 500 } 501 #else 502 static inline void 503 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 504 { 505 } 506 507 static inline void 508 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 509 { 510 } 511 #endif 512 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 513 { 514 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 515 516 qdf_mem_set(be_vdev->partner_vdev_list, 517 WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC, 518 CDP_INVALID_VDEV_ID); 519 } 520 521 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 522 struct cdp_lro_hash_config *lro_hash) 523 { 524 dp_mlo_get_rx_hash_key(soc, lro_hash); 525 } 526 #else 527 static inline void 528 dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev) 529 { 530 } 531 532 static inline void 533 dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev) 534 { 535 } 536 537 static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev) 538 { 539 } 540 541 static void dp_get_rx_hash_key_be(struct dp_soc *soc, 542 struct cdp_lro_hash_config *lro_hash) 543 { 544 dp_get_rx_hash_key_bytes(lro_hash); 545 } 546 #endif 547 548 static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc, 549 struct cdp_soc_attach_params *params) 550 { 551 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 552 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 553 uint32_t max_tx_rx_desc_num, num_spt_pages; 554 uint32_t num_entries; 555 int i = 0; 556 557 max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS + 558 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS; 559 /* estimate how many SPT DDR pages needed */ 560 num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES; 561 num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ? 562 num_spt_pages : DP_CC_PPT_MAX_ENTRIES; 563 564 be_soc->page_desc_base = qdf_mem_malloc( 565 DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc)); 566 if (!be_soc->page_desc_base) { 567 dp_err("spt page descs allocation failed"); 568 return QDF_STATUS_E_NOMEM; 569 } 570 571 soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id(); 572 573 qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION); 574 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 575 goto fail; 576 577 dp_soc_mlo_fill_params(soc, params); 578 579 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 580 num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx); 581 qdf_status = 582 dp_hw_cookie_conversion_attach(be_soc, 583 &be_soc->tx_cc_ctx[i], 584 num_entries, 585 DP_TX_DESC_TYPE, i); 586 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 587 goto fail; 588 } 589 590 qdf_status = dp_get_cmem_allocation(soc, FISA_FST); 591 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 592 goto fail; 593 594 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 595 num_entries = 596 wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx); 597 qdf_status = 598 dp_hw_cookie_conversion_attach(be_soc, 599 &be_soc->rx_cc_ctx[i], 600 num_entries, 601 DP_RX_DESC_BUF_TYPE, i); 602 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 603 goto fail; 604 } 605 606 return qdf_status; 607 fail: 608 dp_soc_detach_be(soc); 609 return qdf_status; 610 } 611 612 static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc) 613 { 614 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 615 int i = 0; 616 617 dp_tx_deinit_bank_profiles(be_soc); 618 for (i = 0; i < MAX_TXDESC_POOLS; i++) 619 dp_hw_cookie_conversion_deinit(be_soc, 620 &be_soc->tx_cc_ctx[i]); 621 622 for (i = 0; i < MAX_RXDESC_POOLS; i++) 623 dp_hw_cookie_conversion_deinit(be_soc, 624 &be_soc->rx_cc_ctx[i]); 625 626 return QDF_STATUS_SUCCESS; 627 } 628 629 static QDF_STATUS dp_soc_init_be(struct dp_soc *soc) 630 { 631 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 632 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 633 int i = 0; 634 635 for (i = 0; i < MAX_TXDESC_POOLS; i++) { 636 qdf_status = 637 dp_hw_cookie_conversion_init(be_soc, 638 &be_soc->tx_cc_ctx[i]); 639 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 640 goto fail; 641 } 642 643 for (i = 0; i < MAX_RXDESC_POOLS; i++) { 644 qdf_status = 645 dp_hw_cookie_conversion_init(be_soc, 646 &be_soc->rx_cc_ctx[i]); 647 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 648 goto fail; 649 } 650 651 /* route vdev_id mismatch notification via FW completion */ 652 hal_tx_vdev_mismatch_routing_set(soc->hal_soc, 653 HAL_TX_VDEV_MISMATCH_FW_NOTIFY); 654 655 qdf_status = dp_tx_init_bank_profiles(be_soc); 656 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) 657 goto fail; 658 659 /* write WBM/REO cookie conversion CFG register */ 660 dp_cc_reg_cfg_init(soc, true); 661 662 return qdf_status; 663 fail: 664 dp_soc_deinit_be(soc); 665 return qdf_status; 666 } 667 668 static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev, 669 struct cdp_pdev_attach_params *params) 670 { 671 dp_pdev_mlo_fill_params(pdev, params); 672 dp_mlo_update_link_to_pdev_map(pdev->soc, pdev); 673 674 return QDF_STATUS_SUCCESS; 675 } 676 677 static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev) 678 { 679 dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev); 680 681 return QDF_STATUS_SUCCESS; 682 } 683 684 static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev) 685 { 686 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 687 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 688 struct dp_pdev *pdev = vdev->pdev; 689 690 if (vdev->opmode == wlan_op_mode_monitor) 691 return QDF_STATUS_SUCCESS; 692 693 be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE; 694 695 be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev); 696 vdev->bank_id = be_vdev->bank_id; 697 698 if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) { 699 QDF_BUG(0); 700 return QDF_STATUS_E_FAULT; 701 } 702 703 if (vdev->opmode == wlan_op_mode_sta) { 704 if (soc->cdp_soc.ol_ops->set_mec_timer) 705 soc->cdp_soc.ol_ops->set_mec_timer( 706 soc->ctrl_psoc, 707 vdev->vdev_id, 708 DP_AST_AGING_TIMER_DEFAULT_MS); 709 710 if (pdev->isolation) 711 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 712 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 713 else 714 hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, 715 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 716 } 717 718 dp_mlo_mcast_init(soc, vdev); 719 dp_mlo_init_ptnr_list(vdev); 720 721 return QDF_STATUS_SUCCESS; 722 } 723 724 static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev) 725 { 726 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 727 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 728 729 if (vdev->opmode == wlan_op_mode_monitor) 730 return QDF_STATUS_SUCCESS; 731 732 if (vdev->opmode == wlan_op_mode_ap) 733 dp_mlo_mcast_deinit(soc, vdev); 734 735 dp_tx_put_bank_profile(be_soc, be_vdev); 736 dp_clr_mlo_ptnr_list(soc, vdev); 737 738 return QDF_STATUS_SUCCESS; 739 } 740 741 qdf_size_t dp_get_soc_context_size_be(void) 742 { 743 return sizeof(struct dp_soc_be); 744 } 745 746 #ifdef NO_RX_PKT_HDR_TLV 747 /** 748 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 749 * @soc: Common DP soc handle 750 * 751 * Return: QDF_STATUS 752 */ 753 static QDF_STATUS 754 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 755 { 756 int i; 757 int mac_id; 758 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 759 struct dp_srng *rx_mac_srng; 760 QDF_STATUS status = QDF_STATUS_SUCCESS; 761 762 /* 763 * In Beryllium chipset msdu_start, mpdu_end 764 * and rx_attn are part of msdu_end/mpdu_start 765 */ 766 htt_tlv_filter.msdu_start = 0; 767 htt_tlv_filter.mpdu_end = 0; 768 htt_tlv_filter.attention = 0; 769 htt_tlv_filter.mpdu_start = 1; 770 htt_tlv_filter.msdu_end = 1; 771 htt_tlv_filter.packet = 1; 772 htt_tlv_filter.packet_header = 0; 773 774 htt_tlv_filter.ppdu_start = 0; 775 htt_tlv_filter.ppdu_end = 0; 776 htt_tlv_filter.ppdu_end_user_stats = 0; 777 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 778 htt_tlv_filter.ppdu_end_status_done = 0; 779 htt_tlv_filter.enable_fp = 1; 780 htt_tlv_filter.enable_md = 0; 781 htt_tlv_filter.enable_md = 0; 782 htt_tlv_filter.enable_mo = 0; 783 784 htt_tlv_filter.fp_mgmt_filter = 0; 785 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 786 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 787 FILTER_DATA_MCAST | 788 FILTER_DATA_DATA); 789 htt_tlv_filter.mo_mgmt_filter = 0; 790 htt_tlv_filter.mo_ctrl_filter = 0; 791 htt_tlv_filter.mo_data_filter = 0; 792 htt_tlv_filter.md_data_filter = 0; 793 794 htt_tlv_filter.offset_valid = true; 795 796 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 797 htt_tlv_filter.rx_mpdu_end_offset = 0; 798 htt_tlv_filter.rx_msdu_start_offset = 0; 799 htt_tlv_filter.rx_attn_offset = 0; 800 801 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 802 /*Not subscribing rx_pkt_header*/ 803 htt_tlv_filter.rx_header_offset = 0; 804 htt_tlv_filter.rx_mpdu_start_offset = 805 hal_rx_mpdu_start_offset_get(soc->hal_soc); 806 htt_tlv_filter.rx_msdu_end_offset = 807 hal_rx_msdu_end_offset_get(soc->hal_soc); 808 809 for (i = 0; i < MAX_PDEV_CNT; i++) { 810 struct dp_pdev *pdev = soc->pdev_list[i]; 811 812 if (!pdev) 813 continue; 814 815 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 816 int mac_for_pdev = 817 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 818 /* 819 * Obtain lmac id from pdev to access the LMAC ring 820 * in soc context 821 */ 822 int lmac_id = 823 dp_get_lmac_id_for_pdev_id(soc, mac_id, 824 pdev->pdev_id); 825 826 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 827 828 if (!rx_mac_srng->hal_srng) 829 continue; 830 831 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 832 rx_mac_srng->hal_srng, 833 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 834 &htt_tlv_filter); 835 } 836 } 837 return status; 838 } 839 #else 840 /** 841 * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config 842 * @soc: Common DP soc handle 843 * 844 * Return: QDF_STATUS 845 */ 846 static QDF_STATUS 847 dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc) 848 { 849 int i; 850 int mac_id; 851 struct htt_rx_ring_tlv_filter htt_tlv_filter = {0}; 852 struct dp_srng *rx_mac_srng; 853 QDF_STATUS status = QDF_STATUS_SUCCESS; 854 855 /* 856 * In Beryllium chipset msdu_start, mpdu_end 857 * and rx_attn are part of msdu_end/mpdu_start 858 */ 859 htt_tlv_filter.msdu_start = 0; 860 htt_tlv_filter.mpdu_end = 0; 861 htt_tlv_filter.attention = 0; 862 htt_tlv_filter.mpdu_start = 1; 863 htt_tlv_filter.msdu_end = 1; 864 htt_tlv_filter.packet = 1; 865 htt_tlv_filter.packet_header = 1; 866 867 htt_tlv_filter.ppdu_start = 0; 868 htt_tlv_filter.ppdu_end = 0; 869 htt_tlv_filter.ppdu_end_user_stats = 0; 870 htt_tlv_filter.ppdu_end_user_stats_ext = 0; 871 htt_tlv_filter.ppdu_end_status_done = 0; 872 htt_tlv_filter.enable_fp = 1; 873 htt_tlv_filter.enable_md = 0; 874 htt_tlv_filter.enable_md = 0; 875 htt_tlv_filter.enable_mo = 0; 876 877 htt_tlv_filter.fp_mgmt_filter = 0; 878 htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ; 879 htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST | 880 FILTER_DATA_MCAST | 881 FILTER_DATA_DATA); 882 htt_tlv_filter.mo_mgmt_filter = 0; 883 htt_tlv_filter.mo_ctrl_filter = 0; 884 htt_tlv_filter.mo_data_filter = 0; 885 htt_tlv_filter.md_data_filter = 0; 886 887 htt_tlv_filter.offset_valid = true; 888 889 /* Not subscribing to mpdu_end, msdu_start and rx_attn */ 890 htt_tlv_filter.rx_mpdu_end_offset = 0; 891 htt_tlv_filter.rx_msdu_start_offset = 0; 892 htt_tlv_filter.rx_attn_offset = 0; 893 894 htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size; 895 htt_tlv_filter.rx_header_offset = 896 hal_rx_pkt_tlv_offset_get(soc->hal_soc); 897 htt_tlv_filter.rx_mpdu_start_offset = 898 hal_rx_mpdu_start_offset_get(soc->hal_soc); 899 htt_tlv_filter.rx_msdu_end_offset = 900 hal_rx_msdu_end_offset_get(soc->hal_soc); 901 902 dp_info("TLV subscription\n" 903 "msdu_start %d, mpdu_end %d, attention %d" 904 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n" 905 "TLV offsets\n" 906 "msdu_start %d, mpdu_end %d, attention %d" 907 "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n", 908 htt_tlv_filter.msdu_start, 909 htt_tlv_filter.mpdu_end, 910 htt_tlv_filter.attention, 911 htt_tlv_filter.mpdu_start, 912 htt_tlv_filter.msdu_end, 913 htt_tlv_filter.packet_header, 914 htt_tlv_filter.packet, 915 htt_tlv_filter.rx_msdu_start_offset, 916 htt_tlv_filter.rx_mpdu_end_offset, 917 htt_tlv_filter.rx_attn_offset, 918 htt_tlv_filter.rx_mpdu_start_offset, 919 htt_tlv_filter.rx_msdu_end_offset, 920 htt_tlv_filter.rx_header_offset, 921 htt_tlv_filter.rx_packet_offset); 922 923 for (i = 0; i < MAX_PDEV_CNT; i++) { 924 struct dp_pdev *pdev = soc->pdev_list[i]; 925 926 if (!pdev) 927 continue; 928 929 for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) { 930 int mac_for_pdev = 931 dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id); 932 /* 933 * Obtain lmac id from pdev to access the LMAC ring 934 * in soc context 935 */ 936 int lmac_id = 937 dp_get_lmac_id_for_pdev_id(soc, mac_id, 938 pdev->pdev_id); 939 940 rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id); 941 942 if (!rx_mac_srng->hal_srng) 943 continue; 944 945 htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev, 946 rx_mac_srng->hal_srng, 947 RXDMA_BUF, RX_DATA_BUFFER_SIZE, 948 &htt_tlv_filter); 949 } 950 } 951 return status; 952 953 } 954 #endif 955 956 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 957 /** 958 * dp_service_near_full_srngs_be() - Main bottom half callback for the 959 * near-full IRQs. 960 * @soc: Datapath SoC handle 961 * @int_ctx: Interrupt context 962 * @dp_budget: Budget of the work that can be done in the bottom half 963 * 964 * Return: work done in the handler 965 */ 966 static uint32_t 967 dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx, 968 uint32_t dp_budget) 969 { 970 int ring = 0; 971 int budget = dp_budget; 972 uint32_t work_done = 0; 973 uint32_t remaining_quota = dp_budget; 974 struct dp_intr_stats *intr_stats = &int_ctx->intr_stats; 975 int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask; 976 int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask; 977 int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask; 978 int rx_near_full_mask = rx_near_full_grp_1_mask | 979 rx_near_full_grp_2_mask; 980 981 dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x", 982 rx_near_full_mask, 983 tx_ring_near_full_mask); 984 985 if (rx_near_full_mask) { 986 for (ring = 0; ring < soc->num_reo_dest_rings; ring++) { 987 if (!(rx_near_full_mask & (1 << ring))) 988 continue; 989 990 work_done = dp_rx_nf_process(int_ctx, 991 soc->reo_dest_ring[ring].hal_srng, 992 ring, remaining_quota); 993 if (work_done) { 994 intr_stats->num_rx_ring_near_full_masks[ring]++; 995 dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d", 996 rx_near_full_mask, ring, 997 work_done, 998 budget); 999 budget -= work_done; 1000 if (budget <= 0) 1001 goto budget_done; 1002 remaining_quota = budget; 1003 } 1004 } 1005 } 1006 1007 if (tx_ring_near_full_mask) { 1008 for (ring = 0; ring < soc->num_tcl_data_rings; ring++) { 1009 if (!(tx_ring_near_full_mask & (1 << ring))) 1010 continue; 1011 1012 work_done = dp_tx_comp_nf_handler(int_ctx, soc, 1013 soc->tx_comp_ring[ring].hal_srng, 1014 ring, remaining_quota); 1015 if (work_done) { 1016 intr_stats->num_tx_comp_ring_near_full_masks[ring]++; 1017 dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d", 1018 tx_ring_near_full_mask, ring, 1019 work_done, budget); 1020 budget -= work_done; 1021 if (budget <= 0) 1022 break; 1023 remaining_quota = budget; 1024 } 1025 } 1026 } 1027 1028 intr_stats->num_near_full_masks++; 1029 1030 budget_done: 1031 return dp_budget - budget; 1032 } 1033 1034 /** 1035 * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full 1036 * state and set the reap_limit appropriately 1037 * as per the near full state 1038 * @soc: Datapath soc handle 1039 * @dp_srng: Datapath handle for SRNG 1040 * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per 1041 * the srng near-full state 1042 * 1043 * Return: 1, if the srng is in near-full state 1044 * 0, if the srng is not in near-full state 1045 */ 1046 static int 1047 dp_srng_test_and_update_nf_params_be(struct dp_soc *soc, 1048 struct dp_srng *dp_srng, 1049 int *max_reap_limit) 1050 { 1051 return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit); 1052 } 1053 1054 /** 1055 * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the 1056 * near full IRQ handling operations. 1057 * @arch_ops: arch ops handle 1058 * 1059 * Return: none 1060 */ 1061 static inline void 1062 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1063 { 1064 arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be; 1065 arch_ops->dp_srng_test_and_update_nf_params = 1066 dp_srng_test_and_update_nf_params_be; 1067 } 1068 1069 #else 1070 static inline void 1071 dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops) 1072 { 1073 } 1074 #endif 1075 1076 #ifdef WLAN_SUPPORT_PPEDS 1077 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1078 { 1079 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1080 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1081 1082 soc_cfg_ctx = soc->wlan_cfg_ctx; 1083 1084 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1085 return; 1086 1087 dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0); 1088 wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned, 1089 be_soc->ppe_release_ring.alloc_size, 1090 soc->ctrl_psoc, 1091 WLAN_MD_DP_SRNG_PPE_RELEASE, 1092 "ppe_release_ring"); 1093 1094 dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0); 1095 wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1096 be_soc->ppe2tcl_ring.alloc_size, 1097 soc->ctrl_psoc, 1098 WLAN_MD_DP_SRNG_PPE2TCL, 1099 "ppe2tcl_ring"); 1100 1101 dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0); 1102 wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1103 be_soc->reo2ppe_ring.alloc_size, 1104 soc->ctrl_psoc, 1105 WLAN_MD_DP_SRNG_REO2PPE, 1106 "reo2ppe_ring"); 1107 } 1108 1109 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1110 { 1111 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1112 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1113 1114 soc_cfg_ctx = soc->wlan_cfg_ctx; 1115 1116 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1117 return; 1118 1119 dp_srng_free(soc, &be_soc->ppe_release_ring); 1120 1121 dp_srng_free(soc, &be_soc->ppe2tcl_ring); 1122 1123 dp_srng_free(soc, &be_soc->reo2ppe_ring); 1124 } 1125 1126 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1127 { 1128 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1129 uint32_t entries; 1130 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1131 1132 soc_cfg_ctx = soc->wlan_cfg_ctx; 1133 1134 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1135 return QDF_STATUS_SUCCESS; 1136 1137 entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx); 1138 1139 if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE, 1140 entries, 0)) { 1141 dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc); 1142 goto fail; 1143 } 1144 1145 entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx); 1146 if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 1147 entries, 0)) { 1148 dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc); 1149 goto fail; 1150 } 1151 1152 entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx); 1153 if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 1154 entries, 0)) { 1155 dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc); 1156 goto fail; 1157 } 1158 1159 return QDF_STATUS_SUCCESS; 1160 fail: 1161 dp_soc_ppe_srng_free(soc); 1162 return QDF_STATUS_E_NOMEM; 1163 } 1164 1165 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1166 { 1167 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1168 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1169 hal_soc_handle_t hal_soc = soc->hal_soc; 1170 1171 soc_cfg_ctx = soc->wlan_cfg_ctx; 1172 1173 if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx)) 1174 return QDF_STATUS_SUCCESS; 1175 1176 if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) { 1177 dp_err("%pK: dp_srng_init failed for reo2ppe", soc); 1178 goto fail; 1179 } 1180 1181 wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned, 1182 be_soc->reo2ppe_ring.alloc_size, 1183 soc->ctrl_psoc, 1184 WLAN_MD_DP_SRNG_REO2PPE, 1185 "reo2ppe_ring"); 1186 1187 hal_reo_config_reo2ppe_dest_info(hal_soc); 1188 1189 if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) { 1190 dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc); 1191 goto fail; 1192 } 1193 1194 wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned, 1195 be_soc->ppe2tcl_ring.alloc_size, 1196 soc->ctrl_psoc, 1197 WLAN_MD_DP_SRNG_PPE2TCL, 1198 "ppe2tcl_ring"); 1199 1200 if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) { 1201 dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc); 1202 goto fail; 1203 } 1204 1205 wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned, 1206 be_soc->ppe_release_ring.alloc_size, 1207 soc->ctrl_psoc, 1208 WLAN_MD_DP_SRNG_PPE_RELEASE, 1209 "ppe_release_ring"); 1210 1211 return QDF_STATUS_SUCCESS; 1212 fail: 1213 dp_soc_ppe_srng_deinit(soc); 1214 return QDF_STATUS_E_NOMEM; 1215 } 1216 #else 1217 static void dp_soc_ppe_srng_deinit(struct dp_soc *soc) 1218 { 1219 } 1220 1221 static void dp_soc_ppe_srng_free(struct dp_soc *soc) 1222 { 1223 } 1224 1225 static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc) 1226 { 1227 return QDF_STATUS_SUCCESS; 1228 } 1229 1230 static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc) 1231 { 1232 return QDF_STATUS_SUCCESS; 1233 } 1234 #endif 1235 1236 static void dp_soc_srng_deinit_be(struct dp_soc *soc) 1237 { 1238 uint32_t i; 1239 1240 dp_soc_ppe_srng_deinit(soc); 1241 1242 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1243 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1244 dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i], 1245 RXDMA_BUF, 0); 1246 } 1247 } 1248 } 1249 1250 static void dp_soc_srng_free_be(struct dp_soc *soc) 1251 { 1252 uint32_t i; 1253 1254 dp_soc_ppe_srng_free(soc); 1255 1256 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1257 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) 1258 dp_srng_free(soc, &soc->rx_refill_buf_ring[i]); 1259 } 1260 } 1261 1262 static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc) 1263 { 1264 struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx; 1265 uint32_t ring_size; 1266 uint32_t i; 1267 1268 soc_cfg_ctx = soc->wlan_cfg_ctx; 1269 1270 ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx); 1271 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1272 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1273 if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i], 1274 RXDMA_BUF, ring_size, 0)) { 1275 dp_err("%pK: dp_srng_alloc failed refill ring", 1276 soc); 1277 goto fail; 1278 } 1279 } 1280 } 1281 1282 if (dp_soc_ppe_srng_alloc(soc)) { 1283 dp_err("%pK: ppe rings alloc failed", 1284 soc); 1285 goto fail; 1286 } 1287 1288 return QDF_STATUS_SUCCESS; 1289 fail: 1290 dp_soc_srng_free_be(soc); 1291 return QDF_STATUS_E_NOMEM; 1292 } 1293 1294 static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc) 1295 { 1296 int i = 0; 1297 1298 if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) { 1299 for (i = 0; i < soc->num_rx_refill_buf_rings; i++) { 1300 if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i], 1301 RXDMA_BUF, 0, 0)) { 1302 dp_err("%pK: dp_srng_init failed refill ring", 1303 soc); 1304 goto fail; 1305 } 1306 } 1307 } 1308 1309 if (dp_soc_ppe_srng_init(soc)) { 1310 dp_err("%pK: ppe rings init failed", 1311 soc); 1312 goto fail; 1313 } 1314 1315 return QDF_STATUS_SUCCESS; 1316 fail: 1317 dp_soc_srng_deinit_be(soc); 1318 return QDF_STATUS_E_NOMEM; 1319 } 1320 1321 #ifdef WLAN_FEATURE_11BE_MLO 1322 static inline unsigned 1323 dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj, 1324 union dp_align_mac_addr *mac_addr) 1325 { 1326 uint32_t index; 1327 1328 index = 1329 mac_addr->align2.bytes_ab ^ 1330 mac_addr->align2.bytes_cd ^ 1331 mac_addr->align2.bytes_ef; 1332 1333 index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits; 1334 index &= mld_hash_obj->mld_peer_hash.mask; 1335 1336 return index; 1337 } 1338 1339 QDF_STATUS 1340 dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj, 1341 int hash_elems) 1342 { 1343 int i, log2; 1344 1345 if (!mld_hash_obj) 1346 return QDF_STATUS_E_FAILURE; 1347 1348 hash_elems *= DP_PEER_HASH_LOAD_MULT; 1349 hash_elems >>= DP_PEER_HASH_LOAD_SHIFT; 1350 log2 = dp_log2_ceil(hash_elems); 1351 hash_elems = 1 << log2; 1352 1353 mld_hash_obj->mld_peer_hash.mask = hash_elems - 1; 1354 mld_hash_obj->mld_peer_hash.idx_bits = log2; 1355 /* allocate an array of TAILQ peer object lists */ 1356 mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc( 1357 hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer))); 1358 if (!mld_hash_obj->mld_peer_hash.bins) 1359 return QDF_STATUS_E_NOMEM; 1360 1361 for (i = 0; i < hash_elems; i++) 1362 TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]); 1363 1364 qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock); 1365 1366 return QDF_STATUS_SUCCESS; 1367 } 1368 1369 void 1370 dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj) 1371 { 1372 if (!mld_hash_obj) 1373 return; 1374 1375 if (mld_hash_obj->mld_peer_hash.bins) { 1376 qdf_mem_free(mld_hash_obj->mld_peer_hash.bins); 1377 mld_hash_obj->mld_peer_hash.bins = NULL; 1378 qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock); 1379 } 1380 } 1381 1382 #ifdef WLAN_MLO_MULTI_CHIP 1383 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1384 { 1385 /* In case of MULTI chip MLO peer hash table when MLO global object 1386 * is created, avoid from SOC attach path 1387 */ 1388 return QDF_STATUS_SUCCESS; 1389 } 1390 1391 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1392 { 1393 } 1394 #else 1395 static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc) 1396 { 1397 dp_mld_peer_hash_obj_t mld_hash_obj; 1398 1399 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1400 1401 if (!mld_hash_obj) 1402 return QDF_STATUS_E_FAILURE; 1403 1404 return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers); 1405 } 1406 1407 static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc) 1408 { 1409 dp_mld_peer_hash_obj_t mld_hash_obj; 1410 1411 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1412 1413 if (!mld_hash_obj) 1414 return; 1415 1416 return dp_mlo_peer_find_hash_detach_be(mld_hash_obj); 1417 } 1418 #endif 1419 1420 static struct dp_peer * 1421 dp_mlo_peer_find_hash_find_be(struct dp_soc *soc, 1422 uint8_t *peer_mac_addr, 1423 int mac_addr_is_aligned, 1424 enum dp_mod_id mod_id, 1425 uint8_t vdev_id) 1426 { 1427 union dp_align_mac_addr local_mac_addr_aligned, *mac_addr; 1428 uint32_t index; 1429 struct dp_peer *peer; 1430 struct dp_vdev *vdev; 1431 dp_mld_peer_hash_obj_t mld_hash_obj; 1432 1433 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1434 if (!mld_hash_obj) 1435 return NULL; 1436 1437 if (!mld_hash_obj->mld_peer_hash.bins) 1438 return NULL; 1439 1440 if (mac_addr_is_aligned) { 1441 mac_addr = (union dp_align_mac_addr *)peer_mac_addr; 1442 } else { 1443 qdf_mem_copy( 1444 &local_mac_addr_aligned.raw[0], 1445 peer_mac_addr, QDF_MAC_ADDR_SIZE); 1446 mac_addr = &local_mac_addr_aligned; 1447 } 1448 1449 if (vdev_id != DP_VDEV_ALL) { 1450 vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id); 1451 if (!vdev) { 1452 dp_err("vdev is null\n"); 1453 return NULL; 1454 } 1455 } else { 1456 vdev = NULL; 1457 } 1458 /* search mld peer table if no link peer for given mac address */ 1459 index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr); 1460 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1461 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1462 hash_list_elem) { 1463 if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) { 1464 if ((vdev_id == DP_VDEV_ALL) || ( 1465 dp_peer_find_mac_addr_cmp( 1466 &peer->vdev->mld_mac_addr, 1467 &vdev->mld_mac_addr) == 0)) { 1468 /* take peer reference before returning */ 1469 if (dp_peer_get_ref(NULL, peer, mod_id) != 1470 QDF_STATUS_SUCCESS) 1471 peer = NULL; 1472 1473 if (vdev) 1474 dp_vdev_unref_delete(soc, vdev, mod_id); 1475 1476 qdf_spin_unlock_bh( 1477 &mld_hash_obj->mld_peer_hash_lock); 1478 return peer; 1479 } 1480 } 1481 } 1482 1483 if (vdev) 1484 dp_vdev_unref_delete(soc, vdev, mod_id); 1485 1486 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1487 1488 return NULL; /* failure */ 1489 } 1490 1491 static void 1492 dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer) 1493 { 1494 uint32_t index; 1495 struct dp_peer *tmppeer = NULL; 1496 int found = 0; 1497 dp_mld_peer_hash_obj_t mld_hash_obj; 1498 1499 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1500 1501 if (!mld_hash_obj) 1502 return; 1503 1504 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1505 QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index])); 1506 1507 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1508 TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index], 1509 hash_list_elem) { 1510 if (tmppeer == peer) { 1511 found = 1; 1512 break; 1513 } 1514 } 1515 QDF_ASSERT(found); 1516 TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1517 hash_list_elem); 1518 1519 dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG); 1520 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1521 } 1522 1523 static void 1524 dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer) 1525 { 1526 uint32_t index; 1527 dp_mld_peer_hash_obj_t mld_hash_obj; 1528 1529 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1530 1531 if (!mld_hash_obj) 1532 return; 1533 1534 index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr); 1535 1536 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1537 1538 if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer, 1539 DP_MOD_ID_CONFIG))) { 1540 dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT, 1541 QDF_MAC_ADDR_REF(peer->mac_addr.raw)); 1542 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1543 return; 1544 } 1545 TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer, 1546 hash_list_elem); 1547 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1548 } 1549 1550 void dp_print_mlo_ast_stats_be(struct dp_soc *soc) 1551 { 1552 uint32_t index; 1553 struct dp_peer *peer; 1554 dp_mld_peer_hash_obj_t mld_hash_obj; 1555 1556 mld_hash_obj = dp_mlo_get_peer_hash_obj(soc); 1557 1558 if (!mld_hash_obj) 1559 return; 1560 1561 qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock); 1562 for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) { 1563 TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index], 1564 hash_list_elem) { 1565 dp_print_peer_ast_entries(soc, peer, NULL); 1566 } 1567 } 1568 qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock); 1569 } 1570 1571 #endif 1572 1573 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 1574 static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc, 1575 struct dp_vdev *vdev) 1576 { 1577 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1578 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1579 hal_soc_handle_t hal_soc = soc->hal_soc; 1580 uint8_t vdev_id = vdev->vdev_id; 1581 1582 if (vdev->opmode == wlan_op_mode_sta) { 1583 if (vdev->pdev->isolation) 1584 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1585 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1586 else 1587 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1588 HAL_TX_MCAST_CTRL_MEC_NOTIFY); 1589 } else if (vdev->opmode == wlan_op_mode_ap) { 1590 if (vdev->mlo_vdev) { 1591 if (be_vdev->mcast_primary) { 1592 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1593 HAL_TX_MCAST_CTRL_NO_SPECIAL); 1594 hal_tx_vdev_mcast_ctrl_set(hal_soc, 1595 vdev_id + 128, 1596 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1597 dp_mcast_mlo_iter_ptnr_soc(be_soc, 1598 dp_tx_mcast_mlo_reinject_routing_set, 1599 (void *)&be_vdev->mcast_primary); 1600 } else { 1601 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1602 HAL_TX_MCAST_CTRL_DROP); 1603 } 1604 } else { 1605 hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc, 1606 vdev_id, 1607 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1608 } 1609 } 1610 } 1611 1612 static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev) 1613 { 1614 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1615 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1616 union hal_tx_bank_config *bank_config; 1617 1618 if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID) 1619 return; 1620 1621 bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config; 1622 1623 hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config, 1624 be_vdev->bank_id); 1625 } 1626 1627 #endif 1628 1629 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \ 1630 defined(WLAN_MCAST_MLO) 1631 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1632 struct dp_vdev_be *be_vdev, 1633 cdp_config_param_type val) 1634 { 1635 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc( 1636 be_vdev->vdev.pdev->soc); 1637 hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc; 1638 uint8_t vdev_id = be_vdev->vdev.vdev_id; 1639 1640 be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev; 1641 1642 if (be_vdev->mcast_primary) { 1643 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1644 HAL_TX_MCAST_CTRL_NO_SPECIAL); 1645 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128, 1646 HAL_TX_MCAST_CTRL_FW_EXCEPTION); 1647 dp_mcast_mlo_iter_ptnr_soc(be_soc, 1648 dp_tx_mcast_mlo_reinject_routing_set, 1649 (void *)&be_vdev->mcast_primary); 1650 } else { 1651 hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id, 1652 HAL_TX_MCAST_CTRL_DROP); 1653 } 1654 } 1655 #else 1656 static void dp_txrx_set_mlo_mcast_primary_vdev_param_be( 1657 struct dp_vdev_be *be_vdev, 1658 cdp_config_param_type val) 1659 { 1660 } 1661 #endif 1662 1663 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 1664 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1665 uint8_t tx_ring_id, 1666 uint8_t bm_id) 1667 { 1668 hal_tx_config_rbm_mapping_be(soc->hal_soc, 1669 soc->tcl_data_ring[tx_ring_id].hal_srng, 1670 bm_id); 1671 } 1672 #else 1673 static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc, 1674 uint8_t tx_ring_id, 1675 uint8_t bm_id) 1676 { 1677 } 1678 #endif 1679 1680 QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc, 1681 struct dp_vdev *vdev, 1682 enum cdp_vdev_param_type param, 1683 cdp_config_param_type val) 1684 { 1685 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1686 struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev); 1687 1688 switch (param) { 1689 case CDP_TX_ENCAP_TYPE: 1690 case CDP_UPDATE_DSCP_TO_TID_MAP: 1691 case CDP_UPDATE_TDLS_FLAGS: 1692 dp_tx_update_bank_profile(be_soc, be_vdev); 1693 break; 1694 case CDP_ENABLE_CIPHER: 1695 if (vdev->tx_encap_type == htt_cmn_pkt_type_raw) 1696 dp_tx_update_bank_profile(be_soc, be_vdev); 1697 break; 1698 case CDP_SET_MCAST_VDEV: 1699 dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val); 1700 break; 1701 default: 1702 dp_warn("invalid param %d", param); 1703 break; 1704 } 1705 1706 return QDF_STATUS_SUCCESS; 1707 } 1708 1709 #ifdef WLAN_FEATURE_11BE_MLO 1710 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 1711 static inline void 1712 dp_soc_max_peer_id_set(struct dp_soc *soc) 1713 { 1714 soc->peer_id_shift = dp_log2_ceil(soc->max_peers); 1715 soc->peer_id_mask = (1 << soc->peer_id_shift) - 1; 1716 /* 1717 * Double the peers since we use ML indication bit 1718 * alongwith peer_id to find peers. 1719 */ 1720 soc->max_peer_id = 1 << (soc->peer_id_shift + 1); 1721 } 1722 #else 1723 static inline void 1724 dp_soc_max_peer_id_set(struct dp_soc *soc) 1725 { 1726 soc->max_peer_id = 1727 (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1; 1728 } 1729 #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */ 1730 #else 1731 static inline void 1732 dp_soc_max_peer_id_set(struct dp_soc *soc) 1733 { 1734 soc->max_peer_id = soc->max_peers; 1735 } 1736 #endif /* WLAN_FEATURE_11BE_MLO */ 1737 1738 static void dp_peer_map_detach_be(struct dp_soc *soc) 1739 { 1740 if (soc->host_ast_db_enable) 1741 dp_peer_ast_hash_detach(soc); 1742 } 1743 1744 static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc) 1745 { 1746 QDF_STATUS status; 1747 1748 if (soc->host_ast_db_enable) { 1749 status = dp_peer_ast_hash_attach(soc); 1750 if (QDF_IS_STATUS_ERROR(status)) 1751 return status; 1752 } 1753 1754 dp_soc_max_peer_id_set(soc); 1755 1756 return QDF_STATUS_SUCCESS; 1757 } 1758 1759 static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc, 1760 uint8_t *dest_mac, 1761 uint8_t vdev_id) 1762 { 1763 struct dp_peer *peer = NULL; 1764 struct dp_peer *tgt_peer = NULL; 1765 struct dp_ast_entry *ast_entry = NULL; 1766 uint16_t peer_id; 1767 1768 qdf_spin_lock_bh(&soc->ast_lock); 1769 ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac); 1770 if (!ast_entry) { 1771 qdf_spin_unlock_bh(&soc->ast_lock); 1772 dp_err("NULL ast entry"); 1773 return NULL; 1774 } 1775 1776 peer_id = ast_entry->peer_id; 1777 qdf_spin_unlock_bh(&soc->ast_lock); 1778 1779 if (peer_id == HTT_INVALID_PEER) 1780 return NULL; 1781 1782 peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF); 1783 if (!peer) { 1784 dp_err("NULL peer for peer_id:%d", peer_id); 1785 return NULL; 1786 } 1787 1788 tgt_peer = dp_get_tgt_peer_from_peer(peer); 1789 1790 /* 1791 * Once tgt_peer is obtained, 1792 * release the ref taken for original peer. 1793 */ 1794 dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF); 1795 dp_peer_unref_delete(peer, DP_MOD_ID_SAWF); 1796 1797 return tgt_peer; 1798 } 1799 1800 #ifdef WLAN_FEATURE_11BE_MLO 1801 #ifdef WLAN_MCAST_MLO 1802 static inline void 1803 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1804 { 1805 arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be; 1806 arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler; 1807 } 1808 #else /* WLAN_MCAST_MLO */ 1809 static inline void 1810 dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops) 1811 { 1812 } 1813 #endif /* WLAN_MCAST_MLO */ 1814 1815 #ifdef WLAN_MLO_MULTI_CHIP 1816 static inline void 1817 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops) 1818 { 1819 arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map; 1820 arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap; 1821 } 1822 #else 1823 static inline void 1824 dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops) 1825 { 1826 } 1827 #endif 1828 1829 static inline void 1830 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1831 { 1832 dp_initialize_arch_ops_be_mcast_mlo(arch_ops); 1833 dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops); 1834 arch_ops->mlo_peer_find_hash_detach = 1835 dp_mlo_peer_find_hash_detach_wrapper; 1836 arch_ops->mlo_peer_find_hash_attach = 1837 dp_mlo_peer_find_hash_attach_wrapper; 1838 arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be; 1839 arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be; 1840 arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be; 1841 } 1842 #else /* WLAN_FEATURE_11BE_MLO */ 1843 static inline void 1844 dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops) 1845 { 1846 } 1847 #endif /* WLAN_FEATURE_11BE_MLO */ 1848 1849 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1850 #define DP_LMAC_PEER_ID_MSB_LEGACY 2 1851 #define DP_LMAC_PEER_ID_MSB_MLO 3 1852 1853 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 1854 struct cdp_peer_setup_info *setup_info, 1855 enum cdp_host_reo_dest_ring *reo_dest, 1856 bool *hash_based, 1857 uint8_t *lmac_peer_id_msb) 1858 { 1859 struct dp_soc *soc = vdev->pdev->soc; 1860 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1861 1862 if (!be_soc->mlo_enabled) 1863 return dp_vdev_get_default_reo_hash(vdev, reo_dest, 1864 hash_based); 1865 1866 *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx); 1867 *reo_dest = vdev->pdev->reo_dest; 1868 1869 /* Not a ML link peer use non-mlo */ 1870 if (!setup_info) { 1871 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 1872 return; 1873 } 1874 1875 /* For STA ML VAP we do not have num links info at this point 1876 * use MLO case always 1877 */ 1878 if (vdev->opmode == wlan_op_mode_sta) { 1879 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 1880 return; 1881 } 1882 1883 /* For AP ML VAP consider the peer as ML only it associates with 1884 * multiple links 1885 */ 1886 if (setup_info->num_links == 1) { 1887 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY; 1888 return; 1889 } 1890 1891 *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO; 1892 } 1893 1894 static bool dp_reo_remap_config_be(struct dp_soc *soc, 1895 uint32_t *remap0, 1896 uint32_t *remap1, 1897 uint32_t *remap2) 1898 { 1899 struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc); 1900 uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx); 1901 uint32_t reo_mlo_config = 1902 wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx); 1903 1904 if (!be_soc->mlo_enabled) 1905 return dp_reo_remap_config(soc, remap0, remap1, remap2); 1906 1907 *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 1908 *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config); 1909 *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config); 1910 1911 return true; 1912 } 1913 #else 1914 static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev, 1915 struct cdp_peer_setup_info *setup_info, 1916 enum cdp_host_reo_dest_ring *reo_dest, 1917 bool *hash_based, 1918 uint8_t *lmac_peer_id_msb) 1919 { 1920 dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based); 1921 } 1922 1923 static bool dp_reo_remap_config_be(struct dp_soc *soc, 1924 uint32_t *remap0, 1925 uint32_t *remap1, 1926 uint32_t *remap2) 1927 { 1928 return dp_reo_remap_config(soc, remap0, remap1, remap2); 1929 } 1930 #endif 1931 1932 void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops) 1933 { 1934 #ifndef QCA_HOST_MODE_WIFI_DISABLED 1935 arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be; 1936 arch_ops->dp_rx_process = dp_rx_process_be; 1937 arch_ops->dp_tx_send_fast = dp_tx_fast_send_be; 1938 arch_ops->tx_comp_get_params_from_hal_desc = 1939 dp_tx_comp_get_params_from_hal_desc_be; 1940 arch_ops->dp_tx_process_htt_completion = 1941 dp_tx_process_htt_completion_be; 1942 arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be; 1943 arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be; 1944 arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be; 1945 arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be; 1946 arch_ops->dp_wbm_get_rx_desc_from_hal_desc = 1947 dp_wbm_get_rx_desc_from_hal_desc_be; 1948 arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be; 1949 #endif 1950 arch_ops->txrx_get_context_size = dp_get_context_size_be; 1951 #ifdef WIFI_MONITOR_SUPPORT 1952 arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be; 1953 #endif 1954 arch_ops->dp_rx_desc_cookie_2_va = 1955 dp_rx_desc_cookie_2_va_be; 1956 arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be; 1957 1958 arch_ops->txrx_soc_attach = dp_soc_attach_be; 1959 arch_ops->txrx_soc_detach = dp_soc_detach_be; 1960 arch_ops->txrx_soc_init = dp_soc_init_be; 1961 arch_ops->txrx_soc_deinit = dp_soc_deinit_be; 1962 arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be; 1963 arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be; 1964 arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be; 1965 arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be; 1966 arch_ops->txrx_pdev_attach = dp_pdev_attach_be; 1967 arch_ops->txrx_pdev_detach = dp_pdev_detach_be; 1968 arch_ops->txrx_vdev_attach = dp_vdev_attach_be; 1969 arch_ops->txrx_vdev_detach = dp_vdev_detach_be; 1970 arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be; 1971 arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be; 1972 arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be; 1973 arch_ops->dp_rx_peer_metadata_peer_id_get = 1974 dp_rx_peer_metadata_peer_id_get_be; 1975 arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be; 1976 arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be; 1977 arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be; 1978 dp_initialize_arch_ops_be_mlo(arch_ops); 1979 arch_ops->dp_peer_rx_reorder_queue_setup = 1980 dp_peer_rx_reorder_queue_setup_be; 1981 arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be; 1982 arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be; 1983 #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT) 1984 arch_ops->dp_bank_reconfig = dp_bank_reconfig_be; 1985 arch_ops->dp_reconfig_tx_vdev_mcast_ctrl = 1986 dp_reconfig_tx_vdev_mcast_ctrl_be; 1987 arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init; 1988 #endif 1989 dp_init_near_full_arch_ops_be(arch_ops); 1990 arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be; 1991 arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be; 1992 arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be; 1993 arch_ops->reo_remap_config = dp_reo_remap_config_be; 1994 } 1995