1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * @file cdp_txrx_stats_struct.h 21 * @brief Define the host data path stats API functions 22 * called by the host control SW and the OS interface module 23 */ 24 #ifndef _CDP_TXRX_STATS_STRUCT_H_ 25 #define _CDP_TXRX_STATS_STRUCT_H_ 26 #ifndef CONFIG_WIN 27 #include <wlan_defs.h> 28 #endif 29 30 #define TXRX_STATS_LEVEL_OFF 0 31 #define TXRX_STATS_LEVEL_BASIC 1 32 #define TXRX_STATS_LEVEL_FULL 2 33 34 #define BSS_CHAN_INFO_READ 1 35 #define BSS_CHAN_INFO_READ_AND_CLEAR 2 36 37 #define TX_FRAME_TYPE_DATA 0 38 #define TX_FRAME_TYPE_MGMT 1 39 #define TX_FRAME_TYPE_BEACON 2 40 41 #ifndef TXRX_STATS_LEVEL 42 #define TXRX_STATS_LEVEL TXRX_STATS_LEVEL_BASIC 43 #endif 44 45 /* 1 additional MCS is for invalid values */ 46 #define MAX_MCS (12 + 1) 47 #define MAX_MCS_11A 8 48 #define MAX_MCS_11B 7 49 #define MAX_MCS_11AC 12 50 /* 1 additional GI is for invalid values */ 51 #define MAX_GI (4 + 1) 52 #define SS_COUNT 8 53 #define MAX_BW 7 54 #define MAX_RECEPTION_TYPES 4 55 56 /* WME stream classes */ 57 #define WME_AC_BE 0 /* best effort */ 58 #define WME_AC_BK 1 /* background */ 59 #define WME_AC_VI 2 /* video */ 60 #define WME_AC_VO 3 /* voice */ 61 #define WME_AC_MAX 4 /* MAX AC Value */ 62 63 #define CDP_MAX_RX_RINGS 4 64 65 /* 66 * Number of TLVs sent by FW. Needs to reflect 67 * HTT_PPDU_STATS_MAX_TAG declared in FW 68 */ 69 #define CDP_PPDU_STATS_MAX_TAG 14 70 71 /* Different Packet Types */ 72 enum cdp_packet_type { 73 DOT11_A = 0, 74 DOT11_B = 1, 75 DOT11_N = 2, 76 DOT11_AC = 3, 77 DOT11_AX = 4, 78 DOT11_MAX = 5, 79 }; 80 81 /* packet info */ 82 struct cdp_pkt_info { 83 /*no of packets*/ 84 uint32_t num; 85 /* total no of bytes */ 86 uint64_t bytes; 87 }; 88 89 /* Tx Stats */ 90 struct cdp_tx_stats { 91 /* Pkt Info for which completions were received */ 92 struct cdp_pkt_info comp_pkt; 93 /* Unicast Packet Count */ 94 struct cdp_pkt_info ucast; 95 /* Multicast Packet Count */ 96 struct cdp_pkt_info mcast; 97 /* Broadcast Packet Count*/ 98 struct cdp_pkt_info bcast; 99 /*NAWDS Multicast Packet Count */ 100 struct cdp_pkt_info nawds_mcast; 101 /*NAWDS Multicast Drop Count */ 102 uint32_t nawds_mcast_drop; 103 /* Successful Tx Packets */ 104 struct cdp_pkt_info tx_success; 105 /* Total Tx failure */ 106 uint32_t tx_failed; 107 /* Total Packets as ofdma*/ 108 uint32_t ofdma; 109 /* Packets in STBC */ 110 uint32_t stbc; 111 /* Packets in LDPC */ 112 uint32_t ldpc; 113 /* Packet retries */ 114 uint32_t retries; 115 /* Number of MSDUs with no MSDU level aggregation */ 116 uint32_t non_amsdu_cnt; 117 /* Number of MSDUs part of AMSDU*/ 118 uint32_t amsdu_cnt; 119 /* Tx Rate */ 120 uint32_t tx_rate; 121 122 /* RSSI of last packet */ 123 uint32_t last_ack_rssi; 124 125 /* Packet Type */ 126 struct { 127 /* MCS Count */ 128 uint32_t mcs_count[MAX_MCS]; 129 } pkt_type[DOT11_MAX]; 130 131 /* SGI count */ 132 uint32_t sgi_count[MAX_GI]; 133 134 /* Packet count for different num_spatial_stream values */ 135 uint32_t nss[SS_COUNT]; 136 137 /* Packet Count for different bandwidths */ 138 uint32_t bw[MAX_BW]; 139 140 /* Wireless Multimedia type Count */ 141 uint32_t wme_ac_type[WME_AC_MAX]; 142 143 /* Wireless Multimedia type Count */ 144 uint32_t excess_retries_per_ac[WME_AC_MAX]; 145 146 /* Packets dropped on the Tx side */ 147 struct { 148 /* Discarded by firmware */ 149 uint32_t fw_rem; 150 /* firmware_discard_untransmitted */ 151 uint32_t fw_rem_notx; 152 /* firmware_discard_transmitted */ 153 uint32_t fw_rem_tx; 154 /* aged out in mpdu/msdu queues*/ 155 uint32_t age_out; 156 /* discarded by firmware reason 1 */ 157 uint32_t fw_reason1; 158 /* discarded by firmware reason 2 */ 159 uint32_t fw_reason2; 160 /* discarded by firmware reason 3 */ 161 uint32_t fw_reason3; 162 } dropped; 163 }; 164 165 /* Rx Level Stats */ 166 struct cdp_rx_stats { 167 /* Total packets sent up the stack */ 168 struct cdp_pkt_info to_stack; 169 /* Packets received on the reo ring */ 170 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 171 /* Total unicast packets */ 172 struct cdp_pkt_info unicast; 173 /* Total multicast packets */ 174 struct cdp_pkt_info multicast; 175 /* Broadcast Packet Count*/ 176 struct cdp_pkt_info bcast; 177 /* Raw Pakets received */ 178 struct cdp_pkt_info raw; 179 /* Total multicast packets */ 180 uint32_t nawds_mcast_drop; 181 182 struct { 183 /* Intra BSS packets received */ 184 struct cdp_pkt_info pkts; 185 struct cdp_pkt_info fail; 186 } intra_bss; 187 188 /* Errors */ 189 struct { 190 /* Rx MIC errors */ 191 uint32_t mic_err; 192 /* Rx Decryption Errors */ 193 uint32_t decrypt_err; 194 } err; 195 196 /* Wireless Multimedia type Count */ 197 uint32_t wme_ac_type[WME_AC_MAX]; 198 /* Reception type os packets */ 199 uint32_t reception_type[MAX_RECEPTION_TYPES]; 200 /* Packet Type */ 201 struct { 202 /* MCS Count */ 203 uint32_t mcs_count[MAX_MCS]; 204 } pkt_type[DOT11_MAX]; 205 /* SGI count */ 206 uint32_t sgi_count[MAX_GI]; 207 /* Packet count in spatiel Streams */ 208 uint32_t nss[SS_COUNT]; 209 /* Packet Count in different bandwidths */ 210 uint32_t bw[MAX_BW]; 211 /* Number of MSDUs with no MPDU level aggregation */ 212 uint32_t non_ampdu_cnt; 213 /* Number of MSDUs part of AMSPU */ 214 uint32_t ampdu_cnt; 215 /* Number of MSDUs with no MSDU level aggregation */ 216 uint32_t non_amsdu_cnt; 217 /* Number of MSDUs part of AMSDU*/ 218 uint32_t amsdu_cnt; 219 /* Number of bar received */ 220 uint32_t bar_recv_cnt; 221 /* RSSI of received signal */ 222 uint32_t rssi; 223 /*Rx rate */ 224 uint32_t rx_rate; 225 }; 226 227 /* Tx ingress Stats */ 228 struct cdp_tx_ingress_stats { 229 /* Total packets received for transmission */ 230 struct cdp_pkt_info rcvd; 231 /* Tx packets processed*/ 232 struct cdp_pkt_info processed; 233 /* Total packets passed Reinject handler */ 234 struct cdp_pkt_info reinject_pkts; 235 /* Total packets passed to inspect handler */ 236 struct cdp_pkt_info inspect_pkts; 237 /*NAWDS Multicast Packet Count */ 238 struct cdp_pkt_info nawds_mcast; 239 /* Number of broadcast packets */ 240 struct cdp_pkt_info bcast; 241 242 struct { 243 /* Total Raw packets */ 244 struct cdp_pkt_info raw_pkt; 245 /* DMA map error */ 246 uint32_t dma_map_error; 247 } raw; 248 249 /* TSO packets info */ 250 struct { 251 /* No of segments in TSO packets */ 252 uint32_t num_seg; 253 /* total no of TSO packets */ 254 struct cdp_pkt_info tso_pkt; 255 /* TSO packets dropped by host */ 256 uint32_t dropped_host; 257 /* TSO packets dropped by target */ 258 uint32_t dropped_target; 259 } tso; 260 261 /* Scatter Gather packet info */ 262 struct { 263 /* Total scatter gather packets */ 264 struct cdp_pkt_info sg_pkt; 265 /* SG packets dropped by host */ 266 uint32_t dropped_host; 267 /* SG packets dropped by target */ 268 uint32_t dropped_target; 269 /* Dma map error */ 270 uint32_t dma_map_error; 271 } sg; 272 273 /* Multicast Enhancement packets info */ 274 struct { 275 /* total no of multicast conversion packets */ 276 struct cdp_pkt_info mcast_pkt; 277 /* packets dropped due to map error */ 278 uint32_t dropped_map_error; 279 /* packets dropped due to self Mac address */ 280 uint32_t dropped_self_mac; 281 /* Packets dropped due to send fail */ 282 uint32_t dropped_send_fail; 283 /* total unicast packets transmitted */ 284 uint32_t ucast; 285 /* Segment allocation failure */ 286 uint32_t fail_seg_alloc; 287 /* NBUF clone failure */ 288 uint32_t clone_fail; 289 } mcast_en; 290 291 /* Packets dropped on the Tx side */ 292 struct { 293 /* Total scatter gather packets */ 294 struct cdp_pkt_info dropped_pkt; 295 /* Desc Not Available */ 296 uint32_t desc_na; 297 /* Ring Full */ 298 uint32_t ring_full; 299 /* Hwenqueue failed */ 300 uint32_t enqueue_fail; 301 /* DMA failed */ 302 uint32_t dma_error; 303 /* Resource Full: Congestion Control */ 304 uint32_t res_full; 305 } dropped; 306 307 /* Mesh packets info */ 308 struct { 309 /* packets sent to fw */ 310 uint32_t exception_fw; 311 /* packets completions received from fw */ 312 uint32_t completion_fw; 313 } mesh; 314 315 /*Number of packets classified by CCE*/ 316 uint32_t cce_classified; 317 318 /*Number of raw packets classified by CCE*/ 319 uint32_t cce_classified_raw; 320 }; 321 322 struct cdp_vdev_stats { 323 /* Tx ingress stats */ 324 struct cdp_tx_ingress_stats tx_i; 325 /* CDP Tx Stats */ 326 struct cdp_tx_stats tx; 327 /* CDP Rx Stats */ 328 struct cdp_rx_stats rx; 329 }; 330 331 struct cdp_peer_stats { 332 /* CDP Tx Stats */ 333 struct cdp_tx_stats tx; 334 /* CDP Rx Stats */ 335 struct cdp_rx_stats rx; 336 }; 337 338 /* Tx completions per interrupt */ 339 struct cdp_hist_tx_comp { 340 uint32_t pkts_1; 341 uint32_t pkts_2_20; 342 uint32_t pkts_21_40; 343 uint32_t pkts_41_60; 344 uint32_t pkts_61_80; 345 uint32_t pkts_81_100; 346 uint32_t pkts_101_200; 347 uint32_t pkts_201_plus; 348 }; 349 350 /* Rx ring descriptors reaped per interrupt */ 351 struct cdp_hist_rx_ind { 352 uint32_t pkts_1; 353 uint32_t pkts_2_20; 354 uint32_t pkts_21_40; 355 uint32_t pkts_41_60; 356 uint32_t pkts_61_80; 357 uint32_t pkts_81_100; 358 uint32_t pkts_101_200; 359 uint32_t pkts_201_plus; 360 }; 361 362 struct cdp_htt_tlv_hdr { 363 /* BIT [11 : 0] :- tag 364 * BIT [23 : 12] :- length 365 * BIT [31 : 24] :- reserved 366 */ 367 uint32_t tag__length; 368 }; 369 370 #define HTT_STATS_SUBTYPE_MAX 16 371 372 struct cdp_htt_rx_pdev_fw_stats_tlv { 373 struct cdp_htt_tlv_hdr tlv_hdr; 374 375 /* BIT [ 7 : 0] :- mac_id 376 * BIT [31 : 8] :- reserved 377 */ 378 uint32_t mac_id__word; 379 /* Num PPDU status processed from HW */ 380 uint32_t ppdu_recvd; 381 /* Num MPDU across PPDUs with FCS ok */ 382 uint32_t mpdu_cnt_fcs_ok; 383 /* Num MPDU across PPDUs with FCS err */ 384 uint32_t mpdu_cnt_fcs_err; 385 /* Num MSDU across PPDUs */ 386 uint32_t tcp_msdu_cnt; 387 /* Num MSDU across PPDUs */ 388 uint32_t tcp_ack_msdu_cnt; 389 /* Num MSDU across PPDUs */ 390 uint32_t udp_msdu_cnt; 391 /* Num MSDU across PPDUs */ 392 uint32_t other_msdu_cnt; 393 /* Num MPDU on FW ring indicated */ 394 uint32_t fw_ring_mpdu_ind; 395 /* Num MGMT MPDU given to protocol */ 396 uint32_t fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 397 /* Num ctrl MPDU given to protocol */ 398 uint32_t fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 399 /* Num mcast data packet received */ 400 uint32_t fw_ring_mcast_data_msdu; 401 /* Num broadcast data packet received */ 402 uint32_t fw_ring_bcast_data_msdu; 403 /* Num unicat data packet received */ 404 uint32_t fw_ring_ucast_data_msdu; 405 /* Num null data packet received */ 406 uint32_t fw_ring_null_data_msdu; 407 /* Num MPDU on FW ring dropped */ 408 uint32_t fw_ring_mpdu_drop; 409 410 /* Num buf indication to offload */ 411 uint32_t ofld_local_data_ind_cnt; 412 /* Num buf recycle from offload */ 413 uint32_t ofld_local_data_buf_recycle_cnt; 414 /* Num buf indication to data_rx */ 415 uint32_t drx_local_data_ind_cnt; 416 /* Num buf recycle from data_rx */ 417 uint32_t drx_local_data_buf_recycle_cnt; 418 /* Num buf indication to protocol */ 419 uint32_t local_nondata_ind_cnt; 420 /* Num buf recycle from protocol */ 421 uint32_t local_nondata_buf_recycle_cnt; 422 423 /* Num buf fed */ 424 uint32_t fw_status_buf_ring_refill_cnt; 425 /* Num ring empty encountered */ 426 uint32_t fw_status_buf_ring_empty_cnt; 427 /* Num buf fed */ 428 uint32_t fw_pkt_buf_ring_refill_cnt; 429 /* Num ring empty encountered */ 430 uint32_t fw_pkt_buf_ring_empty_cnt; 431 /* Num buf fed */ 432 uint32_t fw_link_buf_ring_refill_cnt; 433 /* Num ring empty encountered */ 434 uint32_t fw_link_buf_ring_empty_cnt; 435 436 /* Num buf fed */ 437 uint32_t host_pkt_buf_ring_refill_cnt; 438 /* Num ring empty encountered */ 439 uint32_t host_pkt_buf_ring_empty_cnt; 440 /* Num buf fed */ 441 uint32_t mon_pkt_buf_ring_refill_cnt; 442 /* Num ring empty encountered */ 443 uint32_t mon_pkt_buf_ring_empty_cnt; 444 /* Num buf fed */ 445 uint32_t mon_status_buf_ring_refill_cnt; 446 /* Num ring empty encountered */ 447 uint32_t mon_status_buf_ring_empty_cnt; 448 /* Num buf fed */ 449 uint32_t mon_desc_buf_ring_refill_cnt; 450 /* Num ring empty encountered */ 451 uint32_t mon_desc_buf_ring_empty_cnt; 452 /* Num buf fed */ 453 uint32_t mon_dest_ring_update_cnt; 454 /* Num ring full encountered */ 455 uint32_t mon_dest_ring_full_cnt; 456 457 /* Num rx suspend is attempted */ 458 uint32_t rx_suspend_cnt; 459 /* Num rx suspend failed */ 460 uint32_t rx_suspend_fail_cnt; 461 /* Num rx resume attempted */ 462 uint32_t rx_resume_cnt; 463 /* Num rx resume failed */ 464 uint32_t rx_resume_fail_cnt; 465 /* Num rx ring switch */ 466 uint32_t rx_ring_switch_cnt; 467 /* Num rx ring restore */ 468 uint32_t rx_ring_restore_cnt; 469 /* Num rx flush issued */ 470 uint32_t rx_flush_cnt; 471 }; 472 473 /* == TX PDEV STATS == */ 474 struct cdp_htt_tx_pdev_stats_cmn_tlv { 475 struct cdp_htt_tlv_hdr tlv_hdr; 476 477 /* BIT [ 7 : 0] :- mac_id 478 * BIT [31 : 8] :- reserved 479 */ 480 uint32_t mac_id__word; 481 /* Num queued to HW */ 482 uint32_t hw_queued; 483 /* Num PPDU reaped from HW */ 484 uint32_t hw_reaped; 485 /* Num underruns */ 486 uint32_t underrun; 487 /* Num HW Paused counter. */ 488 uint32_t hw_paused; 489 /* Num HW flush counter. */ 490 uint32_t hw_flush; 491 /* Num HW filtered counter. */ 492 uint32_t hw_filt; 493 /* Num PPDUs cleaned up in TX abort */ 494 uint32_t tx_abort; 495 /* Num MPDUs requed by SW */ 496 uint32_t mpdu_requed; 497 /* excessive retries */ 498 uint32_t tx_xretry; 499 /* Last used data hw rate code */ 500 uint32_t data_rc; 501 /* frames dropped due to excessive sw retries */ 502 uint32_t mpdu_dropped_xretry; 503 /* illegal rate phy errors */ 504 uint32_t illgl_rate_phy_err; 505 /* wal pdev continuous xretry */ 506 uint32_t cont_xretry; 507 /* wal pdev continuous xretry */ 508 uint32_t tx_timeout; 509 /* wal pdev resets */ 510 uint32_t pdev_resets; 511 /* PhY/BB underrun */ 512 uint32_t phy_underrun; 513 /* MPDU is more than txop limit */ 514 uint32_t txop_ovf; 515 /* Number of Sequences posted */ 516 uint32_t seq_posted; 517 /* Number of Sequences failed queueing */ 518 uint32_t seq_failed_queueing; 519 /* Number of Sequences completed */ 520 uint32_t seq_completed; 521 /* Number of Sequences restarted */ 522 uint32_t seq_restarted; 523 /* Number of MU Sequences posted */ 524 uint32_t mu_seq_posted; 525 /* Number of time HW ring is paused between seq switch within ISR */ 526 uint32_t seq_switch_hw_paused; 527 /* Number of times seq continuation in DSR */ 528 uint32_t next_seq_posted_dsr; 529 /* Number of times seq continuation in ISR */ 530 uint32_t seq_posted_isr; 531 /* Number of seq_ctrl cached. */ 532 uint32_t seq_ctrl_cached; 533 /* Number of MPDUs successfully transmitted */ 534 uint32_t mpdu_count_tqm; 535 /* Number of MSDUs successfully transmitted */ 536 uint32_t msdu_count_tqm; 537 /* Number of MPDUs dropped */ 538 uint32_t mpdu_removed_tqm; 539 /* Number of MSDUs dropped */ 540 uint32_t msdu_removed_tqm; 541 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 542 uint32_t mpdus_sw_flush; 543 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 544 uint32_t mpdus_hw_filter; 545 /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ 546 uint32_t mpdus_truncated; 547 /* Num MPDUs that was tried but didn't receive ACK or BA */ 548 uint32_t mpdus_ack_failed; 549 /* Num MPDUs that was dropped due to expiry (MSDU TTL). */ 550 uint32_t mpdus_expired; 551 /* Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ 552 uint32_t mpdus_seq_hw_retry; 553 /* Num of TQM acked cmds processed */ 554 uint32_t ack_tlv_proc; 555 /* coex_abort_mpdu_cnt valid. */ 556 uint32_t coex_abort_mpdu_cnt_valid; 557 /* coex_abort_mpdu_cnt from TX FES stats. */ 558 uint32_t coex_abort_mpdu_cnt; 559 /* Number of total PPDUs(DATA, MGMT, excludes selfgen) tried over the air (OTA) */ 560 uint32_t num_total_ppdus_tried_ota; 561 /* Number of data PPDUs tried over the air (OTA) */ 562 uint32_t num_data_ppdus_tried_ota; 563 /* Num Local control/mgmt frames (MSDUs) queued */ 564 uint32_t local_ctrl_mgmt_enqued; 565 /* local_ctrl_mgmt_freed: 566 * Num Local control/mgmt frames (MSDUs) done 567 * It includes all local ctrl/mgmt completions 568 * (acked, no ack, flush, TTL, etc) 569 */ 570 uint32_t local_ctrl_mgmt_freed; 571 /* Num Local data frames (MSDUs) queued */ 572 uint32_t local_data_enqued; 573 /* local_data_freed: 574 * Num Local data frames (MSDUs) done 575 * It includes all local data completions 576 * (acked, no ack, flush, TTL, etc) 577 */ 578 uint32_t local_data_freed; 579 }; 580 581 struct cdp_htt_tx_pdev_stats_urrn_tlv_v { 582 struct cdp_htt_tlv_hdr tlv_hdr; 583 uint32_t urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */ 584 }; 585 586 /* NOTE: Variable length TLV, use length spec to infer array size */ 587 struct cdp_htt_tx_pdev_stats_flush_tlv_v { 588 struct cdp_htt_tlv_hdr tlv_hdr; 589 uint32_t flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 590 }; 591 592 /* NOTE: Variable length TLV, use length spec to infer array size */ 593 struct cdp_htt_tx_pdev_stats_sifs_tlv_v { 594 struct cdp_htt_tlv_hdr tlv_hdr; 595 uint32_t sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 596 }; 597 598 /* NOTE: Variable length TLV, use length spec to infer array size */ 599 struct cdp_htt_tx_pdev_stats_phy_err_tlv_v { 600 struct cdp_htt_tlv_hdr tlv_hdr; 601 uint32_t phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 602 }; 603 604 /* == RX PDEV/SOC STATS == */ 605 /* HTT_STATS_RX_SOC_FW_STATS_TAG */ 606 struct cdp_htt_rx_soc_fw_stats_tlv { 607 struct cdp_htt_tlv_hdr tlv_hdr; 608 /* Num Packets received on REO FW ring */ 609 uint32_t fw_reo_ring_data_msdu; 610 /* Num bc/mc packets indicated from fw to host */ 611 uint32_t fw_to_host_data_msdu_bcmc; 612 /* Num unicast packets indicated from fw to host */ 613 uint32_t fw_to_host_data_msdu_uc; 614 /* Num remote buf recycle from offload */ 615 uint32_t ofld_remote_data_buf_recycle_cnt; 616 /* Num remote free buf given to offload */ 617 uint32_t ofld_remote_free_buf_indication_cnt; 618 }; 619 620 struct cdp_htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 621 struct cdp_htt_tlv_hdr tlv_hdr; 622 /* Num total buf refilled from refill ring */ 623 uint32_t refill_ring_num_refill[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 624 }; 625 626 struct cdp_htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 627 struct cdp_htt_tlv_hdr tlv_hdr; 628 /* Num error MPDU for each RxDMA error type */ 629 uint32_t fw_ring_mpdu_err[1]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ 630 }; 631 632 struct cdp_htt_rx_pdev_fw_mpdu_drop_tlv_v { 633 struct cdp_htt_tlv_hdr tlv_hdr; 634 /* Num MPDU dropped */ 635 uint32_t fw_mpdu_drop[1]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 636 }; 637 638 #define HTT_STATS_PHY_ERR_MAX 43 639 640 struct cdp_htt_rx_pdev_fw_stats_phy_err_tlv { 641 struct cdp_htt_tlv_hdr tlv_hdr; 642 643 /* BIT [ 7 : 0] :- mac_id 644 * BIT [31 : 8] :- reserved 645 */ 646 uint32_t mac_id__word; 647 /* Num of phy err */ 648 uint32_t total_phy_err_cnt; 649 /* Counts of different types of phy errs 650 * The mapping of PHY error types to phy_err array elements is HW dependent. 651 * The only currently-supported mapping is shown below: 652 * 653 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 654 * 1 phyrx_err_synth_off 655 * 2 phyrx_err_ofdma_timing 656 * 3 phyrx_err_ofdma_signal_parity 657 * 4 phyrx_err_ofdma_rate_illegal 658 * 5 phyrx_err_ofdma_length_illegal 659 * 6 phyrx_err_ofdma_restart 660 * 7 phyrx_err_ofdma_service 661 * 8 phyrx_err_ppdu_ofdma_power_drop 662 * 9 phyrx_err_cck_blokker 663 * 10 phyrx_err_cck_timing 664 * 11 phyrx_err_cck_header_crc 665 * 12 phyrx_err_cck_rate_illegal 666 * 13 phyrx_err_cck_length_illegal 667 * 14 phyrx_err_cck_restart 668 * 15 phyrx_err_cck_service 669 * 16 phyrx_err_cck_power_drop 670 * 17 phyrx_err_ht_crc_err 671 * 18 phyrx_err_ht_length_illegal 672 * 19 phyrx_err_ht_rate_illegal 673 * 20 phyrx_err_ht_zlf 674 * 21 phyrx_err_false_radar_ext 675 * 22 phyrx_err_green_field 676 * 23 phyrx_err_bw_gt_dyn_bw 677 * 24 phyrx_err_leg_ht_mismatch 678 * 25 phyrx_err_vht_crc_error 679 * 26 phyrx_err_vht_siga_unsupported 680 * 27 phyrx_err_vht_lsig_len_invalid 681 * 28 phyrx_err_vht_ndp_or_zlf 682 * 29 phyrx_err_vht_nsym_lt_zero 683 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 684 * 31 phyrx_err_vht_rx_skip_group_id0 685 * 32 phyrx_err_vht_rx_skip_group_id1to62 686 * 33 phyrx_err_vht_rx_skip_group_id63 687 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 688 * 35 phyrx_err_defer_nap 689 * 36 phyrx_err_fdomain_timeout 690 * 37 phyrx_err_lsig_rel_check 691 * 38 phyrx_err_bt_collision 692 * 39 phyrx_err_unsupported_mu_feedback 693 * 40 phyrx_err_ppdu_tx_interrupt_rx 694 * 41 phyrx_err_unsupported_cbf 695 * 42 phyrx_err_other 696 */ 697 uint32_t phy_err[HTT_STATS_PHY_ERR_MAX]; 698 }; 699 700 struct cdp_htt_rx_soc_fw_refill_ring_empty_tlv_v { 701 struct cdp_htt_tlv_hdr tlv_hdr; 702 /* Num ring empty encountered */ 703 uint32_t refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 704 }; 705 706 struct cdp_htt_tx_pdev_stats { 707 struct cdp_htt_tx_pdev_stats_cmn_tlv cmn_tlv; 708 struct cdp_htt_tx_pdev_stats_urrn_tlv_v underrun_tlv; 709 struct cdp_htt_tx_pdev_stats_sifs_tlv_v sifs_tlv; 710 struct cdp_htt_tx_pdev_stats_flush_tlv_v flush_tlv; 711 struct cdp_htt_tx_pdev_stats_phy_err_tlv_v phy_err_tlv; 712 }; 713 714 struct cdp_htt_rx_soc_stats_t { 715 struct cdp_htt_rx_soc_fw_stats_tlv fw_tlv; 716 struct cdp_htt_rx_soc_fw_refill_ring_empty_tlv_v fw_refill_ring_empty_tlv; 717 struct cdp_htt_rx_soc_fw_refill_ring_num_refill_tlv_v fw_refill_ring_num_refill_tlv; 718 }; 719 720 struct cdp_htt_rx_pdev_stats { 721 struct cdp_htt_rx_soc_stats_t soc_stats; 722 struct cdp_htt_rx_pdev_fw_stats_tlv fw_stats_tlv; 723 struct cdp_htt_rx_pdev_fw_ring_mpdu_err_tlv_v fw_ring_mpdu_err_tlv; 724 struct cdp_htt_rx_pdev_fw_mpdu_drop_tlv_v fw_ring_mpdu_drop; 725 struct cdp_htt_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; 726 }; 727 728 struct cdp_pdev_stats { 729 /* packets dropped on rx */ 730 struct { 731 /* packets dropped because nsdu_done bit not set */ 732 uint32_t msdu_not_done; 733 /* Multicast Echo check */ 734 uint32_t mec; 735 /* Mesh Filtered packets */ 736 uint32_t mesh_filter; 737 /* packets dropped on monitor vap */ 738 uint32_t mon_rx_drop; 739 } dropped; 740 741 struct { 742 /* total packets replnished */ 743 struct cdp_pkt_info pkts; 744 /* rxdma errors */ 745 uint32_t rxdma_err; 746 /* nbuf alloc failed */ 747 uint32_t nbuf_alloc_fail; 748 /* Mapping failure */ 749 uint32_t map_err; 750 /* x86 failures */ 751 uint32_t x86_fail; 752 /* low threshold interrupts */ 753 uint32_t low_thresh_intrs; 754 } replenish; 755 756 /* Rx Raw Packets */ 757 uint32_t rx_raw_pkts; 758 /* Mesh Rx Stats Alloc fail */ 759 uint32_t mesh_mem_alloc; 760 761 /* Rx errors */ 762 struct { 763 /* desc alloc failed errors */ 764 uint32_t desc_alloc_fail; 765 /* ip csum errors */ 766 uint32_t ip_csum_err; 767 /* tcp/udp csum errors */ 768 uint32_t tcp_udp_csum_err; 769 } err; 770 771 /* buffers added back in freelist */ 772 uint32_t buf_freelist; 773 /* Tx Ingress stats */ 774 struct cdp_tx_ingress_stats tx_i; 775 /* CDP Tx Stats */ 776 struct cdp_tx_stats tx; 777 /* CDP Rx Stats */ 778 struct cdp_rx_stats rx; 779 /* Number of Tx completions per interrupt */ 780 struct cdp_hist_tx_comp tx_comp_histogram; 781 /* Number of Rx ring descriptors reaped per interrupt */ 782 struct cdp_hist_rx_ind rx_ind_histogram; 783 uint64_t ppdu_stats_counter[CDP_PPDU_STATS_MAX_TAG]; 784 785 struct cdp_htt_tx_pdev_stats htt_tx_pdev_stats; 786 struct cdp_htt_rx_pdev_stats htt_rx_pdev_stats; 787 }; 788 789 #ifndef BIG_ENDIAN_HOST 790 typedef struct { 791 uint64_t pkts; 792 uint64_t bytes; 793 } ol_txrx_stats_elem; 794 #else 795 struct ol_txrx_elem_t { 796 uint64_t pkts; 797 uint64_t bytes; 798 }; 799 typedef struct ol_txrx_elem_t ol_txrx_stats_elem; 800 #endif 801 802 #ifndef CONFIG_MCL 803 /** 804 * @brief data stats published by the host txrx layer 805 */ 806 struct ol_txrx_stats { 807 struct { 808 /* MSDUs received from the stack */ 809 ol_txrx_stats_elem from_stack; 810 /* MSDUs successfully sent across the WLAN */ 811 ol_txrx_stats_elem delivered; 812 struct { 813 /* MSDUs that the host did not accept */ 814 ol_txrx_stats_elem host_reject; 815 /* MSDUs which could not be downloaded to the target */ 816 ol_txrx_stats_elem download_fail; 817 /* 818 * MSDUs which the target discarded 819 * (lack of mem or old age) 820 */ 821 ol_txrx_stats_elem target_discard; 822 /* 823 * MSDUs which the target sent but couldn't get 824 * an ack for 825 */ 826 ol_txrx_stats_elem no_ack; 827 /* MSDUs dropped in NSS-FW */ 828 ol_txrx_stats_elem nss_ol_dropped; 829 } dropped; 830 u_int32_t desc_in_use; 831 u_int32_t desc_alloc_fails; 832 u_int32_t ce_ring_full; 833 u_int32_t dma_map_error; 834 /* MSDUs given to the txrx layer by the management stack */ 835 ol_txrx_stats_elem mgmt; 836 struct { 837 /* TSO applied jumbo packets received from NW Stack */ 838 ol_txrx_stats_elem tso_pkts; 839 /* Non - TSO packets */ 840 ol_txrx_stats_elem non_tso_pkts; 841 /* TSO packets : Dropped during TCP segmentation*/ 842 ol_txrx_stats_elem tso_dropped; 843 /* TSO Descriptors */ 844 u_int32_t tso_desc_cnt; 845 } tso; 846 847 struct { 848 /* TSO applied jumbo packets received from NW Stack */ 849 ol_txrx_stats_elem sg_pkts; 850 /* Non - TSO packets */ 851 ol_txrx_stats_elem non_sg_pkts; 852 /* TSO packets : Dropped during TCP segmentation*/ 853 ol_txrx_stats_elem sg_dropped; 854 /* TSO Descriptors */ 855 u_int32_t sg_desc_cnt; 856 } sg; 857 struct { 858 /* packets enqueued for flow control */ 859 u_int32_t fl_ctrl_enqueue; 860 /* packets discarded for flow control is full */ 861 u_int32_t fl_ctrl_discard; 862 /* packets sent to CE without flow control */ 863 u_int32_t fl_ctrl_avoid; 864 } fl_ctrl; 865 } tx; 866 struct { 867 /* MSDUs given to the OS shim */ 868 ol_txrx_stats_elem delivered; 869 /* MSDUs forwarded from the rx path to the tx path */ 870 ol_txrx_stats_elem forwarded; 871 /* MSDUs in which ipv4 chksum error detected by HW */ 872 ol_txrx_stats_elem ipv4_cksum_err; 873 /* MSDUs in which tcp chksum error detected by HW */ 874 ol_txrx_stats_elem tcp_ipv4_cksum_err; 875 /* MSDUs in which udp chksum error detected by HW */ 876 ol_txrx_stats_elem udp_ipv4_cksum_err; 877 /* MSDUs in which tcp V6 chksum error detected by HW */ 878 ol_txrx_stats_elem tcp_ipv6_cksum_err; 879 /* MSDUs in which UDP V6 chksum error detected by HW */ 880 ol_txrx_stats_elem udp_ipv6_cksum_err; 881 } rx; 882 struct { 883 /* Number of mcast received for conversion */ 884 u_int32_t num_me_rcvd; 885 /* Number of unicast sent as part of mcast conversion */ 886 u_int32_t num_me_ucast; 887 /* Number of multicast frames dropped due to dma_map failure */ 888 u_int32_t num_me_dropped_m; 889 /* 890 * Number of multicast frames dropped due to allocation 891 * failure 892 */ 893 u_int32_t num_me_dropped_a; 894 /* Number of multicast frames dropped due to internal failure */ 895 u_int32_t num_me_dropped_i; 896 /* Number of me buf currently in use */ 897 u_int32_t num_me_buf; 898 /* Number of me buf frames to self mac address */ 899 u_int32_t num_me_dropped_s; 900 /* Number of me buf in use in non pool based allocation*/ 901 u_int32_t num_me_nonpool; 902 /* Number of me buf allocated using non pool based allocation*/ 903 u_int32_t num_me_nonpool_count; 904 } mcast_enhance; 905 }; 906 907 struct ol_ath_dbg_rx_rssi { 908 uint8_t rx_rssi_pri20; 909 uint8_t rx_rssi_sec20; 910 uint8_t rx_rssi_sec40; 911 uint8_t rx_rssi_sec80; 912 }; 913 914 struct ol_ath_radiostats { 915 uint64_t tx_beacon; 916 uint32_t be_nobuf; 917 uint32_t tx_buf_count; 918 uint32_t tx_packets; 919 uint32_t rx_packets; 920 int32_t tx_mgmt; 921 uint32_t tx_num_data; 922 uint32_t rx_num_data; 923 int32_t rx_mgmt; 924 uint32_t rx_num_mgmt; 925 uint32_t rx_num_ctl; 926 uint32_t tx_rssi; 927 uint32_t tx_mcs[10]; 928 uint32_t rx_mcs[10]; 929 uint32_t rx_rssi_comb; 930 struct ol_ath_dbg_rx_rssi rx_rssi_chain0; 931 struct ol_ath_dbg_rx_rssi rx_rssi_chain1; 932 struct ol_ath_dbg_rx_rssi rx_rssi_chain2; 933 struct ol_ath_dbg_rx_rssi rx_rssi_chain3; 934 uint64_t rx_bytes; 935 uint64_t tx_bytes; 936 uint32_t tx_compaggr; 937 uint32_t rx_aggr; 938 uint32_t tx_bawadv; 939 uint32_t tx_compunaggr; 940 uint32_t rx_overrun; 941 uint32_t rx_badcrypt; 942 uint32_t rx_badmic; 943 uint32_t rx_crcerr; 944 uint32_t rx_phyerr; 945 uint32_t ackRcvBad; 946 uint32_t rtsBad; 947 uint32_t rtsGood; 948 uint32_t fcsBad; 949 uint32_t noBeacons; 950 uint32_t mib_int_count; 951 uint32_t rx_looplimit_start; 952 uint32_t rx_looplimit_end; 953 uint8_t ap_stats_tx_cal_enable; 954 uint8_t self_bss_util; 955 uint8_t obss_util; 956 uint32_t tgt_asserts; 957 int16_t chan_nf; 958 uint32_t rx_last_msdu_unset_cnt; 959 int16_t chan_nf_sec80; 960 uint64_t wmi_tx_mgmt; 961 uint64_t wmi_tx_mgmt_completions; 962 uint32_t wmi_tx_mgmt_completion_err; 963 uint32_t peer_delete_req; 964 uint32_t peer_delete_resp; 965 uint32_t rx_mgmt_rssi_drop; 966 uint32_t tx_retries; 967 uint32_t rx_data_bytes; 968 uint32_t tx_frame_count; 969 uint32_t rx_frame_count; 970 uint32_t rx_clear_count; 971 uint32_t cycle_count; 972 uint32_t phy_err_count; 973 uint32_t chan_tx_pwr; 974 }; 975 976 /* 977 * Enumeration of PDEV Configuration parameter 978 */ 979 enum _ol_ath_param_t { 980 OL_ATH_PARAM_TXCHAINMASK = 1, 981 OL_ATH_PARAM_RXCHAINMASK = 2, 982 OL_ATH_PARAM_AMPDU = 6, 983 OL_ATH_PARAM_AMPDU_LIMIT = 7, 984 OL_ATH_PARAM_AMPDU_SUBFRAMES = 8, 985 OL_ATH_PARAM_TXPOWER_LIMIT2G = 12, 986 OL_ATH_PARAM_TXPOWER_LIMIT5G = 13, 987 OL_ATH_PARAM_LDPC = 32, 988 OL_ATH_PARAM_VOW_EXT_STATS = 45, 989 OL_ATH_PARAM_DYN_TX_CHAINMASK = 73, 990 OL_ATH_PARAM_BURST_ENABLE = 77, 991 OL_ATH_PARAM_BURST_DUR = 78, 992 OL_ATH_PARAM_BCN_BURST = 80, 993 OL_ATH_PARAM_DCS = 82, 994 #if UMAC_SUPPORT_PERIODIC_PERFSTATS 995 OL_ATH_PARAM_PRDPERFSTAT_THRPUT_ENAB = 83, 996 OL_ATH_PARAM_PRDPERFSTAT_THRPUT_WIN = 84, 997 OL_ATH_PARAM_PRDPERFSTAT_THRPUT = 85, 998 OL_ATH_PARAM_PRDPERFSTAT_PER_ENAB = 86, 999 OL_ATH_PARAM_PRDPERFSTAT_PER_WIN = 87, 1000 OL_ATH_PARAM_PRDPERFSTAT_PER = 88, 1001 #endif 1002 /* UMAC_SUPPORT_PERIODIC_PERFSTATS */ 1003 OL_ATH_PARAM_TOTAL_PER = 89, 1004 /* set manual rate for rts frame */ 1005 OL_ATH_PARAM_RTS_CTS_RATE = 92, 1006 /* co channel interference threshold level */ 1007 OL_ATH_PARAM_DCS_COCH_THR = 93, 1008 /* transmit error threshold */ 1009 OL_ATH_PARAM_DCS_TXERR_THR = 94, 1010 /* phy error threshold */ 1011 OL_ATH_PARAM_DCS_PHYERR_THR = 95, 1012 /* 1013 * The IOCTL number is 114, it is made 114, inorder to make the IOCTL 1014 * number same as Direct-attach IOCTL. 1015 * Please, don't change number. This IOCTL gets the Interface code path 1016 * it should be either DIRECT-ATTACH or OFF-LOAD. 1017 */ 1018 OL_ATH_PARAM_GET_IF_ID = 114, 1019 /* Enable Acs back Ground Channel selection Scan timer in AP mode*/ 1020 OL_ATH_PARAM_ACS_ENABLE_BK_SCANTIMEREN = 118, 1021 /* ACS scan timer value in Seconds */ 1022 OL_ATH_PARAM_ACS_SCANTIME = 119, 1023 /* Negligence Delta RSSI between two channel */ 1024 OL_ATH_PARAM_ACS_RSSIVAR = 120, 1025 /* Negligence Delta Channel load between two channel*/ 1026 OL_ATH_PARAM_ACS_CHLOADVAR = 121, 1027 /* Enable Limited OBSS check */ 1028 OL_ATH_PARAM_ACS_LIMITEDOBSS = 122, 1029 /* Acs control flag for Scan timer */ 1030 OL_ATH_PARAM_ACS_CTRLFLAG = 123, 1031 /* Acs Run time Debug level*/ 1032 OL_ATH_PARAM_ACS_DEBUGTRACE = 124, 1033 OL_ATH_PARAM_SET_FW_HANG_ID = 137, 1034 /* Radio type 1:11ac 0:11abgn */ 1035 OL_ATH_PARAM_RADIO_TYPE = 138, 1036 OL_ATH_PARAM_IGMPMLD_OVERRIDE, /* IGMP/MLD packet override */ 1037 OL_ATH_PARAM_IGMPMLD_TID, /* IGMP/MLD packet TID no */ 1038 OL_ATH_PARAM_ARPDHCP_AC_OVERRIDE, 1039 OL_ATH_PARAM_NON_AGG_SW_RETRY_TH, 1040 OL_ATH_PARAM_AGG_SW_RETRY_TH, 1041 /* Dont change this number it as per sync with DA 1042 Blocking certian channel from ic channel list */ 1043 OL_ATH_PARAM_DISABLE_DFS = 144, 1044 OL_ATH_PARAM_ENABLE_AMSDU = 145, 1045 OL_ATH_PARAM_ENABLE_AMPDU = 146, 1046 OL_ATH_PARAM_STA_KICKOUT_TH, 1047 OL_ATH_PARAM_WLAN_PROF_ENABLE, 1048 OL_ATH_PARAM_LTR_ENABLE, 1049 OL_ATH_PARAM_LTR_AC_LATENCY_BE = 150, 1050 OL_ATH_PARAM_LTR_AC_LATENCY_BK, 1051 OL_ATH_PARAM_LTR_AC_LATENCY_VI, 1052 OL_ATH_PARAM_LTR_AC_LATENCY_VO, 1053 OL_ATH_PARAM_LTR_AC_LATENCY_TIMEOUT, 1054 OL_ATH_PARAM_LTR_TX_ACTIVITY_TIMEOUT = 155, 1055 OL_ATH_PARAM_LTR_SLEEP_OVERRIDE, 1056 OL_ATH_PARAM_LTR_RX_OVERRIDE, 1057 OL_ATH_PARAM_L1SS_ENABLE, 1058 OL_ATH_PARAM_DSLEEP_ENABLE, 1059 /* radar error threshold */ 1060 OL_ATH_PARAM_DCS_RADAR_ERR_THR = 160, 1061 /* Tx channel utilization due to AP's tx and rx */ 1062 OL_ATH_PARAM_DCS_USERMAX_CU_THR, 1063 /* interference detection threshold */ 1064 OL_ATH_PARAM_DCS_INTR_DETECT_THR, 1065 /* sampling window, default 10secs */ 1066 OL_ATH_PARAM_DCS_SAMPLE_WINDOW, 1067 /* debug logs enable/disable */ 1068 OL_ATH_PARAM_DCS_DEBUG, 1069 OL_ATH_PARAM_ANI_ENABLE = 165, 1070 OL_ATH_PARAM_ANI_POLL_PERIOD, 1071 OL_ATH_PARAM_ANI_LISTEN_PERIOD, 1072 OL_ATH_PARAM_ANI_OFDM_LEVEL, 1073 OL_ATH_PARAM_ANI_CCK_LEVEL, 1074 OL_ATH_PARAM_DSCP_TID_MAP = 170, 1075 OL_ATH_PARAM_TXPOWER_SCALE, 1076 /* Phy error penalty */ 1077 OL_ATH_PARAM_DCS_PHYERR_PENALTY, 1078 #if ATH_SUPPORT_DSCP_OVERRIDE 1079 /* set/get TID for sending HMMC packets */ 1080 OL_ATH_PARAM_HMMC_DSCP_TID_MAP, 1081 /* set/get DSCP mapping override */ 1082 OL_ATH_PARAM_DSCP_OVERRIDE, 1083 /* set/get HMMC-DSCP mapping override */ 1084 OL_ATH_PARAM_HMMC_DSCP_OVERRIDE = 175, 1085 #endif 1086 #if ATH_RX_LOOPLIMIT_TIMER 1087 OL_ATH_PARAM_LOOPLIMIT_NUM, 1088 #endif 1089 OL_ATH_PARAM_ANTENNA_GAIN_2G, 1090 OL_ATH_PARAM_ANTENNA_GAIN_5G, 1091 OL_ATH_PARAM_RX_FILTER, 1092 #if ATH_SUPPORT_HYFI_ENHANCEMENTS 1093 OL_ATH_PARAM_BUFF_THRESH = 180, 1094 OL_ATH_PARAM_BLK_REPORT_FLOOD, 1095 OL_ATH_PARAM_DROP_STA_QUERY, 1096 #endif 1097 OL_ATH_PARAM_QBOOST, 1098 OL_ATH_PARAM_SIFS_FRMTYPE, 1099 OL_ATH_PARAM_SIFS_UAPSD = 185, 1100 OL_ATH_PARAM_FW_RECOVERY_ID, 1101 OL_ATH_PARAM_RESET_OL_STATS, 1102 OL_ATH_PARAM_AGGR_BURST, 1103 /* Number of deauth sent in consecutive rx_peer_invalid */ 1104 OL_ATH_PARAM_DEAUTH_COUNT, 1105 OL_ATH_PARAM_BLOCK_INTERBSS = 190, 1106 /* Firmware reset control for Bmiss / timeout / reset */ 1107 OL_ATH_PARAM_FW_DISABLE_RESET, 1108 OL_ATH_PARAM_MSDU_TTL, 1109 OL_ATH_PARAM_PPDU_DURATION, 1110 OL_ATH_PARAM_SET_TXBF_SND_PERIOD, 1111 OL_ATH_PARAM_ALLOW_PROMISC = 195, 1112 OL_ATH_PARAM_BURST_MODE, 1113 OL_ATH_PARAM_DYN_GROUPING, 1114 OL_ATH_PARAM_DPD_ENABLE, 1115 OL_ATH_PARAM_DBGLOG_RATELIM, 1116 /* firmware should intimate us about ps state change for node */ 1117 OL_ATH_PARAM_PS_STATE_CHANGE = 200, 1118 OL_ATH_PARAM_MCAST_BCAST_ECHO, 1119 /* OBSS RSSI threshold for 20/40 coexistence */ 1120 OL_ATH_PARAM_OBSS_RSSI_THRESHOLD, 1121 /* Link/node RX RSSI threshold for 20/40 coexistence */ 1122 OL_ATH_PARAM_OBSS_RX_RSSI_THRESHOLD, 1123 #if ATH_CHANNEL_BLOCKING 1124 OL_ATH_PARAM_ACS_BLOCK_MODE = 205, 1125 #endif 1126 OL_ATH_PARAM_ACS_TX_POWER_OPTION, 1127 /* 1128 * Default Antenna Polarization MSB 8 bits (24:31) specifying 1129 * enable/disable ; LSB 24 bits (0:23) antenna mask value 1130 */ 1131 OL_ATH_PARAM_ANT_POLARIZATION, 1132 /* rate limit mute type error prints */ 1133 OL_ATH_PARAM_PRINT_RATE_LIMIT, 1134 OL_ATH_PARAM_PDEV_RESET, /* Reset FW PDEV*/ 1135 /* Do not crash host when target assert happened*/ 1136 OL_ATH_PARAM_FW_DUMP_NO_HOST_CRASH = 210, 1137 /* Consider OBSS non-erp to change to long slot*/ 1138 OL_ATH_PARAM_CONSIDER_OBSS_NON_ERP_LONG_SLOT = 211, 1139 OL_ATH_PARAM_STATS_FC, 1140 OL_ATH_PARAM_QFLUSHINTERVAL, 1141 OL_ATH_PARAM_TOTAL_Q_SIZE, 1142 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE0, 1143 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE1, 1144 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE2, 1145 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE3, 1146 OL_ATH_PARAM_MIN_THRESHOLD, 1147 OL_ATH_PARAM_MAX_Q_LIMIT, 1148 OL_ATH_PARAM_MIN_Q_LIMIT, 1149 OL_ATH_PARAM_CONG_CTRL_TIMER_INTV, 1150 OL_ATH_PARAM_STATS_TIMER_INTV, 1151 OL_ATH_PARAM_ROTTING_TIMER_INTV, 1152 OL_ATH_PARAM_LATENCY_PROFILE, 1153 OL_ATH_PARAM_HOSTQ_DUMP, 1154 OL_ATH_PARAM_TIDQ_MAP, 1155 OL_ATH_PARAM_DBG_ARP_SRC_ADDR, /* ARP DEBUG source address*/ 1156 OL_ATH_PARAM_DBG_ARP_DST_ADDR, /* ARP DEBUG destination address*/ 1157 OL_ATH_PARAM_ARP_DBG_CONF, /* ARP debug configuration */ 1158 OL_ATH_PARAM_DISABLE_STA_VAP_AMSDU, /* Disable AMSDU for station vap */ 1159 #if ATH_SUPPORT_DFS && ATH_SUPPORT_STA_DFS 1160 OL_ATH_PARAM_STADFS_ENABLE = 300, /* STA DFS is enabled or not */ 1161 #endif 1162 #if QCA_AIRTIME_FAIRNESS 1163 OL_ATH_PARAM_ATF_STRICT_SCHED = 301, 1164 OL_ATH_PARAM_ATF_GROUP_POLICY = 302, 1165 #endif 1166 #if DBDC_REPEATER_SUPPORT 1167 OL_ATH_PARAM_PRIMARY_RADIO, 1168 OL_ATH_PARAM_DBDC_ENABLE, 1169 #endif 1170 OL_ATH_PARAM_TXPOWER_DBSCALE, 1171 OL_ATH_PARAM_CTL_POWER_SCALE, 1172 #if QCA_AIRTIME_FAIRNESS 1173 OL_ATH_PARAM_ATF_OBSS_SCHED = 307, 1174 OL_ATH_PARAM_ATF_OBSS_SCALE = 308, 1175 #endif 1176 OL_ATH_PARAM_PHY_OFDM_ERR = 309, 1177 OL_ATH_PARAM_PHY_CCK_ERR = 310, 1178 OL_ATH_PARAM_FCS_ERR = 311, 1179 OL_ATH_PARAM_CHAN_UTIL = 312, 1180 #if DBDC_REPEATER_SUPPORT 1181 OL_ATH_PARAM_CLIENT_MCAST, 1182 #endif 1183 OL_ATH_PARAM_EMIWAR_80P80 = 314, 1184 OL_ATH_PARAM_BATCHMODE = 315, 1185 OL_ATH_PARAM_PACK_AGGR_DELAY = 316, 1186 #if UMAC_SUPPORT_ACFG 1187 OL_ATH_PARAM_DIAG_ENABLE = 317, 1188 #endif 1189 #if ATH_SUPPORT_VAP_QOS 1190 OL_ATH_PARAM_VAP_QOS = 318, 1191 #endif 1192 OL_ATH_PARAM_CHAN_STATS_TH = 319, 1193 /* Passive scan is enabled or disabled */ 1194 OL_ATH_PARAM_PASSIVE_SCAN_ENABLE = 320, 1195 OL_ATH_MIN_RSSI_ENABLE = 321, 1196 OL_ATH_MIN_RSSI = 322, 1197 OL_ATH_PARAM_ACS_2G_ALLCHAN = 323, 1198 #if DBDC_REPEATER_SUPPORT 1199 OL_ATH_PARAM_DELAY_STAVAP_UP = 324, 1200 #endif 1201 /* It is used to set the channel switch options */ 1202 OL_ATH_PARAM_CHANSWITCH_OPTIONS = 327, 1203 OL_ATH_BTCOEX_ENABLE = 328, 1204 OL_ATH_BTCOEX_WL_PRIORITY = 329, 1205 OL_ATH_PARAM_TID_OVERRIDE_QUEUE_MAPPING = 330, 1206 OL_ATH_PARAM_CAL_VER_CHECK = 331, 1207 OL_ATH_PARAM_NO_VLAN = 332, 1208 OL_ATH_PARAM_CCA_THRESHOLD = 333, 1209 OL_ATH_PARAM_ATF_LOGGING = 334, 1210 OL_ATH_PARAM_STRICT_DOTH = 335, 1211 OL_ATH_PARAM_DISCONNECTION_TIMEOUT = 336, 1212 OL_ATH_PARAM_RECONFIGURATION_TIMEOUT = 337, 1213 OL_ATH_PARAM_CHANNEL_SWITCH_COUNT = 338, 1214 OL_ATH_PARAM_ALWAYS_PRIMARY = 339, 1215 OL_ATH_PARAM_FAST_LANE = 340, 1216 OL_ATH_GET_BTCOEX_DUTY_CYCLE = 341, 1217 OL_ATH_PARAM_SECONDARY_OFFSET_IE = 342, 1218 OL_ATH_PARAM_WIDE_BAND_SUB_ELEMENT = 343, 1219 OL_ATH_PARAM_PREFERRED_UPLINK = 344, 1220 OL_ATH_PARAM_PRECAC_ENABLE = 345, 1221 OL_ATH_PARAM_PRECAC_TIMEOUT = 346, 1222 OL_ATH_COEX_VER_CFG = 347, 1223 OL_ATH_PARAM_DUMP_TARGET = 348, 1224 OL_ATH_PARAM_PDEV_TO_REO_DEST = 349, 1225 OL_ATH_PARAM_DUMP_CHAINMASK_TABLES = 350, 1226 OL_ATH_PARAM_DUMP_OBJECTS = 351, 1227 OL_ATH_PARAM_ACS_SRLOADVAR = 352, 1228 OL_ATH_PARAM_MGMT_RSSI_THRESHOLD = 353, 1229 OL_ATH_PARAM_EXT_NSS_CAPABLE = 354, 1230 OL_ATH_PARAM_MGMT_PDEV_STATS_TIMER = 355, 1231 OL_ATH_PARAM_TXACKTIMEOUT = 356, 1232 OL_ATH_PARAM_ICM_ACTIVE = 357, 1233 OL_ATH_PARAM_NOMINAL_NOISEFLOOR = 358, 1234 OL_ATH_PARAM_CHAN_INFO = 359, 1235 OL_ATH_PARAM_ACS_RANK = 360, 1236 OL_ATH_PARAM_TXCHAINSOFT = 361, 1237 OL_ATH_PARAM_WIDE_BAND_SCAN = 362, 1238 OL_ATH_PARAM_CCK_TX_ENABLE = 363, 1239 OL_ATH_PARAM_PAPI_ENABLE = 364, 1240 OL_ATH_PARAM_ISOLATION = 365, 1241 OL_ATH_PARAM_MAX_CLIENTS_PER_RADIO = 366, 1242 }; 1243 1244 /* Enumeration of PDEV Configuration parameter */ 1245 enum _ol_hal_param_t { 1246 OL_HAL_CONFIG_DMA_BEACON_RESPONSE_TIME = 0 1247 }; 1248 #endif 1249 1250 /* Bitmasks for stats that can block */ 1251 #define EXT_TXRX_FW_STATS 0x0001 1252 #endif 1253