1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 /** 28 * @file cdp_txrx_stats_struct.h 29 * @brief Define the host data path stats API functions 30 * called by the host control SW and the OS interface module 31 */ 32 #ifndef _CDP_TXRX_STATS_STRUCT_H_ 33 #define _CDP_TXRX_STATS_STRUCT_H_ 34 #ifndef CONFIG_WIN 35 #include <wlan_defs.h> 36 #endif 37 38 #define TXRX_STATS_LEVEL_OFF 0 39 #define TXRX_STATS_LEVEL_BASIC 1 40 #define TXRX_STATS_LEVEL_FULL 2 41 42 #define BSS_CHAN_INFO_READ 1 43 #define BSS_CHAN_INFO_READ_AND_CLEAR 2 44 45 #define TX_FRAME_TYPE_DATA 0 46 #define TX_FRAME_TYPE_MGMT 1 47 #define TX_FRAME_TYPE_BEACON 2 48 49 #ifndef TXRX_STATS_LEVEL 50 #define TXRX_STATS_LEVEL TXRX_STATS_LEVEL_BASIC 51 #endif 52 53 /* 1 additional MCS is for invalid values */ 54 #define MAX_MCS (12 + 1) 55 #define MAX_MCS_11A 8 56 #define MAX_MCS_11B 7 57 #define MAX_MCS_11AC 12 58 /* 1 additional GI is for invalid values */ 59 #define MAX_GI (4 + 1) 60 #define SS_COUNT 8 61 #define MAX_BW 7 62 #define MAX_RECEPTION_TYPES 4 63 64 /* WME stream classes */ 65 #define WME_AC_BE 0 /* best effort */ 66 #define WME_AC_BK 1 /* background */ 67 #define WME_AC_VI 2 /* video */ 68 #define WME_AC_VO 3 /* voice */ 69 #define WME_AC_MAX 4 /* MAX AC Value */ 70 71 #define CDP_MAX_RX_RINGS 4 72 73 /* 74 * Number of TLVs sent by FW. Needs to reflect 75 * HTT_PPDU_STATS_MAX_TAG declared in FW 76 */ 77 #define CDP_PPDU_STATS_MAX_TAG 14 78 79 /* Different Packet Types */ 80 enum cdp_packet_type { 81 DOT11_A = 0, 82 DOT11_B = 1, 83 DOT11_N = 2, 84 DOT11_AC = 3, 85 DOT11_AX = 4, 86 DOT11_MAX = 5, 87 }; 88 89 /* packet info */ 90 struct cdp_pkt_info { 91 /*no of packets*/ 92 uint32_t num; 93 /* total no of bytes */ 94 uint64_t bytes; 95 }; 96 97 /* Tx Stats */ 98 struct cdp_tx_stats { 99 /* Pkt Info for which completions were received */ 100 struct cdp_pkt_info comp_pkt; 101 /* Unicast Packet Count */ 102 struct cdp_pkt_info ucast; 103 /* Multicast Packet Count */ 104 struct cdp_pkt_info mcast; 105 /* Broadcast Packet Count*/ 106 struct cdp_pkt_info bcast; 107 /*NAWDS Multicast Packet Count */ 108 struct cdp_pkt_info nawds_mcast; 109 /*NAWDS Multicast Drop Count */ 110 uint32_t nawds_mcast_drop; 111 /* Successful Tx Packets */ 112 struct cdp_pkt_info tx_success; 113 /* Total Tx failure */ 114 uint32_t tx_failed; 115 /* Total Packets as ofdma*/ 116 uint32_t ofdma; 117 /* Packets in STBC */ 118 uint32_t stbc; 119 /* Packets in LDPC */ 120 uint32_t ldpc; 121 /* Packet retries */ 122 uint32_t retries; 123 /* Number of MSDUs with no MSDU level aggregation */ 124 uint32_t non_amsdu_cnt; 125 /* Number of MSDUs part of AMSDU*/ 126 uint32_t amsdu_cnt; 127 /* Tx Rate */ 128 uint32_t tx_rate; 129 130 /* RSSI of last packet */ 131 uint32_t last_ack_rssi; 132 133 /* Packet Type */ 134 struct { 135 /* MCS Count */ 136 uint32_t mcs_count[MAX_MCS]; 137 } pkt_type[DOT11_MAX]; 138 139 /* SGI count */ 140 uint32_t sgi_count[MAX_GI]; 141 142 /* Packet count for different num_spatial_stream values */ 143 uint32_t nss[SS_COUNT]; 144 145 /* Packet Count for different bandwidths */ 146 uint32_t bw[MAX_BW]; 147 148 /* Wireless Multimedia type Count */ 149 uint32_t wme_ac_type[WME_AC_MAX]; 150 151 /* Wireless Multimedia type Count */ 152 uint32_t excess_retries_per_ac[WME_AC_MAX]; 153 154 /* Packets dropped on the Tx side */ 155 struct { 156 /* Discarded by firmware */ 157 uint32_t fw_rem; 158 /* firmware_discard_untransmitted */ 159 uint32_t fw_rem_notx; 160 /* firmware_discard_transmitted */ 161 uint32_t fw_rem_tx; 162 /* aged out in mpdu/msdu queues*/ 163 uint32_t age_out; 164 /* discarded by firmware reason 1 */ 165 uint32_t fw_reason1; 166 /* discarded by firmware reason 2 */ 167 uint32_t fw_reason2; 168 /* discarded by firmware reason 3 */ 169 uint32_t fw_reason3; 170 } dropped; 171 }; 172 173 /* Rx Level Stats */ 174 struct cdp_rx_stats { 175 /* Total packets sent up the stack */ 176 struct cdp_pkt_info to_stack; 177 /* Packets received on the reo ring */ 178 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 179 /* Total unicast packets */ 180 struct cdp_pkt_info unicast; 181 /* Total multicast packets */ 182 struct cdp_pkt_info multicast; 183 /* Broadcast Packet Count*/ 184 struct cdp_pkt_info bcast; 185 /* Raw Pakets received */ 186 struct cdp_pkt_info raw; 187 /* Total multicast packets */ 188 struct cdp_pkt_info nawds_mcast_drop; 189 190 struct { 191 /* Intra BSS packets received */ 192 struct cdp_pkt_info pkts; 193 struct cdp_pkt_info fail; 194 } intra_bss; 195 196 /* Errors */ 197 struct { 198 /* Rx MIC errors */ 199 uint32_t mic_err; 200 /* Rx Decryption Errors */ 201 uint32_t decrypt_err; 202 } err; 203 204 /* Wireless Multimedia type Count */ 205 uint32_t wme_ac_type[WME_AC_MAX]; 206 /* Reception type os packets */ 207 uint32_t reception_type[MAX_RECEPTION_TYPES]; 208 /* Packet Type */ 209 struct { 210 /* MCS Count */ 211 uint32_t mcs_count[MAX_MCS]; 212 } pkt_type[DOT11_MAX]; 213 /* SGI count */ 214 uint32_t sgi_count[MAX_GI]; 215 /* Packet count in spatiel Streams */ 216 uint32_t nss[SS_COUNT]; 217 /* Packet Count in different bandwidths */ 218 uint32_t bw[MAX_BW]; 219 /* Number of MSDUs with no MPDU level aggregation */ 220 uint32_t non_ampdu_cnt; 221 /* Number of MSDUs part of AMSPU */ 222 uint32_t ampdu_cnt; 223 /* Number of MSDUs with no MSDU level aggregation */ 224 uint32_t non_amsdu_cnt; 225 /* Number of MSDUs part of AMSDU*/ 226 uint32_t amsdu_cnt; 227 /* Number of bar received */ 228 uint32_t bar_recv_cnt; 229 /* RSSI of received signal */ 230 uint32_t rssi; 231 /*Rx rate */ 232 uint32_t rx_rate; 233 }; 234 235 /* Tx ingress Stats */ 236 struct cdp_tx_ingress_stats { 237 /* Total packets received for transmission */ 238 struct cdp_pkt_info rcvd; 239 /* Tx packets processed*/ 240 struct cdp_pkt_info processed; 241 /* Total packets passed Reinject handler */ 242 struct cdp_pkt_info reinject_pkts; 243 /* Total packets passed to inspect handler */ 244 struct cdp_pkt_info inspect_pkts; 245 /*NAWDS Multicast Packet Count */ 246 struct cdp_pkt_info nawds_mcast; 247 /* Number of broadcast packets */ 248 struct cdp_pkt_info bcast; 249 250 struct { 251 /* Total Raw packets */ 252 struct cdp_pkt_info raw_pkt; 253 /* DMA map error */ 254 uint32_t dma_map_error; 255 } raw; 256 257 /* TSO packets info */ 258 struct { 259 /* No of segments in TSO packets */ 260 uint32_t num_seg; 261 /* total no of TSO packets */ 262 struct cdp_pkt_info tso_pkt; 263 /* TSO packets dropped by host */ 264 uint32_t dropped_host; 265 /* TSO packets dropped by target */ 266 uint32_t dropped_target; 267 } tso; 268 269 /* Scatter Gather packet info */ 270 struct { 271 /* Total scatter gather packets */ 272 struct cdp_pkt_info sg_pkt; 273 /* SG packets dropped by host */ 274 uint32_t dropped_host; 275 /* SG packets dropped by target */ 276 uint32_t dropped_target; 277 /* Dma map error */ 278 uint32_t dma_map_error; 279 } sg; 280 281 /* Multicast Enhancement packets info */ 282 struct { 283 /* total no of multicast conversion packets */ 284 struct cdp_pkt_info mcast_pkt; 285 /* packets dropped due to map error */ 286 uint32_t dropped_map_error; 287 /* packets dropped due to self Mac address */ 288 uint32_t dropped_self_mac; 289 /* Packets dropped due to send fail */ 290 uint32_t dropped_send_fail; 291 /* total unicast packets transmitted */ 292 uint32_t ucast; 293 /* Segment allocation failure */ 294 uint32_t fail_seg_alloc; 295 /* NBUF clone failure */ 296 uint32_t clone_fail; 297 } mcast_en; 298 299 /* Packets dropped on the Tx side */ 300 struct { 301 /* Total scatter gather packets */ 302 struct cdp_pkt_info dropped_pkt; 303 /* Desc Not Available */ 304 uint32_t desc_na; 305 /* Ring Full */ 306 uint32_t ring_full; 307 /* Hwenqueue failed */ 308 uint32_t enqueue_fail; 309 /* DMA failed */ 310 uint32_t dma_error; 311 /* Resource Full: Congestion Control */ 312 uint32_t res_full; 313 } dropped; 314 315 /* Mesh packets info */ 316 struct { 317 /* packets sent to fw */ 318 uint32_t exception_fw; 319 /* packets completions received from fw */ 320 uint32_t completion_fw; 321 } mesh; 322 323 /*Number of packets classified by CCE*/ 324 uint32_t cce_classified; 325 326 /*Number of raw packets classified by CCE*/ 327 uint32_t cce_classified_raw; 328 }; 329 330 struct cdp_vdev_stats { 331 /* Tx ingress stats */ 332 struct cdp_tx_ingress_stats tx_i; 333 /* CDP Tx Stats */ 334 struct cdp_tx_stats tx; 335 /* CDP Rx Stats */ 336 struct cdp_rx_stats rx; 337 }; 338 339 struct cdp_peer_stats { 340 /* CDP Tx Stats */ 341 struct cdp_tx_stats tx; 342 /* CDP Rx Stats */ 343 struct cdp_rx_stats rx; 344 }; 345 346 /* Tx completions per interrupt */ 347 struct cdp_hist_tx_comp { 348 uint32_t pkts_1; 349 uint32_t pkts_2_20; 350 uint32_t pkts_21_40; 351 uint32_t pkts_41_60; 352 uint32_t pkts_61_80; 353 uint32_t pkts_81_100; 354 uint32_t pkts_101_200; 355 uint32_t pkts_201_plus; 356 }; 357 358 /* Rx ring descriptors reaped per interrupt */ 359 struct cdp_hist_rx_ind { 360 uint32_t pkts_1; 361 uint32_t pkts_2_20; 362 uint32_t pkts_21_40; 363 uint32_t pkts_41_60; 364 uint32_t pkts_61_80; 365 uint32_t pkts_81_100; 366 uint32_t pkts_101_200; 367 uint32_t pkts_201_plus; 368 }; 369 370 struct cdp_htt_tlv_hdr { 371 /* BIT [11 : 0] :- tag 372 * BIT [23 : 12] :- length 373 * BIT [31 : 24] :- reserved 374 */ 375 uint32_t tag__length; 376 }; 377 378 #define HTT_STATS_SUBTYPE_MAX 16 379 380 struct cdp_htt_rx_pdev_fw_stats_tlv { 381 struct cdp_htt_tlv_hdr tlv_hdr; 382 383 /* BIT [ 7 : 0] :- mac_id 384 * BIT [31 : 8] :- reserved 385 */ 386 uint32_t mac_id__word; 387 /* Num PPDU status processed from HW */ 388 uint32_t ppdu_recvd; 389 /* Num MPDU across PPDUs with FCS ok */ 390 uint32_t mpdu_cnt_fcs_ok; 391 /* Num MPDU across PPDUs with FCS err */ 392 uint32_t mpdu_cnt_fcs_err; 393 /* Num MSDU across PPDUs */ 394 uint32_t tcp_msdu_cnt; 395 /* Num MSDU across PPDUs */ 396 uint32_t tcp_ack_msdu_cnt; 397 /* Num MSDU across PPDUs */ 398 uint32_t udp_msdu_cnt; 399 /* Num MSDU across PPDUs */ 400 uint32_t other_msdu_cnt; 401 /* Num MPDU on FW ring indicated */ 402 uint32_t fw_ring_mpdu_ind; 403 /* Num MGMT MPDU given to protocol */ 404 uint32_t fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 405 /* Num ctrl MPDU given to protocol */ 406 uint32_t fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 407 /* Num mcast data packet received */ 408 uint32_t fw_ring_mcast_data_msdu; 409 /* Num broadcast data packet received */ 410 uint32_t fw_ring_bcast_data_msdu; 411 /* Num unicat data packet received */ 412 uint32_t fw_ring_ucast_data_msdu; 413 /* Num null data packet received */ 414 uint32_t fw_ring_null_data_msdu; 415 /* Num MPDU on FW ring dropped */ 416 uint32_t fw_ring_mpdu_drop; 417 418 /* Num buf indication to offload */ 419 uint32_t ofld_local_data_ind_cnt; 420 /* Num buf recycle from offload */ 421 uint32_t ofld_local_data_buf_recycle_cnt; 422 /* Num buf indication to data_rx */ 423 uint32_t drx_local_data_ind_cnt; 424 /* Num buf recycle from data_rx */ 425 uint32_t drx_local_data_buf_recycle_cnt; 426 /* Num buf indication to protocol */ 427 uint32_t local_nondata_ind_cnt; 428 /* Num buf recycle from protocol */ 429 uint32_t local_nondata_buf_recycle_cnt; 430 431 /* Num buf fed */ 432 uint32_t fw_status_buf_ring_refill_cnt; 433 /* Num ring empty encountered */ 434 uint32_t fw_status_buf_ring_empty_cnt; 435 /* Num buf fed */ 436 uint32_t fw_pkt_buf_ring_refill_cnt; 437 /* Num ring empty encountered */ 438 uint32_t fw_pkt_buf_ring_empty_cnt; 439 /* Num buf fed */ 440 uint32_t fw_link_buf_ring_refill_cnt; 441 /* Num ring empty encountered */ 442 uint32_t fw_link_buf_ring_empty_cnt; 443 444 /* Num buf fed */ 445 uint32_t host_pkt_buf_ring_refill_cnt; 446 /* Num ring empty encountered */ 447 uint32_t host_pkt_buf_ring_empty_cnt; 448 /* Num buf fed */ 449 uint32_t mon_pkt_buf_ring_refill_cnt; 450 /* Num ring empty encountered */ 451 uint32_t mon_pkt_buf_ring_empty_cnt; 452 /* Num buf fed */ 453 uint32_t mon_status_buf_ring_refill_cnt; 454 /* Num ring empty encountered */ 455 uint32_t mon_status_buf_ring_empty_cnt; 456 /* Num buf fed */ 457 uint32_t mon_desc_buf_ring_refill_cnt; 458 /* Num ring empty encountered */ 459 uint32_t mon_desc_buf_ring_empty_cnt; 460 /* Num buf fed */ 461 uint32_t mon_dest_ring_update_cnt; 462 /* Num ring full encountered */ 463 uint32_t mon_dest_ring_full_cnt; 464 465 /* Num rx suspend is attempted */ 466 uint32_t rx_suspend_cnt; 467 /* Num rx suspend failed */ 468 uint32_t rx_suspend_fail_cnt; 469 /* Num rx resume attempted */ 470 uint32_t rx_resume_cnt; 471 /* Num rx resume failed */ 472 uint32_t rx_resume_fail_cnt; 473 /* Num rx ring switch */ 474 uint32_t rx_ring_switch_cnt; 475 /* Num rx ring restore */ 476 uint32_t rx_ring_restore_cnt; 477 /* Num rx flush issued */ 478 uint32_t rx_flush_cnt; 479 }; 480 481 /* == TX PDEV STATS == */ 482 struct cdp_htt_tx_pdev_stats_cmn_tlv { 483 struct cdp_htt_tlv_hdr tlv_hdr; 484 485 /* BIT [ 7 : 0] :- mac_id 486 * BIT [31 : 8] :- reserved 487 */ 488 uint32_t mac_id__word; 489 /* Num queued to HW */ 490 uint32_t hw_queued; 491 /* Num PPDU reaped from HW */ 492 uint32_t hw_reaped; 493 /* Num underruns */ 494 uint32_t underrun; 495 /* Num HW Paused counter. */ 496 uint32_t hw_paused; 497 /* Num HW flush counter. */ 498 uint32_t hw_flush; 499 /* Num HW filtered counter. */ 500 uint32_t hw_filt; 501 /* Num PPDUs cleaned up in TX abort */ 502 uint32_t tx_abort; 503 /* Num MPDUs requed by SW */ 504 uint32_t mpdu_requed; 505 /* excessive retries */ 506 uint32_t tx_xretry; 507 /* Last used data hw rate code */ 508 uint32_t data_rc; 509 /* frames dropped due to excessive sw retries */ 510 uint32_t mpdu_dropped_xretry; 511 /* illegal rate phy errors */ 512 uint32_t illgl_rate_phy_err; 513 /* wal pdev continous xretry */ 514 uint32_t cont_xretry; 515 /* wal pdev continous xretry */ 516 uint32_t tx_timeout; 517 /* wal pdev resets */ 518 uint32_t pdev_resets; 519 /* PhY/BB underrun */ 520 uint32_t phy_underrun; 521 /* MPDU is more than txop limit */ 522 uint32_t txop_ovf; 523 /* Number of Sequences posted */ 524 uint32_t seq_posted; 525 /* Number of Sequences failed queueing */ 526 uint32_t seq_failed_queueing; 527 /* Number of Sequences completed */ 528 uint32_t seq_completed; 529 /* Number of Sequences restarted */ 530 uint32_t seq_restarted; 531 /* Number of MU Sequences posted */ 532 uint32_t mu_seq_posted; 533 /* Number of time HW ring is paused between seq switch within ISR */ 534 uint32_t seq_switch_hw_paused; 535 /* Number of times seq continuation in DSR */ 536 uint32_t next_seq_posted_dsr; 537 /* Number of times seq continuation in ISR */ 538 uint32_t seq_posted_isr; 539 /* Number of seq_ctrl cached. */ 540 uint32_t seq_ctrl_cached; 541 /* Number of MPDUs successfully transmitted */ 542 uint32_t mpdu_count_tqm; 543 /* Number of MSDUs successfully transmitted */ 544 uint32_t msdu_count_tqm; 545 /* Number of MPDUs dropped */ 546 uint32_t mpdu_removed_tqm; 547 /* Number of MSDUs dropped */ 548 uint32_t msdu_removed_tqm; 549 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 550 uint32_t mpdus_sw_flush; 551 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 552 uint32_t mpdus_hw_filter; 553 /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ 554 uint32_t mpdus_truncated; 555 /* Num MPDUs that was tried but didn't receive ACK or BA */ 556 uint32_t mpdus_ack_failed; 557 /* Num MPDUs that was dropped due to expiry (MSDU TTL). */ 558 uint32_t mpdus_expired; 559 /* Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ 560 uint32_t mpdus_seq_hw_retry; 561 /* Num of TQM acked cmds processed */ 562 uint32_t ack_tlv_proc; 563 /* coex_abort_mpdu_cnt valid. */ 564 uint32_t coex_abort_mpdu_cnt_valid; 565 /* coex_abort_mpdu_cnt from TX FES stats. */ 566 uint32_t coex_abort_mpdu_cnt; 567 /* Number of total PPDUs(DATA, MGMT, excludes selfgen) tried over the air (OTA) */ 568 uint32_t num_total_ppdus_tried_ota; 569 /* Number of data PPDUs tried over the air (OTA) */ 570 uint32_t num_data_ppdus_tried_ota; 571 /* Num Local control/mgmt frames (MSDUs) queued */ 572 uint32_t local_ctrl_mgmt_enqued; 573 /* local_ctrl_mgmt_freed: 574 * Num Local control/mgmt frames (MSDUs) done 575 * It includes all local ctrl/mgmt completions 576 * (acked, no ack, flush, TTL, etc) 577 */ 578 uint32_t local_ctrl_mgmt_freed; 579 /* Num Local data frames (MSDUs) queued */ 580 uint32_t local_data_enqued; 581 /* local_data_freed: 582 * Num Local data frames (MSDUs) done 583 * It includes all local data completions 584 * (acked, no ack, flush, TTL, etc) 585 */ 586 uint32_t local_data_freed; 587 }; 588 589 struct cdp_htt_tx_pdev_stats_urrn_tlv_v { 590 struct cdp_htt_tlv_hdr tlv_hdr; 591 uint32_t urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */ 592 }; 593 594 /* NOTE: Variable length TLV, use length spec to infer array size */ 595 struct cdp_htt_tx_pdev_stats_flush_tlv_v { 596 struct cdp_htt_tlv_hdr tlv_hdr; 597 uint32_t flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 598 }; 599 600 /* NOTE: Variable length TLV, use length spec to infer array size */ 601 struct cdp_htt_tx_pdev_stats_sifs_tlv_v { 602 struct cdp_htt_tlv_hdr tlv_hdr; 603 uint32_t sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 604 }; 605 606 /* NOTE: Variable length TLV, use length spec to infer array size */ 607 struct cdp_htt_tx_pdev_stats_phy_err_tlv_v { 608 struct cdp_htt_tlv_hdr tlv_hdr; 609 uint32_t phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 610 }; 611 612 /* == RX PDEV/SOC STATS == */ 613 /* HTT_STATS_RX_SOC_FW_STATS_TAG */ 614 struct cdp_htt_rx_soc_fw_stats_tlv { 615 struct cdp_htt_tlv_hdr tlv_hdr; 616 /* Num Packets received on REO FW ring */ 617 uint32_t fw_reo_ring_data_msdu; 618 /* Num bc/mc packets indicated from fw to host */ 619 uint32_t fw_to_host_data_msdu_bcmc; 620 /* Num unicast packets indicated from fw to host */ 621 uint32_t fw_to_host_data_msdu_uc; 622 /* Num remote buf recycle from offload */ 623 uint32_t ofld_remote_data_buf_recycle_cnt; 624 /* Num remote free buf given to offload */ 625 uint32_t ofld_remote_free_buf_indication_cnt; 626 }; 627 628 struct cdp_htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 629 struct cdp_htt_tlv_hdr tlv_hdr; 630 /* Num total buf refilled from refill ring */ 631 uint32_t refill_ring_num_refill[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 632 }; 633 634 struct cdp_htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 635 struct cdp_htt_tlv_hdr tlv_hdr; 636 /* Num error MPDU for each RxDMA error type */ 637 uint32_t fw_ring_mpdu_err[1]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ 638 }; 639 640 struct cdp_htt_rx_pdev_fw_mpdu_drop_tlv_v { 641 struct cdp_htt_tlv_hdr tlv_hdr; 642 /* Num MPDU dropped */ 643 uint32_t fw_mpdu_drop[1]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 644 }; 645 646 #define HTT_STATS_PHY_ERR_MAX 43 647 648 struct cdp_htt_rx_pdev_fw_stats_phy_err_tlv { 649 struct cdp_htt_tlv_hdr tlv_hdr; 650 651 /* BIT [ 7 : 0] :- mac_id 652 * BIT [31 : 8] :- reserved 653 */ 654 uint32_t mac_id__word; 655 /* Num of phy err */ 656 uint32_t total_phy_err_cnt; 657 /* Counts of different types of phy errs 658 * The mapping of PHY error types to phy_err array elements is HW dependent. 659 * The only currently-supported mapping is shown below: 660 * 661 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 662 * 1 phyrx_err_synth_off 663 * 2 phyrx_err_ofdma_timing 664 * 3 phyrx_err_ofdma_signal_parity 665 * 4 phyrx_err_ofdma_rate_illegal 666 * 5 phyrx_err_ofdma_length_illegal 667 * 6 phyrx_err_ofdma_restart 668 * 7 phyrx_err_ofdma_service 669 * 8 phyrx_err_ppdu_ofdma_power_drop 670 * 9 phyrx_err_cck_blokker 671 * 10 phyrx_err_cck_timing 672 * 11 phyrx_err_cck_header_crc 673 * 12 phyrx_err_cck_rate_illegal 674 * 13 phyrx_err_cck_length_illegal 675 * 14 phyrx_err_cck_restart 676 * 15 phyrx_err_cck_service 677 * 16 phyrx_err_cck_power_drop 678 * 17 phyrx_err_ht_crc_err 679 * 18 phyrx_err_ht_length_illegal 680 * 19 phyrx_err_ht_rate_illegal 681 * 20 phyrx_err_ht_zlf 682 * 21 phyrx_err_false_radar_ext 683 * 22 phyrx_err_green_field 684 * 23 phyrx_err_bw_gt_dyn_bw 685 * 24 phyrx_err_leg_ht_mismatch 686 * 25 phyrx_err_vht_crc_error 687 * 26 phyrx_err_vht_siga_unsupported 688 * 27 phyrx_err_vht_lsig_len_invalid 689 * 28 phyrx_err_vht_ndp_or_zlf 690 * 29 phyrx_err_vht_nsym_lt_zero 691 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 692 * 31 phyrx_err_vht_rx_skip_group_id0 693 * 32 phyrx_err_vht_rx_skip_group_id1to62 694 * 33 phyrx_err_vht_rx_skip_group_id63 695 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 696 * 35 phyrx_err_defer_nap 697 * 36 phyrx_err_fdomain_timeout 698 * 37 phyrx_err_lsig_rel_check 699 * 38 phyrx_err_bt_collision 700 * 39 phyrx_err_unsupported_mu_feedback 701 * 40 phyrx_err_ppdu_tx_interrupt_rx 702 * 41 phyrx_err_unsupported_cbf 703 * 42 phyrx_err_other 704 */ 705 uint32_t phy_err[HTT_STATS_PHY_ERR_MAX]; 706 }; 707 708 struct cdp_htt_rx_soc_fw_refill_ring_empty_tlv_v { 709 struct cdp_htt_tlv_hdr tlv_hdr; 710 /* Num ring empty encountered */ 711 uint32_t refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 712 }; 713 714 struct cdp_htt_tx_pdev_stats { 715 struct cdp_htt_tx_pdev_stats_cmn_tlv cmn_tlv; 716 struct cdp_htt_tx_pdev_stats_urrn_tlv_v underrun_tlv; 717 struct cdp_htt_tx_pdev_stats_sifs_tlv_v sifs_tlv; 718 struct cdp_htt_tx_pdev_stats_flush_tlv_v flush_tlv; 719 struct cdp_htt_tx_pdev_stats_phy_err_tlv_v phy_err_tlv; 720 }; 721 722 struct cdp_htt_rx_soc_stats_t { 723 struct cdp_htt_rx_soc_fw_stats_tlv fw_tlv; 724 struct cdp_htt_rx_soc_fw_refill_ring_empty_tlv_v fw_refill_ring_empty_tlv; 725 struct cdp_htt_rx_soc_fw_refill_ring_num_refill_tlv_v fw_refill_ring_num_refill_tlv; 726 }; 727 728 struct cdp_htt_rx_pdev_stats { 729 struct cdp_htt_rx_soc_stats_t soc_stats; 730 struct cdp_htt_rx_pdev_fw_stats_tlv fw_stats_tlv; 731 struct cdp_htt_rx_pdev_fw_ring_mpdu_err_tlv_v fw_ring_mpdu_err_tlv; 732 struct cdp_htt_rx_pdev_fw_mpdu_drop_tlv_v fw_ring_mpdu_drop; 733 struct cdp_htt_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; 734 }; 735 736 struct cdp_pdev_stats { 737 /* packets dropped on rx */ 738 struct { 739 /* packets dropped because nsdu_done bit not set */ 740 uint32_t msdu_not_done; 741 /* Multicast Echo check */ 742 uint32_t mec; 743 /* Mesh Filtered packets */ 744 uint32_t mesh_filter; 745 /* packets dropped on monitor vap */ 746 uint32_t mon_rx_drop; 747 } dropped; 748 749 struct { 750 /* total packets replnished */ 751 struct cdp_pkt_info pkts; 752 /* rxdma errors */ 753 uint32_t rxdma_err; 754 /* nbuf alloc failed */ 755 uint32_t nbuf_alloc_fail; 756 /* Mapping failure */ 757 uint32_t map_err; 758 /* x86 failures */ 759 uint32_t x86_fail; 760 /* low threshold interrupts */ 761 uint32_t low_thresh_intrs; 762 } replenish; 763 764 /* Rx Raw Packets */ 765 uint32_t rx_raw_pkts; 766 /* Mesh Rx Stats Alloc fail */ 767 uint32_t mesh_mem_alloc; 768 769 /* Rx errors */ 770 struct { 771 /* desc alloc failed errors */ 772 uint32_t desc_alloc_fail; 773 } err; 774 775 /* buffers added back in freelist */ 776 uint32_t buf_freelist; 777 /* Tx Ingress stats */ 778 struct cdp_tx_ingress_stats tx_i; 779 /* CDP Tx Stats */ 780 struct cdp_tx_stats tx; 781 /* CDP Rx Stats */ 782 struct cdp_rx_stats rx; 783 /* Number of Tx completions per interrupt */ 784 struct cdp_hist_tx_comp tx_comp_histogram; 785 /* Number of Rx ring descriptors reaped per interrupt */ 786 struct cdp_hist_rx_ind rx_ind_histogram; 787 uint64_t ppdu_stats_counter[CDP_PPDU_STATS_MAX_TAG]; 788 789 struct cdp_htt_tx_pdev_stats htt_tx_pdev_stats; 790 struct cdp_htt_rx_pdev_stats htt_rx_pdev_stats; 791 }; 792 793 #ifndef BIG_ENDIAN_HOST 794 typedef struct { 795 uint64_t pkts; 796 uint64_t bytes; 797 } ol_txrx_stats_elem; 798 #else 799 struct ol_txrx_elem_t { 800 uint64_t pkts; 801 uint64_t bytes; 802 }; 803 typedef struct ol_txrx_elem_t ol_txrx_stats_elem; 804 #endif 805 806 #ifndef CONFIG_MCL 807 /** 808 * @brief data stats published by the host txrx layer 809 */ 810 struct ol_txrx_stats { 811 struct { 812 /* MSDUs received from the stack */ 813 ol_txrx_stats_elem from_stack; 814 /* MSDUs successfully sent across the WLAN */ 815 ol_txrx_stats_elem delivered; 816 struct { 817 /* MSDUs that the host did not accept */ 818 ol_txrx_stats_elem host_reject; 819 /* MSDUs which could not be downloaded to the target */ 820 ol_txrx_stats_elem download_fail; 821 /* 822 * MSDUs which the target discarded 823 * (lack of mem or old age) 824 */ 825 ol_txrx_stats_elem target_discard; 826 /* 827 * MSDUs which the target sent but couldn't get 828 * an ack for 829 */ 830 ol_txrx_stats_elem no_ack; 831 /* MSDUs dropped in NSS-FW */ 832 ol_txrx_stats_elem nss_ol_dropped; 833 } dropped; 834 u_int32_t desc_in_use; 835 u_int32_t desc_alloc_fails; 836 u_int32_t ce_ring_full; 837 u_int32_t dma_map_error; 838 /* MSDUs given to the txrx layer by the management stack */ 839 ol_txrx_stats_elem mgmt; 840 struct { 841 /* TSO applied jumbo packets received from NW Stack */ 842 ol_txrx_stats_elem tso_pkts; 843 /* Non - TSO packets */ 844 ol_txrx_stats_elem non_tso_pkts; 845 /* TSO packets : Dropped during TCP segmentation*/ 846 ol_txrx_stats_elem tso_dropped; 847 /* TSO Descriptors */ 848 u_int32_t tso_desc_cnt; 849 } tso; 850 851 struct { 852 /* TSO applied jumbo packets received from NW Stack */ 853 ol_txrx_stats_elem sg_pkts; 854 /* Non - TSO packets */ 855 ol_txrx_stats_elem non_sg_pkts; 856 /* TSO packets : Dropped during TCP segmentation*/ 857 ol_txrx_stats_elem sg_dropped; 858 /* TSO Descriptors */ 859 u_int32_t sg_desc_cnt; 860 } sg; 861 struct { 862 /* packets enqueued for flow control */ 863 u_int32_t fl_ctrl_enqueue; 864 /* packets discarded for flow control is full */ 865 u_int32_t fl_ctrl_discard; 866 /* packets sent to CE without flow control */ 867 u_int32_t fl_ctrl_avoid; 868 } fl_ctrl; 869 } tx; 870 struct { 871 /* MSDUs given to the OS shim */ 872 ol_txrx_stats_elem delivered; 873 /* MSDUs forwarded from the rx path to the tx path */ 874 ol_txrx_stats_elem forwarded; 875 /* MSDUs in which ipv4 chksum error detected by HW */ 876 ol_txrx_stats_elem ipv4_cksum_err; 877 /* MSDUs in which tcp chksum error detected by HW */ 878 ol_txrx_stats_elem tcp_ipv4_cksum_err; 879 /* MSDUs in which udp chksum error detected by HW */ 880 ol_txrx_stats_elem udp_ipv4_cksum_err; 881 /* MSDUs in which tcp V6 chksum error detected by HW */ 882 ol_txrx_stats_elem tcp_ipv6_cksum_err; 883 /* MSDUs in which UDP V6 chksum error detected by HW */ 884 ol_txrx_stats_elem udp_ipv6_cksum_err; 885 } rx; 886 struct { 887 /* Number of mcast received for conversion */ 888 u_int32_t num_me_rcvd; 889 /* Number of unicast sent as part of mcast conversion */ 890 u_int32_t num_me_ucast; 891 /* Number of multicast frames dropped due to dma_map failure */ 892 u_int32_t num_me_dropped_m; 893 /* 894 * Number of multicast frames dropped due to allocation 895 * failure 896 */ 897 u_int32_t num_me_dropped_a; 898 /* Number of multicast frames dropped due to internal failure */ 899 u_int32_t num_me_dropped_i; 900 /* Number of me buf currently in use */ 901 u_int32_t num_me_buf; 902 /* Number of me buf frames to self mac address */ 903 u_int32_t num_me_dropped_s; 904 /* Number of me buf in use in non pool based allocation*/ 905 u_int32_t num_me_nonpool; 906 /* Number of me buf allocated using non pool based allocation*/ 907 u_int32_t num_me_nonpool_count; 908 } mcast_enhance; 909 }; 910 911 struct ol_ath_dbg_rx_rssi { 912 uint8_t rx_rssi_pri20; 913 uint8_t rx_rssi_sec20; 914 uint8_t rx_rssi_sec40; 915 uint8_t rx_rssi_sec80; 916 }; 917 918 struct ol_ath_radiostats { 919 uint64_t tx_beacon; 920 uint32_t be_nobuf; 921 uint32_t tx_buf_count; 922 uint32_t tx_packets; 923 uint32_t rx_packets; 924 int32_t tx_mgmt; 925 uint32_t tx_num_data; 926 uint32_t rx_num_data; 927 int32_t rx_mgmt; 928 uint32_t rx_num_mgmt; 929 uint32_t rx_num_ctl; 930 uint32_t tx_rssi; 931 uint32_t tx_mcs[10]; 932 uint32_t rx_mcs[10]; 933 uint32_t rx_rssi_comb; 934 struct ol_ath_dbg_rx_rssi rx_rssi_chain0; 935 struct ol_ath_dbg_rx_rssi rx_rssi_chain1; 936 struct ol_ath_dbg_rx_rssi rx_rssi_chain2; 937 struct ol_ath_dbg_rx_rssi rx_rssi_chain3; 938 uint64_t rx_bytes; 939 uint64_t tx_bytes; 940 uint32_t tx_compaggr; 941 uint32_t rx_aggr; 942 uint32_t tx_bawadv; 943 uint32_t tx_compunaggr; 944 uint32_t rx_overrun; 945 uint32_t rx_badcrypt; 946 uint32_t rx_badmic; 947 uint32_t rx_crcerr; 948 uint32_t rx_phyerr; 949 uint32_t ackRcvBad; 950 uint32_t rtsBad; 951 uint32_t rtsGood; 952 uint32_t fcsBad; 953 uint32_t noBeacons; 954 uint32_t mib_int_count; 955 uint32_t rx_looplimit_start; 956 uint32_t rx_looplimit_end; 957 uint8_t ap_stats_tx_cal_enable; 958 uint32_t tgt_asserts; 959 int16_t chan_nf; 960 uint32_t rx_last_msdu_unset_cnt; 961 int16_t chan_nf_sec80; 962 uint64_t wmi_tx_mgmt; 963 uint64_t wmi_tx_mgmt_completions; 964 uint32_t wmi_tx_mgmt_completion_err; 965 uint32_t peer_delete_req; 966 uint32_t peer_delete_resp; 967 uint32_t rx_mgmt_rssi_drop; 968 uint32_t tx_retries; 969 uint32_t rx_data_bytes; 970 uint32_t tx_frame_count; 971 uint32_t rx_frame_count; 972 uint32_t rx_clear_count; 973 uint32_t cycle_count; 974 uint32_t phy_err_count; 975 uint32_t chan_tx_pwr; 976 }; 977 978 /* 979 * Enumeration of PDEV Configuration parameter 980 */ 981 enum _ol_ath_param_t { 982 OL_ATH_PARAM_TXCHAINMASK = 1, 983 OL_ATH_PARAM_RXCHAINMASK = 2, 984 OL_ATH_PARAM_AMPDU = 6, 985 OL_ATH_PARAM_AMPDU_LIMIT = 7, 986 OL_ATH_PARAM_AMPDU_SUBFRAMES = 8, 987 OL_ATH_PARAM_TXPOWER_LIMIT2G = 12, 988 OL_ATH_PARAM_TXPOWER_LIMIT5G = 13, 989 OL_ATH_PARAM_LDPC = 32, 990 OL_ATH_PARAM_VOW_EXT_STATS = 45, 991 OL_ATH_PARAM_DYN_TX_CHAINMASK = 73, 992 OL_ATH_PARAM_BURST_ENABLE = 77, 993 OL_ATH_PARAM_BURST_DUR = 78, 994 OL_ATH_PARAM_BCN_BURST = 80, 995 OL_ATH_PARAM_DCS = 82, 996 #if UMAC_SUPPORT_PERIODIC_PERFSTATS 997 OL_ATH_PARAM_PRDPERFSTAT_THRPUT_ENAB = 83, 998 OL_ATH_PARAM_PRDPERFSTAT_THRPUT_WIN = 84, 999 OL_ATH_PARAM_PRDPERFSTAT_THRPUT = 85, 1000 OL_ATH_PARAM_PRDPERFSTAT_PER_ENAB = 86, 1001 OL_ATH_PARAM_PRDPERFSTAT_PER_WIN = 87, 1002 OL_ATH_PARAM_PRDPERFSTAT_PER = 88, 1003 #endif 1004 /* UMAC_SUPPORT_PERIODIC_PERFSTATS */ 1005 OL_ATH_PARAM_TOTAL_PER = 89, 1006 /* set manual rate for rts frame */ 1007 OL_ATH_PARAM_RTS_CTS_RATE = 92, 1008 /* co channel interference threshold level */ 1009 OL_ATH_PARAM_DCS_COCH_THR = 93, 1010 /* transmit error threshold */ 1011 OL_ATH_PARAM_DCS_TXERR_THR = 94, 1012 /* phy error threshold */ 1013 OL_ATH_PARAM_DCS_PHYERR_THR = 95, 1014 /* 1015 * The IOCTL number is 114, it is made 114, inorder to make the IOCTL 1016 * number same as Direct-attach IOCTL. 1017 * Please, don't change number. This IOCTL gets the Interface code path 1018 * it should be either DIRECT-ATTACH or OFF-LOAD. 1019 */ 1020 OL_ATH_PARAM_GET_IF_ID = 114, 1021 /* Enable Acs back Ground Channel selection Scan timer in AP mode*/ 1022 OL_ATH_PARAM_ACS_ENABLE_BK_SCANTIMEREN = 118, 1023 /* ACS scan timer value in Seconds */ 1024 OL_ATH_PARAM_ACS_SCANTIME = 119, 1025 /* Negligence Delta RSSI between two channel */ 1026 OL_ATH_PARAM_ACS_RSSIVAR = 120, 1027 /* Negligence Delta Channel load between two channel*/ 1028 OL_ATH_PARAM_ACS_CHLOADVAR = 121, 1029 /* Enable Limited OBSS check */ 1030 OL_ATH_PARAM_ACS_LIMITEDOBSS = 122, 1031 /* Acs control flag for Scan timer */ 1032 OL_ATH_PARAM_ACS_CTRLFLAG = 123, 1033 /* Acs Run time Debug level*/ 1034 OL_ATH_PARAM_ACS_DEBUGTRACE = 124, 1035 OL_ATH_PARAM_SET_FW_HANG_ID = 137, 1036 /* Radio type 1:11ac 0:11abgn */ 1037 OL_ATH_PARAM_RADIO_TYPE = 138, 1038 OL_ATH_PARAM_IGMPMLD_OVERRIDE, /* IGMP/MLD packet override */ 1039 OL_ATH_PARAM_IGMPMLD_TID, /* IGMP/MLD packet TID no */ 1040 OL_ATH_PARAM_ARPDHCP_AC_OVERRIDE, 1041 OL_ATH_PARAM_NON_AGG_SW_RETRY_TH, 1042 OL_ATH_PARAM_AGG_SW_RETRY_TH, 1043 /* Dont change this number it as per sync with DA 1044 Blocking certian channel from ic channel list */ 1045 OL_ATH_PARAM_DISABLE_DFS = 144, 1046 OL_ATH_PARAM_ENABLE_AMSDU = 145, 1047 OL_ATH_PARAM_ENABLE_AMPDU = 146, 1048 OL_ATH_PARAM_STA_KICKOUT_TH, 1049 OL_ATH_PARAM_WLAN_PROF_ENABLE, 1050 OL_ATH_PARAM_LTR_ENABLE, 1051 OL_ATH_PARAM_LTR_AC_LATENCY_BE = 150, 1052 OL_ATH_PARAM_LTR_AC_LATENCY_BK, 1053 OL_ATH_PARAM_LTR_AC_LATENCY_VI, 1054 OL_ATH_PARAM_LTR_AC_LATENCY_VO, 1055 OL_ATH_PARAM_LTR_AC_LATENCY_TIMEOUT, 1056 OL_ATH_PARAM_LTR_TX_ACTIVITY_TIMEOUT = 155, 1057 OL_ATH_PARAM_LTR_SLEEP_OVERRIDE, 1058 OL_ATH_PARAM_LTR_RX_OVERRIDE, 1059 OL_ATH_PARAM_L1SS_ENABLE, 1060 OL_ATH_PARAM_DSLEEP_ENABLE, 1061 /* radar error threshold */ 1062 OL_ATH_PARAM_DCS_RADAR_ERR_THR = 160, 1063 /* Tx channel utilization due to AP's tx and rx */ 1064 OL_ATH_PARAM_DCS_USERMAX_CU_THR, 1065 /* interference detection threshold */ 1066 OL_ATH_PARAM_DCS_INTR_DETECT_THR, 1067 /* sampling window, default 10secs */ 1068 OL_ATH_PARAM_DCS_SAMPLE_WINDOW, 1069 /* debug logs enable/disable */ 1070 OL_ATH_PARAM_DCS_DEBUG, 1071 OL_ATH_PARAM_ANI_ENABLE = 165, 1072 OL_ATH_PARAM_ANI_POLL_PERIOD, 1073 OL_ATH_PARAM_ANI_LISTEN_PERIOD, 1074 OL_ATH_PARAM_ANI_OFDM_LEVEL, 1075 OL_ATH_PARAM_ANI_CCK_LEVEL, 1076 OL_ATH_PARAM_DSCP_TID_MAP = 170, 1077 OL_ATH_PARAM_TXPOWER_SCALE, 1078 /* Phy error penalty */ 1079 OL_ATH_PARAM_DCS_PHYERR_PENALTY, 1080 #if ATH_SUPPORT_DSCP_OVERRIDE 1081 /* set/get TID for sending HMMC packets */ 1082 OL_ATH_PARAM_HMMC_DSCP_TID_MAP, 1083 /* set/get DSCP mapping override */ 1084 OL_ATH_PARAM_DSCP_OVERRIDE, 1085 /* set/get HMMC-DSCP mapping override */ 1086 OL_ATH_PARAM_HMMC_DSCP_OVERRIDE = 175, 1087 #endif 1088 #if ATH_RX_LOOPLIMIT_TIMER 1089 OL_ATH_PARAM_LOOPLIMIT_NUM, 1090 #endif 1091 OL_ATH_PARAM_ANTENNA_GAIN_2G, 1092 OL_ATH_PARAM_ANTENNA_GAIN_5G, 1093 OL_ATH_PARAM_RX_FILTER, 1094 #if ATH_SUPPORT_HYFI_ENHANCEMENTS 1095 OL_ATH_PARAM_BUFF_THRESH = 180, 1096 OL_ATH_PARAM_BLK_REPORT_FLOOD, 1097 OL_ATH_PARAM_DROP_STA_QUERY, 1098 #endif 1099 OL_ATH_PARAM_QBOOST, 1100 OL_ATH_PARAM_SIFS_FRMTYPE, 1101 OL_ATH_PARAM_SIFS_UAPSD = 185, 1102 OL_ATH_PARAM_FW_RECOVERY_ID, 1103 OL_ATH_PARAM_RESET_OL_STATS, 1104 OL_ATH_PARAM_AGGR_BURST, 1105 /* Number of deauth sent in consecutive rx_peer_invalid */ 1106 OL_ATH_PARAM_DEAUTH_COUNT, 1107 OL_ATH_PARAM_BLOCK_INTERBSS = 190, 1108 /* Firmware reset control for Bmiss / timeout / reset */ 1109 OL_ATH_PARAM_FW_DISABLE_RESET, 1110 OL_ATH_PARAM_MSDU_TTL, 1111 OL_ATH_PARAM_PPDU_DURATION, 1112 OL_ATH_PARAM_SET_TXBF_SND_PERIOD, 1113 OL_ATH_PARAM_ALLOW_PROMISC = 195, 1114 OL_ATH_PARAM_BURST_MODE, 1115 OL_ATH_PARAM_DYN_GROUPING, 1116 OL_ATH_PARAM_DPD_ENABLE, 1117 OL_ATH_PARAM_DBGLOG_RATELIM, 1118 /* firmware should intimate us about ps state change for node */ 1119 OL_ATH_PARAM_PS_STATE_CHANGE = 200, 1120 OL_ATH_PARAM_MCAST_BCAST_ECHO, 1121 /* OBSS RSSI threshold for 20/40 coexistance */ 1122 OL_ATH_PARAM_OBSS_RSSI_THRESHOLD, 1123 /* Link/node RX RSSI threshold for 20/40 coexistance */ 1124 OL_ATH_PARAM_OBSS_RX_RSSI_THRESHOLD, 1125 #if ATH_CHANNEL_BLOCKING 1126 OL_ATH_PARAM_ACS_BLOCK_MODE = 205, 1127 #endif 1128 OL_ATH_PARAM_ACS_TX_POWER_OPTION, 1129 /* 1130 * Default Antenna Polarization MSB 8 bits (24:31) specifying 1131 * enable/disable ; LSB 24 bits (0:23) antenna mask value 1132 */ 1133 OL_ATH_PARAM_ANT_POLARIZATION, 1134 /* rate limit mute type error prints */ 1135 OL_ATH_PARAM_PRINT_RATE_LIMIT, 1136 OL_ATH_PARAM_PDEV_RESET, /* Reset FW PDEV*/ 1137 /* Do not crash host when target assert happened*/ 1138 OL_ATH_PARAM_FW_DUMP_NO_HOST_CRASH = 210, 1139 /* Consider OBSS non-erp to change to long slot*/ 1140 OL_ATH_PARAM_CONSIDER_OBSS_NON_ERP_LONG_SLOT = 211, 1141 OL_ATH_PARAM_STATS_FC, 1142 OL_ATH_PARAM_QFLUSHINTERVAL, 1143 OL_ATH_PARAM_TOTAL_Q_SIZE, 1144 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE0, 1145 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE1, 1146 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE2, 1147 OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE3, 1148 OL_ATH_PARAM_MIN_THRESHOLD, 1149 OL_ATH_PARAM_MAX_Q_LIMIT, 1150 OL_ATH_PARAM_MIN_Q_LIMIT, 1151 OL_ATH_PARAM_CONG_CTRL_TIMER_INTV, 1152 OL_ATH_PARAM_STATS_TIMER_INTV, 1153 OL_ATH_PARAM_ROTTING_TIMER_INTV, 1154 OL_ATH_PARAM_LATENCY_PROFILE, 1155 OL_ATH_PARAM_HOSTQ_DUMP, 1156 OL_ATH_PARAM_TIDQ_MAP, 1157 OL_ATH_PARAM_DBG_ARP_SRC_ADDR, /* ARP DEBUG source address*/ 1158 OL_ATH_PARAM_DBG_ARP_DST_ADDR, /* ARP DEBUG destination address*/ 1159 OL_ATH_PARAM_ARP_DBG_CONF, /* ARP debug configuration */ 1160 OL_ATH_PARAM_DISABLE_STA_VAP_AMSDU, /* Disable AMSDU for station vap */ 1161 #if ATH_SUPPORT_DFS && ATH_SUPPORT_STA_DFS 1162 OL_ATH_PARAM_STADFS_ENABLE = 300, /* STA DFS is enabled or not */ 1163 #endif 1164 #if QCA_AIRTIME_FAIRNESS 1165 OL_ATH_PARAM_ATF_STRICT_SCHED = 301, 1166 OL_ATH_PARAM_ATF_GROUP_POLICY = 302, 1167 #endif 1168 #if DBDC_REPEATER_SUPPORT 1169 OL_ATH_PARAM_PRIMARY_RADIO, 1170 OL_ATH_PARAM_DBDC_ENABLE, 1171 #endif 1172 OL_ATH_PARAM_TXPOWER_DBSCALE, 1173 OL_ATH_PARAM_CTL_POWER_SCALE, 1174 #if QCA_AIRTIME_FAIRNESS 1175 OL_ATH_PARAM_ATF_OBSS_SCHED = 307, 1176 OL_ATH_PARAM_ATF_OBSS_SCALE = 308, 1177 #endif 1178 OL_ATH_PARAM_PHY_OFDM_ERR = 309, 1179 OL_ATH_PARAM_PHY_CCK_ERR = 310, 1180 OL_ATH_PARAM_FCS_ERR = 311, 1181 OL_ATH_PARAM_CHAN_UTIL = 312, 1182 #if DBDC_REPEATER_SUPPORT 1183 OL_ATH_PARAM_CLIENT_MCAST, 1184 #endif 1185 OL_ATH_PARAM_EMIWAR_80P80 = 314, 1186 OL_ATH_PARAM_BATCHMODE = 315, 1187 OL_ATH_PARAM_PACK_AGGR_DELAY = 316, 1188 #if UMAC_SUPPORT_ACFG 1189 OL_ATH_PARAM_DIAG_ENABLE = 317, 1190 #endif 1191 #if ATH_SUPPORT_VAP_QOS 1192 OL_ATH_PARAM_VAP_QOS = 318, 1193 #endif 1194 OL_ATH_PARAM_CHAN_STATS_TH = 319, 1195 /* Passive scan is enabled or disabled */ 1196 OL_ATH_PARAM_PASSIVE_SCAN_ENABLE = 320, 1197 OL_ATH_MIN_RSSI_ENABLE = 321, 1198 OL_ATH_MIN_RSSI = 322, 1199 OL_ATH_PARAM_ACS_2G_ALLCHAN = 323, 1200 #if DBDC_REPEATER_SUPPORT 1201 OL_ATH_PARAM_DELAY_STAVAP_UP = 324, 1202 #endif 1203 /* It is used to set the channel switch options */ 1204 OL_ATH_PARAM_CHANSWITCH_OPTIONS = 327, 1205 OL_ATH_BTCOEX_ENABLE = 328, 1206 OL_ATH_BTCOEX_WL_PRIORITY = 329, 1207 OL_ATH_PARAM_TID_OVERRIDE_QUEUE_MAPPING = 330, 1208 OL_ATH_PARAM_CAL_VER_CHECK = 331, 1209 OL_ATH_PARAM_NO_VLAN = 332, 1210 OL_ATH_PARAM_CCA_THRESHOLD = 333, 1211 OL_ATH_PARAM_ATF_LOGGING = 334, 1212 OL_ATH_PARAM_STRICT_DOTH = 335, 1213 OL_ATH_PARAM_DISCONNECTION_TIMEOUT = 336, 1214 OL_ATH_PARAM_RECONFIGURATION_TIMEOUT = 337, 1215 OL_ATH_PARAM_CHANNEL_SWITCH_COUNT = 338, 1216 OL_ATH_PARAM_ALWAYS_PRIMARY = 339, 1217 OL_ATH_PARAM_FAST_LANE = 340, 1218 OL_ATH_GET_BTCOEX_DUTY_CYCLE = 341, 1219 OL_ATH_PARAM_SECONDARY_OFFSET_IE = 342, 1220 OL_ATH_PARAM_WIDE_BAND_SUB_ELEMENT = 343, 1221 OL_ATH_PARAM_PREFERRED_UPLINK = 344, 1222 OL_ATH_PARAM_PRECAC_ENABLE = 345, 1223 OL_ATH_PARAM_PRECAC_TIMEOUT = 346, 1224 OL_ATH_COEX_VER_CFG = 347, 1225 OL_ATH_PARAM_DUMP_TARGET = 348, 1226 OL_ATH_PARAM_PDEV_TO_REO_DEST = 349, 1227 OL_ATH_PARAM_DUMP_CHAINMASK_TABLES = 350, 1228 OL_ATH_PARAM_DUMP_OBJECTS = 351, 1229 OL_ATH_PARAM_ACS_SRLOADVAR = 352, 1230 OL_ATH_PARAM_MGMT_RSSI_THRESHOLD = 353, 1231 OL_ATH_PARAM_EXT_NSS_CAPABLE = 354, 1232 OL_ATH_PARAM_MGMT_PDEV_STATS_TIMER = 355, 1233 OL_ATH_PARAM_TXACKTIMEOUT = 356, 1234 OL_ATH_PARAM_ICM_ACTIVE = 357, 1235 OL_ATH_PARAM_NOMINAL_NOISEFLOOR = 358, 1236 OL_ATH_PARAM_CHAN_INFO = 359, 1237 OL_ATH_PARAM_ACS_RANK = 360, 1238 OL_ATH_PARAM_TXCHAINSOFT = 361, 1239 OL_ATH_PARAM_WIDE_BAND_SCAN = 362, 1240 OL_ATH_PARAM_CCK_TX_ENABLE = 363, 1241 OL_ATH_PARAM_PAPI_ENABLE = 364, 1242 OL_ATH_PARAM_ISOLATION = 365, 1243 }; 1244 1245 /* Enumeration of PDEV Configuration parameter */ 1246 enum _ol_hal_param_t { 1247 OL_HAL_CONFIG_DMA_BEACON_RESPONSE_TIME = 0 1248 }; 1249 #endif 1250 1251 /* Bitmasks for stats that can block */ 1252 #define EXT_TXRX_FW_STATS 0x0001 1253 #endif 1254