1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * @file cdp_txrx_mon_struct.h 22 * @brief Define the monitor mode API structure 23 * shared by data path and the OS interface module 24 */ 25 26 #ifndef _CDP_TXRX_MON_STRUCT_H_ 27 #define _CDP_TXRX_MON_STRUCT_H_ 28 29 #ifdef QCA_SUPPORT_LITE_MONITOR 30 31 #define CDP_LITE_MON_PEER_MAX 16 32 33 #define CDP_MON_FRM_TYPE_MAX 3 34 #define CDP_MON_FRM_FILTER_MODE_MAX 4 35 36 #define CDP_LITE_MON_LEN_64B 0x40 37 #define CDP_LITE_MON_LEN_128B 0x80 38 #define CDP_LITE_MON_LEN_256B 0x100 39 #define CDP_LITE_MON_LEN_FULL 0xFFFF 40 41 #define CDP_LITE_MON_FILTER_ALL 0xFFFF 42 43 /* This should align with nac mac type enumerations in ieee80211_ioctl.h */ 44 #define CDP_LITE_MON_PEER_MAC_TYPE_CLIENT 2 45 46 /* lite mon frame levels */ 47 enum cdp_lite_mon_level { 48 /* level invalid */ 49 CDP_LITE_MON_LEVEL_INVALID = 0, 50 /* level msdu */ 51 CDP_LITE_MON_LEVEL_MSDU = 1, 52 /* level mpdu */ 53 CDP_LITE_MON_LEVEL_MPDU = 2, 54 /* level ppdu */ 55 CDP_LITE_MON_LEVEL_PPDU = 3, 56 }; 57 58 /* lite mon peer action */ 59 enum cdp_lite_mon_peer_action { 60 /* peer add */ 61 CDP_LITE_MON_PEER_ADD = 0, 62 /* peer remove */ 63 CDP_LITE_MON_PEER_REMOVE = 1, 64 }; 65 66 /* lite mon config direction */ 67 enum cdp_lite_mon_direction { 68 /* lite mon config direction rx */ 69 CDP_LITE_MON_DIRECTION_RX = 1, 70 /* lite mon config direction tx */ 71 CDP_LITE_MON_DIRECTION_TX = 2, 72 }; 73 #endif 74 /* Same as MAX_20MHZ_SEGMENTS */ 75 #define CDP_MAX_20MHZ_SEGS 16 76 /* Same as MAX_ANTENNA_EIGHT */ 77 #define CDP_MAX_NUM_ANTENNA 8 78 79 /* XXX not really a mode; there are really multiple PHY's */ 80 enum cdp_mon_phymode { 81 /* autoselect */ 82 CDP_IEEE80211_MODE_AUTO = 0, 83 /* 5GHz, OFDM */ 84 CDP_IEEE80211_MODE_11A = 1, 85 /* 2GHz, CCK */ 86 CDP_IEEE80211_MODE_11B = 2, 87 /* 2GHz, OFDM */ 88 CDP_IEEE80211_MODE_11G = 3, 89 /* 2GHz, GFSK */ 90 CDP_IEEE80211_MODE_FH = 4, 91 /* 5GHz, OFDM, 2x clock dynamic turbo */ 92 CDP_IEEE80211_MODE_TURBO_A = 5, 93 /* 2GHz, OFDM, 2x clock dynamic turbo */ 94 CDP_IEEE80211_MODE_TURBO_G = 6, 95 /* 5Ghz, HT20 */ 96 CDP_IEEE80211_MODE_11NA_HT20 = 7, 97 /* 2Ghz, HT20 */ 98 CDP_IEEE80211_MODE_11NG_HT20 = 8, 99 /* 5Ghz, HT40 (ext ch +1) */ 100 CDP_IEEE80211_MODE_11NA_HT40PLUS = 9, 101 /* 5Ghz, HT40 (ext ch -1) */ 102 CDP_IEEE80211_MODE_11NA_HT40MINUS = 10, 103 /* 2Ghz, HT40 (ext ch +1) */ 104 CDP_IEEE80211_MODE_11NG_HT40PLUS = 11, 105 /* 2Ghz, HT40 (ext ch -1) */ 106 CDP_IEEE80211_MODE_11NG_HT40MINUS = 12, 107 /* 2Ghz, Auto HT40 */ 108 CDP_IEEE80211_MODE_11NG_HT40 = 13, 109 /* 5Ghz, Auto HT40 */ 110 CDP_IEEE80211_MODE_11NA_HT40 = 14, 111 /* 5Ghz, VHT20 */ 112 CDP_IEEE80211_MODE_11AC_VHT20 = 15, 113 /* 5Ghz, VHT40 (Ext ch +1) */ 114 CDP_IEEE80211_MODE_11AC_VHT40PLUS = 16, 115 /* 5Ghz VHT40 (Ext ch -1) */ 116 CDP_IEEE80211_MODE_11AC_VHT40MINUS = 17, 117 /* 5Ghz, VHT40 */ 118 CDP_IEEE80211_MODE_11AC_VHT40 = 18, 119 /* 5Ghz, VHT80 */ 120 CDP_IEEE80211_MODE_11AC_VHT80 = 19, 121 /* 5Ghz, VHT160 */ 122 CDP_IEEE80211_MODE_11AC_VHT160 = 20, 123 /* 5Ghz, VHT80_80 */ 124 CDP_IEEE80211_MODE_11AC_VHT80_80 = 21, 125 }; 126 127 enum { 128 CDP_PKT_TYPE_OFDM = 0, 129 CDP_PKT_TYPE_CCK, 130 CDP_PKT_TYPE_HT, 131 CDP_PKT_TYPE_VHT, 132 CDP_PKT_TYPE_HE, 133 }; 134 135 enum { 136 CDP_SGI_0_8_US = 0, 137 CDP_SGI_0_4_US, 138 CDP_SGI_1_6_US, 139 CDP_SGI_3_2_US, 140 }; 141 142 enum { 143 CDP_RX_TYPE_SU = 0, 144 CDP_RX_TYPE_MU_MIMO, 145 CDP_RX_TYPE_MU_OFDMA, 146 CDP_RX_TYPE_MU_OFDMA_MIMO, 147 }; 148 149 /* 150 *Band Width Types 151 */ 152 enum CMN_BW_TYPES { 153 CMN_BW_20MHZ, 154 CMN_BW_40MHZ, 155 CMN_BW_80MHZ, 156 CMN_BW_160MHZ, 157 CMN_BW_80_80MHZ, 158 #ifdef WLAN_FEATURE_11BE 159 CMN_BW_320MHZ, 160 #endif 161 CMN_BW_CNT, 162 CMN_BW_IDLE = 0xFF, /*default BW state */ 163 }; 164 165 enum cdp_punctured_modes { 166 NO_PUNCTURE, 167 #ifdef WLAN_FEATURE_11BE 168 PUNCTURED_20MHZ, 169 PUNCTURED_40MHZ, 170 PUNCTURED_80MHZ, 171 PUNCTURED_120MHZ, 172 #endif 173 PUNCTURED_MODE_CNT, 174 }; 175 176 struct cdp_mon_status { 177 /* bss color value 1-63 used for update on ppdu_desc bsscolor */ 178 uint8_t bsscolor; 179 int rs_numchains; 180 int rs_flags; 181 #define IEEE80211_RX_FCS_ERROR 0x01 182 #define IEEE80211_RX_MIC_ERROR 0x02 183 #define IEEE80211_RX_DECRYPT_ERROR 0x04 184 /* holes in flags here between, ATH_RX_XXXX to IEEE80211_RX_XXX */ 185 #define IEEE80211_RX_KEYMISS 0x200 186 #define IEEE80211_RX_PN_ERROR 0x400 187 int rs_rssi; /* RSSI (noise floor adjusted) */ 188 int rs_abs_rssi; /* absolute RSSI */ 189 int rs_datarate; /* data rate received */ 190 int rs_rateieee; 191 int rs_ratephy1; 192 int rs_ratephy2; 193 int rs_ratephy3; 194 195 /* Keep the same as ATH_MAX_ANTENNA */ 196 #define IEEE80211_MAX_ANTENNA 3 197 /* RSSI (noise floor adjusted) */ 198 u_int8_t rs_rssictl[IEEE80211_MAX_ANTENNA]; 199 /* RSSI (noise floor adjusted) */ 200 u_int8_t rs_rssiextn[IEEE80211_MAX_ANTENNA]; 201 /* rs_rssi is valid or not */ 202 u_int8_t rs_isvalidrssi; 203 204 enum cdp_mon_phymode rs_phymode; 205 int rs_freq; 206 207 union { 208 u_int8_t data[8]; 209 u_int64_t tsf; 210 } rs_tstamp; 211 212 /* 213 * Detail channel structure of recv frame. 214 * It could be NULL if not available 215 */ 216 217 218 #ifdef ATH_SUPPORT_AOW 219 u_int16_t rs_rxseq; /* WLAN Sequence number */ 220 #endif 221 #ifdef ATH_VOW_EXT_STATS 222 /* Lower 16 bits holds the udp checksum offset in the data pkt */ 223 u_int32_t vow_extstats_offset; 224 /* Higher 16 bits contains offset in the data pkt at which vow 225 * ext stats are embedded 226 */ 227 #endif 228 u_int8_t rs_isaggr; 229 u_int8_t rs_isapsd; 230 int16_t rs_noisefloor; 231 u_int16_t rs_channel; 232 #ifdef ATH_SUPPORT_TxBF 233 u_int32_t rs_rpttstamp; /* txbf report time stamp*/ 234 #endif 235 236 /* The following counts are meant to assist in stats calculation. 237 * These variables are incremented only in specific situations, and 238 * should not be relied upon for any purpose other than the original 239 * stats related purpose they have been introduced for. 240 */ 241 242 u_int16_t rs_cryptodecapcount; /* Crypto bytes decapped/demic'ed. */ 243 u_int8_t rs_padspace; /* No. of padding bytes present after 244 header in wbuf. */ 245 u_int8_t rs_qosdecapcount; /* QoS/HTC bytes decapped. */ 246 247 /* End of stats calculation related counts. */ 248 249 /* 250 * uint8_t rs_lsig[IEEE80211_LSIG_LEN]; 251 * uint8_t rs_htsig[IEEE80211_HTSIG_LEN]; 252 * uint8_t rs_servicebytes[IEEE80211_SB_LEN]; 253 * uint8_t rs_fcs_error; 254 */ 255 256 /* cdp convergence monitor mode status */ 257 union { 258 u_int8_t cdp_data[8]; 259 u_int64_t cdp_tsf; 260 } cdp_rs_tstamp; 261 262 uint8_t cdp_rs_pream_type; 263 uint32_t cdp_rs_user_rssi; 264 uint8_t cdp_rs_stbc; 265 uint8_t cdp_rs_sgi; 266 uint32_t cdf_rs_rate_mcs; 267 uint32_t cdp_rs_reception_type; 268 uint32_t cdp_rs_bw; 269 uint32_t cdp_rs_nss; 270 uint8_t cdp_rs_fcs_err; 271 bool cdp_rs_rxdma_err; 272 }; 273 274 enum { 275 CDP_MON_PPDU_START = 0, 276 CDP_MON_PPDU_END, 277 }; 278 279 #ifdef QCA_UNDECODED_METADATA_SUPPORT 280 /** 281 * enum cdp_mon_phyrx_abort_reason_code: Phy err code to store the reason 282 * why PHY generated an abort request. 283 */ 284 enum cdp_mon_phyrx_abort_reason_code { 285 CDP_PHYRX_ERR_PHY_OFF = 0, 286 CDP_PHYRX_ERR_SYNTH_OFF, 287 CDP_PHYRX_ERR_OFDMA_TIMING, 288 CDP_PHYRX_ERR_OFDMA_SIGNAL_PARITY, 289 CDP_PHYRX_ERR_OFDMA_RATE_ILLEGAL, 290 CDP_PHYRX_ERR_OFDMA_LENGTH_ILLEGAL, 291 CDP_PHYRX_ERR_OFDMA_RESTART, 292 CDP_PHYRX_ERR_OFDMA_SERVICE, 293 CDP_PHYRX_ERR_PPDU_OFDMA_POWER_DROP, 294 CDP_PHYRX_ERR_CCK_BLOKKER, 295 CDP_PHYRX_ERR_CCK_TIMING = 10, 296 CDP_PHYRX_ERR_CCK_HEADER_CRC, 297 CDP_PHYRX_ERR_CCK_RATE_ILLEGAL, 298 CDP_PHYRX_ERR_CCK_LENGTH_ILLEGAL, 299 CDP_PHYRX_ERR_CCK_RESTART, 300 CDP_PHYRX_ERR_CCK_SERVICE, 301 CDP_PHYRX_ERR_CCK_POWER_DROP, 302 CDP_PHYRX_ERR_HT_CRC_ERR, 303 CDP_PHYRX_ERR_HT_LENGTH_ILLEGAL, 304 CDP_PHYRX_ERR_HT_RATE_ILLEGAL, 305 CDP_PHYRX_ERR_HT_ZLF = 20, 306 CDP_PHYRX_ERR_FALSE_RADAR_EXT, 307 CDP_PHYRX_ERR_GREEN_FIELD, 308 CDP_PHYRX_ERR_BW_GT_DYN_BW, 309 CDP_PHYRX_ERR_HT_LSIG_RATE_MISMATCH, 310 CDP_PHYRX_ERR_VHT_CRC_ERROR, 311 CDP_PHYRX_ERR_VHT_SIGA_UNSUPPORTED, 312 CDP_PHYRX_ERR_VHT_LSIG_LEN_INVALID, 313 CDP_PHYRX_ERR_VHT_NDP_OR_ZLF, 314 CDP_PHYRX_ERR_VHT_NSYM_LT_ZERO, 315 CDP_PHYRX_ERR_VHT_RX_EXTRA_SYMBOL_MISMATCH = 30, 316 CDP_PHYRX_ERR_VHT_RX_SKIP_GROUP_ID0, 317 CDP_PHYRX_ERR_VHT_RX_SKIP_GROUP_ID1TO62, 318 CDP_PHYRX_ERR_VHT_RX_SKIP_GROUP_ID63, 319 CDP_PHYRX_ERR_OFDM_LDPC_DECODER_DISABLED, 320 CDP_PHYRX_ERR_DEFER_NAP, 321 CDP_PHYRX_ERR_FDOMAIN_TIMEOUT, 322 CDP_PHYRX_ERR_LSIG_REL_CHECK, 323 CDP_PHYRX_ERR_BT_COLLISION, 324 CDP_PHYRX_ERR_UNSUPPORTED_MU_FEEDBACK, 325 CDP_PHYRX_ERR_PPDU_TX_INTERRUPT_RX = 40, 326 CDP_PHYRX_ERR_UNSUPPORTED_CBF, 327 CDP_PHYRX_ERR_OTHER, 328 CDP_PHYRX_ERR_HE_SIGA_UNSUPPORTED, 329 CDP_PHYRX_ERR_HE_SIGA_CRC_ERROR, 330 CDP_PHYRX_ERR_HE_SIGB_UNSUPPORTED, 331 CDP_PHYRX_ERR_HE_SIGB_CRC_ERROR, 332 CDP_PHYRX_ERR_HE_MU_MODE_UNSUPPORTED, 333 CDP_PHYRX_ERR_HE_NDP_OR_ZLF, 334 CDP_PHYRX_ERR_HE_NSYM_LT_ZERO, 335 CDP_PHYRX_ERR_HE_RU_PARAMS_UNSUPPORTED = 50, 336 CDP_PHYRX_ERR_HE_NUM_USERS_UNSUPPORTED, 337 CDP_PHYRX_ERR_HE_SOUNDING_PARAMS_UNSUPPORTED, 338 CDP_PHYRX_ERR_HE_EXT_SU_UNSUPPORTED, 339 CDP_PHYRX_ERR_HE_TRIG_UNSUPPORTED, 340 CDP_PHYRX_ERR_HE_LSIG_LEN_INVALID = 55, 341 CDP_PHYRX_ERR_HE_LSIG_RATE_MISMATCH, 342 CDP_PHYRX_ERR_OFDMA_SIGNAL_RELIABILITY, 343 CDP_PHYRX_ERR_HT_NSYM_LT_ZERO, 344 CDP_PHYRX_ERR_VHT_LSIG_RATE_MISMATCH, 345 CDP_PHYRX_ERR_VHT_PAID_GID_MISMATCH = 60, 346 CDP_PHYRX_ERR_VHT_UNSUPPORTED_BW, 347 CDP_PHYRX_ERR_VHT_GI_DISAM_MISMATCH, 348 CDP_PHYRX_ERR_RX_WDG_TIMEOUT = 63, 349 CDP_PHYRX_ERR_MAX 350 }; 351 #endif 352 353 #define MAX_PPDU_ID_HIST 128 354 355 /** 356 * struct cdp_pdev_mon_stats 357 * @status_ppdu_state: state on PPDU start and end 358 * @status_ppdu_start: status ring PPDU start TLV count 359 * @status_ppdu_end: status ring PPDU end TLV count 360 * @status_ppdu_compl: status ring matching start and end count on PPDU 361 * @status_ppdu_start_mis: status ring missing start TLV count on PPDU 362 * @status_ppdu_end_mis: status ring missing end TLV count on PPDU 363 * @status_ppdu_done: status ring PPDU done TLV count 364 * @dest_ppdu_done: destination ring PPDU count 365 * @dest_mpdu_done: destination ring MPDU count 366 * @dup_mon_linkdesc_cnt: duplicate link descriptor indications from HW 367 * @dup_mon_buf_cnt: duplicate buffer indications from HW 368 * @tlv_tag_status_err: status not correct in the tlv tag 369 * @status_buf_done_war: Number of status ring buffers for which DMA not done 370 * WAR is applied. 371 * @mon_rx_bufs_replenished_dest: Rx buffers replenish count 372 * @mon_rx_bufs_reaped_dest: Rx buffer reap count 373 * @ppdu_id_mismatch: counter to track ppdu id mismatch in 374 * mointor status and monitor destination ring 375 * @ppdu_id_match: counter to track ppdu id match in 376 * mointor status and monitor destination ring 377 * @status_ppdu_drop: Number of ppdu dropped from monitor status ring 378 * @dest_ppdu_drop: Number of ppdu dropped from monitor destination ring 379 * @mon_link_desc_invalid: msdu link desc invalid count 380 * @mon_rx_desc_invalid: rx_desc invalid count 381 * @mpdu_ppdu_id_mismatch_drop: mpdu's ppdu id did not match destination 382 * ring ppdu id 383 * @mpdu_decap_type_invalid: mpdu decap type invalid count 384 * @rx_undecoded_count: Received undecoded frame count 385 * @rx_undecoded_error: Rx undecoded errors 386 * @rx_hdr_not_received: Rx HDR not received for MPDU 387 * @parent_buf_alloc: Numder of parent nbuf allocated for MPDU 388 * @parent_buf_free: Number of parent nbuf freed 389 * @pkt_buf_count: Number of packet buffers received 390 * @mpdus_to_stack: Number of MPDUs delivered to stack 391 * @status_buf_count: Number of status buffer received 392 * @empty_desc_ppdu: Number of empty desc received 393 * @total_ppdu_info_enq: Number of PPDUs enqueued to wq 394 * @total_ppdu_info_drop: Number of PPDUs dropped 395 * @total_ppdu_info_alloc: Number of PPDU info allocated 396 * @total_ppdu_info_free: Number of PPDU info freed 397 */ 398 struct cdp_pdev_mon_stats { 399 #ifndef REMOVE_MON_DBG_STATS 400 uint32_t status_ppdu_state; 401 uint32_t status_ppdu_start; 402 uint32_t status_ppdu_end; 403 uint32_t status_ppdu_compl; 404 uint32_t status_ppdu_start_mis; 405 uint32_t status_ppdu_end_mis; 406 #endif 407 uint32_t status_ppdu_done; 408 uint32_t dest_ppdu_done; 409 uint32_t dest_mpdu_done; 410 uint32_t dest_mpdu_drop; 411 uint32_t dup_mon_linkdesc_cnt; 412 uint32_t dup_mon_buf_cnt; 413 uint32_t stat_ring_ppdu_id_hist[MAX_PPDU_ID_HIST]; 414 uint32_t dest_ring_ppdu_id_hist[MAX_PPDU_ID_HIST]; 415 uint32_t ppdu_id_hist_idx; 416 uint32_t mon_rx_dest_stuck; 417 uint32_t tlv_tag_status_err; 418 uint32_t status_buf_done_war; 419 uint32_t mon_rx_bufs_replenished_dest; 420 uint32_t mon_rx_bufs_reaped_dest; 421 uint32_t ppdu_id_mismatch; 422 uint32_t ppdu_id_match; 423 uint32_t status_ppdu_drop; 424 uint32_t dest_ppdu_drop; 425 uint32_t mon_link_desc_invalid; 426 uint32_t mon_rx_desc_invalid; 427 uint32_t mon_nbuf_sanity_err; 428 uint32_t mpdu_ppdu_id_mismatch_drop; 429 uint32_t mpdu_decap_type_invalid; 430 #ifdef QCA_UNDECODED_METADATA_SUPPORT 431 uint32_t rx_undecoded_count; 432 uint32_t rx_undecoded_error[CDP_PHYRX_ERR_MAX]; 433 #endif 434 uint32_t rx_hdr_not_received; 435 uint32_t parent_buf_alloc; 436 uint32_t parent_buf_free; 437 uint32_t pkt_buf_count; 438 uint32_t mpdus_buf_to_stack; 439 uint32_t status_buf_count; 440 uint32_t empty_desc_ppdu; 441 uint32_t total_ppdu_info_enq; 442 uint32_t total_ppdu_info_drop; 443 uint32_t total_ppdu_info_alloc; 444 uint32_t total_ppdu_info_free; 445 }; 446 447 #ifdef QCA_SUPPORT_LITE_MONITOR 448 /** 449 * cdp_lite_mon_filter_config - lite mon set/get filter config 450 * @direction: direction tx/rx 451 * @disable: disables lite mon 452 * @level: MSDU/MPDU/PPDU levels 453 * @metadata: meta information to be added 454 * @mgmt_filter: mgmt filter for modes fp,md,mo 455 * @ctrl_filter: ctrl filter for modes fp,md,mo 456 * @data_filter: data filter for modes fp,md,mo 457 * @len: mgmt/ctrl/data frame lens 458 * @debug: debug options 459 * @vdev_id: output vdev id 460 */ 461 struct cdp_lite_mon_filter_config { 462 uint8_t direction; 463 uint8_t disable; 464 uint8_t level; 465 uint8_t metadata; 466 uint16_t mgmt_filter[CDP_MON_FRM_FILTER_MODE_MAX]; 467 uint16_t ctrl_filter[CDP_MON_FRM_FILTER_MODE_MAX]; 468 uint16_t data_filter[CDP_MON_FRM_FILTER_MODE_MAX]; 469 uint16_t len[CDP_MON_FRM_TYPE_MAX]; 470 uint8_t debug; 471 uint8_t vdev_id; 472 }; 473 474 /** 475 * cdp_lite_mon_peer_config - lite mon set peer config 476 * @direction: direction tx/rx 477 * @action: add/del 478 * @vdev_id: peer vdev id 479 * @mac: peer mac 480 */ 481 struct cdp_lite_mon_peer_config { 482 uint8_t direction; 483 uint8_t action; 484 uint8_t vdev_id; 485 uint8_t mac[QDF_MAC_ADDR_SIZE]; 486 }; 487 488 /** 489 * cdp_lite_mon_peer_info - lite mon get peer config 490 * @direction: direction tx/rx 491 * @count: no of peers 492 * @mac: peer macs 493 */ 494 struct cdp_lite_mon_peer_info { 495 uint8_t direction; 496 uint8_t count; 497 uint8_t mac[CDP_LITE_MON_PEER_MAX][QDF_MAC_ADDR_SIZE]; 498 }; 499 #endif 500 /* channel operating width */ 501 enum cdp_channel_width { 502 CHAN_WIDTH_20 = 0, 503 CHAN_WIDTH_40, 504 CHAN_WIDTH_80, 505 CHAN_WIDTH_160, 506 CHAN_WIDTH_80P80, 507 CHAN_WIDTH_5, 508 CHAN_WIDTH_10, 509 CHAN_WIDTH_165, 510 CHAN_WIDTH_160P160, 511 CHAN_WIDTH_320, 512 513 CHAN_WIDTH_MAX, 514 }; 515 516 /* struct cdp_rssi_temp_off_param_dp 517 * @rssi_temp_offset: Temperature based rssi offset , send every 30 secs 518 */ 519 520 struct cdp_rssi_temp_off_param_dp { 521 int32_t rssi_temp_offset; 522 }; 523 524 /* 525 * struct cdp_rssi_dbm_conv_param_dp 526 * @curr_bw: Current bandwidth 527 * @curr_rx_chainmask: Current rx chainmask 528 * @xbar_config: 4 bytes, used for BB to RF Chain mapping 529 * @xlna_bypass_offset: Low noise amplifier bypass offset 530 * @xlna_bypass_threshold: Low noise amplifier bypass threshold 531 * @nfHwDbm: HW noise floor in dBm per chain, per 20MHz subband 532 */ 533 struct cdp_rssi_dbm_conv_param_dp { 534 uint32_t curr_bw; 535 uint32_t curr_rx_chainmask; 536 uint32_t xbar_config; 537 int32_t xlna_bypass_offset; 538 int32_t xlna_bypass_threshold; 539 int8_t nf_hw_dbm[CDP_MAX_NUM_ANTENNA][CDP_MAX_20MHZ_SEGS]; 540 }; 541 542 /* 543 * struct cdp_rssi_db2dbm_param_dp 544 * @pdev_id: pdev_id 545 * @rssi_temp_off_present: to check temp offset values present or not 546 * @rssi_dbm_info_present: to check rssi dbm conversion parameters 547 * present or not 548 * @temp_off_param: cdp_rssi_temp_off_param_dp structure value 549 * @rssi_dbm_param: cdp_rssi_dbm_conv_param_dp staructure value 550 */ 551 struct cdp_rssi_db2dbm_param_dp { 552 uint32_t pdev_id; 553 bool rssi_temp_off_present; 554 bool rssi_dbm_info_present; 555 struct cdp_rssi_temp_off_param_dp temp_off_param; 556 struct cdp_rssi_dbm_conv_param_dp rssi_dbm_param; 557 }; 558 559 /* 560 * enum cdp_mon_reap_source: trigger source of the reap timer of 561 * monitor status ring 562 * @CDP_MON_REAP_SOURCE_PKTLOG: pktlog 563 * @CDP_MON_REAP_SOURCE_CFR: CFR 564 * @CDP_MON_REAP_SOURCE_EMESH: easy mesh 565 * @CDP_MON_REAP_SOURCE_NUM: total number of the sources 566 * @CDP_MON_REAP_SOURCE_ANY: any of the sources 567 */ 568 enum cdp_mon_reap_source { 569 CDP_MON_REAP_SOURCE_PKTLOG, 570 CDP_MON_REAP_SOURCE_CFR, 571 CDP_MON_REAP_SOURCE_EMESH, 572 573 /* keep last */ 574 CDP_MON_REAP_SOURCE_NUM, 575 CDP_MON_REAP_SOURCE_ANY, 576 }; 577 #endif 578