1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ 3 /* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ 4 5 #ifndef WLAN_FIRMWARE_SERVICE_V01_H 6 #define WLAN_FIRMWARE_SERVICE_V01_H 7 8 #include <linux/soc/qcom/qmi.h> 9 10 #define WLFW_SERVICE_ID_V01 0x45 11 #define WLFW_SERVICE_VERS_V01 0x01 12 13 #define QMI_WLFW_SUBSYS_RESTART_LEVEL_RESP_V01 0x0055 14 #define QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01 0x0055 15 #define QMI_WLFW_POWER_SAVE_RESP_V01 0x0050 16 #define QMI_WLFW_CAP_REQ_V01 0x0024 17 #define QMI_WLFW_INI_FILE_DOWNLOAD_RESP_V01 0x0056 18 #define QMI_WLFW_CAL_REPORT_REQ_V01 0x0026 19 #define QMI_WLFW_M3_INFO_RESP_V01 0x003C 20 #define QMI_WLFW_CAL_REPORT_RESP_V01 0x0026 21 #define QMI_WLFW_PCIE_LINK_CTRL_RESP_V01 0x0059 22 #define QMI_WLFW_MAC_ADDR_RESP_V01 0x0033 23 #define QMI_WLFW_DYNAMIC_FEATURE_MASK_RESP_V01 0x003B 24 #define QMI_WLFW_IND_REGISTER_REQ_V01 0x0020 25 #define QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01 0x003B 26 #define QMI_WLFW_QDSS_TRACE_MODE_RESP_V01 0x0045 27 #define QMI_WLFW_AUX_UC_INFO_REQ_V01 0x005A 28 #define QMI_WLFW_FW_READY_IND_V01 0x0021 29 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_RESP_V01 0x0040 30 #define QMI_WLFW_CAL_UPDATE_REQ_V01 0x0029 31 #define QMI_WLFW_PHY_CAP_REQ_V01 0x0057 32 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 33 #define QMI_WLFW_QDSS_TRACE_DATA_RESP_V01 0x0042 34 #define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 35 #define QMI_WLFW_VBATT_RESP_V01 0x0032 36 #define QMI_WLFW_QDSS_TRACE_MODE_REQ_V01 0x0045 37 #define QMI_WLFW_CAL_DOWNLOAD_REQ_V01 0x0027 38 #define QMI_WLFW_IND_REGISTER_RESP_V01 0x0020 39 #define QMI_WLFW_CAL_UPDATE_RESP_V01 0x0029 40 #define QMI_WLFW_BMPS_CTRL_RESP_V01 0x005D 41 #define QMI_WLFW_LPASS_SSR_RESP_V01 0x005E 42 #define QMI_WLFW_AUX_UC_INFO_RESP_V01 0x005A 43 #define QMI_WLFW_M3_INFO_REQ_V01 0x003C 44 #define QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01 0x0053 45 #define QMI_WLFW_ANTENNA_GRANT_RESP_V01 0x0048 46 #define QMI_WLFW_INITIATE_CAL_UPDATE_IND_V01 0x002A 47 #define QMI_WLFW_RESPOND_MEM_REQ_V01 0x0036 48 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 49 #define QMI_WLFW_MSA_READY_IND_V01 0x002B 50 #define QMI_WLFW_WLAN_MODE_REQ_V01 0x0022 51 #define QMI_WLFW_WLAN_CFG_RESP_V01 0x0023 52 #define QMI_WLFW_REJUVENATE_IND_V01 0x0039 53 #define QMI_WLFW_ATHDIAG_WRITE_REQ_V01 0x0031 54 #define QMI_WLFW_SOC_WAKE_REQ_V01 0x004F 55 #define QMI_WLFW_PIN_CONNECT_RESULT_IND_V01 0x002C 56 #define QMI_WLFW_M3_DUMP_UPLOAD_DONE_RESP_V01 0x004E 57 #define QMI_WLFW_QDSS_TRACE_SAVE_IND_V01 0x0041 58 #define QMI_WLFW_BDF_DOWNLOAD_RESP_V01 0x0025 59 #define QMI_WLFW_REJUVENATE_ACK_RESP_V01 0x003A 60 #define QMI_WLFW_MSA_INFO_RESP_V01 0x002D 61 #define QMI_WLFW_TME_LITE_INFO_RESP_V01 0x005B 62 #define QMI_WLFW_SHUTDOWN_REQ_V01 0x0043 63 #define QMI_WLFW_VBATT_REQ_V01 0x0032 64 #define QMI_WLFW_PCIE_LINK_CTRL_REQ_V01 0x0059 65 #define QMI_WLFW_MAC_ADDR_REQ_V01 0x0033 66 #define QMI_WLFW_WLAN_CFG_REQ_V01 0x0023 67 #define QMI_WLFW_ANTENNA_GRANT_REQ_V01 0x0048 68 #define QMI_WLFW_BDF_DOWNLOAD_REQ_V01 0x0025 69 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 70 #define QMI_WLFW_WLAN_HW_INIT_CFG_REQ_V01 0x0058 71 #define QMI_WLFW_RESPOND_GET_INFO_IND_V01 0x004B 72 #define QMI_WLFW_QDSS_TRACE_DATA_REQ_V01 0x0042 73 #define QMI_WLFW_LPASS_SSR_REQ_V01 0x005E 74 #define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027 75 #define QMI_WLFW_INI_RESP_V01 0x002F 76 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040 77 #define QMI_WLFW_ANTENNA_SWITCH_REQ_V01 0x0047 78 #define QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01 0x003F 79 #define QMI_WLFW_INITIATE_CAL_DOWNLOAD_IND_V01 0x0028 80 #define QMI_WLFW_ATHDIAG_WRITE_RESP_V01 0x0031 81 #define QMI_WLFW_FW_SSR_IND_V01 0x005C 82 #define QMI_WLFW_PHY_CAP_RESP_V01 0x0057 83 #define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_V01 0x0044 84 #define QMI_WLFW_SOC_WAKE_RESP_V01 0x004F 85 #define QMI_WLFW_GET_INFO_RESP_V01 0x004A 86 #define QMI_WLFW_BMPS_CTRL_REQ_V01 0x005D 87 #define QMI_WLFW_PCIE_GEN_SWITCH_RESP_V01 0x0053 88 #define QMI_WLFW_INI_REQ_V01 0x002F 89 #define QMI_WLFW_M3_DUMP_UPLOAD_SEGMENTS_REQ_IND_V01 0x0054 90 #define QMI_WLFW_MSA_READY_REQ_V01 0x002E 91 #define QMI_WLFW_M3_DUMP_UPLOAD_DONE_REQ_V01 0x004E 92 #define QMI_WLFW_CAP_RESP_V01 0x0024 93 #define QMI_WLFW_REJUVENATE_ACK_REQ_V01 0x003A 94 #define QMI_WLFW_ATHDIAG_READ_RESP_V01 0x0030 95 #define QMI_WLFW_ANTENNA_SWITCH_RESP_V01 0x0047 96 #define QMI_WLFW_DEVICE_INFO_REQ_V01 0x004C 97 #define QMI_WLFW_MSA_INFO_REQ_V01 0x002D 98 #define QMI_WLFW_HOST_CAP_REQ_V01 0x0034 99 #define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044 100 #define QMI_WLFW_GET_INFO_REQ_V01 0x004A 101 #define QMI_WLFW_CAL_DONE_IND_V01 0x003E 102 #define QMI_WLFW_M3_DUMP_UPLOAD_REQ_IND_V01 0x004D 103 #define QMI_WLFW_WFC_CALL_STATUS_RESP_V01 0x0049 104 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 105 #define QMI_WLFW_POWER_SAVE_REQ_V01 0x0050 106 #define QMI_WLFW_XO_CAL_IND_V01 0x003D 107 #define QMI_WLFW_SHUTDOWN_RESP_V01 0x0043 108 #define QMI_WLFW_ATHDIAG_READ_REQ_V01 0x0030 109 #define QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01 0x0051 110 #define QMI_WLFW_WLAN_MODE_RESP_V01 0x0022 111 #define QMI_WLFW_WFC_CALL_STATUS_REQ_V01 0x0049 112 #define QMI_WLFW_DEVICE_INFO_RESP_V01 0x004C 113 #define QMI_WLFW_MSA_READY_RESP_V01 0x002E 114 #define QMI_WLFW_WLAN_HW_INIT_CFG_RESP_V01 0x0058 115 #define QMI_WLFW_INI_FILE_DOWNLOAD_REQ_V01 0x0056 116 #define QMI_WLFW_QDSS_TRACE_FREE_IND_V01 0x0046 117 #define QMI_WLFW_TME_LITE_INFO_REQ_V01 0x005B 118 #define QMI_WLFW_QDSS_MEM_READY_IND_V01 0x0052 119 120 #define QMI_WLFW_MAX_NUM_CAL_V01 5 121 #define QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01 64 122 #define QMI_WLFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 123 #define QMI_WLFW_MAX_NUM_ADJ_MLO_CHIPS_V01 2 124 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V01 24 125 #define QMI_WLFW_MAX_BUILD_ID_LEN_V01 128 126 #define QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 127 #define QMI_WLFW_MAX_NUM_MLO_V2_CHIPS_V01 4 128 #define QMI_WLFW_MAX_NUM_SHARE_MEM_V01 8 129 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 130 #define QMI_WLFW_MAX_NUM_SVC_V01 24 131 #define QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01 2 132 #define QMI_WLFW_MAC_ADDR_SIZE_V01 6 133 #define QMI_WLFW_MAX_NUM_GPIO_INFO_V01 20 134 #define QMI_WLFW_MAX_NUM_MEM_CFG_V01 2 135 #define QMI_WLFW_PMU_PARAMS_MAX_V01 16 136 #define QMI_WLFW_MAX_NUM_MEM_SEG_V01 52 137 #define QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01 256 138 #define QMI_WLFW_MAX_DATA_SIZE_V01 6144 139 #define QMI_WLFW_FUNCTION_NAME_LEN_V01 128 140 #define QMI_WLFW_MAX_NUM_CE_V01 12 141 #define QMI_WLFW_MAX_TIMESTAMP_LEN_V01 32 142 #define QMI_WLFW_MAX_M3_SEGMENTS_SIZE_V01 10 143 #define QMI_WLFW_PMU_PIN_NAME_MAX_LEN_V01 32 144 #define QMI_WLFW_MAX_STR_LEN_V01 16 145 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_V01 60 146 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01 36 147 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 40 148 #define QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01 6144 149 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 150 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 151 152 enum wlfw_driver_mode_enum_v01 { 153 WLFW_DRIVER_MODE_ENUM_MIN_VAL_V01 = INT_MIN, 154 QMI_WLFW_MISSION_V01 = 0, 155 QMI_WLFW_FTM_V01 = 1, 156 QMI_WLFW_EPPING_V01 = 2, 157 QMI_WLFW_WALTEST_V01 = 3, 158 QMI_WLFW_OFF_V01 = 4, 159 QMI_WLFW_CCPM_V01 = 5, 160 QMI_WLFW_QVIT_V01 = 6, 161 QMI_WLFW_CALIBRATION_V01 = 7, 162 QMI_WLFW_FTM_CALIBRATION_V01 = 10, 163 WLFW_DRIVER_MODE_ENUM_MAX_VAL_V01 = INT_MAX, 164 }; 165 166 enum wlfw_cal_temp_id_enum_v01 { 167 WLFW_CAL_TEMP_ID_ENUM_MIN_VAL_V01 = INT_MIN, 168 QMI_WLFW_CAL_TEMP_IDX_0_V01 = 0, 169 QMI_WLFW_CAL_TEMP_IDX_1_V01 = 1, 170 QMI_WLFW_CAL_TEMP_IDX_2_V01 = 2, 171 QMI_WLFW_CAL_TEMP_IDX_3_V01 = 3, 172 QMI_WLFW_CAL_TEMP_IDX_4_V01 = 4, 173 WLFW_CAL_TEMP_ID_ENUM_MAX_VAL_V01 = INT_MAX, 174 }; 175 176 enum wlfw_pipedir_enum_v01 { 177 WLFW_PIPEDIR_ENUM_MIN_VAL_V01 = INT_MIN, 178 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 179 QMI_WLFW_PIPEDIR_IN_V01 = 1, 180 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 181 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 182 WLFW_PIPEDIR_ENUM_MAX_VAL_V01 = INT_MAX, 183 }; 184 185 enum wlfw_mem_type_enum_v01 { 186 WLFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 187 QMI_WLFW_MEM_TYPE_MSA_V01 = 0, 188 QMI_WLFW_MEM_TYPE_DDR_V01 = 1, 189 QMI_WLFW_MEM_BDF_V01 = 2, 190 QMI_WLFW_MEM_M3_V01 = 3, 191 QMI_WLFW_MEM_CAL_V01 = 4, 192 QMI_WLFW_MEM_DPD_V01 = 5, 193 QMI_WLFW_MEM_QDSS_V01 = 6, 194 QMI_WLFW_MEM_HANG_DATA_V01 = 7, 195 QMI_WLFW_MLO_GLOBAL_MEM_V01 = 8, 196 QMI_WLFW_PAGEABLE_MEM_V01 = 9, 197 QMI_WLFW_AFC_MEM_V01 = 10, 198 QMI_WLFW_MEM_LPASS_SHARED_V01 = 11, 199 WLFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 200 }; 201 202 enum wlfw_share_mem_type_enum_v01 { 203 WLFW_SHARE_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 204 QMI_WLFW_SHARE_MEM_CRASHDBG_V01 = 0, 205 QMI_WLFW_SHARE_MEM_TXSAR_V01 = 1, 206 QMI_WLFW_SHARE_MEM_AFC_V01 = 2, 207 QMI_WLFW_SHARE_MEM_REMOTE_COPY_V01 = 3, 208 QMI_WLFW_SHARE_MEM_MAX_V01 = 8, 209 WLFW_SHARE_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 210 }; 211 212 enum wlfw_qdss_trace_mode_enum_v01 { 213 WLFW_QDSS_TRACE_MODE_ENUM_MIN_VAL_V01 = INT_MIN, 214 QMI_WLFW_QDSS_TRACE_OFF_V01 = 0, 215 QMI_WLFW_QDSS_TRACE_ON_V01 = 1, 216 WLFW_QDSS_TRACE_MODE_ENUM_MAX_VAL_V01 = INT_MAX, 217 }; 218 219 enum wlfw_wfc_media_quality_v01 { 220 WLFW_WFC_MEDIA_QUALITY_MIN_VAL_V01 = INT_MIN, 221 QMI_WLFW_WFC_MEDIA_QUAL_NOT_AVAILABLE_V01 = 0, 222 QMI_WLFW_WFC_MEDIA_QUAL_BAD_V01 = 1, 223 QMI_WLFW_WFC_MEDIA_QUAL_GOOD_V01 = 2, 224 QMI_WLFW_WFC_MEDIA_QUAL_EXCELLENT_V01 = 3, 225 WLFW_WFC_MEDIA_QUALITY_MAX_VAL_V01 = INT_MAX, 226 }; 227 228 enum wlfw_soc_wake_enum_v01 { 229 WLFW_SOC_WAKE_ENUM_MIN_VAL_V01 = INT_MIN, 230 QMI_WLFW_WAKE_REQUEST_V01 = 0, 231 QMI_WLFW_WAKE_RELEASE_V01 = 1, 232 WLFW_SOC_WAKE_ENUM_MAX_VAL_V01 = INT_MAX, 233 }; 234 235 enum wlfw_host_build_type_v01 { 236 WLFW_HOST_BUILD_TYPE_MIN_VAL_V01 = INT_MIN, 237 QMI_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 238 QMI_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 239 QMI_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 240 WLFW_HOST_BUILD_TYPE_MAX_VAL_V01 = INT_MAX, 241 }; 242 243 enum wlfw_qmi_param_value_v01 { 244 WLFW_QMI_PARAM_VALUE_MIN_VAL_V01 = INT_MIN, 245 QMI_PARAM_INVALID_V01 = 0, 246 QMI_PARAM_ENABLE_V01 = 1, 247 QMI_PARAM_DISABLE_V01 = 2, 248 WLFW_QMI_PARAM_VALUE_MAX_VAL_V01 = INT_MAX, 249 }; 250 251 enum wlfw_rd_card_chain_cap_v01 { 252 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 253 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 254 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 255 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 256 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 257 }; 258 259 enum wlfw_he_channel_width_cap_v01 { 260 WLFW_HE_CHANNEL_WIDTH_CAP_MIN_VAL_V01 = INT_MIN, 261 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_UNSPECIFIED_V01 = 0, 262 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_80MHZ_V01 = 1, 263 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_160MHZ_V01 = 2, 264 WLFW_HE_CHANNEL_WIDTH_CAP_MAX_VAL_V01 = INT_MAX, 265 }; 266 267 enum wlfw_phy_qam_cap_v01 { 268 WLFW_PHY_QAM_CAP_MIN_VAL_V01 = INT_MIN, 269 WLFW_PHY_QAM_CAP_UNSPECIFIED_V01 = 0, 270 WLFW_PHY_QAM_CAP_1K_V01 = 1, 271 WLFW_PHY_QAM_CAP_4K_V01 = 2, 272 WLFW_PHY_QAM_CAP_MAX_VAL_V01 = INT_MAX, 273 }; 274 275 enum wlfw_pcie_gen_speed_v01 { 276 WLFW_PCIE_GEN_SPEED_MIN_VAL_V01 = INT_MIN, 277 QMI_PCIE_GEN_SPEED_INVALID_V01 = 0, 278 QMI_PCIE_GEN_SPEED_1_V01 = 1, 279 QMI_PCIE_GEN_SPEED_2_V01 = 2, 280 QMI_PCIE_GEN_SPEED_3_V01 = 3, 281 WLFW_PCIE_GEN_SPEED_MAX_VAL_V01 = INT_MAX, 282 }; 283 284 enum wlfw_power_save_mode_v01 { 285 WLFW_POWER_SAVE_MODE_MIN_VAL_V01 = INT_MIN, 286 WLFW_POWER_SAVE_ENTER_V01 = 0, 287 WLFW_POWER_SAVE_EXIT_V01 = 1, 288 WLFW_POWER_SAVE_MODE_MAX_VAL_V01 = INT_MAX, 289 }; 290 291 enum wlfw_m3_segment_type_v01 { 292 WLFW_M3_SEGMENT_TYPE_MIN_VAL_V01 = INT_MIN, 293 QMI_M3_SEGMENT_INVALID_V01 = 0, 294 QMI_M3_SEGMENT_PHYAREG_V01 = 1, 295 QMI_M3_SEGMENT_PHYDBG_V01 = 2, 296 QMI_M3_SEGMENT_WMAC0_REG_V01 = 3, 297 QMI_M3_SEGMENT_WCSSDBG_V01 = 4, 298 QMI_M3_SEGMENT_PHYAPDMEM_V01 = 5, 299 QMI_M3_SEGMENT_MAX_V01 = 6, 300 WLFW_M3_SEGMENT_TYPE_MAX_VAL_V01 = INT_MAX, 301 }; 302 303 enum cnss_feature_v01 { 304 CNSS_FEATURE_MIN_VAL_V01 = INT_MIN, 305 BOOTSTRAP_CLOCK_SELECT_V01 = 0, 306 CNSS_DRV_SUPPORT_V01 = 1, 307 CNSS_WLAN_EN_SUPPORT_V01 = 2, 308 CNSS_QDSS_CFG_MISS_V01 = 3, 309 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 310 CNSS_RC_EP_ULTRASHORT_CHANNEL_V01 = 5, 311 CNSS_AUX_UC_SUPPORT_V01 = 6, 312 CNSS_MAX_FEATURE_V01 = 64, 313 CNSS_FEATURE_MAX_VAL_V01 = INT_MAX, 314 }; 315 316 enum wlfw_bdf_dnld_method_v01 { 317 WLFW_BDF_DNLD_METHOD_MIN_VAL_V01 = INT_MIN, 318 WLFW_DIRECT_BDF_COPY_V01 = 0, 319 WLFW_SEND_BDF_OVER_QMI_V01 = 1, 320 WLFW_BDF_DNLD_METHOD_MAX_VAL_V01 = INT_MAX, 321 }; 322 323 enum wlfw_gpio_info_type_v01 { 324 WLFW_GPIO_INFO_TYPE_MIN_VAL_V01 = INT_MIN, 325 WLAN_EN_GPIO_V01 = 0, 326 BT_EN_GPIO_V01 = 1, 327 HOST_SOL_GPIO_V01 = 2, 328 TARGET_SOL_GPIO_V01 = 3, 329 GPIO_TYPE_MAX_V01 = 4, 330 WLFW_GPIO_INFO_TYPE_MAX_VAL_V01 = INT_MAX, 331 }; 332 333 enum wlfw_ini_file_type_v01 { 334 WLFW_INI_FILE_TYPE_MIN_VAL_V01 = INT_MIN, 335 WLFW_INI_CFG_FILE_V01 = 0, 336 WLFW_CONN_ROAM_INI_V01 = 1, 337 WLFW_INI_FILE_TYPE_MAX_VAL_V01 = INT_MAX, 338 }; 339 340 enum wlfw_wlan_rf_subtype_v01 { 341 WLFW_WLAN_RF_SUBTYPE_MIN_VAL_V01 = INT_MIN, 342 WLFW_WLAN_RF_SLATE_V01 = 0, 343 WLFW_WLAN_RF_APACHE_V01 = 1, 344 WLFW_WLAN_RF_SUBTYPE_MAX_VAL_V01 = INT_MAX, 345 }; 346 347 enum wlfw_pcie_link_state_enum_v01 { 348 WLFW_PCIE_LINK_STATE_ENUM_MIN_VAL_V01 = INT_MIN, 349 QMI_WLFW_PCIE_ALLOW_LOW_PWR_V01 = 0, 350 QMI_WLFW_PCIE_PREVENT_LOW_PWR_V01 = 1, 351 WLFW_PCIE_LINK_STATE_ENUM_MAX_VAL_V01 = INT_MAX, 352 }; 353 354 enum wlfw_tme_lite_file_type_v01 { 355 WLFW_TME_LITE_FILE_TYPE_MIN_VAL_V01 = INT_MIN, 356 WLFW_TME_LITE_PATCH_FILE_V01 = 0, 357 WLFW_TME_LITE_OEM_FUSE_FILE_V01 = 1, 358 WLFW_TME_LITE_RPR_FILE_V01 = 2, 359 WLFW_TME_LITE_DPR_FILE_V01 = 3, 360 WLFW_TME_LITE_FILE_TYPE_MAX_VAL_V01 = INT_MAX, 361 }; 362 363 enum wlfw_bmps_state_enum_v01 { 364 WLFW_BMPS_STATE_ENUM_MIN_VAL_V01 = INT_MIN, 365 QMI_WLFW_BMPS_ENABLE_V01 = 0, 366 QMI_WLFW_BMPS_DISABLE_V01 = 1, 367 WLFW_BMPS_STATE_ENUM_MAX_VAL_V01 = INT_MAX, 368 }; 369 370 enum wlfw_fw_ssr_reason_v01 { 371 WLFW_FW_SSR_REASON_MIN_VAL_V01 = INT_MIN, 372 WLFW_FW_SSR_REASON_DEFAULT_V01 = 0, 373 WLFW_FW_SSR_REASON_XPAN_V01 = 1, 374 WLFW_FW_SSR_REASON_MAX_VAL_V01 = INT_MAX, 375 }; 376 377 enum wlfw_lpass_ssr_reason_v01 { 378 WLFW_LPASS_SSR_REASON_MIN_VAL_V01 = INT_MIN, 379 WLFW_LPASS_SSR_REASON_NON_CE_V01 = 0, 380 WLFW_LPASS_SSR_REASON_CE_V01 = 1, 381 WLFW_LPASS_SSR_REASON_MAX_VAL_V01 = INT_MAX, 382 }; 383 384 #define QMI_WLFW_CE_ATTR_FLAGS_V01 ((u32)0x00) 385 #define QMI_WLFW_CE_ATTR_NO_SNOOP_V01 ((u32)0x01) 386 #define QMI_WLFW_CE_ATTR_BYTE_SWAP_DATA_V01 ((u32)0x02) 387 #define QMI_WLFW_CE_ATTR_SWIZZLE_DESCRIPTORS_V01 ((u32)0x04) 388 #define QMI_WLFW_CE_ATTR_DISABLE_INTR_V01 ((u32)0x08) 389 #define QMI_WLFW_CE_ATTR_ENABLE_POLL_V01 ((u32)0x10) 390 391 #define QMI_WLFW_ALREADY_REGISTERED_V01 ((u64)0x01ULL) 392 #define QMI_WLFW_FW_READY_V01 ((u64)0x02ULL) 393 #define QMI_WLFW_MSA_READY_V01 ((u64)0x04ULL) 394 #define QMI_WLFW_FW_MEM_READY_V01 ((u64)0x08ULL) 395 #define QMI_WLFW_FW_INIT_DONE_V01 ((u64)0x10ULL) 396 397 #define QMI_WLFW_FW_REJUVENATE_V01 ((u64)0x01ULL) 398 399 #define QMI_WLFW_HW_XPA_V01 ((u64)0x01ULL) 400 #define QMI_WLFW_CBC_FILE_DOWNLOAD_V01 ((u64)0x02ULL) 401 402 #define QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01 ((u64)0x01ULL) 403 #define QMI_WLFW_DIRECT_LINK_SUPPORT_V01 ((u64)0x02ULL) 404 #define QMI_WLFW_AUX_UC_SUPPORT_V01 ((u64)0x04ULL) 405 406 struct wlfw_ce_tgt_pipe_cfg_s_v01 { 407 u32 pipe_num; 408 enum wlfw_pipedir_enum_v01 pipe_dir; 409 u32 nentries; 410 u32 nbytes_max; 411 u32 flags; 412 }; 413 414 struct wlfw_ce_svc_pipe_cfg_s_v01 { 415 u32 service_id; 416 enum wlfw_pipedir_enum_v01 pipe_dir; 417 u32 pipe_num; 418 }; 419 420 struct wlfw_shadow_reg_cfg_s_v01 { 421 u16 id; 422 u16 offset; 423 }; 424 425 struct wlfw_shadow_reg_v2_cfg_s_v01 { 426 u32 addr; 427 }; 428 429 struct wlfw_rri_over_ddr_cfg_s_v01 { 430 u32 base_addr_low; 431 u32 base_addr_high; 432 }; 433 434 struct wlfw_msi_cfg_s_v01 { 435 u16 ce_id; 436 u16 msi_vector; 437 }; 438 439 struct wlfw_memory_region_info_s_v01 { 440 u64 region_addr; 441 u32 size; 442 u8 secure_flag; 443 }; 444 445 struct wlfw_mem_cfg_s_v01 { 446 u64 offset; 447 u32 size; 448 u8 secure_flag; 449 }; 450 451 struct wlfw_mem_seg_s_v01 { 452 u32 size; 453 enum wlfw_mem_type_enum_v01 type; 454 u32 mem_cfg_len; 455 struct wlfw_mem_cfg_s_v01 mem_cfg[QMI_WLFW_MAX_NUM_MEM_CFG_V01]; 456 }; 457 458 struct wlfw_mem_seg_resp_s_v01 { 459 u64 addr; 460 u32 size; 461 enum wlfw_mem_type_enum_v01 type; 462 u8 restore; 463 }; 464 465 struct wlfw_rf_chip_info_s_v01 { 466 u32 chip_id; 467 u32 chip_family; 468 }; 469 470 struct wlfw_rf_board_info_s_v01 { 471 u32 board_id; 472 }; 473 474 struct wlfw_soc_info_s_v01 { 475 u32 soc_id; 476 }; 477 478 struct wlfw_fw_version_info_s_v01 { 479 u32 fw_version; 480 char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN_V01 + 1]; 481 }; 482 483 struct wlfw_host_ddr_range_s_v01 { 484 u64 start; 485 u64 size; 486 }; 487 488 struct wlfw_m3_segment_info_s_v01 { 489 enum wlfw_m3_segment_type_v01 type; 490 u64 addr; 491 u64 size; 492 char name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 493 }; 494 495 struct wlfw_dev_mem_info_s_v01 { 496 u64 start; 497 u64 size; 498 }; 499 500 struct wlfw_host_mlo_chip_info_s_v01 { 501 u8 chip_id; 502 u8 num_local_links; 503 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 504 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 505 }; 506 507 struct wlfw_host_mlo_chip_v2_info_s_v01 { 508 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info; 509 u8 adj_mlo_num_chips; 510 struct wlfw_host_mlo_chip_info_s_v01 adj_mlo_chip_info[QMI_WLFW_MAX_NUM_ADJ_MLO_CHIPS_V01]; 511 }; 512 513 struct wlfw_pmu_param_v01 { 514 u8 pin_name[QMI_WLFW_PMU_PIN_NAME_MAX_LEN_V01]; 515 u32 wake_volt_valid; 516 u32 wake_volt; 517 u32 sleep_volt_valid; 518 u32 sleep_volt; 519 }; 520 521 struct wlfw_pmu_cfg_v01 { 522 u32 pmu_param_len; 523 struct wlfw_pmu_param_v01 pmu_param[QMI_WLFW_PMU_PARAMS_MAX_V01]; 524 }; 525 526 struct wlfw_shadow_reg_v3_cfg_s_v01 { 527 u32 addr; 528 }; 529 530 struct wlfw_share_mem_info_s_v01 { 531 enum wlfw_share_mem_type_enum_v01 type; 532 u64 start; 533 u64 size; 534 }; 535 536 struct wlfw_host_pcie_link_info_s_v01 { 537 u32 pci_link_speed; 538 u32 pci_link_width; 539 }; 540 541 struct wlfw_ind_register_req_msg_v01 { 542 u8 fw_ready_enable_valid; 543 u8 fw_ready_enable; 544 u8 initiate_cal_download_enable_valid; 545 u8 initiate_cal_download_enable; 546 u8 initiate_cal_update_enable_valid; 547 u8 initiate_cal_update_enable; 548 u8 msa_ready_enable_valid; 549 u8 msa_ready_enable; 550 u8 pin_connect_result_enable_valid; 551 u8 pin_connect_result_enable; 552 u8 client_id_valid; 553 u32 client_id; 554 u8 request_mem_enable_valid; 555 u8 request_mem_enable; 556 u8 fw_mem_ready_enable_valid; 557 u8 fw_mem_ready_enable; 558 u8 fw_init_done_enable_valid; 559 u8 fw_init_done_enable; 560 u8 rejuvenate_enable_valid; 561 u32 rejuvenate_enable; 562 u8 xo_cal_enable_valid; 563 u8 xo_cal_enable; 564 u8 cal_done_enable_valid; 565 u8 cal_done_enable; 566 u8 qdss_trace_req_mem_enable_valid; 567 u8 qdss_trace_req_mem_enable; 568 u8 qdss_trace_save_enable_valid; 569 u8 qdss_trace_save_enable; 570 u8 qdss_trace_free_enable_valid; 571 u8 qdss_trace_free_enable; 572 u8 respond_get_info_enable_valid; 573 u8 respond_get_info_enable; 574 u8 m3_dump_upload_req_enable_valid; 575 u8 m3_dump_upload_req_enable; 576 u8 wfc_call_twt_config_enable_valid; 577 u8 wfc_call_twt_config_enable; 578 u8 qdss_mem_ready_enable_valid; 579 u8 qdss_mem_ready_enable; 580 u8 m3_dump_upload_segments_req_enable_valid; 581 u8 m3_dump_upload_segments_req_enable; 582 u8 fw_ssr_enable_valid; 583 u8 fw_ssr_enable; 584 }; 585 #define WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN 90 586 extern struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[]; 587 588 struct wlfw_ind_register_resp_msg_v01 { 589 struct qmi_response_type_v01 resp; 590 u8 fw_status_valid; 591 u64 fw_status; 592 }; 593 #define WLFW_IND_REGISTER_RESP_MSG_V01_MAX_MSG_LEN 18 594 extern struct qmi_elem_info wlfw_ind_register_resp_msg_v01_ei[]; 595 596 struct wlfw_fw_ready_ind_msg_v01 { 597 char placeholder; 598 }; 599 #define WLFW_FW_READY_IND_MSG_V01_MAX_MSG_LEN 0 600 extern struct qmi_elem_info wlfw_fw_ready_ind_msg_v01_ei[]; 601 602 struct wlfw_msa_ready_ind_msg_v01 { 603 u8 hang_data_addr_offset_valid; 604 u32 hang_data_addr_offset; 605 u8 hang_data_length_valid; 606 u16 hang_data_length; 607 }; 608 #define WLFW_MSA_READY_IND_MSG_V01_MAX_MSG_LEN 12 609 extern struct qmi_elem_info wlfw_msa_ready_ind_msg_v01_ei[]; 610 611 struct wlfw_pin_connect_result_ind_msg_v01 { 612 u8 pwr_pin_result_valid; 613 u32 pwr_pin_result; 614 u8 phy_io_pin_result_valid; 615 u32 phy_io_pin_result; 616 u8 rf_pin_result_valid; 617 u32 rf_pin_result; 618 }; 619 #define WLFW_PIN_CONNECT_RESULT_IND_MSG_V01_MAX_MSG_LEN 21 620 extern struct qmi_elem_info wlfw_pin_connect_result_ind_msg_v01_ei[]; 621 622 struct wlfw_wlan_mode_req_msg_v01 { 623 enum wlfw_driver_mode_enum_v01 mode; 624 u8 hw_debug_valid; 625 u8 hw_debug; 626 u8 xo_cal_data_valid; 627 u8 xo_cal_data; 628 u8 wlan_en_delay_valid; 629 u32 wlan_en_delay; 630 }; 631 #define WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN 22 632 extern struct qmi_elem_info wlfw_wlan_mode_req_msg_v01_ei[]; 633 634 struct wlfw_wlan_mode_resp_msg_v01 { 635 struct qmi_response_type_v01 resp; 636 }; 637 #define WLFW_WLAN_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 638 extern struct qmi_elem_info wlfw_wlan_mode_resp_msg_v01_ei[]; 639 640 struct wlfw_wlan_cfg_req_msg_v01 { 641 u8 host_version_valid; 642 char host_version[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 643 u8 tgt_cfg_valid; 644 u32 tgt_cfg_len; 645 struct wlfw_ce_tgt_pipe_cfg_s_v01 tgt_cfg[QMI_WLFW_MAX_NUM_CE_V01]; 646 u8 svc_cfg_valid; 647 u32 svc_cfg_len; 648 struct wlfw_ce_svc_pipe_cfg_s_v01 svc_cfg[QMI_WLFW_MAX_NUM_SVC_V01]; 649 u8 shadow_reg_valid; 650 u32 shadow_reg_len; 651 struct wlfw_shadow_reg_cfg_s_v01 shadow_reg[QMI_WLFW_MAX_NUM_SHADOW_REG_V01]; 652 u8 shadow_reg_v2_valid; 653 u32 shadow_reg_v2_len; 654 struct wlfw_shadow_reg_v2_cfg_s_v01 shadow_reg_v2[QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01]; 655 u8 rri_over_ddr_cfg_valid; 656 struct wlfw_rri_over_ddr_cfg_s_v01 rri_over_ddr_cfg; 657 u8 msi_cfg_valid; 658 u32 msi_cfg_len; 659 struct wlfw_msi_cfg_s_v01 msi_cfg[QMI_WLFW_MAX_NUM_CE_V01]; 660 u8 shadow_reg_v3_valid; 661 u32 shadow_reg_v3_len; 662 struct wlfw_shadow_reg_v3_cfg_s_v01 shadow_reg_v3[QMI_WLFW_MAX_NUM_SHADOW_REG_V3_V01]; 663 }; 664 #define WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN 1110 665 extern struct qmi_elem_info wlfw_wlan_cfg_req_msg_v01_ei[]; 666 667 struct wlfw_wlan_cfg_resp_msg_v01 { 668 struct qmi_response_type_v01 resp; 669 }; 670 #define WLFW_WLAN_CFG_RESP_MSG_V01_MAX_MSG_LEN 7 671 extern struct qmi_elem_info wlfw_wlan_cfg_resp_msg_v01_ei[]; 672 673 struct wlfw_cap_req_msg_v01 { 674 char placeholder; 675 }; 676 #define WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN 0 677 extern struct qmi_elem_info wlfw_cap_req_msg_v01_ei[]; 678 679 struct wlfw_cap_resp_msg_v01 { 680 struct qmi_response_type_v01 resp; 681 u8 chip_info_valid; 682 struct wlfw_rf_chip_info_s_v01 chip_info; 683 u8 board_info_valid; 684 struct wlfw_rf_board_info_s_v01 board_info; 685 u8 soc_info_valid; 686 struct wlfw_soc_info_s_v01 soc_info; 687 u8 fw_version_info_valid; 688 struct wlfw_fw_version_info_s_v01 fw_version_info; 689 u8 fw_build_id_valid; 690 char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN_V01 + 1]; 691 u8 num_macs_valid; 692 u8 num_macs; 693 u8 voltage_mv_valid; 694 u32 voltage_mv; 695 u8 time_freq_hz_valid; 696 u32 time_freq_hz; 697 u8 otp_version_valid; 698 u32 otp_version; 699 u8 eeprom_caldata_read_timeout_valid; 700 u32 eeprom_caldata_read_timeout; 701 u8 fw_caps_valid; 702 u64 fw_caps; 703 u8 rd_card_chain_cap_valid; 704 enum wlfw_rd_card_chain_cap_v01 rd_card_chain_cap; 705 u8 dev_mem_info_valid; 706 struct wlfw_dev_mem_info_s_v01 dev_mem_info[QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 707 u8 foundry_name_valid; 708 char foundry_name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 709 u8 hang_data_addr_offset_valid; 710 u32 hang_data_addr_offset; 711 u8 hang_data_length_valid; 712 u16 hang_data_length; 713 u8 bdf_dnld_method_valid; 714 enum wlfw_bdf_dnld_method_v01 bdf_dnld_method; 715 u8 hwid_bitmap_valid; 716 u8 hwid_bitmap; 717 u8 ol_cpr_cfg_valid; 718 struct wlfw_pmu_cfg_v01 ol_cpr_cfg; 719 u8 regdb_mandatory_valid; 720 u8 regdb_mandatory; 721 u8 regdb_support_valid; 722 u8 regdb_support; 723 u8 rxgainlut_support_valid; 724 u8 rxgainlut_support; 725 u8 he_channel_width_cap_valid; 726 enum wlfw_he_channel_width_cap_v01 he_channel_width_cap; 727 u8 phy_qam_cap_valid; 728 enum wlfw_phy_qam_cap_v01 phy_qam_cap; 729 }; 730 #define WLFW_CAP_RESP_MSG_V01_MAX_MSG_LEN 1160 731 extern struct qmi_elem_info wlfw_cap_resp_msg_v01_ei[]; 732 733 struct wlfw_bdf_download_req_msg_v01 { 734 u8 valid; 735 u8 file_id_valid; 736 enum wlfw_cal_temp_id_enum_v01 file_id; 737 u8 total_size_valid; 738 u32 total_size; 739 u8 seg_id_valid; 740 u32 seg_id; 741 u8 data_valid; 742 u32 data_len; 743 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 744 u8 end_valid; 745 u8 end; 746 u8 bdf_type_valid; 747 u8 bdf_type; 748 }; 749 #define WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6182 750 extern struct qmi_elem_info wlfw_bdf_download_req_msg_v01_ei[]; 751 752 struct wlfw_bdf_download_resp_msg_v01 { 753 struct qmi_response_type_v01 resp; 754 u8 host_bdf_data_valid; 755 u64 host_bdf_data; 756 }; 757 #define WLFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 18 758 extern struct qmi_elem_info wlfw_bdf_download_resp_msg_v01_ei[]; 759 760 struct wlfw_cal_report_req_msg_v01 { 761 u32 meta_data_len; 762 enum wlfw_cal_temp_id_enum_v01 meta_data[QMI_WLFW_MAX_NUM_CAL_V01]; 763 u8 xo_cal_data_valid; 764 u8 xo_cal_data; 765 u8 cal_remove_supported_valid; 766 u8 cal_remove_supported; 767 u8 cal_file_download_size_valid; 768 u64 cal_file_download_size; 769 }; 770 #define WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN 43 771 extern struct qmi_elem_info wlfw_cal_report_req_msg_v01_ei[]; 772 773 struct wlfw_cal_report_resp_msg_v01 { 774 struct qmi_response_type_v01 resp; 775 }; 776 #define WLFW_CAL_REPORT_RESP_MSG_V01_MAX_MSG_LEN 7 777 extern struct qmi_elem_info wlfw_cal_report_resp_msg_v01_ei[]; 778 779 struct wlfw_initiate_cal_download_ind_msg_v01 { 780 enum wlfw_cal_temp_id_enum_v01 cal_id; 781 u8 total_size_valid; 782 u32 total_size; 783 u8 cal_data_location_valid; 784 u32 cal_data_location; 785 }; 786 #define WLFW_INITIATE_CAL_DOWNLOAD_IND_MSG_V01_MAX_MSG_LEN 21 787 extern struct qmi_elem_info wlfw_initiate_cal_download_ind_msg_v01_ei[]; 788 789 struct wlfw_cal_download_req_msg_v01 { 790 u8 valid; 791 u8 file_id_valid; 792 enum wlfw_cal_temp_id_enum_v01 file_id; 793 u8 total_size_valid; 794 u32 total_size; 795 u8 seg_id_valid; 796 u32 seg_id; 797 u8 data_valid; 798 u32 data_len; 799 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 800 u8 end_valid; 801 u8 end; 802 u8 cal_data_location_valid; 803 u32 cal_data_location; 804 }; 805 #define WLFW_CAL_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6185 806 extern struct qmi_elem_info wlfw_cal_download_req_msg_v01_ei[]; 807 808 struct wlfw_cal_download_resp_msg_v01 { 809 struct qmi_response_type_v01 resp; 810 }; 811 #define WLFW_CAL_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 812 extern struct qmi_elem_info wlfw_cal_download_resp_msg_v01_ei[]; 813 814 struct wlfw_initiate_cal_update_ind_msg_v01 { 815 enum wlfw_cal_temp_id_enum_v01 cal_id; 816 u32 total_size; 817 u8 cal_data_location_valid; 818 u32 cal_data_location; 819 }; 820 #define WLFW_INITIATE_CAL_UPDATE_IND_MSG_V01_MAX_MSG_LEN 21 821 extern struct qmi_elem_info wlfw_initiate_cal_update_ind_msg_v01_ei[]; 822 823 struct wlfw_cal_update_req_msg_v01 { 824 enum wlfw_cal_temp_id_enum_v01 cal_id; 825 u32 seg_id; 826 }; 827 #define WLFW_CAL_UPDATE_REQ_MSG_V01_MAX_MSG_LEN 14 828 extern struct qmi_elem_info wlfw_cal_update_req_msg_v01_ei[]; 829 830 struct wlfw_cal_update_resp_msg_v01 { 831 struct qmi_response_type_v01 resp; 832 u8 file_id_valid; 833 enum wlfw_cal_temp_id_enum_v01 file_id; 834 u8 total_size_valid; 835 u32 total_size; 836 u8 seg_id_valid; 837 u32 seg_id; 838 u8 data_valid; 839 u32 data_len; 840 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 841 u8 end_valid; 842 u8 end; 843 u8 cal_data_location_valid; 844 u32 cal_data_location; 845 }; 846 #define WLFW_CAL_UPDATE_RESP_MSG_V01_MAX_MSG_LEN 6188 847 extern struct qmi_elem_info wlfw_cal_update_resp_msg_v01_ei[]; 848 849 struct wlfw_msa_info_req_msg_v01 { 850 u64 msa_addr; 851 u32 size; 852 }; 853 #define WLFW_MSA_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 854 extern struct qmi_elem_info wlfw_msa_info_req_msg_v01_ei[]; 855 856 struct wlfw_msa_info_resp_msg_v01 { 857 struct qmi_response_type_v01 resp; 858 u32 mem_region_info_len; 859 struct wlfw_memory_region_info_s_v01 mem_region_info[QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01]; 860 }; 861 #define WLFW_MSA_INFO_RESP_MSG_V01_MAX_MSG_LEN 37 862 extern struct qmi_elem_info wlfw_msa_info_resp_msg_v01_ei[]; 863 864 struct wlfw_msa_ready_req_msg_v01 { 865 char placeholder; 866 }; 867 #define WLFW_MSA_READY_REQ_MSG_V01_MAX_MSG_LEN 0 868 extern struct qmi_elem_info wlfw_msa_ready_req_msg_v01_ei[]; 869 870 struct wlfw_msa_ready_resp_msg_v01 { 871 struct qmi_response_type_v01 resp; 872 }; 873 #define WLFW_MSA_READY_RESP_MSG_V01_MAX_MSG_LEN 7 874 extern struct qmi_elem_info wlfw_msa_ready_resp_msg_v01_ei[]; 875 876 struct wlfw_ini_req_msg_v01 { 877 u8 enablefwlog_valid; 878 u8 enablefwlog; 879 }; 880 #define WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN 4 881 extern struct qmi_elem_info wlfw_ini_req_msg_v01_ei[]; 882 883 struct wlfw_ini_resp_msg_v01 { 884 struct qmi_response_type_v01 resp; 885 }; 886 #define WLFW_INI_RESP_MSG_V01_MAX_MSG_LEN 7 887 extern struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[]; 888 889 struct wlfw_athdiag_read_req_msg_v01 { 890 u32 offset; 891 u32 mem_type; 892 u32 data_len; 893 }; 894 #define WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN 21 895 extern struct qmi_elem_info wlfw_athdiag_read_req_msg_v01_ei[]; 896 897 struct wlfw_athdiag_read_resp_msg_v01 { 898 struct qmi_response_type_v01 resp; 899 u8 data_valid; 900 u32 data_len; 901 u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; 902 }; 903 #define WLFW_ATHDIAG_READ_RESP_MSG_V01_MAX_MSG_LEN 6156 904 extern struct qmi_elem_info wlfw_athdiag_read_resp_msg_v01_ei[]; 905 906 struct wlfw_athdiag_write_req_msg_v01 { 907 u32 offset; 908 u32 mem_type; 909 u32 data_len; 910 u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; 911 }; 912 #define WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN 6163 913 extern struct qmi_elem_info wlfw_athdiag_write_req_msg_v01_ei[]; 914 915 struct wlfw_athdiag_write_resp_msg_v01 { 916 struct qmi_response_type_v01 resp; 917 }; 918 #define WLFW_ATHDIAG_WRITE_RESP_MSG_V01_MAX_MSG_LEN 7 919 extern struct qmi_elem_info wlfw_athdiag_write_resp_msg_v01_ei[]; 920 921 struct wlfw_vbatt_req_msg_v01 { 922 u64 voltage_uv; 923 }; 924 #define WLFW_VBATT_REQ_MSG_V01_MAX_MSG_LEN 11 925 extern struct qmi_elem_info wlfw_vbatt_req_msg_v01_ei[]; 926 927 struct wlfw_vbatt_resp_msg_v01 { 928 struct qmi_response_type_v01 resp; 929 }; 930 #define WLFW_VBATT_RESP_MSG_V01_MAX_MSG_LEN 7 931 extern struct qmi_elem_info wlfw_vbatt_resp_msg_v01_ei[]; 932 933 struct wlfw_mac_addr_req_msg_v01 { 934 u8 mac_addr_valid; 935 u8 mac_addr[QMI_WLFW_MAC_ADDR_SIZE_V01]; 936 }; 937 #define WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN 9 938 extern struct qmi_elem_info wlfw_mac_addr_req_msg_v01_ei[]; 939 940 struct wlfw_mac_addr_resp_msg_v01 { 941 struct qmi_response_type_v01 resp; 942 }; 943 #define WLFW_MAC_ADDR_RESP_MSG_V01_MAX_MSG_LEN 7 944 extern struct qmi_elem_info wlfw_mac_addr_resp_msg_v01_ei[]; 945 946 struct wlfw_host_cap_req_msg_v01 { 947 u8 num_clients_valid; 948 u32 num_clients; 949 u8 wake_msi_valid; 950 u32 wake_msi; 951 u8 gpios_valid; 952 u32 gpios_len; 953 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 954 u8 nm_modem_valid; 955 u8 nm_modem; 956 u8 bdf_support_valid; 957 u8 bdf_support; 958 u8 bdf_cache_support_valid; 959 u8 bdf_cache_support; 960 u8 m3_support_valid; 961 u8 m3_support; 962 u8 m3_cache_support_valid; 963 u8 m3_cache_support; 964 u8 cal_filesys_support_valid; 965 u8 cal_filesys_support; 966 u8 cal_cache_support_valid; 967 u8 cal_cache_support; 968 u8 cal_done_valid; 969 u8 cal_done; 970 u8 mem_bucket_valid; 971 u32 mem_bucket; 972 u8 mem_cfg_mode_valid; 973 u8 mem_cfg_mode; 974 u8 cal_duration_valid; 975 u16 cal_duration; 976 u8 platform_name_valid; 977 char platform_name[QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 978 u8 ddr_range_valid; 979 struct wlfw_host_ddr_range_s_v01 ddr_range[QMI_WLFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 980 u8 host_build_type_valid; 981 enum wlfw_host_build_type_v01 host_build_type; 982 u8 mlo_capable_valid; 983 u8 mlo_capable; 984 u8 mlo_chip_id_valid; 985 u16 mlo_chip_id; 986 u8 mlo_group_id_valid; 987 u8 mlo_group_id; 988 u8 max_mlo_peer_valid; 989 u16 max_mlo_peer; 990 u8 mlo_num_chips_valid; 991 u8 mlo_num_chips; 992 u8 mlo_chip_info_valid; 993 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 994 u8 feature_list_valid; 995 u64 feature_list; 996 u8 num_wlan_clients_valid; 997 u16 num_wlan_clients; 998 u8 num_wlan_vaps_valid; 999 u8 num_wlan_vaps; 1000 u8 wake_msi_addr_valid; 1001 u32 wake_msi_addr; 1002 u8 wlan_enable_delay_valid; 1003 u32 wlan_enable_delay; 1004 u8 ddr_type_valid; 1005 u32 ddr_type; 1006 u8 gpio_info_valid; 1007 u32 gpio_info_len; 1008 u32 gpio_info[QMI_WLFW_MAX_NUM_GPIO_INFO_V01]; 1009 u8 fw_ini_cfg_support_valid; 1010 u8 fw_ini_cfg_support; 1011 u8 mlo_chip_v2_info_valid; 1012 struct wlfw_host_mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MAX_NUM_MLO_V2_CHIPS_V01]; 1013 u8 pcie_link_info_valid; 1014 struct wlfw_host_pcie_link_info_s_v01 pcie_link_info; 1015 }; 1016 #define WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN 581 1017 extern struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[]; 1018 1019 struct wlfw_host_cap_resp_msg_v01 { 1020 struct qmi_response_type_v01 resp; 1021 }; 1022 #define WLFW_HOST_CAP_RESP_MSG_V01_MAX_MSG_LEN 7 1023 extern struct qmi_elem_info wlfw_host_cap_resp_msg_v01_ei[]; 1024 1025 struct wlfw_request_mem_ind_msg_v01 { 1026 u32 mem_seg_len; 1027 struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1028 }; 1029 #define WLFW_REQUEST_MEM_IND_MSG_V01_MAX_MSG_LEN 1824 1030 extern struct qmi_elem_info wlfw_request_mem_ind_msg_v01_ei[]; 1031 1032 struct wlfw_respond_mem_req_msg_v01 { 1033 u32 mem_seg_len; 1034 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1035 }; 1036 #define WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN 888 1037 extern struct qmi_elem_info wlfw_respond_mem_req_msg_v01_ei[]; 1038 1039 struct wlfw_respond_mem_resp_msg_v01 { 1040 struct qmi_response_type_v01 resp; 1041 u8 share_mem_valid; 1042 u32 share_mem_len; 1043 struct wlfw_share_mem_info_s_v01 share_mem[QMI_WLFW_MAX_NUM_SHARE_MEM_V01]; 1044 }; 1045 #define WLFW_RESPOND_MEM_RESP_MSG_V01_MAX_MSG_LEN 171 1046 extern struct qmi_elem_info wlfw_respond_mem_resp_msg_v01_ei[]; 1047 1048 struct wlfw_fw_mem_ready_ind_msg_v01 { 1049 char placeholder; 1050 }; 1051 #define WLFW_FW_MEM_READY_IND_MSG_V01_MAX_MSG_LEN 0 1052 extern struct qmi_elem_info wlfw_fw_mem_ready_ind_msg_v01_ei[]; 1053 1054 struct wlfw_fw_init_done_ind_msg_v01 { 1055 u8 hang_data_addr_offset_valid; 1056 u32 hang_data_addr_offset; 1057 u8 hang_data_length_valid; 1058 u16 hang_data_length; 1059 }; 1060 #define WLFW_FW_INIT_DONE_IND_MSG_V01_MAX_MSG_LEN 12 1061 extern struct qmi_elem_info wlfw_fw_init_done_ind_msg_v01_ei[]; 1062 1063 struct wlfw_rejuvenate_ind_msg_v01 { 1064 u8 cause_for_rejuvenation_valid; 1065 u8 cause_for_rejuvenation; 1066 u8 requesting_sub_system_valid; 1067 u8 requesting_sub_system; 1068 u8 line_number_valid; 1069 u16 line_number; 1070 u8 function_name_valid; 1071 char function_name[QMI_WLFW_FUNCTION_NAME_LEN_V01 + 1]; 1072 }; 1073 #define WLFW_REJUVENATE_IND_MSG_V01_MAX_MSG_LEN 144 1074 extern struct qmi_elem_info wlfw_rejuvenate_ind_msg_v01_ei[]; 1075 1076 struct wlfw_rejuvenate_ack_req_msg_v01 { 1077 char placeholder; 1078 }; 1079 #define WLFW_REJUVENATE_ACK_REQ_MSG_V01_MAX_MSG_LEN 0 1080 extern struct qmi_elem_info wlfw_rejuvenate_ack_req_msg_v01_ei[]; 1081 1082 struct wlfw_rejuvenate_ack_resp_msg_v01 { 1083 struct qmi_response_type_v01 resp; 1084 }; 1085 #define WLFW_REJUVENATE_ACK_RESP_MSG_V01_MAX_MSG_LEN 7 1086 extern struct qmi_elem_info wlfw_rejuvenate_ack_resp_msg_v01_ei[]; 1087 1088 struct wlfw_dynamic_feature_mask_req_msg_v01 { 1089 u8 mask_valid; 1090 u64 mask; 1091 }; 1092 #define WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN 11 1093 extern struct qmi_elem_info wlfw_dynamic_feature_mask_req_msg_v01_ei[]; 1094 1095 struct wlfw_dynamic_feature_mask_resp_msg_v01 { 1096 struct qmi_response_type_v01 resp; 1097 u8 prev_mask_valid; 1098 u64 prev_mask; 1099 u8 curr_mask_valid; 1100 u64 curr_mask; 1101 }; 1102 #define WLFW_DYNAMIC_FEATURE_MASK_RESP_MSG_V01_MAX_MSG_LEN 29 1103 extern struct qmi_elem_info wlfw_dynamic_feature_mask_resp_msg_v01_ei[]; 1104 1105 struct wlfw_m3_info_req_msg_v01 { 1106 u64 addr; 1107 u32 size; 1108 }; 1109 #define WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 1110 extern struct qmi_elem_info wlfw_m3_info_req_msg_v01_ei[]; 1111 1112 struct wlfw_m3_info_resp_msg_v01 { 1113 struct qmi_response_type_v01 resp; 1114 }; 1115 #define WLFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1116 extern struct qmi_elem_info wlfw_m3_info_resp_msg_v01_ei[]; 1117 1118 struct wlfw_xo_cal_ind_msg_v01 { 1119 u8 xo_cal_data; 1120 }; 1121 #define WLFW_XO_CAL_IND_MSG_V01_MAX_MSG_LEN 4 1122 extern struct qmi_elem_info wlfw_xo_cal_ind_msg_v01_ei[]; 1123 1124 struct wlfw_cal_done_ind_msg_v01 { 1125 u8 cal_file_upload_size_valid; 1126 u64 cal_file_upload_size; 1127 }; 1128 #define WLFW_CAL_DONE_IND_MSG_V01_MAX_MSG_LEN 11 1129 extern struct qmi_elem_info wlfw_cal_done_ind_msg_v01_ei[]; 1130 1131 struct wlfw_qdss_trace_req_mem_ind_msg_v01 { 1132 u32 mem_seg_len; 1133 struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1134 }; 1135 #define WLFW_QDSS_TRACE_REQ_MEM_IND_MSG_V01_MAX_MSG_LEN 1824 1136 extern struct qmi_elem_info wlfw_qdss_trace_req_mem_ind_msg_v01_ei[]; 1137 1138 struct wlfw_qdss_trace_mem_info_req_msg_v01 { 1139 u32 mem_seg_len; 1140 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1141 u8 end_valid; 1142 u8 end; 1143 }; 1144 #define WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN 892 1145 extern struct qmi_elem_info wlfw_qdss_trace_mem_info_req_msg_v01_ei[]; 1146 1147 struct wlfw_qdss_trace_mem_info_resp_msg_v01 { 1148 struct qmi_response_type_v01 resp; 1149 }; 1150 #define WLFW_QDSS_TRACE_MEM_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1151 extern struct qmi_elem_info wlfw_qdss_trace_mem_info_resp_msg_v01_ei[]; 1152 1153 struct wlfw_qdss_trace_save_ind_msg_v01 { 1154 u32 source; 1155 u32 total_size; 1156 u8 mem_seg_valid; 1157 u32 mem_seg_len; 1158 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1159 u8 file_name_valid; 1160 char file_name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 1161 }; 1162 #define WLFW_QDSS_TRACE_SAVE_IND_MSG_V01_MAX_MSG_LEN 921 1163 extern struct qmi_elem_info wlfw_qdss_trace_save_ind_msg_v01_ei[]; 1164 1165 struct wlfw_qdss_trace_data_req_msg_v01 { 1166 u32 seg_id; 1167 }; 1168 #define WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN 7 1169 extern struct qmi_elem_info wlfw_qdss_trace_data_req_msg_v01_ei[]; 1170 1171 struct wlfw_qdss_trace_data_resp_msg_v01 { 1172 struct qmi_response_type_v01 resp; 1173 u8 total_size_valid; 1174 u32 total_size; 1175 u8 seg_id_valid; 1176 u32 seg_id; 1177 u8 data_valid; 1178 u32 data_len; 1179 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1180 u8 end_valid; 1181 u8 end; 1182 }; 1183 #define WLFW_QDSS_TRACE_DATA_RESP_MSG_V01_MAX_MSG_LEN 6174 1184 extern struct qmi_elem_info wlfw_qdss_trace_data_resp_msg_v01_ei[]; 1185 1186 struct wlfw_qdss_trace_config_download_req_msg_v01 { 1187 u8 total_size_valid; 1188 u32 total_size; 1189 u8 seg_id_valid; 1190 u32 seg_id; 1191 u8 data_valid; 1192 u32 data_len; 1193 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1194 u8 end_valid; 1195 u8 end; 1196 }; 1197 #define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6167 1198 extern struct qmi_elem_info wlfw_qdss_trace_config_download_req_msg_v01_ei[]; 1199 1200 struct wlfw_qdss_trace_config_download_resp_msg_v01 { 1201 struct qmi_response_type_v01 resp; 1202 }; 1203 #define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 1204 extern struct qmi_elem_info wlfw_qdss_trace_config_download_resp_msg_v01_ei[]; 1205 1206 struct wlfw_qdss_trace_mode_req_msg_v01 { 1207 u8 mode_valid; 1208 enum wlfw_qdss_trace_mode_enum_v01 mode; 1209 u8 option_valid; 1210 u64 option; 1211 u8 hw_trc_disable_override_valid; 1212 enum wlfw_qmi_param_value_v01 hw_trc_disable_override; 1213 }; 1214 #define WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN 25 1215 extern struct qmi_elem_info wlfw_qdss_trace_mode_req_msg_v01_ei[]; 1216 1217 struct wlfw_qdss_trace_mode_resp_msg_v01 { 1218 struct qmi_response_type_v01 resp; 1219 }; 1220 #define WLFW_QDSS_TRACE_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 1221 extern struct qmi_elem_info wlfw_qdss_trace_mode_resp_msg_v01_ei[]; 1222 1223 struct wlfw_qdss_trace_free_ind_msg_v01 { 1224 u8 mem_seg_valid; 1225 u32 mem_seg_len; 1226 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1227 }; 1228 #define WLFW_QDSS_TRACE_FREE_IND_MSG_V01_MAX_MSG_LEN 888 1229 extern struct qmi_elem_info wlfw_qdss_trace_free_ind_msg_v01_ei[]; 1230 1231 struct wlfw_shutdown_req_msg_v01 { 1232 u8 shutdown_valid; 1233 u8 shutdown; 1234 }; 1235 #define WLFW_SHUTDOWN_REQ_MSG_V01_MAX_MSG_LEN 4 1236 extern struct qmi_elem_info wlfw_shutdown_req_msg_v01_ei[]; 1237 1238 struct wlfw_shutdown_resp_msg_v01 { 1239 struct qmi_response_type_v01 resp; 1240 }; 1241 #define WLFW_SHUTDOWN_RESP_MSG_V01_MAX_MSG_LEN 7 1242 extern struct qmi_elem_info wlfw_shutdown_resp_msg_v01_ei[]; 1243 1244 struct wlfw_antenna_switch_req_msg_v01 { 1245 char placeholder; 1246 }; 1247 #define WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN 0 1248 extern struct qmi_elem_info wlfw_antenna_switch_req_msg_v01_ei[]; 1249 1250 struct wlfw_antenna_switch_resp_msg_v01 { 1251 struct qmi_response_type_v01 resp; 1252 u8 antenna_valid; 1253 u64 antenna; 1254 }; 1255 #define WLFW_ANTENNA_SWITCH_RESP_MSG_V01_MAX_MSG_LEN 18 1256 extern struct qmi_elem_info wlfw_antenna_switch_resp_msg_v01_ei[]; 1257 1258 struct wlfw_antenna_grant_req_msg_v01 { 1259 u8 grant_valid; 1260 u64 grant; 1261 }; 1262 #define WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN 11 1263 extern struct qmi_elem_info wlfw_antenna_grant_req_msg_v01_ei[]; 1264 1265 struct wlfw_antenna_grant_resp_msg_v01 { 1266 struct qmi_response_type_v01 resp; 1267 }; 1268 #define WLFW_ANTENNA_GRANT_RESP_MSG_V01_MAX_MSG_LEN 7 1269 extern struct qmi_elem_info wlfw_antenna_grant_resp_msg_v01_ei[]; 1270 1271 struct wlfw_wfc_call_status_req_msg_v01 { 1272 u32 wfc_call_status_len; 1273 u8 wfc_call_status[QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01]; 1274 u8 wfc_call_active_valid; 1275 u8 wfc_call_active; 1276 u8 all_wfc_calls_held_valid; 1277 u8 all_wfc_calls_held; 1278 u8 is_wfc_emergency_valid; 1279 u8 is_wfc_emergency; 1280 u8 twt_ims_start_valid; 1281 u64 twt_ims_start; 1282 u8 twt_ims_int_valid; 1283 u16 twt_ims_int; 1284 u8 media_quality_valid; 1285 enum wlfw_wfc_media_quality_v01 media_quality; 1286 }; 1287 #define WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN 296 1288 extern struct qmi_elem_info wlfw_wfc_call_status_req_msg_v01_ei[]; 1289 1290 struct wlfw_wfc_call_status_resp_msg_v01 { 1291 struct qmi_response_type_v01 resp; 1292 }; 1293 #define WLFW_WFC_CALL_STATUS_RESP_MSG_V01_MAX_MSG_LEN 7 1294 extern struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[]; 1295 1296 struct wlfw_get_info_req_msg_v01 { 1297 u8 type; 1298 u32 data_len; 1299 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1300 }; 1301 #define WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN 6153 1302 extern struct qmi_elem_info wlfw_get_info_req_msg_v01_ei[]; 1303 1304 struct wlfw_get_info_resp_msg_v01 { 1305 struct qmi_response_type_v01 resp; 1306 }; 1307 #define WLFW_GET_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1308 extern struct qmi_elem_info wlfw_get_info_resp_msg_v01_ei[]; 1309 1310 struct wlfw_respond_get_info_ind_msg_v01 { 1311 u32 data_len; 1312 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1313 u8 type_valid; 1314 u8 type; 1315 u8 is_last_valid; 1316 u8 is_last; 1317 u8 seq_no_valid; 1318 u32 seq_no; 1319 }; 1320 #define WLFW_RESPOND_GET_INFO_IND_MSG_V01_MAX_MSG_LEN 6164 1321 extern struct qmi_elem_info wlfw_respond_get_info_ind_msg_v01_ei[]; 1322 1323 struct wlfw_device_info_req_msg_v01 { 1324 char placeholder; 1325 }; 1326 #define WLFW_DEVICE_INFO_REQ_MSG_V01_MAX_MSG_LEN 0 1327 extern struct qmi_elem_info wlfw_device_info_req_msg_v01_ei[]; 1328 1329 struct wlfw_device_info_resp_msg_v01 { 1330 struct qmi_response_type_v01 resp; 1331 u8 bar_addr_valid; 1332 u64 bar_addr; 1333 u8 bar_size_valid; 1334 u32 bar_size; 1335 u8 mhi_state_info_addr_valid; 1336 u64 mhi_state_info_addr; 1337 u8 mhi_state_info_size_valid; 1338 u32 mhi_state_info_size; 1339 }; 1340 #define WLFW_DEVICE_INFO_RESP_MSG_V01_MAX_MSG_LEN 43 1341 extern struct qmi_elem_info wlfw_device_info_resp_msg_v01_ei[]; 1342 1343 struct wlfw_m3_dump_upload_req_ind_msg_v01 { 1344 u32 pdev_id; 1345 u64 addr; 1346 u64 size; 1347 }; 1348 #define WLFW_M3_DUMP_UPLOAD_REQ_IND_MSG_V01_MAX_MSG_LEN 29 1349 extern struct qmi_elem_info wlfw_m3_dump_upload_req_ind_msg_v01_ei[]; 1350 1351 struct wlfw_m3_dump_upload_done_req_msg_v01 { 1352 u32 pdev_id; 1353 u32 status; 1354 }; 1355 #define WLFW_M3_DUMP_UPLOAD_DONE_REQ_MSG_V01_MAX_MSG_LEN 14 1356 extern struct qmi_elem_info wlfw_m3_dump_upload_done_req_msg_v01_ei[]; 1357 1358 struct wlfw_m3_dump_upload_done_resp_msg_v01 { 1359 struct qmi_response_type_v01 resp; 1360 }; 1361 #define WLFW_M3_DUMP_UPLOAD_DONE_RESP_MSG_V01_MAX_MSG_LEN 7 1362 extern struct qmi_elem_info wlfw_m3_dump_upload_done_resp_msg_v01_ei[]; 1363 1364 struct wlfw_soc_wake_req_msg_v01 { 1365 u8 wake_valid; 1366 enum wlfw_soc_wake_enum_v01 wake; 1367 }; 1368 #define WLFW_SOC_WAKE_REQ_MSG_V01_MAX_MSG_LEN 7 1369 extern struct qmi_elem_info wlfw_soc_wake_req_msg_v01_ei[]; 1370 1371 struct wlfw_soc_wake_resp_msg_v01 { 1372 struct qmi_response_type_v01 resp; 1373 }; 1374 #define WLFW_SOC_WAKE_RESP_MSG_V01_MAX_MSG_LEN 7 1375 extern struct qmi_elem_info wlfw_soc_wake_resp_msg_v01_ei[]; 1376 1377 struct wlfw_power_save_req_msg_v01 { 1378 u8 power_save_mode_valid; 1379 enum wlfw_power_save_mode_v01 power_save_mode; 1380 }; 1381 #define WLFW_POWER_SAVE_REQ_MSG_V01_MAX_MSG_LEN 7 1382 extern struct qmi_elem_info wlfw_power_save_req_msg_v01_ei[]; 1383 1384 struct wlfw_power_save_resp_msg_v01 { 1385 struct qmi_response_type_v01 resp; 1386 }; 1387 #define WLFW_POWER_SAVE_RESP_MSG_V01_MAX_MSG_LEN 7 1388 extern struct qmi_elem_info wlfw_power_save_resp_msg_v01_ei[]; 1389 1390 struct wlfw_wfc_call_twt_config_ind_msg_v01 { 1391 u8 twt_sta_start_valid; 1392 u64 twt_sta_start; 1393 u8 twt_sta_int_valid; 1394 u16 twt_sta_int; 1395 u8 twt_sta_upo_valid; 1396 u16 twt_sta_upo; 1397 u8 twt_sta_sp_valid; 1398 u16 twt_sta_sp; 1399 u8 twt_sta_dl_valid; 1400 u16 twt_sta_dl; 1401 u8 twt_sta_config_changed_valid; 1402 u8 twt_sta_config_changed; 1403 }; 1404 #define WLFW_WFC_CALL_TWT_CONFIG_IND_MSG_V01_MAX_MSG_LEN 35 1405 extern struct qmi_elem_info wlfw_wfc_call_twt_config_ind_msg_v01_ei[]; 1406 1407 struct wlfw_qdss_mem_ready_ind_msg_v01 { 1408 char placeholder; 1409 }; 1410 #define WLFW_QDSS_MEM_READY_IND_MSG_V01_MAX_MSG_LEN 0 1411 extern struct qmi_elem_info wlfw_qdss_mem_ready_ind_msg_v01_ei[]; 1412 1413 struct wlfw_pcie_gen_switch_req_msg_v01 { 1414 enum wlfw_pcie_gen_speed_v01 pcie_speed; 1415 }; 1416 #define WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN 7 1417 extern struct qmi_elem_info wlfw_pcie_gen_switch_req_msg_v01_ei[]; 1418 1419 struct wlfw_pcie_gen_switch_resp_msg_v01 { 1420 struct qmi_response_type_v01 resp; 1421 }; 1422 #define WLFW_PCIE_GEN_SWITCH_RESP_MSG_V01_MAX_MSG_LEN 7 1423 extern struct qmi_elem_info wlfw_pcie_gen_switch_resp_msg_v01_ei[]; 1424 1425 struct wlfw_m3_dump_upload_segments_req_ind_msg_v01 { 1426 u32 pdev_id; 1427 u32 no_of_valid_segments; 1428 struct wlfw_m3_segment_info_s_v01 m3_segment[QMI_WLFW_MAX_M3_SEGMENTS_SIZE_V01]; 1429 }; 1430 #define WLFW_M3_DUMP_UPLOAD_SEGMENTS_REQ_IND_MSG_V01_MAX_MSG_LEN 387 1431 extern struct qmi_elem_info wlfw_m3_dump_upload_segments_req_ind_msg_v01_ei[]; 1432 1433 struct wlfw_subsys_restart_level_req_msg_v01 { 1434 u8 restart_level_type_valid; 1435 u8 restart_level_type; 1436 }; 1437 #define WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 4 1438 extern struct qmi_elem_info wlfw_subsys_restart_level_req_msg_v01_ei[]; 1439 1440 struct wlfw_subsys_restart_level_resp_msg_v01 { 1441 struct qmi_response_type_v01 resp; 1442 }; 1443 #define WLFW_SUBSYS_RESTART_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 7 1444 extern struct qmi_elem_info wlfw_subsys_restart_level_resp_msg_v01_ei[]; 1445 1446 struct wlfw_ini_file_download_req_msg_v01 { 1447 u8 file_type_valid; 1448 enum wlfw_ini_file_type_v01 file_type; 1449 u8 total_size_valid; 1450 u32 total_size; 1451 u8 seg_id_valid; 1452 u32 seg_id; 1453 u8 data_valid; 1454 u32 data_len; 1455 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1456 u8 end_valid; 1457 u8 end; 1458 }; 1459 #define WLFW_INI_FILE_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6174 1460 extern struct qmi_elem_info wlfw_ini_file_download_req_msg_v01_ei[]; 1461 1462 struct wlfw_ini_file_download_resp_msg_v01 { 1463 struct qmi_response_type_v01 resp; 1464 }; 1465 #define WLFW_INI_FILE_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 1466 extern struct qmi_elem_info wlfw_ini_file_download_resp_msg_v01_ei[]; 1467 1468 struct wlfw_phy_cap_req_msg_v01 { 1469 char placeholder; 1470 }; 1471 #define WLFW_PHY_CAP_REQ_MSG_V01_MAX_MSG_LEN 0 1472 extern struct qmi_elem_info wlfw_phy_cap_req_msg_v01_ei[]; 1473 1474 struct wlfw_phy_cap_resp_msg_v01 { 1475 struct qmi_response_type_v01 resp; 1476 u8 num_phy_valid; 1477 u8 num_phy; 1478 u8 board_id_valid; 1479 u32 board_id; 1480 u8 mlo_cap_v2_support_valid; 1481 u32 mlo_cap_v2_support; 1482 }; 1483 #define WLFW_PHY_CAP_RESP_MSG_V01_MAX_MSG_LEN 25 1484 extern struct qmi_elem_info wlfw_phy_cap_resp_msg_v01_ei[]; 1485 1486 struct wlfw_wlan_hw_init_cfg_req_msg_v01 { 1487 u8 rf_subtype_valid; 1488 enum wlfw_wlan_rf_subtype_v01 rf_subtype; 1489 }; 1490 #define WLFW_WLAN_HW_INIT_CFG_REQ_MSG_V01_MAX_MSG_LEN 7 1491 extern struct qmi_elem_info wlfw_wlan_hw_init_cfg_req_msg_v01_ei[]; 1492 1493 struct wlfw_wlan_hw_init_cfg_resp_msg_v01 { 1494 struct qmi_response_type_v01 resp; 1495 }; 1496 #define WLFW_WLAN_HW_INIT_CFG_RESP_MSG_V01_MAX_MSG_LEN 7 1497 extern struct qmi_elem_info wlfw_wlan_hw_init_cfg_resp_msg_v01_ei[]; 1498 1499 struct wlfw_pcie_link_ctrl_req_msg_v01 { 1500 enum wlfw_pcie_link_state_enum_v01 link_state_req; 1501 }; 1502 #define WLFW_PCIE_LINK_CTRL_REQ_MSG_V01_MAX_MSG_LEN 7 1503 extern struct qmi_elem_info wlfw_pcie_link_ctrl_req_msg_v01_ei[]; 1504 1505 struct wlfw_pcie_link_ctrl_resp_msg_v01 { 1506 struct qmi_response_type_v01 resp; 1507 }; 1508 #define WLFW_PCIE_LINK_CTRL_RESP_MSG_V01_MAX_MSG_LEN 7 1509 extern struct qmi_elem_info wlfw_pcie_link_ctrl_resp_msg_v01_ei[]; 1510 1511 struct wlfw_aux_uc_info_req_msg_v01 { 1512 u64 addr; 1513 u32 size; 1514 }; 1515 #define WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 1516 extern struct qmi_elem_info wlfw_aux_uc_info_req_msg_v01_ei[]; 1517 1518 struct wlfw_aux_uc_info_resp_msg_v01 { 1519 struct qmi_response_type_v01 resp; 1520 }; 1521 #define WLFW_AUX_UC_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1522 extern struct qmi_elem_info wlfw_aux_uc_info_resp_msg_v01_ei[]; 1523 1524 struct wlfw_tme_lite_info_req_msg_v01 { 1525 enum wlfw_tme_lite_file_type_v01 tme_file; 1526 u64 addr; 1527 u32 size; 1528 }; 1529 #define WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN 25 1530 extern struct qmi_elem_info wlfw_tme_lite_info_req_msg_v01_ei[]; 1531 1532 struct wlfw_tme_lite_info_resp_msg_v01 { 1533 struct qmi_response_type_v01 resp; 1534 }; 1535 #define WLFW_TME_LITE_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1536 extern struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[]; 1537 1538 struct wlfw_fw_ssr_ind_msg_v01 { 1539 enum wlfw_fw_ssr_reason_v01 reason_code; 1540 }; 1541 #define WLFW_FW_SSR_IND_MSG_V01_MAX_MSG_LEN 7 1542 extern struct qmi_elem_info wlfw_fw_ssr_ind_msg_v01_ei[]; 1543 1544 struct wlfw_bmps_ctrl_req_msg_v01 { 1545 enum wlfw_bmps_state_enum_v01 bmps_state; 1546 }; 1547 #define WLFW_BMPS_CTRL_REQ_MSG_V01_MAX_MSG_LEN 7 1548 extern struct qmi_elem_info wlfw_bmps_ctrl_req_msg_v01_ei[]; 1549 1550 struct wlfw_bmps_ctrl_resp_msg_v01 { 1551 struct qmi_response_type_v01 resp; 1552 }; 1553 #define WLFW_BMPS_CTRL_RESP_MSG_V01_MAX_MSG_LEN 7 1554 extern struct qmi_elem_info wlfw_bmps_ctrl_resp_msg_v01_ei[]; 1555 1556 struct wlfw_lpass_ssr_req_msg_v01 { 1557 enum wlfw_lpass_ssr_reason_v01 reason_code; 1558 }; 1559 #define WLFW_LPASS_SSR_REQ_MSG_V01_MAX_MSG_LEN 7 1560 extern struct qmi_elem_info wlfw_lpass_ssr_req_msg_v01_ei[]; 1561 1562 struct wlfw_lpass_ssr_resp_msg_v01 { 1563 struct qmi_response_type_v01 resp; 1564 }; 1565 #define WLFW_LPASS_SSR_RESP_MSG_V01_MAX_MSG_LEN 7 1566 extern struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[]; 1567 1568 #endif 1569