1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _CNSS_REG_H 8 #define _CNSS_REG_H 9 10 #define QCA6390_PCIE_REMAP_BAR_CTRL_OFFSET 0x310C 11 #define PEACH_PCIE_REMAP_BAR_CTRL_OFFSET 0x3278 12 13 #define QCA6390_CE_SRC_RING_REG_BASE 0xA00000 14 #define QCA6390_CE_DST_RING_REG_BASE 0xA01000 15 #define QCA6390_CE_COMMON_REG_BASE 0xA18000 16 17 #define QCA6490_CE_SRC_RING_REG_BASE 0x1B80000 18 #define QCA6490_CE_DST_RING_REG_BASE 0x1B81000 19 #define QCA6490_CE_COMMON_REG_BASE 0x1B98000 20 21 #define CE_SRC_RING_BASE_LSB_OFFSET 0x0 22 #define CE_SRC_RING_BASE_MSB_OFFSET 0x4 23 #define CE_SRC_RING_ID_OFFSET 0x8 24 #define CE_SRC_RING_MISC_OFFSET 0x10 25 #define CE_SRC_CTRL_OFFSET 0x58 26 #define CE_SRC_R0_CE_CH_SRC_IS_OFFSET 0x5C 27 #define CE_SRC_RING_HP_OFFSET 0x400 28 #define CE_SRC_RING_TP_OFFSET 0x404 29 30 #define CE_DEST_RING_BASE_LSB_OFFSET 0x0 31 #define CE_DEST_RING_BASE_MSB_OFFSET 0x4 32 #define CE_DEST_RING_ID_OFFSET 0x8 33 #define CE_DEST_RING_MISC_OFFSET 0x10 34 #define CE_DEST_CTRL_OFFSET 0xB0 35 #define CE_CH_DST_IS_OFFSET 0xB4 36 #define CE_CH_DEST_CTRL2_OFFSET 0xB8 37 #define CE_DEST_RING_HP_OFFSET 0x400 38 #define CE_DEST_RING_TP_OFFSET 0x404 39 40 #define CE_STATUS_RING_BASE_LSB_OFFSET 0x58 41 #define CE_STATUS_RING_BASE_MSB_OFFSET 0x5C 42 #define CE_STATUS_RING_ID_OFFSET 0x60 43 #define CE_STATUS_RING_MISC_OFFSET 0x68 44 #define CE_STATUS_RING_HP_OFFSET 0x408 45 #define CE_STATUS_RING_TP_OFFSET 0x40C 46 47 #define CE_COMMON_GXI_ERR_INTS 0x14 48 #define CE_COMMON_GXI_ERR_STATS 0x18 49 #define CE_COMMON_GXI_WDOG_STATUS 0x2C 50 #define CE_COMMON_TARGET_IE_0 0x48 51 #define CE_COMMON_TARGET_IE_1 0x4C 52 53 #define CE_REG_INTERVAL 0x2000 54 55 #define SHADOW_REG_COUNT 36 56 #define SHADOW_REG_LEN_BYTES 4 57 #define PCIE_SHADOW_REG_VALUE_0 0x8FC 58 #define PCIE_SHADOW_REG_VALUE_1 0x900 59 #define PCIE_SHADOW_REG_VALUE_34 0x984 60 #define PCIE_SHADOW_REG_VALUE_35 0x988 61 62 #define SHADOW_REG_INTER_COUNT 43 63 #define PCIE_SHADOW_REG_INTER_0 0x1E05000 64 65 #define PCIE_MHI_TIME_LOW 0xA28 66 #define PCIE_MHI_TIME_HIGH 0xA2C 67 68 #define QDSS_APB_DEC_CSR_BASE 0x1C01000 69 70 #define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C 71 #define QDSS_APB_DEC_CSR_PRESERVEETF_OFFSET 0x70 72 #define QDSS_APB_DEC_CSR_PRESERVEETR0_OFFSET 0x74 73 #define QDSS_APB_DEC_CSR_PRESERVEETR1_OFFSET 0x78 74 75 #define MAX_UNWINDOWED_ADDRESS 0x80000 76 #define WINDOW_ENABLE_BIT 0x40000000 77 #define WINDOW_SHIFT 19 78 #define WINDOW_VALUE_MASK 0x3F 79 #define WINDOW_START MAX_UNWINDOWED_ADDRESS 80 #define WINDOW_RANGE_MASK 0x7FFFF 81 82 #define TIME_SYNC_ENABLE 0x80000000 83 #define TIME_SYNC_CLEAR 0x0 84 85 #define QCA6390_DEBUG_PBL_LOG_SRAM_START 0x01403D58 86 #define QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE 80 87 #define QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE 44 88 89 #define QCA6490_DEBUG_PBL_LOG_SRAM_START 0x01403DA0 90 #define QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40 91 #define QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48 92 93 #define KIWI_DEBUG_PBL_LOG_SRAM_START 0x01403D98 94 #define KIWI_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40 95 #define KIWI_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48 96 #define KIWI_PBL_BOOTSTRAP_STATUS 0x01A10008 97 98 #define MANGO_DEBUG_PBL_LOG_SRAM_START 0x01403D98 99 #define MANGO_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40 100 #define MANGO_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48 101 #define MANGO_PBL_BOOTSTRAP_STATUS 0x01A10008 102 103 #define PEACH_DEBUG_PBL_LOG_SRAM_START 0x01403640 104 #define PEACH_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40 105 #define PEACH_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48 106 #define PEACH_PBL_BOOTSTRAP_STATUS 0x01A10008 107 108 #define TCSR_PBL_LOGGING_REG 0x01B000F8 109 #define PCIE_BHI_ERRDBG2_REG 0x01E0E238 110 #define PCIE_BHI_ERRDBG3_REG 0x01E0E23C 111 #define PBL_WLAN_BOOT_CFG 0x01E22B34 112 #define PBL_BOOTSTRAP_STATUS 0x01910008 113 #define SRAM_START 0x01400000 114 #define SRAM_END 0x01800000 115 #define SRAM_DUMP_SIZE 0x400000 116 117 #define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG 0x01E04234 118 #define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL 0xDEAD1234 119 #define PEACH_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG 0x01E04334 120 #define PEACH_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL 0xDEAD1334 121 #define QCA6390_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG 0x01E03140 122 #define PEACH_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG 0x01E03284 123 #define QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG 0x1E04054 124 #define QCA6390_PCIE_SOC_PCIE_WRAP_INTR_STATUS_SOC_PCIE_REG 0x1E04058 125 #define QCA6390_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG 0x01E05090 126 #define PEACH_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG 0x01E01100 127 #define QCA6390_PCIE_SOC_PCIE_REG_PCIE_SCRATCH_2_SOC_PCIE_REG 0x01E0405C 128 #define QCA6390_PCIE_PCIE_PARF_LTSSM 0x01E081B0 129 #define QCA6390_PCIE_PCIE_PARF_PM_STTS 0x01E08024 130 #define QCA6390_PCIE_PCIE_PARF_PM_STTS_1 0x01E08028 131 #define QCA6390_PCIE_PCIE_PARF_INT_STATUS 0x01E08220 132 #define QCA6390_PCIE_PCIE_INT_ALL_STATUS 0x01E08224 133 #define QCA6390_PCIE_PCIE_INT_ALL_MASK 0x01E0822C 134 #define QCA6390_PCIE_PCIE_PARF_BDF_TO_SID_CFG 0x01E0AC00 135 #define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4 0x01E08530 136 #define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_3 0x01E0852c 137 #define QCA6390_PCIE_PCIE_PARF_MHI_CLOCK_RESET_CTRL 0x01E08174 138 #define QCA6390_PCIE_PCIE_PARF_MHI_BASE_ADDR_LOWER 0x01E08178 139 #define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS 0x01E084D0 140 #define QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_CFG 0x01E084d4 141 #define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0x01E0ec88 142 #define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB 0x01E0ec08 143 #define QCA6390_PCIE_PCIE_CORE_CONFIG 0x01E08640 144 #define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L2 0x01E0EC04 145 #define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1 0x01E0EC0C 146 #define QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0x01E0EC84 147 #define QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH 0x01E030C8 148 #define QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW 0x01E030CC 149 #define QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH 0x01E0313C 150 #define QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW 0x01E03140 151 #define PEACH_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH 0x01E03214 152 #define PEACH_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW 0x01E03218 153 #define PEACH_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH 0x01E03280 154 #define PEACH_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW 0x01E03284 155 #define QCA6390_PCIE_PCIE_BHI_EXECENV_REG 0x01E0E228 156 157 #define QCA6390_GCC_DEBUG_CLK_CTL 0x001E4025C 158 159 #define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_PLL_MODE 0x00D00200 160 #define QCA6390_WCSS_WFSS_PMM_WFSS_PMM_R0_PMM_CTRL 0x00B60164 161 #define QCA6390_WCSS_PMM_TOP_PMU_CX_CSR 0x00B70080 162 #define QCA6390_WCSS_PMM_TOP_AON_INT_RAW_STAT 0x00B700E0 163 #define QCA6390_WCSS_PMM_TOP_AON_INT_EN 0x00B700D0 164 #define QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_STS 0x00B70020 165 #define QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_CTL 0x00B7001C 166 #define QCA6390_WCSS_PMM_TOP_TESTBUS_STS 0x00B70028 167 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG 0x00DB0008 168 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG_MSK 0x20 169 #define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL 0x00D02000 170 #define QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE 0x00D02004 171 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_STS 0x00DB000C 172 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_CTL 0x00DB0030 173 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_0 0x00DB0400 174 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_9 0x00DB0424 175 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS0 0x00D90380 176 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS1 0x00D90384 177 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS2 0x00D90388 178 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS3 0x00D9038C 179 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS4 0x00D90390 180 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS5 0x00D90394 181 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS6 0x00D90398 182 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE0 0x00D90100 183 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE1 0x00D90104 184 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE2 0x00D90108 185 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE3 0x00D9010C 186 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE4 0x00D90110 187 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE5 0x00D90114 188 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE6 0x00D90118 189 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING0 0x00D90500 190 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING1 0x00D90504 191 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING2 0x00D90508 192 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING3 0x00D9050C 193 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING4 0x00D90510 194 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING5 0x00D90514 195 #define QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING6 0x00D90518 196 #define QCA6390_WCSS_CC_WCSS_UMAC_NOC_CBCR 0x00C3029C 197 #define QCA6390_WCSS_CC_WCSS_UMAC_AHB_CBCR 0x00C302BC 198 #define QCA6390_WCSS_CC_WCSS_UMAC_GDSCR 0x00C30298 199 #define QCA6390_WCSS_CC_WCSS_WLAN1_GDSCR 0x00C300C4 200 #define QCA6390_WCSS_CC_WCSS_WLAN2_GDSCR 0x00C30138 201 #define QCA6390_WCSS_PMM_TOP_PMM_INT_CLR 0x00B70168 202 #define QCA6390_WCSS_PMM_TOP_AON_INT_STICKY_EN 0x00B700D8 203 204 #define QCA6390_TLMM_GPIO_IN_OUT57 0x01839004 205 #define QCA6390_TLMM_GPIO_INTR_CFG57 0x01839008 206 #define QCA6390_TLMM_GPIO_INTR_STATUS57 0x0183900C 207 #define QCA6390_TLMM_GPIO_IN_OUT59 0x0183b004 208 #define QCA6390_TLMM_GPIO_INTR_CFG59 0x0183b008 209 #define QCA6390_TLMM_GPIO_INTR_STATUS59 0x0183b00C 210 211 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2 0x00B6017C 212 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_STATUS_REG2 0x00B60190 213 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN2_CFG_REG1 0x00B6018C 214 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1 0x00B60178 215 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1 0x00B600B0 216 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 0x00B60044 217 218 #define WLAON_SOC_POWER_CTRL 0x01F80000 219 #define WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004 220 #define WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008 221 #define WLAON_SW_COLD_RESET 0x1F8000C 222 #define WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C 223 #define WLAON_GDSC_DELAY_SETTING 0x1F80024 224 #define WLAON_GDSC_DELAY_SETTING2 0x1F80028 225 #define WLAON_WL_PWR_STATUS_REG 0x1F8002C 226 #define WLAON_WL_AON_DBG_CFG_REG 0x1F80030 227 #define WLAON_WL_AON_DBG_ENABLE_GRP0_REG 0x1F80034 228 #define WLAON_WL_AON_DBG_ENABLE_GRP1_REG 0x1F80038 229 #define WLAON_WL_AON_APM_CFG_CTRL0 0x1F80040 230 #define WLAON_WL_AON_APM_CFG_CTRL1 0x1F80044 231 #define WLAON_WL_AON_APM_CFG_CTRL2 0x1F80048 232 #define WLAON_WL_AON_APM_CFG_CTRL3 0x1F8004C 233 #define WLAON_WL_AON_APM_CFG_CTRL4 0x1F80050 234 #define WLAON_WL_AON_APM_CFG_CTRL5 0x1F80054 235 #define WLAON_WL_AON_APM_CFG_CTRL5_1 0x1F80058 236 #define WLAON_WL_AON_APM_CFG_CTRL6 0x1F8005C 237 #define WLAON_WL_AON_APM_CFG_CTRL6_1 0x1F80060 238 #define WLAON_WL_AON_APM_CFG_CTRL7 0x1F80064 239 #define WLAON_WL_AON_APM_CFG_CTRL8 0x1F80068 240 #define WLAON_WL_AON_APM_CFG_CTRL8_1 0x1F8006C 241 #define WLAON_WL_AON_APM_CFG_CTRL9 0x1F80070 242 #define WLAON_WL_AON_APM_CFG_CTRL9_1 0x1F80074 243 #define WLAON_WL_AON_APM_CFG_CTRL10 0x1F80078 244 #define WLAON_WL_AON_APM_CFG_CTRL11 0x1F8007C 245 #define WLAON_WL_AON_APM_CFG_CTRL12 0x1F80080 246 #define WLAON_WL_AON_APM_OVERRIDE_REG 0x1F800B0 247 #define WLAON_WL_AON_CXPC_REG 0x1F800B4 248 #define WLAON_WL_AON_APM_STATUS0 0x1F800C0 249 #define WLAON_WL_AON_APM_STATUS1 0x1F800C4 250 #define WLAON_WL_AON_APM_STATUS2 0x1F800C8 251 #define WLAON_WL_AON_APM_STATUS3 0x1F800CC 252 #define WLAON_WL_AON_APM_STATUS4 0x1F800D0 253 #define WLAON_WL_AON_APM_STATUS5 0x1F800D4 254 #define WLAON_WL_AON_APM_STATUS6 0x1F800D8 255 #define WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100 256 #define WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108 257 #define WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C 258 #define WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118 259 #define WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C 260 #define WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120 261 #define WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0 262 #define WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4 263 #define WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8 264 #define WLAON_RTC_CLK_CAL_CTRL1 0x1F80200 265 #define WLAON_RTC_CLK_CAL_CTRL2 0x1F80204 266 #define WLAON_RTC_CLK_CAL_CTRL3 0x1F80208 267 #define WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C 268 #define WLAON_RTC_CLK_CAL_CTRL5 0x1F80210 269 #define WLAON_RTC_CLK_CAL_CTRL6 0x1F80214 270 #define WLAON_RTC_CLK_CAL_CTRL7 0x1F80218 271 #define WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C 272 #define WLAON_RTC_CLK_CAL_CTRL9 0x1F80220 273 #define WLAON_WCSSAON_CONFIG_REG 0x1F80300 274 #define WLAON_WLAN_OEM_DEBUG_REG 0x1F80304 275 #define WLAON_WLAN_RAM_DUMP_REG 0x1F80308 276 #define WLAON_QDSS_WCSS_REG 0x1F8030C 277 #define WLAON_QDSS_WCSS_ACK 0x1F80310 278 #define WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314 279 #define WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318 280 #define WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C 281 #define QFPROM_PWR_CTRL_VDD4BLOW_SW_EN_MASK 0x4 282 #define QFPROM_PWR_CTRL_SHUTDOWN_EN_MASK 0x1 283 #define WLAON_DLY_CONFIG 0x1F80400 284 #define WLAON_WLAON_Q6_IRQ_REG 0x1F80404 285 #define WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408 286 #define WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C 287 #define WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410 288 #define WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414 289 #define WLAON_Q6_COOKIE_BIT 0x1F80500 290 #define WLAON_WARM_SW_ENTRY 0x1F80504 291 #define WLAON_RESET_DBG_SW_ENTRY 0x1F80508 292 #define WLAON_WL_PMUNOC_CFG_REG 0x1F8050C 293 #define WLAON_RESET_CAUSE_CFG_REG 0x1F80510 294 #define WLAON_SOC_RESET_CAUSE_SHADOW_REG 0x1F80608 295 #define WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514 296 #define WLAON_DEBUG 0x1F80600 297 #define WLAON_SOC_PARAMETERS 0x1F80604 298 #define WLAON_WLPM_SIGNAL 0x1F80608 299 #define WLAON_SOC_RESET_CAUSE_REG 0x1F8060C 300 #define WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610 301 #define WLAON_PBL_STACK_CANARY 0x1F80614 302 #define WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618 303 #define WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C 304 #define WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620 305 #define WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624 306 #define WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628 307 #define WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C 308 #define WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630 309 #define WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634 310 #define WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638 311 #define WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C 312 #define WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640 313 #define WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644 314 #define WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648 315 #define WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C 316 #define WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650 317 #define WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654 318 #define WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658 319 #define WLAON_MEM_CNT_SEL_REG 0x1F8065C 320 #define WLAON_MEM_NO_EXTBHS_REG 0x1F80660 321 #define WLAON_MEM_DEBUG_REG 0x1F80664 322 #define WLAON_MEM_DEBUG_BUS_REG 0x1F80668 323 #define WLAON_MEM_REDUN_CFG_REG 0x1F8066C 324 #define WLAON_WL_AON_SPARE2 0x1F80670 325 #define WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680 326 #define WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690 327 #define WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0 328 #define WLAON_WLPM_CHICKEN_BITS 0x1F806A4 329 #define WLAON_PCIE_PHY_PWR_REG 0x1F806A8 330 #define WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC 331 #define WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0 332 #define WLAON_POWERCTRL_PMU_REG 0x1F806B4 333 #define WLAON_POWERCTRL_MEM_REG 0x1F806B8 334 #define WLAON_PCIE_PWR_CTRL_REG 0x01F806BC 335 #define WLAON_SOC_PWR_PROFILE_REG 0x1F806C0 336 #define WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4 337 #define WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8 338 #define WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC 339 #define WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0 340 #define WLAON_MEM_SVS_CFG_REG 0x1F806D4 341 #define WLAON_CMN_AON_MISC_REG 0x1F806D8 342 #define WLAON_INTR_STATUS 0x1F80700 343 #define WLAON_INTR_ENABLE 0x1F807040 344 #define WLAON_NOC_DBG_BUS_SEL_REG 0x1F80708 345 #define WLAON_NOC_DBG_BUS_REG 0x1F8070C 346 #define WLAON_WL_CTRL_MISC_REG 0x1F80710 347 #define WLAON_DBG_STATUS0 0x1F80720 348 #define WLAON_DBG_STATUS1 0x1F80724 349 #define WLAON_TIMERSYNC_OFFSET_L 0x1F80730 350 #define WLAON_TIMERSYNC_OFFSET_H 0x1F80734 351 #define WLAON_PMU_LDO_SETTLE_REG 0x1F80740 352 353 #define QCA6390_SYSPM_SYSPM_PWR_STATUS 0x1F82000 354 #define QCA6390_SYSPM_DBG_BTFM_AON_REG 0x1F82004 355 #define QCA6390_SYSPM_DBG_BUS_SEL_REG 0x1F82008 356 #define QCA6390_SYSPM_WCSSAON_SR_STATUS 0x1F8200C 357 358 /* PCIE SOC scratch registers, address same for QCA6390 & QCA6490*/ 359 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040 360 #define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044 361 #define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C 362 363 /* PCIE BHIE DEBUG registers */ 364 #define PCIE_PCIE_BHIE_DEBUG_0 0x1E0E1C0 365 #define PCIE_PCIE_BHIE_DEBUG_1 0x1E0E1C4 366 #define PCIE_PCIE_BHIE_DEBUG_2 0x1E0E1C8 367 #define PCIE_PCIE_BHIE_DEBUG_3 0x1E0E1CC 368 #define PCIE_PCIE_BHIE_DEBUG_4 0x1E0E1D0 369 #define PCIE_PCIE_BHIE_DEBUG_5 0x1E0E1D4 370 #define PCIE_PCIE_BHIE_DEBUG_6 0x1E0E1D8 371 #define PCIE_PCIE_BHIE_DEBUG_7 0x1E0E1DC 372 #define PCIE_PCIE_BHIE_DEBUG_8 0x1E0E1E0 373 #define PCIE_PCIE_BHIE_DEBUG_9 0x1E0E1E4 374 #define PCIE_PCIE_BHIE_DEBUG_10 0x1E0E1E8 375 376 #define GCC_GCC_SPARE_REG_1 0x1E40310 377 #define GCC_PRE_ARES_DEBUG_TIMER_VAL 0x1E40270 378 379 #define QCN7605_WINDOW_ENABLE_BIT 0x80000000 380 #endif 381