1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _CNSS_PCI_H 8 #define _CNSS_PCI_H 9 10 #include <linux/cma.h> 11 #include <linux/iommu.h> 12 #include <linux/mhi.h> 13 #if IS_ENABLED(CONFIG_MHI_BUS_MISC) 14 #include <linux/mhi_misc.h> 15 #endif 16 #if IS_ENABLED(CONFIG_PCI_MSM) 17 #include <linux/msm_pcie.h> 18 #endif 19 #include <linux/of_reserved_mem.h> 20 #include <linux/pci.h> 21 22 #include "main.h" 23 24 #define PM_OPTIONS_DEFAULT 0 25 #define PCI_LINK_DOWN 0 26 27 #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV 28 #define LINK_TRAINING_RETRY_MAX_TIMES 2 29 #else 30 #define LINK_TRAINING_RETRY_MAX_TIMES 3 31 #endif 32 33 #define LINK_TRAINING_RETRY_DELAY_MS 500 34 #define MSI_USERS 4 35 36 enum cnss_mhi_state { 37 CNSS_MHI_INIT, 38 CNSS_MHI_DEINIT, 39 CNSS_MHI_POWER_ON, 40 CNSS_MHI_POWERING_OFF, 41 CNSS_MHI_POWER_OFF, 42 CNSS_MHI_FORCE_POWER_OFF, 43 CNSS_MHI_SUSPEND, 44 CNSS_MHI_RESUME, 45 CNSS_MHI_TRIGGER_RDDM, 46 CNSS_MHI_RDDM, 47 CNSS_MHI_RDDM_DONE, 48 }; 49 50 enum pci_link_status { 51 PCI_GEN1, 52 PCI_GEN2, 53 PCI_DEF, 54 }; 55 56 enum cnss_rtpm_id { 57 RTPM_ID_CNSS, 58 RTPM_ID_MHI, 59 RTPM_ID_MAX, 60 }; 61 62 enum cnss_pci_reg_dev_mask { 63 REG_MASK_QCA6390, 64 REG_MASK_QCA6490, 65 REG_MASK_KIWI, 66 REG_MASK_MANGO, 67 REG_MASK_PEACH, 68 }; 69 70 struct cnss_msi_user { 71 char *name; 72 int num_vectors; 73 u32 base_vector; 74 }; 75 76 struct cnss_msi_config { 77 int total_vectors; 78 int total_users; 79 struct cnss_msi_user *users; 80 }; 81 82 struct cnss_pci_reg { 83 char *name; 84 u32 offset; 85 }; 86 87 struct cnss_pci_debug_reg { 88 u32 offset; 89 u32 val; 90 }; 91 92 struct cnss_misc_reg { 93 unsigned long dev_mask; 94 u8 wr; 95 u32 offset; 96 u32 val; 97 }; 98 99 struct cnss_pm_stats { 100 atomic_t runtime_get; 101 atomic_t runtime_put; 102 atomic_t runtime_get_id[RTPM_ID_MAX]; 103 atomic_t runtime_put_id[RTPM_ID_MAX]; 104 u64 runtime_get_timestamp_id[RTPM_ID_MAX]; 105 u64 runtime_put_timestamp_id[RTPM_ID_MAX]; 106 }; 107 108 struct cnss_print_optimize { 109 int msi_log_chk[MSI_USERS]; 110 int msi_addr_chk; 111 }; 112 113 struct cnss_pci_data { 114 struct pci_dev *pci_dev; 115 struct cnss_plat_data *plat_priv; 116 const struct pci_device_id *pci_device_id; 117 u32 device_id; 118 u16 revision_id; 119 u64 dma_bit_mask; 120 struct cnss_wlan_driver *driver_ops; 121 u8 pci_link_state; 122 u8 pci_link_down_ind; 123 struct pci_saved_state *saved_state; 124 struct pci_saved_state *default_state; 125 #if IS_ENABLED(CONFIG_PCI_MSM) 126 struct msm_pcie_register_event msm_pci_event; 127 #endif 128 struct cnss_pm_stats pm_stats; 129 atomic_t auto_suspended; 130 atomic_t drv_connected; 131 u8 drv_connected_last; 132 u32 qmi_send_usage_count; 133 u16 def_link_speed; 134 u16 def_link_width; 135 u16 cur_link_speed; 136 int wake_gpio; 137 int wake_irq; 138 u32 wake_counter; 139 u8 monitor_wake_intr; 140 struct iommu_domain *iommu_domain; 141 u8 smmu_s1_enable; 142 dma_addr_t smmu_iova_start; 143 size_t smmu_iova_len; 144 dma_addr_t smmu_iova_ipa_start; 145 dma_addr_t smmu_iova_ipa_current; 146 size_t smmu_iova_ipa_len; 147 void __iomem *bar; 148 struct cnss_msi_config *msi_config; 149 u32 msi_ep_base_data; 150 struct mhi_controller *mhi_ctrl; 151 unsigned long mhi_state; 152 u32 remap_window; 153 struct timer_list dev_rddm_timer; 154 struct timer_list boot_debug_timer; 155 struct delayed_work time_sync_work; 156 u8 disable_pc; 157 struct mutex bus_lock; /* mutex for suspend and resume bus */ 158 struct cnss_pci_debug_reg *debug_reg; 159 struct cnss_misc_reg *wcss_reg; 160 struct cnss_misc_reg *pcie_reg; 161 struct cnss_misc_reg *wlaon_reg; 162 struct cnss_misc_reg *syspm_reg; 163 unsigned long misc_reg_dev_mask; 164 u8 iommu_geometry; 165 bool drv_supported; 166 bool is_smmu_fault; 167 }; 168 169 static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data) 170 { 171 pci_set_drvdata(pci_dev, data); 172 } 173 174 static inline struct cnss_pci_data *cnss_get_pci_priv(struct pci_dev *pci_dev) 175 { 176 return pci_get_drvdata(pci_dev); 177 } 178 179 static inline struct cnss_plat_data *cnss_pci_priv_to_plat_priv(void *bus_priv) 180 { 181 struct cnss_pci_data *pci_priv = bus_priv; 182 183 return pci_priv->plat_priv; 184 } 185 186 static inline void cnss_pci_set_monitor_wake_intr(void *bus_priv, bool val) 187 { 188 struct cnss_pci_data *pci_priv = bus_priv; 189 190 pci_priv->monitor_wake_intr = val; 191 } 192 193 static inline bool cnss_pci_get_monitor_wake_intr(void *bus_priv) 194 { 195 struct cnss_pci_data *pci_priv = bus_priv; 196 197 return pci_priv->monitor_wake_intr; 198 } 199 200 static inline void cnss_pci_set_auto_suspended(void *bus_priv, int val) 201 { 202 struct cnss_pci_data *pci_priv = bus_priv; 203 204 atomic_set(&pci_priv->auto_suspended, val); 205 } 206 207 static inline int cnss_pci_get_auto_suspended(void *bus_priv) 208 { 209 struct cnss_pci_data *pci_priv = bus_priv; 210 211 return atomic_read(&pci_priv->auto_suspended); 212 } 213 214 static inline void cnss_pci_set_drv_connected(void *bus_priv, int val) 215 { 216 struct cnss_pci_data *pci_priv = bus_priv; 217 218 atomic_set(&pci_priv->drv_connected, val); 219 } 220 221 static inline int cnss_pci_get_drv_connected(void *bus_priv) 222 { 223 struct cnss_pci_data *pci_priv = bus_priv; 224 225 return atomic_read(&pci_priv->drv_connected); 226 } 227 228 void cnss_mhi_controller_set_base(struct cnss_pci_data *pci_priv, 229 phys_addr_t base); 230 int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv); 231 int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv); 232 int cnss_resume_pci_link(struct cnss_pci_data *pci_priv); 233 int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv); 234 int cnss_pci_init(struct cnss_plat_data *plat_priv); 235 void cnss_pci_deinit(struct cnss_plat_data *plat_priv); 236 void cnss_pci_add_fw_prefix_name(struct cnss_pci_data *pci_priv, 237 char *prefix_name, char *name); 238 int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv); 239 int cnss_pci_alloc_qdss_mem(struct cnss_pci_data *pci_priv); 240 void cnss_pci_free_qdss_mem(struct cnss_pci_data *pci_priv); 241 int cnss_pci_load_m3(struct cnss_pci_data *pci_priv); 242 void cnss_pci_free_blob_mem(struct cnss_pci_data *pci_priv); 243 int cnss_pci_handle_dev_sol_irq(struct cnss_pci_data *pci_priv); 244 int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv); 245 void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic); 246 #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP 247 void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv); 248 #else 249 static inline 250 void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv) 251 { 252 } 253 #endif 254 void cnss_pci_device_crashed(struct cnss_pci_data *pci_priv); 255 void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv); 256 u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv); 257 int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv); 258 int cnss_pci_qmi_send_get(struct cnss_pci_data *pci_priv); 259 int cnss_pci_qmi_send_put(struct cnss_pci_data *pci_priv); 260 void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv); 261 int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv); 262 int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv); 263 int cnss_pci_dev_powerup(struct cnss_pci_data *pci_priv); 264 int cnss_pci_dev_shutdown(struct cnss_pci_data *pci_priv); 265 int cnss_pci_dev_crash_shutdown(struct cnss_pci_data *pci_priv); 266 int cnss_pci_dev_ramdump(struct cnss_pci_data *pci_priv); 267 int cnss_pci_register_driver_hdlr(struct cnss_pci_data *pci_priv, void *data); 268 int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv); 269 int cnss_pci_call_driver_modem_status(struct cnss_pci_data *pci_priv, 270 int modem_current_status); 271 void cnss_pci_pm_runtime_show_usage_count(struct cnss_pci_data *pci_priv); 272 int cnss_pci_pm_request_resume(struct cnss_pci_data *pci_priv); 273 int cnss_pci_pm_runtime_resume(struct cnss_pci_data *pci_priv); 274 int cnss_pci_pm_runtime_get(struct cnss_pci_data *pci_priv, 275 enum cnss_rtpm_id id); 276 int cnss_pci_pm_runtime_get_sync(struct cnss_pci_data *pci_priv, 277 enum cnss_rtpm_id id); 278 void cnss_pci_pm_runtime_get_noresume(struct cnss_pci_data *pci_priv, 279 enum cnss_rtpm_id id); 280 int cnss_pci_pm_runtime_put_autosuspend(struct cnss_pci_data *pci_priv, 281 enum cnss_rtpm_id id); 282 void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv, 283 enum cnss_rtpm_id id); 284 void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv); 285 int cnss_pci_update_status(struct cnss_pci_data *pci_priv, 286 enum cnss_driver_status status); 287 int cnss_pci_call_driver_uevent(struct cnss_pci_data *pci_priv, 288 enum cnss_driver_status status, void *data); 289 int cnss_pcie_is_device_down(struct cnss_pci_data *pci_priv); 290 int cnss_pci_suspend_bus(struct cnss_pci_data *pci_priv); 291 int cnss_pci_resume_bus(struct cnss_pci_data *pci_priv); 292 int cnss_pci_debug_reg_read(struct cnss_pci_data *pci_priv, u32 offset, 293 u32 *val, bool raw_access); 294 int cnss_pci_debug_reg_write(struct cnss_pci_data *pci_priv, u32 offset, 295 u32 val, bool raw_access); 296 int cnss_pci_get_iova(struct cnss_pci_data *pci_priv, u64 *addr, u64 *size); 297 int cnss_pci_get_iova_ipa(struct cnss_pci_data *pci_priv, u64 *addr, 298 u64 *size); 299 bool cnss_pci_is_smmu_s1_enabled(struct cnss_pci_data *pci_priv); 300 void cnss_pci_handle_linkdown(struct cnss_pci_data *pci_priv); 301 302 int cnss_pci_update_time_sync_period(struct cnss_pci_data *pci_priv, 303 unsigned int time_sync_period); 304 int cnss_pci_set_therm_cdev_state(struct cnss_pci_data *pci_priv, 305 unsigned long thermal_state, 306 int tcdev_id); 307 int cnss_pci_get_user_msi_assignment(struct cnss_pci_data *pci_priv, 308 char *user_name, 309 int *num_vectors, 310 u32 *user_base_data, 311 u32 *base_vector); 312 #endif /* _CNSS_PCI_H */ 313