xref: /wlan-dirver/platform/cnss2/main.h (revision 44ad9ad95fe5075cb34c52cf0a6fb81a9036d281) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef _CNSS_MAIN_H
8 #define _CNSS_MAIN_H
9 
10 #if IS_ENABLED(CONFIG_ARM) || IS_ENABLED(CONFIG_ARM64)
11 #include <asm/arch_timer.h>
12 #endif
13 #if IS_ENABLED(CONFIG_ESOC)
14 #include <linux/esoc_client.h>
15 #endif
16 #include <linux/etherdevice.h>
17 #include <linux/firmware.h>
18 #if IS_ENABLED(CONFIG_INTERCONNECT)
19 #include <linux/interconnect.h>
20 #endif
21 #include <linux/mailbox_client.h>
22 #include <linux/pm_qos.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/time64.h>
26 #ifdef CONFIG_CNSS_OUT_OF_TREE
27 #include "cnss2.h"
28 #else
29 #include <net/cnss2.h>
30 #endif
31 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) || IS_ENABLED(CONFIG_QCOM_MINIDUMP)
32 #include <soc/qcom/memory_dump.h>
33 #endif
34 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART) || \
35 	IS_ENABLED(CONFIG_QCOM_RAMDUMP)
36 #include <soc/qcom/qcom_ramdump.h>
37 #endif
38 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
39 #include <soc/qcom/subsystem_notif.h>
40 #include <soc/qcom/subsystem_restart.h>
41 #endif
42 
43 #include "qmi.h"
44 
45 #define MAX_NO_OF_MAC_ADDR		4
46 #define QMI_WLFW_MAX_TIMESTAMP_LEN	32
47 #define QMI_WLFW_MAX_NUM_MEM_SEG	32
48 #define QMI_WLFW_MAX_BUILD_ID_LEN	128
49 #define CNSS_RDDM_TIMEOUT_MS		20000
50 #define RECOVERY_TIMEOUT		60000
51 #define WLAN_WD_TIMEOUT_MS		60000
52 #define WLAN_COLD_BOOT_CAL_TIMEOUT	60000
53 #define WLAN_MISSION_MODE_TIMEOUT	30000
54 #define TIME_CLOCK_FREQ_HZ		19200000
55 #define CNSS_RAMDUMP_MAGIC		0x574C414E
56 #define CNSS_RAMDUMP_VERSION		0
57 #define MAX_FIRMWARE_NAME_LEN		40
58 #define FW_V2_NUMBER                    2
59 #define POWER_ON_RETRY_MAX_TIMES        4
60 #define POWER_ON_RETRY_DELAY_MS         500
61 #define WLFW_MAX_HANG_EVENT_DATA_SIZE   384
62 
63 #define CNSS_EVENT_SYNC   BIT(0)
64 #define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
65 #define CNSS_EVENT_UNKILLABLE BIT(2)
66 #define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \
67 				CNSS_EVENT_UNINTERRUPTIBLE)
68 #define CNSS_EVENT_SYNC_UNKILLABLE (CNSS_EVENT_SYNC | CNSS_EVENT_UNKILLABLE)
69 
70 enum cnss_dt_type {
71 	CNSS_DTT_LEGACY = 0,
72 	CNSS_DTT_CONVERGED = 1,
73 	CNSS_DTT_MULTIEXCHG = 2
74 };
75 
76 enum cnss_dev_bus_type {
77 	CNSS_BUS_NONE = -1,
78 	CNSS_BUS_PCI,
79 	CNSS_BUS_MAX
80 };
81 
82 struct cnss_vreg_cfg {
83 	const char *name;
84 	u32 min_uv;
85 	u32 max_uv;
86 	u32 load_ua;
87 	u32 delay_us;
88 	u32 need_unvote;
89 };
90 
91 struct cnss_vreg_info {
92 	struct list_head list;
93 	struct regulator *reg;
94 	struct cnss_vreg_cfg cfg;
95 	u32 enabled;
96 };
97 
98 enum cnss_vreg_type {
99 	CNSS_VREG_PRIM,
100 };
101 
102 struct cnss_clk_cfg {
103 	const char *name;
104 	u32 freq;
105 	u32 required;
106 };
107 
108 struct cnss_clk_info {
109 	struct list_head list;
110 	struct clk *clk;
111 	struct cnss_clk_cfg cfg;
112 	u32 enabled;
113 };
114 
115 struct cnss_pinctrl_info {
116 	struct pinctrl *pinctrl;
117 	struct pinctrl_state *bootstrap_active;
118 	struct pinctrl_state *sol_default;
119 	struct pinctrl_state *wlan_en_active;
120 	struct pinctrl_state *wlan_en_sleep;
121 	int bt_en_gpio;
122 	int wlan_en_gpio;
123 	int xo_clk_gpio; /*qca6490 only */
124 	int sw_ctrl_gpio;
125 	int wlan_sw_ctrl_gpio;
126 };
127 
128 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
129 struct cnss_subsys_info {
130 	struct subsys_device *subsys_device;
131 	struct subsys_desc subsys_desc;
132 	void *subsys_handle;
133 };
134 #endif
135 
136 struct cnss_ramdump_info {
137 	void *ramdump_dev;
138 	unsigned long ramdump_size;
139 	void *ramdump_va;
140 	phys_addr_t ramdump_pa;
141 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
142 	struct msm_dump_data dump_data;
143 #endif
144 };
145 
146 struct cnss_dump_seg {
147 	unsigned long address;
148 	void *v_address;
149 	unsigned long size;
150 	u32 type;
151 };
152 
153 struct cnss_dump_data {
154 	u32 version;
155 	u32 magic;
156 	char name[32];
157 	phys_addr_t paddr;
158 	int nentries;
159 	u32 seg_version;
160 };
161 
162 struct cnss_ramdump_info_v2 {
163 	void *ramdump_dev;
164 	unsigned long ramdump_size;
165 	void *dump_data_vaddr;
166 	u8 dump_data_valid;
167 	struct cnss_dump_data dump_data;
168 };
169 
170 #if IS_ENABLED(CONFIG_ESOC)
171 struct cnss_esoc_info {
172 	struct esoc_desc *esoc_desc;
173 	u8 notify_modem_status;
174 	void *modem_notify_handler;
175 	int modem_current_status;
176 };
177 #endif
178 
179 #if IS_ENABLED(CONFIG_INTERCONNECT)
180 /**
181  * struct cnss_bus_bw_cfg - Interconnect vote data
182  * @avg_bw: Vote for average bandwidth
183  * @peak_bw: Vote for peak bandwidth
184  */
185 struct cnss_bus_bw_cfg {
186 	u32 avg_bw;
187 	u32 peak_bw;
188 };
189 
190 /* Number of bw votes (avg, peak) entries that ICC requires */
191 #define CNSS_ICC_VOTE_MAX 2
192 
193 /**
194  * struct cnss_bus_bw_info - Bus bandwidth config for interconnect path
195  * @list: Kernel linked list
196  * @icc_name: Name of interconnect path as defined in Device tree
197  * @icc_path: Interconnect path data structure
198  * @cfg_table: Interconnect vote data for average and peak bandwidth
199  */
200 struct cnss_bus_bw_info {
201 	struct list_head list;
202 	const char *icc_name;
203 	struct icc_path *icc_path;
204 	struct cnss_bus_bw_cfg *cfg_table;
205 };
206 #endif
207 
208 /**
209  * struct cnss_interconnect_cfg - CNSS platform interconnect config
210  * @list_head: List of interconnect path bandwidth configs
211  * @path_count: Count of interconnect path configured in device tree
212  * @current_bw_vote: WLAN driver provided bandwidth vote
213  * @bus_bw_cfg_count: Number of bandwidth configs for voting. It is the array
214  *                    size of struct cnss_bus_bw_info.cfg_table
215  */
216 struct cnss_interconnect_cfg {
217 	struct list_head list_head;
218 	u32 path_count;
219 	int current_bw_vote;
220 	u32 bus_bw_cfg_count;
221 };
222 
223 struct cnss_fw_mem {
224 	size_t size;
225 	void *va;
226 	phys_addr_t pa;
227 	u8 valid;
228 	u32 type;
229 	unsigned long attrs;
230 };
231 
232 struct wlfw_rf_chip_info {
233 	u32 chip_id;
234 	u32 chip_family;
235 };
236 
237 struct wlfw_rf_board_info {
238 	u32 board_id;
239 };
240 
241 struct wlfw_soc_info {
242 	u32 soc_id;
243 };
244 
245 struct wlfw_fw_version_info {
246 	u32 fw_version;
247 	char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1];
248 };
249 
250 enum cnss_mem_type {
251 	CNSS_MEM_TYPE_MSA,
252 	CNSS_MEM_TYPE_DDR,
253 	CNSS_MEM_BDF,
254 	CNSS_MEM_M3,
255 	CNSS_MEM_CAL_V01,
256 	CNSS_MEM_DPD_V01,
257 };
258 
259 enum cnss_fw_dump_type {
260 	CNSS_FW_IMAGE,
261 	CNSS_FW_RDDM,
262 	CNSS_FW_REMOTE_HEAP,
263 	CNSS_FW_DUMP_TYPE_MAX,
264 };
265 
266 struct cnss_dump_entry {
267 	u32 type;
268 	u32 entry_start;
269 	u32 entry_num;
270 };
271 
272 struct cnss_dump_meta_info {
273 	u32 magic;
274 	u32 version;
275 	u32 chipset;
276 	u32 total_entries;
277 	struct cnss_dump_entry entry[CNSS_FW_DUMP_TYPE_MAX];
278 };
279 
280 enum cnss_driver_event_type {
281 	CNSS_DRIVER_EVENT_SERVER_ARRIVE,
282 	CNSS_DRIVER_EVENT_SERVER_EXIT,
283 	CNSS_DRIVER_EVENT_REQUEST_MEM,
284 	CNSS_DRIVER_EVENT_FW_MEM_READY,
285 	CNSS_DRIVER_EVENT_FW_READY,
286 	CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
287 	CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
288 	CNSS_DRIVER_EVENT_REGISTER_DRIVER,
289 	CNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
290 	CNSS_DRIVER_EVENT_RECOVERY,
291 	CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
292 	CNSS_DRIVER_EVENT_POWER_UP,
293 	CNSS_DRIVER_EVENT_POWER_DOWN,
294 	CNSS_DRIVER_EVENT_IDLE_RESTART,
295 	CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
296 	CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
297 	CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND,
298 	CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
299 	CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
300 	CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
301 	CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
302 	CNSS_DRIVER_EVENT_MAX,
303 };
304 
305 enum cnss_driver_state {
306 	CNSS_QMI_WLFW_CONNECTED = 0,
307 	CNSS_FW_MEM_READY,
308 	CNSS_FW_READY,
309 	CNSS_IN_COLD_BOOT_CAL,
310 	CNSS_DRIVER_LOADING,
311 	CNSS_DRIVER_UNLOADING = 5,
312 	CNSS_DRIVER_IDLE_RESTART,
313 	CNSS_DRIVER_IDLE_SHUTDOWN,
314 	CNSS_DRIVER_PROBED,
315 	CNSS_DRIVER_RECOVERY,
316 	CNSS_FW_BOOT_RECOVERY = 10,
317 	CNSS_DEV_ERR_NOTIFY,
318 	CNSS_DRIVER_DEBUG,
319 	CNSS_COEX_CONNECTED,
320 	CNSS_IMS_CONNECTED,
321 	CNSS_IN_SUSPEND_RESUME = 15,
322 	CNSS_IN_REBOOT,
323 	CNSS_COLD_BOOT_CAL_DONE,
324 	CNSS_IN_PANIC,
325 	CNSS_QMI_DEL_SERVER,
326 	CNSS_QMI_DMS_CONNECTED = 20,
327 	CNSS_DAEMON_CONNECTED,
328 	CNSS_PCI_PROBE_DONE,
329 	CNSS_DRIVER_REGISTER,
330 	CNSS_WLAN_HW_DISABLED,
331 	CNSS_FS_READY = 25,
332 	CNSS_DRIVER_REGISTERED,
333 	CNSS_DMS_DEL_SERVER,
334 };
335 
336 struct cnss_recovery_data {
337 	enum cnss_recovery_reason reason;
338 };
339 
340 enum cnss_pins {
341 	CNSS_WLAN_EN,
342 	CNSS_PCIE_TXP,
343 	CNSS_PCIE_TXN,
344 	CNSS_PCIE_RXP,
345 	CNSS_PCIE_RXN,
346 	CNSS_PCIE_REFCLKP,
347 	CNSS_PCIE_REFCLKN,
348 	CNSS_PCIE_RST,
349 	CNSS_PCIE_WAKE,
350 };
351 
352 struct cnss_pin_connect_result {
353 	u32 fw_pwr_pin_result;
354 	u32 fw_phy_io_pin_result;
355 	u32 fw_rf_pin_result;
356 	u32 host_pin_result;
357 };
358 
359 enum cnss_debug_quirks {
360 	LINK_DOWN_SELF_RECOVERY,
361 	SKIP_DEVICE_BOOT,
362 	USE_CORE_ONLY_FW,
363 	SKIP_RECOVERY,
364 	QMI_BYPASS,
365 	ENABLE_WALTEST,
366 	ENABLE_PCI_LINK_DOWN_PANIC,
367 	FBC_BYPASS,
368 	ENABLE_DAEMON_SUPPORT,
369 	DISABLE_DRV,
370 	DISABLE_IO_COHERENCY,
371 	IGNORE_PCI_LINK_FAILURE,
372 	DISABLE_TIME_SYNC,
373 	FORCE_ONE_MSI,
374 	QUIRK_MAX_VALUE
375 };
376 
377 enum cnss_bdf_type {
378 	CNSS_BDF_BIN,
379 	CNSS_BDF_ELF,
380 	CNSS_BDF_REGDB = 4,
381 	CNSS_BDF_HDS = 6,
382 };
383 
384 enum cnss_cal_status {
385 	CNSS_CAL_DONE,
386 	CNSS_CAL_TIMEOUT,
387 	CNSS_CAL_FAILURE,
388 };
389 
390 struct cnss_cal_info {
391 	enum cnss_cal_status cal_status;
392 };
393 
394 struct cnss_control_params {
395 	unsigned long quirks;
396 	unsigned int mhi_timeout;
397 	unsigned int mhi_m2_timeout;
398 	unsigned int qmi_timeout;
399 	unsigned int bdf_type;
400 	unsigned int time_sync_period;
401 };
402 
403 struct cnss_tcs_info {
404 	resource_size_t cmd_base_addr;
405 	void __iomem *cmd_base_addr_io;
406 };
407 
408 struct cnss_cpr_info {
409 	resource_size_t tcs_cmd_data_addr;
410 	void __iomem *tcs_cmd_data_addr_io;
411 	u32 cpr_pmic_addr;
412 	u32 voltage;
413 };
414 
415 enum cnss_ce_index {
416 	CNSS_CE_00,
417 	CNSS_CE_01,
418 	CNSS_CE_02,
419 	CNSS_CE_03,
420 	CNSS_CE_04,
421 	CNSS_CE_05,
422 	CNSS_CE_06,
423 	CNSS_CE_07,
424 	CNSS_CE_08,
425 	CNSS_CE_09,
426 	CNSS_CE_10,
427 	CNSS_CE_11,
428 	CNSS_CE_COMMON,
429 };
430 
431 struct cnss_dms_data {
432 	u32 mac_valid;
433 	u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
434 };
435 
436 enum cnss_timeout_type {
437 	CNSS_TIMEOUT_QMI,
438 	CNSS_TIMEOUT_POWER_UP,
439 	CNSS_TIMEOUT_IDLE_RESTART,
440 	CNSS_TIMEOUT_CALIBRATION,
441 	CNSS_TIMEOUT_WLAN_WATCHDOG,
442 	CNSS_TIMEOUT_RDDM,
443 	CNSS_TIMEOUT_RECOVERY,
444 	CNSS_TIMEOUT_DAEMON_CONNECTION,
445 };
446 
447 struct cnss_sol_gpio {
448 	int dev_sol_gpio;
449 	int dev_sol_irq;
450 	u32 dev_sol_counter;
451 	int host_sol_gpio;
452 };
453 
454 struct cnss_plat_data {
455 	struct platform_device *plat_dev;
456 	void *bus_priv;
457 	enum cnss_dev_bus_type bus_type;
458 	struct list_head vreg_list;
459 	struct list_head clk_list;
460 	struct cnss_pinctrl_info pinctrl_info;
461 	struct cnss_sol_gpio sol_gpio;
462 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
463 	struct cnss_subsys_info subsys_info;
464 #endif
465 	struct cnss_ramdump_info ramdump_info;
466 	struct cnss_ramdump_info_v2 ramdump_info_v2;
467 #if IS_ENABLED(CONFIG_ESOC)
468 	struct cnss_esoc_info esoc_info;
469 #endif
470 	struct cnss_interconnect_cfg icc;
471 	struct notifier_block modem_nb;
472 	struct notifier_block reboot_nb;
473 	struct notifier_block panic_nb;
474 	struct cnss_platform_cap cap;
475 	struct pm_qos_request qos_request;
476 	struct cnss_device_version device_version;
477 	u32 rc_num;
478 	unsigned long device_id;
479 	enum cnss_driver_status driver_status;
480 	u32 recovery_count;
481 	u8 recovery_enabled;
482 	u8 recovery_pcss_enabled;
483 	u8 hds_enabled;
484 	unsigned long driver_state;
485 	struct list_head event_list;
486 	spinlock_t event_lock; /* spinlock for driver work event handling */
487 	struct work_struct event_work;
488 	struct workqueue_struct *event_wq;
489 	struct work_struct recovery_work;
490 	struct delayed_work wlan_reg_driver_work;
491 	struct qmi_handle qmi_wlfw;
492 	struct qmi_handle qmi_dms;
493 	struct wlfw_rf_chip_info chip_info;
494 	struct wlfw_rf_board_info board_info;
495 	struct wlfw_soc_info soc_info;
496 	struct wlfw_fw_version_info fw_version_info;
497 	struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM];
498 	char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN + 1];
499 	u32 otp_version;
500 	u32 fw_mem_seg_len;
501 	struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG];
502 	struct cnss_fw_mem m3_mem;
503 	struct cnss_fw_mem *cal_mem;
504 	u64 cal_time;
505 	bool cbc_file_download;
506 	u32 cal_file_size;
507 	struct completion daemon_connected;
508 	u32 qdss_mem_seg_len;
509 	struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG];
510 	u32 *qdss_reg;
511 	struct cnss_pin_connect_result pin_result;
512 	struct dentry *root_dentry;
513 	atomic_t pm_count;
514 	struct timer_list fw_boot_timer;
515 	struct completion power_up_complete;
516 	struct completion cal_complete;
517 	struct mutex dev_lock; /* mutex for register access through debugfs */
518 	struct mutex driver_ops_lock; /* mutex for external driver ops */
519 	struct cnss_wlan_driver *driver_ops;
520 	u32 device_freq_hz;
521 	u32 diag_reg_read_addr;
522 	u32 diag_reg_read_mem_type;
523 	u32 diag_reg_read_len;
524 	u8 *diag_reg_read_buf;
525 	u8 cal_done;
526 	u8 powered_on;
527 	u8 use_fw_path_with_prefix;
528 	char firmware_name[MAX_FIRMWARE_NAME_LEN];
529 	char fw_fallback_name[MAX_FIRMWARE_NAME_LEN];
530 	u8 *sram_dump;
531 	struct completion rddm_complete;
532 	struct completion recovery_complete;
533 	struct cnss_control_params ctrl_params;
534 	struct cnss_cpr_info cpr_info;
535 	u64 antenna;
536 	u64 grant;
537 	struct qmi_handle coex_qmi;
538 	struct qmi_handle ims_qmi;
539 	struct qmi_txn txn;
540 	struct wakeup_source *recovery_ws;
541 	u64 dynamic_feature;
542 	void *get_info_cb_ctx;
543 	int (*get_info_cb)(void *ctx, void *event, int event_len);
544 	bool cbc_enabled;
545 	u8 use_pm_domain;
546 	u8 use_nv_mac;
547 	u8 set_wlaon_pwr_ctrl;
548 	struct cnss_tcs_info tcs_info;
549 	bool fw_pcie_gen_switch;
550 	u8 pcie_gen_speed;
551 	struct cnss_dms_data dms;
552 	int power_up_error;
553 	u32 hw_trc_override;
554 	u8 charger_mode;
555 	struct mbox_client mbox_client_data;
556 	struct mbox_chan *mbox_chan;
557 	const char *vreg_ol_cpr, *vreg_ipa;
558 	const char **pdc_init_table, **vreg_pdc_map, **pmu_vreg_map;
559 	int pdc_init_table_len, vreg_pdc_map_len, pmu_vreg_map_len;
560 	bool adsp_pc_enabled;
561 	u64 feature_list;
562 	u32 dt_type;
563 	struct kobject *wifi_kobj;
564 	u16 hang_event_data_len;
565 	u32 hang_data_addr_offset;
566 	/* bitmap to detect FEM combination */
567 	u8 hwid_bitmap;
568 	enum cnss_driver_mode driver_mode;
569 	uint32_t num_shadow_regs_v3;
570 	bool sec_peri_feature_disable;
571 	struct device_node *dev_node;
572 };
573 
574 #if IS_ENABLED(CONFIG_ARCH_QCOM)
575 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
576 {
577 	u64 ticks = __arch_counter_get_cntvct();
578 
579 	do_div(ticks, TIME_CLOCK_FREQ_HZ / 100000);
580 
581 	return ticks * 10;
582 }
583 #else
584 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
585 {
586 	struct timespec64 ts;
587 
588 	ktime_get_ts64(&ts);
589 
590 	return (ts.tv_sec * 1000000) + (ts.tv_nsec / 1000);
591 }
592 #endif
593 
594 int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv);
595 int cnss_wlan_hw_enable(void);
596 struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev);
597 void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv);
598 void cnss_pm_relax(struct cnss_plat_data *plat_priv);
599 int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
600 			   enum cnss_driver_event_type type,
601 			   u32 flags, void *data);
602 int cnss_get_vreg_type(struct cnss_plat_data *plat_priv,
603 		       enum cnss_vreg_type type);
604 void cnss_put_vreg_type(struct cnss_plat_data *plat_priv,
605 			enum cnss_vreg_type type);
606 int cnss_vreg_on_type(struct cnss_plat_data *plat_priv,
607 		      enum cnss_vreg_type type);
608 int cnss_vreg_off_type(struct cnss_plat_data *plat_priv,
609 		       enum cnss_vreg_type type);
610 int cnss_get_clk(struct cnss_plat_data *plat_priv);
611 void cnss_put_clk(struct cnss_plat_data *plat_priv);
612 int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv,
613 			  enum cnss_vreg_type type);
614 int cnss_get_pinctrl(struct cnss_plat_data *plat_priv);
615 int cnss_get_wlan_sw_ctrl(struct cnss_plat_data *plat_priv);
616 int cnss_power_on_device(struct cnss_plat_data *plat_priv);
617 void cnss_power_off_device(struct cnss_plat_data *plat_priv);
618 bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv);
619 int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv);
620 int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv);
621 int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv);
622 int cnss_init_dev_sol_irq(struct cnss_plat_data *plat_priv);
623 int cnss_deinit_dev_sol_irq(struct cnss_plat_data *plat_priv);
624 int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value);
625 int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv);
626 int cnss_register_subsys(struct cnss_plat_data *plat_priv);
627 void cnss_unregister_subsys(struct cnss_plat_data *plat_priv);
628 int cnss_register_ramdump(struct cnss_plat_data *plat_priv);
629 void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
630 int cnss_do_ramdump(struct cnss_plat_data *plat_priv);
631 int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv);
632 void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
633 int cnss_get_cpr_info(struct cnss_plat_data *plat_priv);
634 int cnss_update_cpr_info(struct cnss_plat_data *plat_priv);
635 int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
636 		  phys_addr_t *pa, unsigned long attrs);
637 int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
638 			     enum cnss_fw_dump_type type, int seg_no,
639 			     void *va, phys_addr_t pa, size_t size);
640 int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
641 				enum cnss_fw_dump_type type, int seg_no,
642 				void *va, phys_addr_t pa, size_t size);
643 int cnss_enable_int_pow_amp_vreg(struct cnss_plat_data *plat_priv);
644 int cnss_get_tcs_info(struct cnss_plat_data *plat_priv);
645 unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
646 			      enum cnss_timeout_type);
647 int cnss_aop_mbox_init(struct cnss_plat_data *plat_priv);
648 int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv);
649 int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *msg);
650 void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv);
651 int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
652 			      struct wlfw_pmu_cfg_v01 *fw_pmu_cfg);
653 int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
654 				 const struct firmware **fw_entry,
655 				 const char *filename);
656 int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
657 			  enum cnss_feature_v01 feature);
658 int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
659 			    enum cnss_feature_v01 feature);
660 int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
661 			  u64 *feature_list);
662 int cnss_get_input_gpio_value(struct cnss_plat_data *plat_priv, int gpio_num);
663 bool cnss_check_driver_loading_allowed(void);
664 int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv);
665 #endif /* _CNSS_MAIN_H */
666