xref: /wlan-dirver/platform/cnss2/main.h (revision 075cc964ceec3489aa89464eac35949a3f5307c2) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef _CNSS_MAIN_H
8 #define _CNSS_MAIN_H
9 
10 #if IS_ENABLED(CONFIG_ARM) || IS_ENABLED(CONFIG_ARM64)
11 #include <asm/arch_timer.h>
12 #endif
13 #if IS_ENABLED(CONFIG_ESOC)
14 #include <linux/esoc_client.h>
15 #endif
16 #include <linux/etherdevice.h>
17 #include <linux/firmware.h>
18 #if IS_ENABLED(CONFIG_INTERCONNECT)
19 #include <linux/interconnect.h>
20 #endif
21 #include <linux/mailbox_client.h>
22 #include <linux/pm_qos.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/time64.h>
26 #ifdef CONFIG_CNSS_OUT_OF_TREE
27 #include "cnss2.h"
28 #else
29 #include <net/cnss2.h>
30 #endif
31 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) || IS_ENABLED(CONFIG_QCOM_MINIDUMP)
32 #include <soc/qcom/memory_dump.h>
33 #endif
34 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART) || \
35 	IS_ENABLED(CONFIG_QCOM_RAMDUMP)
36 #include <soc/qcom/qcom_ramdump.h>
37 #endif
38 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
39 #include <soc/qcom/subsystem_notif.h>
40 #include <soc/qcom/subsystem_restart.h>
41 #endif
42 #include <linux/iommu.h>
43 #include "qmi.h"
44 
45 #define MAX_NO_OF_MAC_ADDR		4
46 #define QMI_WLFW_MAX_TIMESTAMP_LEN	32
47 #define QMI_WLFW_MAX_BUILD_ID_LEN	128
48 #define CNSS_RDDM_TIMEOUT_MS		20000
49 #define RECOVERY_TIMEOUT		60000
50 #define WLAN_WD_TIMEOUT_MS		60000
51 #define WLAN_COLD_BOOT_CAL_TIMEOUT	60000
52 #define WLAN_MISSION_MODE_TIMEOUT	30000
53 #define TIME_CLOCK_FREQ_HZ		19200000
54 #define CNSS_RAMDUMP_MAGIC		0x574C414E
55 #define CNSS_RAMDUMP_VERSION		0
56 #define MAX_FIRMWARE_NAME_LEN		40
57 #define FW_V2_NUMBER                    2
58 #define POWER_ON_RETRY_MAX_TIMES        4
59 #define POWER_ON_RETRY_DELAY_MS         500
60 #define WLFW_MAX_HANG_EVENT_DATA_SIZE   384
61 
62 #define CNSS_EVENT_SYNC   BIT(0)
63 #define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
64 #define CNSS_EVENT_UNKILLABLE BIT(2)
65 #define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \
66 				CNSS_EVENT_UNINTERRUPTIBLE)
67 #define CNSS_EVENT_SYNC_UNKILLABLE (CNSS_EVENT_SYNC | CNSS_EVENT_UNKILLABLE)
68 
69 enum cnss_dt_type {
70 	CNSS_DTT_LEGACY = 0,
71 	CNSS_DTT_CONVERGED = 1,
72 	CNSS_DTT_MULTIEXCHG = 2
73 };
74 
75 enum cnss_dev_bus_type {
76 	CNSS_BUS_NONE = -1,
77 	CNSS_BUS_PCI,
78 	CNSS_BUS_MAX
79 };
80 
81 struct cnss_vreg_cfg {
82 	const char *name;
83 	u32 min_uv;
84 	u32 max_uv;
85 	u32 load_ua;
86 	u32 delay_us;
87 	u32 need_unvote;
88 };
89 
90 struct cnss_vreg_info {
91 	struct list_head list;
92 	struct regulator *reg;
93 	struct cnss_vreg_cfg cfg;
94 	u32 enabled;
95 };
96 
97 enum cnss_vreg_type {
98 	CNSS_VREG_PRIM,
99 };
100 
101 struct cnss_clk_cfg {
102 	const char *name;
103 	u32 freq;
104 	u32 required;
105 };
106 
107 struct cnss_clk_info {
108 	struct list_head list;
109 	struct clk *clk;
110 	struct cnss_clk_cfg cfg;
111 	u32 enabled;
112 };
113 
114 struct cnss_pinctrl_info {
115 	struct pinctrl *pinctrl;
116 	struct pinctrl_state *bootstrap_active;
117 	struct pinctrl_state *sol_default;
118 	struct pinctrl_state *wlan_en_active;
119 	struct pinctrl_state *wlan_en_sleep;
120 	int bt_en_gpio;
121 	int wlan_en_gpio;
122 	int xo_clk_gpio; /*qca6490 only */
123 	int sw_ctrl_gpio;
124 	int wlan_sw_ctrl_gpio;
125 };
126 
127 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
128 struct cnss_subsys_info {
129 	struct subsys_device *subsys_device;
130 	struct subsys_desc subsys_desc;
131 	void *subsys_handle;
132 };
133 #endif
134 
135 struct cnss_ramdump_info {
136 	void *ramdump_dev;
137 	unsigned long ramdump_size;
138 	void *ramdump_va;
139 	phys_addr_t ramdump_pa;
140 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
141 	struct msm_dump_data dump_data;
142 #endif
143 };
144 
145 struct cnss_dump_seg {
146 	unsigned long address;
147 	void *v_address;
148 	unsigned long size;
149 	u32 type;
150 };
151 
152 struct cnss_dump_data {
153 	u32 version;
154 	u32 magic;
155 	char name[32];
156 	phys_addr_t paddr;
157 	int nentries;
158 	u32 seg_version;
159 };
160 
161 struct cnss_ramdump_info_v2 {
162 	void *ramdump_dev;
163 	unsigned long ramdump_size;
164 	void *dump_data_vaddr;
165 	u8 dump_data_valid;
166 	struct cnss_dump_data dump_data;
167 };
168 
169 #if IS_ENABLED(CONFIG_ESOC)
170 struct cnss_esoc_info {
171 	struct esoc_desc *esoc_desc;
172 	u8 notify_modem_status;
173 	void *modem_notify_handler;
174 	int modem_current_status;
175 };
176 #endif
177 
178 #if IS_ENABLED(CONFIG_INTERCONNECT)
179 /**
180  * struct cnss_bus_bw_cfg - Interconnect vote data
181  * @avg_bw: Vote for average bandwidth
182  * @peak_bw: Vote for peak bandwidth
183  */
184 struct cnss_bus_bw_cfg {
185 	u32 avg_bw;
186 	u32 peak_bw;
187 };
188 
189 /* Number of bw votes (avg, peak) entries that ICC requires */
190 #define CNSS_ICC_VOTE_MAX 2
191 
192 /**
193  * struct cnss_bus_bw_info - Bus bandwidth config for interconnect path
194  * @list: Kernel linked list
195  * @icc_name: Name of interconnect path as defined in Device tree
196  * @icc_path: Interconnect path data structure
197  * @cfg_table: Interconnect vote data for average and peak bandwidth
198  */
199 struct cnss_bus_bw_info {
200 	struct list_head list;
201 	const char *icc_name;
202 	struct icc_path *icc_path;
203 	struct cnss_bus_bw_cfg *cfg_table;
204 };
205 #endif
206 
207 /**
208  * struct cnss_interconnect_cfg - CNSS platform interconnect config
209  * @list_head: List of interconnect path bandwidth configs
210  * @path_count: Count of interconnect path configured in device tree
211  * @current_bw_vote: WLAN driver provided bandwidth vote
212  * @bus_bw_cfg_count: Number of bandwidth configs for voting. It is the array
213  *                    size of struct cnss_bus_bw_info.cfg_table
214  */
215 struct cnss_interconnect_cfg {
216 	struct list_head list_head;
217 	u32 path_count;
218 	int current_bw_vote;
219 	u32 bus_bw_cfg_count;
220 };
221 
222 struct cnss_fw_mem {
223 	size_t size;
224 	void *va;
225 	phys_addr_t pa;
226 	u8 valid;
227 	u32 type;
228 	unsigned long attrs;
229 };
230 
231 struct wlfw_rf_chip_info {
232 	u32 chip_id;
233 	u32 chip_family;
234 };
235 
236 struct wlfw_rf_board_info {
237 	u32 board_id;
238 };
239 
240 struct wlfw_soc_info {
241 	u32 soc_id;
242 };
243 
244 struct wlfw_fw_version_info {
245 	u32 fw_version;
246 	char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1];
247 };
248 
249 enum cnss_mem_type {
250 	CNSS_MEM_TYPE_MSA,
251 	CNSS_MEM_TYPE_DDR,
252 	CNSS_MEM_BDF,
253 	CNSS_MEM_M3,
254 	CNSS_MEM_CAL_V01,
255 	CNSS_MEM_DPD_V01,
256 };
257 
258 enum cnss_fw_dump_type {
259 	CNSS_FW_IMAGE,
260 	CNSS_FW_RDDM,
261 	CNSS_FW_REMOTE_HEAP,
262 	CNSS_FW_DUMP_TYPE_MAX,
263 };
264 
265 struct cnss_dump_entry {
266 	u32 type;
267 	u32 entry_start;
268 	u32 entry_num;
269 };
270 
271 struct cnss_dump_meta_info {
272 	u32 magic;
273 	u32 version;
274 	u32 chipset;
275 	u32 total_entries;
276 	struct cnss_dump_entry entry[CNSS_FW_DUMP_TYPE_MAX];
277 };
278 
279 enum cnss_driver_event_type {
280 	CNSS_DRIVER_EVENT_SERVER_ARRIVE,
281 	CNSS_DRIVER_EVENT_SERVER_EXIT,
282 	CNSS_DRIVER_EVENT_REQUEST_MEM,
283 	CNSS_DRIVER_EVENT_FW_MEM_READY,
284 	CNSS_DRIVER_EVENT_FW_READY,
285 	CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
286 	CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
287 	CNSS_DRIVER_EVENT_REGISTER_DRIVER,
288 	CNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
289 	CNSS_DRIVER_EVENT_RECOVERY,
290 	CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
291 	CNSS_DRIVER_EVENT_POWER_UP,
292 	CNSS_DRIVER_EVENT_POWER_DOWN,
293 	CNSS_DRIVER_EVENT_IDLE_RESTART,
294 	CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
295 	CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
296 	CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND,
297 	CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
298 	CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
299 	CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
300 	CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
301 	CNSS_DRIVER_EVENT_MAX,
302 };
303 
304 enum cnss_driver_state {
305 	CNSS_QMI_WLFW_CONNECTED = 0,
306 	CNSS_FW_MEM_READY,
307 	CNSS_FW_READY,
308 	CNSS_IN_COLD_BOOT_CAL,
309 	CNSS_DRIVER_LOADING,
310 	CNSS_DRIVER_UNLOADING = 5,
311 	CNSS_DRIVER_IDLE_RESTART,
312 	CNSS_DRIVER_IDLE_SHUTDOWN,
313 	CNSS_DRIVER_PROBED,
314 	CNSS_DRIVER_RECOVERY,
315 	CNSS_FW_BOOT_RECOVERY = 10,
316 	CNSS_DEV_ERR_NOTIFY,
317 	CNSS_DRIVER_DEBUG,
318 	CNSS_COEX_CONNECTED,
319 	CNSS_IMS_CONNECTED,
320 	CNSS_IN_SUSPEND_RESUME = 15,
321 	CNSS_IN_REBOOT,
322 	CNSS_COLD_BOOT_CAL_DONE,
323 	CNSS_IN_PANIC,
324 	CNSS_QMI_DEL_SERVER,
325 	CNSS_QMI_DMS_CONNECTED = 20,
326 	CNSS_DAEMON_CONNECTED,
327 	CNSS_PCI_PROBE_DONE,
328 	CNSS_DRIVER_REGISTER,
329 	CNSS_WLAN_HW_DISABLED,
330 	CNSS_FS_READY = 25,
331 	CNSS_DRIVER_REGISTERED,
332 	CNSS_DMS_DEL_SERVER,
333 };
334 
335 struct cnss_recovery_data {
336 	enum cnss_recovery_reason reason;
337 };
338 
339 enum cnss_pins {
340 	CNSS_WLAN_EN,
341 	CNSS_PCIE_TXP,
342 	CNSS_PCIE_TXN,
343 	CNSS_PCIE_RXP,
344 	CNSS_PCIE_RXN,
345 	CNSS_PCIE_REFCLKP,
346 	CNSS_PCIE_REFCLKN,
347 	CNSS_PCIE_RST,
348 	CNSS_PCIE_WAKE,
349 };
350 
351 struct cnss_pin_connect_result {
352 	u32 fw_pwr_pin_result;
353 	u32 fw_phy_io_pin_result;
354 	u32 fw_rf_pin_result;
355 	u32 host_pin_result;
356 };
357 
358 enum cnss_debug_quirks {
359 	LINK_DOWN_SELF_RECOVERY,
360 	SKIP_DEVICE_BOOT,
361 	USE_CORE_ONLY_FW,
362 	SKIP_RECOVERY,
363 	QMI_BYPASS,
364 	ENABLE_WALTEST,
365 	ENABLE_PCI_LINK_DOWN_PANIC,
366 	FBC_BYPASS,
367 	ENABLE_DAEMON_SUPPORT,
368 	DISABLE_DRV,
369 	DISABLE_IO_COHERENCY,
370 	IGNORE_PCI_LINK_FAILURE,
371 	DISABLE_TIME_SYNC,
372 	FORCE_ONE_MSI,
373 	QUIRK_MAX_VALUE
374 };
375 
376 enum cnss_bdf_type {
377 	CNSS_BDF_BIN,
378 	CNSS_BDF_ELF,
379 	CNSS_BDF_REGDB = 4,
380 	CNSS_BDF_HDS = 6,
381 };
382 
383 enum cnss_cal_status {
384 	CNSS_CAL_DONE,
385 	CNSS_CAL_TIMEOUT,
386 	CNSS_CAL_FAILURE,
387 };
388 
389 struct cnss_cal_info {
390 	enum cnss_cal_status cal_status;
391 };
392 
393 struct cnss_control_params {
394 	unsigned long quirks;
395 	unsigned int mhi_timeout;
396 	unsigned int mhi_m2_timeout;
397 	unsigned int qmi_timeout;
398 	unsigned int bdf_type;
399 	unsigned int time_sync_period;
400 };
401 
402 struct cnss_tcs_info {
403 	resource_size_t cmd_base_addr;
404 	void __iomem *cmd_base_addr_io;
405 };
406 
407 struct cnss_cpr_info {
408 	resource_size_t tcs_cmd_data_addr;
409 	void __iomem *tcs_cmd_data_addr_io;
410 	u32 cpr_pmic_addr;
411 	u32 voltage;
412 };
413 
414 enum cnss_ce_index {
415 	CNSS_CE_00,
416 	CNSS_CE_01,
417 	CNSS_CE_02,
418 	CNSS_CE_03,
419 	CNSS_CE_04,
420 	CNSS_CE_05,
421 	CNSS_CE_06,
422 	CNSS_CE_07,
423 	CNSS_CE_08,
424 	CNSS_CE_09,
425 	CNSS_CE_10,
426 	CNSS_CE_11,
427 	CNSS_CE_COMMON,
428 };
429 
430 struct cnss_dms_data {
431 	u32 mac_valid;
432 	u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
433 };
434 
435 enum cnss_timeout_type {
436 	CNSS_TIMEOUT_QMI,
437 	CNSS_TIMEOUT_POWER_UP,
438 	CNSS_TIMEOUT_IDLE_RESTART,
439 	CNSS_TIMEOUT_CALIBRATION,
440 	CNSS_TIMEOUT_WLAN_WATCHDOG,
441 	CNSS_TIMEOUT_RDDM,
442 	CNSS_TIMEOUT_RECOVERY,
443 	CNSS_TIMEOUT_DAEMON_CONNECTION,
444 };
445 
446 struct cnss_sol_gpio {
447 	int dev_sol_gpio;
448 	int dev_sol_irq;
449 	u32 dev_sol_counter;
450 	int host_sol_gpio;
451 };
452 
453 struct cnss_plat_data {
454 	struct platform_device *plat_dev;
455 	void *bus_priv;
456 	enum cnss_dev_bus_type bus_type;
457 	struct list_head vreg_list;
458 	struct list_head clk_list;
459 	struct cnss_pinctrl_info pinctrl_info;
460 	struct cnss_sol_gpio sol_gpio;
461 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
462 	struct cnss_subsys_info subsys_info;
463 #endif
464 	struct cnss_ramdump_info ramdump_info;
465 	struct cnss_ramdump_info_v2 ramdump_info_v2;
466 #if IS_ENABLED(CONFIG_ESOC)
467 	struct cnss_esoc_info esoc_info;
468 #endif
469 	struct cnss_interconnect_cfg icc;
470 	struct notifier_block modem_nb;
471 	struct notifier_block reboot_nb;
472 	struct notifier_block panic_nb;
473 	struct cnss_platform_cap cap;
474 	struct pm_qos_request qos_request;
475 	struct cnss_device_version device_version;
476 	u32 rc_num;
477 	unsigned long device_id;
478 	enum cnss_driver_status driver_status;
479 	u32 recovery_count;
480 	u8 recovery_enabled;
481 	u8 recovery_pcss_enabled;
482 	u8 hds_enabled;
483 	unsigned long driver_state;
484 	struct list_head event_list;
485 	spinlock_t event_lock; /* spinlock for driver work event handling */
486 	struct work_struct event_work;
487 	struct workqueue_struct *event_wq;
488 	struct work_struct recovery_work;
489 	struct delayed_work wlan_reg_driver_work;
490 	struct qmi_handle qmi_wlfw;
491 	struct qmi_handle qmi_dms;
492 	struct wlfw_rf_chip_info chip_info;
493 	struct wlfw_rf_board_info board_info;
494 	struct wlfw_soc_info soc_info;
495 	struct wlfw_fw_version_info fw_version_info;
496 	struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM];
497 	char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN + 1];
498 	u32 otp_version;
499 	u32 fw_mem_seg_len;
500 	struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
501 	struct cnss_fw_mem m3_mem;
502 	struct cnss_fw_mem *cal_mem;
503 	u64 cal_time;
504 	bool cbc_file_download;
505 	u32 cal_file_size;
506 	struct completion daemon_connected;
507 	u32 qdss_mem_seg_len;
508 	struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
509 	u32 *qdss_reg;
510 	struct cnss_pin_connect_result pin_result;
511 	struct dentry *root_dentry;
512 	atomic_t pm_count;
513 	struct timer_list fw_boot_timer;
514 	struct completion power_up_complete;
515 	struct completion cal_complete;
516 	struct mutex dev_lock; /* mutex for register access through debugfs */
517 	struct mutex driver_ops_lock; /* mutex for external driver ops */
518 	struct cnss_wlan_driver *driver_ops;
519 	u32 device_freq_hz;
520 	u32 diag_reg_read_addr;
521 	u32 diag_reg_read_mem_type;
522 	u32 diag_reg_read_len;
523 	u8 *diag_reg_read_buf;
524 	u8 cal_done;
525 	u8 powered_on;
526 	u8 use_fw_path_with_prefix;
527 	char firmware_name[MAX_FIRMWARE_NAME_LEN];
528 	char fw_fallback_name[MAX_FIRMWARE_NAME_LEN];
529 	u8 *sram_dump;
530 	struct completion rddm_complete;
531 	struct completion recovery_complete;
532 	struct cnss_control_params ctrl_params;
533 	struct cnss_cpr_info cpr_info;
534 	u64 antenna;
535 	u64 grant;
536 	struct qmi_handle coex_qmi;
537 	struct qmi_handle ims_qmi;
538 	struct qmi_txn txn;
539 	struct wakeup_source *recovery_ws;
540 	u64 dynamic_feature;
541 	void *get_info_cb_ctx;
542 	int (*get_info_cb)(void *ctx, void *event, int event_len);
543 	bool cbc_enabled;
544 	u8 use_pm_domain;
545 	u8 use_nv_mac;
546 	u8 set_wlaon_pwr_ctrl;
547 	struct cnss_tcs_info tcs_info;
548 	bool fw_pcie_gen_switch;
549 	u64 fw_caps;
550 	u8 pcie_gen_speed;
551 	struct iommu_domain *audio_iommu_domain;
552 	struct cnss_dms_data dms;
553 	int power_up_error;
554 	u32 hw_trc_override;
555 	u8 charger_mode;
556 	struct mbox_client mbox_client_data;
557 	struct mbox_chan *mbox_chan;
558 	const char *vreg_ol_cpr, *vreg_ipa;
559 	const char **pdc_init_table, **vreg_pdc_map, **pmu_vreg_map;
560 	int pdc_init_table_len, vreg_pdc_map_len, pmu_vreg_map_len;
561 	bool adsp_pc_enabled;
562 	u64 feature_list;
563 	u32 dt_type;
564 	struct kobject *wifi_kobj;
565 	u16 hang_event_data_len;
566 	u32 hang_data_addr_offset;
567 	/* bitmap to detect FEM combination */
568 	u8 hwid_bitmap;
569 	enum cnss_driver_mode driver_mode;
570 	uint32_t num_shadow_regs_v3;
571 	bool sec_peri_feature_disable;
572 	struct device_node *dev_node;
573 };
574 
575 #if IS_ENABLED(CONFIG_ARCH_QCOM)
576 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
577 {
578 	u64 ticks = __arch_counter_get_cntvct();
579 
580 	do_div(ticks, TIME_CLOCK_FREQ_HZ / 100000);
581 
582 	return ticks * 10;
583 }
584 #else
585 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
586 {
587 	struct timespec64 ts;
588 
589 	ktime_get_ts64(&ts);
590 
591 	return (ts.tv_sec * 1000000) + (ts.tv_nsec / 1000);
592 }
593 #endif
594 
595 int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv);
596 int cnss_wlan_hw_enable(void);
597 struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev);
598 void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv);
599 void cnss_pm_relax(struct cnss_plat_data *plat_priv);
600 int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
601 			   enum cnss_driver_event_type type,
602 			   u32 flags, void *data);
603 int cnss_get_vreg_type(struct cnss_plat_data *plat_priv,
604 		       enum cnss_vreg_type type);
605 void cnss_put_vreg_type(struct cnss_plat_data *plat_priv,
606 			enum cnss_vreg_type type);
607 int cnss_vreg_on_type(struct cnss_plat_data *plat_priv,
608 		      enum cnss_vreg_type type);
609 int cnss_vreg_off_type(struct cnss_plat_data *plat_priv,
610 		       enum cnss_vreg_type type);
611 int cnss_get_clk(struct cnss_plat_data *plat_priv);
612 void cnss_put_clk(struct cnss_plat_data *plat_priv);
613 int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv,
614 			  enum cnss_vreg_type type);
615 int cnss_get_pinctrl(struct cnss_plat_data *plat_priv);
616 int cnss_get_wlan_sw_ctrl(struct cnss_plat_data *plat_priv);
617 int cnss_power_on_device(struct cnss_plat_data *plat_priv, bool reset);
618 void cnss_power_off_device(struct cnss_plat_data *plat_priv);
619 bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv);
620 int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv);
621 int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv);
622 int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv);
623 int cnss_init_dev_sol_irq(struct cnss_plat_data *plat_priv);
624 int cnss_deinit_dev_sol_irq(struct cnss_plat_data *plat_priv);
625 int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value);
626 int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv);
627 int cnss_register_subsys(struct cnss_plat_data *plat_priv);
628 void cnss_unregister_subsys(struct cnss_plat_data *plat_priv);
629 int cnss_register_ramdump(struct cnss_plat_data *plat_priv);
630 void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
631 int cnss_do_ramdump(struct cnss_plat_data *plat_priv);
632 int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv);
633 void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
634 int cnss_get_cpr_info(struct cnss_plat_data *plat_priv);
635 int cnss_update_cpr_info(struct cnss_plat_data *plat_priv);
636 int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
637 		  phys_addr_t *pa, unsigned long attrs);
638 int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
639 			     enum cnss_fw_dump_type type, int seg_no,
640 			     void *va, phys_addr_t pa, size_t size);
641 int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
642 				enum cnss_fw_dump_type type, int seg_no,
643 				void *va, phys_addr_t pa, size_t size);
644 int cnss_enable_int_pow_amp_vreg(struct cnss_plat_data *plat_priv);
645 int cnss_get_tcs_info(struct cnss_plat_data *plat_priv);
646 unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
647 			      enum cnss_timeout_type);
648 int cnss_aop_mbox_init(struct cnss_plat_data *plat_priv);
649 int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv);
650 int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *msg);
651 void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv);
652 int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
653 			      struct wlfw_pmu_cfg_v01 *fw_pmu_cfg);
654 int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
655 				 const struct firmware **fw_entry,
656 				 const char *filename);
657 int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
658 			  enum cnss_feature_v01 feature);
659 int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
660 			    enum cnss_feature_v01 feature);
661 int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
662 			  u64 *feature_list);
663 int cnss_get_input_gpio_value(struct cnss_plat_data *plat_priv, int gpio_num);
664 bool cnss_check_driver_loading_allowed(void);
665 int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv);
666 #endif /* _CNSS_MAIN_H */
667