1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "bus.h" 8 #include "debug.h" 9 #include "pci.h" 10 11 enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev) 12 { 13 if (!dev) 14 return CNSS_BUS_NONE; 15 16 if (!dev->bus) 17 return CNSS_BUS_NONE; 18 19 if (memcmp(dev->bus->name, "pci", 3) == 0) 20 return CNSS_BUS_PCI; 21 else 22 return CNSS_BUS_NONE; 23 } 24 25 enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv) 26 { 27 int ret; 28 struct device *dev; 29 u32 bus_type_dt = CNSS_BUS_NONE; 30 31 if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) { 32 dev = &plat_priv->plat_dev->dev; 33 ret = of_property_read_u32(dev->of_node, "qcom,bus-type", 34 &bus_type_dt); 35 if (!ret) 36 if (bus_type_dt < CNSS_BUS_MAX) 37 cnss_pr_dbg("Got bus type[%u] from dt\n", 38 bus_type_dt); 39 else 40 bus_type_dt = CNSS_BUS_NONE; 41 else 42 cnss_pr_err("No bus type for multi-exchg dt\n"); 43 44 return bus_type_dt; 45 } 46 47 switch (plat_priv->device_id) { 48 case QCA6174_DEVICE_ID: 49 case QCA6290_DEVICE_ID: 50 case QCA6390_DEVICE_ID: 51 case QCN7605_DEVICE_ID: 52 case QCA6490_DEVICE_ID: 53 case KIWI_DEVICE_ID: 54 case MANGO_DEVICE_ID: 55 case PEACH_DEVICE_ID: 56 return CNSS_BUS_PCI; 57 default: 58 cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id); 59 return CNSS_BUS_NONE; 60 } 61 } 62 63 void *cnss_bus_dev_to_bus_priv(struct device *dev) 64 { 65 if (!dev) 66 return NULL; 67 68 switch (cnss_get_dev_bus_type(dev)) { 69 case CNSS_BUS_PCI: 70 return cnss_get_pci_priv(to_pci_dev(dev)); 71 default: 72 return NULL; 73 } 74 } 75 76 struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev) 77 { 78 void *bus_priv; 79 80 if (!dev) 81 return cnss_get_plat_priv(NULL); 82 83 bus_priv = cnss_bus_dev_to_bus_priv(dev); 84 if (!bus_priv) 85 return NULL; 86 87 switch (cnss_get_dev_bus_type(dev)) { 88 case CNSS_BUS_PCI: 89 return cnss_pci_priv_to_plat_priv(bus_priv); 90 default: 91 return NULL; 92 } 93 } 94 95 int cnss_bus_init(struct cnss_plat_data *plat_priv) 96 { 97 if (!plat_priv) 98 return -ENODEV; 99 100 switch (plat_priv->bus_type) { 101 case CNSS_BUS_PCI: 102 return cnss_pci_init(plat_priv); 103 default: 104 cnss_pr_err("Unsupported bus type: %d\n", 105 plat_priv->bus_type); 106 return -EINVAL; 107 } 108 } 109 110 void cnss_bus_deinit(struct cnss_plat_data *plat_priv) 111 { 112 if (!plat_priv) 113 return; 114 115 switch (plat_priv->bus_type) { 116 case CNSS_BUS_PCI: 117 return cnss_pci_deinit(plat_priv); 118 default: 119 cnss_pr_err("Unsupported bus type: %d\n", 120 plat_priv->bus_type); 121 return; 122 } 123 } 124 125 void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv, 126 char *prefix_name, char *name) 127 { 128 if (!plat_priv) 129 return; 130 131 switch (plat_priv->bus_type) { 132 case CNSS_BUS_PCI: 133 return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv, 134 prefix_name, name); 135 default: 136 cnss_pr_err("Unsupported bus type: %d\n", 137 plat_priv->bus_type); 138 return; 139 } 140 } 141 142 int cnss_bus_load_tme_patch(struct cnss_plat_data *plat_priv) 143 { 144 if (!plat_priv) 145 return -ENODEV; 146 147 switch (plat_priv->bus_type) { 148 case CNSS_BUS_PCI: 149 return cnss_pci_load_tme_patch(plat_priv->bus_priv); 150 default: 151 cnss_pr_err("Unsupported bus type: %d\n", 152 plat_priv->bus_type); 153 return -EINVAL; 154 } 155 } 156 157 int cnss_bus_load_m3(struct cnss_plat_data *plat_priv) 158 { 159 if (!plat_priv) 160 return -ENODEV; 161 162 switch (plat_priv->bus_type) { 163 case CNSS_BUS_PCI: 164 return cnss_pci_load_m3(plat_priv->bus_priv); 165 default: 166 cnss_pr_err("Unsupported bus type: %d\n", 167 plat_priv->bus_type); 168 return -EINVAL; 169 } 170 } 171 172 int cnss_bus_load_aux(struct cnss_plat_data *plat_priv) 173 { 174 if (!plat_priv) 175 return -ENODEV; 176 177 switch (plat_priv->bus_type) { 178 case CNSS_BUS_PCI: 179 return cnss_pci_load_aux(plat_priv->bus_priv); 180 default: 181 cnss_pr_err("Unsupported bus type: %d\n", 182 plat_priv->bus_type); 183 return -EINVAL; 184 } 185 } 186 187 int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv) 188 { 189 if (!plat_priv) 190 return -ENODEV; 191 192 switch (plat_priv->bus_type) { 193 case CNSS_BUS_PCI: 194 return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv); 195 default: 196 cnss_pr_err("Unsupported bus type: %d\n", 197 plat_priv->bus_type); 198 return -EINVAL; 199 } 200 } 201 202 int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv) 203 { 204 if (!plat_priv) 205 return -ENODEV; 206 207 switch (plat_priv->bus_type) { 208 case CNSS_BUS_PCI: 209 return cnss_pci_alloc_fw_mem(plat_priv->bus_priv); 210 default: 211 cnss_pr_err("Unsupported bus type: %d\n", 212 plat_priv->bus_type); 213 return -EINVAL; 214 } 215 } 216 217 int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv) 218 { 219 if (!plat_priv) 220 return -ENODEV; 221 222 switch (plat_priv->bus_type) { 223 case CNSS_BUS_PCI: 224 return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv); 225 default: 226 cnss_pr_err("Unsupported bus type: %d\n", 227 plat_priv->bus_type); 228 return -EINVAL; 229 } 230 } 231 232 void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv) 233 { 234 if (!plat_priv) 235 return; 236 237 switch (plat_priv->bus_type) { 238 case CNSS_BUS_PCI: 239 cnss_pci_free_qdss_mem(plat_priv->bus_priv); 240 return; 241 default: 242 cnss_pr_err("Unsupported bus type: %d\n", 243 plat_priv->bus_type); 244 return; 245 } 246 } 247 248 u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv) 249 { 250 if (!plat_priv) 251 return -ENODEV; 252 253 switch (plat_priv->bus_type) { 254 case CNSS_BUS_PCI: 255 return cnss_pci_get_wake_msi(plat_priv->bus_priv); 256 default: 257 cnss_pr_err("Unsupported bus type: %d\n", 258 plat_priv->bus_type); 259 return -EINVAL; 260 } 261 } 262 263 int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv) 264 { 265 if (!plat_priv) 266 return -ENODEV; 267 268 switch (plat_priv->bus_type) { 269 case CNSS_BUS_PCI: 270 return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv); 271 default: 272 cnss_pr_err("Unsupported bus type: %d\n", 273 plat_priv->bus_type); 274 return -EINVAL; 275 } 276 } 277 278 int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv) 279 { 280 if (!plat_priv) 281 return -ENODEV; 282 283 switch (plat_priv->bus_type) { 284 case CNSS_BUS_PCI: 285 return cnss_pci_qmi_send_get(plat_priv->bus_priv); 286 default: 287 cnss_pr_err("Unsupported bus type: %d\n", 288 plat_priv->bus_type); 289 return -EINVAL; 290 } 291 } 292 293 int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv) 294 { 295 if (!plat_priv) 296 return -ENODEV; 297 298 switch (plat_priv->bus_type) { 299 case CNSS_BUS_PCI: 300 return cnss_pci_qmi_send_put(plat_priv->bus_priv); 301 default: 302 cnss_pr_err("Unsupported bus type: %d\n", 303 plat_priv->bus_type); 304 return -EINVAL; 305 } 306 } 307 308 void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t) 309 { 310 struct cnss_plat_data *plat_priv = 311 from_timer(plat_priv, t, fw_boot_timer); 312 313 if (!plat_priv) 314 return; 315 316 switch (plat_priv->bus_type) { 317 case CNSS_BUS_PCI: 318 return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv); 319 default: 320 cnss_pr_err("Unsupported bus type: %d\n", 321 plat_priv->bus_type); 322 return; 323 } 324 } 325 326 void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic) 327 { 328 if (!plat_priv) 329 return; 330 331 switch (plat_priv->bus_type) { 332 case CNSS_BUS_PCI: 333 return cnss_pci_collect_dump_info(plat_priv->bus_priv, 334 in_panic); 335 default: 336 cnss_pr_err("Unsupported bus type: %d\n", 337 plat_priv->bus_type); 338 return; 339 } 340 } 341 342 void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv) 343 { 344 if (!plat_priv) 345 return; 346 347 switch (plat_priv->bus_type) { 348 case CNSS_BUS_PCI: 349 return cnss_pci_device_crashed(plat_priv->bus_priv); 350 default: 351 cnss_pr_err("Unsupported bus type: %d\n", 352 plat_priv->bus_type); 353 return; 354 } 355 } 356 357 int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv) 358 { 359 if (!plat_priv) 360 return -ENODEV; 361 362 switch (plat_priv->bus_type) { 363 case CNSS_BUS_PCI: 364 return cnss_pci_call_driver_probe(plat_priv->bus_priv); 365 default: 366 cnss_pr_err("Unsupported bus type: %d\n", 367 plat_priv->bus_type); 368 return -EINVAL; 369 } 370 } 371 372 int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv) 373 { 374 if (!plat_priv) 375 return -ENODEV; 376 377 switch (plat_priv->bus_type) { 378 case CNSS_BUS_PCI: 379 return cnss_pci_call_driver_remove(plat_priv->bus_priv); 380 default: 381 cnss_pr_err("Unsupported bus type: %d\n", 382 plat_priv->bus_type); 383 return -EINVAL; 384 } 385 } 386 387 int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv) 388 { 389 if (!plat_priv) 390 return -ENODEV; 391 392 switch (plat_priv->bus_type) { 393 case CNSS_BUS_PCI: 394 return cnss_pci_dev_powerup(plat_priv->bus_priv); 395 default: 396 cnss_pr_err("Unsupported bus type: %d\n", 397 plat_priv->bus_type); 398 return -EINVAL; 399 } 400 } 401 402 int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv) 403 { 404 if (!plat_priv) 405 return -ENODEV; 406 407 switch (plat_priv->bus_type) { 408 case CNSS_BUS_PCI: 409 return cnss_pci_dev_shutdown(plat_priv->bus_priv); 410 default: 411 cnss_pr_err("Unsupported bus type: %d\n", 412 plat_priv->bus_type); 413 return -EINVAL; 414 } 415 } 416 417 int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv) 418 { 419 if (!plat_priv) 420 return -ENODEV; 421 422 switch (plat_priv->bus_type) { 423 case CNSS_BUS_PCI: 424 return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv); 425 default: 426 cnss_pr_err("Unsupported bus type: %d\n", 427 plat_priv->bus_type); 428 return -EINVAL; 429 } 430 } 431 432 int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv) 433 { 434 if (!plat_priv) 435 return -ENODEV; 436 437 switch (plat_priv->bus_type) { 438 case CNSS_BUS_PCI: 439 return cnss_pci_dev_ramdump(plat_priv->bus_priv); 440 default: 441 cnss_pr_err("Unsupported bus type: %d\n", 442 plat_priv->bus_type); 443 return -EINVAL; 444 } 445 } 446 447 int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data) 448 { 449 if (!plat_priv) 450 return -ENODEV; 451 452 switch (plat_priv->bus_type) { 453 case CNSS_BUS_PCI: 454 return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data); 455 default: 456 cnss_pr_err("Unsupported bus type: %d\n", 457 plat_priv->bus_type); 458 return -EINVAL; 459 } 460 } 461 462 int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv) 463 { 464 if (!plat_priv) 465 return -ENODEV; 466 467 switch (plat_priv->bus_type) { 468 case CNSS_BUS_PCI: 469 return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv); 470 default: 471 cnss_pr_err("Unsupported bus type: %d\n", 472 plat_priv->bus_type); 473 return -EINVAL; 474 } 475 } 476 477 int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv, 478 int modem_current_status) 479 { 480 if (!plat_priv) 481 return -ENODEV; 482 483 switch (plat_priv->bus_type) { 484 case CNSS_BUS_PCI: 485 return cnss_pci_call_driver_modem_status(plat_priv->bus_priv, 486 modem_current_status); 487 default: 488 cnss_pr_err("Unsupported bus type: %d\n", 489 plat_priv->bus_type); 490 return -EINVAL; 491 } 492 } 493 494 int cnss_bus_update_status(struct cnss_plat_data *plat_priv, 495 enum cnss_driver_status status) 496 { 497 if (!plat_priv) 498 return -ENODEV; 499 500 switch (plat_priv->bus_type) { 501 case CNSS_BUS_PCI: 502 return cnss_pci_update_status(plat_priv->bus_priv, status); 503 default: 504 cnss_pr_err("Unsupported bus type: %d\n", 505 plat_priv->bus_type); 506 return -EINVAL; 507 } 508 } 509 510 int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv, 511 enum cnss_driver_status status, void *data) 512 { 513 if (!plat_priv) 514 return -ENODEV; 515 516 switch (plat_priv->bus_type) { 517 case CNSS_BUS_PCI: 518 return cnss_pci_call_driver_uevent(plat_priv->bus_priv, 519 status, data); 520 default: 521 cnss_pr_err("Unsupported bus type: %d\n", 522 plat_priv->bus_type); 523 return -EINVAL; 524 } 525 } 526 527 int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv) 528 { 529 if (!plat_priv) 530 return -ENODEV; 531 532 switch (plat_priv->bus_type) { 533 case CNSS_BUS_PCI: 534 return cnss_pcie_is_device_down(plat_priv->bus_priv); 535 default: 536 cnss_pr_dbg("Unsupported bus type: %d\n", 537 plat_priv->bus_type); 538 return 0; 539 } 540 } 541 542 int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv) 543 { 544 if (!plat_priv) 545 return -ENODEV; 546 547 switch (plat_priv->bus_type) { 548 case CNSS_BUS_PCI: 549 return cnss_pci_check_link_status(plat_priv->bus_priv); 550 default: 551 cnss_pr_dbg("Unsupported bus type: %d\n", 552 plat_priv->bus_type); 553 return 0; 554 } 555 } 556 557 int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv) 558 { 559 if (!plat_priv) 560 return -ENODEV; 561 562 switch (plat_priv->bus_type) { 563 case CNSS_BUS_PCI: 564 return cnss_pci_recover_link_down(plat_priv->bus_priv); 565 default: 566 cnss_pr_dbg("Unsupported bus type: %d\n", 567 plat_priv->bus_type); 568 return -EINVAL; 569 } 570 } 571 572 int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset, 573 u32 *val, bool raw_access) 574 { 575 if (!plat_priv) 576 return -ENODEV; 577 578 switch (plat_priv->bus_type) { 579 case CNSS_BUS_PCI: 580 return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset, 581 val, raw_access); 582 default: 583 cnss_pr_dbg("Unsupported bus type: %d\n", 584 plat_priv->bus_type); 585 return 0; 586 } 587 } 588 589 int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset, 590 u32 val, bool raw_access) 591 { 592 if (!plat_priv) 593 return -ENODEV; 594 595 switch (plat_priv->bus_type) { 596 case CNSS_BUS_PCI: 597 return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset, 598 val, raw_access); 599 default: 600 cnss_pr_dbg("Unsupported bus type: %d\n", 601 plat_priv->bus_type); 602 return 0; 603 } 604 } 605 606 int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size) 607 { 608 if (!plat_priv) 609 return -ENODEV; 610 611 switch (plat_priv->bus_type) { 612 case CNSS_BUS_PCI: 613 return cnss_pci_get_iova(plat_priv->bus_priv, addr, size); 614 default: 615 cnss_pr_err("Unsupported bus type: %d\n", 616 plat_priv->bus_type); 617 return -EINVAL; 618 } 619 } 620 621 int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr, 622 u64 *size) 623 { 624 if (!plat_priv) 625 return -ENODEV; 626 627 switch (plat_priv->bus_type) { 628 case CNSS_BUS_PCI: 629 return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size); 630 default: 631 cnss_pr_err("Unsupported bus type: %d\n", 632 plat_priv->bus_type); 633 return -EINVAL; 634 } 635 } 636 637 bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv) 638 { 639 if (!plat_priv) 640 return false; 641 642 switch (plat_priv->bus_type) { 643 case CNSS_BUS_PCI: 644 return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv); 645 default: 646 cnss_pr_err("Unsupported bus type: %d\n", 647 plat_priv->bus_type); 648 return false; 649 } 650 } 651 652 int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv, 653 unsigned int time_sync_period) 654 { 655 if (!plat_priv) 656 return -ENODEV; 657 658 switch (plat_priv->bus_type) { 659 case CNSS_BUS_PCI: 660 return cnss_pci_update_time_sync_period(plat_priv->bus_priv, 661 time_sync_period); 662 default: 663 cnss_pr_err("Unsupported bus type: %d\n", 664 plat_priv->bus_type); 665 return -EINVAL; 666 } 667 } 668 669 int cnss_bus_set_therm_cdev_state(struct cnss_plat_data *plat_priv, 670 unsigned long thermal_state, 671 int tcdev_id) 672 { 673 if (!plat_priv) 674 return -ENODEV; 675 676 switch (plat_priv->bus_type) { 677 case CNSS_BUS_PCI: 678 return cnss_pci_set_therm_cdev_state(plat_priv->bus_priv, 679 thermal_state, 680 tcdev_id); 681 default: 682 cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type); 683 return -EINVAL; 684 } 685 } 686 687 int cnss_bus_get_msi_assignment(struct cnss_plat_data *plat_priv, 688 char *msi_name, 689 int *num_vectors, 690 u32 *user_base_data, 691 u32 *base_vector) 692 { 693 if (!plat_priv) 694 return -ENODEV; 695 696 switch (plat_priv->bus_type) { 697 case CNSS_BUS_PCI: 698 return cnss_pci_get_user_msi_assignment(plat_priv->bus_priv, 699 msi_name, 700 num_vectors, 701 user_base_data, 702 base_vector); 703 default: 704 cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type); 705 return -EINVAL; 706 } 707 } 708 709 #if IS_ENABLED(CONFIG_MHI_BUS_MISC) 710 void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv) 711 { 712 struct cnss_pci_data *pci_priv; 713 714 pci_priv = plat_priv->bus_priv; 715 if (!pci_priv) { 716 cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n"); 717 return; 718 } 719 720 switch (plat_priv->bus_type) { 721 case CNSS_BUS_PCI: 722 /* MHI satellite configuration is only for KIWI V2 and 723 * that too only in DRV mode. 724 */ 725 if (plat_priv->device_id == KIWI_DEVICE_ID && 726 plat_priv->device_version.major_version == FW_V2_NUMBER) { 727 cnss_pr_dbg("Remove MHI satellite configuration\n"); 728 return cnss_mhi_controller_set_base(pci_priv, 0); 729 } 730 break; 731 default: 732 cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n", 733 plat_priv->bus_type); 734 return; 735 } 736 737 return; 738 } 739 #else 740 void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv) 741 { 742 } 743 #endif 744