1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MON_BUFFER_ADDR_H_ 27 #define _MON_BUFFER_ADDR_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 32 33 #define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 34 35 36 struct mon_buffer_addr { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t buffer_virt_addr_31_0 : 32; 39 uint32_t buffer_virt_addr_63_32 : 32; 40 uint32_t dma_length : 12, 41 reserved_2a : 4, 42 msdu_continuation : 1, 43 truncated : 1, 44 reserved_2b : 14; 45 uint32_t tlv64_padding : 32; 46 #else 47 uint32_t buffer_virt_addr_31_0 : 32; 48 uint32_t buffer_virt_addr_63_32 : 32; 49 uint32_t reserved_2b : 14, 50 truncated : 1, 51 msdu_continuation : 1, 52 reserved_2a : 4, 53 dma_length : 12; 54 uint32_t tlv64_padding : 32; 55 #endif 56 }; 57 58 59 60 61 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 62 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 63 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 64 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff 65 66 67 68 69 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 70 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 71 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 72 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 73 74 75 76 77 #define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 78 #define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 79 #define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 80 #define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff 81 82 83 84 85 #define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 86 #define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 87 #define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 88 #define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 89 90 91 92 93 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 94 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 95 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 96 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 97 98 99 100 101 #define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 102 #define MON_BUFFER_ADDR_TRUNCATED_LSB 17 103 #define MON_BUFFER_ADDR_TRUNCATED_MSB 17 104 #define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 105 106 107 108 109 #define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 110 #define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 111 #define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 112 #define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 113 114 115 116 117 #define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 118 #define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 119 #define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 120 #define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 121 122 123 124 #endif 125