1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_MPDU_START_H_ 27 #define _TX_MPDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_MPDU_START 10 32 33 #define NUM_OF_QWORDS_TX_MPDU_START 5 34 35 36 struct tx_mpdu_start { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t mpdu_length : 14, 39 frame_not_from_tqm : 1, 40 vht_control_present : 1, 41 mpdu_header_length : 8, 42 retry_count : 7, 43 wds : 1; 44 uint32_t pn_31_0 : 32; 45 uint32_t pn_47_32 : 16, 46 mpdu_sequence_number : 12, 47 raw_already_encrypted : 1, 48 frame_type : 2, 49 txdma_dropped_mpdu_warning : 1; 50 uint32_t iv_byte_0 : 8, 51 iv_byte_1 : 8, 52 iv_byte_2 : 8, 53 iv_byte_3 : 8; 54 uint32_t iv_byte_4 : 8, 55 iv_byte_5 : 8, 56 iv_byte_6 : 8, 57 iv_byte_7 : 8; 58 uint32_t iv_byte_8 : 8, 59 iv_byte_9 : 8, 60 iv_byte_10 : 8, 61 iv_byte_11 : 8; 62 uint32_t iv_byte_12 : 8, 63 iv_byte_13 : 8, 64 iv_byte_14 : 8, 65 iv_byte_15 : 8; 66 uint32_t iv_byte_16 : 8, 67 iv_byte_17 : 8, 68 iv_len : 5, 69 icv_len : 5, 70 vht_control_offset : 6; 71 uint32_t mpdu_type : 1, 72 transmit_bw_restriction : 1, 73 allowed_transmit_bw : 4, 74 tx_notify_frame : 3, 75 reserved_8a : 23; 76 uint32_t tlv64_padding : 32; 77 #else 78 uint32_t wds : 1, 79 retry_count : 7, 80 mpdu_header_length : 8, 81 vht_control_present : 1, 82 frame_not_from_tqm : 1, 83 mpdu_length : 14; 84 uint32_t pn_31_0 : 32; 85 uint32_t txdma_dropped_mpdu_warning : 1, 86 frame_type : 2, 87 raw_already_encrypted : 1, 88 mpdu_sequence_number : 12, 89 pn_47_32 : 16; 90 uint32_t iv_byte_3 : 8, 91 iv_byte_2 : 8, 92 iv_byte_1 : 8, 93 iv_byte_0 : 8; 94 uint32_t iv_byte_7 : 8, 95 iv_byte_6 : 8, 96 iv_byte_5 : 8, 97 iv_byte_4 : 8; 98 uint32_t iv_byte_11 : 8, 99 iv_byte_10 : 8, 100 iv_byte_9 : 8, 101 iv_byte_8 : 8; 102 uint32_t iv_byte_15 : 8, 103 iv_byte_14 : 8, 104 iv_byte_13 : 8, 105 iv_byte_12 : 8; 106 uint32_t vht_control_offset : 6, 107 icv_len : 5, 108 iv_len : 5, 109 iv_byte_17 : 8, 110 iv_byte_16 : 8; 111 uint32_t reserved_8a : 23, 112 tx_notify_frame : 3, 113 allowed_transmit_bw : 4, 114 transmit_bw_restriction : 1, 115 mpdu_type : 1; 116 uint32_t tlv64_padding : 32; 117 #endif 118 }; 119 120 121 122 123 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 124 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 125 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 126 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff 127 128 129 130 131 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 132 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 133 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 134 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 135 136 137 138 139 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 140 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 141 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 142 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 143 144 145 146 147 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 148 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 149 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 150 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 151 152 153 154 155 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 156 #define TX_MPDU_START_RETRY_COUNT_LSB 24 157 #define TX_MPDU_START_RETRY_COUNT_MSB 30 158 #define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 159 160 161 162 163 #define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 164 #define TX_MPDU_START_WDS_LSB 31 165 #define TX_MPDU_START_WDS_MSB 31 166 #define TX_MPDU_START_WDS_MASK 0x0000000080000000 167 168 169 170 171 #define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 172 #define TX_MPDU_START_PN_31_0_LSB 32 173 #define TX_MPDU_START_PN_31_0_MSB 63 174 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 175 176 177 178 179 #define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 180 #define TX_MPDU_START_PN_47_32_LSB 0 181 #define TX_MPDU_START_PN_47_32_MSB 15 182 #define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff 183 184 185 186 187 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 188 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 189 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 190 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 191 192 193 194 195 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 196 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 197 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 198 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 199 200 201 202 203 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 204 #define TX_MPDU_START_FRAME_TYPE_LSB 29 205 #define TX_MPDU_START_FRAME_TYPE_MSB 30 206 #define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 207 208 209 210 211 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 212 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 213 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 214 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 215 216 217 218 219 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 220 #define TX_MPDU_START_IV_BYTE_0_LSB 32 221 #define TX_MPDU_START_IV_BYTE_0_MSB 39 222 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 223 224 225 226 227 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 228 #define TX_MPDU_START_IV_BYTE_1_LSB 40 229 #define TX_MPDU_START_IV_BYTE_1_MSB 47 230 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 231 232 233 234 235 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 236 #define TX_MPDU_START_IV_BYTE_2_LSB 48 237 #define TX_MPDU_START_IV_BYTE_2_MSB 55 238 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 239 240 241 242 243 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 244 #define TX_MPDU_START_IV_BYTE_3_LSB 56 245 #define TX_MPDU_START_IV_BYTE_3_MSB 63 246 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 247 248 249 250 251 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 252 #define TX_MPDU_START_IV_BYTE_4_LSB 0 253 #define TX_MPDU_START_IV_BYTE_4_MSB 7 254 #define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff 255 256 257 258 259 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 260 #define TX_MPDU_START_IV_BYTE_5_LSB 8 261 #define TX_MPDU_START_IV_BYTE_5_MSB 15 262 #define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 263 264 265 266 267 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 268 #define TX_MPDU_START_IV_BYTE_6_LSB 16 269 #define TX_MPDU_START_IV_BYTE_6_MSB 23 270 #define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 271 272 273 274 275 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 276 #define TX_MPDU_START_IV_BYTE_7_LSB 24 277 #define TX_MPDU_START_IV_BYTE_7_MSB 31 278 #define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 279 280 281 282 283 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 284 #define TX_MPDU_START_IV_BYTE_8_LSB 32 285 #define TX_MPDU_START_IV_BYTE_8_MSB 39 286 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 287 288 289 290 291 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 292 #define TX_MPDU_START_IV_BYTE_9_LSB 40 293 #define TX_MPDU_START_IV_BYTE_9_MSB 47 294 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 295 296 297 298 299 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 300 #define TX_MPDU_START_IV_BYTE_10_LSB 48 301 #define TX_MPDU_START_IV_BYTE_10_MSB 55 302 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 303 304 305 306 307 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 308 #define TX_MPDU_START_IV_BYTE_11_LSB 56 309 #define TX_MPDU_START_IV_BYTE_11_MSB 63 310 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 311 312 313 314 315 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 316 #define TX_MPDU_START_IV_BYTE_12_LSB 0 317 #define TX_MPDU_START_IV_BYTE_12_MSB 7 318 #define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff 319 320 321 322 323 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 324 #define TX_MPDU_START_IV_BYTE_13_LSB 8 325 #define TX_MPDU_START_IV_BYTE_13_MSB 15 326 #define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 327 328 329 330 331 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 332 #define TX_MPDU_START_IV_BYTE_14_LSB 16 333 #define TX_MPDU_START_IV_BYTE_14_MSB 23 334 #define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 335 336 337 338 339 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 340 #define TX_MPDU_START_IV_BYTE_15_LSB 24 341 #define TX_MPDU_START_IV_BYTE_15_MSB 31 342 #define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 343 344 345 346 347 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 348 #define TX_MPDU_START_IV_BYTE_16_LSB 32 349 #define TX_MPDU_START_IV_BYTE_16_MSB 39 350 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 351 352 353 354 355 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 356 #define TX_MPDU_START_IV_BYTE_17_LSB 40 357 #define TX_MPDU_START_IV_BYTE_17_MSB 47 358 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 359 360 361 362 363 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 364 #define TX_MPDU_START_IV_LEN_LSB 48 365 #define TX_MPDU_START_IV_LEN_MSB 52 366 #define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 367 368 369 370 371 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 372 #define TX_MPDU_START_ICV_LEN_LSB 53 373 #define TX_MPDU_START_ICV_LEN_MSB 57 374 #define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 375 376 377 378 379 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 380 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 381 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 382 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 383 384 385 386 387 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 388 #define TX_MPDU_START_MPDU_TYPE_LSB 0 389 #define TX_MPDU_START_MPDU_TYPE_MSB 0 390 #define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 391 392 393 394 395 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 396 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 397 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 398 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 399 400 401 402 403 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 404 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 405 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 406 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c 407 408 409 410 411 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 412 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 413 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 414 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 415 416 417 418 419 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 420 #define TX_MPDU_START_RESERVED_8A_LSB 9 421 #define TX_MPDU_START_RESERVED_8A_MSB 31 422 #define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 423 424 425 426 427 #define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 428 #define TX_MPDU_START_TLV64_PADDING_LSB 32 429 #define TX_MPDU_START_TLV64_PADDING_MSB 63 430 #define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 431 432 433 434 #endif 435