1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RXPCU_PPDU_END_INFO_H_ 27 #define _RXPCU_PPDU_END_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phyrx_abort_request_info.h" 32 #include "macrx_abort_request_info.h" 33 #include "rxpcu_ppdu_end_layout_info.h" 34 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 35 36 #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 37 38 39 struct rxpcu_ppdu_end_info { 40 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 41 uint32_t wb_timestamp_lower_32 : 32; 42 uint32_t wb_timestamp_upper_32 : 32; 43 uint32_t rx_antenna : 24, 44 tx_ht_vht_ack : 1, 45 unsupported_mu_nc : 1, 46 otp_txbf_disable : 1, 47 previous_tlv_corrupted : 1, 48 phyrx_abort_request_info_valid : 1, 49 macrx_abort_request_info_valid : 1, 50 reserved : 2; 51 uint32_t coex_bt_tx_from_start_of_rx : 1, 52 coex_bt_tx_after_start_of_rx : 1, 53 coex_wan_tx_from_start_of_rx : 1, 54 coex_wan_tx_after_start_of_rx : 1, 55 coex_wlan_tx_from_start_of_rx : 1, 56 coex_wlan_tx_after_start_of_rx : 1, 57 mpdu_delimiter_errors_seen : 1, 58 ftm_tm : 2, 59 dialog_token : 8, 60 follow_up_dialog_token : 8, 61 bb_captured_channel : 1, 62 bb_captured_reason : 3, 63 bb_captured_timeout : 1, 64 reserved_3 : 2; 65 uint32_t before_mpdu_count_passing_fcs : 10, 66 before_mpdu_count_failing_fcs : 10, 67 after_mpdu_count_passing_fcs : 10, 68 reserved_4 : 2; 69 uint32_t after_mpdu_count_failing_fcs : 10, 70 reserved_5 : 22; 71 uint32_t phy_timestamp_tx_lower_32 : 32; 72 uint32_t phy_timestamp_tx_upper_32 : 32; 73 uint32_t bb_length : 16, 74 bb_data : 1, 75 reserved_8 : 3, 76 first_bt_broadcast_status_details : 12; 77 uint32_t rx_ppdu_duration : 24, 78 reserved_9 : 8; 79 uint32_t ast_index : 16, 80 ast_index_valid : 1, 81 reserved_10 : 3, 82 second_bt_broadcast_status_details : 12; 83 struct phyrx_abort_request_info phyrx_abort_request_info_details; 84 struct macrx_abort_request_info macrx_abort_request_info_details; 85 uint16_t pre_bt_broadcast_status_details : 12, 86 reserved_12a : 4; 87 uint32_t non_qos_sn_info_valid : 1, 88 reserved_13a : 5, 89 non_qos_sn_highest : 12, 90 non_qos_sn_highest_retry_setting : 1, 91 non_qos_sn_lowest : 12, 92 non_qos_sn_lowest_retry_setting : 1; 93 uint32_t qos_sn_1_info_valid : 1, 94 reserved_14a : 1, 95 qos_sn_1_tid : 4, 96 qos_sn_1_highest : 12, 97 qos_sn_1_highest_retry_setting : 1, 98 qos_sn_1_lowest : 12, 99 qos_sn_1_lowest_retry_setting : 1; 100 uint32_t qos_sn_2_info_valid : 1, 101 reserved_15a : 1, 102 qos_sn_2_tid : 4, 103 qos_sn_2_highest : 12, 104 qos_sn_2_highest_retry_setting : 1, 105 qos_sn_2_lowest : 12, 106 qos_sn_2_lowest_retry_setting : 1; 107 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 108 uint32_t corrupted_due_to_fifo_delay : 1, 109 qos_sn_1_more_frag_state : 1, 110 qos_sn_1_frag_num_state : 4, 111 qos_sn_2_more_frag_state : 1, 112 qos_sn_2_frag_num_state : 4, 113 reserved_26a : 21; 114 uint32_t rx_ppdu_end_marker : 32; 115 #else 116 uint32_t wb_timestamp_lower_32 : 32; 117 uint32_t wb_timestamp_upper_32 : 32; 118 uint32_t reserved : 2, 119 macrx_abort_request_info_valid : 1, 120 phyrx_abort_request_info_valid : 1, 121 previous_tlv_corrupted : 1, 122 otp_txbf_disable : 1, 123 unsupported_mu_nc : 1, 124 tx_ht_vht_ack : 1, 125 rx_antenna : 24; 126 uint32_t reserved_3 : 2, 127 bb_captured_timeout : 1, 128 bb_captured_reason : 3, 129 bb_captured_channel : 1, 130 follow_up_dialog_token : 8, 131 dialog_token : 8, 132 ftm_tm : 2, 133 mpdu_delimiter_errors_seen : 1, 134 coex_wlan_tx_after_start_of_rx : 1, 135 coex_wlan_tx_from_start_of_rx : 1, 136 coex_wan_tx_after_start_of_rx : 1, 137 coex_wan_tx_from_start_of_rx : 1, 138 coex_bt_tx_after_start_of_rx : 1, 139 coex_bt_tx_from_start_of_rx : 1; 140 uint32_t reserved_4 : 2, 141 after_mpdu_count_passing_fcs : 10, 142 before_mpdu_count_failing_fcs : 10, 143 before_mpdu_count_passing_fcs : 10; 144 uint32_t reserved_5 : 22, 145 after_mpdu_count_failing_fcs : 10; 146 uint32_t phy_timestamp_tx_lower_32 : 32; 147 uint32_t phy_timestamp_tx_upper_32 : 32; 148 uint32_t first_bt_broadcast_status_details : 12, 149 reserved_8 : 3, 150 bb_data : 1, 151 bb_length : 16; 152 uint32_t reserved_9 : 8, 153 rx_ppdu_duration : 24; 154 uint32_t second_bt_broadcast_status_details : 12, 155 reserved_10 : 3, 156 ast_index_valid : 1, 157 ast_index : 16; 158 struct phyrx_abort_request_info phyrx_abort_request_info_details; 159 uint32_t reserved_12a : 4, 160 pre_bt_broadcast_status_details : 12; 161 struct macrx_abort_request_info macrx_abort_request_info_details; 162 uint32_t non_qos_sn_lowest_retry_setting : 1, 163 non_qos_sn_lowest : 12, 164 non_qos_sn_highest_retry_setting : 1, 165 non_qos_sn_highest : 12, 166 reserved_13a : 5, 167 non_qos_sn_info_valid : 1; 168 uint32_t qos_sn_1_lowest_retry_setting : 1, 169 qos_sn_1_lowest : 12, 170 qos_sn_1_highest_retry_setting : 1, 171 qos_sn_1_highest : 12, 172 qos_sn_1_tid : 4, 173 reserved_14a : 1, 174 qos_sn_1_info_valid : 1; 175 uint32_t qos_sn_2_lowest_retry_setting : 1, 176 qos_sn_2_lowest : 12, 177 qos_sn_2_highest_retry_setting : 1, 178 qos_sn_2_highest : 12, 179 qos_sn_2_tid : 4, 180 reserved_15a : 1, 181 qos_sn_2_info_valid : 1; 182 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 183 uint32_t reserved_26a : 21, 184 qos_sn_2_frag_num_state : 4, 185 qos_sn_2_more_frag_state : 1, 186 qos_sn_1_frag_num_state : 4, 187 qos_sn_1_more_frag_state : 1, 188 corrupted_due_to_fifo_delay : 1; 189 uint32_t rx_ppdu_end_marker : 32; 190 #endif 191 }; 192 193 194 195 196 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 197 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 198 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 199 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 200 201 202 203 204 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 205 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 206 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 207 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 208 209 210 211 212 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 213 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 214 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 215 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 216 217 218 219 220 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 221 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 222 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 223 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 224 225 226 227 228 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 229 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 230 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 231 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 232 233 234 235 236 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 237 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 238 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 239 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 240 241 242 243 244 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 245 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 246 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 247 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 248 249 250 251 252 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 253 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 254 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 255 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 256 257 258 259 260 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 261 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 262 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 263 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 264 265 266 267 268 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 269 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 270 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 271 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 272 273 274 275 276 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 277 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 278 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 279 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 280 281 282 283 284 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 285 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 286 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 287 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 288 289 290 291 292 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 293 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 294 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 295 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 296 297 298 299 300 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 301 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 302 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 303 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 304 305 306 307 308 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 309 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 310 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 311 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 312 313 314 315 316 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 317 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 318 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 319 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 320 321 322 323 324 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 325 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 326 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 327 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 328 329 330 331 332 #define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 333 #define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 334 #define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 335 #define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 336 337 338 339 340 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 341 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 342 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 343 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 344 345 346 347 348 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 349 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 350 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 351 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 352 353 354 355 356 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 357 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 358 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 359 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 360 361 362 363 364 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 365 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 366 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 367 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 368 369 370 371 372 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 373 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 374 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 375 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 376 377 378 379 380 #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 381 #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 382 #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 383 #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 384 385 386 387 388 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 389 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 390 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 391 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 392 393 394 395 396 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 397 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 398 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 399 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 400 401 402 403 404 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 405 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 406 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 407 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 408 409 410 411 412 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 413 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 414 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 415 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 416 417 418 419 420 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 421 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 422 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 423 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 424 425 426 427 428 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 429 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 430 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 431 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 432 433 434 435 436 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 437 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 438 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 439 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 440 441 442 443 444 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 445 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 446 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 447 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 448 449 450 451 452 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 453 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 454 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 455 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 456 457 458 459 460 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 461 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 462 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 463 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 464 465 466 467 468 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 469 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 470 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 471 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 472 473 474 475 476 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 477 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 478 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 479 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 480 481 482 483 484 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 485 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 486 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 487 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 488 489 490 491 492 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 493 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 494 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 495 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 496 497 498 499 500 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 501 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 502 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 503 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 504 505 506 507 508 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 509 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 510 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 511 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 512 513 514 515 516 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 517 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 518 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 519 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 520 521 522 523 524 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 525 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 526 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 527 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 528 529 530 531 532 533 534 535 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 536 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 537 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 538 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 539 540 541 542 543 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 544 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 545 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 546 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 547 548 549 550 551 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 552 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 553 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 554 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 555 556 557 558 559 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 560 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 561 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 562 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 563 564 565 566 567 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 568 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 569 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 570 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 571 572 573 574 575 576 577 578 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 579 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 580 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 581 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 582 583 584 585 586 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 587 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 588 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 589 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 590 591 592 593 594 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 595 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 596 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 597 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 598 599 600 601 602 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 603 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 604 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 605 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 606 607 608 609 610 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 611 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 612 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 613 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 614 615 616 617 618 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 619 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 620 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 621 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 622 623 624 625 626 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 627 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 628 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 629 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 630 631 632 633 634 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 635 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 636 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 637 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 638 639 640 641 642 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 643 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 644 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 645 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 646 647 648 649 650 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 651 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 652 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 653 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 654 655 656 657 658 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 659 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 660 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 661 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 662 663 664 665 666 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 667 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 668 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 669 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 670 671 672 673 674 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 675 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 676 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 677 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 678 679 680 681 682 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 683 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 684 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 685 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 686 687 688 689 690 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 691 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 692 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 693 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 694 695 696 697 698 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 699 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 700 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 701 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 702 703 704 705 706 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 707 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 708 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 709 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 710 711 712 713 714 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 715 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 716 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 717 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 718 719 720 721 722 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 723 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 724 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 725 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 726 727 728 729 730 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 731 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 732 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 733 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 734 735 736 737 738 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 739 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 740 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 741 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 742 743 744 745 746 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 747 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 748 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 749 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 750 751 752 753 754 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 755 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 756 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 757 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 758 759 760 761 762 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 763 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 764 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 765 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 766 767 768 769 770 771 772 773 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 774 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 775 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 776 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 777 778 779 780 781 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 782 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 783 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 784 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 785 786 787 788 789 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 790 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 791 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 792 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 793 794 795 796 797 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 798 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 799 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 800 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 801 802 803 804 805 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 806 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 807 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 808 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 809 810 811 812 813 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 814 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 815 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 816 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 817 818 819 820 821 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 822 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 823 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 824 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 825 826 827 828 829 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 830 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 831 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 832 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 833 834 835 836 837 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 838 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 839 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 840 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 841 842 843 844 845 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 846 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 847 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 848 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 849 850 851 852 853 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 854 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 855 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 856 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 857 858 859 860 861 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 862 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 863 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 864 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 865 866 867 868 869 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 870 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 871 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 872 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 873 874 875 876 877 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 878 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 879 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 880 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 881 882 883 884 885 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 886 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 887 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 888 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 889 890 891 892 893 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 894 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 895 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 896 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 897 898 899 900 901 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 902 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 903 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 904 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 905 906 907 908 909 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 910 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 911 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 912 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 913 914 915 916 917 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 918 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 919 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 920 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 921 922 923 924 925 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 926 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 927 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 928 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 929 930 931 932 933 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 934 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 935 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 936 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 937 938 939 940 941 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 942 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 943 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 944 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 945 946 947 948 949 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 950 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 951 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 952 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 953 954 955 956 957 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 958 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 959 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 960 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 961 962 963 964 965 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 966 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 967 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 968 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 969 970 971 972 973 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 974 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 975 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 976 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 977 978 979 980 981 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 982 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 983 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 984 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 985 986 987 988 989 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 990 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 991 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 992 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 993 994 995 996 997 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 998 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 999 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 1000 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 1001 1002 1003 1004 1005 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 1006 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 1007 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 1008 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 1009 1010 1011 1012 1013 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 1014 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 1015 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 1016 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 1017 1018 1019 1020 1021 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 1022 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 1023 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 1024 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 1025 1026 1027 1028 1029 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 1030 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 1031 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 1032 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 1033 1034 1035 1036 1037 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 1038 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 1039 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 1040 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 1041 1042 1043 1044 1045 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 1046 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 1047 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 1048 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 1049 1050 1051 1052 1053 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 1054 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 1055 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 1056 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 1057 1058 1059 1060 1061 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 1062 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 1063 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 1064 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 1065 1066 1067 1068 1069 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 1070 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 1071 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 1072 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 1073 1074 1075 1076 1077 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 1078 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 1079 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 1080 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 1081 1082 1083 1084 1085 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 1086 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 1087 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 1088 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 1089 1090 1091 1092 1093 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 1094 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 1095 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 1096 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 1097 1098 1099 1100 1101 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 1102 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 1103 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 1104 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 1105 1106 1107 1108 1109 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 1110 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 1111 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 1112 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 1113 1114 1115 1116 1117 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 1118 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 1119 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 1120 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 1121 1122 1123 1124 1125 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 1126 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 1127 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 1128 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 1129 1130 1131 1132 1133 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1134 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 1135 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 1136 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 1137 1138 1139 1140 1141 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1142 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 1143 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 1144 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 1145 1146 1147 1148 1149 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1150 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 1151 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 1152 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 1153 1154 1155 1156 1157 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1158 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 1159 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 1160 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 1161 1162 1163 1164 1165 #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 1166 #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 1167 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 1168 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 1169 1170 1171 1172 1173 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 1174 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 1175 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 1176 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 1177 1178 1179 1180 #endif 1181