1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _MACTX_HE_SIG_B1_MU_H_ 18 #define _MACTX_HE_SIG_B1_MU_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "he_sig_b1_mu_info.h" 23 #define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 24 25 #define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 26 27 28 struct mactx_he_sig_b1_mu { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 31 uint32_t tlv64_padding : 32; // [31:0] 32 #else 33 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 34 uint32_t tlv64_padding : 32; // [31:0] 35 #endif 36 }; 37 38 39 /* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS 40 41 See detailed description of the STRUCT 42 */ 43 44 45 /* Description RU_ALLOCATION 46 47 RU allocation for the user(s) following this common portion 48 of the SIG 49 50 For details, refer to RU_TYPE description 51 <legal all> 52 */ 53 54 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 55 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 56 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 57 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff 58 59 60 /* Description RESERVED_0 61 62 <legal 0> 63 */ 64 65 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 66 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 67 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 68 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 69 70 71 /* Description RX_INTEGRITY_CHECK_PASSED 72 73 TX side: Set to 0 74 RX side: Set to 1 if PHY determines the CRC check of the 75 codeblock containing the HE-SIG-B common info has passed, 76 else set to 0 77 78 <legal all> 79 */ 80 81 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 82 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 83 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 84 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 85 86 87 /* Description TLV64_PADDING 88 89 Automatic DWORD padding inserted while converting TLV32 90 to TLV64 for 64 bit ARCH 91 <legal 0> 92 */ 93 94 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 95 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 96 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 97 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 98 99 100 101 #endif // MACTX_HE_SIG_B1_MU 102