1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _HE_SIG_A_MU_UL_INFO_H_ 18 #define _HE_SIG_A_MU_UL_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 23 24 25 struct he_sig_a_mu_ul_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t format_indication : 1, // [0:0] 28 bss_color_id : 6, // [6:1] 29 spatial_reuse : 16, // [22:7] 30 reserved_0a : 1, // [23:23] 31 transmit_bw : 2, // [25:24] 32 reserved_0b : 6; // [31:26] 33 uint32_t txop_duration : 7, // [6:0] 34 reserved_1a : 9, // [15:7] 35 crc : 4, // [19:16] 36 tail : 6, // [25:20] 37 reserved_1b : 5, // [30:26] 38 rx_integrity_check_passed : 1; // [31:31] 39 #else 40 uint32_t reserved_0b : 6, // [31:26] 41 transmit_bw : 2, // [25:24] 42 reserved_0a : 1, // [23:23] 43 spatial_reuse : 16, // [22:7] 44 bss_color_id : 6, // [6:1] 45 format_indication : 1; // [0:0] 46 uint32_t rx_integrity_check_passed : 1, // [31:31] 47 reserved_1b : 5, // [30:26] 48 tail : 6, // [25:20] 49 crc : 4, // [19:16] 50 reserved_1a : 9, // [15:7] 51 txop_duration : 7; // [6:0] 52 #endif 53 }; 54 55 56 /* Description FORMAT_INDICATION 57 58 Indicates whether the transmission is SU PPDU or a trigger 59 based UL MU PDDU 60 <enum 0 HE_SIGA_FORMAT_HE_TRIG> 61 <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU> 62 <legal all> 63 */ 64 65 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 66 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 67 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 68 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 69 70 71 /* Description BSS_COLOR_ID 72 73 BSS color ID 74 <legal all> 75 */ 76 77 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 78 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 79 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 80 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e 81 82 83 /* Description SPATIAL_REUSE 84 85 Spatial reuse 86 87 <legal all> 88 */ 89 90 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 91 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 92 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 93 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 94 95 96 /* Description RESERVED_0A 97 98 Note: spec indicates this shall be set to 1 99 <legal 1> 100 */ 101 102 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 103 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 104 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 105 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 106 107 108 /* Description TRANSMIT_BW 109 110 Bandwidth of the PPDU. 111 112 <enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz 113 <enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz 114 <enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz 115 <enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz 116 117 On RX side, Field Used by MAC HW 118 <legal 0-3> 119 */ 120 121 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 122 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 123 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 124 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 125 126 127 /* Description RESERVED_0B 128 129 <legal 0> 130 */ 131 132 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 133 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 134 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 135 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 136 137 138 /* Description TXOP_DURATION 139 140 Indicates the remaining time in the current TXOP <legal 141 all> 142 */ 143 144 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 145 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 146 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 147 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f 148 149 150 /* Description RESERVED_1A 151 152 Set to value indicated in the trigger frame 153 <legal 255> 154 */ 155 156 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 157 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 158 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 159 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 160 161 162 /* Description CRC 163 164 CRC for HE-SIG-A contents. 165 This CRC may also cover some fields of L-SIG (TBD) 166 <legal all> 167 */ 168 169 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 170 #define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 171 #define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 172 #define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 173 174 175 /* Description TAIL 176 177 BCC encoding (similar to VHT-SIG-A) with 6 tail bits is 178 used 179 <legal 0> 180 */ 181 182 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 183 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 184 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 185 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 186 187 188 /* Description RESERVED_1B 189 190 <legal 0> 191 */ 192 193 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 194 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 195 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 196 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 197 198 199 /* Description RX_INTEGRITY_CHECK_PASSED 200 201 TX side: Set to 0 202 RX side: Set to 1 if PHY determines the HE-SIG-A CRC check 203 has passed, else set to 0 204 205 <legal all> 206 */ 207 208 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 209 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 210 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 211 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 212 213 214 215 #endif // HE_SIG_A_MU_UL_INFO 216