1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RESPONSE_START_STATUS_H_ 20 #define _RESPONSE_START_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 25 26 #define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 27 28 29 struct response_start_status { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t generated_response : 3, 32 ftm_tm : 2, 33 trig_response_related : 1, 34 response_sta_count : 7, 35 reserved : 19; 36 uint32_t phy_ppdu_id : 16, 37 sw_peer_id : 16; 38 #else 39 uint32_t reserved : 19, 40 response_sta_count : 7, 41 trig_response_related : 1, 42 ftm_tm : 2, 43 generated_response : 3; 44 uint32_t sw_peer_id : 16, 45 phy_ppdu_id : 16; 46 #endif 47 }; 48 49 50 51 52 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 53 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 54 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 55 #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 56 57 58 59 60 #define RESPONSE_START_STATUS_FTM_TM_OFFSET 0x0000000000000000 61 #define RESPONSE_START_STATUS_FTM_TM_LSB 3 62 #define RESPONSE_START_STATUS_FTM_TM_MSB 4 63 #define RESPONSE_START_STATUS_FTM_TM_MASK 0x0000000000000018 64 65 66 67 68 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 69 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 70 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 71 #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 72 73 74 75 76 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 77 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 78 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 79 #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 80 81 82 83 84 #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 85 #define RESPONSE_START_STATUS_RESERVED_LSB 13 86 #define RESPONSE_START_STATUS_RESERVED_MSB 31 87 #define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 88 89 90 91 92 #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 93 #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 94 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 95 #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 96 97 98 99 100 #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 101 #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 102 #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 103 #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 104 105 106 107 #endif 108