1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_FES_SETUP_H_ 21 #define _TX_FES_SETUP_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_TX_FES_SETUP 10 26 27 #define NUM_OF_QWORDS_TX_FES_SETUP 5 28 29 struct tx_fes_setup { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t schedule_id : 32; 32 uint32_t fes_in_11ax_trigger_response_config : 1, 33 bo_based_tid_aggregation_limit : 4, 34 __reserved_g_0005 : 1, 35 expect_i2r_lmr : 1, 36 transmit_start_reason : 3, 37 use_alt_power_sr : 1, 38 static_2_pwr_mode_status : 1, 39 obss_srg_opport_transmit_status : 1, 40 srp_based_transmit_status : 1, 41 obss_pd_based_transmit_status : 1, 42 puncture_from_all_allowed_modes : 1, 43 schedule_cmd_ring_id : 5, 44 fes_control_mode : 2, 45 number_of_users : 6, 46 mu_type : 1, 47 ofdma_triggered_response : 1, 48 response_to_response_cmd : 1; 49 uint32_t schedule_try : 4, 50 ndp_frame : 2, 51 txbf : 1, 52 allow_txop_exceed_in_1st_pkt : 1, 53 ignore_bw_available : 1, 54 ignore_tbtt : 1, 55 static_bandwidth : 3, 56 set_txop_duration_all_ones : 1, 57 transmission_contains_mu_rts : 1, 58 bw_restricted_frames_embedded : 1, 59 ast_index : 16; 60 uint32_t cv_id : 8, 61 trigger_resp_txpdu_ppdu_boundary : 2, 62 rxpcu_setup_complete_present : 1, 63 rbo_must_have_data_user_limit : 4, 64 mu_ndp : 1, 65 bf_type : 2, 66 cbf_nc_index_mask : 1, 67 cbf_nc_index : 3, 68 cbf_nr_index_mask : 1, 69 cbf_nr_index : 3, 70 secure___reserved_g_0005_ista : 1, 71 ndpa : 1, 72 wait_sifs : 2, 73 cbf_feedback_type_mask : 1, 74 cbf_feedback_type : 1; 75 uint32_t cbf_sounding_token : 6, 76 cbf_sounding_token_mask : 1, 77 cbf_bw_mask : 1, 78 cbf_bw : 3, 79 use_static_bw : 1, 80 coex_nack_count : 5, 81 sch_tx_burst_ongoing : 1, 82 gen_tqm_update_mpdu_count_tlv : 1, 83 transmit_vif : 4, 84 optimal_bw_retry_count : 4, 85 fes_continuation_ratio_threshold : 5; 86 uint32_t transmit_cca_bitmap : 32; 87 uint32_t tb___reserved_g_0005 : 1, 88 __reserved_g_0005_trigger_subtype : 4, 89 min_cts2self_count : 4, 90 max_cts2self_count : 4, 91 wifi_radar_enable : 1, 92 reserved_6a : 18; 93 uint32_t monitor_override_sta_31_0 : 32; 94 uint32_t monitor_override_sta_36_32 : 5, 95 reserved_8a : 27; 96 uint32_t fw2sw_info : 32; 97 #else 98 uint32_t schedule_id : 32; 99 uint32_t response_to_response_cmd : 1, 100 ofdma_triggered_response : 1, 101 mu_type : 1, 102 number_of_users : 6, 103 fes_control_mode : 2, 104 schedule_cmd_ring_id : 5, 105 puncture_from_all_allowed_modes : 1, 106 obss_pd_based_transmit_status : 1, 107 srp_based_transmit_status : 1, 108 obss_srg_opport_transmit_status : 1, 109 static_2_pwr_mode_status : 1, 110 use_alt_power_sr : 1, 111 transmit_start_reason : 3, 112 expect_i2r_lmr : 1, 113 __reserved_g_0005 : 1, 114 bo_based_tid_aggregation_limit : 4, 115 fes_in_11ax_trigger_response_config : 1; 116 uint32_t ast_index : 16, 117 bw_restricted_frames_embedded : 1, 118 transmission_contains_mu_rts : 1, 119 set_txop_duration_all_ones : 1, 120 static_bandwidth : 3, 121 ignore_tbtt : 1, 122 ignore_bw_available : 1, 123 allow_txop_exceed_in_1st_pkt : 1, 124 txbf : 1, 125 ndp_frame : 2, 126 schedule_try : 4; 127 uint32_t cbf_feedback_type : 1, 128 cbf_feedback_type_mask : 1, 129 wait_sifs : 2, 130 ndpa : 1, 131 secure___reserved_g_0005_ista : 1, 132 cbf_nr_index : 3, 133 cbf_nr_index_mask : 1, 134 cbf_nc_index : 3, 135 cbf_nc_index_mask : 1, 136 bf_type : 2, 137 mu_ndp : 1, 138 rbo_must_have_data_user_limit : 4, 139 rxpcu_setup_complete_present : 1, 140 trigger_resp_txpdu_ppdu_boundary : 2, 141 cv_id : 8; 142 uint32_t fes_continuation_ratio_threshold : 5, 143 optimal_bw_retry_count : 4, 144 transmit_vif : 4, 145 gen_tqm_update_mpdu_count_tlv : 1, 146 sch_tx_burst_ongoing : 1, 147 coex_nack_count : 5, 148 use_static_bw : 1, 149 cbf_bw : 3, 150 cbf_bw_mask : 1, 151 cbf_sounding_token_mask : 1, 152 cbf_sounding_token : 6; 153 uint32_t transmit_cca_bitmap : 32; 154 uint32_t reserved_6a : 18, 155 wifi_radar_enable : 1, 156 max_cts2self_count : 4, 157 min_cts2self_count : 4, 158 __reserved_g_0005_trigger_subtype : 4, 159 tb___reserved_g_0005 : 1; 160 uint32_t monitor_override_sta_31_0 : 32; 161 uint32_t reserved_8a : 27, 162 monitor_override_sta_36_32 : 5; 163 uint32_t fw2sw_info : 32; 164 #endif 165 }; 166 167 #define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 168 #define TX_FES_SETUP_SCHEDULE_ID_LSB 0 169 #define TX_FES_SETUP_SCHEDULE_ID_MSB 31 170 #define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff 171 172 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 173 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 174 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 175 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 176 177 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 178 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 179 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 180 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 181 182 #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 183 #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 184 #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 185 #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 186 187 #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 188 #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 189 #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 190 #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 191 192 #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 193 #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 194 #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 195 #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 196 197 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 198 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 199 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 200 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 201 202 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 203 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 204 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 205 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 206 207 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 208 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 209 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 210 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 211 212 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 213 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 214 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 215 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 216 217 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 218 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 219 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 220 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 221 222 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 223 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 224 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 225 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 226 227 #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 228 #define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 229 #define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 230 #define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 231 232 #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 233 #define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 234 #define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 235 #define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 236 237 #define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 238 #define TX_FES_SETUP_MU_TYPE_LSB 61 239 #define TX_FES_SETUP_MU_TYPE_MSB 61 240 #define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 241 242 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 243 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 244 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 245 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 246 247 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 248 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 249 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 250 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 251 252 #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 253 #define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 254 #define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 255 #define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f 256 257 #define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 258 #define TX_FES_SETUP_NDP_FRAME_LSB 4 259 #define TX_FES_SETUP_NDP_FRAME_MSB 5 260 #define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 261 262 #define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 263 #define TX_FES_SETUP_TXBF_LSB 6 264 #define TX_FES_SETUP_TXBF_MSB 6 265 #define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 266 267 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 268 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 269 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 270 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 271 272 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 273 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 274 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 275 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 276 277 #define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 278 #define TX_FES_SETUP_IGNORE_TBTT_LSB 9 279 #define TX_FES_SETUP_IGNORE_TBTT_MSB 9 280 #define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 281 282 #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 283 #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 284 #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 285 #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 286 287 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 288 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 289 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 290 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 291 292 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 293 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 294 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 295 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 296 297 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 298 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 299 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 300 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 301 302 #define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 303 #define TX_FES_SETUP_AST_INDEX_LSB 16 304 #define TX_FES_SETUP_AST_INDEX_MSB 31 305 #define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 306 307 #define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 308 #define TX_FES_SETUP_CV_ID_LSB 32 309 #define TX_FES_SETUP_CV_ID_MSB 39 310 #define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 311 312 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 313 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 314 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 315 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 316 317 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 318 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 319 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 320 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 321 322 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 323 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 324 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 325 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 326 327 #define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 328 #define TX_FES_SETUP_MU_NDP_LSB 47 329 #define TX_FES_SETUP_MU_NDP_MSB 47 330 #define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 331 332 #define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 333 #define TX_FES_SETUP_BF_TYPE_LSB 48 334 #define TX_FES_SETUP_BF_TYPE_MSB 49 335 #define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 336 337 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 338 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 339 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 340 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 341 342 #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 343 #define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 344 #define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 345 #define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 346 347 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 348 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 349 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 350 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 351 352 #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 353 #define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 354 #define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 355 #define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 356 357 #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 358 #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 359 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 360 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 361 362 #define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 363 #define TX_FES_SETUP_NDPA_LSB 59 364 #define TX_FES_SETUP_NDPA_MSB 59 365 #define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 366 367 #define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 368 #define TX_FES_SETUP_WAIT_SIFS_LSB 60 369 #define TX_FES_SETUP_WAIT_SIFS_MSB 61 370 #define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 371 372 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 373 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 374 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 375 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 376 377 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 378 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 379 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 380 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 381 382 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 383 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 384 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 385 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f 386 387 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 388 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 389 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 390 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 391 392 #define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 393 #define TX_FES_SETUP_CBF_BW_MASK_LSB 7 394 #define TX_FES_SETUP_CBF_BW_MASK_MSB 7 395 #define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 396 397 #define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 398 #define TX_FES_SETUP_CBF_BW_LSB 8 399 #define TX_FES_SETUP_CBF_BW_MSB 10 400 #define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 401 402 #define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 403 #define TX_FES_SETUP_USE_STATIC_BW_LSB 11 404 #define TX_FES_SETUP_USE_STATIC_BW_MSB 11 405 #define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 406 407 #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 408 #define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 409 #define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 410 #define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 411 412 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 413 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 414 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 415 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 416 417 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 418 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 419 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 420 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 421 422 #define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 423 #define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 424 #define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 425 #define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 426 427 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 428 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 429 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 430 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 431 432 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 433 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 434 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 435 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 436 437 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 438 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 439 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 440 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 441 442 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 443 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 444 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 445 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e 446 447 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 448 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 449 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 450 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 451 452 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 453 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 454 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 455 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 456 457 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 458 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 459 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 460 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 461 462 #define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 463 #define TX_FES_SETUP_RESERVED_6A_LSB 14 464 #define TX_FES_SETUP_RESERVED_6A_MSB 31 465 #define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 466 467 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 468 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 469 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 470 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 471 472 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 473 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 474 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 475 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f 476 477 #define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 478 #define TX_FES_SETUP_RESERVED_8A_LSB 5 479 #define TX_FES_SETUP_RESERVED_8A_MSB 31 480 #define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 481 482 #define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 483 #define TX_FES_SETUP_FW2SW_INFO_LSB 32 484 #define TX_FES_SETUP_FW2SW_INFO_MSB 63 485 #define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 486 487 #endif 488