1dea4501bSVishwajith Upendra /* 247329d82Sspuligil * Copyright (c) 2013-2016, 2018-2021 The Linux Foundation. All rights reserved. 3*a07d3dfcSspuligil * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4dea4501bSVishwajith Upendra * 5dea4501bSVishwajith Upendra * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 6dea4501bSVishwajith Upendra * 7dea4501bSVishwajith Upendra * 8dea4501bSVishwajith Upendra * Permission to use, copy, modify, and/or distribute this software for 9dea4501bSVishwajith Upendra * any purpose with or without fee is hereby granted, provided that the 10dea4501bSVishwajith Upendra * above copyright notice and this permission notice appear in all 11dea4501bSVishwajith Upendra * copies. 12dea4501bSVishwajith Upendra * 13dea4501bSVishwajith Upendra * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 14dea4501bSVishwajith Upendra * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 15dea4501bSVishwajith Upendra * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 16dea4501bSVishwajith Upendra * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 17dea4501bSVishwajith Upendra * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 18dea4501bSVishwajith Upendra * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19dea4501bSVishwajith Upendra * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20dea4501bSVishwajith Upendra * PERFORMANCE OF THIS SOFTWARE. 21dea4501bSVishwajith Upendra */ 22dea4501bSVishwajith Upendra 23dea4501bSVishwajith Upendra /* 24dea4501bSVishwajith Upendra * This file was originally distributed by Qualcomm Atheros, Inc. 25dea4501bSVishwajith Upendra * under proprietary terms before Copyright ownership was assigned 26dea4501bSVishwajith Upendra * to the Linux Foundation. 27dea4501bSVishwajith Upendra */ 28dea4501bSVishwajith Upendra #ifndef __WLAN_DEFS_H__ 29dea4501bSVishwajith Upendra #define __WLAN_DEFS_H__ 30dea4501bSVishwajith Upendra 3190c68bd3Sqcabuildsw #include <a_osapi.h> /* A_COMPILE_TIME_ASSERT */ 32dea4501bSVishwajith Upendra 33dea4501bSVishwajith Upendra /* 34dea4501bSVishwajith Upendra * This file contains WLAN definitions that may be used across both 35dea4501bSVishwajith Upendra * Host and Target software. 36dea4501bSVishwajith Upendra */ 3790c68bd3Sqcabuildsw 3890c68bd3Sqcabuildsw 39dea4501bSVishwajith Upendra /* 40dea4501bSVishwajith Upendra * MAX_SPATIAL_STREAM should be defined in a fwconfig_xxx.h file, 41dea4501bSVishwajith Upendra * but for now provide a default value here in case it's not defined 42dea4501bSVishwajith Upendra * in the fwconfig_xxx.h file. 43dea4501bSVishwajith Upendra */ 44dea4501bSVishwajith Upendra #ifndef MAX_SPATIAL_STREAM 45dea4501bSVishwajith Upendra #define MAX_SPATIAL_STREAM 3 46dea4501bSVishwajith Upendra #endif 47dea4501bSVishwajith Upendra 481ed83134Sspuligil /* 491ed83134Sspuligil * NOTE: The CONFIG_160MHZ_SUPPORT is not used consistently - some code 501ed83134Sspuligil * uses "#ifdef CONFIG_160MHZ_SUPPORT" while other code uses 511ed83134Sspuligil * "#if CONFIG_160MHZ_SUPPORT". 521ed83134Sspuligil * This use is being standardized in the recent versions of code to use 531ed83134Sspuligil * #ifdef, but is being left as is in the legacy code branches. 541ed83134Sspuligil * To minimize impact to legacy code branches, this file internally 551ed83134Sspuligil * converts CONFIG_160MHZ_SUPPORT=0 to having CONFIG_160MHZ_SUPPORT 561ed83134Sspuligil * undefined. 571ed83134Sspuligil * For builds that explicitly set CONFIG_160MHZ_SUPPORT=0, the bottom of 581ed83134Sspuligil * this file restores CONFIG_160MHZ_SUPPORT from being undefined to being 0. 591ed83134Sspuligil */ 601ed83134Sspuligil // OLD: 611ed83134Sspuligil //#ifndef CONFIG_160MHZ_SUPPORT 621ed83134Sspuligil //#define CONFIG_160MHZ_SUPPORT 0 /* default: 160 MHz channels not supported */ 631ed83134Sspuligil //#endif 641ed83134Sspuligil // NEW: 651ed83134Sspuligil #ifdef CONFIG_160MHZ_SUPPORT 661ed83134Sspuligil /* CONFIG_160MHZ_SUPPORT is explicitly enabled or explicitly disabled */ 671ed83134Sspuligil #if !CONFIG_160MHZ_SUPPORT 681ed83134Sspuligil /* CONFIG_160MHZ_SUPPORT is explicitly disabled */ 691ed83134Sspuligil /* Change from CONFIG_160MHZ_SUPPORT=0 to CONFIG_160MHZ_SUPPORT=<undef> */ 701ed83134Sspuligil #undef CONFIG_160MHZ_SUPPORT 711ed83134Sspuligil /* 721ed83134Sspuligil * Set a flag to indicate this CONFIG_160MHZ_SUPPORT = 0 --> undef 731ed83134Sspuligil * change has been done, so we can undo the change at the bottom 741ed83134Sspuligil * of the file. 751ed83134Sspuligil */ 761ed83134Sspuligil #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR 771ed83134Sspuligil #endif 781ed83134Sspuligil #else 791ed83134Sspuligil /* 801ed83134Sspuligil * For backwards compatibility, if CONFIG_160MHZ_SUPPORT is not defined, 811ed83134Sspuligil * default it to 0, if this is either a host build or a Rome target build. 821ed83134Sspuligil * This maintains the prior behavior for the host and Rome target builds. 831ed83134Sspuligil */ 841ed83134Sspuligil #if defined(AR6320) || !defined(ATH_TARGET) 851ed83134Sspuligil /* 861ed83134Sspuligil * Set a flag to indicate that at the end of the file, 871ed83134Sspuligil * CONFIG_160MHZ_SUPPORT should be set to 0. 881ed83134Sspuligil */ 891ed83134Sspuligil #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR 901ed83134Sspuligil #endif 915e6ced2eSLeo Chang #endif 925e6ced2eSLeo Chang 935e6ced2eSLeo Chang #ifndef SUPPORT_11AX 945e6ced2eSLeo Chang #define SUPPORT_11AX 0 /* 11ax not supported by default */ 955e6ced2eSLeo Chang #endif 965e6ced2eSLeo Chang 9790c68bd3Sqcabuildsw /* 9890c68bd3Sqcabuildsw * MAX_SPATIAL_STREAM_ANY - 9990c68bd3Sqcabuildsw * what is the largest number of spatial streams that any target supports 10090c68bd3Sqcabuildsw */ 10190c68bd3Sqcabuildsw #define MAX_SPATIAL_STREAM_ANY_V2 4 /* pre-hawkeye */ 10290c68bd3Sqcabuildsw #define MAX_SPATIAL_STREAM_ANY_V3 8 /* includes hawkeye */ 10390c68bd3Sqcabuildsw /* 10490c68bd3Sqcabuildsw * (temporarily) leave the old MAX_SPATIAL_STREAM_ANY name in place as an alias, 10590c68bd3Sqcabuildsw * and in case some old code is using it 10690c68bd3Sqcabuildsw */ 10790c68bd3Sqcabuildsw #define MAX_SPATIAL_STREAM_ANY MAX_SPATIAL_STREAM_ANY_V2 /* DEPRECATED */ 10890c68bd3Sqcabuildsw 1099af1257eSspuligil /* defines to set Packet extension values which can be 0, 8, or 16 usec */ 1105e6ced2eSLeo Chang /* NOTE: Below values cannot be changed without breaking WMI Compatibility */ 1115e6ced2eSLeo Chang #define MAX_HE_NSS 8 1125e6ced2eSLeo Chang #define MAX_HE_MODULATION 8 1135e6ced2eSLeo Chang #define MAX_HE_RU 4 1145e6ced2eSLeo Chang #define HE_MODULATION_NONE 7 1155e6ced2eSLeo Chang #define HE_PET_0_USEC 0 1165e6ced2eSLeo Chang #define HE_PET_8_USEC 1 1175e6ced2eSLeo Chang #define HE_PET_16_USEC 2 118dea4501bSVishwajith Upendra 11957f8014cSspuligil #define DEFAULT_OFDMA_RU26_COUNT 0 12057f8014cSspuligil 121dea4501bSVishwajith Upendra typedef enum { 122dea4501bSVishwajith Upendra MODE_11A = 0, /* 11a Mode */ 123dea4501bSVishwajith Upendra MODE_11G = 1, /* 11b/g Mode */ 124dea4501bSVishwajith Upendra MODE_11B = 2, /* 11b Mode */ 125dea4501bSVishwajith Upendra MODE_11GONLY = 3, /* 11g only Mode */ 126dea4501bSVishwajith Upendra MODE_11NA_HT20 = 4, /* 11a HT20 mode */ 127dea4501bSVishwajith Upendra MODE_11NG_HT20 = 5, /* 11g HT20 mode */ 128dea4501bSVishwajith Upendra MODE_11NA_HT40 = 6, /* 11a HT40 mode */ 129dea4501bSVishwajith Upendra MODE_11NG_HT40 = 7, /* 11g HT40 mode */ 130dea4501bSVishwajith Upendra MODE_11AC_VHT20 = 8, 131dea4501bSVishwajith Upendra MODE_11AC_VHT40 = 9, 132dea4501bSVishwajith Upendra MODE_11AC_VHT80 = 10, 133dea4501bSVishwajith Upendra MODE_11AC_VHT20_2G = 11, 134dea4501bSVishwajith Upendra MODE_11AC_VHT40_2G = 12, 135dea4501bSVishwajith Upendra MODE_11AC_VHT80_2G = 13, 1361ed83134Sspuligil #ifdef CONFIG_160MHZ_SUPPORT 137dea4501bSVishwajith Upendra MODE_11AC_VHT80_80 = 14, 138dea4501bSVishwajith Upendra MODE_11AC_VHT160 = 15, 139dea4501bSVishwajith Upendra #endif 140dea4501bSVishwajith Upendra 141dea4501bSVishwajith Upendra #if SUPPORT_11AX 142dea4501bSVishwajith Upendra MODE_11AX_HE20 = 16, 143dea4501bSVishwajith Upendra MODE_11AX_HE40 = 17, 144dea4501bSVishwajith Upendra MODE_11AX_HE80 = 18, 145dea4501bSVishwajith Upendra MODE_11AX_HE80_80 = 19, 146dea4501bSVishwajith Upendra MODE_11AX_HE160 = 20, 147dea4501bSVishwajith Upendra MODE_11AX_HE20_2G = 21, 148dea4501bSVishwajith Upendra MODE_11AX_HE40_2G = 22, 149dea4501bSVishwajith Upendra MODE_11AX_HE80_2G = 23, 150dea4501bSVishwajith Upendra #endif 151dea4501bSVishwajith Upendra 1521bd7eb19Sspuligil #if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) 153f18a3d79Sspuligil MODE_11BE_EHT20 = 24, 154f18a3d79Sspuligil MODE_11BE_EHT40 = 25, 155f18a3d79Sspuligil MODE_11BE_EHT80 = 26, 156f18a3d79Sspuligil MODE_11BE_EHT80_80 = 27, 157f18a3d79Sspuligil MODE_11BE_EHT160 = 28, 158f18a3d79Sspuligil MODE_11BE_EHT160_160 = 29, 159f18a3d79Sspuligil MODE_11BE_EHT320 = 30, 160f18a3d79Sspuligil MODE_11BE_EHT20_2G = 31, /* For WIN */ 161f18a3d79Sspuligil MODE_11BE_EHT40_2G = 32, /* For WIN */ 162f18a3d79Sspuligil #endif 163f18a3d79Sspuligil 164dea4501bSVishwajith Upendra /* 165dea4501bSVishwajith Upendra * MODE_UNKNOWN should not be used within the host / target interface. 166f18a3d79Sspuligil * Thus, it is permissible for MODE_UNKNOWN to be conditionally-defined, 167dea4501bSVishwajith Upendra * taking different values when compiling for different targets. 168dea4501bSVishwajith Upendra */ 169dea4501bSVishwajith Upendra MODE_UNKNOWN, 170dea4501bSVishwajith Upendra MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */ 171dea4501bSVishwajith Upendra MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */ 172dea4501bSVishwajith Upendra 173dea4501bSVishwajith Upendra #ifdef ATHR_WIN_NWF 174dea4501bSVishwajith Upendra PHY_MODE_MAX = MODE_UNKNOWN, 175dea4501bSVishwajith Upendra PHY_MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, 176dea4501bSVishwajith Upendra PHY_MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, 177dea4501bSVishwajith Upendra #else 178dea4501bSVishwajith Upendra MODE_MAX = MODE_UNKNOWN, 179dea4501bSVishwajith Upendra MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, 180dea4501bSVishwajith Upendra MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, 181dea4501bSVishwajith Upendra #endif 182dea4501bSVishwajith Upendra } WLAN_PHY_MODE; 183dea4501bSVishwajith Upendra 1847caf4c00Sspuligil #if (!defined(CONFIG_160MHZ_SUPPORT)) && (!defined(SUPPORT_11AX)) 185dea4501bSVishwajith Upendra A_COMPILE_TIME_ASSERT( 186dea4501bSVishwajith Upendra mode_unknown_value_consistency_Check, 187dea4501bSVishwajith Upendra MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT); 188dea4501bSVishwajith Upendra #else 1897caf4c00Sspuligil /* 1907caf4c00Sspuligil * If SUPPORT_11AX is defined but CONFIG_160MHZ_SUPPORT is not defined, 1917caf4c00Sspuligil * there will be a gap in the mode values, with 14 and 15 being unused. 1927caf4c00Sspuligil * But MODE_UNKNOWN_NO_160MHZ_SUPPORT will have an invalid value, since 1937caf4c00Sspuligil * mode values 16 through 23 will be used for 11AX modes. 1947caf4c00Sspuligil * Thus, MODE_UNKNOWN would still be MODE_UNKNOWN_160MHZ_SUPPORT, for 1957caf4c00Sspuligil * cases where 160 MHz is not supported by 11AX is supported. 1967caf4c00Sspuligil * (Ideally, MODE_UNKNOWN_160MHZ_SUPPORT and NO_160MHZ_SUPPORT should be 1977caf4c00Sspuligil * renamed to cover the 4 permutations of support or no support for 1987caf4c00Sspuligil * 11AX and 160 MHZ, but that is impractical, due to backwards 1997caf4c00Sspuligil * compatibility concerns.) 2007caf4c00Sspuligil */ 201dea4501bSVishwajith Upendra A_COMPILE_TIME_ASSERT( 202dea4501bSVishwajith Upendra mode_unknown_value_consistency_Check, 203dea4501bSVishwajith Upendra MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT); 204dea4501bSVishwajith Upendra #endif 205dea4501bSVishwajith Upendra 206dea4501bSVishwajith Upendra typedef enum { 207dea4501bSVishwajith Upendra VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */ 208dea4501bSVishwajith Upendra VHT_MODE_20M = 1, 209dea4501bSVishwajith Upendra VHT_MODE_40M = 2, 210dea4501bSVishwajith Upendra VHT_MODE_80M = 3, 211dea4501bSVishwajith Upendra VHT_MODE_160M = 4 212dea4501bSVishwajith Upendra } VHT_OPER_MODE; 213dea4501bSVishwajith Upendra 214dea4501bSVishwajith Upendra typedef enum { 215dea4501bSVishwajith Upendra WLAN_11A_CAPABILITY = 1, 216dea4501bSVishwajith Upendra WLAN_11G_CAPABILITY = 2, 217dea4501bSVishwajith Upendra WLAN_11AG_CAPABILITY = 3, 218dea4501bSVishwajith Upendra } WLAN_CAPABILITY; 219dea4501bSVishwajith Upendra 2201ed83134Sspuligil #ifdef CONFIG_160MHZ_SUPPORT 221dea4501bSVishwajith Upendra #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ 222dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT40) || \ 223dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT80) || \ 224dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT80_80) || \ 225dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT160)) 226dea4501bSVishwajith Upendra #else 227dea4501bSVishwajith Upendra #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ 228dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT40) || \ 229dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT80)) 230dea4501bSVishwajith Upendra #endif 231dea4501bSVishwajith Upendra 2321abc4a5dSspuligil #if SUPPORT_11AX 233dea4501bSVishwajith Upendra #define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \ 234dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE40) || \ 235dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE80) || \ 236dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE80_80) || \ 237dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE160) || \ 238dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE20_2G) || \ 239dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE40_2G) || \ 240dea4501bSVishwajith Upendra ((mode) == MODE_11AX_HE80_2G)) 241c8ad4eafSspuligil #define IS_MODE_HE_5G_6G(mode) (((mode) == MODE_11AX_HE20) || \ 242c8ad4eafSspuligil ((mode) == MODE_11AX_HE40) || \ 243c8ad4eafSspuligil ((mode) == MODE_11AX_HE80) || \ 244c8ad4eafSspuligil ((mode) == MODE_11AX_HE80_80) || \ 245c8ad4eafSspuligil ((mode) == MODE_11AX_HE160)) 2461abc4a5dSspuligil #define IS_MODE_HE_2G(mode) (((mode) == MODE_11AX_HE20_2G) || \ 2471abc4a5dSspuligil ((mode) == MODE_11AX_HE40_2G) || \ 2481abc4a5dSspuligil ((mode) == MODE_11AX_HE80_2G)) 2491abc4a5dSspuligil #endif /* SUPPORT_11AX */ 250dea4501bSVishwajith Upendra 2511bd7eb19Sspuligil #if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) 252f18a3d79Sspuligil #define IS_MODE_EHT(mode) (((mode) == MODE_11BE_EHT20) || \ 253f18a3d79Sspuligil ((mode) == MODE_11BE_EHT40) || \ 254f18a3d79Sspuligil ((mode) == MODE_11BE_EHT80) || \ 255f18a3d79Sspuligil ((mode) == MODE_11BE_EHT80_80) || \ 256f18a3d79Sspuligil ((mode) == MODE_11BE_EHT160) || \ 257f18a3d79Sspuligil ((mode) == MODE_11BE_EHT160_160)|| \ 258f18a3d79Sspuligil ((mode) == MODE_11BE_EHT320) || \ 259f18a3d79Sspuligil ((mode) == MODE_11BE_EHT20_2G) || \ 260f18a3d79Sspuligil ((mode) == MODE_11BE_EHT40_2G)) 261f18a3d79Sspuligil #define IS_MODE_EHT_2G(mode) (((mode) == MODE_11BE_EHT20_2G) || \ 262f18a3d79Sspuligil ((mode) == MODE_11BE_EHT40_2G)) 263f18a3d79Sspuligil #endif /* SUPPORT_11BE */ 264f18a3d79Sspuligil 265dea4501bSVishwajith Upendra #define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ 266dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT40_2G) || \ 267dea4501bSVishwajith Upendra ((mode) == MODE_11AC_VHT80_2G)) 268dea4501bSVishwajith Upendra 26990c68bd3Sqcabuildsw 270dea4501bSVishwajith Upendra #define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ 271dea4501bSVishwajith Upendra ((mode) == MODE_11NA_HT20) || \ 272dea4501bSVishwajith Upendra ((mode) == MODE_11NA_HT40) || \ 273dea4501bSVishwajith Upendra (IS_MODE_VHT(mode))) 274dea4501bSVishwajith Upendra 275dea4501bSVishwajith Upendra #define IS_MODE_11B(mode) ((mode) == MODE_11B) 276dea4501bSVishwajith Upendra #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ 277dea4501bSVishwajith Upendra ((mode) == MODE_11GONLY) || \ 278dea4501bSVishwajith Upendra ((mode) == MODE_11NG_HT20) || \ 279dea4501bSVishwajith Upendra ((mode) == MODE_11NG_HT40) || \ 280dea4501bSVishwajith Upendra (IS_MODE_VHT_2G(mode))) 281dea4501bSVishwajith Upendra #define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \ 282dea4501bSVishwajith Upendra ((mode) == MODE_11NG_HT40)) 283dea4501bSVishwajith Upendra #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) 284dea4501bSVishwajith Upendra 285cfd15daeSspuligil #define IS_MODE_LEGACY(phymode) ((phymode == MODE_11A) || \ 286cfd15daeSspuligil (phymode == MODE_11G) || \ 287cfd15daeSspuligil (phymode == MODE_11B) || \ 288cfd15daeSspuligil (phymode == MODE_11GONLY)) 289cfd15daeSspuligil 290cfd15daeSspuligil #define IS_MODE_11N(phymode) ((phymode >= MODE_11NA_HT20) && \ 291cfd15daeSspuligil (phymode <= MODE_11NG_HT40)) 292cfd15daeSspuligil #ifdef CONFIG_160MHZ_SUPPORT 293cfd15daeSspuligil #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \ 294cfd15daeSspuligil (phymode <= MODE_11AC_VHT160)) 295c8ad4eafSspuligil #define IS_MODE_11AC_5G(phymode) ((phymode == MODE_11AC_VHT20) || \ 296c8ad4eafSspuligil (phymode == MODE_11AC_VHT40) || \ 297c8ad4eafSspuligil (phymode == MODE_11AC_VHT80) || \ 298c8ad4eafSspuligil (phymode == MODE_11AC_VHT80_80) || \ 299c8ad4eafSspuligil (phymode == MODE_11AC_VHT160)) 300cfd15daeSspuligil #else 301cfd15daeSspuligil #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \ 302cfd15daeSspuligil (phymode <= MODE_11AC_VHT80_2G)) 303c8ad4eafSspuligil #define IS_MODE_11AC_5G(phymode) ((phymode == MODE_11AC_VHT20) || \ 304c8ad4eafSspuligil (phymode == MODE_11AC_VHT40) || \ 305c8ad4eafSspuligil (phymode == MODE_11AC_VHT80)) 306cfd15daeSspuligil #endif /* CONFIG_160MHZ_SUPPORT */ 307cfd15daeSspuligil 308cfd15daeSspuligil #if SUPPORT_11AX 309cfd15daeSspuligil #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \ 310cfd15daeSspuligil (phymode == MODE_11AC_VHT80) || \ 311cfd15daeSspuligil (phymode == MODE_11AX_HE80) || \ 312cfd15daeSspuligil (phymode == MODE_11AX_HE80_2G)) 313cfd15daeSspuligil #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \ 314cfd15daeSspuligil (phymode == MODE_11AC_VHT40) || \ 315cfd15daeSspuligil (phymode == MODE_11NG_HT40) || \ 316cfd15daeSspuligil (phymode == MODE_11NA_HT40) || \ 317cfd15daeSspuligil (phymode == MODE_11AX_HE40) || \ 318cfd15daeSspuligil (phymode == MODE_11AX_HE40_2G)) 319cfd15daeSspuligil #else 320cfd15daeSspuligil #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \ 321cfd15daeSspuligil (phymode == MODE_11AC_VHT80)) 322cfd15daeSspuligil #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \ 323cfd15daeSspuligil (phymode == MODE_11AC_VHT40) || \ 324cfd15daeSspuligil (phymode == MODE_11NG_HT40) || \ 325cfd15daeSspuligil (phymode == MODE_11NA_HT40)) 326cfd15daeSspuligil #endif /* SUPPORT_11AX */ 32790c68bd3Sqcabuildsw 328dea4501bSVishwajith Upendra enum { 329f0434a6eSspuligil REGDMN_MODE_11A_BIT = 0, /* 11a channels */ 330f0434a6eSspuligil REGDMN_MODE_TURBO_BIT = 1, /* 11a turbo-only channels */ 331f0434a6eSspuligil REGDMN_MODE_11B_BIT = 2, /* 11b channels */ 332f0434a6eSspuligil REGDMN_MODE_PUREG_BIT = 3, /* 11g channels (OFDM only) */ 333f0434a6eSspuligil REGDMN_MODE_11G_BIT = 3, /* XXX historical */ 334f0434a6eSspuligil /* bit 4 is reserved */ 335f0434a6eSspuligil REGDMN_MODE_108G_BIT = 5, /* 11g+Turbo channels */ 336f0434a6eSspuligil REGDMN_MODE_108A_BIT = 6, /* 11a+Turbo channels */ 337f0434a6eSspuligil /* bit 7 is reserved */ 338f0434a6eSspuligil REGDMN_MODE_XR_BIT = 8, /* XR channels */ 339f0434a6eSspuligil REGDMN_MODE_11A_HALF_RATE_BIT = 9, /* 11A half rate channels */ 340f0434a6eSspuligil REGDMN_MODE_11A_QUARTER_RATE_BIT = 10, /* 11A quarter rate channels */ 341f0434a6eSspuligil REGDMN_MODE_11NG_HT20_BIT = 11, /* 11N-G HT20 channels */ 342f0434a6eSspuligil REGDMN_MODE_11NA_HT20_BIT = 12, /* 11N-A HT20 channels */ 343f0434a6eSspuligil REGDMN_MODE_11NG_HT40PLUS_BIT = 13, /* 11N-G HT40 + channels */ 344f0434a6eSspuligil REGDMN_MODE_11NG_HT40MINUS_BIT = 14, /* 11N-G HT40 - channels */ 345f0434a6eSspuligil REGDMN_MODE_11NA_HT40PLUS_BIT = 15, /* 11N-A HT40 + channels */ 346f0434a6eSspuligil REGDMN_MODE_11NA_HT40MINUS_BIT = 16, /* 11N-A HT40 - channels */ 347f0434a6eSspuligil REGDMN_MODE_11AC_VHT20_BIT = 17, /* 5Ghz, VHT20 */ 348f0434a6eSspuligil REGDMN_MODE_11AC_VHT40PLUS_BIT = 18, /* 5Ghz, VHT40 + channels */ 349f0434a6eSspuligil REGDMN_MODE_11AC_VHT40MINUS_BIT = 19, /* 5Ghz VHT40 - channels */ 350f0434a6eSspuligil REGDMN_MODE_11AC_VHT80_BIT = 20, /* 5Ghz, VHT80 channels */ 351f0434a6eSspuligil REGDMN_MODE_11AC_VHT20_2G_BIT = 21, /* 2Ghz, VHT20 */ 352f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2G_BIT = 22, /* 2Ghz, VHT40 */ 353f0434a6eSspuligil REGDMN_MODE_11AC_VHT80_2G_BIT = 23, /* 2Ghz, VHT80 */ 354f0434a6eSspuligil REGDMN_MODE_11AC_VHT160_BIT = 24, /* 5Ghz, VHT160 */ 355f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2GPLUS_BIT = 25, /* 2Ghz, VHT40+ */ 356f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2GMINUS_BIT = 26, /* 2Ghz, VHT40- */ 357f0434a6eSspuligil REGDMN_MODE_11AC_VHT80_80_BIT = 27, /* 5GHz, VHT80+80 */ 358f0434a6eSspuligil /* bits 28 to 31 are reserved */ 359f0434a6eSspuligil REGDMN_MODE_11AXG_HE20_BIT = 32, /* 2Ghz, HE20 */ 360f0434a6eSspuligil REGDMN_MODE_11AXA_HE20_BIT = 33, /* 5Ghz, HE20 */ 361f0434a6eSspuligil REGDMN_MODE_11AXG_HE40PLUS_BIT = 34, /* 2Ghz, HE40+ */ 362f0434a6eSspuligil REGDMN_MODE_11AXG_HE40MINUS_BIT = 35, /* 2Ghz, HE40- */ 363f0434a6eSspuligil REGDMN_MODE_11AXA_HE40PLUS_BIT = 36, /* 5Ghz, HE40+ */ 364f0434a6eSspuligil REGDMN_MODE_11AXA_HE40MINUS_BIT = 37, /* 5Ghz, HE40- */ 365f0434a6eSspuligil REGDMN_MODE_11AXA_HE80_BIT = 38, /* 5Ghz, HE80 */ 366f0434a6eSspuligil REGDMN_MODE_11AXA_HE160_BIT = 39, /* 5Ghz, HE160 */ 367f0434a6eSspuligil REGDMN_MODE_11AXA_HE80_80_BIT = 40, /* 5Ghz, HE80+80 */ 368e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEG_EHT20_BIT = 41, /* 2Ghz, EHT20 */ 369e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT20_BIT = 42, /* 5Ghz, EHT20 */ 370e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEG_EHT40PLUS_BIT = 43, /* 2Ghz, EHT40+ */ 371e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEG_EHT40MINUS_BIT = 44, /* 2Ghz, EHT40- */ 372e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT40PLUS_BIT = 45, /* 5Ghz, EHT40+ */ 373e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT40MINUS_BIT = 46, /* 5Ghz, EHT40- */ 374e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT80_BIT = 47, /* 5Ghz, EHT80 */ 375e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT160_BIT = 48, /* 5Ghz, EHT160 */ 376e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_11BEA_EHT320_BIT = 49, /* 5Ghz, EHT320 */ 377f0434a6eSspuligil }; 378f0434a6eSspuligil 379f0434a6eSspuligil enum { 380f0434a6eSspuligil REGDMN_MODE_11A = 1 << REGDMN_MODE_11A_BIT, /* 11a channels */ 381f0434a6eSspuligil REGDMN_MODE_TURBO = 1 << REGDMN_MODE_TURBO_BIT, /* 11a turbo-only channels */ 382f0434a6eSspuligil REGDMN_MODE_11B = 1 << REGDMN_MODE_11B_BIT, /* 11b channels */ 383f0434a6eSspuligil REGDMN_MODE_PUREG = 1 << REGDMN_MODE_PUREG_BIT, /* 11g channels (OFDM only) */ 384f0434a6eSspuligil REGDMN_MODE_11G = 1 << REGDMN_MODE_11G_BIT, /* XXX historical */ 385f0434a6eSspuligil REGDMN_MODE_108G = 1 << REGDMN_MODE_108G_BIT, /* 11g+Turbo channels */ 386f0434a6eSspuligil REGDMN_MODE_108A = 1 << REGDMN_MODE_108A_BIT, /* 11a+Turbo channels */ 387f0434a6eSspuligil REGDMN_MODE_XR = 1 << REGDMN_MODE_XR_BIT, /* XR channels */ 388f0434a6eSspuligil REGDMN_MODE_11A_HALF_RATE = 1 << REGDMN_MODE_11A_HALF_RATE_BIT, /* 11A half rate channels */ 389f0434a6eSspuligil REGDMN_MODE_11A_QUARTER_RATE = 1 << REGDMN_MODE_11A_QUARTER_RATE_BIT, /* 11A quarter rate channels */ 390f0434a6eSspuligil REGDMN_MODE_11NG_HT20 = 1 << REGDMN_MODE_11NG_HT20_BIT, /* 11N-G HT20 channels */ 391f0434a6eSspuligil REGDMN_MODE_11NA_HT20 = 1 << REGDMN_MODE_11NA_HT20_BIT, /* 11N-A HT20 channels */ 392f0434a6eSspuligil REGDMN_MODE_11NG_HT40PLUS = 1 << REGDMN_MODE_11NG_HT40PLUS_BIT, /* 11N-G HT40 + channels */ 393f0434a6eSspuligil REGDMN_MODE_11NG_HT40MINUS = 1 << REGDMN_MODE_11NG_HT40MINUS_BIT, /* 11N-G HT40 - channels */ 394f0434a6eSspuligil REGDMN_MODE_11NA_HT40PLUS = 1 << REGDMN_MODE_11NA_HT40PLUS_BIT, /* 11N-A HT40 + channels */ 395f0434a6eSspuligil REGDMN_MODE_11NA_HT40MINUS = 1 << REGDMN_MODE_11NA_HT40MINUS_BIT, /* 11N-A HT40 - channels */ 396f0434a6eSspuligil REGDMN_MODE_11AC_VHT20 = 1 << REGDMN_MODE_11AC_VHT20_BIT, /* 5Ghz, VHT20 */ 397f0434a6eSspuligil REGDMN_MODE_11AC_VHT40PLUS = 1 << REGDMN_MODE_11AC_VHT40PLUS_BIT, /* 5Ghz, VHT40 + channels */ 398f0434a6eSspuligil REGDMN_MODE_11AC_VHT40MINUS = 1 << REGDMN_MODE_11AC_VHT40MINUS_BIT, /* 5Ghz VHT40 - channels */ 399f0434a6eSspuligil REGDMN_MODE_11AC_VHT80 = 1 << REGDMN_MODE_11AC_VHT80_BIT, /* 5Ghz, VHT80 channels */ 400f0434a6eSspuligil REGDMN_MODE_11AC_VHT20_2G = 1 << REGDMN_MODE_11AC_VHT20_2G_BIT, /* 2Ghz, VHT20 */ 401f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2G = 1 << REGDMN_MODE_11AC_VHT40_2G_BIT, /* 2Ghz, VHT40 */ 402f0434a6eSspuligil REGDMN_MODE_11AC_VHT80_2G = 1 << REGDMN_MODE_11AC_VHT80_2G_BIT, /* 2Ghz, VHT80 */ 403f0434a6eSspuligil REGDMN_MODE_11AC_VHT160 = 1 << REGDMN_MODE_11AC_VHT160_BIT, /* 5Ghz, VHT160 */ 404f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2GPLUS = 1 << REGDMN_MODE_11AC_VHT40_2GPLUS_BIT, /* 2Ghz, VHT40+ */ 405f0434a6eSspuligil REGDMN_MODE_11AC_VHT40_2GMINUS = 1 << REGDMN_MODE_11AC_VHT40_2GMINUS_BIT, /* 2Ghz, VHT40- */ 406f0434a6eSspuligil REGDMN_MODE_11AC_VHT80_80 = 1 << REGDMN_MODE_11AC_VHT80_80_BIT, /* 5GHz, VHT80+80 */ 407f0434a6eSspuligil }; 408f0434a6eSspuligil 409f0434a6eSspuligil enum { 410f0434a6eSspuligil REGDMN_MODE_U32_11AXG_HE20 = 1 << (REGDMN_MODE_11AXG_HE20_BIT - 32), 411f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE20 = 1 << (REGDMN_MODE_11AXA_HE20_BIT - 32), 412f0434a6eSspuligil REGDMN_MODE_U32_11AXG_HE40PLUS = 1 << (REGDMN_MODE_11AXG_HE40PLUS_BIT - 32), 413f0434a6eSspuligil REGDMN_MODE_U32_11AXG_HE40MINUS = 1 << (REGDMN_MODE_11AXG_HE40MINUS_BIT - 32), 414f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE40PLUS = 1 << (REGDMN_MODE_11AXA_HE40PLUS_BIT - 32), 415f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE40MINUS = 1 << (REGDMN_MODE_11AXA_HE40MINUS_BIT - 32), 416f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE80 = 1 << (REGDMN_MODE_11AXA_HE80_BIT - 32), 417f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE160 = 1 << (REGDMN_MODE_11AXA_HE160_BIT - 32), 418f0434a6eSspuligil REGDMN_MODE_U32_11AXA_HE80_80 = 1 << (REGDMN_MODE_11AXA_HE80_80_BIT - 32), 419e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEG_EHT20 = 1 << (REGDMN_MODE_11BEG_EHT20_BIT - 32), 420e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT20 = 1 << (REGDMN_MODE_11BEA_EHT20_BIT - 32), 421e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEG_EHT40PLUS = 1 << (REGDMN_MODE_11BEG_EHT40PLUS_BIT - 32), 422e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEG_EHT40MINUS = 1 << (REGDMN_MODE_11BEG_EHT40MINUS_BIT - 32), 423e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT40PLUS = 1 << (REGDMN_MODE_11BEA_EHT40PLUS_BIT - 32), 424e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT40MINUS = 1 << (REGDMN_MODE_11BEA_EHT40MINUS_BIT - 32), 425e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT80 = 1 << (REGDMN_MODE_11BEA_EHT80_BIT - 32), 426e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT160 = 1 << (REGDMN_MODE_11BEA_EHT160_BIT - 32), 427e560c8b5SPragaspathi Thilagaraj REGDMN_MODE_U32_11BEA_EHT320 = 1 << (REGDMN_MODE_11BEA_EHT320_BIT - 32), 428dea4501bSVishwajith Upendra }; 429dea4501bSVishwajith Upendra 430dea4501bSVishwajith Upendra #define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum 431dea4501bSVishwajith Upendra * to prevent the ARM compile "warning #66: 432dea4501bSVishwajith Upendra * enumeration value is out of int range" 433dea4501bSVishwajith Upendra * Anyway, this is a BIT-OR of all possible values. 434dea4501bSVishwajith Upendra */ 435dea4501bSVishwajith Upendra 436dea4501bSVishwajith Upendra #define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001 437dea4501bSVishwajith Upendra #define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002 438dea4501bSVishwajith Upendra #define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004 439dea4501bSVishwajith Upendra 44090c68bd3Sqcabuildsw 441dea4501bSVishwajith Upendra /* regulatory capabilities */ 442dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 443dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 444dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100 445dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 446dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 447dea4501bSVishwajith Upendra #define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 448dea4501bSVishwajith Upendra 449dea4501bSVishwajith Upendra typedef struct { 450dea4501bSVishwajith Upendra A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */ 451dea4501bSVishwajith Upendra A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */ 452dea4501bSVishwajith Upendra A_UINT32 eeprom_rd_ext; /* regdomain */ 453dea4501bSVishwajith Upendra A_UINT32 regcap1; /* CAP1 capabilities bit map. */ 454dea4501bSVishwajith Upendra A_UINT32 regcap2; /* REGDMN EEPROM CAP. */ 455dea4501bSVishwajith Upendra A_UINT32 wireless_modes; /* REGDMN MODE */ 456dea4501bSVishwajith Upendra A_UINT32 low_2ghz_chan; 457dea4501bSVishwajith Upendra A_UINT32 high_2ghz_chan; 458dea4501bSVishwajith Upendra A_UINT32 low_5ghz_chan; 459dea4501bSVishwajith Upendra A_UINT32 high_5ghz_chan; 460f0434a6eSspuligil A_UINT32 wireless_modes_ext; /* REGDMN MODE ext */ 4612c8535ecSspuligil A_UINT32 low_2ghz_chan_ext; 4622c8535ecSspuligil A_UINT32 high_2ghz_chan_ext; 4632c8535ecSspuligil A_UINT32 low_5ghz_chan_ext; 4642c8535ecSspuligil A_UINT32 high_5ghz_chan_ext; 465dea4501bSVishwajith Upendra } HAL_REG_CAPABILITIES; 466dea4501bSVishwajith Upendra 4674ba0d98aSSandeep Puligilla #ifdef NUM_SPATIAL_STREAM 46890c68bd3Sqcabuildsw /* 46990c68bd3Sqcabuildsw * The rate control definitions below are only used in the target. 47090c68bd3Sqcabuildsw * (Host-based rate control is no longer applicable.) 47190c68bd3Sqcabuildsw * Maintain the defs in wlanfw_cmn for the sake of existing Rome / Helium 47290c68bd3Sqcabuildsw * targets, but for Lithium targets remove them from wlanfw_cmn and define 47390c68bd3Sqcabuildsw * them in a target-only location instead. 47490c68bd3Sqcabuildsw * SUPPORT_11AX is essentially used as a condition to identify Lithium targets. 47590c68bd3Sqcabuildsw * Some host drivers would also have SUPPORT_11AX defined, and thus would lose 47690c68bd3Sqcabuildsw * the definition of RATE_CODE, RC_TX_DONE_PARAMS, and related macros, but 47790c68bd3Sqcabuildsw * that's okay because the host should have no references to these 47890c68bd3Sqcabuildsw * target-only data structures. 47990c68bd3Sqcabuildsw */ 48090c68bd3Sqcabuildsw #if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) /* following N/A for Lithium */ 48190c68bd3Sqcabuildsw 482dea4501bSVishwajith Upendra /* 483dea4501bSVishwajith Upendra * Used to update rate-control logic with the status of the tx-completion. 4849af1257eSspuligil * In host-based implementation of the rate-control feature, this structure 4859af1257eSspuligil * is used to create the payload for HTT message/s from target to host. 486dea4501bSVishwajith Upendra */ 4872fdd9ac6Sspuligil #ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE 48890c68bd3Sqcabuildsw #if (NUM_SPATIAL_STREAM > 3) 48990c68bd3Sqcabuildsw #define A_RATEMASK A_UINT64 49090c68bd3Sqcabuildsw #else 49190c68bd3Sqcabuildsw #define A_RATEMASK A_UINT32 49290c68bd3Sqcabuildsw #endif 4932fdd9ac6Sspuligil #endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */ 49490c68bd3Sqcabuildsw 49590c68bd3Sqcabuildsw typedef A_UINT8 A_RATE; 49690c68bd3Sqcabuildsw typedef A_UINT8 A_RATECODE; 49790c68bd3Sqcabuildsw 49890c68bd3Sqcabuildsw #define A_RATEMASK_NUM_OCTET (sizeof (A_RATEMASK)) 49990c68bd3Sqcabuildsw #define A_RATEMASK_NUM_BITS ((sizeof (A_RATEMASK)) << 3) 50090c68bd3Sqcabuildsw 501dea4501bSVishwajith Upendra typedef struct { 50290c68bd3Sqcabuildsw A_RATECODE rateCode; 503dea4501bSVishwajith Upendra A_UINT8 flags; 504dea4501bSVishwajith Upendra } RATE_CODE; 505dea4501bSVishwajith Upendra 506dea4501bSVishwajith Upendra typedef struct { 507dea4501bSVishwajith Upendra RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */ 508dea4501bSVishwajith Upendra A_UINT8 reserved[2]; 509dea4501bSVishwajith Upendra A_UINT32 flags; /* Encodes information such as excessive 510dea4501bSVishwajith Upendra retransmission, aggregate, some info 511dea4501bSVishwajith Upendra from .11 frame control, 512dea4501bSVishwajith Upendra STBC, LDPC, (SGI and Tx Chain Mask 513dea4501bSVishwajith Upendra are encoded in ptx_rc->flags field), 514dea4501bSVishwajith Upendra AMPDU truncation (BT/time based etc.), 515dea4501bSVishwajith Upendra RTS/CTS attempt */ 516dea4501bSVishwajith Upendra A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ 517dea4501bSVishwajith Upendra A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ 518dea4501bSVishwajith Upendra A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ 519dea4501bSVishwajith Upendra A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ 520dea4501bSVishwajith Upendra A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ 521dea4501bSVishwajith Upendra A_UINT32 is_probe; /* Valid if probing. Else, 0 */ 522dea4501bSVishwajith Upendra A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */ 523dea4501bSVishwajith Upendra A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */ 524dea4501bSVishwajith Upendra A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */ 525dea4501bSVishwajith Upendra A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */ 526dea4501bSVishwajith Upendra A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */ 527dea4501bSVishwajith Upendra } RC_TX_DONE_PARAMS; 528dea4501bSVishwajith Upendra 52990c68bd3Sqcabuildsw 530dea4501bSVishwajith Upendra #define RC_SET_TX_DONE_INFO(_dst, _rc, _f, _nq, _nr, _nf, _rssi, _ts) \ 531dea4501bSVishwajith Upendra do { \ 532dea4501bSVishwajith Upendra (_dst).ptx_rc.rateCode = (_rc).rateCode; \ 533dea4501bSVishwajith Upendra (_dst).ptx_rc.flags = (_rc).flags; \ 534dea4501bSVishwajith Upendra (_dst).flags = (_f); \ 535dea4501bSVishwajith Upendra (_dst).num_enqued = (_nq); \ 536dea4501bSVishwajith Upendra (_dst).num_retries = (_nr); \ 537dea4501bSVishwajith Upendra (_dst).num_failed = (_nf); \ 538dea4501bSVishwajith Upendra (_dst).ack_rssi = (_rssi); \ 539dea4501bSVishwajith Upendra (_dst).time_stamp = (_ts); \ 540dea4501bSVishwajith Upendra } while (0) 541dea4501bSVishwajith Upendra 542dea4501bSVishwajith Upendra #define RC_SET_TXBF_DONE_INFO(_dst, _f) \ 543dea4501bSVishwajith Upendra do { \ 544dea4501bSVishwajith Upendra (_dst).flags |= (_f); \ 545dea4501bSVishwajith Upendra } while (0) 546dea4501bSVishwajith Upendra 547fc0c85ccSspuligil /* 548fc0c85ccSspuligil * NOTE: NUM_SCHED_ENTRIES is not used in the host/target interface, but for 549fc0c85ccSspuligil * historical reasons has been defined in the host/target interface files. 550fc0c85ccSspuligil * The NUM_SCHED_ENTRIES definition is being moved into a target-only 551fc0c85ccSspuligil * header file for newer (Lithium) targets, but is being left here for 552fc0c85ccSspuligil * non-Lithium cases, to avoid having to rework legacy targets to move 553fc0c85ccSspuligil * the NUM_SCHED_ENTRIES definition into a target-only header file. 554fc0c85ccSspuligil * Moving the NUM_SCHED_ENTRIES definition into a non-Lithium conditional 555fc0c85ccSspuligil * block should have no impact on the host, since the host does not use 556fc0c85ccSspuligil * NUM_SCHED_ENTRIES. 557fc0c85ccSspuligil */ 558fc0c85ccSspuligil #define NUM_SCHED_ENTRIES 2 559fc0c85ccSspuligil 56090c68bd3Sqcabuildsw #endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */ /* above N/A for Lithium */ 5612db4b64aSqcabuildsw #endif /* NUM_SPATIAL_STREAM */ 56290c68bd3Sqcabuildsw 563fc0c85ccSspuligil /* NOTE: NUM_DYN_BW cannot be changed without breaking WMI Compatibility */ 564dea4501bSVishwajith Upendra #define NUM_DYN_BW_MAX 4 565dea4501bSVishwajith Upendra 566dea4501bSVishwajith Upendra /* Some products only use 20/40/80; some use 20/40/80/160 */ 567dea4501bSVishwajith Upendra #ifndef NUM_DYN_BW 56890c68bd3Sqcabuildsw #define NUM_DYN_BW 3 /* default: support up through 80 MHz */ 569dea4501bSVishwajith Upendra #endif 570dea4501bSVishwajith Upendra 571dea4501bSVishwajith Upendra #define NUM_DYN_BW_MASK 0x3 572dea4501bSVishwajith Upendra 573dea4501bSVishwajith Upendra #define PROD_SCHED_BW_ENTRIES (NUM_SCHED_ENTRIES * NUM_DYN_BW) 574dea4501bSVishwajith Upendra 575ec05a7c9Sspuligil #if NUM_DYN_BW > 5 576dea4501bSVishwajith Upendra /* Extend rate table module first */ 577dea4501bSVishwajith Upendra #error "Extend rate table module first" 578dea4501bSVishwajith Upendra #endif 579dea4501bSVishwajith Upendra 58090c68bd3Sqcabuildsw #define MAX_IBSS_PEERS 32 581dea4501bSVishwajith Upendra 5824ba0d98aSSandeep Puligilla #ifdef NUM_SPATIAL_STREAM 58390c68bd3Sqcabuildsw /* 58490c68bd3Sqcabuildsw * RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO defs are used only in the target. 58590c68bd3Sqcabuildsw * (Host-based rate control is no longer applicable.) 58690c68bd3Sqcabuildsw * Maintain the defs in wlanfw_cmn for the sake of existing Rome / Helium 58790c68bd3Sqcabuildsw * targets, but for Lithium targets remove them from wlanfw_cmn and define 58890c68bd3Sqcabuildsw * them in a target-only location instead. 58990c68bd3Sqcabuildsw * SUPPORT_11AX is essentially used as a condition to identify Lithium targets. 59090c68bd3Sqcabuildsw * Some host drivers would also have SUPPORT_11AX defined, and thus would lose 59190c68bd3Sqcabuildsw * the definition of RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO, but that's okay 59290c68bd3Sqcabuildsw * because the host should have no references to these target-only data 59390c68bd3Sqcabuildsw * structures. 59490c68bd3Sqcabuildsw */ 595326b09cfSspuligil #ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE 59690c68bd3Sqcabuildsw #if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) 597dea4501bSVishwajith Upendra #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) 598dea4501bSVishwajith Upendra typedef struct{ 599dea4501bSVishwajith Upendra A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 600dea4501bSVishwajith Upendra A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 601dea4501bSVishwajith Upendra A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 602dea4501bSVishwajith Upendra A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 603dea4501bSVishwajith Upendra A_UINT32 antmask[NUM_SCHED_ENTRIES]; 604dea4501bSVishwajith Upendra A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 605dea4501bSVishwajith Upendra A_UINT16 txbf_cv_len; 606dea4501bSVishwajith Upendra A_UINT32 txbf_cv_ptr; 607dea4501bSVishwajith Upendra A_UINT16 txbf_flags; 608dea4501bSVishwajith Upendra A_UINT16 txbf_cv_size; 609dea4501bSVishwajith Upendra A_UINT8 txbf_nc_idx; 610dea4501bSVishwajith Upendra A_UINT8 tries[NUM_SCHED_ENTRIES]; 611dea4501bSVishwajith Upendra A_UINT8 bw_mask[NUM_SCHED_ENTRIES]; 612dea4501bSVishwajith Upendra A_UINT8 max_bw[NUM_SCHED_ENTRIES]; 613dea4501bSVishwajith Upendra A_UINT8 num_sched_entries; 614dea4501bSVishwajith Upendra A_UINT8 paprd_mask; 61590c68bd3Sqcabuildsw A_RATE rts_rix; 616dea4501bSVishwajith Upendra A_UINT8 sh_pream; 617dea4501bSVishwajith Upendra A_UINT8 min_spacing_1_4_us; 618dea4501bSVishwajith Upendra A_UINT8 fixed_delims; 619dea4501bSVishwajith Upendra A_UINT8 bw_in_service; 620dea4501bSVishwajith Upendra A_RATE probe_rix; 621dea4501bSVishwajith Upendra A_UINT8 num_valid_rates; 622dea4501bSVishwajith Upendra A_UINT8 rtscts_tpc; 623dea4501bSVishwajith Upendra A_UINT8 dd_profile; 624dea4501bSVishwajith Upendra } RC_TX_RATE_SCHEDULE; 625dea4501bSVishwajith Upendra #else 626dea4501bSVishwajith Upendra typedef struct{ 627dea4501bSVishwajith Upendra A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 628dea4501bSVishwajith Upendra A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 629dea4501bSVishwajith Upendra A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 630dea4501bSVishwajith Upendra A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 631dea4501bSVishwajith Upendra A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 632dea4501bSVishwajith Upendra A_UINT32 antmask[NUM_SCHED_ENTRIES]; 633dea4501bSVishwajith Upendra A_UINT32 txbf_cv_ptr; 634dea4501bSVishwajith Upendra A_UINT16 txbf_cv_len; 635dea4501bSVishwajith Upendra A_UINT8 tries[NUM_SCHED_ENTRIES]; 636dea4501bSVishwajith Upendra A_UINT8 num_valid_rates; 637dea4501bSVishwajith Upendra A_UINT8 paprd_mask; 63890c68bd3Sqcabuildsw A_RATE rts_rix; 639dea4501bSVishwajith Upendra A_UINT8 sh_pream; 640dea4501bSVishwajith Upendra A_UINT8 min_spacing_1_4_us; 641dea4501bSVishwajith Upendra A_UINT8 fixed_delims; 642dea4501bSVishwajith Upendra A_UINT8 bw_in_service; 643dea4501bSVishwajith Upendra A_RATE probe_rix; 644dea4501bSVishwajith Upendra } RC_TX_RATE_SCHEDULE; 645dea4501bSVishwajith Upendra #endif 646dea4501bSVishwajith Upendra 647dea4501bSVishwajith Upendra typedef struct{ 648dea4501bSVishwajith Upendra A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 649dea4501bSVishwajith Upendra A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 650dea4501bSVishwajith Upendra #ifdef DYN_TPC_ENABLE 651dea4501bSVishwajith Upendra A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 652dea4501bSVishwajith Upendra #endif 653dea4501bSVishwajith Upendra #ifdef SECTORED_ANTENNA 654dea4501bSVishwajith Upendra A_UINT32 antmask[NUM_SCHED_ENTRIES]; 655dea4501bSVishwajith Upendra #endif 656dea4501bSVishwajith Upendra A_UINT8 tries[NUM_SCHED_ENTRIES]; 657dea4501bSVishwajith Upendra A_UINT8 num_valid_rates; 65890c68bd3Sqcabuildsw A_RATE rts_rix; 659dea4501bSVishwajith Upendra A_UINT8 sh_pream; 660dea4501bSVishwajith Upendra A_UINT8 bw_in_service; 661dea4501bSVishwajith Upendra A_RATE probe_rix; 662dea4501bSVishwajith Upendra A_UINT8 dd_profile; 663dea4501bSVishwajith Upendra } RC_TX_RATE_INFO; 66490c68bd3Sqcabuildsw #endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */ 665326b09cfSspuligil #endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */ 6664ba0d98aSSandeep Puligilla #endif 667dea4501bSVishwajith Upendra 668dea4501bSVishwajith Upendra /* 66990c68bd3Sqcabuildsw * Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defs.h 670dea4501bSVishwajith Upendra * for older targets. 671dea4501bSVishwajith Upendra * The WHAL_RX_INIT_RC_MASKS macro def needs to be moved into ratectrl_11ac.h 672dea4501bSVishwajith Upendra * for all targets, but until this is complete, the WHAL_RC_INIT_RC_MASKS def 673dea4501bSVishwajith Upendra * will be maintained here in its old location. 674dea4501bSVishwajith Upendra */ 6751ed83134Sspuligil #ifndef CONFIG_160MHZ_SUPPORT 676dea4501bSVishwajith Upendra #define WHAL_RC_INIT_RC_MASKS(_rm) do { \ 677dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \ 678dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \ 679dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \ 680dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \ 681dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \ 682dea4501bSVishwajith Upendra _rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \ 683dea4501bSVishwajith Upendra } while (0) 684dea4501bSVishwajith Upendra #endif 685dea4501bSVishwajith Upendra 686dea4501bSVishwajith Upendra /** 6879af1257eSspuligil * structure describing host memory chunk. 688dea4501bSVishwajith Upendra */ 689dea4501bSVishwajith Upendra typedef struct { 690dea4501bSVishwajith Upendra A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */ 691dea4501bSVishwajith Upendra /** id of the request that is passed up in service ready */ 692dea4501bSVishwajith Upendra A_UINT32 req_id; 693dea4501bSVishwajith Upendra /** the physical address the memory chunk */ 694dea4501bSVishwajith Upendra A_UINT32 ptr; 695dea4501bSVishwajith Upendra /** size of the chunk */ 696dea4501bSVishwajith Upendra A_UINT32 size; 6977e0a3422Sspuligil /** ptr_high 6987e0a3422Sspuligil * most significant bits of physical address of the memory chunk 6997e0a3422Sspuligil * Only applicable for addressing more than 32 bit. 7007e0a3422Sspuligil * This will only be non-zero if the target has set 7017e0a3422Sspuligil * WMI_SERVICE_SUPPORT_EXTEND_ADDRESS flag. 7027e0a3422Sspuligil */ 7037e0a3422Sspuligil A_UINT32 ptr_high; 704dea4501bSVishwajith Upendra } wlan_host_memory_chunk; 705dea4501bSVishwajith Upendra 706dea4501bSVishwajith Upendra #define NUM_UNITS_IS_NUM_VDEVS 0x1 707dea4501bSVishwajith Upendra #define NUM_UNITS_IS_NUM_PEERS 0x2 708dea4501bSVishwajith Upendra #define NUM_UNITS_IS_NUM_ACTIVE_PEERS 0x4 709dea4501bSVishwajith Upendra /* request host to allocate memory contiguously */ 710dea4501bSVishwajith Upendra #define REQ_TO_HOST_FOR_CONT_MEMORY 0x8 711dea4501bSVishwajith Upendra 712dea4501bSVishwajith Upendra /** 713dea4501bSVishwajith Upendra * structure used by FW for requesting host memory 714dea4501bSVishwajith Upendra */ 715dea4501bSVishwajith Upendra typedef struct { 716dea4501bSVishwajith Upendra A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */ 717dea4501bSVishwajith Upendra 718dea4501bSVishwajith Upendra /** ID of the request */ 719dea4501bSVishwajith Upendra A_UINT32 req_id; 720dea4501bSVishwajith Upendra /** size of the of each unit */ 721dea4501bSVishwajith Upendra A_UINT32 unit_size; 722dea4501bSVishwajith Upendra /** 723dea4501bSVishwajith Upendra * flags to indicate that 724dea4501bSVishwajith Upendra * the number units is dependent 725dea4501bSVishwajith Upendra * on number of resources(num vdevs num peers .. etc) 726dea4501bSVishwajith Upendra */ 727dea4501bSVishwajith Upendra A_UINT32 num_unit_info; 728dea4501bSVishwajith Upendra /* 729dea4501bSVishwajith Upendra * actual number of units to allocate . if flags in the num_unit_info 730dea4501bSVishwajith Upendra * indicate that number of units is tied to number of a particular 731dea4501bSVishwajith Upendra * resource to allocate then num_units filed is set to 0 and host 732dea4501bSVishwajith Upendra * will derive the number units from number of the resources it is 733dea4501bSVishwajith Upendra * requesting. 734dea4501bSVishwajith Upendra */ 735dea4501bSVishwajith Upendra A_UINT32 num_units; 736dea4501bSVishwajith Upendra } wlan_host_mem_req; 737dea4501bSVishwajith Upendra 738dea4501bSVishwajith Upendra typedef enum { 739dea4501bSVishwajith Upendra IGNORE_DTIM = 0x01, 740dea4501bSVishwajith Upendra NORMAL_DTIM = 0x02, 741dea4501bSVishwajith Upendra STICK_DTIM = 0x03, 742dea4501bSVishwajith Upendra AUTO_DTIM = 0x04, 743dea4501bSVishwajith Upendra } BEACON_DTIM_POLICY; 744dea4501bSVishwajith Upendra 745dea4501bSVishwajith Upendra /* During test it is observed that 6 * 400 = 2400 can 746dea4501bSVishwajith Upendra * be alloced in addition to CFG_TGT_NUM_MSDU_DESC. 747dea4501bSVishwajith Upendra * If there is any change memory requirement, this number 748dea4501bSVishwajith Upendra * needs to be revisited. */ 749dea4501bSVishwajith Upendra #define TOTAL_VOW_ALLOCABLE 2400 750dea4501bSVishwajith Upendra #define VOW_DESC_GRAB_MAX 800 751dea4501bSVishwajith Upendra 752dea4501bSVishwajith Upendra #define VOW_GET_NUM_VI_STA(vow_config) (((vow_config) & 0xffff0000) >> 16) 753dea4501bSVishwajith Upendra #define VOW_GET_DESC_PER_VI_STA(vow_config) ((vow_config) & 0x0000ffff) 754dea4501bSVishwajith Upendra 755dea4501bSVishwajith Upendra /***TODO!!! Get these values dynamically in WMI_READY event and use it to calculate the mem req*/ 756dea4501bSVishwajith Upendra /* size in bytes required for msdu descriptor. If it changes, this should be updated. LARGE_AP 757dea4501bSVishwajith Upendra * case is not considered. LARGE_AP is disabled when VoW is enabled.*/ 758dea4501bSVishwajith Upendra #define MSDU_DESC_SIZE 20 759dea4501bSVishwajith Upendra 760dea4501bSVishwajith Upendra /* size in bytes required to support a peer in target. 761dea4501bSVishwajith Upendra * This obtained by considering Two tids per peer. 762dea4501bSVishwajith Upendra * peer structure = 168 bytes 763dea4501bSVishwajith Upendra * tid = 96 bytes (per sta 2 means we need 192 bytes) 764dea4501bSVishwajith Upendra * peer_cb = 16 * 2 765dea4501bSVishwajith Upendra * key = 52 * 2 766dea4501bSVishwajith Upendra * AST = 12 * 2 767dea4501bSVishwajith Upendra * rate, reorder.. = 384 768dea4501bSVishwajith Upendra * smart antenna = 50 769dea4501bSVishwajith Upendra */ 770dea4501bSVishwajith Upendra #define MEMORY_REQ_FOR_PEER 800 771dea4501bSVishwajith Upendra /* 772dea4501bSVishwajith Upendra * NB: it is important to keep all the fields in the structure dword long 773dea4501bSVishwajith Upendra * so that it is easy to handle the statistics in BE host. 774dea4501bSVishwajith Upendra */ 775dea4501bSVishwajith Upendra 776594ae963Sspuligil /* 777594ae963Sspuligil * wlan_dbg_tx_stats_v1, _v2: 778594ae963Sspuligil * differing versions of the wlan_dbg_tx_stats struct used by different 779594ae963Sspuligil * targets 780594ae963Sspuligil */ 781594ae963Sspuligil struct wlan_dbg_tx_stats_v1 { 782dea4501bSVishwajith Upendra /* Num HTT cookies queued to dispatch list */ 783dea4501bSVishwajith Upendra A_INT32 comp_queued; 784dea4501bSVishwajith Upendra /* Num HTT cookies dispatched */ 785dea4501bSVishwajith Upendra A_INT32 comp_delivered; 786dea4501bSVishwajith Upendra /* Num MSDU queued to WAL */ 787dea4501bSVishwajith Upendra A_INT32 msdu_enqued; 788dea4501bSVishwajith Upendra /* Num MPDU queue to WAL */ 789dea4501bSVishwajith Upendra A_INT32 mpdu_enqued; 790dea4501bSVishwajith Upendra /* Num MSDUs dropped by WMM limit */ 791dea4501bSVishwajith Upendra A_INT32 wmm_drop; 792dea4501bSVishwajith Upendra /* Num Local frames queued */ 793dea4501bSVishwajith Upendra A_INT32 local_enqued; 794dea4501bSVishwajith Upendra /* Num Local frames done */ 795dea4501bSVishwajith Upendra A_INT32 local_freed; 796dea4501bSVishwajith Upendra /* Num queued to HW */ 797dea4501bSVishwajith Upendra A_INT32 hw_queued; 798dea4501bSVishwajith Upendra /* Num PPDU reaped from HW */ 799dea4501bSVishwajith Upendra A_INT32 hw_reaped; 800dea4501bSVishwajith Upendra /* Num underruns */ 801dea4501bSVishwajith Upendra A_INT32 underrun; 802dea4501bSVishwajith Upendra /* Num PPDUs cleaned up in TX abort */ 803dea4501bSVishwajith Upendra A_INT32 tx_abort; 804dea4501bSVishwajith Upendra /* Num MPDUs requed by SW */ 805dea4501bSVishwajith Upendra A_INT32 mpdus_requed; 806dea4501bSVishwajith Upendra /* excessive retries */ 807dea4501bSVishwajith Upendra A_UINT32 tx_ko; 808dea4501bSVishwajith Upendra /* data hw rate code */ 809dea4501bSVishwajith Upendra A_UINT32 data_rc; 810dea4501bSVishwajith Upendra /* Scheduler self triggers */ 811dea4501bSVishwajith Upendra A_UINT32 self_triggers; 812dea4501bSVishwajith Upendra /* frames dropped due to excessive sw retries */ 813dea4501bSVishwajith Upendra A_UINT32 sw_retry_failure; 814dea4501bSVishwajith Upendra /* illegal rate phy errors */ 815dea4501bSVishwajith Upendra A_UINT32 illgl_rate_phy_err; 8169af1257eSspuligil /* wal pdev continuous xretry */ 817dea4501bSVishwajith Upendra A_UINT32 pdev_cont_xretry; 8189af1257eSspuligil /* wal pdev continuous xretry */ 819dea4501bSVishwajith Upendra A_UINT32 pdev_tx_timeout; 820dea4501bSVishwajith Upendra /* wal pdev resets */ 821dea4501bSVishwajith Upendra A_UINT32 pdev_resets; 822dea4501bSVishwajith Upendra /* frames dropped due to non-availability of stateless TIDs */ 823dea4501bSVishwajith Upendra A_UINT32 stateless_tid_alloc_failure; 824dea4501bSVishwajith Upendra /* PhY/BB underrun */ 825dea4501bSVishwajith Upendra A_UINT32 phy_underrun; 826dea4501bSVishwajith Upendra /* MPDU is more than txop limit */ 827dea4501bSVishwajith Upendra A_UINT32 txop_ovf; 828594ae963Sspuligil }; 829594ae963Sspuligil 830594ae963Sspuligil struct wlan_dbg_tx_stats_v2 { 831594ae963Sspuligil /* Num HTT cookies queued to dispatch list */ 832594ae963Sspuligil A_INT32 comp_queued; 833594ae963Sspuligil /* Num HTT cookies dispatched */ 834594ae963Sspuligil A_INT32 comp_delivered; 835594ae963Sspuligil /* Num MSDU queued to WAL */ 836594ae963Sspuligil A_INT32 msdu_enqued; 837594ae963Sspuligil /* Num MPDU queue to WAL */ 838594ae963Sspuligil A_INT32 mpdu_enqued; 839594ae963Sspuligil /* Num MSDUs dropped by WMM limit */ 840594ae963Sspuligil A_INT32 wmm_drop; 841594ae963Sspuligil /* Num Local frames queued */ 842594ae963Sspuligil A_INT32 local_enqued; 843594ae963Sspuligil /* Num Local frames done */ 844594ae963Sspuligil A_INT32 local_freed; 845594ae963Sspuligil /* Num queued to HW */ 846594ae963Sspuligil A_INT32 hw_queued; 847594ae963Sspuligil /* Num PPDU reaped from HW */ 848594ae963Sspuligil A_INT32 hw_reaped; 849594ae963Sspuligil /* Num underruns */ 850594ae963Sspuligil A_INT32 underrun; 851594ae963Sspuligil /* HW Paused. */ 852594ae963Sspuligil A_UINT32 hw_paused; 853594ae963Sspuligil /* Num PPDUs cleaned up in TX abort */ 854594ae963Sspuligil A_INT32 tx_abort; 855594ae963Sspuligil /* Num MPDUs requed by SW */ 856594ae963Sspuligil A_INT32 mpdus_requed; 857594ae963Sspuligil /* excessive retries */ 858594ae963Sspuligil A_UINT32 tx_ko; 859594ae963Sspuligil A_UINT32 tx_xretry; 860594ae963Sspuligil /* data hw rate code */ 861594ae963Sspuligil A_UINT32 data_rc; 862594ae963Sspuligil /* Scheduler self triggers */ 863594ae963Sspuligil A_UINT32 self_triggers; 864594ae963Sspuligil /* frames dropped due to excessive sw retries */ 865594ae963Sspuligil A_UINT32 sw_retry_failure; 866594ae963Sspuligil /* illegal rate phy errors */ 867594ae963Sspuligil A_UINT32 illgl_rate_phy_err; 8689af1257eSspuligil /* wal pdev continuous xretry */ 869594ae963Sspuligil A_UINT32 pdev_cont_xretry; 8709af1257eSspuligil /* wal pdev continuous xretry */ 871594ae963Sspuligil A_UINT32 pdev_tx_timeout; 872594ae963Sspuligil /* wal pdev resets */ 873594ae963Sspuligil A_UINT32 pdev_resets; 874594ae963Sspuligil /* frames dropped due to non-availability of stateless TIDs */ 875594ae963Sspuligil A_UINT32 stateless_tid_alloc_failure; 876594ae963Sspuligil /* PhY/BB underrun */ 877594ae963Sspuligil A_UINT32 phy_underrun; 878594ae963Sspuligil /* MPDU is more than txop limit */ 879594ae963Sspuligil A_UINT32 txop_ovf; 880dea4501bSVishwajith Upendra /* Number of Sequences posted */ 881dea4501bSVishwajith Upendra A_UINT32 seq_posted; 882dea4501bSVishwajith Upendra /* Number of Sequences failed queueing */ 883dea4501bSVishwajith Upendra A_UINT32 seq_failed_queueing; 884dea4501bSVishwajith Upendra /* Number of Sequences completed */ 885dea4501bSVishwajith Upendra A_UINT32 seq_completed; 886dea4501bSVishwajith Upendra /* Number of Sequences restarted */ 887dea4501bSVishwajith Upendra A_UINT32 seq_restarted; 888dea4501bSVishwajith Upendra /* Number of MU Sequences posted */ 889dea4501bSVishwajith Upendra A_UINT32 mu_seq_posted; 890dea4501bSVishwajith Upendra /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 891dea4501bSVishwajith Upendra A_INT32 mpdus_sw_flush; 892dea4501bSVishwajith Upendra /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 893dea4501bSVishwajith Upendra A_INT32 mpdus_hw_filter; 894dea4501bSVishwajith Upendra /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ 895dea4501bSVishwajith Upendra A_INT32 mpdus_truncated; 896dea4501bSVishwajith Upendra /* Num MPDUs that was tried but didn't receive ACK or BA */ 897dea4501bSVishwajith Upendra A_INT32 mpdus_ack_failed; 898dea4501bSVishwajith Upendra /* Num MPDUs that was dropped du to expiry. */ 899dea4501bSVishwajith Upendra A_INT32 mpdus_expired; 900dea4501bSVishwajith Upendra }; 901dea4501bSVishwajith Upendra 902594ae963Sspuligil #if defined(AR900B) 903594ae963Sspuligil #define wlan_dbg_tx_stats wlan_dbg_tx_stats_v2 904594ae963Sspuligil #else 905594ae963Sspuligil #define wlan_dbg_tx_stats wlan_dbg_tx_stats_v1 906594ae963Sspuligil #endif 907594ae963Sspuligil 908594ae963Sspuligil /* 909594ae963Sspuligil * wlan_dbg_rx_stats_v1, _v2: 910594ae963Sspuligil * differing versions of the wlan_dbg_rx_stats struct used by different 911594ae963Sspuligil * targets 912594ae963Sspuligil */ 913594ae963Sspuligil struct wlan_dbg_rx_stats_v1 { 914dea4501bSVishwajith Upendra /* Cnts any change in ring routing mid-ppdu */ 915dea4501bSVishwajith Upendra A_INT32 mid_ppdu_route_change; 916dea4501bSVishwajith Upendra /* Total number of statuses processed */ 917dea4501bSVishwajith Upendra A_INT32 status_rcvd; 918dea4501bSVishwajith Upendra /* Extra frags on rings 0-3 */ 919dea4501bSVishwajith Upendra A_INT32 r0_frags; 920dea4501bSVishwajith Upendra A_INT32 r1_frags; 921dea4501bSVishwajith Upendra A_INT32 r2_frags; 922dea4501bSVishwajith Upendra A_INT32 r3_frags; 923dea4501bSVishwajith Upendra /* MSDUs / MPDUs delivered to HTT */ 924dea4501bSVishwajith Upendra A_INT32 htt_msdus; 925dea4501bSVishwajith Upendra A_INT32 htt_mpdus; 926dea4501bSVishwajith Upendra /* MSDUs / MPDUs delivered to local stack */ 927dea4501bSVishwajith Upendra A_INT32 loc_msdus; 928dea4501bSVishwajith Upendra A_INT32 loc_mpdus; 929dea4501bSVishwajith Upendra /* AMSDUs that have more MSDUs than the status ring size */ 930dea4501bSVishwajith Upendra A_INT32 oversize_amsdu; 931dea4501bSVishwajith Upendra /* Number of PHY errors */ 932dea4501bSVishwajith Upendra A_INT32 phy_errs; 933dea4501bSVishwajith Upendra /* Number of PHY errors drops */ 934dea4501bSVishwajith Upendra A_INT32 phy_err_drop; 935dea4501bSVishwajith Upendra /* Number of mpdu errors - FCS, MIC, ENC etc. */ 936dea4501bSVishwajith Upendra A_INT32 mpdu_errs; 937dea4501bSVishwajith Upendra }; 938dea4501bSVishwajith Upendra 939594ae963Sspuligil struct wlan_dbg_rx_stats_v2 { 940594ae963Sspuligil /* Cnts any change in ring routing mid-ppdu */ 941594ae963Sspuligil A_INT32 mid_ppdu_route_change; 942594ae963Sspuligil /* Total number of statuses processed */ 943594ae963Sspuligil A_INT32 status_rcvd; 944594ae963Sspuligil /* Extra frags on rings 0-3 */ 945594ae963Sspuligil A_INT32 r0_frags; 946594ae963Sspuligil A_INT32 r1_frags; 947594ae963Sspuligil A_INT32 r2_frags; 948594ae963Sspuligil A_INT32 r3_frags; 949594ae963Sspuligil /* MSDUs / MPDUs delivered to HTT */ 950594ae963Sspuligil A_INT32 htt_msdus; 951594ae963Sspuligil A_INT32 htt_mpdus; 952594ae963Sspuligil /* MSDUs / MPDUs delivered to local stack */ 953594ae963Sspuligil A_INT32 loc_msdus; 954594ae963Sspuligil A_INT32 loc_mpdus; 955594ae963Sspuligil /* AMSDUs that have more MSDUs than the status ring size */ 956594ae963Sspuligil A_INT32 oversize_amsdu; 957594ae963Sspuligil /* Number of PHY errors */ 958594ae963Sspuligil A_INT32 phy_errs; 959594ae963Sspuligil /* Number of PHY errors drops */ 960594ae963Sspuligil A_INT32 phy_err_drop; 961594ae963Sspuligil /* Number of mpdu errors - FCS, MIC, ENC etc. */ 962594ae963Sspuligil A_INT32 mpdu_errs; 963594ae963Sspuligil /* Number of rx overflow errors. */ 964594ae963Sspuligil A_INT32 rx_ovfl_errs; 965594ae963Sspuligil }; 966594ae963Sspuligil 967594ae963Sspuligil #if defined(AR900B) 968594ae963Sspuligil #define wlan_dbg_rx_stats wlan_dbg_rx_stats_v2 969594ae963Sspuligil #else 970594ae963Sspuligil #define wlan_dbg_rx_stats wlan_dbg_rx_stats_v1 971594ae963Sspuligil #endif 97290c68bd3Sqcabuildsw 973dea4501bSVishwajith Upendra struct wlan_dbg_mem_stats { 974dea4501bSVishwajith Upendra A_UINT32 iram_free_size; 975dea4501bSVishwajith Upendra A_UINT32 dram_free_size; 976dea4501bSVishwajith Upendra }; 977dea4501bSVishwajith Upendra 978dea4501bSVishwajith Upendra struct wlan_dbg_peer_stats { 979dea4501bSVishwajith Upendra A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 980dea4501bSVishwajith Upendra }; 981dea4501bSVishwajith Upendra 982594ae963Sspuligil /* 983594ae963Sspuligil * wlan_dbg_rx_rate_info_v1a_t, _v1b_t: 984594ae963Sspuligil * differing versions of the wlan_dbg_rx_rate_info struct used by different 985594ae963Sspuligil * targets 986594ae963Sspuligil */ 987594ae963Sspuligil typedef struct { 988594ae963Sspuligil A_UINT32 mcs[10]; 989594ae963Sspuligil A_UINT32 sgi[10]; 990594ae963Sspuligil A_UINT32 nss[4]; 991594ae963Sspuligil A_UINT32 nsts; 992594ae963Sspuligil A_UINT32 stbc[10]; 993594ae963Sspuligil A_UINT32 bw[3]; 994594ae963Sspuligil A_UINT32 pream[6]; 995594ae963Sspuligil A_UINT32 ldpc; 996594ae963Sspuligil A_UINT32 txbf; 997594ae963Sspuligil A_UINT32 mgmt_rssi; 998594ae963Sspuligil A_UINT32 data_rssi; 999594ae963Sspuligil A_UINT32 rssi_chain0; 1000594ae963Sspuligil A_UINT32 rssi_chain1; 1001594ae963Sspuligil A_UINT32 rssi_chain2; 1002594ae963Sspuligil } wlan_dbg_rx_rate_info_v1a_t; 1003594ae963Sspuligil 1004dea4501bSVishwajith Upendra typedef struct { 1005dea4501bSVishwajith Upendra A_UINT32 mcs[10]; 1006dea4501bSVishwajith Upendra A_UINT32 sgi[10]; 1007dea4501bSVishwajith Upendra A_UINT32 nss[4]; 1008dea4501bSVishwajith Upendra A_UINT32 nsts; 1009dea4501bSVishwajith Upendra A_UINT32 stbc[10]; 1010dea4501bSVishwajith Upendra A_UINT32 bw[3]; 1011dea4501bSVishwajith Upendra A_UINT32 pream[6]; 1012dea4501bSVishwajith Upendra A_UINT32 ldpc; 1013dea4501bSVishwajith Upendra A_UINT32 txbf; 1014dea4501bSVishwajith Upendra A_UINT32 mgmt_rssi; 1015dea4501bSVishwajith Upendra A_UINT32 data_rssi; 1016dea4501bSVishwajith Upendra A_UINT32 rssi_chain0; 1017dea4501bSVishwajith Upendra A_UINT32 rssi_chain1; 1018dea4501bSVishwajith Upendra A_UINT32 rssi_chain2; 101990c68bd3Sqcabuildsw /* 102090c68bd3Sqcabuildsw * TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using 102190c68bd3Sqcabuildsw * rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t. 102290c68bd3Sqcabuildsw */ 1023dea4501bSVishwajith Upendra A_UINT32 rssi_chain3; 1024594ae963Sspuligil } wlan_dbg_rx_rate_info_v1b_t; 1025594ae963Sspuligil 1026594ae963Sspuligil #if defined(AR900B) 1027594ae963Sspuligil #define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1b_t 1028594ae963Sspuligil #else 1029594ae963Sspuligil #define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1a_t 1030dea4501bSVishwajith Upendra #endif 1031dea4501bSVishwajith Upendra 1032dea4501bSVishwajith Upendra typedef struct { 1033dea4501bSVishwajith Upendra A_UINT32 mcs[10]; 1034dea4501bSVishwajith Upendra A_UINT32 sgi[10]; 103590c68bd3Sqcabuildsw /* 103690c68bd3Sqcabuildsw * TEMPORARY: leave nss conditionally defined, until all code that 103790c68bd3Sqcabuildsw * requires nss[4] is converted to use wlan_dbg_tx_rate_info_v2_t. 103890c68bd3Sqcabuildsw * At that time, this nss array will be made length = 3 unconditionally. 103990c68bd3Sqcabuildsw */ 1040dea4501bSVishwajith Upendra #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) 1041dea4501bSVishwajith Upendra A_UINT32 nss[4]; 1042dea4501bSVishwajith Upendra #else 1043dea4501bSVishwajith Upendra A_UINT32 nss[3]; 1044dea4501bSVishwajith Upendra #endif 1045dea4501bSVishwajith Upendra A_UINT32 stbc[10]; 1046dea4501bSVishwajith Upendra A_UINT32 bw[3]; 1047dea4501bSVishwajith Upendra A_UINT32 pream[4]; 1048dea4501bSVishwajith Upendra A_UINT32 ldpc; 1049dea4501bSVishwajith Upendra A_UINT32 rts_cnt; 1050dea4501bSVishwajith Upendra A_UINT32 ack_rssi; 1051dea4501bSVishwajith Upendra } wlan_dbg_tx_rate_info_t ; 1052dea4501bSVishwajith Upendra 1053dea4501bSVishwajith Upendra #define WLAN_MAX_MCS 10 1054dea4501bSVishwajith Upendra 1055dea4501bSVishwajith Upendra typedef struct { 1056dea4501bSVishwajith Upendra A_UINT32 mcs[WLAN_MAX_MCS]; 1057dea4501bSVishwajith Upendra A_UINT32 sgi[WLAN_MAX_MCS]; 105890c68bd3Sqcabuildsw A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; 1059dea4501bSVishwajith Upendra A_UINT32 nsts; 1060dea4501bSVishwajith Upendra A_UINT32 stbc[WLAN_MAX_MCS]; 1061dea4501bSVishwajith Upendra A_UINT32 bw[NUM_DYN_BW_MAX]; 1062dea4501bSVishwajith Upendra A_UINT32 pream[6]; 1063dea4501bSVishwajith Upendra A_UINT32 ldpc; 1064dea4501bSVishwajith Upendra A_UINT32 txbf; 1065dea4501bSVishwajith Upendra A_UINT32 mgmt_rssi; 1066dea4501bSVishwajith Upendra A_UINT32 data_rssi; 1067dea4501bSVishwajith Upendra A_UINT32 rssi_chain0; 1068dea4501bSVishwajith Upendra A_UINT32 rssi_chain1; 1069dea4501bSVishwajith Upendra A_UINT32 rssi_chain2; 1070dea4501bSVishwajith Upendra A_UINT32 rssi_chain3; 1071dea4501bSVishwajith Upendra A_UINT32 reserved[8]; 1072dea4501bSVishwajith Upendra } wlan_dbg_rx_rate_info_v2_t; 1073dea4501bSVishwajith Upendra 1074dea4501bSVishwajith Upendra typedef struct { 1075dea4501bSVishwajith Upendra A_UINT32 mcs[WLAN_MAX_MCS]; 1076dea4501bSVishwajith Upendra A_UINT32 sgi[WLAN_MAX_MCS]; 107790c68bd3Sqcabuildsw A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; 1078dea4501bSVishwajith Upendra A_UINT32 stbc[WLAN_MAX_MCS]; 1079dea4501bSVishwajith Upendra A_UINT32 bw[NUM_DYN_BW_MAX]; 1080dea4501bSVishwajith Upendra A_UINT32 pream[4]; 1081dea4501bSVishwajith Upendra A_UINT32 ldpc; 1082dea4501bSVishwajith Upendra A_UINT32 rts_cnt; 1083dea4501bSVishwajith Upendra A_UINT32 ack_rssi; 1084dea4501bSVishwajith Upendra A_UINT32 reserved[8]; 1085dea4501bSVishwajith Upendra } wlan_dbg_tx_rate_info_v2_t; 1086dea4501bSVishwajith Upendra 108790c68bd3Sqcabuildsw typedef struct { 108890c68bd3Sqcabuildsw A_UINT32 mcs[WLAN_MAX_MCS]; 108990c68bd3Sqcabuildsw A_UINT32 sgi[WLAN_MAX_MCS]; 109090c68bd3Sqcabuildsw A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; 109190c68bd3Sqcabuildsw A_UINT32 nsts; 109290c68bd3Sqcabuildsw A_UINT32 stbc[WLAN_MAX_MCS]; 109390c68bd3Sqcabuildsw A_UINT32 bw[NUM_DYN_BW_MAX]; 109490c68bd3Sqcabuildsw A_UINT32 pream[6]; 109590c68bd3Sqcabuildsw A_UINT32 ldpc; 109690c68bd3Sqcabuildsw A_UINT32 txbf; 109790c68bd3Sqcabuildsw A_UINT32 mgmt_rssi; 109890c68bd3Sqcabuildsw A_UINT32 data_rssi; 109990c68bd3Sqcabuildsw A_UINT32 rssi_chain0; 110090c68bd3Sqcabuildsw A_UINT32 rssi_chain1; 110190c68bd3Sqcabuildsw A_UINT32 rssi_chain2; 110290c68bd3Sqcabuildsw A_UINT32 rssi_chain3; 110390c68bd3Sqcabuildsw A_UINT32 reserved[8]; 110490c68bd3Sqcabuildsw } wlan_dbg_rx_rate_info_v3_t; 110590c68bd3Sqcabuildsw 110690c68bd3Sqcabuildsw typedef struct { 110790c68bd3Sqcabuildsw A_UINT32 mcs[WLAN_MAX_MCS]; 110890c68bd3Sqcabuildsw A_UINT32 sgi[WLAN_MAX_MCS]; 110990c68bd3Sqcabuildsw A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; 111090c68bd3Sqcabuildsw A_UINT32 stbc[WLAN_MAX_MCS]; 111190c68bd3Sqcabuildsw A_UINT32 bw[NUM_DYN_BW_MAX]; 111290c68bd3Sqcabuildsw A_UINT32 pream[4]; 111390c68bd3Sqcabuildsw A_UINT32 ldpc; 111490c68bd3Sqcabuildsw A_UINT32 rts_cnt; 111590c68bd3Sqcabuildsw A_UINT32 ack_rssi; 111690c68bd3Sqcabuildsw A_UINT32 reserved[8]; 111790c68bd3Sqcabuildsw } wlan_dbg_tx_rate_info_v3_t; 111890c68bd3Sqcabuildsw 1119dea4501bSVishwajith Upendra #define WHAL_DBG_PHY_ERR_MAXCNT 18 1120dea4501bSVishwajith Upendra #define WHAL_DBG_SIFS_STATUS_MAXCNT 8 1121dea4501bSVishwajith Upendra #define WHAL_DBG_SIFS_ERR_MAXCNT 8 1122dea4501bSVishwajith Upendra #define WHAL_DBG_CMD_RESULT_MAXCNT 11 1123dea4501bSVishwajith Upendra #define WHAL_DBG_CMD_STALL_ERR_MAXCNT 4 1124dea4501bSVishwajith Upendra #define WHAL_DBG_FLUSH_REASON_MAXCNT 40 1125dea4501bSVishwajith Upendra 1126dea4501bSVishwajith Upendra typedef enum { 1127dea4501bSVishwajith Upendra WIFI_URRN_STATS_FIRST_PKT, 1128dea4501bSVishwajith Upendra WIFI_URRN_STATS_BETWEEN_MPDU, 1129dea4501bSVishwajith Upendra WIFI_URRN_STATS_WITHIN_MPDU, 1130dea4501bSVishwajith Upendra WHAL_MAX_URRN_STATS 1131dea4501bSVishwajith Upendra } wifi_urrn_type_t; 1132dea4501bSVishwajith Upendra 1133dea4501bSVishwajith Upendra typedef struct wlan_dbg_txbf_snd_stats { 1134dea4501bSVishwajith Upendra A_UINT32 cbf_20[4]; 1135dea4501bSVishwajith Upendra A_UINT32 cbf_40[4]; 1136dea4501bSVishwajith Upendra A_UINT32 cbf_80[4]; 1137dea4501bSVishwajith Upendra A_UINT32 sounding[9]; 1138dea4501bSVishwajith Upendra A_UINT32 cbf_160[4]; 1139dea4501bSVishwajith Upendra } wlan_dbg_txbf_snd_stats_t; 1140dea4501bSVishwajith Upendra 1141dea4501bSVishwajith Upendra typedef struct wlan_dbg_wifi2_error_stats { 1142dea4501bSVishwajith Upendra A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS]; 1143dea4501bSVishwajith Upendra A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT]; 1144dea4501bSVishwajith Upendra A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; 1145dea4501bSVishwajith Upendra A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT]; 1146dea4501bSVishwajith Upendra A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT]; 1147dea4501bSVishwajith Upendra A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT]; 1148dea4501bSVishwajith Upendra A_UINT32 rx_rate_inval; 1149dea4501bSVishwajith Upendra } wlan_dbg_wifi2_error_stats_t; 1150dea4501bSVishwajith Upendra 1151dea4501bSVishwajith Upendra typedef struct wlan_dbg_wifi2_error2_stats { 1152dea4501bSVishwajith Upendra A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; 1153dea4501bSVishwajith Upendra A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT]; 1154dea4501bSVishwajith Upendra } wlan_dbg_wifi2_error2_stats_t; 1155dea4501bSVishwajith Upendra 1156dea4501bSVishwajith Upendra #define WLAN_DBG_STATS_SIZE_TXBF_VHT 10 1157dea4501bSVishwajith Upendra #define WLAN_DBG_STATS_SIZE_TXBF_HT 8 1158dea4501bSVishwajith Upendra #define WLAN_DBG_STATS_SIZE_TXBF_OFDM 8 1159dea4501bSVishwajith Upendra #define WLAN_DBG_STATS_SIZE_TXBF_CCK 7 1160dea4501bSVishwajith Upendra 1161dea4501bSVishwajith Upendra typedef struct wlan_dbg_txbf_data_stats { 1162dea4501bSVishwajith Upendra A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; 1163dea4501bSVishwajith Upendra A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; 1164dea4501bSVishwajith Upendra A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT]; 1165dea4501bSVishwajith Upendra A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM]; 1166dea4501bSVishwajith Upendra A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK]; 1167dea4501bSVishwajith Upendra } wlan_dbg_txbf_data_stats_t; 1168dea4501bSVishwajith Upendra 1169dea4501bSVishwajith Upendra struct wlan_dbg_tx_mu_stats { 1170dea4501bSVishwajith Upendra A_UINT32 mu_sch_nusers_2; 1171dea4501bSVishwajith Upendra A_UINT32 mu_sch_nusers_3; 1172dea4501bSVishwajith Upendra A_UINT32 mu_mpdus_queued_usr[4]; 1173dea4501bSVishwajith Upendra A_UINT32 mu_mpdus_tried_usr[4]; 1174dea4501bSVishwajith Upendra A_UINT32 mu_mpdus_failed_usr[4]; 1175dea4501bSVishwajith Upendra A_UINT32 mu_mpdus_requeued_usr[4]; 1176dea4501bSVishwajith Upendra A_UINT32 mu_err_no_ba_usr[4]; 1177dea4501bSVishwajith Upendra A_UINT32 mu_mpdu_underrun_usr[4]; 1178dea4501bSVishwajith Upendra A_UINT32 mu_ampdu_underrun_usr[4]; 1179dea4501bSVishwajith Upendra }; 1180dea4501bSVishwajith Upendra 1181dea4501bSVishwajith Upendra struct wlan_dbg_tx_selfgen_stats { 1182dea4501bSVishwajith Upendra A_UINT32 su_ndpa; 1183dea4501bSVishwajith Upendra A_UINT32 su_ndp; 1184dea4501bSVishwajith Upendra A_UINT32 mu_ndpa; 1185dea4501bSVishwajith Upendra A_UINT32 mu_ndp; 1186dea4501bSVishwajith Upendra A_UINT32 mu_brpoll_1; 1187dea4501bSVishwajith Upendra A_UINT32 mu_brpoll_2; 1188dea4501bSVishwajith Upendra A_UINT32 mu_bar_1; 1189dea4501bSVishwajith Upendra A_UINT32 mu_bar_2; 1190dea4501bSVishwajith Upendra A_UINT32 cts_burst; 1191dea4501bSVishwajith Upendra A_UINT32 su_ndp_err; 1192dea4501bSVishwajith Upendra A_UINT32 su_ndpa_err; 1193dea4501bSVishwajith Upendra A_UINT32 mu_ndp_err; 1194dea4501bSVishwajith Upendra A_UINT32 mu_brp1_err; 1195dea4501bSVishwajith Upendra A_UINT32 mu_brp2_err; 1196dea4501bSVishwajith Upendra }; 1197dea4501bSVishwajith Upendra 1198dea4501bSVishwajith Upendra typedef struct wlan_dbg_sifs_resp_stats { 1199dea4501bSVishwajith Upendra A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */ 1200dea4501bSVishwajith Upendra A_UINT32 uapsd_trigger; /* num uapsd trigger frames */ 1201dea4501bSVishwajith Upendra A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */ 1202dea4501bSVishwajith Upendra A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */ 1203dea4501bSVishwajith Upendra A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */ 1204dea4501bSVishwajith Upendra A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */ 1205dea4501bSVishwajith Upendra } wlan_dgb_sifs_resp_stats_t; 1206dea4501bSVishwajith Upendra 120790c68bd3Sqcabuildsw 120890c68bd3Sqcabuildsw 1209dea4501bSVishwajith Upendra /** wlan_dbg_wifi2_error_stats_t is not grouped with the 1210dea4501bSVishwajith Upendra * following structure as it is allocated differently and only 1211dea4501bSVishwajith Upendra * belongs to whal 1212dea4501bSVishwajith Upendra */ 1213dea4501bSVishwajith Upendra typedef struct wlan_dbg_stats_wifi2 { 1214dea4501bSVishwajith Upendra wlan_dbg_txbf_snd_stats_t txbf_snd_info; 1215dea4501bSVishwajith Upendra wlan_dbg_txbf_data_stats_t txbf_data_info; 1216dea4501bSVishwajith Upendra struct wlan_dbg_tx_selfgen_stats tx_selfgen; 1217dea4501bSVishwajith Upendra struct wlan_dbg_tx_mu_stats tx_mu; 1218dea4501bSVishwajith Upendra wlan_dgb_sifs_resp_stats_t sifs_resp_info; 1219dea4501bSVishwajith Upendra } wlan_dbg_wifi2_stats_t; 1220dea4501bSVishwajith Upendra 1221da16b46eSspuligil /* 1222da16b46eSspuligil * wlan_dbg_rx_rate_info_v1a, _v1b: 1223da16b46eSspuligil * differing versions of the wlan_dbg_rx_rate_info struct used by different 1224da16b46eSspuligil * targets 1225da16b46eSspuligil */ 1226dea4501bSVishwajith Upendra typedef struct { 1227da16b46eSspuligil wlan_dbg_rx_rate_info_v1a_t rx_phy_info; 1228dea4501bSVishwajith Upendra wlan_dbg_tx_rate_info_t tx_rate_info; 1229da16b46eSspuligil } wlan_dbg_rate_info_v1a_t; 1230da16b46eSspuligil 1231da16b46eSspuligil typedef struct { 1232da16b46eSspuligil wlan_dbg_rx_rate_info_v1b_t rx_phy_info; 1233da16b46eSspuligil wlan_dbg_tx_rate_info_t tx_rate_info; 1234da16b46eSspuligil } wlan_dbg_rate_info_v1b_t; 1235da16b46eSspuligil 1236da16b46eSspuligil #if defined(AR900B) 1237da16b46eSspuligil #define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1b_t 1238da16b46eSspuligil #else 1239da16b46eSspuligil #define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1a_t 1240da16b46eSspuligil #endif 1241dea4501bSVishwajith Upendra 1242dea4501bSVishwajith Upendra typedef struct { 1243dea4501bSVishwajith Upendra wlan_dbg_rx_rate_info_v2_t rx_phy_info; 1244dea4501bSVishwajith Upendra wlan_dbg_tx_rate_info_v2_t tx_rate_info; 1245dea4501bSVishwajith Upendra } wlan_dbg_rate_info_v2_t; 1246dea4501bSVishwajith Upendra 1247da16b46eSspuligil /* 1248da16b46eSspuligil * wlan_dbg_stats_v1, _v2: 1249da16b46eSspuligil * differing versions of the wlan_dbg_stats struct used by different 1250da16b46eSspuligil * targets 1251da16b46eSspuligil */ 1252da16b46eSspuligil struct wlan_dbg_stats_v1 { 1253da16b46eSspuligil struct wlan_dbg_tx_stats_v1 tx; 1254da16b46eSspuligil struct wlan_dbg_rx_stats_v1 rx; 1255dea4501bSVishwajith Upendra struct wlan_dbg_peer_stats peer; 1256dea4501bSVishwajith Upendra }; 1257dea4501bSVishwajith Upendra 1258da16b46eSspuligil struct wlan_dbg_stats_v2 { 1259da16b46eSspuligil struct wlan_dbg_tx_stats_v2 tx; 1260da16b46eSspuligil struct wlan_dbg_rx_stats_v2 rx; 1261da16b46eSspuligil struct wlan_dbg_mem_stats mem; 1262da16b46eSspuligil struct wlan_dbg_peer_stats peer; 1263da16b46eSspuligil }; 1264da16b46eSspuligil 1265da16b46eSspuligil #if defined(AR900B) 1266da16b46eSspuligil #define wlan_dbg_stats wlan_dbg_stats_v2 1267da16b46eSspuligil #else 1268da16b46eSspuligil #define wlan_dbg_stats wlan_dbg_stats_v1 1269da16b46eSspuligil #endif 1270da16b46eSspuligil 1271dea4501bSVishwajith Upendra #define DBG_STATS_MAX_HWQ_NUM 10 1272dea4501bSVishwajith Upendra #define DBG_STATS_MAX_TID_NUM 20 1273dea4501bSVishwajith Upendra #define DBG_STATS_MAX_CONG_NUM 16 1274dea4501bSVishwajith Upendra struct wlan_dbg_txq_stats { 1275dea4501bSVishwajith Upendra A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM]; 1276dea4501bSVishwajith Upendra A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ 1277dea4501bSVishwajith Upendra A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ 1278dea4501bSVishwajith Upendra }; 1279dea4501bSVishwajith Upendra 1280dea4501bSVishwajith Upendra struct wlan_dbg_tidq_stats { 1281dea4501bSVishwajith Upendra A_UINT32 wlan_dbg_tid_txq_status; 1282dea4501bSVishwajith Upendra struct wlan_dbg_txq_stats txq_st; 1283dea4501bSVishwajith Upendra }; 12844b6e9b9eSsnandini 12854b6e9b9eSsnandini typedef enum { 12863e76aba9Sspuligil WLAN_DBG_DATA_STALL_NONE = 0, 1287cc6b10adSspuligil WLAN_DBG_DATA_STALL_VDEV_PAUSE = 1, 1288cc6b10adSspuligil WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER = 2, 1289cc6b10adSspuligil WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH = 3, 1290cc6b10adSspuligil WLAN_DBG_DATA_STALL_RX_REFILL_FAILED = 4, 1291cc6b10adSspuligil WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR = 5, 1292cc6b10adSspuligil WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS = 6, /* Mac watch dog */ 1293cc6b10adSspuligil WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR = 7, /* PHY watch dog */ 1294cc6b10adSspuligil WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR = 8, 1295cc6b10adSspuligil WLAN_DBG_DATA_STALL_CONSECUTIVE_NON_FLUSH = 9, 1296cc6b10adSspuligil WLAN_DBG_DATA_STALL_CONSECUTIVE_NOACK = 10, 1297cc6b10adSspuligil WLAN_DBG_DATA_STALL_CONSECUTIVE_LT_EXPIRY = 11, 12983e76aba9Sspuligil WLAN_DBG_DATA_STALL_MAX, 12994b6e9b9eSsnandini } wlan_dbg_data_stall_type_e; 13004b6e9b9eSsnandini 13014b6e9b9eSsnandini typedef enum { 13023e76aba9Sspuligil WLAN_DBG_DATA_STALL_RECOVERY_NONE = 0, 13033e76aba9Sspuligil WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_DISCONNECT, 13044b6e9b9eSsnandini WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_MAC_PHY_RESET, 13054b6e9b9eSsnandini WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_PDR, 13063e76aba9Sspuligil WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_SSR, 13074b6e9b9eSsnandini } wlan_dbg_data_stall_recovery_type_e; 1308dea4501bSVishwajith Upendra 13091ed83134Sspuligil /* 13101ed83134Sspuligil * NOTE: If necessary, restore the explicit disabling of CONFIG_160MHZ_SUPPORT 13111ed83134Sspuligil * See the corresponding comment + pre-processor block at the top of the file. 13121ed83134Sspuligil */ 13131ed83134Sspuligil #ifdef CONFIG_160MHZ_SUPPORT_UNDEF_WAR 13141ed83134Sspuligil #define CONFIG_160MHZ_SUPPORT 0 13151ed83134Sspuligil #undef CONFIG_160MHZ_SUPPORT_UNDEF_WAR 13161ed83134Sspuligil #endif 13171ed83134Sspuligil 1318119f03c3Sspuligil /** MGMT RX REO Changes */ 1319119f03c3Sspuligil /* Macros for having versioning info for compatibility check between host and firmware */ 1320028e554fSspuligil #define MLO_SHMEM_MAJOR_VERSION 2 1321119f03c3Sspuligil #define MLO_SHMEM_MINOR_VERSION 1 1322119f03c3Sspuligil 1323119f03c3Sspuligil /** Helper Macros for tlv header of the given tlv buffer */ 1324119f03c3Sspuligil /* Size of the TLV Header which is the Tag and Length fields */ 1325119f03c3Sspuligil #define MLO_SHMEM_TLV_HDR_SIZE (1 * sizeof(A_UINT32)) 1326119f03c3Sspuligil 1327119f03c3Sspuligil /* TLV Helper macro to get the TLV Header given the pointer to the TLV buffer. */ 1328119f03c3Sspuligil #define MLO_SHMEMTLV_GET_HDR(tlv_buf) (((A_UINT32 *) (tlv_buf))[0]) 1329119f03c3Sspuligil 1330119f03c3Sspuligil /* TLV Helper macro to set the TLV Header given the pointer to the TLV buffer. */ 1331119f03c3Sspuligil #define MLO_SHMEMTLV_SET_HDR(tlv_buf, tag, len) \ 1332119f03c3Sspuligil (((A_UINT32 *)(tlv_buf))[0]) = ((tag << 16) | (len & 0x0000FFFF)) 1333119f03c3Sspuligil 1334119f03c3Sspuligil /* TLV Helper macro to get the TLV Tag given the TLV header. */ 1335119f03c3Sspuligil #define MLO_SHMEMTLV_GET_TLVTAG(tlv_header) ((A_UINT32)((tlv_header) >> 16)) 1336119f03c3Sspuligil 1337119f03c3Sspuligil /* 1338119f03c3Sspuligil * TLV Helper macro to get the TLV Buffer Length (minus TLV header size) 1339119f03c3Sspuligil * given the TLV header. 1340119f03c3Sspuligil */ 1341119f03c3Sspuligil #define MLO_SHMEMTLV_GET_TLVLEN(tlv_header) \ 1342119f03c3Sspuligil ((A_UINT32)((tlv_header) & 0x0000FFFF)) 1343119f03c3Sspuligil 1344119f03c3Sspuligil /* 1345119f03c3Sspuligil * TLV Helper macro to get the TLV length from TLV structure size 1346119f03c3Sspuligil * by removing TLV header size. 1347119f03c3Sspuligil */ 1348119f03c3Sspuligil #define MLO_SHMEMTLV_GET_STRUCT_TLVLEN(tlv_struct) \ 1349119f03c3Sspuligil ((A_UINT32)(sizeof(tlv_struct)-MLO_SHMEM_TLV_HDR_SIZE)) 1350119f03c3Sspuligil 1351119f03c3Sspuligil /** 1352119f03c3Sspuligil * Helper Macros for getting and setting the required number of bits 1353119f03c3Sspuligil * from the TLV params. 1354119f03c3Sspuligil */ 1355119f03c3Sspuligil #define MLO_SHMEM_GET_BITS(_val,_index,_num_bits) \ 1356119f03c3Sspuligil (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) 1357119f03c3Sspuligil 1358119f03c3Sspuligil #define MLO_SHMEM_SET_BITS(_var,_index,_num_bits,_val) \ 1359119f03c3Sspuligil do { \ 1360119f03c3Sspuligil (_var) &= ~(((1 << (_num_bits)) - 1) << (_index)); \ 1361119f03c3Sspuligil (_var) |= (((_val) & ((1 << (_num_bits)) - 1)) << (_index)); \ 1362119f03c3Sspuligil } while (0) 1363119f03c3Sspuligil 1364028e554fSspuligil /** 1365028e554fSspuligil * Enum which defines different versions of management Rx reorder snapshots. 1366028e554fSspuligil */ 1367028e554fSspuligil typedef enum { 1368028e554fSspuligil /** 1369028e554fSspuligil * DWORD Lower: 1370028e554fSspuligil * [15:0] : Management packet counter 1371028e554fSspuligil * [30:16] : Redundant global time stamp = Global time stamp[14:0] 1372028e554fSspuligil * [31] : Valid 1373028e554fSspuligil * 1374028e554fSspuligil * DWORD Upper: 1375028e554fSspuligil * [31:0] : Global time stamp 1376028e554fSspuligil * 1377028e554fSspuligil */ 1378028e554fSspuligil MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY = 0, 1379028e554fSspuligil 1380028e554fSspuligil /** 1381028e554fSspuligil * DWORD Lower: 1382028e554fSspuligil * [14:0] : Global time stamp[14:0] 1383028e554fSspuligil * [30:15] : Management packet counter 1384028e554fSspuligil * [31] : Valid 1385028e554fSspuligil * 1386028e554fSspuligil * DWORD Upper: 1387028e554fSspuligil * [14:0] : Redundant management packet counter = Management packet 1388028e554fSspuligil * counter[14:0] 1389028e554fSspuligil * [31:15] : Global time stamp[31:15] 1390028e554fSspuligil */ 1391028e554fSspuligil MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY = 1, 1392028e554fSspuligil } MGMT_RX_REO_SNAPSHOT_VERSION; 1393028e554fSspuligil 1394119f03c3Sspuligil /** Definition of the GLB_H_SHMEM arena tlv structures */ 1395119f03c3Sspuligil 1396119f03c3Sspuligil typedef enum { 1397119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT, 1398119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO, 1399119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO, 1400119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK, 1401119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO, 1402119f03c3Sspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM, 1403ec350f9eSspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO, 1404ec350f9eSspuligil MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO, 1405119f03c3Sspuligil } MLO_SHMEM_TLV_TAG_ID; 1406119f03c3Sspuligil 1407119f03c3Sspuligil /** Helper macro for params GET/SET of mgmt_rx_reo_snapshot */ 1408119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 1) 1409119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 0, 1, value) 1410119f03c3Sspuligil 1411119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 1, 16) 1412119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 1, 16, value) 1413119f03c3Sspuligil 1414119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET(mgmt_rx_reo_snapshot) \ 1415119f03c3Sspuligil (MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17) << 15) | \ 1416119f03c3Sspuligil MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15) 1417119f03c3Sspuligil 1418119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_SET(mgmt_rx_reo_snapshot, value) \ 1419119f03c3Sspuligil do { \ 1420119f03c3Sspuligil MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17, ((value) >> 15)); \ 1421119f03c3Sspuligil MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15, ((value) & 0x7fff)); \ 1422119f03c3Sspuligil } while (0) 1423119f03c3Sspuligil 1424119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_GET(mgmt_rx_reo_snapshot_high) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 17, 15) 1425119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_SET(mgmt_rx_reo_snapshot_high, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_high, 17, 15, value) 1426119f03c3Sspuligil 1427119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_IS_CONSISTENT(mgmt_pkt_ctr, mgmt_pkt_ctr_redundant) \ 1428119f03c3Sspuligil (MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15)) 1429119f03c3Sspuligil 1430119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET_FROM_DWORDS(mgmt_rx_reo_snapshot_low,mgmt_rx_reo_snapshot_high) \ 1431119f03c3Sspuligil (MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_high), 0, 17) << 15) | \ 1432119f03c3Sspuligil MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_low), 17, 15) 1433119f03c3Sspuligil 1434119f03c3Sspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GET_ADRESS(mgmt_rx_reo_snapshot) \ 1435119f03c3Sspuligil (&mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low) 1436119f03c3Sspuligil 1437028e554fSspuligil /** 1438028e554fSspuligil * Helper macros/functions for params GET/SET of different hw version 1439028e554fSspuligil * of the mgmt_rx_reo_snapshot 1440028e554fSspuligil */ 1441028e554fSspuligil 1442028e554fSspuligil static INLINE A_UINT8 1443028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_GET( 1444028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_low, A_UINT8 snapshot_ver) 1445028e554fSspuligil { 1446028e554fSspuligil if ((snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) && 1447028e554fSspuligil (snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY)) 1448028e554fSspuligil { 1449028e554fSspuligil A_ASSERT(0); 1450028e554fSspuligil } 1451028e554fSspuligil 1452028e554fSspuligil return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 31, 1); 1453028e554fSspuligil } 1454028e554fSspuligil 1455028e554fSspuligil static INLINE void 1456028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_SET( 1457028e554fSspuligil A_UINT32 *mgmt_rx_reo_snapshot_low, A_UINT8 value, A_UINT8 snapshot_ver) 1458028e554fSspuligil { 1459028e554fSspuligil if ((snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) && 1460028e554fSspuligil (snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY)) { 1461028e554fSspuligil A_ASSERT(0); 1462028e554fSspuligil } 1463028e554fSspuligil 1464028e554fSspuligil MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 31, 1, value); 1465028e554fSspuligil } 1466028e554fSspuligil 1467028e554fSspuligil static INLINE A_UINT16 1468028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_GET( 1469028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_low, A_UINT8 snapshot_ver) 1470028e554fSspuligil { 1471028e554fSspuligil if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1472028e554fSspuligil return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 16); 1473028e554fSspuligil } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1474028e554fSspuligil return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 15, 16); 1475028e554fSspuligil } else { 1476028e554fSspuligil A_ASSERT(0); 1477028e554fSspuligil return 0; 1478028e554fSspuligil } 1479028e554fSspuligil } 1480028e554fSspuligil 1481028e554fSspuligil static INLINE void 1482028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_SET( 1483028e554fSspuligil A_UINT32 *mgmt_rx_reo_snapshot_low, A_UINT16 value, A_UINT8 snapshot_ver) 1484028e554fSspuligil { 1485028e554fSspuligil if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1486028e554fSspuligil MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 0, 16, value); 1487028e554fSspuligil } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1488028e554fSspuligil MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 15, 16, value); 1489028e554fSspuligil } else { 1490028e554fSspuligil A_ASSERT(0); 1491028e554fSspuligil } 1492028e554fSspuligil } 1493028e554fSspuligil 1494028e554fSspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( \ 1495028e554fSspuligil mgmt_rx_reo_snapshot_high) \ 1496028e554fSspuligil MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 0, 15) 1497028e554fSspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_SET( \ 1498028e554fSspuligil mgmt_rx_reo_snapshot_high, value) \ 1499028e554fSspuligil MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_high, 0, 15, value) 1500028e554fSspuligil 1501028e554fSspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( \ 1502028e554fSspuligil mgmt_rx_reo_snapshot_low) \ 1503028e554fSspuligil MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 16, 15) 1504028e554fSspuligil #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_SET( \ 1505028e554fSspuligil mgmt_rx_reo_snapshot_low, value) \ 1506028e554fSspuligil MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 16, 15, value) 1507028e554fSspuligil 1508028e554fSspuligil static INLINE A_UINT32 1509028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_GET( 1510028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_low, 1511028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_high, 1512028e554fSspuligil A_UINT8 snapshot_ver) 1513028e554fSspuligil { 1514028e554fSspuligil if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1515028e554fSspuligil return mgmt_rx_reo_snapshot_high; 1516028e554fSspuligil } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1517028e554fSspuligil return 1518028e554fSspuligil ((MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 15, 17) << 15) | 1519028e554fSspuligil MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 15)); 1520028e554fSspuligil } else { 1521028e554fSspuligil A_ASSERT(0); 1522028e554fSspuligil return 0; 1523028e554fSspuligil } 1524028e554fSspuligil } 1525028e554fSspuligil 1526028e554fSspuligil static INLINE void 1527028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_SET( 1528028e554fSspuligil A_UINT32 *mgmt_rx_reo_snapshot_low, 1529028e554fSspuligil A_UINT32 *mgmt_rx_reo_snapshot_high, 1530028e554fSspuligil A_UINT32 value, 1531028e554fSspuligil A_UINT8 snapshot_ver) 1532028e554fSspuligil { 1533028e554fSspuligil if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1534028e554fSspuligil *mgmt_rx_reo_snapshot_high = value; 1535028e554fSspuligil } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1536028e554fSspuligil MLO_SHMEM_SET_BITS( 1537028e554fSspuligil *mgmt_rx_reo_snapshot_high, 15, 17, ((value) >> 15)); 1538028e554fSspuligil MLO_SHMEM_SET_BITS( 1539028e554fSspuligil *mgmt_rx_reo_snapshot_low, 0, 15, ((value) & 0x7fff)); 1540028e554fSspuligil } else { 1541028e554fSspuligil A_ASSERT(0); 1542028e554fSspuligil } 1543028e554fSspuligil } 1544028e554fSspuligil 1545028e554fSspuligil static INLINE A_BOOL 1546028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_CHECK_CONSISTENCY( 1547028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_low, 1548028e554fSspuligil A_UINT32 mgmt_rx_reo_snapshot_high, 1549028e554fSspuligil A_UINT8 snapshot_ver) 1550028e554fSspuligil { 1551028e554fSspuligil if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1552028e554fSspuligil A_UINT32 global_timestamp; 1553028e554fSspuligil A_UINT32 global_timestamp_redundant; 1554028e554fSspuligil 1555028e554fSspuligil global_timestamp = MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_GET( 1556028e554fSspuligil mgmt_rx_reo_snapshot_low, mgmt_rx_reo_snapshot_high, snapshot_ver); 1557028e554fSspuligil global_timestamp_redundant = 1558028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( 1559028e554fSspuligil mgmt_rx_reo_snapshot_low); 1560028e554fSspuligil 1561028e554fSspuligil return 1562028e554fSspuligil (MLO_SHMEM_GET_BITS(global_timestamp, 0, 15) == 1563028e554fSspuligil MLO_SHMEM_GET_BITS(global_timestamp_redundant, 0, 15)); 1564028e554fSspuligil } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1565028e554fSspuligil A_UINT16 mgmt_pkt_ctr; 1566028e554fSspuligil A_UINT16 mgmt_pkt_ctr_redundant; 1567028e554fSspuligil 1568028e554fSspuligil mgmt_pkt_ctr = MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_GET( 1569028e554fSspuligil mgmt_rx_reo_snapshot_low, snapshot_ver); 1570028e554fSspuligil mgmt_pkt_ctr_redundant = 1571028e554fSspuligil MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( 1572028e554fSspuligil mgmt_rx_reo_snapshot_high); 1573028e554fSspuligil 1574028e554fSspuligil return 1575028e554fSspuligil (MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == 1576028e554fSspuligil MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15)); 1577028e554fSspuligil } else { 1578028e554fSspuligil A_ASSERT(0); 1579028e554fSspuligil return 0; 1580028e554fSspuligil } 1581028e554fSspuligil } 1582028e554fSspuligil 1583119f03c3Sspuligil /* REO snapshot structure */ 1584119f03c3Sspuligil typedef struct { 1585119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT */ 1586119f03c3Sspuligil A_UINT32 tlv_header; 1587119f03c3Sspuligil A_UINT32 reserved_alignment_padding; 1588119f03c3Sspuligil /** 1589119f03c3Sspuligil * mgmt_rx_reo_snapshot_low 1590119f03c3Sspuligil * 1591119f03c3Sspuligil * [0]: valid 1592119f03c3Sspuligil * [16:1]: mgmt_pkt_ctr 1593119f03c3Sspuligil * [31:17]: global_timestamp_low 1594119f03c3Sspuligil */ 1595119f03c3Sspuligil A_UINT32 mgmt_rx_reo_snapshot_low; 1596119f03c3Sspuligil 1597119f03c3Sspuligil /** 1598119f03c3Sspuligil * mgmt_rx_reo_snapshot_high 1599119f03c3Sspuligil * 1600119f03c3Sspuligil * [16:0]: global_timestamp_high 1601119f03c3Sspuligil * [31:17]: mgmt_pkt_ctr_redundant 1602119f03c3Sspuligil */ 1603119f03c3Sspuligil A_UINT32 mgmt_rx_reo_snapshot_high; 1604119f03c3Sspuligil 1605119f03c3Sspuligil } mgmt_rx_reo_snapshot; 1606119f03c3Sspuligil 1607119f03c3Sspuligil A_COMPILE_TIME_ASSERT(check_mgmt_rx_reo_snapshot_8byte_size_quantum, 1608119f03c3Sspuligil (((sizeof(mgmt_rx_reo_snapshot) % sizeof(A_UINT64) == 0x0)))); 1609119f03c3Sspuligil 1610119f03c3Sspuligil A_COMPILE_TIME_ASSERT(verify_mgmt_rx_reo_snapshot_low_offset, 1611c08ad387Sspuligil (A_OFFSETOF(mgmt_rx_reo_snapshot, mgmt_rx_reo_snapshot_low) % sizeof(A_UINT64) == 0)); 1612119f03c3Sspuligil 1613119f03c3Sspuligil typedef struct { 1614119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO */ 1615119f03c3Sspuligil A_UINT32 tlv_header; 1616119f03c3Sspuligil A_UINT32 reserved_alignment_padding; 1617119f03c3Sspuligil mgmt_rx_reo_snapshot fw_consumed; 1618119f03c3Sspuligil mgmt_rx_reo_snapshot fw_forwarded; 1619119f03c3Sspuligil mgmt_rx_reo_snapshot hw_forwarded; 1620119f03c3Sspuligil } mlo_glb_rx_reo_per_link_snapshot_info; 1621119f03c3Sspuligil 1622119f03c3Sspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_per_link_snapshot_info_8byte_size_quantum, 1623119f03c3Sspuligil (((sizeof(mlo_glb_rx_reo_per_link_snapshot_info) % sizeof(A_UINT64) == 0x0)))); 1624119f03c3Sspuligil 1625119f03c3Sspuligil A_COMPILE_TIME_ASSERT(verify_mlo_glb_rx_reo_per_link_snapshot_fw_consumed_offset, 1626c08ad387Sspuligil (A_OFFSETOF(mlo_glb_rx_reo_per_link_snapshot_info, fw_consumed) % sizeof(A_UINT64) == 0)); 1627119f03c3Sspuligil 1628119f03c3Sspuligil /** Helper macro for params GET/SET of mlo_glb_rx_reo_snapshot_info */ 1629119f03c3Sspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4) 1630119f03c3Sspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value) 1631119f03c3Sspuligil 1632119f03c3Sspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16) 1633119f03c3Sspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value) 1634119f03c3Sspuligil 1635028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 0, 3) 1636028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 0, 3, value) 1637028e554fSspuligil 1638028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 3, 3) 1639028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 3, 3, value) 1640028e554fSspuligil 1641028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 6, 3) 1642028e554fSspuligil #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 6, 3, value) 1643028e554fSspuligil 1644119f03c3Sspuligil /* Definition of the complete REO snapshot info */ 1645119f03c3Sspuligil typedef struct { 1646119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO */ 1647119f03c3Sspuligil A_UINT32 tlv_header; 1648119f03c3Sspuligil 1649119f03c3Sspuligil /** 1650119f03c3Sspuligil * link_info 1651119f03c3Sspuligil * 1652119f03c3Sspuligil * [3:0]: no_of_links 1653119f03c3Sspuligil * [19:4]: valid_link_bmap 1654119f03c3Sspuligil * [31:20]: reserved 1655119f03c3Sspuligil */ 1656119f03c3Sspuligil A_UINT32 link_info; 1657028e554fSspuligil 1658028e554fSspuligil /** 1659028e554fSspuligil * snapshot_ver_info 1660028e554fSspuligil * 1661028e554fSspuligil * [2:0]: hw_forwarded snapshot version 1662028e554fSspuligil * [5:3]: fw_forwarded snapshot version 1663028e554fSspuligil * [8:6]: fw_consumed snapshot version 1664028e554fSspuligil * [31:9]: reserved 1665028e554fSspuligil */ 1666028e554fSspuligil A_UINT32 snapshot_ver_info; 1667028e554fSspuligil A_UINT32 reserved_alignment_padding; 1668028e554fSspuligil 1669119f03c3Sspuligil /* This TLV is followed by array of mlo_glb_rx_reo_per_link_snapshot_info: 1670119f03c3Sspuligil * mlo_glb_rx_reo_per_link_snapshot_info will have multiple instances 1671119f03c3Sspuligil * equal to num of hw links received by no_of_link 1672119f03c3Sspuligil * mlo_glb_rx_reo_per_link_snapshot_info per_link_info[]; 1673119f03c3Sspuligil */ 1674119f03c3Sspuligil } mlo_glb_rx_reo_snapshot_info; 1675119f03c3Sspuligil 1676119f03c3Sspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_snapshot_info_8byte_size_quantum, 1677119f03c3Sspuligil (((sizeof(mlo_glb_rx_reo_snapshot_info) % sizeof(A_UINT64) == 0x0)))); 1678119f03c3Sspuligil 1679119f03c3Sspuligil /** Helper macro for params GET/SET of mlo_glb_link */ 1680119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_GET(link_status) MLO_SHMEM_GET_BITS(link_status, 0, 8) 1681119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_SET(link_status, value) MLO_SHMEM_SET_BITS(link_status, 0, 8, value) 1682119f03c3Sspuligil 1683119f03c3Sspuligil /*glb link info structures used for scratchpad memory (crash and recovery) */ 1684119f03c3Sspuligil typedef struct { 1685119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK */ 1686119f03c3Sspuligil A_UINT32 tlv_header; 1687119f03c3Sspuligil /** 1688119f03c3Sspuligil * link_status 1689119f03c3Sspuligil * 1690119f03c3Sspuligil * [7:0]: link_status 1691119f03c3Sspuligil * [31:8]: reserved 1692119f03c3Sspuligil */ 1693119f03c3Sspuligil A_UINT32 link_status; 1694119f03c3Sspuligil /* 1695119f03c3Sspuligil * Based on MLO timestamp, which is global across chips - 1696119f03c3Sspuligil * this will be first updated when MLO sync is completed. 1697119f03c3Sspuligil */ 1698119f03c3Sspuligil A_UINT32 boot_timestamp_low_us; 1699119f03c3Sspuligil A_UINT32 boot_timestamp_high_us; 1700119f03c3Sspuligil /* 1701119f03c3Sspuligil * Based on MLO timestamp, will be updated with a configurable 1702119f03c3Sspuligil * periodicity (default 1 sec) 1703119f03c3Sspuligil */ 1704119f03c3Sspuligil A_UINT32 health_check_timestamp_low_us; 1705119f03c3Sspuligil A_UINT32 health_check_timestamp_high_us; 1706119f03c3Sspuligil 1707119f03c3Sspuligil } mlo_glb_link; 1708119f03c3Sspuligil 1709119f03c3Sspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_link_8byte_size_quantum, 1710119f03c3Sspuligil (((sizeof(mlo_glb_link) % sizeof(A_UINT64) == 0x0)))); 1711119f03c3Sspuligil 1712119f03c3Sspuligil A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_boot_timestamp_low_offset, 1713c08ad387Sspuligil (A_OFFSETOF(mlo_glb_link, boot_timestamp_low_us) % sizeof(A_UINT64) == 0)); 1714119f03c3Sspuligil 1715119f03c3Sspuligil A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_health_check_timestamp_low_offset, 1716c08ad387Sspuligil (A_OFFSETOF(mlo_glb_link, health_check_timestamp_low_us) % sizeof(A_UINT64) == 0)); 1717119f03c3Sspuligil 1718119f03c3Sspuligil 1719119f03c3Sspuligil /** Helper macro for params GET/SET of mlo_glb_link_info */ 1720119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4) 1721119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value) 1722119f03c3Sspuligil 1723119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16) 1724119f03c3Sspuligil #define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value) 1725119f03c3Sspuligil 1726119f03c3Sspuligil typedef struct { 1727119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO */ 1728119f03c3Sspuligil A_UINT32 tlv_header; 1729119f03c3Sspuligil 1730119f03c3Sspuligil /** 1731119f03c3Sspuligil * link_info 1732119f03c3Sspuligil * 1733119f03c3Sspuligil * [3:0]: no_of_links 1734119f03c3Sspuligil * [19:4]: valid_link_bmap 1735119f03c3Sspuligil * [31:20]: reserved 1736119f03c3Sspuligil */ 1737119f03c3Sspuligil A_UINT32 link_info; 1738119f03c3Sspuligil /* This TLV is followed by array of mlo_glb_link: 17399af1257eSspuligil * mlo_glb_link will have multiple instances equal to num of hw links 1740119f03c3Sspuligil * received by no_of_link 1741119f03c3Sspuligil * mlo_glb_link glb_link_info[]; 1742119f03c3Sspuligil */ 1743119f03c3Sspuligil } mlo_glb_link_info; 1744119f03c3Sspuligil 1745c08ad387Sspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum, 1746119f03c3Sspuligil (((sizeof(mlo_glb_link_info) % sizeof(A_UINT64) == 0x0)))); 1747119f03c3Sspuligil 1748ec350f9eSspuligil typedef enum { 1749ec350f9eSspuligil MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, 1750ad526ef0Sspuligil MLO_SHMEM_CRASH_SW_PANIC = 2, 1751ad526ef0Sspuligil MLO_SHMEM_CRASH_SW_ASSERT = 3, 1752ec350f9eSspuligil } MLO_SHMEM_CHIP_CRASH_REASON; 1753ec350f9eSspuligil 1754ad526ef0Sspuligil typedef enum { 1755ad526ef0Sspuligil MLO_SHMEM_RECOVERY_CRASH_PARTNER_CHIPS = 1, 1756ad526ef0Sspuligil MLO_SHMEM_RECOVER_NON_MLO_MODE = 2, 1757*a07d3dfcSspuligil MLO_SHMEM_RECOVER_NON_CRASH_MLO_MODE = 3, 1758ad526ef0Sspuligil } MLO_SHMEM_CHIP_RECOVERY_MODE; 1759ad526ef0Sspuligil 1760ec350f9eSspuligil /* glb link info structures used for scratchpad memory (crash and recovery) */ 1761ec350f9eSspuligil typedef struct { 1762ec350f9eSspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ 1763ec350f9eSspuligil A_UINT32 tlv_header; 1764ec350f9eSspuligil /** 1765ec350f9eSspuligil * crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON 1766ec350f9eSspuligil */ 1767ec350f9eSspuligil A_UINT32 crash_reason; 1768ad526ef0Sspuligil /** 1769ad526ef0Sspuligil * crash reason, takes value in enum MLO_SHMEM_CHIP_RECOVERY_MODE 1770ad526ef0Sspuligil */ 1771ad526ef0Sspuligil A_UINT32 recovery_mode; 1772ad526ef0Sspuligil /* reserved: added for padding to A_UINT64 size, available for future use */ 1773ad526ef0Sspuligil A_UINT32 reserved; 1774ec350f9eSspuligil } mlo_glb_per_chip_crash_info; 1775ec350f9eSspuligil 1776ec350f9eSspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, 1777ec350f9eSspuligil (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); 1778ec350f9eSspuligil 1779ec350f9eSspuligil /** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ 17804d7a7383Sspuligil #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ 17814d7a7383Sspuligil (MLO_SHMEM_GET_BITS(chip_info, 0, 2) + \ 17824d7a7383Sspuligil (MLO_SHMEM_GET_BITS(chip_info, 12, 4) << 2)) 17834d7a7383Sspuligil #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) \ 17844d7a7383Sspuligil do { \ 17854d7a7383Sspuligil MLO_SHMEM_SET_BITS(chip_info, 0, 2, ((value) & 0x03)); \ 17864d7a7383Sspuligil MLO_SHMEM_SET_BITS(chip_info, 12, 4, ((value) >> 2)); \ 17874d7a7383Sspuligil } while (0) 1788ec350f9eSspuligil 17894d7a7383Sspuligil #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 8) 17904d7a7383Sspuligil #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 8, value) 1791ec350f9eSspuligil 1792ec350f9eSspuligil typedef struct { 1793ec350f9eSspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ 1794ec350f9eSspuligil A_UINT32 tlv_header; 1795ec350f9eSspuligil 1796ec350f9eSspuligil /** 1797ec350f9eSspuligil * chip_info 1798ec350f9eSspuligil * 1799ec350f9eSspuligil * [1:0]: no_of_chips 1800ec350f9eSspuligil * [4:2]: valid_chip_bmap 18014d7a7383Sspuligil * For number of chips beyond 3, extension fields are added. 18024d7a7383Sspuligil * To maintain backward compatibility, with 3 chip board and 18034d7a7383Sspuligil * old host driver, valid chip bmap is extended in continuation from 18044d7a7383Sspuligil * existing bit 4 onwards, while extending no_of_chips information 18054d7a7383Sspuligil * would overlap with old valid_chip_bmap, hence extended from 18064d7a7383Sspuligil * bit 12:15. Now no_of_chip will have two parts, lower 2 bits from 0-1 and 18074d7a7383Sspuligil * upper 4 bits from 12-15. SET-GET macros are modified accordingly. 18084d7a7383Sspuligil * This helps in no change in respective processing files and don't need 18094d7a7383Sspuligil * to maintain two copy of information for backward compatibility. 18104d7a7383Sspuligil * [9:5]: valid_chip_bmap_ext 18114d7a7383Sspuligil * [15:12]: no_of_chips_ext 18124d7a7383Sspuligil * [31:16]: reserved 1813ec350f9eSspuligil */ 1814ec350f9eSspuligil A_UINT32 chip_info; 1815ec350f9eSspuligil /* This TLV is followed by array of mlo_glb_per_chip_crash_info: 18169af1257eSspuligil * mlo_glb_per_chip_crash_info will have multiple instances equal to num of partner chips 1817ec350f9eSspuligil * received by no_of_chips 1818ec350f9eSspuligil * mlo_glb_per_chip_crash_info per_chip_crash_info[]; 1819ec350f9eSspuligil */ 1820ec350f9eSspuligil } mlo_glb_chip_crash_info; 1821ec350f9eSspuligil 1822ec350f9eSspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_chip_crash_info, 1823ec350f9eSspuligil (((sizeof(mlo_glb_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); 1824ec350f9eSspuligil 1825119f03c3Sspuligil /** Helper macro for params GET/SET of mlo_glb_h_shmem */ 1826119f03c3Sspuligil #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 0, 16) 1827119f03c3Sspuligil #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 0, 16, value) 1828119f03c3Sspuligil 1829119f03c3Sspuligil #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 16, 16) 1830119f03c3Sspuligil #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 16, 16, value) 1831119f03c3Sspuligil 1832119f03c3Sspuligil /* Definition of Global H SHMEM Arena */ 1833119f03c3Sspuligil typedef struct { 1834119f03c3Sspuligil /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM */ 1835119f03c3Sspuligil A_UINT32 tlv_header; 1836119f03c3Sspuligil /** 1837119f03c3Sspuligil * major_minor_version 1838119f03c3Sspuligil * 1839119f03c3Sspuligil * [15:0]: minor version 1840119f03c3Sspuligil * [31:16]: major version 1841119f03c3Sspuligil */ 1842119f03c3Sspuligil A_UINT32 major_minor_version; 1843119f03c3Sspuligil /* This TLV is followed by TLVs 1844119f03c3Sspuligil * mlo_glb_rx_reo_snapshot_info reo_snapshot; 1845119f03c3Sspuligil * mlo_glb_link_info glb_info; 1846ec350f9eSspuligil * mlo_glb_chip_crash_info crash_info; 1847119f03c3Sspuligil */ 1848119f03c3Sspuligil } mlo_glb_h_shmem; 1849119f03c3Sspuligil 1850119f03c3Sspuligil A_COMPILE_TIME_ASSERT(check_mlo_glb_h_shmem_8byte_size_quantum, 1851119f03c3Sspuligil (((sizeof(mlo_glb_h_shmem) % sizeof(A_UINT64) == 0x0)))); 1852119f03c3Sspuligil 1853a80a6124Sspuligil /** 2 word representation of MAC addr */ 1854a80a6124Sspuligil typedef struct _wmi_mac_addr { 1855a80a6124Sspuligil /** upper 4 bytes of MAC address */ 1856a80a6124Sspuligil A_UINT32 mac_addr31to0; 1857a80a6124Sspuligil /** lower 2 bytes of MAC address */ 1858a80a6124Sspuligil A_UINT32 mac_addr47to32; 1859a80a6124Sspuligil } wmi_mac_addr; 1860119f03c3Sspuligil 1861dea4501bSVishwajith Upendra #endif /* __WLANDEFS_H__ */ 1862