1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * @file htt_stats.h 22 * 23 * @details the public header file of HTT STATS 24 */ 25 #ifndef __HTT_STATS_H__ 26 #define __HTT_STATS_H__ 27 28 #include <htt_deps.h> /* A_UINT32 */ 29 #include <htt_common.h> 30 #include <htt.h> /* HTT stats TLV struct def and tag defs */ 31 32 /** 33 * htt_dbg_ext_stats_type - 34 * The base structure for each of the stats_type is only for reference 35 * Host should use this information to know the type of TLVs to expect 36 * for a particular stats type. 37 * 38 * Max supported stats :- 256. 39 */ 40 enum htt_dbg_ext_stats_type { 41 /** HTT_DBG_EXT_STATS_RESET 42 * PARAM: 43 * - config_param0 : start_offset (stats type) 44 * - config_param1 : stats bmask from start offset 45 * - config_param2 : stats bmask from start offset + 32 46 * - config_param3 : stats bmask from start offset + 64 47 * RESP MSG: 48 * - No response sent. 49 */ 50 HTT_DBG_EXT_STATS_RESET = 0, 51 52 /** HTT_DBG_EXT_STATS_PDEV_TX 53 * PARAMS: 54 * - No Params 55 * RESP MSG: 56 * - htt_tx_pdev_stats_t 57 */ 58 HTT_DBG_EXT_STATS_PDEV_TX = 1, 59 60 /** HTT_DBG_EXT_STATS_PDEV_RX 61 * PARAMS: 62 * - No Params 63 * RESP MSG: 64 * - htt_rx_pdev_stats_t 65 */ 66 HTT_DBG_EXT_STATS_PDEV_RX = 2, 67 68 /** HTT_DBG_EXT_STATS_PDEV_TX_HWQ 69 * PARAMS: 70 * - config_param0: [Bit31: Bit0] HWQ mask 71 * RESP MSG: 72 * - htt_tx_hwq_stats_t 73 */ 74 HTT_DBG_EXT_STATS_PDEV_TX_HWQ = 3, 75 76 /** HTT_DBG_EXT_STATS_PDEV_TX_SCHED 77 * PARAMS: 78 * - config_param0: [Bit31: Bit0] TXQ mask 79 * RESP MSG: 80 * - htt_stats_tx_sched_t 81 */ 82 HTT_DBG_EXT_STATS_PDEV_TX_SCHED = 4, 83 84 /** HTT_DBG_EXT_STATS_PDEV_ERROR 85 * PARAMS: 86 * - No Params 87 * RESP MSG: 88 * - htt_hw_err_stats_t 89 */ 90 HTT_DBG_EXT_STATS_PDEV_ERROR = 5, 91 92 /** HTT_DBG_EXT_STATS_PDEV_TQM 93 * PARAMS: 94 * - No Params 95 * RESP MSG: 96 * - htt_tx_tqm_pdev_stats_t 97 */ 98 HTT_DBG_EXT_STATS_PDEV_TQM = 6, 99 100 /** HTT_DBG_EXT_STATS_TQM_CMDQ 101 * PARAMS: 102 * - config_param0: 103 * [Bit15: Bit0 ] cmdq id :if 0xFFFF print all cmdq's 104 * [Bit31: Bit16] reserved 105 * RESP MSG: 106 * - htt_tx_tqm_cmdq_stats_t 107 */ 108 HTT_DBG_EXT_STATS_TQM_CMDQ = 7, 109 110 /** HTT_DBG_EXT_STATS_TX_DE_INFO 111 * PARAMS: 112 * - No Params 113 * RESP MSG: 114 * - htt_tx_de_stats_t 115 */ 116 HTT_DBG_EXT_STATS_TX_DE_INFO = 8, 117 118 /** HTT_DBG_EXT_STATS_PDEV_TX_RATE 119 * PARAMS: 120 * - No Params 121 * RESP MSG: 122 * - htt_tx_pdev_rate_stats_t 123 */ 124 HTT_DBG_EXT_STATS_PDEV_TX_RATE = 9, 125 126 /** HTT_DBG_EXT_STATS_PDEV_RX_RATE 127 * PARAMS: 128 * - No Params 129 * RESP MSG: 130 * - htt_rx_pdev_rate_stats_t 131 */ 132 HTT_DBG_EXT_STATS_PDEV_RX_RATE = 10, 133 134 /** HTT_DBG_EXT_STATS_PEER_INFO 135 * PARAMS: 136 * - config_param0: 137 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 138 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 139 * [Bit31 : Bit16] sw_peer_id 140 * config_param1: 141 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 142 * 0 bit htt_peer_stats_cmn_tlv 143 * 1 bit htt_peer_details_tlv 144 * 2 bit htt_tx_peer_rate_stats_tlv 145 * 3 bit htt_rx_peer_rate_stats_tlv 146 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 147 * 5 bit htt_rx_tid_stats_tlv 148 * 6 bit htt_msdu_flow_stats_tlv 149 * 7 bit htt_peer_sched_stats_tlv 150 * 8 bit htt_peer_ax_ofdma_stats_tlv 151 * 9 bit htt_peer_be_ofdma_stats_tlv 152 * - config_param2: [Bit31 : Bit0] mac_addr31to0 153 * - config_param3: [Bit15 : Bit0] mac_addr47to32 154 * [Bit 16] If this bit is set, reset per peer stats 155 * of corresponding tlv indicated by config 156 * param 1. 157 * HTT_DBG_EXT_PEER_STATS_RESET_GET will be 158 * used to get this bit position. 159 * WMI_SERVICE_PER_PEER_HTT_STATS_RESET 160 * indicates that FW supports per peer HTT 161 * stats reset. 162 * [Bit31 : Bit17] reserved 163 * RESP MSG: 164 * - htt_peer_stats_t 165 */ 166 HTT_DBG_EXT_STATS_PEER_INFO = 11, 167 168 /** HTT_DBG_EXT_STATS_TX_SELFGEN_INFO 169 * PARAMS: 170 * - No Params 171 * RESP MSG: 172 * - htt_tx_pdev_selfgen_stats_t 173 */ 174 HTT_DBG_EXT_STATS_TX_SELFGEN_INFO = 12, 175 176 /** HTT_DBG_EXT_STATS_TX_MU_HWQ 177 * PARAMS: 178 * - config_param0: [Bit31: Bit0] HWQ mask 179 * RESP MSG: 180 * - htt_tx_hwq_mu_mimo_stats_t 181 */ 182 HTT_DBG_EXT_STATS_TX_MU_HWQ = 13, 183 184 /** HTT_DBG_EXT_STATS_RING_IF_INFO 185 * PARAMS: 186 * - config_param0: 187 * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings 188 * [Bit31: Bit16] reserved 189 * RESP MSG: 190 * - htt_ring_if_stats_t 191 */ 192 HTT_DBG_EXT_STATS_RING_IF_INFO = 14, 193 194 /** HTT_DBG_EXT_STATS_SRNG_INFO 195 * PARAMS: 196 * - config_param0: 197 * [Bit15: Bit0 ] ring id :if 0xFFFF print all rings 198 * [Bit31: Bit16] reserved 199 * - No Params 200 * RESP MSG: 201 * - htt_sring_stats_t 202 */ 203 HTT_DBG_EXT_STATS_SRNG_INFO = 15, 204 205 /** HTT_DBG_EXT_STATS_SFM_INFO 206 * PARAMS: 207 * - No Params 208 * RESP MSG: 209 * - htt_sfm_stats_t 210 */ 211 HTT_DBG_EXT_STATS_SFM_INFO = 16, 212 213 /** HTT_DBG_EXT_STATS_PDEV_TX_MU 214 * PARAMS: 215 * - No Params 216 * RESP MSG: 217 * - htt_tx_pdev_mu_mimo_stats_t 218 */ 219 HTT_DBG_EXT_STATS_PDEV_TX_MU = 17, 220 221 /** HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST 222 * PARAMS: 223 * - config_param0: 224 * [Bit7 : Bit0] vdev_id:8 225 * note:0xFF to get all active peers based on pdev_mask. 226 * [Bit31 : Bit8] rsvd:24 227 * RESP MSG: 228 * - htt_active_peer_details_list_t 229 */ 230 HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST = 18, 231 232 /** HTT_DBG_EXT_STATS_PDEV_CCA_STATS 233 * PARAMS: 234 * - config_param0: 235 * [Bit0] - Clear bit0 to read 1sec,100ms & cumulative CCA stats. 236 * Set bit0 to 1 to read 1sec interval histogram. 237 * [Bit1] - 100ms interval histogram 238 * [Bit3] - Cumulative CCA stats 239 * RESP MSG: 240 * - htt_pdev_cca_stats_t 241 */ 242 HTT_DBG_EXT_STATS_PDEV_CCA_STATS = 19, 243 244 /** HTT_DBG_EXT_STATS_TWT_SESSIONS 245 * PARAMS: 246 * - config_param0: 247 * No params 248 * RESP MSG: 249 * - htt_pdev_twt_sessions_stats_t 250 */ 251 HTT_DBG_EXT_STATS_TWT_SESSIONS = 20, 252 253 /** HTT_DBG_EXT_STATS_REO_CNTS 254 * PARAMS: 255 * - config_param0: 256 * No params 257 * RESP MSG: 258 * - htt_soc_reo_resource_stats_t 259 */ 260 HTT_DBG_EXT_STATS_REO_RESOURCE_STATS = 21, 261 262 /** HTT_DBG_EXT_STATS_TX_SOUNDING_INFO 263 * PARAMS: 264 * - config_param0: 265 * [Bit0] vdev_id_set:1 266 * set to 1 if vdev_id is set and vdev stats are requested. 267 * set to 0 if pdev_stats sounding stats are requested. 268 * [Bit8 : Bit1] vdev_id:8 269 * note:0xFF to get all active vdevs based on pdev_mask. 270 * [Bit31 : Bit9] rsvd:22 271 * 272 * RESP MSG: 273 * - htt_tx_sounding_stats_t 274 */ 275 HTT_DBG_EXT_STATS_TX_SOUNDING_INFO = 22, 276 277 /** HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS 278 * PARAMS: 279 * - config_param0: 280 * No params 281 * RESP MSG: 282 * - htt_pdev_obss_pd_stats_t 283 */ 284 HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 285 286 /** HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS 287 * PARAMS: 288 * - config_param0: 289 * No params 290 * RESP MSG: 291 * - htt_stats_ring_backpressure_stats_t 292 */ 293 HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS = 24, 294 295 /** HTT_DBG_EXT_STATS_LATENCY_PROF_STATS 296 * PARAMS: 297 * 298 * RESP MSG: 299 * - htt_soc_latency_prof_t 300 */ 301 HTT_DBG_EXT_STATS_LATENCY_PROF_STATS = 25, 302 303 /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER 304 * PARAMS: 305 * - No Params 306 * RESP MSG: 307 * - htt_rx_pdev_ul_trig_stats_t 308 */ 309 HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS = 26, 310 311 /** HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27 312 * PARAMS: 313 * - No Params 314 * RESP MSG: 315 * - htt_rx_pdev_ul_mumimo_trig_stats_t 316 */ 317 HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, 318 319 /** HTT_DBG_EXT_STATS_FSE_RX 320 * PARAMS: 321 * - No Params 322 * RESP MSG: 323 * - htt_rx_fse_stats_t 324 */ 325 HTT_DBG_EXT_STATS_FSE_RX = 28, 326 327 /** HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS 328 * PARAMS: 329 * - config_param0: [Bit0] : [1] for mac_addr based request 330 * - config_param1: [Bit31 : Bit0] mac_addr31to0 331 * - config_param2: [Bit15 : Bit0] mac_addr47to32 332 * RESP MSG: 333 * - htt_ctrl_path_txrx_stats_t 334 */ 335 HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS = 29, 336 337 /** HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT 338 * PARAMS: 339 * - No Params 340 * RESP MSG: 341 * - htt_rx_pdev_rate_ext_stats_t 342 */ 343 HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT = 30, 344 345 /** HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF 346 * PARAMS: 347 * - No Params 348 * RESP MSG: 349 * - htt_tx_pdev_txbf_rate_stats_t 350 */ 351 HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 352 353 /** HTT_DBG_EXT_STATS_TXBF_OFDMA 354 */ 355 HTT_DBG_EXT_STATS_TXBF_OFDMA = 32, 356 357 /** HTT_DBG_EXT_STA_11AX_UL_STATS 358 * PARAMS: 359 * - No Params 360 * RESP MSG: 361 * - htt_sta_11ax_ul_stats 362 */ 363 HTT_DBG_EXT_STA_11AX_UL_STATS = 33, 364 365 /** HTT_DBG_EXT_VDEV_RTT_RESP_STATS 366 * PARAMS: 367 * - config_param0: 368 * [Bit7 : Bit0] vdev_id:8 369 * [Bit31 : Bit8] rsvd:24 370 * RESP MSG: 371 * - 372 */ 373 HTT_DBG_EXT_VDEV_RTT_RESP_STATS = 34, 374 375 /** HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS 376 * PARAMS: 377 * - No Params 378 * RESP MSG: 379 * - htt_pktlog_and_htt_ring_stats_t 380 */ 381 HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS = 35, 382 383 /** HTT_DBG_EXT_STATS_DLPAGER_STATS 384 * PARAMS: 385 * 386 * RESP MSG: 387 * - htt_dlpager_stats_t 388 */ 389 HTT_DBG_EXT_STATS_DLPAGER_STATS = 36, 390 391 /** HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS 392 * PARAMS: 393 * - No Params 394 * RESP MSG: 395 * - htt_phy_counters_and_phy_stats_t 396 */ 397 HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 398 399 /** HTT_DBG_EXT_VDEVS_TXRX_STATS 400 * PARAMS: 401 * - No Params 402 * RESP MSG: 403 * - htt_vdevs_txrx_stats_t 404 */ 405 HTT_DBG_EXT_VDEVS_TXRX_STATS = 38, 406 407 HTT_DBG_EXT_VDEV_RTT_INITIATOR_STATS = 39, 408 409 /** HTT_DBG_EXT_PDEV_PER_STATS 410 * PARAMS: 411 * - No Params 412 * RESP MSG: 413 * - htt_tx_pdev_per_stats_t 414 */ 415 HTT_DBG_EXT_PDEV_PER_STATS = 40, 416 417 HTT_DBG_EXT_AST_ENTRIES = 41, 418 419 /** HTT_DBG_EXT_RX_RING_STATS 420 * PARAMS: 421 * - No Params 422 * RESP MSG: 423 * - htt_rx_fw_ring_stats_tlv_v 424 */ 425 HTT_DBG_EXT_RX_RING_STATS = 42, 426 427 /** HTT_STRM_GEN_MPDUS_STATS, HTT_STRM_GEN_MPDUS_DETAILS_STATS 428 * PARAMS: 429 * - No params 430 * RESP MSG: HTT_T2H STREAMING_STATS_IND (not EXT_STATS_CONF) 431 * - HTT_STRM_GEN_MPDUS_STATS: 432 * htt_stats_strm_gen_mpdus_tlv_t 433 * - HTT_STRM_GEN_MPDUS_DETAILS_STATS: 434 * htt_stats_strm_gen_mpdus_details_tlv_t 435 */ 436 HTT_STRM_GEN_MPDUS_STATS = 43, 437 HTT_STRM_GEN_MPDUS_DETAILS_STATS = 44, 438 439 /** HTT_DBG_SOC_ERROR_STATS 440 * PARAMS: 441 * - No Params 442 * RESP MSG: 443 * - htt_dmac_reset_stats_tlv 444 */ 445 HTT_DBG_SOC_ERROR_STATS = 45, 446 447 /** HTT_DBG_PDEV_PUNCTURE_STATS 448 * PARAMS: 449 * - param 0: enum from htt_tx_pdev_puncture_stats_upload_t, indicating 450 * the stats to upload 451 * RESP MSG: 452 * - one or more htt_pdev_puncture_stats_tlv, depending on param 0 453 */ 454 HTT_DBG_PDEV_PUNCTURE_STATS = 46, 455 456 /** HTT_DBG_EXT_STATS_ML_PEERS_INFO 457 * PARAMS: 458 * - param 0: 459 * Bit 0 -> HTT_ML_PEER_DETAILS_TLV always enabled by default 460 * Bit 1 -> HTT_ML_PEER_EXT_DETAILS_TLV will be uploaded when 461 * this bit is set 462 * Bit 2 -> HTT_ML_LINK_INFO_TLV will be uploaded when this bit is set 463 * RESP MSG: 464 * - htt_ml_peer_stats_t 465 */ 466 HTT_DBG_EXT_STATS_ML_PEERS_INFO = 47, 467 468 /** HTT_DBG_ODD_MANDATORY_STATS 469 * params: 470 * None 471 * Response MSG: 472 * htt_odd_mandatory_pdev_stats_tlv 473 */ 474 HTT_DBG_ODD_MANDATORY_STATS = 48, 475 476 /** HTT_DBG_PDEV_SCHED_ALGO_STATS 477 * PARAMS: 478 * - No Params 479 * RESP MSG: 480 * - htt_pdev_sched_algo_ofdma_stats_tlv 481 */ 482 HTT_DBG_PDEV_SCHED_ALGO_STATS = 49, 483 484 /** HTT_DBG_ODD_MANDATORY_MUMIMO_STATS 485 * params: 486 * None 487 * Response MSG: 488 * htt_odd_mandatory_mumimo_pdev_stats_tlv 489 */ 490 HTT_DBG_ODD_MANDATORY_MUMIMO_STATS = 50, 491 /** HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS 492 * params: 493 * None 494 * Response MSG: 495 * htt_odd_mandatory_muofdma_pdev_stats_tlv 496 */ 497 HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS = 51, 498 499 /** HTT_DBG_EXT_PHY_PROF_CAL_STATS 500 * params: 501 * None 502 * Response MSG: 503 * htt_stats_latency_prof_cal_data_tlv 504 */ 505 HTT_DBG_EXT_PHY_PROF_CAL_STATS = 52, 506 507 /** HTT_DBG_EXT_STATS_PDEV_BW_MGR 508 * PARAMS: 509 * - No Params 510 * RESP MSG: 511 * - htt_pdev_bw_mgr_stats_t 512 */ 513 HTT_DBG_EXT_STATS_PDEV_BW_MGR = 53, 514 515 /** HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS 516 * PARAMS: 517 * - No Params 518 * RESP MSG: 519 * - htt_pdev_mbssid_ctrl_frame_stats 520 */ 521 HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, 522 523 /** HTT_DBG_SOC_SSR_STATS 524 * Used for non-MLO UMAC recovery stats. 525 * PARAMS: 526 * - No Params 527 * RESP MSG: 528 * - htt_umac_ssr_stats_tlv 529 */ 530 HTT_DBG_SOC_SSR_STATS = 55, 531 532 /** HTT_DBG_MLO_UMAC_SSR_STATS 533 * Used for MLO UMAC recovery stats. 534 * PARAMS: 535 * - No Params 536 * RESP MSG: 537 * - htt_mlo_umac_ssr_stats_tlv 538 */ 539 HTT_DBG_MLO_UMAC_SSR_STATS = 56, 540 541 /** HTT_DBG_PDEV_TDMA_STATS 542 * PARAMS: 543 * - No Params 544 * RESP MSG: 545 * - htt_pdev_tdma_stats_tlv 546 */ 547 HTT_DBG_PDEV_TDMA_STATS = 57, 548 549 /** HTT_DBG_CODEL_STATS 550 * PARAMS: 551 * - No Params 552 * RESP MSG: 553 * - htt_codel_svc_class_stats_tlv 554 * - htt_codel_msduq_stats_tlv 555 */ 556 HTT_DBG_CODEL_STATS = 58, 557 558 /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS 559 * PARAMS: 560 * - No Params 561 * RESP MSG: 562 * - htt_tx_pdev_mpdu_stats_tlv 563 */ 564 HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59, 565 566 /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER 567 * PARAMS: 568 * - No Params 569 * RESP MSG: 570 * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv 571 */ 572 HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60, 573 574 /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS 575 */ 576 HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61, 577 578 /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS 579 * PARAMS: 580 * - No Params 581 * RESP MSG: 582 * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv 583 */ 584 HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62, 585 586 /** HTT_DBG_MLO_SCHED_STATS 587 * PARAMS: 588 * - No Params 589 * RESP MSG: 590 * - htt_pdev_mlo_sched_stats_tlv 591 */ 592 HTT_DBG_MLO_SCHED_STATS = 63, 593 594 /** HTT_DBG_PDEV_MLO_IPC_STATS 595 * PARAMS: 596 * - No Params 597 * RESP MSG: 598 * - htt_pdev_mlo_ipc_stats_tlv 599 */ 600 HTT_DBG_PDEV_MLO_IPC_STATS = 64, 601 602 /** HTT_DBG_EXT_PDEV_RTT_RESP_STATS 603 * PARAMS: 604 * - No Params 605 * RESP MSG: 606 * - htt_stats_pdev_rtt_resp_stats_tlv 607 * - htt_stats_pdev_rtt_hw_stats_tlv 608 * - htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv 609 * - htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv 610 */ 611 HTT_DBG_EXT_PDEV_RTT_RESP_STATS = 65, 612 613 /** HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS 614 * PARAMS: 615 * - No Params 616 * RESP MSG: 617 * - htt_stats_pdev_rtt_init_stats_tlv 618 * - htt_stats_pdev_rtt_hw_stats_tlv 619 */ 620 HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS = 66, 621 622 623 /* keep this last */ 624 HTT_DBG_NUM_EXT_STATS = 256, 625 }; 626 627 /* 628 * Macros to get/set the bit field in config param[3] that indicates to 629 * clear corresponding per peer stats specified by config param 1 630 */ 631 #define HTT_DBG_EXT_PEER_STATS_RESET_M 0x00010000 632 #define HTT_DBG_EXT_PEER_STATS_RESET_S 16 633 634 #define HTT_DBG_EXT_PEER_STATS_RESET_GET(_var) \ 635 (((_var) & HTT_DBG_EXT_PEER_STATS_RESET_M) >> \ 636 HTT_DBG_EXT_PEER_STATS_RESET_S) 637 638 #define HTT_DBG_EXT_PEER_STATS_RESET_SET(_var, _val) \ 639 do { \ 640 HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_STATS_RESET, _val); \ 641 ((_var) |= ((_val) << HTT_DBG_EXT_PEER_STATS_RESET_S)); \ 642 } while (0) 643 644 #define HTT_STATS_SUBTYPE_MAX 16 645 646 /* htt_mu_stats_upload_t 647 * Enumerations for specifying whether to upload all MU stats in response to 648 * HTT_DBG_EXT_STATS_PDEV_TX_MU, or if not all, then which subset. 649 */ 650 typedef enum { 651 /* HTT_UPLOAD_MU_STATS: upload all MU stats: 652 * UL MU-MIMO + DL MU-MIMO + UL MU-OFDMA + DL MU-OFDMA 653 * (note: included OFDMA stats are limited to 11ax) 654 */ 655 HTT_UPLOAD_MU_STATS, 656 657 /* HTT_UPLOAD_MU_MIMO_STATS: upload UL MU-MIMO + DL MU-MIMO stats */ 658 HTT_UPLOAD_MU_MIMO_STATS, 659 660 /* HTT_UPLOAD_MU_OFDMA_STATS: 661 * upload UL MU-OFDMA + DL MU-OFDMA stats (note: 11ax only stats) 662 */ 663 HTT_UPLOAD_MU_OFDMA_STATS, 664 665 HTT_UPLOAD_DL_MU_MIMO_STATS, 666 HTT_UPLOAD_UL_MU_MIMO_STATS, 667 /* HTT_UPLOAD_DL_MU_OFDMA_STATS: 668 * upload DL MU-OFDMA stats (note: 11ax only stats) 669 */ 670 HTT_UPLOAD_DL_MU_OFDMA_STATS, 671 /* HTT_UPLOAD_UL_MU_OFDMA_STATS: 672 * upload UL MU-OFDMA stats (note: 11ax only stats) 673 */ 674 HTT_UPLOAD_UL_MU_OFDMA_STATS, 675 676 /* 677 * Upload BE UL MU-OFDMA + BE DL MU-OFDMA stats, 678 * TLV: htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv and 679 * htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv 680 */ 681 HTT_UPLOAD_BE_MU_OFDMA_STATS, 682 683 /* 684 * Upload BE DL MU-OFDMA 685 * TLV: htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv 686 */ 687 HTT_UPLOAD_BE_DL_MU_OFDMA_STATS, 688 689 /* 690 * Upload BE UL MU-OFDMA 691 * TLV: htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv 692 */ 693 HTT_UPLOAD_BE_UL_MU_OFDMA_STATS, 694 } htt_mu_stats_upload_t; 695 696 /* htt_tx_rate_stats_upload_t 697 * Enumerations for specifying which stats to upload in response to 698 * HTT_DBG_EXT_STATS_PDEV_TX_RATE. 699 */ 700 typedef enum { 701 /* 11abgn, 11ac, and 11ax TX stats, and a few 11be SU stats 702 * 703 * TLV: htt_tx_pdev_rate_stats_tlv 704 */ 705 HTT_TX_RATE_STATS_DEFAULT, 706 707 /* 708 * Upload 11be OFDMA TX stats 709 * 710 * TLV: htt_tx_pdev_rate_stats_be_ofdma_tlv 711 */ 712 HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA, 713 } htt_tx_rate_stats_upload_t; 714 715 /* htt_rx_ul_trigger_stats_upload_t 716 * Enumerations for specifying which stats to upload in response to 717 * HTT_DBG_EXT_STATS_PDEV_TX_RATE. 718 */ 719 typedef enum { 720 /* Upload 11ax UL OFDMA RX Trigger stats 721 * 722 * TLV: htt_rx_pdev_ul_trigger_stats_tlv 723 */ 724 HTT_RX_UL_TRIGGER_STATS_UPLOAD_11AX_OFDMA, 725 726 /* 727 * Upload 11be UL OFDMA RX Trigger stats 728 * 729 * TLV: htt_rx_pdev_be_ul_trigger_stats_tlv 730 */ 731 HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA, 732 } htt_rx_ul_trigger_stats_upload_t; 733 734 /* 735 * The htt_rx_ul_mumimo_trigger_stats_upload_t enum values are 736 * provided by the host as one of the config param elements in 737 * the HTT_H2T EXT_STATS_REQ message, for stats type == 738 * HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS. 739 */ 740 typedef enum { 741 /* 742 * Upload 11ax UL MUMIMO RX Trigger stats 743 * TLV: htt_rx_pdev_ul_mumimo_trig_stats_tlv 744 */ 745 HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11AX, 746 747 /* 748 * Upload 11be UL MUMIMO RX Trigger stats 749 * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv 750 */ 751 HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE, 752 } htt_rx_ul_mumimo_trigger_stats_upload_t; 753 754 /* htt_tx_pdev_txbf_ofdma_stats_upload_t 755 * Enumerations for specifying which stats to upload in response to 756 * HTT_DBG_EXT_STATS_TXBF_OFDMA. 757 */ 758 typedef enum { 759 /* upload 11ax TXBF OFDMA stats 760 * 761 * TLV: htt_tx_pdev_ax_txbf_ofdma_stats_t 762 */ 763 HTT_UPLOAD_AX_TXBF_OFDMA_STATS, 764 765 /* 766 * Upload 11be TXBF OFDMA stats 767 * 768 * TLV: htt_tx_pdev_be_txbf_ofdma_stats_t 769 */ 770 HTT_UPLOAD_BE_TXBF_OFDMA_STATS, 771 } htt_tx_pdev_txbf_ofdma_stats_upload_t; 772 773 /* htt_tx_pdev_puncture_stats_upload_t 774 * Enumerations for specifying which stats to upload in response to 775 * HTT_DBG_PDEV_PUNCTURE_STATS. 776 */ 777 typedef enum { 778 /* upload puncture stats for all supported modes, both TX and RX */ 779 HTT_UPLOAD_PUNCTURE_STATS_ALL, 780 781 /* upload puncture stats for all supported TX modes */ 782 HTT_UPLOAD_PUNCTURE_STATS_TX, 783 784 /* upload puncture stats for all supported RX modes */ 785 HTT_UPLOAD_PUNCTURE_STATS_RX, 786 } htt_tx_pdev_puncture_stats_upload_t; 787 788 #define HTT_STATS_MAX_STRING_SZ32 4 789 #define HTT_STATS_MACID_INVALID 0xff 790 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 791 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 792 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 793 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 794 #define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16 795 #define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250 796 797 typedef enum { 798 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 799 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 800 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 801 HTT_TX_PDEV_MAX_URRN_STATS = 3, 802 } htt_tx_pdev_underrun_enum; 803 804 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 805 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 806 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 807 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 808 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX: 809 * DEPRECATED - num sched tx mode max is 8 810 */ 811 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 812 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 813 814 #define HTT_RX_STATS_REFILL_MAX_RING 4 815 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 816 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 817 818 /* Bytes stored in little endian order */ 819 /* Length should be multiple of DWORD */ 820 typedef struct { 821 htt_tlv_hdr_t tlv_hdr; 822 A_UINT32 data[1]; /* Can be variable length */ 823 } htt_stats_string_tlv; 824 825 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_M 0x000000ff 826 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_S 0 827 828 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \ 829 (((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \ 830 HTT_TX_PDEV_STATS_CMN_MAC_ID_S) 831 832 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \ 833 do { \ 834 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \ 835 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_CMN_MAC_ID_S)); \ 836 } while (0) 837 838 /* == TX PDEV STATS == */ 839 typedef struct { 840 htt_tlv_hdr_t tlv_hdr; 841 842 /** 843 * BIT [ 7 : 0] :- mac_id 844 * BIT [31 : 8] :- reserved 845 */ 846 A_UINT32 mac_id__word; 847 /** Num PPDUs queued to HW */ 848 A_UINT32 hw_queued; 849 /** Num PPDUs reaped from HW */ 850 A_UINT32 hw_reaped; 851 /** Num underruns */ 852 A_UINT32 underrun; 853 /** Num HW Paused counter */ 854 A_UINT32 hw_paused; 855 /** Num HW flush counter */ 856 A_UINT32 hw_flush; 857 /** Num HW filtered counter */ 858 A_UINT32 hw_filt; 859 /** Num PPDUs cleaned up in TX abort */ 860 A_UINT32 tx_abort; 861 /** Num MPDUs requeued by SW */ 862 A_UINT32 mpdu_requed; 863 /** excessive retries */ 864 A_UINT32 tx_xretry; 865 /** Last used data hw rate code */ 866 A_UINT32 data_rc; 867 /** frames dropped due to excessive SW retries */ 868 A_UINT32 mpdu_dropped_xretry; 869 /** illegal rate phy errors */ 870 A_UINT32 illgl_rate_phy_err; 871 /** wal pdev continuous xretry */ 872 A_UINT32 cont_xretry; 873 /** wal pdev tx timeout */ 874 A_UINT32 tx_timeout; 875 /** wal pdev resets */ 876 A_UINT32 pdev_resets; 877 /** PHY/BB underrun */ 878 A_UINT32 phy_underrun; 879 /** MPDU is more than txop limit */ 880 A_UINT32 txop_ovf; 881 /** Number of Sequences posted */ 882 A_UINT32 seq_posted; 883 /** Number of Sequences failed queueing */ 884 A_UINT32 seq_failed_queueing; 885 /** Number of Sequences completed */ 886 A_UINT32 seq_completed; 887 /** Number of Sequences restarted */ 888 A_UINT32 seq_restarted; 889 /** Number of MU Sequences posted */ 890 A_UINT32 mu_seq_posted; 891 /** Number of time HW ring is paused between seq switch within ISR */ 892 A_UINT32 seq_switch_hw_paused; 893 /** Number of times seq continuation in DSR */ 894 A_UINT32 next_seq_posted_dsr; 895 /** Number of times seq continuation in ISR */ 896 A_UINT32 seq_posted_isr; 897 /** Number of seq_ctrl cached. */ 898 A_UINT32 seq_ctrl_cached; 899 /** Number of MPDUs successfully transmitted */ 900 A_UINT32 mpdu_count_tqm; 901 /** Number of MSDUs successfully transmitted */ 902 A_UINT32 msdu_count_tqm; 903 /** Number of MPDUs dropped */ 904 A_UINT32 mpdu_removed_tqm; 905 /** Number of MSDUs dropped */ 906 A_UINT32 msdu_removed_tqm; 907 /** Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 908 A_UINT32 mpdus_sw_flush; 909 /** Num MPDUs filtered by HW, all filter condition (TTL expired) */ 910 A_UINT32 mpdus_hw_filter; 911 /** 912 * Num MPDUs truncated by PDG 913 * (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) 914 */ 915 A_UINT32 mpdus_truncated; 916 /** Num MPDUs that was tried but didn't receive ACK or BA */ 917 A_UINT32 mpdus_ack_failed; 918 /** Num MPDUs that was dropped due to expiry (MSDU TTL) */ 919 A_UINT32 mpdus_expired; 920 /** Num MPDUs that was retried within seq_ctrl (MGMT/LEGACY) */ 921 A_UINT32 mpdus_seq_hw_retry; 922 /** Num of TQM acked cmds processed */ 923 A_UINT32 ack_tlv_proc; 924 /** coex_abort_mpdu_cnt valid */ 925 A_UINT32 coex_abort_mpdu_cnt_valid; 926 /** coex_abort_mpdu_cnt from TX FES stats */ 927 A_UINT32 coex_abort_mpdu_cnt; 928 /** 929 * Number of total PPDUs 930 * (DATA, MGMT, excludes selfgen) tried over the air (OTA) 931 */ 932 A_UINT32 num_total_ppdus_tried_ota; 933 /** Number of data PPDUs tried over the air (OTA) */ 934 A_UINT32 num_data_ppdus_tried_ota; 935 /** Num Local control/mgmt frames (MSDUs) queued */ 936 A_UINT32 local_ctrl_mgmt_enqued; 937 /** 938 * Num Local control/mgmt frames (MSDUs) done 939 * It includes all local ctrl/mgmt completions 940 * (acked, no ack, flush, TTL, etc) 941 */ 942 A_UINT32 local_ctrl_mgmt_freed; 943 /** Num Local data frames (MSDUs) queued */ 944 A_UINT32 local_data_enqued; 945 /** 946 * Num Local data frames (MSDUs) done 947 * It includes all local data completions 948 * (acked, no ack, flush, TTL, etc) 949 */ 950 A_UINT32 local_data_freed; 951 952 /** Num MPDUs tried by SW */ 953 A_UINT32 mpdu_tried; 954 /** Num of waiting seq posted in ISR completion handler */ 955 A_UINT32 isr_wait_seq_posted; 956 957 A_UINT32 tx_active_dur_us_low; 958 A_UINT32 tx_active_dur_us_high; 959 /** Number of MPDUs dropped after max retries */ 960 A_UINT32 remove_mpdus_max_retries; 961 /** Num HTT cookies dispatched */ 962 A_UINT32 comp_delivered; 963 /** successful ppdu transmissions */ 964 A_UINT32 ppdu_ok; 965 /** Scheduler self triggers */ 966 A_UINT32 self_triggers; 967 /** FES duration of last tx data PPDU in us (sch_eval_end - ppdu_start) */ 968 A_UINT32 tx_time_dur_data; 969 /** Num of times sequence terminated due to ppdu duration < burst limit */ 970 A_UINT32 seq_qdepth_repost_stop; 971 /** Num of times MU sequence terminated due to MSDUs reaching threshold */ 972 A_UINT32 mu_seq_min_msdu_repost_stop; 973 /** Num of times SU sequence terminated due to MSDUs reaching threshold */ 974 A_UINT32 seq_min_msdu_repost_stop; 975 /** Num of times sequence terminated due to no TXOP available */ 976 A_UINT32 seq_txop_repost_stop; 977 /** Num of times the next sequence got cancelled */ 978 A_UINT32 next_seq_cancel; 979 /** Num of times fes offset was misaligned */ 980 A_UINT32 fes_offsets_err_cnt; 981 /** Num of times peer denylisted for MU-MIMO transmission */ 982 A_UINT32 num_mu_peer_blacklisted; 983 /** Num of times mu_ofdma seq posted */ 984 A_UINT32 mu_ofdma_seq_posted; 985 /** Num of times UL MU MIMO seq posted */ 986 A_UINT32 ul_mumimo_seq_posted; 987 /** Num of times UL OFDMA seq posted */ 988 A_UINT32 ul_ofdma_seq_posted; 989 /** Num of times Thermal module suspended scheduler */ 990 A_UINT32 thermal_suspend_cnt; 991 /** Num of times DFS module suspended scheduler */ 992 A_UINT32 dfs_suspend_cnt; 993 /** Num of times TX abort module suspended scheduler */ 994 A_UINT32 tx_abort_suspend_cnt; 995 /** 996 * This field is a target-specific bit mask of suspended PPDU tx queues. 997 * Since the bit mask definition is different for different targets, 998 * this field is not meant for general use, but rather for debugging use. 999 */ 1000 A_UINT32 tgt_specific_opaque_txq_suspend_info; 1001 /** 1002 * Last SCHEDULER suspend reason 1003 * 1 -> Thermal Module 1004 * 2 -> DFS Module 1005 * 3 -> Tx Abort Module 1006 */ 1007 A_UINT32 last_suspend_reason; 1008 /** Num of dynamic mimo ps dlmumimo sequences posted */ 1009 A_UINT32 num_dyn_mimo_ps_dlmumimo_sequences; 1010 /** Num of times su bf sequences are denylisted */ 1011 A_UINT32 num_su_txbf_denylisted; 1012 /** pdev uptime in microseconds **/ 1013 A_UINT32 pdev_up_time_us_low; 1014 A_UINT32 pdev_up_time_us_high; 1015 /** count of ofdma sequences flushed */ 1016 A_UINT32 ofdma_seq_flush; 1017 } htt_stats_tx_pdev_cmn_tlv; 1018 /* preserve old name alias for new name consistent with the tag name */ 1019 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; 1020 1021 #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1022 /* NOTE: Variable length TLV, use length spec to infer array size */ 1023 typedef struct { 1024 htt_tlv_hdr_t tlv_hdr; 1025 A_UINT32 urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */ 1026 } htt_stats_tx_pdev_underrun_tlv; 1027 /* preserve old name alias for new name consistent with the tag name */ 1028 typedef htt_stats_tx_pdev_underrun_tlv htt_tx_pdev_stats_urrn_tlv_v; 1029 1030 #define HTT_TX_PDEV_STATS_FLUSH_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1031 /* NOTE: Variable length TLV, use length spec to infer array size */ 1032 typedef struct { 1033 htt_tlv_hdr_t tlv_hdr; 1034 A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 1035 } htt_stats_tx_pdev_flush_tlv; 1036 /* preserve old name alias for new name consistent with the tag name */ 1037 typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; 1038 1039 #define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1040 /* NOTE: Variable length TLV, use length spec to infer array size */ 1041 typedef struct { 1042 htt_tlv_hdr_t tlv_hdr; 1043 A_UINT32 mlo_abort_cnt[1]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ 1044 } htt_stats_tx_pdev_mlo_abort_tlv; 1045 /* preserve old name alias for new name consistent with the tag name */ 1046 typedef htt_stats_tx_pdev_mlo_abort_tlv htt_tx_pdev_stats_mlo_abort_tlv_v; 1047 1048 #define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1049 /* NOTE: Variable length TLV, use length spec to infer array size */ 1050 typedef struct { 1051 htt_tlv_hdr_t tlv_hdr; 1052 A_UINT32 mlo_txop_abort_cnt[1]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ 1053 } htt_stats_tx_pdev_mlo_txop_abort_tlv; 1054 /* preserve old name alias for new name consistent with the tag name */ 1055 typedef htt_stats_tx_pdev_mlo_txop_abort_tlv 1056 htt_tx_pdev_stats_mlo_txop_abort_tlv_v; 1057 1058 #define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1059 /* NOTE: Variable length TLV, use length spec to infer array size */ 1060 typedef struct { 1061 htt_tlv_hdr_t tlv_hdr; 1062 A_UINT32 sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 1063 } htt_stats_tx_pdev_sifs_tlv; 1064 /* preserve old name alias for new name consistent with the tag name */ 1065 typedef htt_stats_tx_pdev_sifs_tlv htt_tx_pdev_stats_sifs_tlv_v; 1066 1067 #define HTT_TX_PDEV_STATS_PHY_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1068 /* NOTE: Variable length TLV, use length spec to infer array size */ 1069 typedef struct { 1070 htt_tlv_hdr_t tlv_hdr; 1071 A_UINT32 phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 1072 } htt_stats_tx_pdev_phy_err_tlv; 1073 /* preserve old name alias for new name consistent with the tag name */ 1074 typedef htt_stats_tx_pdev_phy_err_tlv htt_tx_pdev_stats_phy_err_tlv_v; 1075 1076 /* 1077 * Each array in the below struct has 16 elements, to cover the 16 possible 1078 * values for the CW and AIFS parameters. Each element within the array 1079 * stores the counter indicating how many transmissions have occurred with 1080 * that particular value for the MU EDCA parameter in question. 1081 */ 1082 #define HTT_STATS_MUEDCA_VALUE_MAX 16 1083 typedef struct { /* DEPRECATED */ 1084 htt_tlv_hdr_t tlv_hdr; 1085 A_UINT32 aifs[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1086 A_UINT32 cw_min[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1087 A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX]; 1088 } htt_stats_tx_pdev_muedca_params_stats_tlv; 1089 /* preserve old name alias for new name consistent with the tag name */ 1090 typedef htt_stats_tx_pdev_muedca_params_stats_tlv 1091 htt_tx_pdev_muedca_params_stats_tlv_v; 1092 1093 typedef struct { 1094 htt_tlv_hdr_t tlv_hdr; 1095 A_UINT32 relaxed_mu_edca[HTT_NUM_AC_WMM]; 1096 A_UINT32 mumimo_aggressive_mu_edca[HTT_NUM_AC_WMM]; 1097 A_UINT32 mumimo_relaxed_mu_edca[HTT_NUM_AC_WMM]; 1098 A_UINT32 muofdma_aggressive_mu_edca[HTT_NUM_AC_WMM]; 1099 A_UINT32 muofdma_relaxed_mu_edca[HTT_NUM_AC_WMM]; 1100 A_UINT32 latency_mu_edca[HTT_NUM_AC_WMM]; 1101 A_UINT32 psd_boost_mu_edca[HTT_NUM_AC_WMM]; 1102 } htt_stats_tx_pdev_mu_edca_params_stats_tlv; 1103 /* preserve old name alias for new name consistent with the tag name */ 1104 typedef htt_stats_tx_pdev_mu_edca_params_stats_tlv 1105 htt_tx_pdev_mu_edca_params_stats_tlv_v; 1106 1107 typedef struct { 1108 htt_tlv_hdr_t tlv_hdr; 1109 A_UINT32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM]; 1110 A_UINT32 ul_mumimo_medium_aggressive[HTT_NUM_AC_WMM]; 1111 A_UINT32 ul_mumimo_highly_aggressive[HTT_NUM_AC_WMM]; 1112 A_UINT32 ul_mumimo_default_relaxed[HTT_NUM_AC_WMM]; 1113 A_UINT32 ul_muofdma_less_aggressive[HTT_NUM_AC_WMM]; 1114 A_UINT32 ul_muofdma_medium_aggressive[HTT_NUM_AC_WMM]; 1115 A_UINT32 ul_muofdma_highly_aggressive[HTT_NUM_AC_WMM]; 1116 A_UINT32 ul_muofdma_default_relaxed[HTT_NUM_AC_WMM]; 1117 } htt_stats_tx_pdev_ap_edca_params_stats_tlv; 1118 /* preserve old name alias for new name consistent with the tag name */ 1119 typedef htt_stats_tx_pdev_ap_edca_params_stats_tlv 1120 htt_tx_pdev_ap_edca_params_stats_tlv_v; 1121 1122 #define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10 1123 #define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1124 /* NOTE: Variable length TLV, use length spec to infer array size */ 1125 typedef struct { 1126 htt_tlv_hdr_t tlv_hdr; 1127 A_UINT32 sifs_hist_status[1]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 1128 } htt_stats_tx_pdev_sifs_hist_tlv; 1129 /* preserve old name alias for new name consistent with the tag name */ 1130 typedef htt_stats_tx_pdev_sifs_hist_tlv htt_tx_pdev_stats_sifs_hist_tlv_v; 1131 1132 typedef struct { 1133 htt_tlv_hdr_t tlv_hdr; 1134 A_UINT32 num_data_ppdus_legacy_su; 1135 A_UINT32 num_data_ppdus_ac_su; 1136 A_UINT32 num_data_ppdus_ax_su; 1137 A_UINT32 num_data_ppdus_ac_su_txbf; 1138 A_UINT32 num_data_ppdus_ax_su_txbf; 1139 } htt_stats_tx_pdev_tx_ppdu_stats_tlv; 1140 /* preserve old name alias for new name consistent with the tag name */ 1141 typedef htt_stats_tx_pdev_tx_ppdu_stats_tlv 1142 htt_tx_pdev_stats_tx_ppdu_stats_tlv_v; 1143 1144 typedef enum { 1145 HTT_TX_WAL_ISR_SCHED_SUCCESS, 1146 HTT_TX_WAL_ISR_SCHED_FILTER, 1147 HTT_TX_WAL_ISR_SCHED_RESP_TIMEOUT, 1148 HTT_TX_WAL_ISR_SCHED_RATES_EXHAUSTED, 1149 HTT_TX_WAL_ISR_SCHED_DATA_EXHAUSTED, 1150 HTT_TX_WAL_ISR_SCHED_SEQ_ABORT, 1151 HTT_TX_WAL_ISR_SCHED_NOTIFY_FRAME_ENCOUNTERED, 1152 HTT_TX_WAL_ISR_SCHED_COMPLETION, 1153 HTT_TX_WAL_ISR_SCHED_IN_PROGRESS, 1154 } htt_tx_wal_tx_isr_sched_status; 1155 1156 /* [0]- nr4 , [1]- nr8 */ 1157 #define HTT_STATS_NUM_NR_BINS 2 1158 /* Termination status stated in htt_tx_wal_tx_isr_sched_status */ 1159 #define HTT_STATS_MAX_NUM_SCHED_STATUS 9 1160 #define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 1161 #define HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS \ 1162 (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_SCHED_STATUS) 1163 #define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS \ 1164 (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 1165 1166 typedef enum { 1167 HTT_STATS_HWMODE_AC = 0, 1168 HTT_STATS_HWMODE_AX = 1, 1169 HTT_STATS_HWMODE_BE = 2, 1170 } htt_stats_hw_mode; 1171 1172 typedef struct { 1173 htt_tlv_hdr_t tlv_hdr; 1174 1175 A_UINT32 hw_mode; /* HTT_STATS_HWMODE_xx */ 1176 1177 A_UINT32 mu_mimo_num_seq_term_status[HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS]; 1178 1179 A_UINT32 mu_mimo_num_ppdu_completed_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; 1180 1181 A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS]; 1182 1183 A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; 1184 } htt_stats_mu_ppdu_dist_tlv; 1185 /* preserve old name alias for new name consistent with the tag name */ 1186 typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v; 1187 1188 #define HTT_TX_PDEV_STATS_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 1189 /* NOTE: Variable length TLV, use length spec to infer array size . 1190 * 1191 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 1192 * The tries here is the count of the MPDUS within a PPDU that the 1193 * HW had attempted to transmit on air, for the HWSCH Schedule 1194 * command submitted by FW.It is not the retry attempts. 1195 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 1196 * 10 bins in this histogram. They are defined in FW using the 1197 * following macros 1198 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 1199 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 1200 * 1201 */ 1202 typedef struct { 1203 htt_tlv_hdr_t tlv_hdr; 1204 A_UINT32 hist_bin_size; 1205 A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 1206 } htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv; 1207 /* preserve old name alias for new name consistent with the tag name */ 1208 typedef htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv 1209 htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v; 1210 1211 typedef struct { 1212 htt_tlv_hdr_t tlv_hdr; 1213 /* Num MGMT MPDU transmitted by the target */ 1214 A_UINT32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1215 } htt_stats_pdev_ctrl_path_tx_stats_tlv; 1216 /* preserve old name alias for new name consistent with the tag name */ 1217 typedef htt_stats_pdev_ctrl_path_tx_stats_tlv htt_pdev_ctrl_path_tx_stats_tlv_v; 1218 1219 /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_TX 1220 * TLV_TAGS: 1221 * - HTT_STATS_TX_PDEV_CMN_TAG 1222 * - HTT_STATS_TX_PDEV_URRN_TAG 1223 * - HTT_STATS_TX_PDEV_SIFS_TAG 1224 * - HTT_STATS_TX_PDEV_FLUSH_TAG 1225 * - HTT_STATS_TX_PDEV_PHY_ERR_TAG 1226 * - HTT_STATS_TX_PDEV_SIFS_HIST_TAG 1227 * - HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG 1228 * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG 1229 * - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG 1230 * - HTT_STATS_MU_PPDU_DIST_TAG 1231 */ 1232 /* NOTE: 1233 * This structure is for documentation, and cannot be safely used directly. 1234 * Instead, use the constituent TLV structures to fill/parse. 1235 */ 1236 typedef struct _htt_tx_pdev_stats { 1237 htt_stats_tx_pdev_cmn_tlv cmn_tlv; 1238 htt_stats_tx_pdev_underrun_tlv underrun_tlv; 1239 htt_stats_tx_pdev_sifs_tlv sifs_tlv; 1240 htt_stats_tx_pdev_flush_tlv flush_tlv; 1241 htt_stats_tx_pdev_phy_err_tlv phy_err_tlv; 1242 htt_stats_tx_pdev_sifs_hist_tlv sifs_hist_tlv; 1243 htt_stats_tx_pdev_tx_ppdu_stats_tlv tx_su_tlv; 1244 htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv tried_mpdu_cnt_hist_tlv; 1245 htt_stats_pdev_ctrl_path_tx_stats_tlv ctrl_path_tx_tlv; 1246 htt_stats_mu_ppdu_dist_tlv mu_ppdu_dist_tlv; 1247 } htt_tx_pdev_stats_t; 1248 1249 /* == SOC ERROR STATS == */ 1250 1251 /* =============== PDEV ERROR STATS ============== */ 1252 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 1253 typedef struct { 1254 htt_tlv_hdr_t tlv_hdr; 1255 /* Stored as little endian */ 1256 A_UINT8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 1257 A_UINT32 mask; 1258 A_UINT32 count; 1259 } htt_stats_hw_intr_misc_tlv; 1260 /* preserve old name alias for new name consistent with the tag name */ 1261 typedef htt_stats_hw_intr_misc_tlv htt_hw_stats_intr_misc_tlv; 1262 1263 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 1264 typedef struct { 1265 htt_tlv_hdr_t tlv_hdr; 1266 /* Stored as little endian */ 1267 A_UINT8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 1268 A_UINT32 count; 1269 } htt_stats_hw_wd_timeout_tlv; 1270 /* preserve old name alias for new name consistent with the tag name */ 1271 typedef htt_stats_hw_wd_timeout_tlv htt_hw_stats_wd_timeout_tlv; 1272 1273 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_M 0x000000ff 1274 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_S 0 1275 1276 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_GET(_var) \ 1277 (((_var) & HTT_HW_STATS_PDEV_ERRS_MAC_ID_M) >> \ 1278 HTT_HW_STATS_PDEV_ERRS_MAC_ID_S) 1279 1280 #define HTT_HW_STATS_PDEV_ERRS_MAC_ID_SET(_var, _val) \ 1281 do { \ 1282 HTT_CHECK_SET_VAL(HTT_HW_STATS_PDEV_ERRS_MAC_ID, _val); \ 1283 ((_var) |= ((_val) << HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)); \ 1284 } while (0) 1285 1286 typedef struct { 1287 htt_tlv_hdr_t tlv_hdr; 1288 1289 /* BIT [ 7 : 0] :- mac_id 1290 * BIT [31 : 8] :- reserved 1291 */ 1292 A_UINT32 mac_id__word; 1293 A_UINT32 tx_abort; 1294 A_UINT32 tx_abort_fail_count; 1295 A_UINT32 rx_abort; 1296 A_UINT32 rx_abort_fail_count; 1297 A_UINT32 warm_reset; 1298 A_UINT32 cold_reset; 1299 A_UINT32 tx_flush; 1300 A_UINT32 tx_glb_reset; 1301 A_UINT32 tx_txq_reset; 1302 A_UINT32 rx_timeout_reset; 1303 A_UINT32 mac_cold_reset_restore_cal; 1304 A_UINT32 mac_cold_reset; 1305 A_UINT32 mac_warm_reset; 1306 A_UINT32 mac_only_reset; 1307 A_UINT32 phy_warm_reset; 1308 A_UINT32 phy_warm_reset_ucode_trig; 1309 A_UINT32 mac_warm_reset_restore_cal; 1310 A_UINT32 mac_sfm_reset; 1311 A_UINT32 phy_warm_reset_m3_ssr; 1312 A_UINT32 phy_warm_reset_reason_phy_m3; 1313 A_UINT32 phy_warm_reset_reason_tx_hw_stuck; 1314 A_UINT32 phy_warm_reset_reason_num_cca_rx_frame_stuck; 1315 A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy; 1316 A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang; 1317 A_UINT32 phy_warm_reset_reason_mac_reset_converted_phy_reset; 1318 1319 A_UINT32 wal_rx_recovery_rst_mac_hang_count; 1320 A_UINT32 wal_rx_recovery_rst_known_sig_count; 1321 A_UINT32 wal_rx_recovery_rst_no_rx_count; 1322 A_UINT32 wal_rx_recovery_rst_no_rx_consecutive_count; 1323 A_UINT32 wal_rx_recovery_rst_rx_busy_count; 1324 A_UINT32 wal_rx_recovery_rst_phy_mac_hang_count; 1325 A_UINT32 rx_flush_cnt; /* Num rx flush issued */ 1326 A_UINT32 phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck; 1327 A_UINT32 phy_warm_reset_reason_tx_consecutive_flush9_war; 1328 A_UINT32 phy_warm_reset_reason_tx_hwsch_reset_war; 1329 A_UINT32 phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war; 1330 A_UINT32 fw_rx_rings_reset; 1331 /** 1332 * Num of iterations rx leak prevention successfully done. 1333 */ 1334 A_UINT32 rx_dest_drain_rx_descs_leak_prevention_done; 1335 /** 1336 * Num of rx descs successfully saved by rx leak prevention. 1337 */ 1338 A_UINT32 rx_dest_drain_rx_descs_saved_cnt; 1339 /* 1340 * Stats to debug reason Rx leak prevention 1341 * was not required to be kicked in. 1342 */ 1343 A_UINT32 rx_dest_drain_rxdma2reo_leak_detected; 1344 A_UINT32 rx_dest_drain_rxdma2fw_leak_detected; 1345 A_UINT32 rx_dest_drain_rxdma2wbm_leak_detected; 1346 A_UINT32 rx_dest_drain_rxdma1_2sw_leak_detected; 1347 A_UINT32 rx_dest_drain_rx_drain_ok_mac_idle; 1348 A_UINT32 rx_dest_drain_ok_mac_not_idle; 1349 A_UINT32 rx_dest_drain_prerequisite_invld; 1350 A_UINT32 rx_dest_drain_skip_for_non_lmac_reset; 1351 A_UINT32 rx_dest_drain_hw_fifo_not_empty_post_drain_wait; 1352 } htt_stats_hw_pdev_errs_tlv; 1353 /* preserve old name alias for new name consistent with the tag name */ 1354 typedef htt_stats_hw_pdev_errs_tlv htt_hw_stats_pdev_errs_tlv; 1355 1356 typedef struct { 1357 htt_tlv_hdr_t tlv_hdr; 1358 1359 /* BIT [ 7 : 0] :- mac_id 1360 * BIT [31 : 8] :- reserved 1361 */ 1362 A_UINT32 mac_id__word; 1363 A_UINT32 last_unpause_ppdu_id; 1364 A_UINT32 hwsch_unpause_wait_tqm_write; 1365 A_UINT32 hwsch_dummy_tlv_skipped; 1366 A_UINT32 hwsch_misaligned_offset_received; 1367 A_UINT32 hwsch_reset_count; 1368 A_UINT32 hwsch_dev_reset_war; 1369 A_UINT32 hwsch_delayed_pause; 1370 A_UINT32 hwsch_long_delayed_pause; 1371 A_UINT32 sch_rx_ppdu_no_response; 1372 A_UINT32 sch_selfgen_response; 1373 A_UINT32 sch_rx_sifs_resp_trigger; 1374 } htt_stats_whal_tx_tlv; 1375 /* preserve old name alias for new name consistent with the tag name */ 1376 typedef htt_stats_whal_tx_tlv htt_hw_stats_whal_tx_tlv; 1377 1378 typedef struct { 1379 htt_tlv_hdr_t tlv_hdr; 1380 1381 A_UINT32 wsib_event_watchdog_timeout; 1382 A_UINT32 wsib_event_slave_tlv_length_error; 1383 A_UINT32 wsib_event_slave_parity_error; 1384 A_UINT32 wsib_event_slave_direct_message; 1385 A_UINT32 wsib_event_slave_backpressure_error; 1386 A_UINT32 wsib_event_master_tlv_length_error; 1387 } htt_stats_whal_wsi_tlv; 1388 1389 typedef struct { 1390 htt_tlv_hdr_t tlv_hdr; 1391 /** 1392 * BIT [ 7 : 0] :- mac_id 1393 * BIT [31 : 8] :- reserved 1394 */ 1395 union { 1396 struct { 1397 A_UINT32 mac_id: 8, 1398 reserved: 24; 1399 }; 1400 A_UINT32 mac_id__word; 1401 }; 1402 1403 /** 1404 * hw_wars is a variable-length array, with each element counting 1405 * the number of occurrences of the corresponding type of HW WAR. 1406 * That is, hw_wars[0] indicates how many times HW WAR 0 occurred, 1407 * hw_wars[1] indicates how many times HW WAR 1 occurred, etc. 1408 * The target has an internal HW WAR mapping that it uses to keep 1409 * track of which HW WAR is WAR 0, which HW WAR is WAR 1, etc. 1410 */ 1411 A_UINT32 hw_wars[1/*or more*/]; 1412 } htt_stats_hw_war_tlv; 1413 /* preserve old name alias for new name consistent with the tag name */ 1414 typedef htt_stats_hw_war_tlv htt_hw_war_stats_tlv; 1415 1416 /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_ERROR 1417 * TLV_TAGS: 1418 * - HTT_STATS_HW_PDEV_ERRS_TAG 1419 * - HTT_STATS_HW_INTR_MISC_TAG (multiple) 1420 * - HTT_STATS_HW_WD_TIMEOUT_TAG (multiple) 1421 * - HTT_STATS_WHAL_TX_TAG 1422 * - HTT_STATS_HW_WAR_TAG 1423 */ 1424 /* NOTE: 1425 * This structure is for documentation, and cannot be safely used directly. 1426 * Instead, use the constituent TLV structures to fill/parse. 1427 */ 1428 typedef struct _htt_pdev_err_stats { 1429 htt_stats_hw_pdev_errs_tlv pdev_errs; 1430 htt_stats_hw_intr_misc_tlv misc_stats[1]; 1431 htt_stats_hw_wd_timeout_tlv wd_timeout[1]; 1432 htt_stats_whal_tx_tlv whal_tx_stats; 1433 htt_stats_hw_war_tlv hw_war; 1434 } htt_hw_err_stats_t; 1435 1436 /* ============ PEER STATS ============ */ 1437 1438 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M 0x0000ffff 1439 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S 0 1440 #define HTT_MSDU_FLOW_STATS_TID_NUM_M 0x000f0000 1441 #define HTT_MSDU_FLOW_STATS_TID_NUM_S 16 1442 #define HTT_MSDU_FLOW_STATS_DROP_M 0x00100000 1443 #define HTT_MSDU_FLOW_STATS_DROP_S 20 1444 1445 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \ 1446 (((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \ 1447 HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S) 1448 1449 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \ 1450 do { \ 1451 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TX_FLOW_NUM, _val); \ 1452 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)); \ 1453 } while (0) 1454 1455 #define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \ 1456 (((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \ 1457 HTT_MSDU_FLOW_STATS_TID_NUM_S) 1458 1459 #define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \ 1460 do { \ 1461 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TID_NUM, _val); \ 1462 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TID_NUM_S)); \ 1463 } while (0) 1464 1465 #define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \ 1466 (((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \ 1467 HTT_MSDU_FLOW_STATS_DROP_S) 1468 1469 #define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \ 1470 do { \ 1471 HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_DROP, _val); \ 1472 ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_DROP_S)); \ 1473 } while (0) 1474 1475 typedef struct _htt_msdu_flow_stats_tlv { 1476 htt_tlv_hdr_t tlv_hdr; 1477 1478 A_UINT32 last_update_timestamp; 1479 A_UINT32 last_add_timestamp; 1480 A_UINT32 last_remove_timestamp; 1481 A_UINT32 total_processed_msdu_count; 1482 A_UINT32 cur_msdu_count_in_flowq; 1483 /** This will help to find which peer_id is stuck state */ 1484 A_UINT32 sw_peer_id; 1485 /** 1486 * BIT [15 : 0] :- tx_flow_number 1487 * BIT [19 : 16] :- tid_num 1488 * BIT [20 : 20] :- drop_rule 1489 * BIT [31 : 21] :- reserved 1490 */ 1491 A_UINT32 tx_flow_no__tid_num__drop_rule; 1492 A_UINT32 last_cycle_enqueue_count; 1493 A_UINT32 last_cycle_dequeue_count; 1494 A_UINT32 last_cycle_drop_count; 1495 /** 1496 * BIT [15 : 0] :- current_drop_th 1497 * BIT [31 : 16] :- reserved 1498 */ 1499 A_UINT32 current_drop_th; 1500 } htt_stats_peer_msdu_flowq_tlv; 1501 /* preserve old name alias for new name consistent with the tag name */ 1502 typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; 1503 1504 #define MAX_HTT_TID_NAME 8 1505 1506 /* DWORD sw_peer_id__tid_num */ 1507 #define HTT_TX_TID_STATS_SW_PEER_ID_M 0x0000ffff 1508 #define HTT_TX_TID_STATS_SW_PEER_ID_S 0 1509 #define HTT_TX_TID_STATS_TID_NUM_M 0xffff0000 1510 #define HTT_TX_TID_STATS_TID_NUM_S 16 1511 1512 #define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \ 1513 (((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \ 1514 HTT_TX_TID_STATS_SW_PEER_ID_S) 1515 1516 #define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ 1517 do { \ 1518 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \ 1519 ((_var) |= ((_val) << HTT_TX_TID_STATS_SW_PEER_ID_S)); \ 1520 } while (0) 1521 1522 #define HTT_TX_TID_STATS_TID_NUM_GET(_var) \ 1523 (((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \ 1524 HTT_TX_TID_STATS_TID_NUM_S) 1525 1526 #define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \ 1527 do { \ 1528 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \ 1529 ((_var) |= ((_val) << HTT_TX_TID_STATS_TID_NUM_S)); \ 1530 } while (0) 1531 1532 /* DWORD num_sched_pending__num_ppdu_in_hwq */ 1533 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_M 0x000000ff 1534 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_S 0 1535 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M 0x0000ff00 1536 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S 8 1537 1538 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \ 1539 (((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \ 1540 HTT_TX_TID_STATS_NUM_SCHED_PENDING_S) 1541 1542 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \ 1543 do { \ 1544 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \ 1545 ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)); \ 1546 } while (0) 1547 1548 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \ 1549 (((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \ 1550 HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S) 1551 1552 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \ 1553 do { \ 1554 HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \ 1555 ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)); \ 1556 } while (0) 1557 1558 /* Tidq stats */ 1559 typedef struct _htt_tx_tid_stats_tlv { 1560 htt_tlv_hdr_t tlv_hdr; 1561 1562 /** Stored as little endian */ 1563 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1564 /** 1565 * BIT [15 : 0] :- sw_peer_id 1566 * BIT [31 : 16] :- tid_num 1567 */ 1568 A_UINT32 sw_peer_id__tid_num; 1569 /** 1570 * BIT [ 7 : 0] :- num_sched_pending 1571 * BIT [15 : 8] :- num_ppdu_in_hwq 1572 * BIT [31 : 16] :- reserved 1573 */ 1574 A_UINT32 num_sched_pending__num_ppdu_in_hwq; 1575 A_UINT32 tid_flags; 1576 /** per tid # of hw_queued ppdu */ 1577 A_UINT32 hw_queued; 1578 /** number of per tid successful PPDU */ 1579 A_UINT32 hw_reaped; 1580 /** per tid Num MPDUs filtered by HW */ 1581 A_UINT32 mpdus_hw_filter; 1582 1583 A_UINT32 qdepth_bytes; 1584 A_UINT32 qdepth_num_msdu; 1585 A_UINT32 qdepth_num_mpdu; 1586 A_UINT32 last_scheduled_tsmp; 1587 A_UINT32 pause_module_id; 1588 A_UINT32 block_module_id; 1589 /** tid tx airtime in sec */ 1590 A_UINT32 tid_tx_airtime; 1591 } htt_stats_tx_tid_details_tlv; 1592 /* preserve old name alias for new name consistent with the tag name */ 1593 typedef htt_stats_tx_tid_details_tlv htt_tx_tid_stats_tlv; 1594 1595 /* Tidq stats */ 1596 typedef struct _htt_tx_tid_stats_v1_tlv { 1597 htt_tlv_hdr_t tlv_hdr; 1598 /** Stored as little endian */ 1599 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1600 /** 1601 * BIT [15 : 0] :- sw_peer_id 1602 * BIT [31 : 16] :- tid_num 1603 */ 1604 A_UINT32 sw_peer_id__tid_num; 1605 /** 1606 * BIT [ 7 : 0] :- num_sched_pending 1607 * BIT [15 : 8] :- num_ppdu_in_hwq 1608 * BIT [31 : 16] :- reserved 1609 */ 1610 A_UINT32 num_sched_pending__num_ppdu_in_hwq; 1611 A_UINT32 tid_flags; 1612 /** Max qdepth in bytes reached by this tid */ 1613 A_UINT32 max_qdepth_bytes; 1614 /** number of msdus qdepth reached max */ 1615 A_UINT32 max_qdepth_n_msdus; 1616 A_UINT32 rsvd; 1617 1618 A_UINT32 qdepth_bytes; 1619 A_UINT32 qdepth_num_msdu; 1620 A_UINT32 qdepth_num_mpdu; 1621 A_UINT32 last_scheduled_tsmp; 1622 A_UINT32 pause_module_id; 1623 A_UINT32 block_module_id; 1624 /** tid tx airtime in sec */ 1625 A_UINT32 tid_tx_airtime; 1626 A_UINT32 allow_n_flags; 1627 /** 1628 * BIT [15 : 0] :- sendn_frms_allowed 1629 * BIT [31 : 16] :- reserved 1630 */ 1631 A_UINT32 sendn_frms_allowed; 1632 /* 1633 * tid_ext_flags, tid_ext2_flags, and tid_flush_reason are opaque fields 1634 * that cannot be interpreted by the host. 1635 * They are only for off-line debug. 1636 */ 1637 A_UINT32 tid_ext_flags; 1638 A_UINT32 tid_ext2_flags; 1639 A_UINT32 tid_flush_reason; 1640 A_UINT32 mlo_flush_tqm_status_pending_low; 1641 A_UINT32 mlo_flush_tqm_status_pending_high; 1642 A_UINT32 mlo_flush_partner_info_low; 1643 A_UINT32 mlo_flush_partner_info_high; 1644 A_UINT32 mlo_flush_initator_info_low; 1645 A_UINT32 mlo_flush_initator_info_high; 1646 /* 1647 * head_msdu_tqm_timestamp_us: 1648 * MSDU enqueue timestamp (TQM reference timestamp) for the MSDU 1649 * at the head of the MPDU queue 1650 * head_msdu_tqm_latency_us: 1651 * The age of the MSDU that is at the head of the MPDU queue, 1652 * i.e. the delta between the current TQM time and the MSDU's 1653 * enqueue timestamp. 1654 */ 1655 A_UINT32 head_msdu_tqm_timestamp_us; 1656 A_UINT32 head_msdu_tqm_latency_us; 1657 } htt_stats_tx_tid_details_v1_tlv; 1658 /* preserve old name alias for new name consistent with the tag name */ 1659 typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; 1660 1661 #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff 1662 #define HTT_RX_TID_STATS_SW_PEER_ID_S 0 1663 #define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000 1664 #define HTT_RX_TID_STATS_TID_NUM_S 16 1665 1666 #define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \ 1667 (((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \ 1668 HTT_RX_TID_STATS_SW_PEER_ID_S) 1669 1670 #define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ 1671 do { \ 1672 HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \ 1673 ((_var) |= ((_val) << HTT_RX_TID_STATS_SW_PEER_ID_S)); \ 1674 } while (0) 1675 1676 #define HTT_RX_TID_STATS_TID_NUM_GET(_var) \ 1677 (((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \ 1678 HTT_RX_TID_STATS_TID_NUM_S) 1679 1680 #define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \ 1681 do { \ 1682 HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \ 1683 ((_var) |= ((_val) << HTT_RX_TID_STATS_TID_NUM_S)); \ 1684 } while (0) 1685 1686 typedef struct _htt_rx_tid_stats_tlv { 1687 htt_tlv_hdr_t tlv_hdr; 1688 1689 /** 1690 * BIT [15 : 0] : sw_peer_id 1691 * BIT [31 : 16] : tid_num 1692 */ 1693 A_UINT32 sw_peer_id__tid_num; 1694 /** Stored as little endian */ 1695 A_UINT8 tid_name[MAX_HTT_TID_NAME]; 1696 /** 1697 * dup_in_reorder not collected per tid for now, 1698 * as there is no wal_peer back ptr in data rx peer. 1699 */ 1700 A_UINT32 dup_in_reorder; 1701 A_UINT32 dup_past_outside_window; 1702 A_UINT32 dup_past_within_window; 1703 /** Number of per tid MSDUs with flag of decrypt_err */ 1704 A_UINT32 rxdesc_err_decrypt; 1705 /** tid rx airtime in sec */ 1706 A_UINT32 tid_rx_airtime; 1707 } htt_stats_rx_tid_details_tlv; 1708 /* preserve old name alias for new name consistent with the tag name */ 1709 typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv; 1710 1711 #define HTT_MAX_COUNTER_NAME 8 1712 typedef struct { 1713 htt_tlv_hdr_t tlv_hdr; 1714 /** Stored as little endian */ 1715 A_UINT8 counter_name[HTT_MAX_COUNTER_NAME]; 1716 A_UINT32 count; 1717 } htt_stats_counter_name_tlv; 1718 /* preserve old name alias for new name consistent with the tag name */ 1719 typedef htt_stats_counter_name_tlv htt_counter_tlv; 1720 1721 typedef struct { 1722 htt_tlv_hdr_t tlv_hdr; 1723 /** Number of rx PPDU */ 1724 A_UINT32 ppdu_cnt; 1725 /** Number of rx MPDU */ 1726 A_UINT32 mpdu_cnt; 1727 /** Number of rx MSDU */ 1728 A_UINT32 msdu_cnt; 1729 /** pause bitmap */ 1730 A_UINT32 pause_bitmap; 1731 /** block bitmap */ 1732 A_UINT32 block_bitmap; 1733 /** current timestamp */ 1734 A_UINT32 current_timestamp; 1735 /** Peer cumulative tx airtime in sec */ 1736 A_UINT32 peer_tx_airtime; 1737 /** Peer cumulative rx airtime in sec */ 1738 A_UINT32 peer_rx_airtime; 1739 /** Peer current rssi in dBm */ 1740 A_INT32 rssi; 1741 /** Total enqueued, dequeued and dropped MSDU's for peer */ 1742 A_UINT32 peer_enqueued_count_low; 1743 A_UINT32 peer_enqueued_count_high; 1744 A_UINT32 peer_dequeued_count_low; 1745 A_UINT32 peer_dequeued_count_high; 1746 A_UINT32 peer_dropped_count_low; 1747 A_UINT32 peer_dropped_count_high; 1748 /** Total ppdu transmitted bytes for peer: includes MAC header overhead */ 1749 A_UINT32 ppdu_transmitted_bytes_low; 1750 A_UINT32 ppdu_transmitted_bytes_high; 1751 A_UINT32 peer_ttl_removed_count; 1752 /** 1753 * inactive_time 1754 * Running duration of the time since last tx/rx activity by this peer, 1755 * units = seconds. 1756 * If the peer is currently active, this inactive_time will be 0x0. 1757 */ 1758 A_UINT32 inactive_time; 1759 /** Number of MPDUs dropped after max retries */ 1760 A_UINT32 remove_mpdus_max_retries; 1761 } htt_stats_peer_stats_cmn_tlv; 1762 /* preserve old name alias for new name consistent with the tag name */ 1763 typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; 1764 1765 #define HTT_PEER_DETAILS_ML_PEER_OFFSET_BYTES 32 1766 #define HTT_PEER_DETAILS_ML_PEER_OFFSET_DWORD 8 1767 #define HTT_PEER_DETAILS_ML_PEER_ID_VALID_M 0x00000001 1768 #define HTT_PEER_DETAILS_ML_PEER_ID_VALID_S 0 1769 #define HTT_PEER_DETAILS_ML_PEER_ID_M 0x00001ffe 1770 #define HTT_PEER_DETAILS_ML_PEER_ID_S 1 1771 #define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000 1772 #define HTT_PEER_DETAILS_LINK_IDX_S 13 1773 #define HTT_PEER_DETAILS_USE_PPE_M 0x00200000 1774 #define HTT_PEER_DETAILS_USE_PPE_S 21 1775 1776 1777 #define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff 1778 #define HTT_PEER_DETAILS_SRC_INFO_S 0 1779 1780 1781 #define HTT_PEER_DETAILS_SET(word, httsym, val) \ 1782 do { \ 1783 HTT_CHECK_SET_VAL(HTT_PEER_DETAILS_ ## httsym, val); \ 1784 (word) |= ((val) << HTT_PEER_DETAILS_ ## httsym ## _S); \ 1785 } while(0) 1786 1787 #define HTT_PEER_DETAILS_GET(word, httsym) \ 1788 (((word) & HTT_PEER_DETAILS_ ## httsym ## _M) >> HTT_PEER_DETAILS_ ## httsym ## _S) 1789 1790 typedef struct { 1791 htt_tlv_hdr_t tlv_hdr; 1792 /** This enum type of HTT_PEER_TYPE */ 1793 A_UINT32 peer_type; 1794 A_UINT32 sw_peer_id; 1795 /** 1796 * BIT [7 : 0] :- vdev_id 1797 * BIT [15 : 8] :- pdev_id 1798 * BIT [31 : 16] :- ast_indx 1799 */ 1800 A_UINT32 vdev_pdev_ast_idx; 1801 htt_mac_addr mac_addr; 1802 A_UINT32 peer_flags; 1803 A_UINT32 qpeer_flags; 1804 /* Dword 8 */ 1805 A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ 1806 ml_peer_id : 12, /* [12:1] */ 1807 link_idx : 8, /* [20:13] */ 1808 use_ppe : 1, /* [21:21] */ 1809 rsvd0 : 10; /* [31:22] */ 1810 /* Dword 9 */ 1811 A_UINT32 src_info : 12, /* [11:0] */ 1812 rsvd1 : 20; /* [31:12] */ 1813 } htt_stats_peer_details_tlv; 1814 /* preserve old name alias for new name consistent with the tag name */ 1815 typedef htt_stats_peer_details_tlv htt_peer_details_tlv; 1816 1817 typedef struct { 1818 htt_tlv_hdr_t tlv_hdr; 1819 A_UINT32 sw_peer_id; 1820 A_UINT32 ast_index; 1821 htt_mac_addr mac_addr; 1822 A_UINT32 1823 pdev_id : 2, 1824 vdev_id : 8, 1825 next_hop : 1, 1826 mcast : 1, 1827 monitor_direct : 1, 1828 mesh_sta : 1, 1829 mec : 1, 1830 intra_bss : 1, 1831 chip_id : 2, 1832 ml_peer_id : 13, 1833 on_chip : 1; 1834 A_UINT32 1835 tx_monitor_override_sta : 1, 1836 rx_monitor_override_sta : 1, 1837 reserved1 : 30; 1838 } htt_stats_ast_entry_tlv; 1839 /* preserve old name alias for new name consistent with the tag name */ 1840 typedef htt_stats_ast_entry_tlv htt_ast_entry_tlv; 1841 1842 typedef enum { 1843 HTT_STATS_DIRECTION_TX, 1844 HTT_STATS_DIRECTION_RX, 1845 } HTT_STATS_DIRECTION; 1846 1847 typedef enum { 1848 HTT_STATS_PPDU_TYPE_MODE_SU, 1849 HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1850 HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1851 HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1852 HTT_STATS_PPDU_TYPE_UL_MU_OFDMA, 1853 } HTT_STATS_PPDU_TYPE; 1854 1855 typedef enum { 1856 HTT_STATS_PREAM_OFDM, 1857 HTT_STATS_PREAM_CCK, 1858 HTT_STATS_PREAM_HT, 1859 HTT_STATS_PREAM_VHT, 1860 HTT_STATS_PREAM_HE, 1861 HTT_STATS_PREAM_EHT, 1862 HTT_STATS_PREAM_RSVD1, 1863 1864 HTT_STATS_PREAM_COUNT, 1865 } HTT_STATS_PREAM_TYPE; 1866 1867 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 1868 #define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 1869 /* HTT_TX_PEER_STATS_NUM_GI_COUNTERS: 1870 * GI Index 0: WHAL_GI_800 1871 * GI Index 1: WHAL_GI_400 1872 * GI Index 2: WHAL_GI_1600 1873 * GI Index 3: WHAL_GI_3200 1874 */ 1875 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 1876 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 1877 /* HTT_TX_PEER_STATS_NUM_BW_COUNTERS: 1878 * bw index 0: rssi_pri20_chain0 1879 * bw index 1: rssi_ext20_chain0 1880 * bw index 2: rssi_ext40_low20_chain0 1881 * bw index 3: rssi_ext40_high20_chain0 1882 */ 1883 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 1884 /* HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS: 1885 * bw index 4 (bw ext index 0): rssi_ext80_low20_chain0 1886 * bw index 5 (bw ext index 1): rssi_ext80_low_high20_chain0 1887 * bw index 6 (bw ext index 2): rssi_ext80_high_low20_chain0 1888 * bw index 7 (bw ext index 3): rssi_ext80_high20_chain0 1889 */ 1890 #define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4 1891 #define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 1892 1893 /* HTT_RX STATS_NUM_BW_EXT_2_COUNTERS: 1894 * bw index 8 (bw ext_2 index 0): rssi_ext160_0_chainX 1895 * bw index 9 (bw ext_2 index 1): rssi_ext160_1_chainX 1896 * bw index 10 (bw ext_2 index 2): rssi_ext160_2_chainX 1897 * bw index 11 (bw ext_2 index 3): rssi_ext160_3_chainX 1898 * bw index 12 (bw ext_2 index 4): rssi_ext160_4_chainX 1899 * bw index 13 (bw ext_2 index 5): rssi_ext160_5_chainX 1900 * bw index 14 (bw ext_2 index 6): rssi_ext160_6_chainX 1901 * bw index 15 (bw ext_2 index 7): rssi_ext160_7_chainX 1902 */ 1903 #define HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS 8 1904 1905 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 1906 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1907 #define HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 1908 1909 typedef struct _htt_tx_peer_rate_stats_tlv { 1910 htt_tlv_hdr_t tlv_hdr; 1911 1912 /** Number of tx LDPC packets */ 1913 A_UINT32 tx_ldpc; 1914 /** Number of tx RTS packets */ 1915 A_UINT32 rts_cnt; 1916 /** RSSI value of last ack packet (units = dB above noise floor) */ 1917 A_UINT32 ack_rssi; 1918 1919 A_UINT32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 1920 A_UINT32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 1921 A_UINT32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 1922 /** 1923 * element 0,1, ...7 -> NSS 1,2, ...8 1924 */ 1925 A_UINT32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 1926 /** 1927 * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz 1928 */ 1929 A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 1930 A_UINT32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 1931 A_UINT32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 1932 1933 /** 1934 * Counters to track number of tx packets in each GI 1935 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 1936 */ 1937 A_UINT32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 1938 1939 /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 1940 A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 1941 1942 /** Stats for MCS 12/13 */ 1943 A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 1944 A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 1945 A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 1946 A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 1947 A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 1948 A_UINT32 reduced_tx_bw[HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 1949 A_UINT32 tx_bw_320mhz; 1950 } htt_stats_peer_tx_rate_stats_tlv; 1951 /* preserve old name alias for new name consistent with the tag name */ 1952 typedef htt_stats_peer_tx_rate_stats_tlv htt_tx_peer_rate_stats_tlv; 1953 1954 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 1955 #define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 1956 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 1957 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 1958 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 1959 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 1960 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1961 #define HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 1962 1963 typedef struct _htt_rx_peer_rate_stats_tlv { 1964 htt_tlv_hdr_t tlv_hdr; 1965 A_UINT32 nsts; 1966 1967 /** Number of rx LDPC packets */ 1968 A_UINT32 rx_ldpc; 1969 /** Number of rx RTS packets */ 1970 A_UINT32 rts_cnt; 1971 1972 /** units = dB above noise floor */ 1973 A_UINT32 rssi_mgmt; 1974 /** units = dB above noise floor */ 1975 A_UINT32 rssi_data; 1976 /** units = dB above noise floor */ 1977 A_UINT32 rssi_comb; 1978 A_UINT32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 1979 /** 1980 * element 0,1, ...7 -> NSS 1,2, ...8 1981 */ 1982 A_UINT32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 1983 A_UINT32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 1984 A_UINT32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 1985 /** 1986 * element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz 1987 */ 1988 A_UINT32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 1989 A_UINT32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 1990 /** units = dB above noise floor */ 1991 A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 1992 1993 /** Counters to track number of rx packets in each GI in each mcs (0-11) */ 1994 A_UINT32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 1995 1996 A_UINT32 rx_ulofdma_non_data_ppdu; /** PPDU level */ 1997 A_UINT32 rx_ulofdma_data_ppdu; /** PPDU level */ 1998 A_UINT32 rx_ulofdma_mpdu_ok; /** MPDU level */ 1999 A_UINT32 rx_ulofdma_mpdu_fail; /** MPDU level */ 2000 A_INT8 rx_ul_fd_rssi[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* dBm unit */ 2001 /* per_chain_rssi_pkt_type: 2002 * This field shows what type of rx frame the per-chain RSSI was computed 2003 * on, by recording the frame type and sub-type as bit-fields within this 2004 * field: 2005 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 2006 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 2007 * BIT [31 : 8] :- Reserved 2008 */ 2009 A_UINT32 per_chain_rssi_pkt_type; 2010 A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2011 2012 /** PPDU level */ 2013 A_UINT32 rx_ulmumimo_non_data_ppdu; 2014 /** PPDU level */ 2015 A_UINT32 rx_ulmumimo_data_ppdu; 2016 /** MPDU level */ 2017 A_UINT32 rx_ulmumimo_mpdu_ok; 2018 /** mpdu level */ 2019 A_UINT32 rx_ulmumimo_mpdu_fail; 2020 2021 /** units = dB above noise floor */ 2022 A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; 2023 2024 /** Stats for MCS 12/13 */ 2025 A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2026 A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2027 A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; 2028 A_UINT32 reduced_rx_bw[HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 2029 A_INT8 rx_per_chain_rssi_in_dbm_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; 2030 } htt_stats_peer_rx_rate_stats_tlv; 2031 /* preserve old name alias for new name consistent with the tag name */ 2032 typedef htt_stats_peer_rx_rate_stats_tlv htt_rx_peer_rate_stats_tlv; 2033 2034 typedef enum { 2035 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 2036 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 2037 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 2038 } htt_peer_stats_req_mode_t; 2039 2040 typedef enum { 2041 HTT_PEER_STATS_CMN_TLV = 0, 2042 HTT_PEER_DETAILS_TLV = 1, 2043 HTT_TX_PEER_RATE_STATS_TLV = 2, 2044 HTT_RX_PEER_RATE_STATS_TLV = 3, 2045 HTT_TX_TID_STATS_TLV = 4, 2046 HTT_RX_TID_STATS_TLV = 5, 2047 HTT_MSDU_FLOW_STATS_TLV = 6, 2048 HTT_PEER_SCHED_STATS_TLV = 7, 2049 HTT_PEER_AX_OFDMA_STATS_TLV = 8, 2050 HTT_PEER_BE_OFDMA_STATS_TLV = 9, 2051 2052 HTT_PEER_STATS_MAX_TLV = 31, 2053 } htt_peer_stats_tlv_enum; 2054 2055 typedef struct { 2056 htt_tlv_hdr_t tlv_hdr; 2057 A_UINT32 peer_id; 2058 /** Num of DL schedules for peer */ 2059 A_UINT32 num_sched_dl; 2060 /** Num od UL schedules for peer */ 2061 A_UINT32 num_sched_ul; 2062 /** Peer TX time */ 2063 A_UINT32 peer_tx_active_dur_us_low; 2064 A_UINT32 peer_tx_active_dur_us_high; 2065 /** Peer RX time */ 2066 A_UINT32 peer_rx_active_dur_us_low; 2067 A_UINT32 peer_rx_active_dur_us_high; 2068 A_UINT32 peer_curr_rate_kbps; 2069 } htt_stats_peer_sched_stats_tlv; 2070 /* preserve old name alias for new name consistent with the tag name */ 2071 typedef htt_stats_peer_sched_stats_tlv htt_peer_sched_stats_tlv; 2072 2073 typedef struct { 2074 htt_tlv_hdr_t tlv_hdr; 2075 A_UINT32 peer_id; 2076 A_UINT32 ax_basic_trig_count; 2077 A_UINT32 ax_basic_trig_err; 2078 A_UINT32 ax_bsr_trig_count; 2079 A_UINT32 ax_bsr_trig_err; 2080 A_UINT32 ax_mu_bar_trig_count; 2081 A_UINT32 ax_mu_bar_trig_err; 2082 A_UINT32 ax_basic_trig_with_per; 2083 A_UINT32 ax_bsr_trig_with_per; 2084 A_UINT32 ax_mu_bar_trig_with_per; 2085 /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma 2086 * These fields contain 2 counters each. The first element in each 2087 * array counts how many times the airtime is short enough to use 2088 * OFDMA, and the second element in each array counts how many times the 2089 * airtime is too large to select OFDMA for the PPDUs involving the peer. 2090 */ 2091 A_UINT32 is_airtime_large_for_dl_ofdma[2]; 2092 A_UINT32 is_airtime_large_for_ul_ofdma[2]; 2093 /* Last updated value of DL and UL queue depths for each peer per AC */ 2094 A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; 2095 A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; 2096 /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ 2097 A_UINT32 ax_manual_ulofdma_trig_count; 2098 A_UINT32 ax_manual_ulofdma_trig_err_count; 2099 } htt_stats_peer_ax_ofdma_stats_tlv; 2100 /* preserve old name alias for new name consistent with the tag name */ 2101 typedef htt_stats_peer_ax_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; 2102 2103 typedef struct { 2104 htt_tlv_hdr_t tlv_hdr; 2105 A_UINT32 peer_id; 2106 /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */ 2107 A_UINT32 be_manual_ulofdma_trig_count; 2108 A_UINT32 be_manual_ulofdma_trig_err_count; 2109 } htt_stats_peer_be_ofdma_stats_tlv; 2110 /* preserve old name alias for new name consistent with the tag name */ 2111 typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv; 2112 2113 2114 /* config_param0 */ 2115 2116 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 2117 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S 0 2118 2119 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_GET(_var) \ 2120 (((_var) & HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M) >> \ 2121 HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S) 2122 2123 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET(_var, _val) \ 2124 do { \ 2125 HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR, _val); \ 2126 ((_var) |= ((_val) << HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S)); \ 2127 } while (0) 2128 /* DEPRECATED 2129 * The old IS_peer_MAC_ADDR_SET macro name is being retained for now, 2130 * as an alias for the corrected macro name. 2131 * If/when all references to the old name are removed, the definition of 2132 * the old name will also be removed. 2133 */ 2134 #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_peer_MAC_ADDR_SET HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET 2135 2136 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M 0x00000001 2137 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S 0 2138 2139 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_M 0x0000FFFE 2140 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_S 1 2141 2142 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M 0xFFFF0000 2143 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S 16 2144 2145 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(_var, _val) \ 2146 do { \ 2147 HTT_CHECK_SET_VAL(HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR, _val); \ 2148 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)); \ 2149 } while (0) 2150 2151 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_GET(_var) \ 2152 (((_var) & HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M) >> \ 2153 HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S) 2154 2155 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_GET(_var) \ 2156 (((_var) & HTT_DBG_EXT_STATS_PEER_REQ_MODE_M) >> \ 2157 HTT_DBG_EXT_STATS_PEER_REQ_MODE_S) 2158 2159 #define HTT_DBG_EXT_STATS_PEER_REQ_MODE_SET(_var, _val) \ 2160 do { \ 2161 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)); \ 2162 } while (0) 2163 2164 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_GET(_var) \ 2165 (((_var) & HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M) >> \ 2166 HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S) 2167 2168 #define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_SET(_var, _val) \ 2169 do { \ 2170 ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)); \ 2171 } while (0) 2172 2173 /* STATS_TYPE : HTT_DBG_EXT_STATS_PEER_INFO 2174 * TLV_TAGS: 2175 * - HTT_STATS_PEER_STATS_CMN_TAG 2176 * - HTT_STATS_PEER_DETAILS_TAG 2177 * - HTT_STATS_PEER_TX_RATE_STATS_TAG 2178 * - HTT_STATS_PEER_RX_RATE_STATS_TAG 2179 * - HTT_STATS_TX_TID_DETAILS_TAG (multiple) (deprecated, so 0 elements in updated systems) 2180 * - HTT_STATS_RX_TID_DETAILS_TAG (multiple) 2181 * - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple) 2182 * - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple) 2183 * - HTT_STATS_PEER_SCHED_STATS_TAG 2184 * - HTT_STATS_PEER_AX_OFDMA_STATS_TAG 2185 */ 2186 /* NOTE: 2187 * This structure is for documentation, and cannot be safely used directly. 2188 * Instead, use the constituent TLV structures to fill/parse. 2189 */ 2190 typedef struct _htt_peer_stats { 2191 htt_stats_peer_stats_cmn_tlv cmn_tlv; 2192 2193 htt_stats_peer_details_tlv peer_details; 2194 /* from g_rate_info_stats */ 2195 htt_stats_peer_tx_rate_stats_tlv tx_rate; 2196 htt_stats_peer_rx_rate_stats_tlv rx_rate; 2197 htt_stats_tx_tid_details_tlv tx_tid_stats[1]; 2198 htt_stats_rx_tid_details_tlv rx_tid_stats[1]; 2199 htt_stats_peer_msdu_flowq_tlv msdu_flowq[1]; 2200 htt_stats_tx_tid_details_v1_tlv tx_tid_stats_v1[1]; 2201 htt_stats_peer_sched_stats_tlv peer_sched_stats; 2202 htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; 2203 htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; 2204 } htt_peer_stats_t; 2205 2206 /* =========== ACTIVE PEER LIST ========== */ 2207 2208 /* STATS_TYPE: HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST 2209 * TLV_TAGS: 2210 * - HTT_STATS_PEER_DETAILS_TAG 2211 */ 2212 /* NOTE: 2213 * This structure is for documentation, and cannot be safely used directly. 2214 * Instead, use the constituent TLV structures to fill/parse. 2215 */ 2216 typedef struct { 2217 htt_stats_peer_details_tlv peer_details[1]; 2218 } htt_active_peer_details_list_t; 2219 2220 /* =========== MUMIMO HWQ stats =========== */ 2221 2222 /* MU MIMO stats per hwQ */ 2223 typedef struct { 2224 htt_tlv_hdr_t tlv_hdr; 2225 /** number of MU MIMO schedules posted to HW */ 2226 A_UINT32 mu_mimo_sch_posted; 2227 /** number of MU MIMO schedules failed to post */ 2228 A_UINT32 mu_mimo_sch_failed; 2229 /** number of MU MIMO PPDUs posted to HW */ 2230 A_UINT32 mu_mimo_ppdu_posted; 2231 } htt_stats_tx_hwq_mumimo_sch_stats_tlv; 2232 /* preserve old name alias for new name consistent with the tag name */ 2233 typedef htt_stats_tx_hwq_mumimo_sch_stats_tlv htt_tx_hwq_mu_mimo_sch_stats_tlv; 2234 2235 typedef struct { 2236 htt_tlv_hdr_t tlv_hdr; 2237 /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ 2238 A_UINT32 mu_mimo_mpdus_queued_usr; 2239 /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ 2240 A_UINT32 mu_mimo_mpdus_tried_usr; 2241 /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ 2242 A_UINT32 mu_mimo_mpdus_failed_usr; 2243 /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ 2244 A_UINT32 mu_mimo_mpdus_requeued_usr; 2245 /** 11AC DL MU MIMO BA not received, per user */ 2246 A_UINT32 mu_mimo_err_no_ba_usr; 2247 /** 11AC DL MU MIMO mpdu underrun encountered, per user */ 2248 A_UINT32 mu_mimo_mpdu_underrun_usr; 2249 /** 11AC DL MU MIMO ampdu underrun encountered, per user */ 2250 A_UINT32 mu_mimo_ampdu_underrun_usr; 2251 } htt_stats_tx_hwq_mumimo_mpdu_stats_tlv; 2252 /* preserve old name alias for new name consistent with the tag name */ 2253 typedef htt_stats_tx_hwq_mumimo_mpdu_stats_tlv 2254 htt_tx_hwq_mu_mimo_mpdu_stats_tlv; 2255 2256 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M 0x000000ff 2257 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S 0 2258 2259 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M 0x0000ff00 2260 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S 8 2261 2262 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_GET(_var) \ 2263 (((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M) >> \ 2264 HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S) 2265 2266 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_SET(_var, _val) \ 2267 do { \ 2268 HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID, _val); \ 2269 ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)); \ 2270 } while (0) 2271 2272 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_GET(_var) \ 2273 (((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M) >> \ 2274 HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S) 2275 2276 #define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_SET(_var, _val) \ 2277 do { \ 2278 HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID, _val); \ 2279 ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)); \ 2280 } while (0) 2281 2282 typedef struct { 2283 htt_tlv_hdr_t tlv_hdr; 2284 2285 /** 2286 * BIT [ 7 : 0] :- mac_id 2287 * BIT [15 : 8] :- hwq_id 2288 * BIT [31 : 16] :- reserved 2289 */ 2290 A_UINT32 mac_id__hwq_id__word; 2291 } htt_stats_tx_hwq_mumimo_cmn_stats_tlv; 2292 /* preserve old name alias for new name consistent with the tag name */ 2293 typedef htt_stats_tx_hwq_mumimo_cmn_stats_tlv htt_tx_hwq_mu_mimo_cmn_stats_tlv; 2294 2295 /* NOTE: 2296 * This structure is for documentation, and cannot be safely used directly. 2297 * Instead, use the constituent TLV structures to fill/parse. 2298 */ 2299 typedef struct { 2300 struct { 2301 htt_stats_tx_hwq_mumimo_cmn_stats_tlv cmn_tlv; 2302 /** WAL_TX_STATS_MAX_GROUP_SIZE */ 2303 htt_stats_tx_hwq_mumimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; 2304 /** WAL_TX_STATS_TX_MAX_NUM_USERS */ 2305 htt_stats_tx_hwq_mumimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; 2306 } hwq[1]; 2307 } htt_tx_hwq_mu_mimo_stats_t; 2308 2309 /* == TX HWQ STATS == */ 2310 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_M 0x000000ff 2311 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_S 0 2312 2313 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_M 0x0000ff00 2314 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_S 8 2315 2316 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_GET(_var) \ 2317 (((_var) & HTT_TX_HWQ_STATS_CMN_MAC_ID_M) >> \ 2318 HTT_TX_HWQ_STATS_CMN_MAC_ID_S) 2319 2320 #define HTT_TX_HWQ_STATS_CMN_MAC_ID_SET(_var, _val) \ 2321 do { \ 2322 HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_MAC_ID, _val); \ 2323 ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_MAC_ID_S)); \ 2324 } while (0) 2325 2326 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_GET(_var) \ 2327 (((_var) & HTT_TX_HWQ_STATS_CMN_HWQ_ID_M) >> \ 2328 HTT_TX_HWQ_STATS_CMN_HWQ_ID_S) 2329 2330 #define HTT_TX_HWQ_STATS_CMN_HWQ_ID_SET(_var, _val) \ 2331 do { \ 2332 HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_HWQ_ID, _val); \ 2333 ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)); \ 2334 } while (0) 2335 2336 typedef struct { 2337 htt_tlv_hdr_t tlv_hdr; 2338 2339 /** 2340 * BIT [ 7 : 0] :- mac_id 2341 * BIT [15 : 8] :- hwq_id 2342 * BIT [31 : 16] :- reserved 2343 */ 2344 A_UINT32 mac_id__hwq_id__word; 2345 2346 /*--- PPDU level stats */ 2347 /** Number of times ack is failed for the PPDU scheduled on this txQ */ 2348 A_UINT32 xretry; 2349 /** Number of times sched cmd status reported mpdu underrun */ 2350 A_UINT32 underrun_cnt; 2351 /** Number of times sched cmd is flushed */ 2352 A_UINT32 flush_cnt; 2353 /** Number of times sched cmd is filtered */ 2354 A_UINT32 filt_cnt; 2355 /** Number of times HWSCH uploaded null mpdu bitmap */ 2356 A_UINT32 null_mpdu_bmap; 2357 /** 2358 * Number of times user ack or BA TLV is not seen on FES ring 2359 * where it is expected to be 2360 */ 2361 A_UINT32 user_ack_failure; 2362 /** Number of times TQM processed ack TLV received from HWSCH */ 2363 A_UINT32 ack_tlv_proc; 2364 /** Cache latest processed scheduler ID received from ack BA TLV */ 2365 A_UINT32 sched_id_proc; 2366 /** Number of times TxPCU reported MPDUs transmitted for a user is zero */ 2367 A_UINT32 null_mpdu_tx_count; 2368 /** 2369 * Number of times SW did not see any MPDU info bitmap TLV 2370 * on FES status ring 2371 */ 2372 A_UINT32 mpdu_bmap_not_recvd; 2373 2374 /*--- Selfgen stats per hwQ */ 2375 /** Number of SU/MU BAR frames posted to hwQ */ 2376 A_UINT32 num_bar; 2377 /** Number of RTS frames posted to hwQ */ 2378 A_UINT32 rts; 2379 /** Number of cts2self frames posted to hwQ */ 2380 A_UINT32 cts2self; 2381 /** Number of qos null frames posted to hwQ */ 2382 A_UINT32 qos_null; 2383 2384 /*--- MPDU level stats */ 2385 /** mpdus tried Tx by HWSCH/TQM */ 2386 A_UINT32 mpdu_tried_cnt; 2387 /** mpdus queued to HWSCH */ 2388 A_UINT32 mpdu_queued_cnt; 2389 /** mpdus tried but ack was not received */ 2390 A_UINT32 mpdu_ack_fail_cnt; 2391 /** This will include sched cmd flush and time based discard */ 2392 A_UINT32 mpdu_filt_cnt; 2393 /** Number of MPDUs for which ACK was successful but no Tx happened */ 2394 A_UINT32 false_mpdu_ack_count; 2395 2396 /** Number of times txq timeout happened */ 2397 A_UINT32 txq_timeout; 2398 } htt_stats_tx_hwq_cmn_tlv; 2399 /* preserve old name alias for new name consistent with the tag name */ 2400 typedef htt_stats_tx_hwq_cmn_tlv htt_tx_hwq_stats_cmn_tlv; 2401 2402 #define HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) + /* hist_intvl */ \ 2403 (sizeof(A_UINT32) * (_num_elems))) 2404 /* NOTE: Variable length TLV, use length spec to infer array size */ 2405 typedef struct { 2406 htt_tlv_hdr_t tlv_hdr; 2407 A_UINT32 hist_intvl; 2408 /** histogram of ppdu post to hwsch - > cmd status received */ 2409 A_UINT32 difs_latency_hist[1]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ 2410 } htt_stats_tx_hwq_difs_latency_tlv; 2411 /* preserve old name alias for new name consistent with the tag name */ 2412 typedef htt_stats_tx_hwq_difs_latency_tlv htt_tx_hwq_difs_latency_stats_tlv_v; 2413 2414 #define HTT_TX_HWQ_CMD_RESULT_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2415 2416 /* NOTE: Variable length TLV, use length spec to infer array size */ 2417 typedef struct { 2418 htt_tlv_hdr_t tlv_hdr; 2419 /** Histogram of sched cmd result */ 2420 A_UINT32 cmd_result[1]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ 2421 } htt_stats_tx_hwq_cmd_result_tlv; 2422 /* preserve old name alias for new name consistent with the tag name */ 2423 typedef htt_stats_tx_hwq_cmd_result_tlv htt_tx_hwq_cmd_result_stats_tlv_v; 2424 2425 #define HTT_TX_HWQ_CMD_STALL_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2426 2427 /* NOTE: Variable length TLV, use length spec to infer array size */ 2428 typedef struct { 2429 htt_tlv_hdr_t tlv_hdr; 2430 /** Histogram of various pause conitions */ 2431 A_UINT32 cmd_stall_status[1]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ 2432 } htt_stats_tx_hwq_cmd_stall_tlv; 2433 /* preserve old name alias for new name consistent with the tag name */ 2434 typedef htt_stats_tx_hwq_cmd_stall_tlv htt_tx_hwq_cmd_stall_stats_tlv_v; 2435 2436 #define HTT_TX_HWQ_FES_RESULT_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2437 2438 /* NOTE: Variable length TLV, use length spec to infer array size */ 2439 typedef struct { 2440 htt_tlv_hdr_t tlv_hdr; 2441 /** Histogram of number of user fes result */ 2442 A_UINT32 fes_result[1]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ 2443 } htt_stats_tx_hwq_fes_status_tlv; 2444 /* preserve old name alias for new name consistent with the tag name */ 2445 typedef htt_stats_tx_hwq_fes_status_tlv htt_tx_hwq_fes_result_stats_tlv_v; 2446 2447 #define HTT_TX_HWQ_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2448 /* NOTE: Variable length TLV, use length spec to infer array size 2449 * 2450 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 2451 * The tries here is the count of the MPDUS within a PPDU that the HW 2452 * had attempted to transmit on air, for the HWSCH Schedule command 2453 * submitted by FW in this HWQ .It is not the retry attempts. The 2454 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 2455 * in this histogram. 2456 * they are defined in FW using the following macros 2457 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 2458 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 2459 * 2460 * */ 2461 typedef struct { 2462 htt_tlv_hdr_t tlv_hdr; 2463 A_UINT32 hist_bin_size; 2464 /** Histogram of number of mpdus on tried mpdu */ 2465 A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ 2466 } htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv; 2467 /* preserve old name alias for new name consistent with the tag name */ 2468 typedef htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv 2469 htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v; 2470 2471 #define HTT_TX_HWQ_TXOP_USED_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 2472 /* NOTE: Variable length TLV, use length spec to infer array size 2473 * 2474 * The txop_used_cnt_hist is the histogram of txop per burst. After 2475 * completing the burst, we identify the txop used in the burst and 2476 * incr the corresponding bin. 2477 * Each bin represents 1ms & we have 10 bins in this histogram. 2478 * they are defined in FW using the following macros 2479 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 2480 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 2481 * 2482 * */ 2483 typedef struct { 2484 htt_tlv_hdr_t tlv_hdr; 2485 /** Histogram of txop used cnt */ 2486 A_UINT32 txop_used_cnt_hist[1]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ 2487 } htt_stats_tx_hwq_txop_used_cnt_hist_tlv; 2488 /* preserve old name alias for new name consistent with the tag name */ 2489 typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv 2490 htt_tx_hwq_txop_used_cnt_hist_tlv_v; 2491 2492 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_HWQ 2493 * TLV_TAGS: 2494 * - HTT_STATS_STRING_TAG 2495 * - HTT_STATS_TX_HWQ_CMN_TAG 2496 * - HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG 2497 * - HTT_STATS_TX_HWQ_CMD_RESULT_TAG 2498 * - HTT_STATS_TX_HWQ_CMD_STALL_TAG 2499 * - HTT_STATS_TX_HWQ_FES_STATUS_TAG 2500 * - HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG 2501 * - HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG 2502 */ 2503 /* NOTE: 2504 * This structure is for documentation, and cannot be safely used directly. 2505 * Instead, use the constituent TLV structures to fill/parse. 2506 * General HWQ stats Mechanism: 2507 * Once the host request for the stats, FW fill all the HWQ TAGS in a buffer 2508 * for all the HWQ requested. & the FW send the buffer to host. In the 2509 * buffer the HWQ ID is filled in mac_id__hwq_id, thus identifying each 2510 * HWQ distinctly. 2511 */ 2512 typedef struct _htt_tx_hwq_stats { 2513 htt_stats_string_tlv hwq_str_tlv; 2514 htt_stats_tx_hwq_cmn_tlv cmn_tlv; 2515 htt_stats_tx_hwq_difs_latency_tlv difs_tlv; 2516 htt_stats_tx_hwq_cmd_result_tlv cmd_result_tlv; 2517 htt_stats_tx_hwq_cmd_stall_tlv cmd_stall_tlv; 2518 htt_stats_tx_hwq_fes_status_tlv fes_stats_tlv; 2519 htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv tried_mpdu_tlv; 2520 htt_stats_tx_hwq_txop_used_cnt_hist_tlv txop_used_tlv; 2521 } htt_tx_hwq_stats_t; 2522 2523 /* == TX SELFGEN STATS == */ 2524 2525 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M 0x000000ff 2526 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S 0 2527 2528 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_GET(_var) \ 2529 (((_var) & HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M) >> \ 2530 HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S) 2531 2532 #define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_SET(_var, _val) \ 2533 do { \ 2534 HTT_CHECK_SET_VAL(HTT_TX_SELFGEN_CMN_STATS_MAC_ID, _val); \ 2535 ((_var) |= ((_val) << HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)); \ 2536 } while (0) 2537 2538 typedef enum { 2539 HTT_TXERR_NONE, 2540 HTT_TXERR_RESP, /* response timeout, mismatch, 2541 * BW mismatch, mimo ctrl mismatch, 2542 * CRC error.. */ 2543 HTT_TXERR_FILT, /* blocked by tx filtering */ 2544 HTT_TXERR_FIFO, /* fifo, misc errors in HW */ 2545 HTT_TXERR_SWABORT, /* software initialted abort (TX_ABORT) */ 2546 2547 HTT_TXERR_RESERVED1, 2548 HTT_TXERR_RESERVED2, 2549 HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS = 7, 2550 2551 HTT_TXERR_INVALID = 0xff, 2552 } htt_tx_err_status_t; 2553 2554 2555 /* Matching enum for htt_tx_selfgen_sch_tsflag_error_stats */ 2556 typedef enum { 2557 HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 2558 HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 2559 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 2560 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 2561 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 2562 HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 2563 HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 2564 HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 2565 2566 HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS = 8, 2567 HTT_TX_SELFGEN_SCH_TSFLAG_ERROR_STATS_VALID = 8 2568 } htt_tx_selfgen_sch_tsflag_error_stats; 2569 2570 typedef enum { 2571 HTT_TX_MUMIMO_GRP_VALID, 2572 HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 2573 HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 2574 HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 2575 HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 2576 HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 2577 HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 2578 HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 2579 HTT_TX_MUMIMO_GRP_INVALID, 2580 HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 2581 HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 2582 } htt_tx_mumimo_grp_invalid_reason_code_stats; 2583 2584 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 2585 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 2586 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8 2587 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 2588 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 2589 #define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 2590 /* 2591 * Each bin represents a 300 mbps throughput 2592 * [0] - 0-300mbps; [1] - 300-600mbps [2] - 600-900mbps; [3] - 900-1200mbps; [4] - 1200-1500mbps 2593 * [5] - 1500-1800mbps; [6] - 1800-2100mbps; [7] - 2100-2400mbps; [8] - 2400-2700mbps; [9] - >=2700mbps 2594 */ 2595 #define HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 2596 #define HTT_STATS_MAX_INVALID_REASON_CODE \ 2597 HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 2598 /* Reasons stated in htt_tx_mumimo_grp_invalid_reason_code_stats */ 2599 #define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 2600 (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE) 2601 2602 #define HTT_MAX_NUM_SBT_INTR 4 2603 2604 typedef struct { 2605 htt_tlv_hdr_t tlv_hdr; 2606 2607 /* 2608 * BIT [ 7 : 0] :- mac_id 2609 * BIT [31 : 8] :- reserved 2610 */ 2611 A_UINT32 mac_id__word; 2612 /** BAR sent out for SU transmission */ 2613 A_UINT32 su_bar; 2614 /** SW generated RTS frame sent */ 2615 A_UINT32 rts; 2616 /** SW generated CTS-to-self frame sent */ 2617 A_UINT32 cts2self; 2618 /** SW generated QOS NULL frame sent */ 2619 A_UINT32 qos_null; 2620 /** BAR sent for MU user 1 */ 2621 A_UINT32 delayed_bar_1; 2622 /** BAR sent for MU user 2 */ 2623 A_UINT32 delayed_bar_2; 2624 /** BAR sent for MU user 3 */ 2625 A_UINT32 delayed_bar_3; 2626 /** BAR sent for MU user 4 */ 2627 A_UINT32 delayed_bar_4; 2628 /** BAR sent for MU user 5 */ 2629 A_UINT32 delayed_bar_5; 2630 /** BAR sent for MU user 6 */ 2631 A_UINT32 delayed_bar_6; 2632 /** BAR sent for MU user 7 */ 2633 A_UINT32 delayed_bar_7; 2634 A_UINT32 bar_with_tqm_head_seq_num; 2635 A_UINT32 bar_with_tid_seq_num; 2636 /** SW generated RTS frame queued to the HW */ 2637 A_UINT32 su_sw_rts_queued; 2638 /** SW generated RTS frame sent over the air */ 2639 A_UINT32 su_sw_rts_tried; 2640 /** SW generated RTS frame completed with error */ 2641 A_UINT32 su_sw_rts_err; 2642 /** SW generated RTS frame flushed */ 2643 A_UINT32 su_sw_rts_flushed; 2644 /** CTS (RTS response) received in different BW */ 2645 A_UINT32 su_sw_rts_rcvd_cts_diff_bw; 2646 /* START DEPRECATED FIELDS */ 2647 /** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */ 2648 A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2649 /** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */ 2650 A_UINT32 combined_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2651 /** 11AX HE MU Standalone Freq. BSRP Trigger frame sent over the air */ 2652 A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2653 /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ 2654 A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2655 /* END DEPRECATED FIELDS */ 2656 /** smart_basic_trig_sch_histogram: 2657 * Count how many times the interval between predictive basic triggers 2658 * sent to a given STA based on analysis of that STA's traffic patterns 2659 * is within a given range: 2660 * 2661 * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms 2662 * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms 2663 * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms 2664 * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms 2665 * 2666 * (Smart basic triggers are only used with intervals <= 40 ms.) 2667 */ 2668 A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; 2669 } htt_stats_tx_selfgen_cmn_stats_tlv; 2670 /* preserve old name alias for new name consistent with the tag name */ 2671 typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv; 2672 2673 typedef struct { 2674 htt_tlv_hdr_t tlv_hdr; 2675 /** 11AC VHT SU NDPA frame sent over the air */ 2676 A_UINT32 ac_su_ndpa; 2677 /** 11AC VHT SU NDP frame sent over the air */ 2678 A_UINT32 ac_su_ndp; 2679 /** 11AC VHT MU MIMO NDPA frame sent over the air */ 2680 A_UINT32 ac_mu_mimo_ndpa; 2681 /** 11AC VHT MU MIMO NDP frame sent over the air */ 2682 A_UINT32 ac_mu_mimo_ndp; 2683 /** 11AC VHT MU MIMO BR-POLL for user 1 sent over the air */ 2684 A_UINT32 ac_mu_mimo_brpoll_1; 2685 /** 11AC VHT MU MIMO BR-POLL for user 2 sent over the air */ 2686 A_UINT32 ac_mu_mimo_brpoll_2; 2687 /** 11AC VHT MU MIMO BR-POLL for user 3 sent over the air */ 2688 A_UINT32 ac_mu_mimo_brpoll_3; 2689 /** 11AC VHT SU NDPA frame queued to the HW */ 2690 A_UINT32 ac_su_ndpa_queued; 2691 /** 11AC VHT SU NDP frame queued to the HW */ 2692 A_UINT32 ac_su_ndp_queued; 2693 /** 11AC VHT MU MIMO NDPA frame queued to the HW */ 2694 A_UINT32 ac_mu_mimo_ndpa_queued; 2695 /** 11AC VHT MU MIMO NDP frame queued to the HW */ 2696 A_UINT32 ac_mu_mimo_ndp_queued; 2697 /** 11AC VHT MU MIMO BR-POLL for user 1 frame queued to the HW */ 2698 A_UINT32 ac_mu_mimo_brpoll_1_queued; 2699 /** 11AC VHT MU MIMO BR-POLL for user 2 frame queued to the HW */ 2700 A_UINT32 ac_mu_mimo_brpoll_2_queued; 2701 /** 11AC VHT MU MIMO BR-POLL for user 3 frame queued to the HW */ 2702 A_UINT32 ac_mu_mimo_brpoll_3_queued; 2703 } htt_stats_tx_selfgen_ac_stats_tlv; 2704 /* preserve old name alias for new name consistent with the tag name */ 2705 typedef htt_stats_tx_selfgen_ac_stats_tlv htt_tx_selfgen_ac_stats_tlv; 2706 2707 typedef struct { 2708 htt_tlv_hdr_t tlv_hdr; 2709 /** 11AX HE SU NDPA frame sent over the air */ 2710 A_UINT32 ax_su_ndpa; 2711 /** 11AX HE NDP frame sent over the air */ 2712 A_UINT32 ax_su_ndp; 2713 /** 11AX HE MU MIMO NDPA frame sent over the air */ 2714 A_UINT32 ax_mu_mimo_ndpa; 2715 /** 11AX HE MU MIMO NDP frame sent over the air */ 2716 A_UINT32 ax_mu_mimo_ndp; 2717 union { 2718 struct { 2719 /* deprecated old names */ 2720 A_UINT32 ax_mu_mimo_brpoll_1; 2721 A_UINT32 ax_mu_mimo_brpoll_2; 2722 A_UINT32 ax_mu_mimo_brpoll_3; 2723 A_UINT32 ax_mu_mimo_brpoll_4; 2724 A_UINT32 ax_mu_mimo_brpoll_5; 2725 A_UINT32 ax_mu_mimo_brpoll_6; 2726 A_UINT32 ax_mu_mimo_brpoll_7; 2727 }; 2728 /** 11AX HE MU BR-POLL frame for users 1 - 7 sent over the air */ 2729 A_UINT32 ax_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 2730 }; 2731 /** 11AX HE MU Basic Trigger frame sent over the air */ 2732 A_UINT32 ax_basic_trigger; 2733 /** 11AX HE MU BSRP Trigger frame sent over the air */ 2734 A_UINT32 ax_bsr_trigger; 2735 /** 11AX HE MU BAR Trigger frame sent over the air */ 2736 A_UINT32 ax_mu_bar_trigger; 2737 /** 11AX HE MU RTS Trigger frame sent over the air */ 2738 A_UINT32 ax_mu_rts_trigger; 2739 /** 11AX HE MU UL-MUMIMO Trigger frame sent over the air */ 2740 A_UINT32 ax_ulmumimo_trigger; 2741 /** 11AX HE SU NDPA frame queued to the HW */ 2742 A_UINT32 ax_su_ndpa_queued; 2743 /** 11AX HE SU NDP frame queued to the HW */ 2744 A_UINT32 ax_su_ndp_queued; 2745 /** 11AX HE MU MIMO NDPA frame queued to the HW */ 2746 A_UINT32 ax_mu_mimo_ndpa_queued; 2747 /** 11AX HE MU MIMO NDP frame queued to the HW */ 2748 A_UINT32 ax_mu_mimo_ndp_queued; 2749 /** 11AX HE MU BR-POLL frame for users 1 - 7 queued to the HW */ 2750 A_UINT32 ax_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 2751 /** 2752 * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 2753 * successfully sent over the air 2754 */ 2755 A_UINT32 ax_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 2756 /** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */ 2757 A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2758 /** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */ 2759 A_UINT32 combined_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2760 /** 11AX HE MU Standalone Freq. BSRP Trigger frame sent over the air */ 2761 A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2762 /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ 2763 A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; 2764 /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */ 2765 A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2766 /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */ 2767 A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2768 /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */ 2769 A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2770 /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ 2771 A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2772 /** 11AX HE UL OFDMA Basic Trigger frames per AC */ 2773 A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM]; 2774 /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */ 2775 A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2776 /** 11AX HE MU-BAR Trigger frames per AC */ 2777 A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; 2778 /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ 2779 A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2780 } htt_stats_tx_selfgen_ax_stats_tlv; 2781 /* preserve old name alias for new name consistent with the tag name */ 2782 typedef htt_stats_tx_selfgen_ax_stats_tlv htt_tx_selfgen_ax_stats_tlv; 2783 2784 typedef struct { 2785 htt_tlv_hdr_t tlv_hdr; 2786 /** 11be EHT SU NDPA frame sent over the air */ 2787 A_UINT32 be_su_ndpa; 2788 /** 11be EHT NDP frame sent over the air */ 2789 A_UINT32 be_su_ndp; 2790 /** 11be EHT MU MIMO NDPA frame sent over the air */ 2791 A_UINT32 be_mu_mimo_ndpa; 2792 /** 11be EHT MU MIMO NDP frame sent over theT air */ 2793 A_UINT32 be_mu_mimo_ndp; 2794 /** 11be EHT MU BR-POLL frame for users 1 - 7 sent over the air */ 2795 A_UINT32 be_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 2796 /** 11be EHT MU Basic Trigger frame sent over the air */ 2797 A_UINT32 be_basic_trigger; 2798 /** 11be EHT MU BSRP Trigger frame sent over the air */ 2799 A_UINT32 be_bsr_trigger; 2800 /** 11be EHT MU BAR Trigger frame sent over the air */ 2801 A_UINT32 be_mu_bar_trigger; 2802 /** 11be EHT MU RTS Trigger frame sent over the air */ 2803 A_UINT32 be_mu_rts_trigger; 2804 /** 11be EHT MU UL-MUMIMO Trigger frame sent over the air */ 2805 A_UINT32 be_ulmumimo_trigger; 2806 /** 11be EHT SU NDPA frame queued to the HW */ 2807 A_UINT32 be_su_ndpa_queued; 2808 /** 11be EHT SU NDP frame queued to the HW */ 2809 A_UINT32 be_su_ndp_queued; 2810 /** 11be EHT MU MIMO NDPA frame queued to the HW */ 2811 A_UINT32 be_mu_mimo_ndpa_queued; 2812 /** 11be EHT MU MIMO NDP frame queued to the HW */ 2813 A_UINT32 be_mu_mimo_ndp_queued; 2814 /** 11be EHT MU BR-POLL frame for users 1 - 7 queued to the HW */ 2815 A_UINT32 be_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 2816 /** 2817 * 11be EHT UL-MUMIMO Trigger frame for users 0 - 7 2818 * successfully sent over the air 2819 */ 2820 A_UINT32 be_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 2821 /** 11BE EHT MU Combined Freq. BSRP Trigger frame sent over the air */ 2822 A_UINT32 combined_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2823 /** 11BE EHT MU Combined Freq. BSRP Trigger completed with error(s) */ 2824 A_UINT32 combined_be_bsr_trigger_err[HTT_NUM_AC_WMM]; 2825 /** 11BE EHT MU Standalone Freq. BSRP Trigger frame sent over the air */ 2826 A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; 2827 /** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */ 2828 A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM]; 2829 /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */ 2830 A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2831 /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */ 2832 A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2833 /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */ 2834 A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; 2835 /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ 2836 A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; 2837 /** 11BE EHT UL OFDMA Basic Trigger frames per AC */ 2838 A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM]; 2839 /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */ 2840 A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2841 /** 11BE EHT MU-BAR Trigger frames per AC */ 2842 A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; 2843 /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ 2844 A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; 2845 } htt_stats_tx_selfgen_be_stats_tlv; 2846 /* preserve old name alias for new name consistent with the tag name */ 2847 typedef htt_stats_tx_selfgen_be_stats_tlv htt_tx_selfgen_be_stats_tlv; 2848 2849 typedef struct { /* DEPRECATED */ 2850 htt_tlv_hdr_t tlv_hdr; 2851 /** 11AX HE OFDMA NDPA frame queued to the HW */ 2852 A_UINT32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2853 /** 11AX HE OFDMA NDPA frame sent over the air */ 2854 A_UINT32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2855 /** 11AX HE OFDMA NDPA frame flushed by HW */ 2856 A_UINT32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2857 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 2858 A_UINT32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2859 } htt_stats_txbf_ofdma_ndpa_stats_tlv; 2860 /* preserve old name alias for new name consistent with the tag name */ 2861 typedef htt_stats_txbf_ofdma_ndpa_stats_tlv htt_txbf_ofdma_ndpa_stats_tlv; 2862 2863 typedef struct { /* DEPRECATED */ 2864 htt_tlv_hdr_t tlv_hdr; 2865 /** 11AX HE OFDMA NDP frame queued to the HW */ 2866 A_UINT32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2867 /** 11AX HE OFDMA NDPA frame sent over the air */ 2868 A_UINT32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2869 /** 11AX HE OFDMA NDPA frame flushed by HW */ 2870 A_UINT32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2871 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 2872 A_UINT32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2873 } htt_stats_txbf_ofdma_ndp_stats_tlv; 2874 /* preserve old name alias for new name consistent with the tag name */ 2875 typedef htt_stats_txbf_ofdma_ndp_stats_tlv htt_txbf_ofdma_ndp_stats_tlv; 2876 2877 typedef struct { /* DEPRECATED */ 2878 htt_tlv_hdr_t tlv_hdr; 2879 /** 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 2880 A_UINT32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2881 /** 11AX HE OFDMA MU BRPOLL frame sent over the air */ 2882 A_UINT32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2883 /** 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 2884 A_UINT32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2885 /** 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 2886 A_UINT32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2887 /** 2888 * Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 2889 * completed with error(s) 2890 */ 2891 A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS+1]; 2892 } htt_stats_txbf_ofdma_brp_stats_tlv; 2893 /* preserve old name alias for new name consistent with the tag name */ 2894 typedef htt_stats_txbf_ofdma_brp_stats_tlv htt_txbf_ofdma_brp_stats_tlv; 2895 2896 typedef struct { /* DEPRECATED */ 2897 htt_tlv_hdr_t tlv_hdr; 2898 /** 2899 * 11AX HE OFDMA PPDUs that were sent over the air with steering 2900 * (TXBF + OFDMA) 2901 */ 2902 A_UINT32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2903 /** 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 2904 A_UINT32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2905 /** 2906 * 11AX HE OFDMA number of users for which CBF prefetch was initiated 2907 * to PHY HW during TX 2908 */ 2909 A_UINT32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2910 /** 2911 * 11AX HE OFDMA number of users for which sounding was initiated 2912 * during TX 2913 */ 2914 A_UINT32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2915 /** 11AX HE OFDMA number of users for which sounding was forced during TX */ 2916 A_UINT32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 2917 } htt_stats_txbf_ofdma_steer_stats_tlv; 2918 /* preserve old name alias for new name consistent with the tag name */ 2919 typedef htt_stats_txbf_ofdma_steer_stats_tlv htt_txbf_ofdma_steer_stats_tlv; 2920 2921 /* Note: 2922 * This struct htt_tx_pdev_txbf_ofdma_stats_t and all its constituent 2923 * struct TLVs are deprecated, due to the need for restructuring these 2924 * stats into a variable length array 2925 */ 2926 typedef struct { /* DEPRECATED */ 2927 htt_stats_txbf_ofdma_ndpa_stats_tlv ofdma_ndpa_tlv; 2928 htt_stats_txbf_ofdma_ndp_stats_tlv ofdma_ndp_tlv; 2929 htt_stats_txbf_ofdma_brp_stats_tlv ofdma_brp_tlv; 2930 htt_stats_txbf_ofdma_steer_stats_tlv ofdma_steer_tlv; 2931 } htt_tx_pdev_txbf_ofdma_stats_t; 2932 2933 typedef struct { 2934 /** 11AX HE OFDMA NDPA frame queued to the HW */ 2935 A_UINT32 ax_ofdma_ndpa_queued; 2936 /** 11AX HE OFDMA NDPA frame sent over the air */ 2937 A_UINT32 ax_ofdma_ndpa_tried; 2938 /** 11AX HE OFDMA NDPA frame flushed by HW */ 2939 A_UINT32 ax_ofdma_ndpa_flushed; 2940 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 2941 A_UINT32 ax_ofdma_ndpa_err; 2942 } htt_txbf_ofdma_ax_ndpa_stats_elem_t; 2943 2944 typedef struct { 2945 htt_tlv_hdr_t tlv_hdr; 2946 /** 2947 * This field is populated with the num of elems in the ax_ndpa[] 2948 * variable length array. 2949 */ 2950 A_UINT32 num_elems_ax_ndpa_arr; 2951 /** 2952 * This field will be filled by target with value of 2953 * sizeof(htt_txbf_ofdma_ax_ndpa_stats_elem_t). 2954 * This is for allowing host to infer how much data target has provided, 2955 * even if it using different version of the struct def than what target 2956 * had used. 2957 */ 2958 A_UINT32 arr_elem_size_ax_ndpa; 2959 htt_txbf_ofdma_ax_ndpa_stats_elem_t ax_ndpa[1]; /* variable length */ 2960 } htt_stats_txbf_ofdma_ax_ndpa_stats_tlv; 2961 /* preserve old name alias for new name consistent with the tag name */ 2962 typedef htt_stats_txbf_ofdma_ax_ndpa_stats_tlv htt_txbf_ofdma_ax_ndpa_stats_tlv; 2963 2964 typedef struct { 2965 /** 11AX HE OFDMA NDP frame queued to the HW */ 2966 A_UINT32 ax_ofdma_ndp_queued; 2967 /** 11AX HE OFDMA NDPA frame sent over the air */ 2968 A_UINT32 ax_ofdma_ndp_tried; 2969 /** 11AX HE OFDMA NDPA frame flushed by HW */ 2970 A_UINT32 ax_ofdma_ndp_flushed; 2971 /** 11AX HE OFDMA NDPA frame completed with error(s) */ 2972 A_UINT32 ax_ofdma_ndp_err; 2973 } htt_txbf_ofdma_ax_ndp_stats_elem_t; 2974 2975 typedef struct { 2976 htt_tlv_hdr_t tlv_hdr; 2977 /** 2978 * This field is populated with the num of elems in the the ax_ndp[] 2979 * variable length array. 2980 */ 2981 A_UINT32 num_elems_ax_ndp_arr; 2982 /** 2983 * This field will be filled by target with value of 2984 * sizeof(htt_txbf_ofdma_ax_ndp_stats_elem_t). 2985 * This is for allowing host to infer how much data target has provided, 2986 * even if it using different version of the struct def than what target 2987 * had used. 2988 */ 2989 A_UINT32 arr_elem_size_ax_ndp; 2990 htt_txbf_ofdma_ax_ndp_stats_elem_t ax_ndp[1]; /* variable length */ 2991 } htt_stats_txbf_ofdma_ax_ndp_stats_tlv; 2992 /* preserve old name alias for new name consistent with the tag name */ 2993 typedef htt_stats_txbf_ofdma_ax_ndp_stats_tlv htt_txbf_ofdma_ax_ndp_stats_tlv; 2994 2995 typedef struct { 2996 /** 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 2997 A_UINT32 ax_ofdma_brpoll_queued; 2998 /** 11AX HE OFDMA MU BRPOLL frame sent over the air */ 2999 A_UINT32 ax_ofdma_brpoll_tried; 3000 /** 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 3001 A_UINT32 ax_ofdma_brpoll_flushed; 3002 /** 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 3003 A_UINT32 ax_ofdma_brp_err; 3004 /** 3005 * Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 3006 * completed with error(s) 3007 */ 3008 A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd; 3009 } htt_txbf_ofdma_ax_brp_stats_elem_t; 3010 3011 typedef struct { 3012 htt_tlv_hdr_t tlv_hdr; 3013 /** 3014 * This field is populated with the num of elems in the the ax_brp[] 3015 * variable length array. 3016 */ 3017 A_UINT32 num_elems_ax_brp_arr; 3018 /** 3019 * This field will be filled by target with value of 3020 * sizeof(htt_txbf_ofdma_ax_brp_stats_elem_t). 3021 * This is for allowing host to infer how much data target has provided, 3022 * even if it using different version of the struct than what target 3023 * had used. 3024 */ 3025 A_UINT32 arr_elem_size_ax_brp; 3026 htt_txbf_ofdma_ax_brp_stats_elem_t ax_brp[1]; /* variable length */ 3027 } htt_stats_txbf_ofdma_ax_brp_stats_tlv; 3028 /* preserve old name alias for new name consistent with the tag name */ 3029 typedef htt_stats_txbf_ofdma_ax_brp_stats_tlv htt_txbf_ofdma_ax_brp_stats_tlv; 3030 3031 typedef struct { 3032 /** 3033 * 11AX HE OFDMA PPDUs that were sent over the air with steering 3034 * (TXBF + OFDMA) 3035 */ 3036 A_UINT32 ax_ofdma_num_ppdu_steer; 3037 /** 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 3038 A_UINT32 ax_ofdma_num_ppdu_ol; 3039 /** 3040 * 11AX HE OFDMA number of users for which CBF prefetch was initiated 3041 * to PHY HW during TX 3042 */ 3043 A_UINT32 ax_ofdma_num_usrs_prefetch; 3044 /** 3045 * 11AX HE OFDMA number of users for which sounding was initiated 3046 * during TX 3047 */ 3048 A_UINT32 ax_ofdma_num_usrs_sound; 3049 /** 11AX HE OFDMA number of users for which sounding was forced during TX */ 3050 A_UINT32 ax_ofdma_num_usrs_force_sound; 3051 } htt_txbf_ofdma_ax_steer_stats_elem_t; 3052 3053 typedef struct { 3054 htt_tlv_hdr_t tlv_hdr; 3055 /** 3056 * This field is populated with the num of elems in the ax_steer[] 3057 * variable length array. 3058 */ 3059 A_UINT32 num_elems_ax_steer_arr; 3060 /** 3061 * This field will be filled by target with value of 3062 * sizeof(htt_txbf_ofdma_ax_steer_stats_elem_t). 3063 * This is for allowing host to infer how much data target has provided, 3064 * even if it using different version of the struct than what target 3065 * had used. 3066 */ 3067 A_UINT32 arr_elem_size_ax_steer; 3068 htt_txbf_ofdma_ax_steer_stats_elem_t ax_steer[1]; /* variable length */ 3069 } htt_stats_txbf_ofdma_ax_steer_stats_tlv; 3070 /* preserve old name alias for new name consistent with the tag name */ 3071 typedef htt_stats_txbf_ofdma_ax_steer_stats_tlv 3072 htt_txbf_ofdma_ax_steer_stats_tlv; 3073 3074 typedef struct { 3075 htt_tlv_hdr_t tlv_hdr; 3076 /* 11AX HE OFDMA MPDUs tried in rbo steering */ 3077 A_UINT32 ax_ofdma_rbo_steer_mpdus_tried; 3078 /* 11AX HE OFDMA MPDUs failed in rbo steering */ 3079 A_UINT32 ax_ofdma_rbo_steer_mpdus_failed; 3080 /* 11AX HE OFDMA MPDUs tried in sifs steering */ 3081 A_UINT32 ax_ofdma_sifs_steer_mpdus_tried; 3082 /* 11AX HE OFDMA MPDUs failed in sifs steering */ 3083 A_UINT32 ax_ofdma_sifs_steer_mpdus_failed; 3084 } htt_stats_txbf_ofdma_ax_steer_mpdu_stats_tlv; 3085 /* preserve old name alias for new name consistent with the tag name */ 3086 typedef htt_stats_txbf_ofdma_ax_steer_mpdu_stats_tlv 3087 htt_txbf_ofdma_ax_steer_mpdu_stats_tlv; 3088 3089 typedef struct { 3090 /** 11BE EHT OFDMA NDPA frame queued to the HW */ 3091 A_UINT32 be_ofdma_ndpa_queued; 3092 /** 11BE EHT OFDMA NDPA frame sent over the air */ 3093 A_UINT32 be_ofdma_ndpa_tried; 3094 /** 11BE EHT OFDMA NDPA frame flushed by HW */ 3095 A_UINT32 be_ofdma_ndpa_flushed; 3096 /** 11BE EHT OFDMA NDPA frame completed with error(s) */ 3097 A_UINT32 be_ofdma_ndpa_err; 3098 } htt_txbf_ofdma_be_ndpa_stats_elem_t; 3099 3100 typedef struct { 3101 htt_tlv_hdr_t tlv_hdr; 3102 /** 3103 * This field is populated with the num of elems in the be_ndpa[] 3104 * variable length array. 3105 */ 3106 A_UINT32 num_elems_be_ndpa_arr; 3107 /** 3108 * This field will be filled by target with value of 3109 * sizeof(htt_txbf_ofdma_be_ndpa_stats_elem_t). 3110 * This is for allowing host to infer how much data target has provided, 3111 * even if it using different version of the struct than what target 3112 * had used. 3113 */ 3114 A_UINT32 arr_elem_size_be_ndpa; 3115 htt_txbf_ofdma_be_ndpa_stats_elem_t be_ndpa[1]; /* variable length */ 3116 } htt_stats_txbf_ofdma_be_ndpa_stats_tlv; 3117 /* preserve old name alias for new name consistent with the tag name */ 3118 typedef htt_stats_txbf_ofdma_be_ndpa_stats_tlv htt_txbf_ofdma_be_ndpa_stats_tlv; 3119 3120 typedef struct { 3121 /** 11BE EHT OFDMA NDP frame queued to the HW */ 3122 A_UINT32 be_ofdma_ndp_queued; 3123 /** 11BE EHT OFDMA NDPA frame sent over the air */ 3124 A_UINT32 be_ofdma_ndp_tried; 3125 /** 11BE EHT OFDMA NDPA frame flushed by HW */ 3126 A_UINT32 be_ofdma_ndp_flushed; 3127 /** 11BE EHT OFDMA NDPA frame completed with error(s) */ 3128 A_UINT32 be_ofdma_ndp_err; 3129 } htt_txbf_ofdma_be_ndp_stats_elem_t; 3130 3131 typedef struct { 3132 htt_tlv_hdr_t tlv_hdr; 3133 /** 3134 * This field is populated with the num of elems in the be_ndp[] 3135 * variable length array. 3136 */ 3137 A_UINT32 num_elems_be_ndp_arr; 3138 /** 3139 * This field will be filled by target with value of 3140 * sizeof(htt_txbf_ofdma_be_ndp_stats_elem_t). 3141 * This is for allowing host to infer how much data target has provided, 3142 * even if it using different version of the struct than what target 3143 * had used. 3144 */ 3145 A_UINT32 arr_elem_size_be_ndp; 3146 htt_txbf_ofdma_be_ndp_stats_elem_t be_ndp[1]; /* variable length */ 3147 } htt_stats_txbf_ofdma_be_ndp_stats_tlv; 3148 /* preserve old name alias for new name consistent with the tag name */ 3149 typedef htt_stats_txbf_ofdma_be_ndp_stats_tlv htt_txbf_ofdma_be_ndp_stats_tlv; 3150 3151 typedef struct { 3152 /** 11BE EHT OFDMA MU BRPOLL frame queued to the HW */ 3153 A_UINT32 be_ofdma_brpoll_queued; 3154 /** 11BE EHT OFDMA MU BRPOLL frame sent over the air */ 3155 A_UINT32 be_ofdma_brpoll_tried; 3156 /** 11BE EHT OFDMA MU BRPOLL frame flushed by HW */ 3157 A_UINT32 be_ofdma_brpoll_flushed; 3158 /** 11BE EHT OFDMA MU BRPOLL frame completed with error(s) */ 3159 A_UINT32 be_ofdma_brp_err; 3160 /** 3161 * Number of CBF(s) received when 11BE EHT OFDMA MU BRPOLL frame 3162 * completed with error(s) 3163 */ 3164 A_UINT32 be_ofdma_brp_err_num_cbf_rcvd; 3165 } htt_txbf_ofdma_be_brp_stats_elem_t; 3166 3167 typedef struct { 3168 htt_tlv_hdr_t tlv_hdr; 3169 /** 3170 * This field is populated with the num of elems in the be_brp[] 3171 * variable length array. 3172 */ 3173 A_UINT32 num_elems_be_brp_arr; 3174 /** 3175 * This field will be filled by target with value of 3176 * sizeof(htt_txbf_ofdma_be_brp_stats_elem_t). 3177 * This is for allowing host to infer how much data target has provided, 3178 * even if it using different version of the struct than what target 3179 * had used 3180 */ 3181 A_UINT32 arr_elem_size_be_brp; 3182 htt_txbf_ofdma_be_brp_stats_elem_t be_brp[1]; /* variable length */ 3183 } htt_stats_txbf_ofdma_be_brp_stats_tlv; 3184 /* preserve old name alias for new name consistent with the tag name */ 3185 typedef htt_stats_txbf_ofdma_be_brp_stats_tlv htt_txbf_ofdma_be_brp_stats_tlv; 3186 3187 typedef struct { 3188 /** 3189 * 11BE EHT OFDMA PPDUs that were sent over the air with steering 3190 * (TXBF + OFDMA) 3191 */ 3192 A_UINT32 be_ofdma_num_ppdu_steer; 3193 /** 11BE EHT OFDMA PPDUs that were sent over the air in open loop */ 3194 A_UINT32 be_ofdma_num_ppdu_ol; 3195 /** 3196 * 11BE EHT OFDMA number of users for which CBF prefetch was initiated 3197 * to PHY HW during TX 3198 */ 3199 A_UINT32 be_ofdma_num_usrs_prefetch; 3200 /** 3201 * 11BE EHT OFDMA number of users for which sounding was initiated 3202 * during TX 3203 */ 3204 A_UINT32 be_ofdma_num_usrs_sound; 3205 /** 3206 * 11BE EHT OFDMA number of users for which sounding was forced during TX 3207 */ 3208 A_UINT32 be_ofdma_num_usrs_force_sound; 3209 } htt_txbf_ofdma_be_steer_stats_elem_t; 3210 3211 typedef struct { 3212 htt_tlv_hdr_t tlv_hdr; 3213 /** 3214 * This field is populated with the num of elems in the be_steer[] 3215 * variable length array. 3216 */ 3217 A_UINT32 num_elems_be_steer_arr; 3218 /** 3219 * This field will be filled by target with value of 3220 * sizeof(htt_txbf_ofdma_be_steer_stats_elem_t). 3221 * This is for allowing host to infer how much data target has provided, 3222 * even if it using different version of the struct than what target 3223 * had used. 3224 */ 3225 A_UINT32 arr_elem_size_be_steer; 3226 htt_txbf_ofdma_be_steer_stats_elem_t be_steer[1]; /* variable length */ 3227 } htt_stats_txbf_ofdma_be_steer_stats_tlv; 3228 /* preserve old name alias for new name consistent with the tag name */ 3229 typedef htt_stats_txbf_ofdma_be_steer_stats_tlv 3230 htt_txbf_ofdma_be_steer_stats_tlv; 3231 3232 typedef struct { 3233 htt_tlv_hdr_t tlv_hdr; 3234 /* 11BE EHT OFDMA MPDUs tried in rbo steering */ 3235 A_UINT32 be_ofdma_rbo_steer_mpdus_tried; 3236 /* 11BE EHT OFDMA MPDUs failed in rbo steering */ 3237 A_UINT32 be_ofdma_rbo_steer_mpdus_failed; 3238 /* 11BE EHT OFDMA MPDUs tried in sifs steering */ 3239 A_UINT32 be_ofdma_sifs_steer_mpdus_tried; 3240 /* 11BE EHT OFDMA MPDUs failed in sifs steering */ 3241 A_UINT32 be_ofdma_sifs_steer_mpdus_failed; 3242 } htt_stats_txbf_ofdma_be_steer_mpdu_stats_tlv; 3243 /* preserve old name alias for new name consistent with the tag name */ 3244 typedef htt_stats_txbf_ofdma_be_steer_mpdu_stats_tlv 3245 htt_txbf_ofdma_be_steer_mpdu_stats_tlv; 3246 3247 /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA 3248 * TLV_TAGS: 3249 * - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG 3250 * - HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG 3251 * - HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG 3252 * - HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG 3253 * - HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG 3254 * - HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG 3255 * - HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG 3256 * - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG 3257 * - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG 3258 * - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG 3259 */ 3260 3261 typedef struct { 3262 htt_tlv_hdr_t tlv_hdr; 3263 /** 11AC VHT SU NDP frame completed with error(s) */ 3264 A_UINT32 ac_su_ndp_err; 3265 /** 11AC VHT SU NDPA frame completed with error(s) */ 3266 A_UINT32 ac_su_ndpa_err; 3267 /** 11AC VHT MU MIMO NDPA frame completed with error(s) */ 3268 A_UINT32 ac_mu_mimo_ndpa_err; 3269 /** 11AC VHT MU MIMO NDP frame completed with error(s) */ 3270 A_UINT32 ac_mu_mimo_ndp_err; 3271 /** 11AC VHT MU MIMO BRPOLL for user 1 frame completed with error(s) */ 3272 A_UINT32 ac_mu_mimo_brp1_err; 3273 /** 11AC VHT MU MIMO BRPOLL for user 2 frame completed with error(s) */ 3274 A_UINT32 ac_mu_mimo_brp2_err; 3275 /** 11AC VHT MU MIMO BRPOLL for user 3 frame completed with error(s) */ 3276 A_UINT32 ac_mu_mimo_brp3_err; 3277 /** 11AC VHT SU NDPA frame flushed by HW */ 3278 A_UINT32 ac_su_ndpa_flushed; 3279 /** 11AC VHT SU NDP frame flushed by HW */ 3280 A_UINT32 ac_su_ndp_flushed; 3281 /** 11AC VHT MU MIMO NDPA frame flushed by HW */ 3282 A_UINT32 ac_mu_mimo_ndpa_flushed; 3283 /** 11AC VHT MU MIMO NDP frame flushed by HW */ 3284 A_UINT32 ac_mu_mimo_ndp_flushed; 3285 /** 11AC VHT MU MIMO BRPOLL for user 1 frame flushed by HW */ 3286 A_UINT32 ac_mu_mimo_brpoll1_flushed; 3287 /** 11AC VHT MU MIMO BRPOLL for user 2 frame flushed by HW */ 3288 A_UINT32 ac_mu_mimo_brpoll2_flushed; 3289 /** 11AC VHT MU MIMO BRPOLL for user 3 frame flushed by HW */ 3290 A_UINT32 ac_mu_mimo_brpoll3_flushed; 3291 } htt_stats_tx_selfgen_ac_err_stats_tlv; 3292 /* preserve old name alias for new name consistent with the tag name */ 3293 typedef htt_stats_tx_selfgen_ac_err_stats_tlv htt_tx_selfgen_ac_err_stats_tlv; 3294 3295 typedef struct { 3296 htt_tlv_hdr_t tlv_hdr; 3297 /** 11AX HE SU NDP frame completed with error(s) */ 3298 A_UINT32 ax_su_ndp_err; 3299 /** 11AX HE SU NDPA frame completed with error(s) */ 3300 A_UINT32 ax_su_ndpa_err; 3301 /** 11AX HE MU MIMO NDPA frame completed with error(s) */ 3302 A_UINT32 ax_mu_mimo_ndpa_err; 3303 /** 11AX HE MU MIMO NDP frame completed with error(s) */ 3304 A_UINT32 ax_mu_mimo_ndp_err; 3305 union { 3306 struct { 3307 /* deprecated old names */ 3308 A_UINT32 ax_mu_mimo_brp1_err; 3309 A_UINT32 ax_mu_mimo_brp2_err; 3310 A_UINT32 ax_mu_mimo_brp3_err; 3311 A_UINT32 ax_mu_mimo_brp4_err; 3312 A_UINT32 ax_mu_mimo_brp5_err; 3313 A_UINT32 ax_mu_mimo_brp6_err; 3314 A_UINT32 ax_mu_mimo_brp7_err; 3315 }; 3316 /** 11AX HE MU BR-POLL frame for 1 - 7 users completed with error(s) */ 3317 A_UINT32 ax_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 3318 }; 3319 /** 11AX HE MU Basic Trigger frame completed with error(s) */ 3320 A_UINT32 ax_basic_trigger_err; 3321 /** 11AX HE MU BSRP Trigger frame completed with error(s) */ 3322 A_UINT32 ax_bsr_trigger_err; 3323 /** 11AX HE MU BAR Trigger frame completed with error(s) */ 3324 A_UINT32 ax_mu_bar_trigger_err; 3325 /** 11AX HE MU RTS Trigger frame completed with error(s) */ 3326 A_UINT32 ax_mu_rts_trigger_err; 3327 /** 11AX HE MU ULMUMIMO Trigger frame completed with error(s) */ 3328 A_UINT32 ax_ulmumimo_trigger_err; 3329 /** 3330 * Number of CBF(s) received when 11AX HE MU MIMO BRPOLL 3331 * frame completed with error(s) 3332 */ 3333 A_UINT32 ax_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3334 /** 11AX HE SU NDPA frame flushed by HW */ 3335 A_UINT32 ax_su_ndpa_flushed; 3336 /** 11AX HE SU NDP frame flushed by HW */ 3337 A_UINT32 ax_su_ndp_flushed; 3338 /** 11AX HE MU MIMO NDPA frame flushed by HW */ 3339 A_UINT32 ax_mu_mimo_ndpa_flushed; 3340 /** 11AX HE MU MIMO NDP frame flushed by HW */ 3341 A_UINT32 ax_mu_mimo_ndp_flushed; 3342 /** 11AX HE MU BR-POLL frame for users 1 - 7 flushed by HW */ 3343 A_UINT32 ax_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; 3344 /** 3345 * 11AX HE UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) 3346 */ 3347 A_UINT32 ax_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3348 3349 /** 11AX HE MU OFDMA Basic Trigger frame completed with partial user response */ 3350 A_UINT32 ax_basic_trigger_partial_resp; 3351 /** 11AX HE MU BSRP Trigger frame completed with partial user response */ 3352 A_UINT32 ax_bsr_trigger_partial_resp; 3353 /** 11AX HE MU BAR Trigger frame completed with partial user response */ 3354 A_UINT32 ax_mu_bar_trigger_partial_resp; 3355 } htt_stats_tx_selfgen_ax_err_stats_tlv; 3356 /* preserve old name alias for new name consistent with the tag name */ 3357 typedef htt_stats_tx_selfgen_ax_err_stats_tlv htt_tx_selfgen_ax_err_stats_tlv; 3358 3359 typedef struct { 3360 htt_tlv_hdr_t tlv_hdr; 3361 /** 11BE EHT SU NDP frame completed with error(s) */ 3362 A_UINT32 be_su_ndp_err; 3363 /** 11BE EHT SU NDPA frame completed with error(s) */ 3364 A_UINT32 be_su_ndpa_err; 3365 /** 11BE EHT MU MIMO NDPA frame completed with error(s) */ 3366 A_UINT32 be_mu_mimo_ndpa_err; 3367 /** 11BE EHT MU MIMO NDP frame completed with error(s) */ 3368 A_UINT32 be_mu_mimo_ndp_err; 3369 /** 11BE EHT MU BR-POLL frame for 1 - 7 users completed with error(s) */ 3370 A_UINT32 be_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 3371 /** 11BE EHT MU Basic Trigger frame completed with error(s) */ 3372 A_UINT32 be_basic_trigger_err; 3373 /** 11BE EHT MU BSRP Trigger frame completed with error(s) */ 3374 A_UINT32 be_bsr_trigger_err; 3375 /** 11BE EHT MU BAR Trigger frame completed with error(s) */ 3376 A_UINT32 be_mu_bar_trigger_err; 3377 /** 11BE EHT MU RTS Trigger frame completed with error(s) */ 3378 A_UINT32 be_mu_rts_trigger_err; 3379 /** 11BE EHT MU ULMUMIMO Trigger frame completed with error(s) */ 3380 A_UINT32 be_ulmumimo_trigger_err; 3381 /** 3382 * Number of CBF(s) received when 11BE EHT MU MIMO BRPOLL frame 3383 * completed with error(s) 3384 */ 3385 A_UINT32 be_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3386 /** 11BE EHT SU NDPA frame flushed by HW */ 3387 A_UINT32 be_su_ndpa_flushed; 3388 /** 11BE EHT SU NDP frame flushed by HW */ 3389 A_UINT32 be_su_ndp_flushed; 3390 /** 11BE EHT MU MIMO NDPA frame flushed by HW */ 3391 A_UINT32 be_mu_mimo_ndpa_flushed; 3392 /** 11BE HT MU MIMO NDP frame flushed by HW */ 3393 A_UINT32 be_mu_mimo_ndp_flushed; 3394 /** 11BE EHT MU BR-POLL frame for users 1 - 7 flushed by HW */ 3395 A_UINT32 be_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; 3396 /** 3397 * 11BE EHT UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) 3398 */ 3399 A_UINT32 be_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3400 3401 /** 11BE EHT MU OFDMA Basic Trigger frame completed with partial user response */ 3402 A_UINT32 be_basic_trigger_partial_resp; 3403 /** 11BE EHT MU BSRP Trigger frame completed with partial user response */ 3404 A_UINT32 be_bsr_trigger_partial_resp; 3405 /** 11BE EHT MU BAR Trigger frame completed with partial user response */ 3406 A_UINT32 be_mu_bar_trigger_partial_resp; 3407 /** 11BE EHT MU RTS Trigger frame blocked due to partner link TX/RX(eMLSR) */ 3408 A_UINT32 be_mu_rts_trigger_blocked; 3409 /** 11BE EHT MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ 3410 A_UINT32 be_bsr_trigger_blocked; 3411 } htt_stats_tx_selfgen_be_err_stats_tlv; 3412 /* preserve old name alias for new name consistent with the tag name */ 3413 typedef htt_stats_tx_selfgen_be_err_stats_tlv htt_tx_selfgen_be_err_stats_tlv; 3414 3415 /* 3416 * Scheduler completion status reason code. 3417 * (0) HTT_TXERR_NONE - No error (Success). 3418 * (1) HTT_TXERR_RESP - Response timeout, response mismatch, BW mismatch, 3419 * MIMO control mismatch, CRC error etc. 3420 * (2) HTT_TXERR_FILT - Blocked by HW tx filtering. 3421 * (3) HTT_TXERR_FIFO - FIFO, misc. errors in HW. 3422 * (4) HTT_TXERR_SWABORT - Software initialted abort (TX_ABORT). 3423 * (5) HTT_TXERR_RESERVED1 - Currently reserved. 3424 * (6) HTT_TXERR_RESERVED2 - Currently reserved. 3425 */ 3426 3427 /* Scheduler error code. 3428 * (0) HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR - Flush received from HW. 3429 * (1) HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR - Scheduler command was 3430 * filtered by HW. 3431 * (2) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR - Response frame mismatch 3432 * error. 3433 * (3) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR - CBF 3434 * received with MIMO control mismatch. 3435 * (4) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR - CBF received with 3436 * BW mismatch. 3437 * (5) HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR - Error in transmitting 3438 * frame even after maximum retries. 3439 * (6) HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR - Response frame 3440 * received outside RX window. 3441 * (7) HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR - No frame 3442 * received by HW for queuing within SIFS interval. 3443 */ 3444 3445 typedef struct { 3446 htt_tlv_hdr_t tlv_hdr; 3447 /** 11AC VHT SU NDPA scheduler completion status reason code */ 3448 A_UINT32 ac_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3449 /** 11AC VHT SU NDP scheduler completion status reason code */ 3450 A_UINT32 ac_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3451 /** 11AC VHT SU NDP scheduler error code */ 3452 A_UINT32 ac_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3453 /** 11AC VHT MU MIMO NDPA scheduler completion status reason code */ 3454 A_UINT32 ac_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3455 /** 11AC VHT MU MIMO NDP scheduler completion status reason code */ 3456 A_UINT32 ac_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3457 /** 11AC VHT MU MIMO NDP scheduler error code */ 3458 A_UINT32 ac_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3459 /** 11AC VHT MU MIMO BRPOLL scheduler completion status reason code */ 3460 A_UINT32 ac_mu_mimo_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3461 /** 11AC VHT MU MIMO BRPOLL scheduler error code */ 3462 A_UINT32 ac_mu_mimo_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3463 } htt_stats_tx_selfgen_ac_sched_status_stats_tlv; 3464 /* preserve old name alias for new name consistent with the tag name */ 3465 typedef htt_stats_tx_selfgen_ac_sched_status_stats_tlv 3466 htt_tx_selfgen_ac_sched_status_stats_tlv; 3467 3468 typedef struct { 3469 htt_tlv_hdr_t tlv_hdr; 3470 /** 11AX HE SU NDPA scheduler completion status reason code */ 3471 A_UINT32 ax_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3472 /** 11AX SU NDP scheduler completion status reason code */ 3473 A_UINT32 ax_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3474 /** 11AX HE SU NDP scheduler error code */ 3475 A_UINT32 ax_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3476 /** 11AX HE MU MIMO NDPA scheduler completion status reason code */ 3477 A_UINT32 ax_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3478 /** 11AX HE MU MIMO NDP scheduler completion status reason code */ 3479 A_UINT32 ax_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3480 /** 11AX HE MU MIMO NDP scheduler error code */ 3481 A_UINT32 ax_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3482 /** 11AX HE MU MIMO MU BRPOLL scheduler completion status reason code */ 3483 A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3484 /** 11AX HE MU MIMO MU BRPOLL scheduler error code */ 3485 A_UINT32 ax_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3486 /** 11AX HE MU BAR scheduler completion status reason code */ 3487 A_UINT32 ax_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3488 /** 11AX HE MU BAR scheduler error code */ 3489 A_UINT32 ax_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3490 /** 3491 * 11AX HE UL OFDMA Basic Trigger scheduler completion status reason code 3492 */ 3493 A_UINT32 ax_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3494 /** 11AX HE UL OFDMA Basic Trigger scheduler error code */ 3495 A_UINT32 ax_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3496 /** 3497 * 11AX HE UL MUMIMO Basic Trigger scheduler completion status reason code 3498 */ 3499 A_UINT32 ax_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3500 /** 11AX HE UL MUMIMO Basic Trigger scheduler error code */ 3501 A_UINT32 ax_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3502 } htt_stats_tx_selfgen_ax_sched_status_stats_tlv; 3503 /* preserve old name alias for new name consistent with the tag name */ 3504 typedef htt_stats_tx_selfgen_ax_sched_status_stats_tlv 3505 htt_tx_selfgen_ax_sched_status_stats_tlv; 3506 3507 typedef struct { 3508 htt_tlv_hdr_t tlv_hdr; 3509 /** 11BE EHT SU NDPA scheduler completion status reason code */ 3510 A_UINT32 be_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3511 /** 11BE SU NDP scheduler completion status reason code */ 3512 A_UINT32 be_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3513 /** 11BE EHT SU NDP scheduler error code */ 3514 A_UINT32 be_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3515 /** 11BE EHT MU MIMO NDPA scheduler completion status reason code */ 3516 A_UINT32 be_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3517 /** 11BE EHT MU MIMO NDP scheduler completion status reason code */ 3518 A_UINT32 be_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3519 /** 11BE EHT MU MIMO NDP scheduler error code */ 3520 A_UINT32 be_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3521 /** 11BE EHT MU MIMO MU BRPOLL scheduler completion status reason code */ 3522 A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3523 /** 11BE EHT MU MIMO MU BRPOLL scheduler error code */ 3524 A_UINT32 be_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3525 /** 11BE EHT MU BAR scheduler completion status reason code */ 3526 A_UINT32 be_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3527 /** 11BE EHT MU BAR scheduler error code */ 3528 A_UINT32 be_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3529 /** 3530 * 11BE EHT UL OFDMA Basic Trigger scheduler completion status reason code 3531 */ 3532 A_UINT32 be_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3533 /** 11BE EHT UL OFDMA Basic Trigger scheduler error code */ 3534 A_UINT32 be_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3535 /** 3536 * 11BE EHT UL MUMIMO Basic Trigger scheduler completion status reason code 3537 */ 3538 A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 3539 /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ 3540 A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; 3541 } htt_stats_tx_selfgen_be_sched_status_stats_tlv; 3542 /* preserve old name alias for new name consistent with the tag name */ 3543 typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv 3544 htt_tx_selfgen_be_sched_status_stats_tlv; 3545 3546 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO 3547 * TLV_TAGS: 3548 * - HTT_STATS_TX_SELFGEN_CMN_STATS_TAG 3549 * - HTT_STATS_TX_SELFGEN_AC_STATS_TAG 3550 * - HTT_STATS_TX_SELFGEN_AX_STATS_TAG 3551 * - HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG 3552 * - HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG 3553 * - HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG 3554 * - HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG 3555 * - HTT_STATS_TX_SELFGEN_BE_STATS_TAG 3556 * - HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG 3557 * - HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG 3558 */ 3559 /* NOTE: 3560 * This structure is for documentation, and cannot be safely used directly. 3561 * Instead, use the constituent TLV structures to fill/parse. 3562 */ 3563 typedef struct { 3564 htt_stats_tx_selfgen_cmn_stats_tlv cmn_tlv; 3565 htt_stats_tx_selfgen_ac_stats_tlv ac_tlv; 3566 htt_stats_tx_selfgen_ax_stats_tlv ax_tlv; 3567 htt_stats_tx_selfgen_ac_err_stats_tlv ac_err_tlv; 3568 htt_stats_tx_selfgen_ax_err_stats_tlv ax_err_tlv; 3569 htt_stats_tx_selfgen_ac_sched_status_stats_tlv ac_sched_status_tlv; 3570 htt_stats_tx_selfgen_ax_sched_status_stats_tlv ax_sched_status_tlv; 3571 htt_stats_tx_selfgen_be_stats_tlv be_tlv; 3572 htt_stats_tx_selfgen_be_err_stats_tlv be_err_tlv; 3573 htt_stats_tx_selfgen_be_sched_status_stats_tlv be_sched_status_tlv; 3574 } htt_tx_pdev_selfgen_stats_t; 3575 3576 /* == TX MU STATS == */ 3577 3578 typedef struct { 3579 htt_tlv_hdr_t tlv_hdr; 3580 /** Number of MU MIMO schedules posted to HW */ 3581 A_UINT32 mu_mimo_sch_posted; 3582 /** Number of MU MIMO schedules failed to post */ 3583 A_UINT32 mu_mimo_sch_failed; 3584 /** Number of MU MIMO PPDUs posted to HW */ 3585 A_UINT32 mu_mimo_ppdu_posted; 3586 /* 3587 * This is the common description for the below sch stats. 3588 * Counts the number of transmissions of each number of MU users 3589 * in each TX mode. 3590 * The array index is the "number of users - 1". 3591 * For example, ac_mu_mimo_sch_nusers[1] counts the number of 11AC MU2 3592 * TX PPDUs, ac_mu_mimo_sch_nusers[2] counts the number of 11AC MU3 3593 * TX PPDUs and so on. 3594 * The same is applicable for the other TX mode stats. 3595 */ 3596 /** Represents the count for 11AC DL MU MIMO sequences */ 3597 A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3598 /** Represents the count for 11AX DL MU MIMO sequences */ 3599 A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3600 /** Represents the count for 11AX DL MU OFDMA sequences */ 3601 A_UINT32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3602 /** 3603 * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers 3604 */ 3605 A_UINT32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3606 /** Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers */ 3607 A_UINT32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3608 /** Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers */ 3609 A_UINT32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3610 /** Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers */ 3611 A_UINT32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3612 /** 3613 * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers 3614 */ 3615 A_UINT32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3616 /** Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ 3617 A_UINT32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3618 /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ 3619 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3620 /** Number of 11AX DL MU MIMO schedules posted per group size */ 3621 A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3622 /** Represents the count for 11BE DL MU MIMO sequences */ 3623 A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3624 /** Number of 11BE DL MU MIMO schedules posted per group size */ 3625 A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3626 /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ 3627 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3628 } htt_stats_tx_pdev_mu_mimo_stats_tlv; 3629 /* preserve old name alias for new name consistent with the tag name */ 3630 typedef htt_stats_tx_pdev_mu_mimo_stats_tlv htt_tx_pdev_mu_mimo_sch_stats_tlv; 3631 3632 typedef struct { 3633 htt_tlv_hdr_t tlv_hdr; 3634 A_UINT32 dl_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3635 3636 A_UINT32 dl_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3637 3638 A_UINT32 dl_mumimo_grp_eligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3639 3640 A_UINT32 dl_mumimo_grp_ineligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3641 3642 A_UINT32 dl_mumimo_grp_invalid[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 3643 3644 A_UINT32 dl_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 3645 3646 A_UINT32 ul_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; 3647 3648 A_UINT32 ul_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3649 3650 A_UINT32 ul_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 3651 } htt_stats_tx_pdev_mumimo_grp_stats_tlv; 3652 /* preserve old name alias for new name consistent with the tag name */ 3653 typedef htt_stats_tx_pdev_mumimo_grp_stats_tlv htt_tx_pdev_mumimo_grp_stats_tlv; 3654 3655 typedef struct { 3656 htt_tlv_hdr_t tlv_hdr; 3657 /** Number of MU MIMO schedules posted to HW */ 3658 A_UINT32 mu_mimo_sch_posted; 3659 /** Number of MU MIMO schedules failed to post */ 3660 A_UINT32 mu_mimo_sch_failed; 3661 /** Number of MU MIMO PPDUs posted to HW */ 3662 A_UINT32 mu_mimo_ppdu_posted; 3663 /* 3664 * This is the common description for the below sch stats. 3665 * Counts the number of transmissions of each number of MU users 3666 * in each TX mode. 3667 * The array index is the "number of users - 1". 3668 * For example, ac_mu_mimo_sch_nusers[1] counts the number of 11AC MU2 3669 * TX PPDUs, ac_mu_mimo_sch_nusers[2] counts the number of 11AC MU3 3670 * TX PPDUs and so on. 3671 * The same is applicable for the other TX mode stats. 3672 */ 3673 /** Represents the count for 11AC DL MU MIMO sequences */ 3674 A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3675 /** Represents the count for 11AX DL MU MIMO sequences */ 3676 A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3677 /** Number of 11AC DL MU MIMO schedules posted per group size (0-3) */ 3678 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3679 /** Number of 11AX DL MU MIMO schedules posted per group size */ 3680 A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 3681 /** Represents the count for 11BE DL MU MIMO sequences */ 3682 A_UINT32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3683 /** Number of 11BE DL MU MIMO schedules posted per group size */ 3684 A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 3685 /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ 3686 A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 3687 } htt_stats_tx_pdev_dl_mu_mimo_stats_tlv; 3688 /* preserve old name alias for new name consistent with the tag name */ 3689 typedef htt_stats_tx_pdev_dl_mu_mimo_stats_tlv 3690 htt_tx_pdev_dl_mu_mimo_sch_stats_tlv; 3691 3692 typedef struct { 3693 htt_tlv_hdr_t tlv_hdr; 3694 /** Represents the count for 11AX DL MU OFDMA sequences */ 3695 A_UINT32 ax_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3696 } htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv; 3697 /* preserve old name alias for new name consistent with the tag name */ 3698 typedef htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv 3699 htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv; 3700 3701 typedef struct { 3702 htt_tlv_hdr_t tlv_hdr; 3703 /** Represents the count for 11BE DL MU OFDMA sequences */ 3704 A_UINT32 be_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3705 } htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv; 3706 /* preserve old name alias for new name consistent with the tag name */ 3707 typedef htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv 3708 htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv; 3709 3710 typedef struct { 3711 htt_tlv_hdr_t tlv_hdr; 3712 /** 3713 * Represents the count for 11AX UL MU OFDMA sequences with Basic Triggers 3714 */ 3715 A_UINT32 ax_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3716 /** 3717 * Represents the count for 11AX UL MU OFDMA sequences with BSRP Triggers 3718 */ 3719 A_UINT32 ax_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3720 /** 3721 * Represents the count for 11AX UL MU OFDMA sequences with BAR Triggers 3722 */ 3723 A_UINT32 ax_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3724 /** 3725 * Represents the count for 11AX UL MU OFDMA sequences with BRP Triggers 3726 */ 3727 A_UINT32 ax_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3728 } htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv; 3729 /* preserve old name alias for new name consistent with the tag name */ 3730 typedef htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv 3731 htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv; 3732 3733 typedef struct { 3734 htt_tlv_hdr_t tlv_hdr; 3735 /** 3736 * Represents the count for 11BE UL MU OFDMA sequences with Basic Triggers 3737 */ 3738 A_UINT32 be_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3739 /** 3740 * Represents the count for 11BE UL MU OFDMA sequences with BSRP Triggers 3741 */ 3742 A_UINT32 be_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3743 /** 3744 * Represents the count for 11BE UL MU OFDMA sequences with BAR Triggers 3745 */ 3746 A_UINT32 be_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3747 /** 3748 * Represents the count for 11BE UL MU OFDMA sequences with BRP Triggers 3749 */ 3750 A_UINT32 be_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 3751 } htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv; 3752 /* preserve old name alias for new name consistent with the tag name */ 3753 typedef htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv 3754 htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv; 3755 3756 typedef struct { 3757 htt_tlv_hdr_t tlv_hdr; 3758 /** 3759 * Represents the count for 11AX UL MU MIMO sequences with Basic Triggers 3760 */ 3761 A_UINT32 ax_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3762 /** 3763 * Represents the count for 11AX UL MU MIMO sequences with BRP Triggers 3764 */ 3765 A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3766 } htt_stats_tx_pdev_ul_mu_mimo_stats_tlv; 3767 /* preserve old name alias for new name consistent with the tag name */ 3768 typedef htt_stats_tx_pdev_ul_mu_mimo_stats_tlv 3769 htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; 3770 3771 typedef struct { 3772 htt_tlv_hdr_t tlv_hdr; 3773 /** 3774 * Represents the count for 11BE UL MU MIMO sequences with Basic Triggers 3775 */ 3776 A_UINT32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3777 /** 3778 * Represents the count for 11BE UL MU MIMO sequences with BRP Triggers 3779 */ 3780 A_UINT32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 3781 } htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv; 3782 /* preserve old name alias for new name consistent with the tag name */ 3783 typedef htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv 3784 htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; 3785 3786 typedef struct { 3787 htt_tlv_hdr_t tlv_hdr; 3788 /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ 3789 A_UINT32 mu_mimo_mpdus_queued_usr; 3790 /** 11AC DL MU MIMO number of mpdus tried over the air, per user */ 3791 A_UINT32 mu_mimo_mpdus_tried_usr; 3792 /** 11AC DL MU MIMO number of mpdus failed acknowledgement, per user */ 3793 A_UINT32 mu_mimo_mpdus_failed_usr; 3794 /** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */ 3795 A_UINT32 mu_mimo_mpdus_requeued_usr; 3796 /** 11AC DL MU MIMO BA not received, per user */ 3797 A_UINT32 mu_mimo_err_no_ba_usr; 3798 /** 11AC DL MU MIMO mpdu underrun encountered, per user */ 3799 A_UINT32 mu_mimo_mpdu_underrun_usr; 3800 /** 11AC DL MU MIMO ampdu underrun encountered, per user */ 3801 A_UINT32 mu_mimo_ampdu_underrun_usr; 3802 3803 /** 11AX MU MIMO number of mpdus queued to HW, per user */ 3804 A_UINT32 ax_mu_mimo_mpdus_queued_usr; 3805 /** 11AX MU MIMO number of mpdus tried over the air, per user */ 3806 A_UINT32 ax_mu_mimo_mpdus_tried_usr; 3807 /** 11AX DL MU MIMO number of mpdus failed acknowledgement, per user */ 3808 A_UINT32 ax_mu_mimo_mpdus_failed_usr; 3809 /** 11AX DL MU MIMO number of mpdus re-queued to HW, per user */ 3810 A_UINT32 ax_mu_mimo_mpdus_requeued_usr; 3811 /** 11AX DL MU MIMO BA not received, per user */ 3812 A_UINT32 ax_mu_mimo_err_no_ba_usr; 3813 /** 11AX DL MU MIMO mpdu underrun encountered, per user */ 3814 A_UINT32 ax_mu_mimo_mpdu_underrun_usr; 3815 /** 11AX DL MU MIMO ampdu underrun encountered, per user */ 3816 A_UINT32 ax_mu_mimo_ampdu_underrun_usr; 3817 3818 /** 11AX MU OFDMA number of mpdus queued to HW, per user */ 3819 A_UINT32 ax_ofdma_mpdus_queued_usr; 3820 /** 11AX MU OFDMA number of mpdus tried over the air, per user */ 3821 A_UINT32 ax_ofdma_mpdus_tried_usr; 3822 /** 11AX MU OFDMA number of mpdus failed acknowledgement, per user */ 3823 A_UINT32 ax_ofdma_mpdus_failed_usr; 3824 /** 11AX MU OFDMA number of mpdus re-queued to HW, per user */ 3825 A_UINT32 ax_ofdma_mpdus_requeued_usr; 3826 /** 11AX MU OFDMA BA not received, per user */ 3827 A_UINT32 ax_ofdma_err_no_ba_usr; 3828 /** 11AX MU OFDMA mpdu underrun encountered, per user */ 3829 A_UINT32 ax_ofdma_mpdu_underrun_usr; 3830 /** 11AX MU OFDMA ampdu underrun encountered, per user */ 3831 A_UINT32 ax_ofdma_ampdu_underrun_usr; 3832 } htt_stats_tx_pdev_mumimo_mpdu_stats_tlv; 3833 /* preserve old name alias for new name consistent with the tag name */ 3834 typedef htt_stats_tx_pdev_mumimo_mpdu_stats_tlv 3835 htt_tx_pdev_mu_mimo_mpdu_stats_tlv; 3836 3837 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 /* SCHED_TX_MODE_MU_MIMO_AC */ 3838 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 /* SCHED_TX_MODE_MU_MIMO_AX */ 3839 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */ 3840 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE 4 /* SCHED_TX_MODE_MU_OFDMA_BE */ 3841 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 5 /* SCHED_TX_MODE_MU_MIMO_BE */ 3842 3843 typedef struct { 3844 htt_tlv_hdr_t tlv_hdr; 3845 /* mpdu level stats */ 3846 A_UINT32 mpdus_queued_usr; 3847 A_UINT32 mpdus_tried_usr; 3848 A_UINT32 mpdus_failed_usr; 3849 A_UINT32 mpdus_requeued_usr; 3850 A_UINT32 err_no_ba_usr; 3851 A_UINT32 mpdu_underrun_usr; 3852 A_UINT32 ampdu_underrun_usr; 3853 A_UINT32 user_index; 3854 /** HTT_STATS_TX_SCHED_MODE_xxx */ 3855 A_UINT32 tx_sched_mode; 3856 } htt_stats_tx_pdev_mpdu_stats_tlv; 3857 /* preserve old name alias for new name consistent with the tag name */ 3858 typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv; 3859 3860 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_MU 3861 * TLV_TAGS: 3862 * - HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG (multiple) 3863 * - HTT_STATS_TX_PDEV_MPDU_STATS_TAG (multiple) 3864 */ 3865 /* NOTE: 3866 * This structure is for documentation, and cannot be safely used directly. 3867 * Instead, use the constituent TLV structures to fill/parse. 3868 */ 3869 typedef struct { 3870 htt_stats_tx_pdev_mu_mimo_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */ 3871 htt_stats_tx_pdev_dl_mu_mimo_stats_tlv dl_mu_mimo_sch_stats_tlv[1]; 3872 htt_stats_tx_pdev_ul_mu_mimo_stats_tlv ul_mu_mimo_sch_stats_tlv[1]; 3873 htt_stats_tx_pdev_dl_mu_ofdma_stats_tlv dl_mu_ofdma_sch_stats_tlv[1]; 3874 htt_stats_tx_pdev_ul_mu_ofdma_stats_tlv ul_mu_ofdma_sch_stats_tlv[1]; 3875 /* 3876 * Note that though mu_mimo_mpdu_stats_tlv is named MU-MIMO, 3877 * it can also hold MU-OFDMA stats. 3878 */ 3879 htt_stats_tx_pdev_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_MAX_NUM_USERS */ 3880 htt_stats_tx_pdev_mumimo_grp_stats_tlv mumimo_grp_stats_tlv; 3881 } htt_tx_pdev_mu_mimo_stats_t; 3882 3883 /* == TX SCHED STATS == */ 3884 3885 #define HTT_SCHED_TXQ_CMD_POSTED_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 3886 3887 /* NOTE: Variable length TLV, use length spec to infer array size */ 3888 typedef struct { 3889 htt_tlv_hdr_t tlv_hdr; 3890 /** Scheduler command posted per tx_mode */ 3891 A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; 3892 } htt_stats_sched_txq_cmd_posted_tlv; 3893 /* preserve old name alias for new name consistent with the tag name */ 3894 typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; 3895 3896 #define HTT_SCHED_TXQ_CMD_REAPED_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 3897 3898 /* NOTE: Variable length TLV, use length spec to infer array size */ 3899 typedef struct { 3900 htt_tlv_hdr_t tlv_hdr; 3901 /** Scheduler command reaped per tx_mode */ 3902 A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; 3903 } htt_stats_sched_txq_cmd_reaped_tlv; 3904 /* preserve old name alias for new name consistent with the tag name */ 3905 typedef htt_stats_sched_txq_cmd_reaped_tlv htt_sched_txq_cmd_reaped_tlv_v; 3906 3907 #define HTT_SCHED_TXQ_SCHED_ORDER_SU_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 3908 3909 /* NOTE: Variable length TLV, use length spec to infer array size */ 3910 typedef struct { 3911 htt_tlv_hdr_t tlv_hdr; 3912 /** 3913 * sched_order_su contains the peer IDs of peers chosen in the last 3914 * NUM_SCHED_ORDER_LOG scheduler instances. 3915 * The array is circular; it's unspecified which array element corresponds 3916 * to the most recent scheduler invocation, and which corresponds to 3917 * the (NUM_SCHED_ORDER_LOG-1) most recent scheduler invocation. 3918 */ 3919 A_UINT32 sched_order_su[1]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ 3920 } htt_stats_sched_txq_sched_order_su_tlv; 3921 /* preserve old name alias for new name consistent with the tag name */ 3922 typedef htt_stats_sched_txq_sched_order_su_tlv htt_sched_txq_sched_order_su_tlv_v; 3923 3924 typedef struct { 3925 htt_tlv_hdr_t tlv_hdr; 3926 A_UINT32 htt_stats_type; 3927 } htt_stats_error_tlv_v; 3928 3929 typedef enum { 3930 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */ 3931 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, /* Skip the tid's 2nd sched_cmd when 1st cmd is ongoing */ 3932 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, /* Skip the tid when MPDU state is invalid */ 3933 HTT_SCHED_TID_SKIP_SCHED_DISABLED, /* Skip the tid when scheduling is disabled for that tid */ 3934 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, /* Skip the TQM bypass tid when it has pending sched_cmd */ 3935 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, /* Skip tid from 2nd SU schedule when any of the following flag is set 3936 WAL_TX_TID(SEND_BAR | TQM_MPDU_STATE_VALID | SEND_QOS_NULL | TQM_NOTIFY_MPDU | SENDN_PENDING) */ 3937 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, /* Skip the tid when command slot is not available */ 3938 HTT_SCHED_TID_SKIP_NO_DATA, /* Skip tid without data */ 3939 HTT_SCHED_TID_SKIP_NO_ENQ = HTT_SCHED_TID_SKIP_NO_DATA, /* deprecated old name */ 3940 HTT_SCHED_TID_SKIP_LOW_ENQ, /* Skip the tid when enqueue is low */ 3941 HTT_SCHED_TID_SKIP_PAUSED, /* Skipping the paused tid(sendn-frames) */ 3942 HTT_SCHED_TID_SKIP_UL_RESP, /* skip UL response tid */ 3943 HTT_SCHED_TID_SKIP_UL = HTT_SCHED_TID_SKIP_UL_RESP, /* deprecated old name */ 3944 HTT_SCHED_TID_REMOVE_PAUSED, /* Removing the paused tid when number of sendn frames is zero */ 3945 HTT_SCHED_TID_REMOVE_NO_ENQ, /* Remove tid with zero queue depth */ 3946 HTT_SCHED_TID_REMOVE_UL_RESP, /* Remove tid UL response */ 3947 HTT_SCHED_TID_REMOVE_UL = HTT_SCHED_TID_REMOVE_UL_RESP, /* deprecated old name */ 3948 HTT_SCHED_TID_QUERY, /* Moving to next user and adding tid in prepend list when qstats update is pending */ 3949 HTT_SCHED_TID_SU_ONLY, /* Tid is eligible and TX_SCHED_SU_ONLY is true */ 3950 HTT_SCHED_TID_ELIGIBLE, /* Tid is eligible for scheduling */ 3951 HTT_SCHED_TID_SKIP_EXCEPT_EAPOL, /* skip tid except eapol */ 3952 HTT_SCHED_TID_SU_LOW_PRI_ONLY, /* su low priority tid only */ 3953 HTT_SCHED_TID_SKIP_SOUND_IN_PROGRESS, /* skip tid sound in progress */ 3954 HTT_SCHED_TID_SKIP_NO_UL_DATA, /* skip ul tid when no ul data */ 3955 HTT_SCHED_TID_REMOVE_UL_NOT_CAPABLE, /* Remove tid that are not UL capable */ 3956 HTT_SCHED_TID_UL_ELIGIBLE, /* Tid is eligible for UL scheduling */ 3957 HTT_SCHED_TID_FALLBACK_TO_PREV_DECISION, /* Fall back to previous decision */ 3958 HTT_SCHED_TID_SKIP_PEER_ALREADY_IN_TXQ, /* skip tid, peer is already available in the txq */ 3959 HTT_SCHED_TID_SKIP_DELAY_UL_SCHED, /* skip tid delay UL schedule */ 3960 HTT_SCHED_TID_SKIP_PWR_SAVE_STATE_OFF, /* Limit UL scheduling to primary link if not in power save state */ 3961 HTT_SCHED_TID_SKIP_TWT_SUSPEND, /* Skip UL trigger for certain cases ex TWT suspend */ 3962 HTT_SCHED_TID_SKIP_DISABLE_160MHZ_OFDMA, /* Skip ul tid if peer supports 160MHZ */ 3963 HTT_SCHED_TID_SKIP_ULMU_DISABLE_FROM_OMI, /* Skip ul tid if sta send omi to indicate to disable UL mu data */ 3964 HTT_SCHED_TID_SKIP_UL_MAX_SCHED_CMD_EXCEEDED,/* skip ul tid if max sched cmd is exceeded */ 3965 HTT_SCHED_TID_SKIP_UL_SMALL_QDEPTH, /* Skip ul tid for small qdepth */ 3966 HTT_SCHED_TID_SKIP_UL_TWT_PAUSED, /* Skip ul tid if twt txq is paused */ 3967 HTT_SCHED_TID_SKIP_PEER_UL_RX_NOT_ACTIVE, /* Skip ul tid if peer ul rx is not active */ 3968 HTT_SCHED_TID_SKIP_NO_FORCE_TRIGGER, /* Skip ul tid if there is no force triggers */ 3969 HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER, /* Skip ul tid if smart basic trigger doesn't have enough data */ 3970 3971 3972 HTT_SCHED_INELIGIBILITY_MAX, 3973 } htt_sched_txq_sched_ineligibility_tlv_enum; 3974 3975 #define HTT_SCHED_TXQ_SCHED_INELIGIBILITY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 3976 3977 /* NOTE: Variable length TLV, use length spec to infer array size */ 3978 typedef struct { 3979 htt_tlv_hdr_t tlv_hdr; 3980 /** 3981 * sched_ineligibility counts the number of occurrences of different 3982 * reasons for tid ineligibility during eligibility checks per txq 3983 * in scheduling 3984 * 3985 * Indexed by htt_sched_txq_sched_ineligibility_tlv_enum. 3986 */ 3987 A_UINT32 sched_ineligibility[1]; 3988 } htt_stats_sched_txq_sched_ineligibility_tlv; 3989 /* preserve old name alias for new name consistent with the tag name */ 3990 typedef htt_stats_sched_txq_sched_ineligibility_tlv 3991 htt_sched_txq_sched_ineligibility_tlv_v; 3992 3993 typedef enum { 3994 HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, /* Supercycle not triggered */ 3995 HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, /* forced supercycle trigger */ 3996 HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, /* Num tidq entries is less than max_client threshold */ 3997 HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, /* Num active tids is less than max_client threshold */ 3998 HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, /* max sched iteration reached */ 3999 HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, /* duration threshold reached */ 4000 HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, /* TWT supercycle trigger */ 4001 HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 4002 } htt_sched_txq_supercycle_triggers_tlv_enum; 4003 4004 #define HTT_SCHED_TXQ_SUPERCYCLE_TRIGGERS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4005 4006 /* NOTE: Variable length TLV, use length spec to infer array size */ 4007 typedef struct { 4008 htt_tlv_hdr_t tlv_hdr; 4009 /** 4010 * supercycle_triggers[] is a histogram that counts the number of 4011 * occurrences of each different reason for a transmit scheduler 4012 * supercycle to be triggered. 4013 * The htt_sched_txq_supercycle_triggers_tlv_enum is used to index 4014 * supercycle_triggers[], e.g. supercycle_triggers[1] holds the number 4015 * of times a supercycle has been forced. 4016 * These supercycle trigger counts are not automatically reset, but 4017 * are reset upon request. 4018 */ 4019 A_UINT32 supercycle_triggers[1/*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/]; 4020 } htt_stats_sched_txq_supercycle_trigger_tlv; 4021 /* preserve old name alias for new name consistent with the tag name */ 4022 typedef htt_stats_sched_txq_supercycle_trigger_tlv 4023 htt_sched_txq_supercycle_triggers_tlv_v; 4024 4025 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff 4026 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0 4027 4028 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M 0x0000ff00 4029 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S 8 4030 4031 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_GET(_var) \ 4032 (((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M) >> \ 4033 HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S) 4034 4035 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_SET(_var, _val) \ 4036 do { \ 4037 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID, _val); \ 4038 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)); \ 4039 } while (0) 4040 4041 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_GET(_var) \ 4042 (((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M) >> \ 4043 HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S) 4044 4045 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_SET(_var, _val) \ 4046 do { \ 4047 HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID, _val); \ 4048 ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)); \ 4049 } while (0) 4050 4051 typedef struct { 4052 htt_tlv_hdr_t tlv_hdr; 4053 4054 /** 4055 * BIT [ 7 : 0] :- mac_id 4056 * BIT [15 : 8] :- txq_id 4057 * BIT [31 : 16] :- reserved 4058 */ 4059 A_UINT32 mac_id__txq_id__word; 4060 /** Scheduler policy ised for this TxQ */ 4061 A_UINT32 sched_policy; 4062 /** Timestamp of last scheduler command posted */ 4063 A_UINT32 last_sched_cmd_posted_timestamp; 4064 /** Timestamp of last scheduler command completed */ 4065 A_UINT32 last_sched_cmd_compl_timestamp; 4066 /** Num of Sched2TAC ring hit Low Water Mark condition */ 4067 A_UINT32 sched_2_tac_lwm_count; 4068 /** Num of Sched2TAC ring full condition */ 4069 A_UINT32 sched_2_tac_ring_full; 4070 /** 4071 * Num of scheduler command post failures that includes SU/MU-MIMO/MU-OFDMA 4072 * sequence type 4073 */ 4074 A_UINT32 sched_cmd_post_failure; 4075 /** Num of active tids for this TxQ at current instance */ 4076 A_UINT32 num_active_tids; 4077 /** Num of powersave schedules */ 4078 A_UINT32 num_ps_schedules; 4079 /** Num of scheduler commands pending for this TxQ */ 4080 A_UINT32 sched_cmds_pending; 4081 /** Num of tidq registration for this TxQ */ 4082 A_UINT32 num_tid_register; 4083 /** Num of tidq de-registration for this TxQ */ 4084 A_UINT32 num_tid_unregister; 4085 /** Num of iterations msduq stats was updated */ 4086 A_UINT32 num_qstats_queried; 4087 /** qstats query update status */ 4088 A_UINT32 qstats_update_pending; 4089 /** Timestamp of Last query stats made */ 4090 A_UINT32 last_qstats_query_timestamp; 4091 /** Num of sched2tqm command queue full condition */ 4092 A_UINT32 num_tqm_cmdq_full; 4093 /** Num of scheduler trigger from DE Module */ 4094 A_UINT32 num_de_sched_algo_trigger; 4095 /** Num of scheduler trigger from RT Module */ 4096 A_UINT32 num_rt_sched_algo_trigger; 4097 /** Num of scheduler trigger from TQM Module */ 4098 A_UINT32 num_tqm_sched_algo_trigger; 4099 /** Num of schedules for notify frame */ 4100 A_UINT32 notify_sched; 4101 /** Duration based sendn termination */ 4102 A_UINT32 dur_based_sendn_term; 4103 /** scheduled via NOTIFY2 */ 4104 A_UINT32 su_notify2_sched; 4105 /** schedule if queued packets are greater than avg MSDUs in PPDU */ 4106 A_UINT32 su_optimal_queued_msdus_sched; 4107 /** schedule due to timeout */ 4108 A_UINT32 su_delay_timeout_sched; 4109 /** delay if txtime is less than 500us */ 4110 A_UINT32 su_min_txtime_sched_delay; 4111 /** scheduled via no delay */ 4112 A_UINT32 su_no_delay; 4113 /** Num of supercycles for this TxQ */ 4114 A_UINT32 num_supercycles; 4115 /** Num of subcycles with sort for this TxQ */ 4116 A_UINT32 num_subcycles_with_sort; 4117 /** Num of subcycles without sort for this Txq */ 4118 A_UINT32 num_subcycles_no_sort; 4119 } htt_stats_tx_pdev_scheduler_txq_stats_tlv; 4120 /* preserve old name alias for new name consistent with the tag name */ 4121 typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv 4122 htt_tx_pdev_stats_sched_per_txq_tlv; 4123 4124 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_M 0x000000ff 4125 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_S 0 4126 4127 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_GET(_var) \ 4128 (((_var) & HTT_STATS_TX_SCHED_CMN_MAC_ID_M) >> \ 4129 HTT_STATS_TX_SCHED_CMN_MAC_ID_S) 4130 4131 #define HTT_STATS_TX_SCHED_CMN_MAC_ID_SET(_var, _val) \ 4132 do { \ 4133 HTT_CHECK_SET_VAL(HTT_STATS_TX_SCHED_CMN_MAC_ID, _val); \ 4134 ((_var) |= ((_val) << HTT_STATS_TX_SCHED_CMN_MAC_ID_S)); \ 4135 } while (0) 4136 4137 typedef struct { 4138 htt_tlv_hdr_t tlv_hdr; 4139 4140 /** 4141 * BIT [ 7 : 0] :- mac_id 4142 * BIT [31 : 8] :- reserved 4143 */ 4144 A_UINT32 mac_id__word; 4145 /** Current timestamp */ 4146 A_UINT32 current_timestamp; 4147 } htt_stats_tx_sched_cmn_tlv; 4148 4149 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_SCHED 4150 * TLV_TAGS: 4151 * - HTT_STATS_TX_SCHED_CMN_TAG 4152 * - HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG 4153 * - HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG 4154 * - HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG 4155 * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG 4156 * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG 4157 * - HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG 4158 */ 4159 /* NOTE: 4160 * This structure is for documentation, and cannot be safely used directly. 4161 * Instead, use the constituent TLV structures to fill/parse. 4162 */ 4163 typedef struct { 4164 htt_stats_tx_sched_cmn_tlv cmn_tlv; 4165 struct { 4166 htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; 4167 htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; 4168 htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; 4169 htt_stats_sched_txq_sched_order_su_tlv sched_order_su_tlv; 4170 htt_stats_sched_txq_sched_ineligibility_tlv sched_ineligibility_tlv; 4171 htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; 4172 } txq[1]; 4173 } htt_stats_tx_sched_t; 4174 4175 /* == TQM STATS == */ 4176 4177 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 17 4178 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 4179 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 4180 4181 #define HTT_TX_TQM_GEN_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4182 4183 /* NOTE: Variable length TLV, use length spec to infer array size */ 4184 typedef struct { 4185 htt_tlv_hdr_t tlv_hdr; 4186 A_UINT32 gen_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 4187 } htt_stats_tx_tqm_gen_mpdu_tlv; 4188 /* preserve old name alias for new name consistent with the tag name */ 4189 typedef htt_stats_tx_tqm_gen_mpdu_tlv htt_tx_tqm_gen_mpdu_stats_tlv_v; 4190 4191 #define HTT_TX_TQM_LIST_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4192 4193 /* NOTE: Variable length TLV, use length spec to infer array size */ 4194 typedef struct { 4195 htt_tlv_hdr_t tlv_hdr; 4196 A_UINT32 list_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 4197 } htt_stats_tx_tqm_list_mpdu_tlv; 4198 /* preserve old name alias for new name consistent with the tag name */ 4199 typedef htt_stats_tx_tqm_list_mpdu_tlv htt_tx_tqm_list_mpdu_stats_tlv_v; 4200 4201 #define HTT_TX_TQM_LIST_MPDU_CNT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4202 4203 /* NOTE: Variable length TLV, use length spec to infer array size */ 4204 typedef struct { 4205 htt_tlv_hdr_t tlv_hdr; 4206 A_UINT32 list_mpdu_cnt_hist[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 4207 } htt_stats_tx_tqm_list_mpdu_cnt_tlv; 4208 /* preserve old name alias for new name consistent with the tag name */ 4209 typedef htt_stats_tx_tqm_list_mpdu_cnt_tlv htt_tx_tqm_list_mpdu_cnt_tlv_v; 4210 4211 typedef struct { 4212 htt_tlv_hdr_t tlv_hdr; 4213 A_UINT32 msdu_count; 4214 A_UINT32 mpdu_count; 4215 A_UINT32 remove_msdu; 4216 A_UINT32 remove_mpdu; 4217 A_UINT32 remove_msdu_ttl; 4218 A_UINT32 send_bar; 4219 A_UINT32 bar_sync; 4220 A_UINT32 notify_mpdu; 4221 A_UINT32 sync_cmd; 4222 A_UINT32 write_cmd; 4223 A_UINT32 hwsch_trigger; 4224 A_UINT32 ack_tlv_proc; 4225 A_UINT32 gen_mpdu_cmd; 4226 A_UINT32 gen_list_cmd; 4227 A_UINT32 remove_mpdu_cmd; 4228 A_UINT32 remove_mpdu_tried_cmd; 4229 A_UINT32 mpdu_queue_stats_cmd; 4230 A_UINT32 mpdu_head_info_cmd; 4231 A_UINT32 msdu_flow_stats_cmd; 4232 A_UINT32 remove_msdu_cmd; 4233 A_UINT32 remove_msdu_ttl_cmd; 4234 A_UINT32 flush_cache_cmd; 4235 A_UINT32 update_mpduq_cmd; 4236 A_UINT32 enqueue; 4237 A_UINT32 enqueue_notify; 4238 A_UINT32 notify_mpdu_at_head; 4239 A_UINT32 notify_mpdu_state_valid; 4240 /* 4241 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 4242 * the flow is non empty), if the number of MSDUs is greater than the threshold, 4243 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 4244 * for non-UDP MSDUs. 4245 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 4246 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 4247 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 4248 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 4249 * 4250 * Notify signifies that we trigger the scheduler. 4251 */ 4252 A_UINT32 sched_udp_notify1; 4253 A_UINT32 sched_udp_notify2; 4254 A_UINT32 sched_nonudp_notify1; 4255 A_UINT32 sched_nonudp_notify2; 4256 } htt_stats_tx_tqm_pdev_tlv; 4257 /* preserve old name alias for new name consistent with the tag name */ 4258 typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; 4259 4260 #define HTT_TX_TQM_CMN_STATS_MAC_ID_M 0x000000ff 4261 #define HTT_TX_TQM_CMN_STATS_MAC_ID_S 0 4262 4263 #define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \ 4264 (((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \ 4265 HTT_TX_TQM_CMN_STATS_MAC_ID_S) 4266 4267 #define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \ 4268 do { \ 4269 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \ 4270 ((_var) |= ((_val) << HTT_TX_TQM_CMN_STATS_MAC_ID_S)); \ 4271 } while (0) 4272 4273 typedef struct { 4274 htt_tlv_hdr_t tlv_hdr; 4275 4276 /** 4277 * BIT [ 7 : 0] :- mac_id 4278 * BIT [31 : 8] :- reserved 4279 */ 4280 A_UINT32 mac_id__word; 4281 A_UINT32 max_cmdq_id; 4282 A_UINT32 list_mpdu_cnt_hist_intvl; 4283 4284 /* Global stats */ 4285 A_UINT32 add_msdu; 4286 A_UINT32 q_empty; 4287 A_UINT32 q_not_empty; 4288 A_UINT32 drop_notification; 4289 A_UINT32 desc_threshold; 4290 A_UINT32 hwsch_tqm_invalid_status; 4291 A_UINT32 missed_tqm_gen_mpdus; 4292 A_UINT32 tqm_active_tids; 4293 A_UINT32 tqm_inactive_tids; 4294 A_UINT32 tqm_active_msduq_flows; 4295 4296 /* SAWF system delay reference timestamp updation related stats */ 4297 A_UINT32 total_msduq_timestamp_updates; 4298 A_UINT32 total_msduq_timestamp_updates_by_get_mpdu_head_info_cmd; 4299 A_UINT32 total_msduq_timestamp_updates_by_empty_to_nonempty_status; 4300 A_UINT32 total_get_mpdu_head_info_cmds_by_sched_algo_la_query; 4301 A_UINT32 total_get_mpdu_head_info_cmds_by_tac; 4302 A_UINT32 total_gen_mpdu_cmds_by_sched_algo_la_query; 4303 A_UINT32 high_prio_q_not_empty; 4304 } htt_stats_tx_tqm_cmn_tlv; 4305 /* preserve old name alias for new name consistent with the tag name */ 4306 typedef htt_stats_tx_tqm_cmn_tlv htt_tx_tqm_cmn_stats_tlv; 4307 4308 typedef struct { 4309 htt_tlv_hdr_t tlv_hdr; 4310 /* Error stats */ 4311 A_UINT32 q_empty_failure; 4312 A_UINT32 q_not_empty_failure; 4313 A_UINT32 add_msdu_failure; 4314 4315 /* TQM reset debug stats */ 4316 A_UINT32 tqm_cache_ctl_err; 4317 A_UINT32 tqm_soft_reset; 4318 A_UINT32 tqm_reset_total_num_in_use_link_descs; 4319 A_UINT32 tqm_reset_worst_case_num_lost_link_descs; 4320 A_UINT32 tqm_reset_worst_case_num_lost_host_tx_bufs_count; 4321 A_UINT32 tqm_reset_num_in_use_link_descs_internal_tqm; 4322 A_UINT32 tqm_reset_num_in_use_link_descs_wbm_idle_link_ring; 4323 A_UINT32 tqm_reset_time_to_tqm_hang_delta_ms; 4324 A_UINT32 tqm_reset_recovery_time_ms; 4325 A_UINT32 tqm_reset_num_peers_hdl; 4326 A_UINT32 tqm_reset_cumm_dirty_hw_mpduq_proc_cnt; 4327 A_UINT32 tqm_reset_cumm_dirty_hw_msduq_proc; 4328 A_UINT32 tqm_reset_flush_cache_cmd_su_cnt; 4329 A_UINT32 tqm_reset_flush_cache_cmd_other_cnt; 4330 A_UINT32 tqm_reset_flush_cache_cmd_trig_type; 4331 A_UINT32 tqm_reset_flush_cache_cmd_trig_cfg; 4332 A_UINT32 tqm_reset_flush_cache_cmd_skip_cmd_status_null; 4333 } htt_stats_tx_tqm_error_stats_tlv; 4334 /* preserve old name alias for new name consistent with the tag name */ 4335 typedef htt_stats_tx_tqm_error_stats_tlv htt_tx_tqm_error_stats_tlv; 4336 4337 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TQM 4338 * TLV_TAGS: 4339 * - HTT_STATS_TX_TQM_CMN_TAG 4340 * - HTT_STATS_TX_TQM_ERROR_STATS_TAG 4341 * - HTT_STATS_TX_TQM_GEN_MPDU_TAG 4342 * - HTT_STATS_TX_TQM_LIST_MPDU_TAG 4343 * - HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG 4344 * - HTT_STATS_TX_TQM_PDEV_TAG 4345 */ 4346 /* NOTE: 4347 * This structure is for documentation, and cannot be safely used directly. 4348 * Instead, use the constituent TLV structures to fill/parse. 4349 */ 4350 typedef struct { 4351 htt_stats_tx_tqm_cmn_tlv cmn_tlv; 4352 htt_stats_tx_tqm_error_stats_tlv err_tlv; 4353 htt_stats_tx_tqm_gen_mpdu_tlv gen_mpdu_stats_tlv; 4354 htt_stats_tx_tqm_list_mpdu_tlv list_mpdu_stats_tlv; 4355 htt_stats_tx_tqm_list_mpdu_cnt_tlv list_mpdu_cnt_tlv; 4356 htt_stats_tx_tqm_pdev_tlv tqm_pdev_stats_tlv; 4357 } htt_tx_tqm_pdev_stats_t; 4358 4359 /* == TQM CMDQ stats == */ 4360 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M 0x000000ff 4361 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S 0 4362 4363 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M 0x0000ff00 4364 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S 8 4365 4366 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ 4367 (((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \ 4368 HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S) 4369 4370 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \ 4371 do { \ 4372 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \ 4373 ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)); \ 4374 } while (0) 4375 4376 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ 4377 (((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \ 4378 HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S) 4379 4380 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \ 4381 do { \ 4382 HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \ 4383 ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)); \ 4384 } while (0) 4385 4386 typedef struct { 4387 htt_tlv_hdr_t tlv_hdr; 4388 4389 /* 4390 * BIT [ 7 : 0] :- mac_id 4391 * BIT [15 : 8] :- cmdq_id 4392 * BIT [31 : 16] :- reserved 4393 */ 4394 A_UINT32 mac_id__cmdq_id__word; 4395 A_UINT32 sync_cmd; 4396 A_UINT32 write_cmd; 4397 A_UINT32 gen_mpdu_cmd; 4398 A_UINT32 mpdu_queue_stats_cmd; 4399 A_UINT32 mpdu_head_info_cmd; 4400 A_UINT32 msdu_flow_stats_cmd; 4401 A_UINT32 remove_mpdu_cmd; 4402 A_UINT32 remove_msdu_cmd; 4403 A_UINT32 flush_cache_cmd; 4404 A_UINT32 update_mpduq_cmd; 4405 A_UINT32 update_msduq_cmd; 4406 } htt_stats_tx_tqm_cmdq_status_tlv; 4407 /* preserve old name alias for new name consistent with the tag name */ 4408 typedef htt_stats_tx_tqm_cmdq_status_tlv htt_tx_tqm_cmdq_status_tlv; 4409 4410 /* STATS_TYPE : HTT_DBG_EXT_STATS_TQM_CMDQ 4411 * TLV_TAGS: 4412 * - HTT_STATS_STRING_TAG 4413 * - HTT_STATS_TX_TQM_CMDQ_STATUS_TAG 4414 */ 4415 /* NOTE: 4416 * This structure is for documentation, and cannot be safely used directly. 4417 * Instead, use the constituent TLV structures to fill/parse. 4418 */ 4419 typedef struct { 4420 struct { 4421 htt_stats_string_tlv cmdq_str_tlv; 4422 htt_stats_tx_tqm_cmdq_status_tlv status_tlv; 4423 } q[1]; 4424 } htt_tx_tqm_cmdq_stats_t; 4425 4426 /* == TX-DE STATS == */ 4427 4428 /* Structures for tx de stats */ 4429 typedef struct { 4430 htt_tlv_hdr_t tlv_hdr; 4431 A_UINT32 m1_packets; 4432 A_UINT32 m2_packets; 4433 A_UINT32 m3_packets; 4434 A_UINT32 m4_packets; 4435 A_UINT32 g1_packets; 4436 A_UINT32 g2_packets; 4437 A_UINT32 rc4_packets; 4438 A_UINT32 eap_packets; 4439 A_UINT32 eapol_start_packets; 4440 A_UINT32 eapol_logoff_packets; 4441 A_UINT32 eapol_encap_asf_packets; 4442 } htt_stats_tx_de_eapol_packets_tlv; 4443 /* preserve old name alias for new name consistent with the tag name */ 4444 typedef htt_stats_tx_de_eapol_packets_tlv htt_tx_de_eapol_packets_stats_tlv; 4445 4446 typedef struct { 4447 htt_tlv_hdr_t tlv_hdr; 4448 A_UINT32 ap_bss_peer_not_found; 4449 A_UINT32 ap_bcast_mcast_no_peer; 4450 A_UINT32 sta_delete_in_progress; 4451 A_UINT32 ibss_no_bss_peer; 4452 A_UINT32 invaild_vdev_type; 4453 A_UINT32 invalid_ast_peer_entry; 4454 A_UINT32 peer_entry_invalid; 4455 A_UINT32 ethertype_not_ip; 4456 A_UINT32 eapol_lookup_failed; 4457 A_UINT32 qpeer_not_allow_data; 4458 A_UINT32 fse_tid_override; 4459 A_UINT32 ipv6_jumbogram_zero_length; 4460 A_UINT32 qos_to_non_qos_in_prog; 4461 A_UINT32 ap_bcast_mcast_eapol; 4462 A_UINT32 unicast_on_ap_bss_peer; 4463 A_UINT32 ap_vdev_invalid; 4464 A_UINT32 incomplete_llc; 4465 A_UINT32 eapol_duplicate_m3; 4466 A_UINT32 eapol_duplicate_m4; 4467 } htt_stats_tx_de_classify_failed_tlv; 4468 /* preserve old name alias for new name consistent with the tag name */ 4469 typedef htt_stats_tx_de_classify_failed_tlv htt_tx_de_classify_failed_stats_tlv; 4470 4471 typedef struct { 4472 htt_tlv_hdr_t tlv_hdr; 4473 A_UINT32 arp_packets; 4474 A_UINT32 igmp_packets; 4475 A_UINT32 dhcp_packets; 4476 A_UINT32 host_inspected; 4477 A_UINT32 htt_included; 4478 A_UINT32 htt_valid_mcs; 4479 A_UINT32 htt_valid_nss; 4480 A_UINT32 htt_valid_preamble_type; 4481 A_UINT32 htt_valid_chainmask; 4482 A_UINT32 htt_valid_guard_interval; 4483 A_UINT32 htt_valid_retries; 4484 A_UINT32 htt_valid_bw_info; 4485 A_UINT32 htt_valid_power; 4486 A_UINT32 htt_valid_key_flags; 4487 A_UINT32 htt_valid_no_encryption; 4488 A_UINT32 fse_entry_count; 4489 A_UINT32 fse_priority_be; 4490 A_UINT32 fse_priority_high; 4491 A_UINT32 fse_priority_low; 4492 A_UINT32 fse_traffic_ptrn_be; 4493 A_UINT32 fse_traffic_ptrn_over_sub; 4494 A_UINT32 fse_traffic_ptrn_bursty; 4495 A_UINT32 fse_traffic_ptrn_interactive; 4496 A_UINT32 fse_traffic_ptrn_periodic; 4497 A_UINT32 fse_hwqueue_alloc; 4498 A_UINT32 fse_hwqueue_created; 4499 A_UINT32 fse_hwqueue_send_to_host; 4500 A_UINT32 mcast_entry; 4501 A_UINT32 bcast_entry; 4502 A_UINT32 htt_update_peer_cache; 4503 A_UINT32 htt_learning_frame; 4504 A_UINT32 fse_invalid_peer; 4505 /** 4506 * mec_notify is HTT TX WBM multicast echo check notification 4507 * from firmware to host. FW sends SA addresses to host for all 4508 * multicast/broadcast packets received on STA side. 4509 */ 4510 A_UINT32 mec_notify; 4511 A_UINT32 arp_response; 4512 A_UINT32 arp_request; 4513 } htt_stats_tx_de_classify_stats_tlv; 4514 /* preserve old name alias for new name consistent with the tag name */ 4515 typedef htt_stats_tx_de_classify_stats_tlv htt_tx_de_classify_stats_tlv; 4516 4517 typedef struct { 4518 htt_tlv_hdr_t tlv_hdr; 4519 A_UINT32 eok; 4520 A_UINT32 classify_done; 4521 A_UINT32 lookup_failed; 4522 A_UINT32 send_host_dhcp; 4523 A_UINT32 send_host_mcast; 4524 A_UINT32 send_host_unknown_dest; 4525 A_UINT32 send_host; 4526 A_UINT32 status_invalid; 4527 } htt_stats_tx_de_classify_status_tlv; 4528 /* preserve old name alias for new name consistent with the tag name */ 4529 typedef htt_stats_tx_de_classify_status_tlv htt_tx_de_classify_status_stats_tlv; 4530 4531 typedef struct { 4532 htt_tlv_hdr_t tlv_hdr; 4533 A_UINT32 enqueued_pkts; 4534 A_UINT32 to_tqm; 4535 A_UINT32 to_tqm_bypass; 4536 } htt_stats_tx_de_enqueue_packets_tlv; 4537 /* preserve old name alias for new name consistent with the tag name */ 4538 typedef htt_stats_tx_de_enqueue_packets_tlv htt_tx_de_enqueue_packets_stats_tlv; 4539 4540 typedef struct { 4541 htt_tlv_hdr_t tlv_hdr; 4542 A_UINT32 discarded_pkts; 4543 A_UINT32 local_frames; 4544 A_UINT32 is_ext_msdu; 4545 } htt_stats_tx_de_enqueue_discard_tlv; 4546 /* preserve old name alias for new name consistent with the tag name */ 4547 typedef htt_stats_tx_de_enqueue_discard_tlv htt_tx_de_enqueue_discard_stats_tlv; 4548 4549 typedef struct { 4550 htt_tlv_hdr_t tlv_hdr; 4551 A_UINT32 tcl_dummy_frame; 4552 A_UINT32 tqm_dummy_frame; 4553 A_UINT32 tqm_notify_frame; 4554 A_UINT32 fw2wbm_enq; 4555 A_UINT32 tqm_bypass_frame; 4556 } htt_stats_tx_de_compl_stats_tlv; 4557 /* preserve old name alias for new name consistent with the tag name */ 4558 typedef htt_stats_tx_de_compl_stats_tlv htt_tx_de_compl_stats_tlv; 4559 4560 #define HTT_TX_DE_CMN_STATS_MAC_ID_M 0x000000ff 4561 #define HTT_TX_DE_CMN_STATS_MAC_ID_S 0 4562 4563 #define HTT_TX_DE_CMN_STATS_MAC_ID_GET(_var) \ 4564 (((_var) & HTT_TX_DE_CMN_STATS_MAC_ID_M) >> \ 4565 HTT_TX_DE_CMN_STATS_MAC_ID_S) 4566 4567 #define HTT_TX_DE_CMN_STATS_MAC_ID_SET(_var, _val) \ 4568 do { \ 4569 HTT_CHECK_SET_VAL(HTT_TX_DE_CMN_STATS_MAC_ID, _val); \ 4570 ((_var) |= ((_val) << HTT_TX_DE_CMN_STATS_MAC_ID_S)); \ 4571 } while (0) 4572 4573 /* 4574 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 4575 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 4576 * ring,which may fail, due to non availability of buffer. Hence we sleep for 4577 * 200us & again request for it. This is a histogram of time we wait, with 4578 * bin of 200ms & there are 10 bin (2 seconds max) 4579 * They are defined by the following macros in FW 4580 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 4581 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 4582 * ENTRIES_PER_BIN_COUNT) 4583 */ 4584 typedef struct { 4585 htt_tlv_hdr_t tlv_hdr; 4586 4587 A_UINT32 fw2wbm_ring_full_hist[1]; 4588 } htt_stats_tx_de_fw2wbm_ring_full_hist_tlv; 4589 /* preserve old name alias for new name consistent with the tag name */ 4590 typedef htt_stats_tx_de_fw2wbm_ring_full_hist_tlv 4591 htt_tx_de_fw2wbm_ring_full_hist_tlv; 4592 4593 typedef struct { 4594 htt_tlv_hdr_t tlv_hdr; 4595 /** 4596 * BIT [ 7 : 0] :- mac_id 4597 * BIT [31 : 8] :- reserved 4598 */ 4599 A_UINT32 mac_id__word; 4600 4601 /* Global Stats */ 4602 A_UINT32 tcl2fw_entry_count; 4603 A_UINT32 not_to_fw; 4604 A_UINT32 invalid_pdev_vdev_peer; 4605 A_UINT32 tcl_res_invalid_addrx; 4606 A_UINT32 wbm2fw_entry_count; 4607 A_UINT32 invalid_pdev; 4608 A_UINT32 tcl_res_addrx_timeout; 4609 A_UINT32 invalid_vdev; 4610 A_UINT32 invalid_tcl_exp_frame_desc; 4611 A_UINT32 vdev_id_mismatch_cnt; 4612 } htt_stats_tx_de_cmn_tlv; 4613 /* preserve old name alias for new name consistent with the tag name */ 4614 typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv; 4615 4616 #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0) & 0xffff) 4617 #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff) 4618 4619 /* Rx debug info for status rings */ 4620 typedef struct { 4621 htt_tlv_hdr_t tlv_hdr; 4622 /** 4623 * BIT [15 : 0] :- max possible number of entries in respective ring 4624 * (size of the ring in terms of entries) 4625 * BIT [16 : 31] :- current number of entries occupied in respective ring 4626 */ 4627 A_UINT32 entry_status_sw2rxdma; 4628 A_UINT32 entry_status_rxdma2reo; 4629 A_UINT32 entry_status_reo2sw1; 4630 A_UINT32 entry_status_reo2sw4; 4631 A_UINT32 entry_status_refillringipa; 4632 A_UINT32 entry_status_refillringhost; 4633 /** datarate - Moving Average of Number of Entries */ 4634 A_UINT32 datarate_refillringipa; 4635 A_UINT32 datarate_refillringhost; 4636 /** 4637 * refillringhost_backpress_hist and refillringipa_backpress_hist are 4638 * deprecated, and will be filled with 0x0 by the target. 4639 */ 4640 A_UINT32 refillringhost_backpress_hist[3]; 4641 A_UINT32 refillringipa_backpress_hist[3]; 4642 /** 4643 * Number of times reo2sw4(IPA_DEST_RING) ring is back-pressured 4644 * in recent time periods 4645 * element 0: in last 0 to 250ms 4646 * element 1: 250ms to 500ms 4647 * element 2: above 500ms 4648 */ 4649 A_UINT32 reo2sw4ringipa_backpress_hist[3]; 4650 } htt_stats_rx_ring_stats_tlv; 4651 /* preserve old name alias for new name consistent with the tag name */ 4652 typedef htt_stats_rx_ring_stats_tlv htt_rx_fw_ring_stats_tlv_v; 4653 4654 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_DE_INFO 4655 * TLV_TAGS: 4656 * - HTT_STATS_TX_DE_CMN_TAG 4657 * - HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG 4658 * - HTT_STATS_TX_DE_EAPOL_PACKETS_TAG 4659 * - HTT_STATS_TX_DE_CLASSIFY_STATS_TAG 4660 * - HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG 4661 * - HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG 4662 * - HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG 4663 * - HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG 4664 * - HTT_STATS_TX_DE_COMPL_STATS_TAG 4665 */ 4666 /* NOTE: 4667 * This structure is for documentation, and cannot be safely used directly. 4668 * Instead, use the constituent TLV structures to fill/parse. 4669 */ 4670 typedef struct { 4671 htt_stats_tx_de_cmn_tlv cmn_tlv; 4672 htt_stats_tx_de_fw2wbm_ring_full_hist_tlv fw2wbm_hist_tlv; 4673 htt_stats_tx_de_eapol_packets_tlv eapol_stats_tlv; 4674 htt_stats_tx_de_classify_stats_tlv classify_stats_tlv; 4675 htt_stats_tx_de_classify_failed_tlv classify_failed_tlv; 4676 htt_stats_tx_de_classify_status_tlv classify_status_rlv; 4677 htt_stats_tx_de_enqueue_packets_tlv enqueue_packets_tlv; 4678 htt_stats_tx_de_enqueue_discard_tlv enqueue_discard_tlv; 4679 htt_stats_tx_de_compl_stats_tlv comp_status_tlv; 4680 } htt_tx_de_stats_t; 4681 4682 /* == RING-IF STATS == */ 4683 /* DWORD num_elems__prefetch_tail_idx */ 4684 #define HTT_RING_IF_STATS_NUM_ELEMS_M 0x0000ffff 4685 #define HTT_RING_IF_STATS_NUM_ELEMS_S 0 4686 4687 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M 0xffff0000 4688 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S 16 4689 4690 #define HTT_RING_IF_STATS_NUM_ELEMS_GET(_var) \ 4691 (((_var) & HTT_RING_IF_STATS_NUM_ELEMS_M) >> \ 4692 HTT_RING_IF_STATS_NUM_ELEMS_S) 4693 4694 #define HTT_RING_IF_STATS_NUM_ELEMS_SET(_var, _val) \ 4695 do { \ 4696 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_NUM_ELEMS, _val); \ 4697 ((_var) |= ((_val) << HTT_RING_IF_STATS_NUM_ELEMS_S)); \ 4698 } while (0) 4699 4700 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_GET(_var) \ 4701 (((_var) & HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M) >> \ 4702 HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S) 4703 4704 #define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_SET(_var, _val) \ 4705 do { \ 4706 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_PREFETCH_TAIL_IDX, _val); \ 4707 ((_var) |= ((_val) << HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)); \ 4708 } while (0) 4709 4710 /* DWORD head_idx__tail_idx */ 4711 #define HTT_RING_IF_STATS_HEAD_IDX_M 0x0000ffff 4712 #define HTT_RING_IF_STATS_HEAD_IDX_S 0 4713 4714 #define HTT_RING_IF_STATS_TAIL_IDX_M 0xffff0000 4715 #define HTT_RING_IF_STATS_TAIL_IDX_S 16 4716 4717 #define HTT_RING_IF_STATS_HEAD_IDX_GET(_var) \ 4718 (((_var) & HTT_RING_IF_STATS_HEAD_IDX_M) >> \ 4719 HTT_RING_IF_STATS_HEAD_IDX_S) 4720 4721 #define HTT_RING_IF_STATS_HEAD_IDX_SET(_var, _val) \ 4722 do { \ 4723 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HEAD_IDX, _val); \ 4724 ((_var) |= ((_val) << HTT_RING_IF_STATS_HEAD_IDX_S)); \ 4725 } while (0) 4726 4727 #define HTT_RING_IF_STATS_TAIL_IDX_GET(_var) \ 4728 (((_var) & HTT_RING_IF_STATS_TAIL_IDX_M) >> \ 4729 HTT_RING_IF_STATS_TAIL_IDX_S) 4730 4731 #define HTT_RING_IF_STATS_TAIL_IDX_SET(_var, _val) \ 4732 do { \ 4733 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_TAIL_IDX, _val); \ 4734 ((_var) |= ((_val) << HTT_RING_IF_STATS_TAIL_IDX_S)); \ 4735 } while (0) 4736 4737 /* DWORD shadow_head_idx__shadow_tail_idx */ 4738 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M 0x0000ffff 4739 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S 0 4740 4741 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M 0xffff0000 4742 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S 16 4743 4744 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_GET(_var) \ 4745 (((_var) & HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M) >> \ 4746 HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S) 4747 4748 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_SET(_var, _val) \ 4749 do { \ 4750 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_HEAD_IDX, _val); \ 4751 ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)); \ 4752 } while (0) 4753 4754 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_GET(_var) \ 4755 (((_var) & HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M) >> \ 4756 HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S) 4757 4758 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_SET(_var, _val) \ 4759 do { \ 4760 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_TAIL_IDX, _val); \ 4761 ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)); \ 4762 } while (0) 4763 4764 /* DWORD lwm_thresh__hwm_thresh */ 4765 #define HTT_RING_IF_STATS_LWM_THRESHOLD_M 0x0000ffff 4766 #define HTT_RING_IF_STATS_LWM_THRESHOLD_S 0 4767 4768 #define HTT_RING_IF_STATS_HWM_THRESHOLD_M 0xffff0000 4769 #define HTT_RING_IF_STATS_HWM_THRESHOLD_S 16 4770 4771 #define HTT_RING_IF_STATS_LWM_THRESHOLD_GET(_var) \ 4772 (((_var) & HTT_RING_IF_STATS_LWM_THRESHOLD_M) >> \ 4773 HTT_RING_IF_STATS_LWM_THRESHOLD_S) 4774 4775 #define HTT_RING_IF_STATS_LWM_THRESHOLD_SET(_var, _val) \ 4776 do { \ 4777 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_LWM_THRESHOLD, _val); \ 4778 ((_var) |= ((_val) << HTT_RING_IF_STATS_LWM_THRESHOLD_S)); \ 4779 } while (0) 4780 4781 #define HTT_RING_IF_STATS_HWM_THRESHOLD_GET(_var) \ 4782 (((_var) & HTT_RING_IF_STATS_HWM_THRESHOLD_M) >> \ 4783 HTT_RING_IF_STATS_HWM_THRESHOLD_S) 4784 4785 #define HTT_RING_IF_STATS_HWM_THRESHOLD_SET(_var, _val) \ 4786 do { \ 4787 HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HWM_THRESHOLD, _val); \ 4788 ((_var) |= ((_val) << HTT_RING_IF_STATS_HWM_THRESHOLD_S)); \ 4789 } while (0) 4790 4791 #define HTT_STATS_LOW_WM_BINS 5 4792 #define HTT_STATS_HIGH_WM_BINS 5 4793 4794 typedef struct { 4795 /** DWORD aligned base memory address of the ring */ 4796 A_UINT32 base_addr; 4797 4798 /** size of each ring element */ 4799 A_UINT32 elem_size; 4800 4801 /** 4802 * BIT [15 : 0] :- num_elems 4803 * BIT [31 : 16] :- prefetch_tail_idx 4804 */ 4805 A_UINT32 num_elems__prefetch_tail_idx; 4806 /** 4807 * BIT [15 : 0] :- head_idx 4808 * BIT [31 : 16] :- tail_idx 4809 */ 4810 A_UINT32 head_idx__tail_idx; 4811 /** 4812 * BIT [15 : 0] :- shadow_head_idx 4813 * BIT [31 : 16] :- shadow_tail_idx 4814 */ 4815 A_UINT32 shadow_head_idx__shadow_tail_idx; 4816 A_UINT32 num_tail_incr; 4817 /** 4818 * BIT [15 : 0] :- lwm_thresh 4819 * BIT [31 : 16] :- hwm_thresh 4820 */ 4821 A_UINT32 lwm_thresh__hwm_thresh; 4822 A_UINT32 overrun_hit_count; 4823 A_UINT32 underrun_hit_count; 4824 A_UINT32 prod_blockwait_count; 4825 A_UINT32 cons_blockwait_count; 4826 A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 4827 A_UINT32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 4828 } htt_stats_ring_if_tlv; 4829 /* preserve old name alias for new name consistent with the tag name */ 4830 typedef htt_stats_ring_if_tlv htt_ring_if_stats_tlv; 4831 4832 #define HTT_RING_IF_CMN_MAC_ID_M 0x000000ff 4833 #define HTT_RING_IF_CMN_MAC_ID_S 0 4834 4835 #define HTT_RING_IF_CMN_MAC_ID_GET(_var) \ 4836 (((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \ 4837 HTT_RING_IF_CMN_MAC_ID_S) 4838 4839 #define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \ 4840 do { \ 4841 HTT_CHECK_SET_VAL(HTT_RING_IF_CMN_MAC_ID, _val); \ 4842 ((_var) |= ((_val) << HTT_RING_IF_CMN_MAC_ID_S)); \ 4843 } while (0) 4844 4845 typedef struct { 4846 htt_tlv_hdr_t tlv_hdr; 4847 4848 /** 4849 * BIT [ 7 : 0] :- mac_id 4850 * BIT [31 : 8] :- reserved 4851 */ 4852 A_UINT32 mac_id__word; 4853 A_UINT32 num_records; 4854 } htt_stats_ring_if_cmn_tlv; 4855 /* preserve old name alias for new name consistent with the tag name */ 4856 typedef htt_stats_ring_if_cmn_tlv htt_ring_if_cmn_tlv; 4857 4858 /* STATS_TYPE : HTT_DBG_EXT_STATS_RING_IF_INFO 4859 * TLV_TAGS: 4860 * - HTT_STATS_RING_IF_CMN_TAG 4861 * - HTT_STATS_STRING_TAG 4862 * - HTT_STATS_RING_IF_TAG 4863 */ 4864 /* NOTE: 4865 * This structure is for documentation, and cannot be safely used directly. 4866 * Instead, use the constituent TLV structures to fill/parse. 4867 */ 4868 typedef struct { 4869 htt_stats_ring_if_cmn_tlv cmn_tlv; 4870 /** Variable based on the Number of records. */ 4871 struct { 4872 htt_stats_string_tlv ring_str_tlv; 4873 htt_stats_ring_if_tlv ring_tlv; 4874 } r[1]; 4875 } htt_ring_if_stats_t; 4876 4877 /* == SFM STATS == */ 4878 4879 #define HTT_SFM_CLIENT_USER_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 4880 4881 /* NOTE: Variable length TLV, use length spec to infer array size */ 4882 typedef struct { 4883 htt_tlv_hdr_t tlv_hdr; 4884 /** Number of DWORDS used per user and per client */ 4885 A_UINT32 dwords_used_by_user_n[1]; 4886 } htt_stats_sfm_client_user_tlv; 4887 /* preserve old name alias for new name consistent with the tag name */ 4888 typedef htt_stats_sfm_client_user_tlv htt_sfm_client_user_tlv_v; 4889 4890 typedef struct { 4891 htt_tlv_hdr_t tlv_hdr; 4892 /** Client ID */ 4893 A_UINT32 client_id; 4894 /** Minimum number of buffers */ 4895 A_UINT32 buf_min; 4896 /** Maximum number of buffers */ 4897 A_UINT32 buf_max; 4898 /** Number of Busy buffers */ 4899 A_UINT32 buf_busy; 4900 /** Number of Allocated buffers */ 4901 A_UINT32 buf_alloc; 4902 /** Number of Available/Usable buffers */ 4903 A_UINT32 buf_avail; 4904 /** Number of users */ 4905 A_UINT32 num_users; 4906 } htt_stats_sfm_client_tlv; 4907 /* preserve old name alias for new name consistent with the tag name */ 4908 typedef htt_stats_sfm_client_tlv htt_sfm_client_tlv; 4909 4910 #define HTT_SFM_CMN_MAC_ID_M 0x000000ff 4911 #define HTT_SFM_CMN_MAC_ID_S 0 4912 4913 #define HTT_SFM_CMN_MAC_ID_GET(_var) \ 4914 (((_var) & HTT_SFM_CMN_MAC_ID_M) >> \ 4915 HTT_SFM_CMN_MAC_ID_S) 4916 4917 #define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \ 4918 do { \ 4919 HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \ 4920 ((_var) |= ((_val) << HTT_SFM_CMN_MAC_ID_S)); \ 4921 } while (0) 4922 4923 typedef struct { 4924 htt_tlv_hdr_t tlv_hdr; 4925 4926 /** 4927 * BIT [ 7 : 0] :- mac_id 4928 * BIT [31 : 8] :- reserved 4929 */ 4930 A_UINT32 mac_id__word; 4931 /** 4932 * Indicates the total number of 128 byte buffers in the CMEM 4933 * that are available for buffer sharing 4934 */ 4935 A_UINT32 buf_total; 4936 /** 4937 * Indicates for certain client or all the clients there is no 4938 * dword saved in SFM, refer to SFM_R1_MEM_EMPTY 4939 */ 4940 A_UINT32 mem_empty; 4941 /** DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 4942 A_UINT32 deallocate_bufs; 4943 /** Number of Records */ 4944 A_UINT32 num_records; 4945 } htt_stats_sfm_cmn_tlv; 4946 /* preserve old name alias for new name consistent with the tag name */ 4947 typedef htt_stats_sfm_cmn_tlv htt_sfm_cmn_tlv; 4948 4949 /* STATS_TYPE : HTT_DBG_EXT_STATS_RING_IF_INFO 4950 * TLV_TAGS: 4951 * - HTT_STATS_SFM_CMN_TAG 4952 * - HTT_STATS_STRING_TAG 4953 * - HTT_STATS_SFM_CLIENT_TAG 4954 * - HTT_STATS_SFM_CLIENT_USER_TAG 4955 */ 4956 /* NOTE: 4957 * This structure is for documentation, and cannot be safely used directly. 4958 * Instead, use the constituent TLV structures to fill/parse. 4959 */ 4960 typedef struct { 4961 htt_stats_sfm_cmn_tlv cmn_tlv; 4962 /** Variable based on the Number of records. */ 4963 struct { 4964 htt_stats_string_tlv client_str_tlv; 4965 htt_stats_sfm_client_tlv client_tlv; 4966 htt_stats_sfm_client_user_tlv user_tlv; 4967 } r[1]; 4968 } htt_sfm_stats_t; 4969 4970 /* == SRNG STATS == */ 4971 /* DWORD mac_id__ring_id__arena__ep */ 4972 #define HTT_SRING_STATS_MAC_ID_M 0x000000ff 4973 #define HTT_SRING_STATS_MAC_ID_S 0 4974 4975 #define HTT_SRING_STATS_RING_ID_M 0x0000ff00 4976 #define HTT_SRING_STATS_RING_ID_S 8 4977 4978 #define HTT_SRING_STATS_ARENA_M 0x00ff0000 4979 #define HTT_SRING_STATS_ARENA_S 16 4980 4981 #define HTT_SRING_STATS_EP_TYPE_M 0x01000000 4982 #define HTT_SRING_STATS_EP_TYPE_S 24 4983 4984 #define HTT_SRING_STATS_MAC_ID_GET(_var) \ 4985 (((_var) & HTT_SRING_STATS_MAC_ID_M) >> \ 4986 HTT_SRING_STATS_MAC_ID_S) 4987 4988 #define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \ 4989 do { \ 4990 HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \ 4991 ((_var) |= ((_val) << HTT_SRING_STATS_MAC_ID_S)); \ 4992 } while (0) 4993 4994 #define HTT_SRING_STATS_RING_ID_GET(_var) \ 4995 (((_var) & HTT_SRING_STATS_RING_ID_M) >> \ 4996 HTT_SRING_STATS_RING_ID_S) 4997 4998 #define HTT_SRING_STATS_RING_ID_SET(_var, _val) \ 4999 do { \ 5000 HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \ 5001 ((_var) |= ((_val) << HTT_SRING_STATS_RING_ID_S)); \ 5002 } while (0) 5003 5004 #define HTT_SRING_STATS_ARENA_GET(_var) \ 5005 (((_var) & HTT_SRING_STATS_ARENA_M) >> \ 5006 HTT_SRING_STATS_ARENA_S) 5007 5008 #define HTT_SRING_STATS_ARENA_SET(_var, _val) \ 5009 do { \ 5010 HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \ 5011 ((_var) |= ((_val) << HTT_SRING_STATS_ARENA_S)); \ 5012 } while (0) 5013 5014 #define HTT_SRING_STATS_EP_TYPE_GET(_var) \ 5015 (((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \ 5016 HTT_SRING_STATS_EP_TYPE_S) 5017 5018 #define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \ 5019 do { \ 5020 HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \ 5021 ((_var) |= ((_val) << HTT_SRING_STATS_EP_TYPE_S)); \ 5022 } while (0) 5023 5024 /* DWORD num_avail_words__num_valid_words */ 5025 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_M 0x0000ffff 5026 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_S 0 5027 5028 #define HTT_SRING_STATS_NUM_VALID_WORDS_M 0xffff0000 5029 #define HTT_SRING_STATS_NUM_VALID_WORDS_S 16 5030 5031 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ 5032 (((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \ 5033 HTT_SRING_STATS_NUM_AVAIL_WORDS_S) 5034 5035 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \ 5036 do { \ 5037 HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \ 5038 ((_var) |= ((_val) << HTT_SRING_STATS_NUM_AVAIL_WORDS_S)); \ 5039 } while (0) 5040 5041 #define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ 5042 (((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \ 5043 HTT_SRING_STATS_NUM_VALID_WORDS_S) 5044 5045 #define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \ 5046 do { \ 5047 HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \ 5048 ((_var) |= ((_val) << HTT_SRING_STATS_NUM_VALID_WORDS_S)); \ 5049 } while (0) 5050 5051 /* DWORD head_ptr__tail_ptr */ 5052 #define HTT_SRING_STATS_HEAD_PTR_M 0x0000ffff 5053 #define HTT_SRING_STATS_HEAD_PTR_S 0 5054 5055 #define HTT_SRING_STATS_TAIL_PTR_M 0xffff0000 5056 #define HTT_SRING_STATS_TAIL_PTR_S 16 5057 5058 #define HTT_SRING_STATS_HEAD_PTR_GET(_var) \ 5059 (((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \ 5060 HTT_SRING_STATS_HEAD_PTR_S) 5061 5062 #define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \ 5063 do { \ 5064 HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \ 5065 ((_var) |= ((_val) << HTT_SRING_STATS_HEAD_PTR_S)); \ 5066 } while (0) 5067 5068 #define HTT_SRING_STATS_TAIL_PTR_GET(_var) \ 5069 (((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \ 5070 HTT_SRING_STATS_TAIL_PTR_S) 5071 5072 #define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \ 5073 do { \ 5074 HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \ 5075 ((_var) |= ((_val) << HTT_SRING_STATS_TAIL_PTR_S)); \ 5076 } while (0) 5077 5078 /* DWORD consumer_empty__producer_full */ 5079 #define HTT_SRING_STATS_CONSUMER_EMPTY_M 0x0000ffff 5080 #define HTT_SRING_STATS_CONSUMER_EMPTY_S 0 5081 5082 #define HTT_SRING_STATS_PRODUCER_FULL_M 0xffff0000 5083 #define HTT_SRING_STATS_PRODUCER_FULL_S 16 5084 5085 #define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ 5086 (((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \ 5087 HTT_SRING_STATS_CONSUMER_EMPTY_S) 5088 5089 #define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \ 5090 do { \ 5091 HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \ 5092 ((_var) |= ((_val) << HTT_SRING_STATS_CONSUMER_EMPTY_S)); \ 5093 } while (0) 5094 5095 #define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \ 5096 (((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \ 5097 HTT_SRING_STATS_PRODUCER_FULL_S) 5098 5099 #define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \ 5100 do { \ 5101 HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \ 5102 ((_var) |= ((_val) << HTT_SRING_STATS_PRODUCER_FULL_S)); \ 5103 } while (0) 5104 5105 /* DWORD prefetch_count__internal_tail_ptr */ 5106 #define HTT_SRING_STATS_PREFETCH_COUNT_M 0x0000ffff 5107 #define HTT_SRING_STATS_PREFETCH_COUNT_S 0 5108 5109 #define HTT_SRING_STATS_INTERNAL_TP_M 0xffff0000 5110 #define HTT_SRING_STATS_INTERNAL_TP_S 16 5111 5112 #define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \ 5113 (((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \ 5114 HTT_SRING_STATS_PREFETCH_COUNT_S) 5115 5116 #define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \ 5117 do { \ 5118 HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \ 5119 ((_var) |= ((_val) << HTT_SRING_STATS_PREFETCH_COUNT_S)); \ 5120 } while (0) 5121 5122 #define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \ 5123 (((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \ 5124 HTT_SRING_STATS_INTERNAL_TP_S) 5125 5126 #define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \ 5127 do { \ 5128 HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \ 5129 ((_var) |= ((_val) << HTT_SRING_STATS_INTERNAL_TP_S)); \ 5130 } while (0) 5131 5132 typedef struct { 5133 htt_tlv_hdr_t tlv_hdr; 5134 5135 /** 5136 * BIT [ 7 : 0] :- mac_id 5137 * BIT [15 : 8] :- ring_id 5138 * BIT [23 : 16] :- arena 0 -SRING_HRAM, 1 - SRING_HCRAM, 2 - SRING_HW2HW. 5139 * BIT [24 : 24] :- EP 0 -consumer, 1 - producer 5140 * BIT [31 : 25] :- reserved 5141 */ 5142 A_UINT32 mac_id__ring_id__arena__ep; 5143 /** DWORD aligned base memory address of the ring */ 5144 A_UINT32 base_addr_lsb; 5145 A_UINT32 base_addr_msb; 5146 /** size of ring */ 5147 A_UINT32 ring_size; 5148 /** size of each ring element */ 5149 A_UINT32 elem_size; 5150 5151 /** Ring status 5152 * 5153 * BIT [15 : 0] :- num_avail_words 5154 * BIT [31 : 16] :- num_valid_words 5155 */ 5156 A_UINT32 num_avail_words__num_valid_words; 5157 5158 /** Index of head and tail 5159 * BIT [15 : 0] :- head_ptr 5160 * BIT [31 : 16] :- tail_ptr 5161 */ 5162 A_UINT32 head_ptr__tail_ptr; 5163 5164 /** Empty or full counter of rings 5165 * BIT [15 : 0] :- consumer_empty 5166 * BIT [31 : 16] :- producer_full 5167 */ 5168 A_UINT32 consumer_empty__producer_full; 5169 5170 /** Prefetch status of consumer ring 5171 * BIT [15 : 0] :- prefetch_count 5172 * BIT [31 : 16] :- internal_tail_ptr 5173 */ 5174 A_UINT32 prefetch_count__internal_tail_ptr; 5175 } htt_stats_sring_stats_tlv; 5176 /* preserve old name alias for new name consistent with the tag name */ 5177 typedef htt_stats_sring_stats_tlv htt_sring_stats_tlv; 5178 5179 typedef struct { 5180 htt_tlv_hdr_t tlv_hdr; 5181 A_UINT32 num_records; 5182 } htt_stats_sring_cmn_tlv; 5183 /* preserve old name alias for new name consistent with the tag name */ 5184 typedef htt_stats_sring_cmn_tlv htt_sring_cmn_tlv; 5185 5186 /* STATS_TYPE : HTT_DBG_EXT_STATS_SRNG_INFO 5187 * TLV_TAGS: 5188 * - HTT_STATS_SRING_CMN_TAG 5189 * - HTT_STATS_STRING_TAG 5190 * - HTT_STATS_SRING_STATS_TAG 5191 */ 5192 /* NOTE: 5193 * This structure is for documentation, and cannot be safely used directly. 5194 * Instead, use the constituent TLV structures to fill/parse. 5195 */ 5196 typedef struct { 5197 htt_stats_sring_cmn_tlv cmn_tlv; 5198 /** Variable based on the Number of records */ 5199 struct { 5200 htt_stats_string_tlv sring_str_tlv; 5201 htt_stats_sring_stats_tlv sring_stats_tlv; 5202 } r[1]; 5203 } htt_sring_stats_t; 5204 5205 /* == PDEV TX RATE CTRL STATS == */ 5206 5207 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 5208 #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 5209 #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 5210 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 5211 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 5212 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 5213 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 5214 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 5215 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 5216 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 5217 #define HTT_TX_PDEV_STATS_NUM_LTF 4 5218 #define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 5219 #define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6 5220 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 5221 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 5222 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 5223 5224 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff 5225 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_S 0 5226 5227 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_GET(_var) \ 5228 (((_var) & HTT_TX_PDEV_RATE_STATS_MAC_ID_M) >> \ 5229 HTT_TX_PDEV_RATE_STATS_MAC_ID_S) 5230 5231 #define HTT_TX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \ 5232 do { \ 5233 HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_MAC_ID, _val); \ 5234 ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \ 5235 } while (0) 5236 5237 #define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ 5238 (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ 5239 HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ 5240 HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) 5241 5242 #define HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 5243 5244 /* 5245 * Introduce new TX counters to support 320MHz support and punctured modes 5246 */ 5247 typedef enum { 5248 HTT_TX_PDEV_STATS_PUNCTURED_NONE = 0, 5249 HTT_TX_PDEV_STATS_PUNCTURED_20 = 1, 5250 HTT_TX_PDEV_STATS_PUNCTURED_40 = 2, 5251 HTT_TX_PDEV_STATS_PUNCTURED_80 = 3, 5252 HTT_TX_PDEV_STATS_PUNCTURED_120 = 4, 5253 HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 5254 } HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE; 5255 5256 #define HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 5257 /* 11be related updates */ 5258 #define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ 5259 #define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ 5260 5261 #define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 5262 #define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 5263 5264 typedef enum { 5265 HTT_TX_PDEV_STATS_AX_RU_SIZE_26, 5266 HTT_TX_PDEV_STATS_AX_RU_SIZE_52, 5267 HTT_TX_PDEV_STATS_AX_RU_SIZE_106, 5268 HTT_TX_PDEV_STATS_AX_RU_SIZE_242, 5269 HTT_TX_PDEV_STATS_AX_RU_SIZE_484, 5270 HTT_TX_PDEV_STATS_AX_RU_SIZE_996, 5271 HTT_TX_PDEV_STATS_AX_RU_SIZE_996x2, 5272 HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS, 5273 } HTT_TX_PDEV_STATS_AX_RU_SIZE; 5274 5275 typedef enum { 5276 HTT_TX_PDEV_STATS_BE_RU_SIZE_26, 5277 HTT_TX_PDEV_STATS_BE_RU_SIZE_52, 5278 HTT_TX_PDEV_STATS_BE_RU_SIZE_52_26, 5279 HTT_TX_PDEV_STATS_BE_RU_SIZE_106, 5280 HTT_TX_PDEV_STATS_BE_RU_SIZE_106_26, 5281 HTT_TX_PDEV_STATS_BE_RU_SIZE_242, 5282 HTT_TX_PDEV_STATS_BE_RU_SIZE_484, 5283 HTT_TX_PDEV_STATS_BE_RU_SIZE_484_242, 5284 HTT_TX_PDEV_STATS_BE_RU_SIZE_996, 5285 HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484, 5286 HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484_242, 5287 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2, 5288 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2_484, 5289 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3, 5290 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3_484, 5291 HTT_TX_PDEV_STATS_BE_RU_SIZE_996x4, 5292 HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, 5293 } HTT_TX_PDEV_STATS_BE_RU_SIZE; 5294 5295 typedef struct { 5296 htt_tlv_hdr_t tlv_hdr; 5297 5298 /** 5299 * BIT [ 7 : 0] :- mac_id 5300 * BIT [31 : 8] :- reserved 5301 */ 5302 A_UINT32 mac_id__word; 5303 /** Number of tx ldpc packets */ 5304 A_UINT32 tx_ldpc; 5305 /** Number of tx rts packets */ 5306 A_UINT32 rts_cnt; 5307 /** RSSI value of last ack packet (units = dB above noise floor) */ 5308 A_UINT32 ack_rssi; 5309 5310 A_UINT32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5311 5312 /** tx_xx_mcs: currently unused */ 5313 A_UINT32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5314 A_UINT32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5315 5316 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 5317 A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5318 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 5319 A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5320 A_UINT32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5321 A_UINT32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 5322 5323 /** 5324 * Counters to track number of tx packets in each GI 5325 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 5326 */ 5327 A_UINT32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5328 5329 /** Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 5330 A_UINT32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 5331 /** Number of CTS-acknowledged RTS packets */ 5332 A_UINT32 rts_success; 5333 5334 /** 5335 * Counters for legacy 11a and 11b transmissions. 5336 * 5337 * The index corresponds to: 5338 * 5339 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 5340 * 5341 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 5342 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 5343 */ 5344 A_UINT32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 5345 A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 5346 5347 /** 11AC VHT DL MU MIMO LDPC count */ 5348 A_UINT32 ac_mu_mimo_tx_ldpc; 5349 /** 11AX HE DL MU MIMO LDPC count */ 5350 A_UINT32 ax_mu_mimo_tx_ldpc; 5351 /** 11AX HE DL MU OFDMA LDPC count */ 5352 A_UINT32 ofdma_tx_ldpc; 5353 5354 /** 5355 * Counters for 11ax HE LTF selection during TX. 5356 * 5357 * The index corresponds to: 5358 * 5359 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 5360 */ 5361 A_UINT32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 5362 5363 /** 11AC VHT DL MU MIMO TX MCS stats */ 5364 A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5365 /** 11AX HE DL MU MIMO TX MCS stats */ 5366 A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5367 /** 11AX HE DL MU OFDMA TX MCS stats */ 5368 A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5369 5370 /** 11AC VHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5371 A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5372 /** 11AX HE DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5373 A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5374 /** 11AX HE DL MU OFDMA TX NSS stats (Indicates NSS for individual users) */ 5375 A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5376 5377 /** 11AC VHT DL MU MIMO TX BW stats */ 5378 A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5379 /** 11AX HE DL MU MIMO TX BW stats */ 5380 A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5381 /** 11AX HE DL MU OFDMA TX BW stats */ 5382 A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5383 5384 /** 11AC VHT DL MU MIMO TX guard interval stats */ 5385 A_UINT32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5386 /** 11AX HE DL MU MIMO TX guard interval stats */ 5387 A_UINT32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5388 /** 11AX HE DL MU OFDMA TX guard interval stats */ 5389 A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 5390 A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; 5391 A_UINT32 tx_11ax_su_ext; 5392 5393 /* Stats for MCS 12/13 */ 5394 A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5395 A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5396 A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5397 /** 11AX VHT DL MU MIMO extended TX MCS stats for MCS 12/13 */ 5398 A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5399 /** 11AX VHT DL MU OFDMA extended TX MCS stats for MCS 12/13 */ 5400 A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5401 /** 11AX VHT DL MU MIMO extended TX guard interval stats for MCS 12/13 */ 5402 A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5403 /** 11AX VHT DL MU OFDMA extended TX guard interval stats for MCS 12/13 */ 5404 A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5405 /* Stats for MCS 14/15 */ 5406 A_UINT32 tx_mcs_ext_2[HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5407 A_UINT32 tx_bw_320mhz; 5408 A_UINT32 tx_gi_ext_2[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5409 A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 5410 A_UINT32 reduced_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5411 /** 11AC VHT DL MU MIMO TX BW stats at reduced channel config */ 5412 A_UINT32 reduced_ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5413 /** 11AX HE DL MU MIMO TX BW stats at reduced channel config */ 5414 A_UINT32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5415 /** 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ 5416 A_UINT32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5417 /** 11AX HE DL MU OFDMA TX RU Size stats */ 5418 A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 5419 /** 11AX HE DL MU OFDMA HE-SIG-B MCS stats */ 5420 A_UINT32 ofdma_he_sig_b_mcs[HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS]; 5421 /** 11AX HE SU data + embedded trigger PPDU success stats (stats for HETP ack success PPDU cnt) */ 5422 A_UINT32 ax_su_embedded_trigger_data_ppdu; 5423 /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */ 5424 A_UINT32 ax_su_embedded_trigger_data_ppdu_err; 5425 /** sta side trigger stats */ 5426 A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; 5427 /** Stats for Extra EHT LTF */ 5428 A_UINT32 extra_eht_ltf; 5429 /** Counter for Extra EHT LTFs in OFDMA sequences */ 5430 A_UINT32 extra_eht_ltf_ofdma; 5431 } htt_stats_tx_pdev_rate_stats_tlv; 5432 /* preserve old name alias for new name consistent with the tag name */ 5433 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv; 5434 5435 typedef struct { 5436 /* 11be mode pdev rate stats; placed in a separate TLV to adhere to size restrictions */ 5437 htt_tlv_hdr_t tlv_hdr; 5438 /** 11BE EHT DL MU MIMO TX MCS stats */ 5439 A_UINT32 be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5440 /** 11BE EHT DL MU MIMO TX NSS stats (Indicates NSS for individual users) */ 5441 A_UINT32 be_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5442 /** 11BE EHT DL MU MIMO TX BW stats */ 5443 A_UINT32 be_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 5444 /** 11BE EHT DL MU MIMO TX guard interval stats */ 5445 A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5446 /** 11BE DL MU MIMO LDPC count */ 5447 A_UINT32 be_mu_mimo_tx_ldpc; 5448 } htt_stats_tx_pdev_be_rate_stats_tlv; 5449 /* preserve old name alias for new name consistent with the tag name */ 5450 typedef htt_stats_tx_pdev_be_rate_stats_tlv htt_tx_pdev_rate_stats_be_tlv; 5451 5452 typedef struct { 5453 /* 5454 * SAWF pdev rate stats; 5455 * placed in a separate TLV to adhere to size restrictions 5456 */ 5457 htt_tlv_hdr_t tlv_hdr; 5458 5459 /** 5460 * Counter incremented when MCS is dropped due to the successive retries 5461 * to a peer reaching the configured limit. 5462 */ 5463 A_UINT32 rate_retry_mcs_drop_cnt; 5464 5465 /** 5466 * histogram of MCS rate drop down, indexed by pre-drop MCS 5467 */ 5468 A_UINT32 mcs_drop_rate[HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; 5469 5470 /** 5471 * PPDU PER histogram - each PPDU has its PER computed, 5472 * and the bin corresponding to that PER percentage is incremented. 5473 */ 5474 A_UINT32 per_histogram_cnt[HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; 5475 5476 /** 5477 * When the service class contains delay bound rate parameters which 5478 * indicate low latency and we enable latency-based RA params then 5479 * the low_latency_rate_count will be incremented. 5480 * This counts the number of peer-TIDs that have been categorized as 5481 * low-latency. 5482 */ 5483 A_UINT32 low_latency_rate_cnt; 5484 5485 /** Indicate how many times rate drop happened within SIFS burst */ 5486 A_UINT32 su_burst_rate_drop_cnt; 5487 5488 /** Indicates how many within SIFS burst failed to deliver any pkt */ 5489 A_UINT32 su_burst_rate_drop_fail_cnt; 5490 } htt_stats_tx_pdev_sawf_rate_stats_tlv; 5491 /* preserve old name alias for new name consistent with the tag name */ 5492 typedef htt_stats_tx_pdev_sawf_rate_stats_tlv htt_tx_pdev_rate_stats_sawf_tlv; 5493 5494 typedef struct { 5495 htt_tlv_hdr_t tlv_hdr; 5496 5497 /** 5498 * BIT [ 7 : 0] :- mac_id 5499 * BIT [31 : 8] :- reserved 5500 */ 5501 A_UINT32 mac_id__word; 5502 5503 /** 11BE EHT DL MU OFDMA LDPC count */ 5504 A_UINT32 be_ofdma_tx_ldpc; 5505 /** 11BE EHT DL MU OFDMA TX MCS stats */ 5506 A_UINT32 be_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5507 /** 5508 * 11BE EHT DL MU OFDMA TX NSS stats (Indicates NSS for individual users) 5509 */ 5510 A_UINT32 be_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5511 /** 11BE EHT DL MU OFDMA TX BW stats */ 5512 A_UINT32 be_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 5513 /** 11BE EHT DL MU OFDMA TX guard interval stats */ 5514 A_UINT32 be_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5515 /** 11BE EHT DL MU OFDMA TX RU Size stats */ 5516 A_UINT32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 5517 /** 11BE EHT DL MU OFDMA EHT-SIG MCS stats */ 5518 A_UINT32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; 5519 } htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; 5520 /* preserve old name alias for new name consistent with the tag name */ 5521 typedef htt_stats_tx_pdev_rate_stats_be_ofdma_tlv 5522 htt_tx_pdev_rate_stats_be_ofdma_tlv; 5523 5524 typedef struct { 5525 htt_tlv_hdr_t tlv_hdr; 5526 /** tx_ppdu_dur_hist: 5527 * Tx PPDU duration histogram, which holds the tx duration of PPDUs 5528 * under histogram bins of interval 250us 5529 */ 5530 A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 5531 A_UINT32 tx_success_time_us_low; 5532 A_UINT32 tx_success_time_us_high; 5533 A_UINT32 tx_fail_time_us_low; 5534 A_UINT32 tx_fail_time_us_high; 5535 A_UINT32 pdev_up_time_us_low; 5536 A_UINT32 pdev_up_time_us_high; 5537 /** tx_ofdma_ppdu_dur_hist: 5538 * Tx OFDMA PPDU duration histogram, which holds the tx duration of 5539 * OFDMA PPDUs under histogram bins of interval 250us 5540 */ 5541 A_UINT32 tx_ofdma_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 5542 } htt_stats_tx_pdev_ppdu_dur_tlv; 5543 /* preserve old name alias for new name consistent with the tag name */ 5544 typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv; 5545 5546 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE 5547 * TLV_TAGS: 5548 * - HTT_STATS_TX_PDEV_RATE_STATS_TAG 5549 */ 5550 /* NOTE: 5551 * This structure is for documentation, and cannot be safely used directly. 5552 * Instead, use the constituent TLV structures to fill/parse. 5553 */ 5554 typedef struct { 5555 htt_stats_tx_pdev_rate_stats_tlv rate_tlv; 5556 htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv; 5557 htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv; 5558 htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv; 5559 } htt_tx_pdev_rate_stats_t; 5560 5561 /* == PDEV RX RATE CTRL STATS == */ 5562 5563 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 5564 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 5565 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ 5566 #define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ 5567 #define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ 5568 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ 5569 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 5570 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 5571 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 5572 #define HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS \ 5573 (HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS) 5574 #define HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 /* 20, 40, 80, 160, 320Mhz */ 5575 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 5576 #define HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS 8 5577 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 5578 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 5579 #define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 5580 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 5581 #define HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0-13, -2, -1 */ 5582 #define HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ 5583 5584 /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS: 5585 * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 5586 * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 5587 * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 5588 * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 5589 * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 5590 * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 5591 */ 5592 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 5593 /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS: 5594 * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 5595 * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 5596 * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 5597 * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 5598 * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 5599 * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 5600 * RU size index 6: HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 5601 */ 5602 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS 7 /* includes 996x2 */ 5603 5604 typedef enum { 5605 HTT_RX_PDEV_STATS_BE_RU_SIZE_26, 5606 HTT_RX_PDEV_STATS_BE_RU_SIZE_52, 5607 HTT_RX_PDEV_STATS_BE_RU_SIZE_52_26, 5608 HTT_RX_PDEV_STATS_BE_RU_SIZE_106, 5609 HTT_RX_PDEV_STATS_BE_RU_SIZE_106_26, 5610 HTT_RX_PDEV_STATS_BE_RU_SIZE_242, 5611 HTT_RX_PDEV_STATS_BE_RU_SIZE_484, 5612 HTT_RX_PDEV_STATS_BE_RU_SIZE_484_242, 5613 HTT_RX_PDEV_STATS_BE_RU_SIZE_996, 5614 HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484, 5615 HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 5616 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2, 5617 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 5618 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3, 5619 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 5620 HTT_RX_PDEV_STATS_BE_RU_SIZE_996x4, 5621 HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, 5622 } HTT_RX_PDEV_STATS_BE_RU_SIZE; 5623 5624 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff 5625 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0 5626 5627 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_GET(_var) \ 5628 (((_var) & HTT_RX_PDEV_RATE_STATS_MAC_ID_M) >> \ 5629 HTT_RX_PDEV_RATE_STATS_MAC_ID_S) 5630 5631 #define HTT_RX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \ 5632 do { \ 5633 HTT_CHECK_SET_VAL(HTT_RX_PDEV_RATE_STATS_MAC_ID, _val); \ 5634 ((_var) |= ((_val) << HTT_RX_PDEV_RATE_STATS_MAC_ID_S)); \ 5635 } while (0) 5636 5637 /* Introduce new RX counters to support 320MHZ support and punctured modes */ 5638 typedef enum { 5639 HTT_RX_PDEV_STATS_PUNCTURED_NONE = 0, 5640 HTT_RX_PDEV_STATS_PUNCTURED_20 = 1, 5641 HTT_RX_PDEV_STATS_PUNCTURED_40 = 2, 5642 HTT_RX_PDEV_STATS_PUNCTURED_80 = 3, 5643 HTT_RX_PDEV_STATS_PUNCTURED_120 = 4, 5644 HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 5645 } HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE; 5646 5647 #define HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 5648 5649 typedef struct { 5650 htt_tlv_hdr_t tlv_hdr; 5651 5652 /** 5653 * BIT [ 7 : 0] :- mac_id 5654 * BIT [31 : 8] :- reserved 5655 */ 5656 A_UINT32 mac_id__word; 5657 A_UINT32 nsts; 5658 5659 /** Number of rx ldpc packets */ 5660 A_UINT32 rx_ldpc; 5661 /** Number of rx rts packets */ 5662 A_UINT32 rts_cnt; 5663 5664 /** units = dB above noise floor */ 5665 A_UINT32 rssi_mgmt; 5666 /** units = dB above noise floor */ 5667 A_UINT32 rssi_data; 5668 /** units = dB above noise floor */ 5669 A_UINT32 rssi_comb; 5670 A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5671 /** element 0,1, ...7 -> NSS 1,2, ...8 */ 5672 A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5673 A_UINT32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 5674 A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5675 /** element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 5676 A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5677 A_UINT32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 5678 /** units = dB above noise floor */ 5679 A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5680 5681 /** Counters to track number of rx packets in each GI in each mcs (0-11) */ 5682 A_UINT32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5683 /** rx Signal Strength value in dBm unit */ 5684 A_INT32 rssi_in_dbm; 5685 5686 A_UINT32 rx_11ax_su_ext; 5687 A_UINT32 rx_11ac_mumimo; 5688 A_UINT32 rx_11ax_mumimo; 5689 A_UINT32 rx_11ax_ofdma; 5690 A_UINT32 txbf; 5691 A_UINT32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 5692 A_UINT32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 5693 A_UINT32 rx_active_dur_us_low; 5694 A_UINT32 rx_active_dur_us_high; 5695 5696 /** number of times UL MU MIMO RX packets received */ 5697 A_UINT32 rx_11ax_ul_ofdma; 5698 5699 /** 11AX HE UL OFDMA RX TB PPDU MCS stats */ 5700 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5701 /** 11AX HE UL OFDMA RX TB PPDU GI stats */ 5702 A_UINT32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5703 /** 5704 * 11AX HE UL OFDMA RX TB PPDU NSS stats 5705 * (Increments the individual user NSS in the OFDMA PPDU received) 5706 */ 5707 A_UINT32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5708 /** 11AX HE UL OFDMA RX TB PPDU BW stats */ 5709 A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 5710 /** Number of times UL OFDMA TB PPDUs received with stbc */ 5711 A_UINT32 ul_ofdma_rx_stbc; 5712 /** Number of times UL OFDMA TB PPDUs received with ldpc */ 5713 A_UINT32 ul_ofdma_rx_ldpc; 5714 5715 /** 5716 * Number of non data PPDUs received for each degree (number of users) 5717 * in UL OFDMA 5718 */ 5719 A_UINT32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5720 /** 5721 * Number of data ppdus received for each degree (number of users) 5722 * in UL OFDMA 5723 */ 5724 A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5725 /** 5726 * Number of mpdus passed for each degree (number of users) 5727 * in UL OFDMA TB PPDU 5728 */ 5729 A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5730 /** 5731 * Number of mpdus failed for each degree (number of users) 5732 * in UL OFDMA TB PPDU 5733 */ 5734 A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5735 5736 A_UINT32 nss_count; 5737 A_UINT32 pilot_count; 5738 /** RxEVM stats in dB */ 5739 A_INT32 rx_pilot_evm_dB[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 5740 /** 5741 * EVM mean across pilots, computed as 5742 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_dB) 5743 */ 5744 A_INT32 rx_pilot_evm_dB_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5745 /** dBm units */ 5746 A_INT8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5747 /** per_chain_rssi_pkt_type: 5748 * This field shows what type of rx frame the per-chain RSSI was computed 5749 * on, by recording the frame type and sub-type as bit-fields within this 5750 * field: 5751 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 5752 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 5753 * BIT [31 : 8] :- Reserved 5754 */ 5755 A_UINT32 per_chain_rssi_pkt_type; 5756 A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5757 A_UINT32 rx_su_ndpa; 5758 A_UINT32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5759 A_UINT32 rx_mu_ndpa; 5760 A_UINT32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5761 A_UINT32 rx_br_poll; 5762 A_UINT32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5763 A_UINT32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 5764 5765 /** 5766 * Number of non data ppdus received for each degree (number of users) 5767 * with UL MUMIMO 5768 */ 5769 A_UINT32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5770 /** 5771 * Number of data ppdus received for each degree (number of users) 5772 * with UL MUMIMO 5773 */ 5774 A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5775 /** 5776 * Number of mpdus passed for each degree (number of users) 5777 * with UL MUMIMO TB PPDU 5778 */ 5779 A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5780 /** 5781 * Number of mpdus failed for each degree (number of users) 5782 * with UL MUMIMO TB PPDU 5783 */ 5784 A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 5785 /** 5786 * Number of non data ppdus received for each degree (number of users) 5787 * in UL OFDMA 5788 */ 5789 A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5790 /** 5791 * Number of data ppdus received for each degree (number of users) 5792 *in UL OFDMA 5793 */ 5794 A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 5795 5796 /* Stats for MCS 12/13 */ 5797 A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 5798 /* 5799 * NOTE - this TLV is already large enough that it causes the HTT message 5800 * carrying it to be nearly at the message size limit that applies to 5801 * many targets/hosts. 5802 * No further fields should be added to this TLV without very careful 5803 * review to ensure the size increase is acceptable. 5804 */ 5805 } htt_stats_rx_pdev_rate_stats_tlv; 5806 /* preserve old name alias for new name consistent with the tag name */ 5807 typedef htt_stats_rx_pdev_rate_stats_tlv htt_rx_pdev_rate_stats_tlv; 5808 5809 typedef struct { 5810 htt_tlv_hdr_t tlv_hdr; 5811 /** Tx PPDU duration histogram **/ 5812 A_UINT32 rx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; 5813 } htt_stats_rx_pdev_ppdu_dur_tlv; 5814 /* preserve old name alias for new name consistent with the tag name */ 5815 typedef htt_stats_rx_pdev_ppdu_dur_tlv htt_rx_pdev_ppdu_dur_stats_tlv; 5816 5817 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE 5818 * TLV_TAGS: 5819 * - HTT_STATS_RX_PDEV_RATE_STATS_TAG 5820 */ 5821 /* NOTE: 5822 * This structure is for documentation, and cannot be safely used directly. 5823 * Instead, use the constituent TLV structures to fill/parse. 5824 */ 5825 typedef struct { 5826 htt_stats_rx_pdev_rate_stats_tlv rate_tlv; 5827 htt_stats_rx_pdev_ppdu_dur_tlv rx_ppdu_dur_tlv; 5828 } htt_rx_pdev_rate_stats_t; 5829 5830 typedef struct { 5831 htt_tlv_hdr_t tlv_hdr; 5832 /** units = dB above noise floor */ 5833 A_UINT8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 5834 A_INT8 rx_per_chain_rssi_ext_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 5835 /** rx mcast signal strength value in dBm unit */ 5836 A_INT32 rssi_mcast_in_dbm; 5837 /** rx mgmt packet signal Strength value in dBm unit */ 5838 A_INT32 rssi_mgmt_in_dbm; 5839 /* 5840 * Stats for MCS 0-13 since rx_pdev_rate_stats_tlv cannot be updated, 5841 * due to message size limitations. 5842 */ 5843 A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5844 A_UINT32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5845 A_UINT32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5846 A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5847 A_UINT32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5848 A_UINT32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5849 A_UINT32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5850 A_UINT32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 5851 /* MCS 14,15 */ 5852 A_UINT32 rx_mcs_ext_2[HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5853 A_UINT32 rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; 5854 A_UINT32 rx_gi_ext_2[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 5855 A_UINT32 rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 5856 A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5857 A_UINT8 rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; /* units = dB above noise floor */ 5858 A_INT8 rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; 5859 } htt_stats_rx_pdev_rate_ext_stats_tlv; 5860 /* preserve old name alias for new name consistent with the tag name */ 5861 typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv; 5862 5863 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT 5864 * TLV_TAGS: 5865 * - HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG 5866 */ 5867 /* NOTE: 5868 * This structure is for documentation, and cannot be safely used directly. 5869 * Instead, use the constituent TLV structures to fill/parse. 5870 */ 5871 typedef struct { 5872 htt_stats_rx_pdev_rate_ext_stats_tlv rate_tlv; 5873 } htt_rx_pdev_rate_ext_stats_t; 5874 5875 #define HTT_STATS_CMN_MAC_ID_M 0x000000ff 5876 #define HTT_STATS_CMN_MAC_ID_S 0 5877 5878 #define HTT_STATS_CMN_MAC_ID_GET(_var) \ 5879 (((_var) & HTT_STATS_CMN_MAC_ID_M) >> \ 5880 HTT_STATS_CMN_MAC_ID_S) 5881 5882 #define HTT_STATS_CMN_MAC_ID_SET(_var, _val) \ 5883 do { \ 5884 HTT_CHECK_SET_VAL(HTT_STATS_CMN_MAC_ID, _val); \ 5885 ((_var) |= ((_val) << HTT_STATS_CMN_MAC_ID_S)); \ 5886 } while (0) 5887 5888 #define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 5889 5890 typedef struct { 5891 htt_tlv_hdr_t tlv_hdr; 5892 5893 /** 5894 * BIT [ 7 : 0] :- mac_id 5895 * BIT [31 : 8] :- reserved 5896 */ 5897 A_UINT32 mac_id__word; 5898 5899 A_UINT32 rx_11ax_ul_ofdma; 5900 5901 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5902 A_UINT32 ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 5903 A_UINT32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5904 A_UINT32 ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5905 A_UINT32 ul_ofdma_rx_stbc; 5906 A_UINT32 ul_ofdma_rx_ldpc; 5907 5908 /* 5909 * These are arrays to hold the number of PPDUs that we received per RU. 5910 * E.g. PPDUs (data or non data) received in RU26 will be incremented in 5911 * array offset 0 and similarly RU52 will be incremented in array offset 1 5912 */ 5913 A_UINT32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ 5914 A_UINT32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ 5915 5916 /* 5917 * These arrays hold Target RSSI (rx power the AP wants), 5918 * FD RSSI (rx power the AP sees) & Power headroom values of STAs 5919 * which can be identified by AIDs, during trigger based RX. 5920 * Array acts a circular buffer and holds values for last 5 STAs 5921 * in the same order as RX. 5922 */ 5923 /** 5924 * STA AID array for identifying which STA the 5925 * Target-RSSI / FD-RSSI / pwr headroom stats are for 5926 */ 5927 A_UINT32 uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 5928 /** 5929 * Trig Target RSSI for STA AID in same index - UNIT(dBm) 5930 */ 5931 A_INT32 uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 5932 /** 5933 * Trig FD RSSI from STA AID in same index - UNIT(dBm) 5934 */ 5935 A_INT32 uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 5936 /** 5937 * Trig power headroom for STA AID in same idx - UNIT(dB) 5938 */ 5939 A_UINT32 uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 5940 A_UINT32 reduced_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 5941 5942 /* 5943 * Number of HE UL OFDMA per-user responses containing only a QoS null in 5944 * response to basic trigger. Typically a data response is expected. 5945 */ 5946 A_UINT32 ul_ofdma_basic_trigger_rx_qos_null_only; 5947 } htt_stats_rx_pdev_ul_trig_stats_tlv; 5948 /* preserve old name alias for new name consistent with the tag name */ 5949 typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv; 5950 5951 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS 5952 * TLV_TAGS: 5953 * - HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG 5954 * NOTE: 5955 * This structure is for documentation, and cannot be safely used directly. 5956 * Instead, use the constituent TLV structures to fill/parse. 5957 */ 5958 typedef struct { 5959 htt_stats_rx_pdev_ul_trig_stats_tlv ul_trigger_tlv; 5960 } htt_rx_pdev_ul_trigger_stats_t; 5961 5962 typedef struct { 5963 htt_tlv_hdr_t tlv_hdr; 5964 5965 /** 5966 * BIT [ 7 : 0] :- mac_id 5967 * BIT [31 : 8] :- reserved 5968 */ 5969 A_UINT32 mac_id__word; 5970 5971 A_UINT32 rx_11be_ul_ofdma; 5972 5973 A_UINT32 be_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5974 A_UINT32 be_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 5975 A_UINT32 be_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 5976 A_UINT32 be_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 5977 A_UINT32 be_ul_ofdma_rx_stbc; 5978 A_UINT32 be_ul_ofdma_rx_ldpc; 5979 5980 /* 5981 * These are arrays to hold the number of PPDUs that we received per RU. 5982 * E.g. PPDUs (data or non data) received in RU26 will be incremented in 5983 * array offset 0 and similarly RU52 will be incremented in array offset 1 5984 */ 5985 /** PPDU level */ 5986 A_UINT32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 5987 /** PPDU level */ 5988 A_UINT32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 5989 5990 /* 5991 * These arrays hold Target RSSI (rx power the AP wants), 5992 * FD RSSI (rx power the AP sees) & Power headroom values of STAs 5993 * which can be identified by AIDs, during trigger based RX. 5994 * Array acts a circular buffer and holds values for last 5 STAs 5995 * in the same order as RX. 5996 */ 5997 /** 5998 * STA AID array for identifying which STA the 5999 * Target-RSSI / FD-RSSI / pwr headroom stats are for 6000 */ 6001 A_UINT32 be_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6002 /** 6003 * Trig Target RSSI for STA AID in same index - UNIT(dBm) 6004 */ 6005 A_INT32 be_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6006 /** 6007 * Trig FD RSSI from STA AID in same index - UNIT(dBm) 6008 */ 6009 A_INT32 be_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6010 /** 6011 * Trig power headroom for STA AID in same idx - UNIT(dB) 6012 */ 6013 A_UINT32 be_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 6014 6015 /* 6016 * Number of EHT UL OFDMA per-user responses containing only a QoS null in 6017 * response to basic trigger. Typically a data response is expected. 6018 */ 6019 A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only; 6020 6021 /* UL MLO Queue Depth Sharing Stats */ 6022 A_UINT32 ul_mlo_send_qdepth_params_count; 6023 A_UINT32 ul_mlo_proc_qdepth_params_count; 6024 A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; 6025 A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; 6026 } htt_stats_rx_pdev_be_ul_trig_stats_tlv; 6027 /* preserve old name alias for new name consistent with the tag name */ 6028 typedef htt_stats_rx_pdev_be_ul_trig_stats_tlv 6029 htt_rx_pdev_be_ul_trigger_stats_tlv; 6030 6031 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS 6032 * TLV_TAGS: 6033 * - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG 6034 * NOTE: 6035 * This structure is for documentation, and cannot be safely used directly. 6036 * Instead, use the constituent TLV structures to fill/parse. 6037 */ 6038 typedef struct { 6039 htt_stats_rx_pdev_be_ul_trig_stats_tlv ul_trigger_tlv; 6040 } htt_rx_pdev_be_ul_trigger_stats_t; 6041 6042 typedef struct { 6043 htt_tlv_hdr_t tlv_hdr; 6044 6045 A_UINT32 user_index; 6046 /** PPDU level */ 6047 A_UINT32 rx_ulofdma_non_data_ppdu; 6048 /** PPDU level */ 6049 A_UINT32 rx_ulofdma_data_ppdu; 6050 /** MPDU level */ 6051 A_UINT32 rx_ulofdma_mpdu_ok; 6052 /** MPDU level */ 6053 A_UINT32 rx_ulofdma_mpdu_fail; 6054 A_UINT32 rx_ulofdma_non_data_nusers; 6055 A_UINT32 rx_ulofdma_data_nusers; 6056 } htt_stats_rx_pdev_ul_ofdma_user_stats_tlv; 6057 /* preserve old name alias for new name consistent with the tag name */ 6058 typedef htt_stats_rx_pdev_ul_ofdma_user_stats_tlv 6059 htt_rx_pdev_ul_ofdma_user_stats_tlv; 6060 6061 typedef struct { 6062 htt_tlv_hdr_t tlv_hdr; 6063 6064 A_UINT32 user_index; 6065 /** PPDU level */ 6066 A_UINT32 be_rx_ulofdma_non_data_ppdu; 6067 /** PPDU level */ 6068 A_UINT32 be_rx_ulofdma_data_ppdu; 6069 /** MPDU level */ 6070 A_UINT32 be_rx_ulofdma_mpdu_ok; 6071 /** MPDU level */ 6072 A_UINT32 be_rx_ulofdma_mpdu_fail; 6073 A_UINT32 be_rx_ulofdma_non_data_nusers; 6074 A_UINT32 be_rx_ulofdma_data_nusers; 6075 } htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv; 6076 /* preserve old name alias for new name consistent with the tag name */ 6077 typedef htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv 6078 htt_rx_pdev_be_ul_ofdma_user_stats_tlv; 6079 6080 typedef struct { 6081 htt_tlv_hdr_t tlv_hdr; 6082 6083 A_UINT32 user_index; 6084 /** PPDU level */ 6085 A_UINT32 rx_ulmumimo_non_data_ppdu; 6086 /** PPDU level */ 6087 A_UINT32 rx_ulmumimo_data_ppdu; 6088 /** MPDU level */ 6089 A_UINT32 rx_ulmumimo_mpdu_ok; 6090 /** MPDU level */ 6091 A_UINT32 rx_ulmumimo_mpdu_fail; 6092 } htt_stats_rx_pdev_ul_mimo_user_stats_tlv; 6093 /* preserve old name alias for new name consistent with the tag name */ 6094 typedef htt_stats_rx_pdev_ul_mimo_user_stats_tlv 6095 htt_rx_pdev_ul_mimo_user_stats_tlv; 6096 6097 typedef struct { 6098 htt_tlv_hdr_t tlv_hdr; 6099 6100 A_UINT32 user_index; 6101 /** PPDU level */ 6102 A_UINT32 be_rx_ulmumimo_non_data_ppdu; 6103 /** PPDU level */ 6104 A_UINT32 be_rx_ulmumimo_data_ppdu; 6105 /** MPDU level */ 6106 A_UINT32 be_rx_ulmumimo_mpdu_ok; 6107 /** MPDU level */ 6108 A_UINT32 be_rx_ulmumimo_mpdu_fail; 6109 } htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv; 6110 /* preserve old name alias for new name consistent with the tag name */ 6111 typedef htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv 6112 htt_rx_pdev_be_ul_mimo_user_stats_tlv; 6113 6114 /* == RX PDEV/SOC STATS == */ 6115 6116 typedef struct { 6117 htt_tlv_hdr_t tlv_hdr; 6118 6119 /** 6120 * BIT [7:0] :- mac_id 6121 * BIT [31:8] :- reserved 6122 * 6123 * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. 6124 */ 6125 A_UINT32 mac_id__word; 6126 6127 /** Number of times UL MUMIMO RX packets received */ 6128 A_UINT32 rx_11ax_ul_mumimo; 6129 6130 /** 11AX HE UL MU-MIMO RX TB PPDU MCS stats */ 6131 A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6132 /** 6133 * 11AX HE UL MU-MIMO RX GI & LTF stats. 6134 * Index 0 indicates 1xLTF + 1.6 msec GI 6135 * Index 1 indicates 2xLTF + 1.6 msec GI 6136 * Index 2 indicates 4xLTF + 3.2 msec GI 6137 */ 6138 A_UINT32 ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 6139 /** 6140 * 11AX HE UL MU-MIMO RX TB PPDU NSS stats 6141 * (Increments the individual user NSS in the UL MU MIMO PPDU received) 6142 */ 6143 A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6144 /** 11AX HE UL MU-MIMO RX TB PPDU BW stats */ 6145 A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6146 /** Number of times UL MUMIMO TB PPDUs received with STBC */ 6147 A_UINT32 ul_mumimo_rx_stbc; 6148 /** Number of times UL MUMIMO TB PPDUs received with LDPC */ 6149 A_UINT32 ul_mumimo_rx_ldpc; 6150 6151 /* Stats for MCS 12/13 */ 6152 A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 6153 A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 6154 6155 /** RSSI in dBm for Rx TB PPDUs */ 6156 A_INT8 rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS]; 6157 /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ 6158 A_INT8 rx_ul_mumimo_target_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6159 /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ 6160 A_INT8 rx_ul_mumimo_fd_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6161 /** Average pilot EVM measued for RX UL TB PPDU */ 6162 A_INT8 rx_ulmumimo_pilot_evm_dB_mean[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6163 A_UINT32 reduced_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 6164 6165 /* 6166 * Number of HE UL MU-MIMO per-user responses containing only a QoS null in 6167 * response to basic trigger. Typically a data response is expected. 6168 */ 6169 A_UINT32 ul_mumimo_basic_trigger_rx_qos_null_only; 6170 } htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv; 6171 /* preserve old name alias for new name consistent with the tag name */ 6172 typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv 6173 htt_rx_pdev_ul_mumimo_trig_stats_tlv; 6174 6175 typedef struct { 6176 htt_tlv_hdr_t tlv_hdr; 6177 6178 /** 6179 * BIT [7:0] :- mac_id 6180 * BIT [31:8] :- reserved 6181 * 6182 * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. 6183 */ 6184 A_UINT32 mac_id__word; 6185 6186 /** Number of times UL MUMIMO RX packets received */ 6187 A_UINT32 rx_11be_ul_mumimo; 6188 6189 /** 11BE EHT UL MU-MIMO RX TB PPDU MCS stats */ 6190 A_UINT32 be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6191 /** 6192 * 11BE EHT UL MU-MIMO RX GI & LTF stats. 6193 * Index 0 indicates 1xLTF + 1.6 msec GI 6194 * Index 1 indicates 2xLTF + 1.6 msec GI 6195 * Index 2 indicates 4xLTF + 3.2 msec GI 6196 */ 6197 A_UINT32 be_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; 6198 /** 6199 * 11BE EHT UL MU-MIMO RX TB PPDU NSS stats 6200 * (Increments the individual user NSS in the UL MU MIMO PPDU received) 6201 */ 6202 A_UINT32 be_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6203 /** 11BE EHT UL MU-MIMO RX TB PPDU BW stats */ 6204 A_UINT32 be_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6205 /** Number of times UL MUMIMO TB PPDUs received with STBC */ 6206 A_UINT32 be_ul_mumimo_rx_stbc; 6207 /** Number of times UL MUMIMO TB PPDUs received with LDPC */ 6208 A_UINT32 be_ul_mumimo_rx_ldpc; 6209 6210 /** RSSI in dBm for Rx TB PPDUs */ 6211 A_INT8 be_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6212 /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ 6213 A_INT8 be_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; 6214 /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ 6215 A_INT8 be_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6216 /** Average pilot EVM measued for RX UL TB PPDU */ 6217 A_INT8 be_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 6218 /** Number of times UL MUMIMO TB PPDUs received in a punctured mode */ 6219 A_UINT32 rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 6220 6221 /* 6222 * Number of EHT UL MU-MIMO per-user responses containing only a QoS null 6223 * in response to basic trigger. Typically a data response is expected. 6224 */ 6225 A_UINT32 be_ul_mumimo_basic_trigger_rx_qos_null_only; 6226 } htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv; 6227 /* preserve old name alias for new name consistent with the tag name */ 6228 typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv 6229 htt_rx_pdev_ul_mumimo_trig_be_stats_tlv; 6230 6231 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS 6232 * TLV_TAGS: 6233 * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG 6234 * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG 6235 */ 6236 typedef struct { 6237 htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv ul_mumimo_trig_tlv; 6238 htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv; 6239 } htt_rx_pdev_ul_mumimo_trig_stats_t; 6240 6241 typedef struct { 6242 htt_tlv_hdr_t tlv_hdr; 6243 /** Num Packets received on REO FW ring */ 6244 A_UINT32 fw_reo_ring_data_msdu; 6245 /** Num bc/mc packets indicated from fw to host */ 6246 A_UINT32 fw_to_host_data_msdu_bcmc; 6247 /** Num unicast packets indicated from fw to host */ 6248 A_UINT32 fw_to_host_data_msdu_uc; 6249 /** Num remote buf recycle from offload */ 6250 A_UINT32 ofld_remote_data_buf_recycle_cnt; 6251 /** Num remote free buf given to offload */ 6252 A_UINT32 ofld_remote_free_buf_indication_cnt; 6253 6254 /** Num unicast packets from local path indicated to host */ 6255 A_UINT32 ofld_buf_to_host_data_msdu_uc; 6256 /** Num unicast packets from REO indicated to host */ 6257 A_UINT32 reo_fw_ring_to_host_data_msdu_uc; 6258 6259 /** Num Packets received from WBM SW1 ring */ 6260 A_UINT32 wbm_sw_ring_reap; 6261 /** Num packets from WBM forwarded from fw to host via WBM */ 6262 A_UINT32 wbm_forward_to_host_cnt; 6263 /** Num packets from WBM recycled to target refill ring */ 6264 A_UINT32 wbm_target_recycle_cnt; 6265 6266 /** 6267 * Total Num of recycled to refill ring, 6268 * including packets from WBM and REO 6269 */ 6270 A_UINT32 target_refill_ring_recycle_cnt; 6271 } htt_stats_rx_soc_fw_stats_tlv; 6272 /* preserve old name alias for new name consistent with the tag name */ 6273 typedef htt_stats_rx_soc_fw_stats_tlv htt_rx_soc_fw_stats_tlv; 6274 6275 #define HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6276 6277 /* NOTE: Variable length TLV, use length spec to infer array size */ 6278 typedef struct { 6279 htt_tlv_hdr_t tlv_hdr; 6280 /** Num ring empty encountered */ 6281 A_UINT32 refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 6282 } htt_stats_rx_soc_fw_refill_ring_empty_tlv; 6283 /* preserve old name alias for new name consistent with the tag name */ 6284 typedef htt_stats_rx_soc_fw_refill_ring_empty_tlv 6285 htt_rx_soc_fw_refill_ring_empty_tlv_v; 6286 6287 #define HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6288 6289 /* NOTE: Variable length TLV, use length spec to infer array size */ 6290 typedef struct { 6291 htt_tlv_hdr_t tlv_hdr; 6292 /** Num total buf refilled from refill ring */ 6293 A_UINT32 refill_ring_num_refill[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ 6294 } htt_stats_rx_soc_fw_refill_ring_num_refill_tlv; 6295 /* preserve old name alias for new name consistent with the tag name */ 6296 typedef htt_stats_rx_soc_fw_refill_ring_num_refill_tlv 6297 htt_rx_soc_fw_refill_ring_num_refill_tlv_v; 6298 6299 /* RXDMA error code from WBM released packets */ 6300 typedef enum { 6301 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 6302 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 6303 HTT_RX_RXDMA_FCS_ERR = 2, 6304 HTT_RX_RXDMA_DECRYPT_ERR = 3, 6305 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 6306 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 6307 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 6308 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 6309 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 6310 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 6311 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 6312 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 6313 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 6314 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 6315 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 6316 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 6317 6318 /* 6319 * This MAX_ERR_CODE should not be used in any host/target messages, 6320 * so that even though it is defined within a host/target interface 6321 * definition header file, it isn't actually part of the host/target 6322 * interface, and thus can be modified. 6323 */ 6324 HTT_RX_RXDMA_MAX_ERR_CODE 6325 } htt_rx_rxdma_error_code_enum; 6326 6327 /* NOTE: Variable length TLV, use length spec to infer array size */ 6328 typedef struct { 6329 htt_tlv_hdr_t tlv_hdr; 6330 6331 /** NOTE: 6332 * The mapping of RXDMA error types to rxdma_err array elements is HW dependent. 6333 * It is expected but not required that the target will provide a rxdma_err element 6334 * for each of the htt_rx_rxdma_error_code_enum values, up to but not including 6335 * MAX_ERR_CODE. The host should ignore any array elements whose 6336 * indices are >= the MAX_ERR_CODE value the host was compiled with. 6337 */ 6338 A_UINT32 rxdma_err[1]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ 6339 } htt_stats_rx_refill_rxdma_err_tlv; 6340 /* preserve old name alias for new name consistent with the tag name */ 6341 typedef htt_stats_rx_refill_rxdma_err_tlv 6342 htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v; 6343 6344 /* REO error code from WBM released packets */ 6345 typedef enum { 6346 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 6347 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 6348 HTT_RX_AMPDU_IN_NON_BA = 2, 6349 HTT_RX_NON_BA_DUPLICATE = 3, 6350 HTT_RX_BA_DUPLICATE = 4, 6351 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 6352 HTT_RX_BAR_FRAME_2K_JUMP = 6, 6353 HTT_RX_REGULAR_FRAME_OOR = 7, 6354 HTT_RX_BAR_FRAME_OOR = 8, 6355 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 6356 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 6357 HTT_RX_PN_CHECK_FAILED = 11, 6358 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 6359 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 6360 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 6361 HTT_RX_REO_ERR_CODE_RVSD = 15, 6362 6363 /* 6364 * This MAX_ERR_CODE should not be used in any host/target messages, 6365 * so that even though it is defined within a host/target interface 6366 * definition header file, it isn't actually part of the host/target 6367 * interface, and thus can be modified. 6368 */ 6369 HTT_RX_REO_MAX_ERR_CODE 6370 } htt_rx_reo_error_code_enum; 6371 6372 /* NOTE: Variable length TLV, use length spec to infer array size */ 6373 typedef struct { 6374 htt_tlv_hdr_t tlv_hdr; 6375 6376 /** NOTE: 6377 * The mapping of REO error types to reo_err array elements is HW dependent. 6378 * It is expected but not required that the target will provide a rxdma_err element 6379 * for each of the htt_rx_reo_error_code_enum values, up to but not including 6380 * MAX_ERR_CODE. The host should ignore any array elements whose 6381 * indices are >= the MAX_ERR_CODE value the host was compiled with. 6382 */ 6383 A_UINT32 reo_err[1]; /* HTT_RX_REO_MAX_ERR_CODE */ 6384 } htt_stats_rx_refill_reo_err_tlv; 6385 /* preserve old name alias for new name consistent with the tag name */ 6386 typedef htt_stats_rx_refill_reo_err_tlv 6387 htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v; 6388 6389 /* NOTE: 6390 * This structure is for documentation, and cannot be safely used directly. 6391 * Instead, use the constituent TLV structures to fill/parse. 6392 */ 6393 typedef struct { 6394 htt_stats_rx_soc_fw_stats_tlv fw_tlv; 6395 htt_stats_rx_soc_fw_refill_ring_empty_tlv fw_refill_ring_empty_tlv; 6396 htt_stats_rx_soc_fw_refill_ring_num_refill_tlv 6397 fw_refill_ring_num_refill_tlv; 6398 htt_stats_rx_refill_rxdma_err_tlv fw_refill_ring_num_rxdma_err_tlv; 6399 htt_stats_rx_refill_reo_err_tlv fw_refill_ring_num_reo_err_tlv; 6400 } htt_rx_soc_stats_t; 6401 6402 /* == RX PDEV STATS == */ 6403 #define HTT_RX_PDEV_FW_STATS_MAC_ID_M 0x000000ff 6404 #define HTT_RX_PDEV_FW_STATS_MAC_ID_S 0 6405 6406 #define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ 6407 (((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \ 6408 HTT_RX_PDEV_FW_STATS_MAC_ID_S) 6409 6410 #define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \ 6411 do { \ 6412 HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \ 6413 ((_var) |= ((_val) << HTT_RX_PDEV_FW_STATS_MAC_ID_S)); \ 6414 } while (0) 6415 6416 typedef struct { 6417 htt_tlv_hdr_t tlv_hdr; 6418 6419 /** 6420 * BIT [ 7 : 0] :- mac_id 6421 * BIT [31 : 8] :- reserved 6422 */ 6423 A_UINT32 mac_id__word; 6424 /** Num PPDU status processed from HW */ 6425 A_UINT32 ppdu_recvd; 6426 /** Num MPDU across PPDUs with FCS ok */ 6427 A_UINT32 mpdu_cnt_fcs_ok; 6428 /** Num MPDU across PPDUs with FCS err */ 6429 A_UINT32 mpdu_cnt_fcs_err; 6430 /** Num MSDU across PPDUs */ 6431 A_UINT32 tcp_msdu_cnt; 6432 /** Num MSDU across PPDUs */ 6433 A_UINT32 tcp_ack_msdu_cnt; 6434 /** Num MSDU across PPDUs */ 6435 A_UINT32 udp_msdu_cnt; 6436 /** Num MSDU across PPDUs */ 6437 A_UINT32 other_msdu_cnt; 6438 /** Num MPDU on FW ring indicated */ 6439 A_UINT32 fw_ring_mpdu_ind; 6440 /** Num MGMT MPDU given to protocol */ 6441 A_UINT32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6442 /** Num ctrl MPDU given to protocol */ 6443 A_UINT32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 6444 /** Num mcast data packet received */ 6445 A_UINT32 fw_ring_mcast_data_msdu; 6446 /** Num broadcast data packet received */ 6447 A_UINT32 fw_ring_bcast_data_msdu; 6448 /** Num unicast data packet received */ 6449 A_UINT32 fw_ring_ucast_data_msdu; 6450 /** Num null data packet received */ 6451 A_UINT32 fw_ring_null_data_msdu; 6452 /** Num MPDU on FW ring dropped */ 6453 A_UINT32 fw_ring_mpdu_drop; 6454 6455 /** Num buf indication to offload */ 6456 A_UINT32 ofld_local_data_ind_cnt; 6457 /** Num buf recycle from offload */ 6458 A_UINT32 ofld_local_data_buf_recycle_cnt; 6459 /** Num buf indication to data_rx */ 6460 A_UINT32 drx_local_data_ind_cnt; 6461 /** Num buf recycle from data_rx */ 6462 A_UINT32 drx_local_data_buf_recycle_cnt; 6463 /** Num buf indication to protocol */ 6464 A_UINT32 local_nondata_ind_cnt; 6465 /** Num buf recycle from protocol */ 6466 A_UINT32 local_nondata_buf_recycle_cnt; 6467 6468 /** Num buf fed */ 6469 A_UINT32 fw_status_buf_ring_refill_cnt; 6470 /** Num ring empty encountered */ 6471 A_UINT32 fw_status_buf_ring_empty_cnt; 6472 /** Num buf fed */ 6473 A_UINT32 fw_pkt_buf_ring_refill_cnt; 6474 /** Num ring empty encountered */ 6475 A_UINT32 fw_pkt_buf_ring_empty_cnt; 6476 /** Num buf fed */ 6477 A_UINT32 fw_link_buf_ring_refill_cnt; 6478 /** Num ring empty encountered */ 6479 A_UINT32 fw_link_buf_ring_empty_cnt; 6480 6481 /** Num buf fed */ 6482 A_UINT32 host_pkt_buf_ring_refill_cnt; 6483 /** Num ring empty encountered */ 6484 A_UINT32 host_pkt_buf_ring_empty_cnt; 6485 /** Num buf fed */ 6486 A_UINT32 mon_pkt_buf_ring_refill_cnt; 6487 /** Num ring empty encountered */ 6488 A_UINT32 mon_pkt_buf_ring_empty_cnt; 6489 /** Num buf fed */ 6490 A_UINT32 mon_status_buf_ring_refill_cnt; 6491 /** Num ring empty encountered */ 6492 A_UINT32 mon_status_buf_ring_empty_cnt; 6493 /** Num buf fed */ 6494 A_UINT32 mon_desc_buf_ring_refill_cnt; 6495 /** Num ring empty encountered */ 6496 A_UINT32 mon_desc_buf_ring_empty_cnt; 6497 /** Num buf fed */ 6498 A_UINT32 mon_dest_ring_update_cnt; 6499 /** Num ring full encountered */ 6500 A_UINT32 mon_dest_ring_full_cnt; 6501 6502 /** Num rx suspend is attempted */ 6503 A_UINT32 rx_suspend_cnt; 6504 /** Num rx suspend failed */ 6505 A_UINT32 rx_suspend_fail_cnt; 6506 /** Num rx resume attempted */ 6507 A_UINT32 rx_resume_cnt; 6508 /** Num rx resume failed */ 6509 A_UINT32 rx_resume_fail_cnt; 6510 /** Num rx ring switch */ 6511 A_UINT32 rx_ring_switch_cnt; 6512 /** Num rx ring restore */ 6513 A_UINT32 rx_ring_restore_cnt; 6514 /** Num rx flush issued */ 6515 A_UINT32 rx_flush_cnt; 6516 /** Num rx recovery */ 6517 A_UINT32 rx_recovery_reset_cnt; 6518 } htt_stats_rx_pdev_fw_stats_tlv; 6519 /* preserve old name alias for new name consistent with the tag name */ 6520 typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv; 6521 6522 typedef struct { 6523 htt_tlv_hdr_t tlv_hdr; 6524 /** peer mac address */ 6525 htt_mac_addr peer_mac_addr; 6526 /** Num of tx mgmt frames with subtype on peer level */ 6527 A_UINT32 peer_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6528 /** Num of rx mgmt frames with subtype on peer level */ 6529 A_UINT32 peer_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 6530 } htt_stats_peer_ctrl_path_txrx_stats_tlv; 6531 /* preserve old name alias for new name consistent with the tag name */ 6532 typedef htt_stats_peer_ctrl_path_txrx_stats_tlv 6533 htt_peer_ctrl_path_txrx_stats_tlv; 6534 6535 #define HTT_STATS_PHY_ERR_MAX 43 6536 6537 typedef struct { 6538 htt_tlv_hdr_t tlv_hdr; 6539 6540 /** 6541 * BIT [ 7 : 0] :- mac_id 6542 * BIT [31 : 8] :- reserved 6543 */ 6544 A_UINT32 mac_id__word; 6545 /** Num of phy err */ 6546 A_UINT32 total_phy_err_cnt; 6547 /** Counts of different types of phy errs 6548 * The mapping of PHY error types to phy_err array elements is HW dependent. 6549 * The only currently-supported mapping is shown below: 6550 * 6551 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 6552 * 1 phyrx_err_synth_off 6553 * 2 phyrx_err_ofdma_timing 6554 * 3 phyrx_err_ofdma_signal_parity 6555 * 4 phyrx_err_ofdma_rate_illegal 6556 * 5 phyrx_err_ofdma_length_illegal 6557 * 6 phyrx_err_ofdma_restart 6558 * 7 phyrx_err_ofdma_service 6559 * 8 phyrx_err_ppdu_ofdma_power_drop 6560 * 9 phyrx_err_cck_blokker 6561 * 10 phyrx_err_cck_timing 6562 * 11 phyrx_err_cck_header_crc 6563 * 12 phyrx_err_cck_rate_illegal 6564 * 13 phyrx_err_cck_length_illegal 6565 * 14 phyrx_err_cck_restart 6566 * 15 phyrx_err_cck_service 6567 * 16 phyrx_err_cck_power_drop 6568 * 17 phyrx_err_ht_crc_err 6569 * 18 phyrx_err_ht_length_illegal 6570 * 19 phyrx_err_ht_rate_illegal 6571 * 20 phyrx_err_ht_zlf 6572 * 21 phyrx_err_false_radar_ext 6573 * 22 phyrx_err_green_field 6574 * 23 phyrx_err_bw_gt_dyn_bw 6575 * 24 phyrx_err_leg_ht_mismatch 6576 * 25 phyrx_err_vht_crc_error 6577 * 26 phyrx_err_vht_siga_unsupported 6578 * 27 phyrx_err_vht_lsig_len_invalid 6579 * 28 phyrx_err_vht_ndp_or_zlf 6580 * 29 phyrx_err_vht_nsym_lt_zero 6581 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 6582 * 31 phyrx_err_vht_rx_skip_group_id0 6583 * 32 phyrx_err_vht_rx_skip_group_id1to62 6584 * 33 phyrx_err_vht_rx_skip_group_id63 6585 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 6586 * 35 phyrx_err_defer_nap 6587 * 36 phyrx_err_fdomain_timeout 6588 * 37 phyrx_err_lsig_rel_check 6589 * 38 phyrx_err_bt_collision 6590 * 39 phyrx_err_unsupported_mu_feedback 6591 * 40 phyrx_err_ppdu_tx_interrupt_rx 6592 * 41 phyrx_err_unsupported_cbf 6593 * 42 phyrx_err_other 6594 */ 6595 A_UINT32 phy_err[HTT_STATS_PHY_ERR_MAX]; 6596 } htt_stats_rx_pdev_fw_stats_phy_err_tlv; 6597 /* preserve old name alias for new name consistent with the tag name */ 6598 typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv; 6599 6600 #define HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6601 6602 /* NOTE: Variable length TLV, use length spec to infer array size */ 6603 typedef struct { 6604 htt_tlv_hdr_t tlv_hdr; 6605 /** Num error MPDU for each RxDMA error type */ 6606 A_UINT32 fw_ring_mpdu_err[1]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ 6607 } htt_stats_rx_pdev_fw_ring_mpdu_err_tlv; 6608 /* preserve old name alias for new name consistent with the tag name */ 6609 typedef htt_stats_rx_pdev_fw_ring_mpdu_err_tlv 6610 htt_rx_pdev_fw_ring_mpdu_err_tlv_v; 6611 6612 #define HTT_RX_PDEV_FW_MPDU_DROP_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) 6613 6614 /* NOTE: Variable length TLV, use length spec to infer array size */ 6615 typedef struct { 6616 htt_tlv_hdr_t tlv_hdr; 6617 /** Num MPDU dropped */ 6618 A_UINT32 fw_mpdu_drop[1]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 6619 } htt_stats_rx_pdev_fw_mpdu_drop_tlv; 6620 /* preserve old name alias for new name consistent with the tag name */ 6621 typedef htt_stats_rx_pdev_fw_mpdu_drop_tlv htt_rx_pdev_fw_mpdu_drop_tlv_v; 6622 6623 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX 6624 * TLV_TAGS: 6625 * - HTT_STATS_RX_SOC_FW_STATS_TAG (head TLV in soc_stats) 6626 * - HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG (inside soc_stats) 6627 * - HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG (inside soc_stats) 6628 * - HTT_STATS_RX_PDEV_FW_STATS_TAG 6629 * - HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG 6630 * - HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG 6631 */ 6632 /* NOTE: 6633 * This structure is for documentation, and cannot be safely used directly. 6634 * Instead, use the constituent TLV structures to fill/parse. 6635 */ 6636 typedef struct { 6637 htt_rx_soc_stats_t soc_stats; 6638 htt_stats_rx_pdev_fw_stats_tlv fw_stats_tlv; 6639 htt_stats_rx_pdev_fw_ring_mpdu_err_tlv fw_ring_mpdu_err_tlv; 6640 htt_stats_rx_pdev_fw_mpdu_drop_tlv fw_ring_mpdu_drop; 6641 htt_stats_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; 6642 } htt_rx_pdev_stats_t; 6643 6644 /* STATS_TYPE : HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS 6645 * TLV_TAGS: 6646 * - HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG 6647 * 6648 */ 6649 typedef struct { 6650 htt_stats_peer_ctrl_path_txrx_stats_tlv peer_ctrl_path_txrx_stats_tlv; 6651 } htt_ctrl_path_txrx_stats_t; 6652 6653 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 6654 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 6655 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 6656 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 6657 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 6658 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 6659 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 6660 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 6661 6662 typedef struct { 6663 htt_tlv_hdr_t tlv_hdr; 6664 6665 /* Below values are obtained from the HW Cycles counter registers */ 6666 A_UINT32 tx_frame_usec; 6667 A_UINT32 rx_frame_usec; 6668 A_UINT32 rx_clear_usec; 6669 A_UINT32 my_rx_frame_usec; 6670 A_UINT32 usec_cnt; 6671 A_UINT32 med_rx_idle_usec; 6672 A_UINT32 med_tx_idle_global_usec; 6673 A_UINT32 cca_obss_usec; 6674 A_UINT32 pre_rx_frame_usec; 6675 } htt_stats_pdev_cca_counters_tlv; 6676 /* preserve old name alias for new name consistent with the tag name */ 6677 typedef htt_stats_pdev_cca_counters_tlv htt_pdev_stats_cca_counters_tlv; 6678 6679 /* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED, 6680 * due to lack of support in some host stats infrastructures for 6681 * TLVs nested within TLVs. 6682 */ 6683 typedef struct { 6684 htt_tlv_hdr_t tlv_hdr; 6685 6686 /** The channel number on which these stats were collected */ 6687 A_UINT32 chan_num; 6688 6689 /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 6690 A_UINT32 num_records; 6691 6692 /** 6693 * Bit map of valid CCA counters 6694 * Bit0 - tx_frame_usec 6695 * Bit1 - rx_frame_usec 6696 * Bit2 - rx_clear_usec 6697 * Bit3 - my_rx_frame_usec 6698 * bit4 - usec_cnt 6699 * Bit5 - med_rx_idle_usec 6700 * Bit6 - med_tx_idle_global_usec 6701 * Bit7 - cca_obss_usec 6702 * 6703 * See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs 6704 */ 6705 A_UINT32 valid_cca_counters_bitmap; 6706 6707 /** Indicates the stats collection interval 6708 * Valid Values: 6709 * 100 - For the 100ms interval CCA stats histogram 6710 * 1000 - For 1sec interval CCA histogram 6711 * 0xFFFFFFFF - For Cumulative CCA Stats 6712 */ 6713 A_UINT32 collection_interval; 6714 6715 /** 6716 * This will be followed by an array which contains the CCA stats 6717 * collected in the last N intervals, 6718 * if the indication is for last N intervals CCA stats. 6719 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 6720 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 6721 */ 6722 htt_stats_pdev_cca_counters_tlv cca_hist_tlv[1]; 6723 } htt_pdev_cca_stats_hist_tlv; 6724 6725 typedef struct { 6726 htt_tlv_hdr_t tlv_hdr; 6727 6728 /** The channel number on which these stats were collected */ 6729 A_UINT32 chan_num; 6730 6731 /** num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 6732 A_UINT32 num_records; 6733 6734 /** 6735 * Bit map of valid CCA counters 6736 * Bit0 - tx_frame_usec 6737 * Bit1 - rx_frame_usec 6738 * Bit2 - rx_clear_usec 6739 * Bit3 - my_rx_frame_usec 6740 * bit4 - usec_cnt 6741 * Bit5 - med_rx_idle_usec 6742 * Bit6 - med_tx_idle_global_usec 6743 * Bit7 - cca_obss_usec 6744 * 6745 * See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs 6746 */ 6747 A_UINT32 valid_cca_counters_bitmap; 6748 6749 /** Indicates the stats collection interval 6750 * Valid Values: 6751 * 100 - For the 100ms interval CCA stats histogram 6752 * 1000 - For 1sec interval CCA histogram 6753 * 0xFFFFFFFF - For Cumulative CCA Stats 6754 */ 6755 A_UINT32 collection_interval; 6756 6757 /** 6758 * This will be followed by an array which contains the CCA stats 6759 * collected in the last N intervals, 6760 * if the indication is for last N intervals CCA stats. 6761 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 6762 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 6763 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 6764 */ 6765 } htt_pdev_cca_stats_hist_v1_tlv; 6766 6767 #define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000000f 6768 #define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0 6769 6770 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M 0x0000fff0 6771 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S 4 6772 6773 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000 6774 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16 6775 6776 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M 0x00020000 6777 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S 17 6778 6779 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M 0x00040000 6780 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S 18 6781 6782 #define HTT_TWT_SESSION_FLAG_FLOW_ID_GET(_var) \ 6783 (((_var) & HTT_TWT_SESSION_FLAG_FLOW_ID_M) >> \ 6784 HTT_TWT_SESSION_FLAG_FLOW_ID_S) 6785 6786 #define HTT_TWT_SESSION_FLAG_FLOW_ID_SET(_var, _val) \ 6787 do { \ 6788 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_FLOW_ID, _val); \ 6789 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \ 6790 } while (0) 6791 6792 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_GET(_var) \ 6793 (((_var) & HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M) >> \ 6794 HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S) 6795 6796 #define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_SET(_var, _val) \ 6797 do { \ 6798 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT, _val); \ 6799 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S)); \ 6800 } while (0) 6801 6802 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \ 6803 (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \ 6804 HTT_TWT_SESSION_FLAG_BCAST_TWT_S) 6805 6806 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_SET(_var, _val) \ 6807 do { \ 6808 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BCAST_TWT, _val); \ 6809 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BCAST_TWT_S)); \ 6810 } while (0) 6811 6812 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_GET(_var) \ 6813 (((_var) & HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M) >> \ 6814 HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S) 6815 6816 #define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_SET(_var, _val) \ 6817 do { \ 6818 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_TRIGGER_TWT, _val); \ 6819 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)); \ 6820 } while (0) 6821 6822 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_GET(_var) \ 6823 (((_var) & HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M) >> \ 6824 HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S) 6825 6826 #define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_SET(_var, _val) \ 6827 do { \ 6828 HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_ANNOUN_TWT, _val); \ 6829 ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)); \ 6830 } while (0) 6831 6832 #define TWT_DIALOG_ID_UNAVAILABLE 0xFFFFFFFF 6833 6834 typedef struct { 6835 htt_tlv_hdr_t tlv_hdr; 6836 6837 A_UINT32 vdev_id; 6838 htt_mac_addr peer_mac; 6839 A_UINT32 flow_id_flags; 6840 /** 6841 * TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is 6842 * not initiated by host 6843 */ 6844 A_UINT32 dialog_id; 6845 A_UINT32 wake_dura_us; 6846 A_UINT32 wake_intvl_us; 6847 A_UINT32 sp_offset_us; 6848 } htt_stats_pdev_twt_session_tlv; 6849 /* preserve old name alias for new name consistent with the tag name */ 6850 typedef htt_stats_pdev_twt_session_tlv htt_pdev_stats_twt_session_tlv; 6851 6852 typedef struct { 6853 htt_tlv_hdr_t tlv_hdr; 6854 6855 A_UINT32 pdev_id; 6856 A_UINT32 num_sessions; 6857 6858 htt_stats_pdev_twt_session_tlv twt_session[1]; 6859 } htt_stats_pdev_twt_sessions_tlv; 6860 /* preserve old name alias for new name consistent with the tag name */ 6861 typedef htt_stats_pdev_twt_sessions_tlv htt_pdev_stats_twt_sessions_tlv; 6862 6863 /* STATS_TYPE: HTT_DBG_EXT_STATS_TWT_SESSIONS 6864 * TLV_TAGS: 6865 * - HTT_STATS_PDEV_TWT_SESSIONS_TAG 6866 * - HTT_STATS_PDEV_TWT_SESSION_TAG 6867 */ 6868 /* NOTE: 6869 * This structure is for documentation, and cannot be safely used directly. 6870 * Instead, use the constituent TLV structures to fill/parse. 6871 */ 6872 typedef struct { 6873 htt_stats_pdev_twt_session_tlv twt_sessions[1]; 6874 } htt_pdev_twt_sessions_stats_t; 6875 6876 typedef enum { 6877 /* Global link descriptor queued in REO */ 6878 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 6879 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 6880 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 6881 /*Number of queue descriptors of this aging group */ 6882 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 6883 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 6884 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 6885 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 6886 /* Total number of MSDUs buffered in AC */ 6887 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 6888 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 6889 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 6890 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 6891 6892 HTT_RX_REO_RESOURCE_STATS_MAX = 16 6893 } htt_rx_reo_resource_sample_id_enum; 6894 6895 typedef struct { 6896 htt_tlv_hdr_t tlv_hdr; 6897 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 6898 /** htt_rx_reo_debug_sample_id_enum */ 6899 A_UINT32 sample_id; 6900 /** Max value of all samples */ 6901 A_UINT32 total_max; 6902 /** Average value of total samples */ 6903 A_UINT32 total_avg; 6904 /** Num of samples including both zeros and non zeros ones*/ 6905 A_UINT32 total_sample; 6906 /** Average value of all non zeros samples */ 6907 A_UINT32 non_zeros_avg; 6908 /** Num of non zeros samples */ 6909 A_UINT32 non_zeros_sample; 6910 /** Max value of last N non zero samples (N = last_non_zeros_sample) */ 6911 A_UINT32 last_non_zeros_max; 6912 /** Min value of last N non zero samples (N = last_non_zeros_sample) */ 6913 A_UINT32 last_non_zeros_min; 6914 /** Average value of last N non zero samples (N = last_non_zeros_sample) */ 6915 A_UINT32 last_non_zeros_avg; 6916 /** Num of last non zero samples */ 6917 A_UINT32 last_non_zeros_sample; 6918 } htt_stats_rx_reo_resource_stats_tlv; 6919 /* preserve old name alias for new name consistent with the tag name */ 6920 typedef htt_stats_rx_reo_resource_stats_tlv htt_rx_reo_resource_stats_tlv_v; 6921 6922 /* STATS_TYPE: HTT_DBG_EXT_STATS_REO_RESOURCE_STATS 6923 * TLV_TAGS: 6924 * - HTT_STATS_RX_REO_RESOURCE_STATS_TAG 6925 */ 6926 /* NOTE: 6927 * This structure is for documentation, and cannot be safely used directly. 6928 * Instead, use the constituent TLV structures to fill/parse. 6929 */ 6930 typedef struct { 6931 htt_stats_rx_reo_resource_stats_tlv reo_resource_stats; 6932 } htt_soc_reo_resource_stats_t; 6933 6934 /* == TX SOUNDING STATS == */ 6935 6936 /* config_param0 */ 6937 6938 #define HTT_DBG_EXT_STATS_SET_VDEV_MASK(_var) ((_var << 1) | 0x1) 6939 #define HTT_DBG_EXT_STATS_GET_VDEV_ID_FROM_VDEV_MASK(_var) ((_var >> 1) & 0xFF) 6940 #define HTT_DBG_EXT_STATS_IS_VDEV_ID_SET(_var) ((_var) & 0x1) 6941 6942 typedef enum { 6943 /* Implicit beamforming stats */ 6944 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 6945 /* Single user short inter frame sequence steer stats */ 6946 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 6947 /* Single user random back off steer stats */ 6948 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 6949 /* Multi user short inter frame sequence steer stats */ 6950 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 6951 /* Multi user random back off steer stats */ 6952 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 6953 /* For backward compatibility new modes cannot be added */ 6954 HTT_TXBF_MAX_NUM_OF_MODES = 5 6955 } htt_txbf_sound_steer_modes; 6956 6957 typedef enum { 6958 HTT_TX_AC_SOUNDING_MODE = 0, 6959 HTT_TX_AX_SOUNDING_MODE = 1, 6960 HTT_TX_BE_SOUNDING_MODE = 2, 6961 HTT_TX_CMN_SOUNDING_MODE = 3, 6962 HTT_TX_CV_CORR_MODE = 4, 6963 } htt_stats_sounding_tx_mode; 6964 6965 #define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 6966 6967 typedef struct { 6968 htt_tlv_hdr_t tlv_hdr; 6969 A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 6970 /* Counts number of soundings for all steering modes in each bw */ 6971 A_UINT32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 6972 A_UINT32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 6973 A_UINT32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 6974 A_UINT32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 6975 /** 6976 * The sounding array is a 2-D array stored as an 1-D array of 6977 * A_UINT32. The stats for a particular user/bw combination is 6978 * referenced with the following: 6979 * 6980 * sounding[(user* max_bw) + bw] 6981 * 6982 * ... where max_bw == 4 for 160mhz 6983 */ 6984 A_UINT32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 6985 6986 /* cv upload handler stats */ 6987 /** total times CV nc mismatched */ 6988 A_UINT32 cv_nc_mismatch_err; 6989 /** total times CV has FCS error */ 6990 A_UINT32 cv_fcs_err; 6991 /** total times CV has invalid NSS index */ 6992 A_UINT32 cv_frag_idx_mismatch; 6993 /** total times CV has invalid SW peer ID */ 6994 A_UINT32 cv_invalid_peer_id; 6995 /** total times CV rejected because TXBF is not setup in peer */ 6996 A_UINT32 cv_no_txbf_setup; 6997 /** total times CV expired while in updating state */ 6998 A_UINT32 cv_expiry_in_update; 6999 /** total times Pkt b/w exceeding the cbf_bw */ 7000 A_UINT32 cv_pkt_bw_exceed; 7001 /** total times CV DMA not completed */ 7002 A_UINT32 cv_dma_not_done_err; 7003 /** total times CV update to peer failed */ 7004 A_UINT32 cv_update_failed; 7005 7006 /* cv query stats */ 7007 /** total times CV query happened */ 7008 A_UINT32 cv_total_query; 7009 /** total pattern based CV query */ 7010 A_UINT32 cv_total_pattern_query; 7011 /** total BW based CV query */ 7012 A_UINT32 cv_total_bw_query; 7013 /** incorrect encoding in CV flags */ 7014 A_UINT32 cv_invalid_bw_coding; 7015 /** forced sounding enabled for the peer */ 7016 A_UINT32 cv_forced_sounding; 7017 /** standalone sounding sequence on-going */ 7018 A_UINT32 cv_standalone_sounding; 7019 /** NC of available CV lower than expected */ 7020 A_UINT32 cv_nc_mismatch; 7021 /** feedback type different from expected */ 7022 A_UINT32 cv_fb_type_mismatch; 7023 /** CV BW not equal to expected BW for OFDMA */ 7024 A_UINT32 cv_ofdma_bw_mismatch; 7025 /** CV BW not greater than or equal to expected BW */ 7026 A_UINT32 cv_bw_mismatch; 7027 /** CV pattern not matching with the expected pattern */ 7028 A_UINT32 cv_pattern_mismatch; 7029 /** CV available is of different preamble type than expected. */ 7030 A_UINT32 cv_preamble_mismatch; 7031 /** NR of available CV is lower than expected. */ 7032 A_UINT32 cv_nr_mismatch; 7033 /** CV in use count has exceeded threshold and cannot be used further. */ 7034 A_UINT32 cv_in_use_cnt_exceeded; 7035 /** A valid CV has been found. */ 7036 A_UINT32 cv_found; 7037 /** No valid CV was found. */ 7038 A_UINT32 cv_not_found; 7039 /** Sounding per user in 320MHz bandwidth */ 7040 A_UINT32 sounding_320[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; 7041 /** Counts number of soundings for all steering modes in 320MHz bandwidth */ 7042 A_UINT32 cbf_320[HTT_TXBF_MAX_NUM_OF_MODES]; 7043 /* This part can be used for new counters added for CV query/upload. */ 7044 /** non-trigger based ranging sequence on-going */ 7045 A_UINT32 cv_ntbr_sounding; 7046 /** CV found, but upload is in progress. */ 7047 A_UINT32 cv_found_upload_in_progress; 7048 /** Expired CV found during query. */ 7049 A_UINT32 cv_expired_during_query; 7050 /** total times CV dma timeout happened */ 7051 A_UINT32 cv_dma_timeout_error; 7052 /** total times CV bufs uploaded for IBF case */ 7053 A_UINT32 cv_buf_ibf_uploads; 7054 /** total times CV bufs uploaded for EBF case */ 7055 A_UINT32 cv_buf_ebf_uploads; 7056 /** total times CV bufs received from IPC ring */ 7057 A_UINT32 cv_buf_received; 7058 /** total times CV bufs fed back to the IPC ring */ 7059 A_UINT32 cv_buf_fed_back; 7060 /** Total times CV query happened for IBF case */ 7061 A_UINT32 cv_total_query_ibf; 7062 /** A valid CV has been found for IBF case */ 7063 A_UINT32 cv_found_ibf; 7064 /** A valid CV has not been found for IBF case */ 7065 A_UINT32 cv_not_found_ibf; 7066 /** Expired CV found during query for IBF case */ 7067 A_UINT32 cv_expired_during_query_ibf; 7068 /** Total number of times adaptive sounding logic has been queried */ 7069 A_UINT32 adaptive_snd_total_query; 7070 /** 7071 * Total number of times adaptive sounding mcs drop has been computed 7072 * and recorded. 7073 */ 7074 A_UINT32 adaptive_snd_total_mcs_drop[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 7075 /** Total number of times adaptive sounding logic kicked in */ 7076 A_UINT32 adaptive_snd_kicked_in; 7077 /** Total number of times we switched back to normal sounding interval */ 7078 A_UINT32 adaptive_snd_back_to_default; 7079 7080 /** 7081 * Below are CV correlation feature related stats. 7082 * This feature is used for DL MU MIMO, but is not available 7083 * from certain legacy targets. 7084 */ 7085 7086 /** number of CV Correlation triggers for online mode */ 7087 A_UINT32 cv_corr_trigger_online_mode; 7088 /** number of CV Correlation triggers for offline mode */ 7089 A_UINT32 cv_corr_trigger_offline_mode; 7090 /** number of CV Correlation triggers for hybrid mode */ 7091 A_UINT32 cv_corr_trigger_hybrid_mode; 7092 /** number of CV Correlation triggers with computation level 0 */ 7093 A_UINT32 cv_corr_trigger_computation_level_0; 7094 /** number of CV Correlation triggers with computation level 1 */ 7095 A_UINT32 cv_corr_trigger_computation_level_1; 7096 /** number of CV Correlation triggers with computation level 2 */ 7097 A_UINT32 cv_corr_trigger_computation_level_2; 7098 /** number of users for which CV Correlation was triggered */ 7099 A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7100 /** number of streams for which CV Correlation was triggered */ 7101 A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7102 /** number of CV Correlation buffers received through IPC tickle */ 7103 A_UINT32 cv_corr_upload_total_buf_received; 7104 /** number of CV Correlation buffers fed back to the IPC ring */ 7105 A_UINT32 cv_corr_upload_total_buf_fed_back; 7106 /** number of CV Correlation buffers for which processing failed */ 7107 A_UINT32 cv_corr_upload_total_processing_failed; 7108 /** 7109 * number of CV Correlation buffers for which processing failed, 7110 * due to no users being present in parsed buffer 7111 */ 7112 A_UINT32 cv_corr_upload_failed_total_users_zero; 7113 /** 7114 * number of CV Correlation buffers for which processing failed, 7115 * due to number of users present in parsed buffer exceeded 7116 * CV_CORR_MAX_NUM_COLUMNS 7117 */ 7118 A_UINT32 cv_corr_upload_failed_total_users_exceeded; 7119 /** 7120 * number of CV Correlation buffers for which processing failed, 7121 * due to peer pointer for parsed peer not available 7122 */ 7123 A_UINT32 cv_corr_upload_failed_peer_not_found; 7124 /** 7125 * number of CV Correlation buffers for which processing encountered, 7126 * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS 7127 */ 7128 A_UINT32 cv_corr_upload_user_nss_exceeded; 7129 /** 7130 * number of CV Correlation buffers for which processing encountered, 7131 * invalid reverse look up index for fetching CV correlation results 7132 */ 7133 A_UINT32 cv_corr_upload_invalid_lookup_index; 7134 /** number of users present in uploaded CV Correlation results buffer */ 7135 A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7136 /** number of streams present in uploaded CV Correlation results buffer */ 7137 A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; 7138 } htt_stats_tx_sounding_stats_tlv; 7139 /* preserve old name alias for new name consistent with the tag name */ 7140 typedef htt_stats_tx_sounding_stats_tlv htt_tx_sounding_stats_tlv; 7141 7142 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO 7143 * TLV_TAGS: 7144 * - HTT_STATS_TX_SOUNDING_STATS_TAG 7145 */ 7146 /* NOTE: 7147 * This structure is for documentation, and cannot be safely used directly. 7148 * Instead, use the constituent TLV structures to fill/parse. 7149 */ 7150 typedef struct { 7151 htt_stats_tx_sounding_stats_tlv sounding_tlv; 7152 } htt_tx_sounding_stats_t; 7153 7154 typedef struct { 7155 htt_tlv_hdr_t tlv_hdr; 7156 7157 A_UINT32 num_obss_tx_ppdu_success; 7158 A_UINT32 num_obss_tx_ppdu_failure; 7159 /** num_sr_tx_transmissions: 7160 * Counter of TX done by aborting other BSS RX with spatial reuse 7161 * (for cases where rx RSSI from other BSS is below the packet-detection 7162 * threshold for doing spatial reuse) 7163 */ 7164 union { 7165 A_UINT32 num_sr_tx_transmissions; /* CORRECTED - use this one */ 7166 A_UINT32 num_sr_tx_tranmissions; /* DEPRECATED - has typo in name */ 7167 }; 7168 union { 7169 /** 7170 * Count the number of times the RSSI from an other-BSS signal 7171 * is below the spatial reuse power threshold, thus providing an 7172 * opportunity for spatial reuse since OBSS interference will be 7173 * inconsequential. 7174 */ 7175 A_UINT32 num_spatial_reuse_opportunities; 7176 7177 /* DEPRECATED: num_sr_rx_ge_pd_rssi_thr 7178 * This old name has been deprecated because it does not 7179 * clearly and accurately reflect the information stored within 7180 * this field. 7181 * Use the new name (num_spatial_reuse_opportunities) instead of 7182 * the deprecated old name (num_sr_rx_ge_pd_rssi_thr). 7183 */ 7184 A_UINT32 num_sr_rx_ge_pd_rssi_thr; 7185 }; 7186 7187 /** 7188 * Count of number of times OBSS frames were aborted and non-SRG 7189 * opportunities were created. Non-SRG opportunities are created when 7190 * incoming OBSS RSSI is lesser than the global configured non-SRG RSSI 7191 * threshold and non-SRG OBSS color / non-SRG OBSS BSSID registers 7192 * allow non-SRG TX. 7193 */ 7194 A_UINT32 num_non_srg_opportunities; 7195 /** 7196 * Count of number of times TX PPDU were transmitted using non-SRG 7197 * opportunities created. Incoming OBSS frame RSSI is compared with per 7198 * PPDU non-SRG RSSI threshold configured in each PPDU. If incoming OBSS 7199 * RSSI < non-SRG RSSI threshold configured in each PPDU, then non-SRG 7200 * transmission happens. 7201 */ 7202 A_UINT32 num_non_srg_ppdu_tried; 7203 /** 7204 * Count of number of times non-SRG based TX transmissions were successful 7205 */ 7206 A_UINT32 num_non_srg_ppdu_success; 7207 /** 7208 * Count of number of times OBSS frames were aborted and SRG opportunities 7209 * were created. Srg opportunities are created when incoming OBSS RSSI 7210 * is less than the global configured SRG RSSI threshold and SRC OBSS 7211 * color / SRG OBSS BSSID / SRG partial bssid / SRG BSS color bitmap 7212 * registers allow SRG TX. 7213 */ 7214 A_UINT32 num_srg_opportunities; 7215 /** 7216 * Count of number of times TX PPDU were transmitted using SRG 7217 * opportunities created. 7218 * Incoming OBSS frame RSSI is compared with per PPDU SRG RSSI 7219 * threshold configured in each PPDU. 7220 * If incoming OBSS RSSI < SRG RSSI threshold configured in each PPDU, 7221 * then SRG transmission happens. 7222 */ 7223 A_UINT32 num_srg_ppdu_tried; 7224 /** 7225 * Count of number of times SRG based TX transmissions were successful 7226 */ 7227 A_UINT32 num_srg_ppdu_success; 7228 /** 7229 * Count of number of times PSR opportunities were created by aborting 7230 * OBSS UL OFDMA HE-TB PPDU frame. HE-TB ppdu frames are aborted if the 7231 * spatial reuse info in the OBSS trigger common field is set to allow PSR 7232 * based spatial reuse. 7233 */ 7234 A_UINT32 num_psr_opportunities; 7235 /** 7236 * Count of number of times TX PPDU were transmitted using PSR 7237 * opportunities created. 7238 */ 7239 A_UINT32 num_psr_ppdu_tried; 7240 /** 7241 * Count of number of times PSR based TX transmissions were successful. 7242 */ 7243 A_UINT32 num_psr_ppdu_success; 7244 /** 7245 * Count of number of times TX PPDU per access category were transmitted 7246 * using non-SRG opportunities created. 7247 */ 7248 A_UINT32 num_non_srg_ppdu_tried_per_ac[HTT_NUM_AC_WMM]; 7249 /** 7250 * Count of number of times non-SRG based TX transmissions per access 7251 * category were successful 7252 */ 7253 A_UINT32 num_non_srg_ppdu_success_per_ac[HTT_NUM_AC_WMM]; 7254 /** 7255 * Count of number of times TX PPDU per access category were transmitted 7256 * using SRG opportunities created. 7257 */ 7258 A_UINT32 num_srg_ppdu_tried_per_ac[HTT_NUM_AC_WMM]; 7259 /** 7260 * Count of number of times SRG based TX transmissions per access 7261 * category were successful 7262 */ 7263 A_UINT32 num_srg_ppdu_success_per_ac[HTT_NUM_AC_WMM]; 7264 /** 7265 * Count of number of times ppdu was flushed due to ongoing OBSS 7266 * frame duration value lesser than minimum required frame duration. 7267 */ 7268 A_UINT32 num_obss_min_duration_check_flush_cnt; 7269 /** 7270 * Count of number of times ppdu was flushed due to ppdu duration 7271 * exceeding aborted OBSS frame duration 7272 */ 7273 A_UINT32 num_sr_ppdu_abort_flush_cnt; 7274 } htt_stats_pdev_obss_pd_tlv; 7275 /* preserve old name alias for new name consistent with the tag name */ 7276 typedef htt_stats_pdev_obss_pd_tlv htt_pdev_obss_pd_stats_tlv; 7277 7278 /* NOTE: 7279 * This structure is for documentation, and cannot be safely used directly. 7280 * Instead, use the constituent TLV structures to fill/parse. 7281 */ 7282 typedef struct { 7283 htt_stats_pdev_obss_pd_tlv obss_pd_stat; 7284 } htt_pdev_obss_pd_stats_t; 7285 7286 typedef struct { 7287 htt_tlv_hdr_t tlv_hdr; 7288 A_UINT32 pdev_id; 7289 A_UINT32 current_head_idx; 7290 A_UINT32 current_tail_idx; 7291 A_UINT32 num_htt_msgs_sent; 7292 /** 7293 * Time in milliseconds for which the ring has been in 7294 * its current backpressure condition 7295 */ 7296 A_UINT32 backpressure_time_ms; 7297 /** backpressure_hist - 7298 * histogram showing how many times different degrees of backpressure 7299 * duration occurred: 7300 * Index 0 indicates the number of times ring was 7301 * continuously in backpressure state for 100 - 200ms. 7302 * Index 1 indicates the number of times ring was 7303 * continuously in backpressure state for 200 - 300ms. 7304 * Index 2 indicates the number of times ring was 7305 * continuously in backpressure state for 300 - 400ms. 7306 * Index 3 indicates the number of times ring was 7307 * continuously in backpressure state for 400 - 500ms. 7308 * Index 4 indicates the number of times ring was 7309 * continuously in backpressure state beyond 500ms. 7310 */ 7311 A_UINT32 backpressure_hist[5]; 7312 } htt_stats_ring_backpressure_stats_tlv; 7313 /* preserve old name alias for new name consistent with the tag name */ 7314 typedef htt_stats_ring_backpressure_stats_tlv htt_ring_backpressure_stats_tlv; 7315 7316 /* STATS_TYPE : HTT_STATS_RING_BACKPRESSURE_STATS_INFO 7317 * TLV_TAGS: 7318 * - HTT_STATS_RING_BACKPRESSURE_STATS_TAG 7319 */ 7320 /* NOTE: 7321 * This structure is for documentation, and cannot be safely used directly. 7322 * Instead, use the constituent TLV structures to fill/parse. 7323 */ 7324 typedef struct { 7325 htt_stats_sring_cmn_tlv cmn_tlv; 7326 struct { 7327 htt_stats_string_tlv sring_str_tlv; 7328 htt_stats_ring_backpressure_stats_tlv backpressure_stats_tlv; 7329 } r[1]; /* variable-length array */ 7330 } htt_ring_backpressure_stats_t; 7331 7332 #define HTT_LATENCY_PROFILE_MAX_HIST 3 7333 #define HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 7334 #define HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 7335 typedef struct { 7336 htt_tlv_hdr_t tlv_hdr; 7337 /** print_header: 7338 * This field suggests whether the host should print a header when 7339 * displaying the TLV (because this is the first latency_prof_stats 7340 * TLV within a series), or if only the TLV contents should be displayed 7341 * without a header (because this is not the first TLV within the series). 7342 */ 7343 A_UINT32 print_header; 7344 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 7345 /** number of data values included in the tot sum */ 7346 A_UINT32 cnt; 7347 /** time in us */ 7348 A_UINT32 min; 7349 /** time in us */ 7350 A_UINT32 max; 7351 A_UINT32 last; 7352 /** time in us */ 7353 A_UINT32 tot; 7354 /** time in us */ 7355 A_UINT32 avg; 7356 /** hist_intvl: 7357 * Histogram interval, i.e. the latency range covered by each 7358 * bin of the histogram, in microsecond units. 7359 * hist[0] counts how many latencies were between 0 to hist_intvl 7360 * hist[1] counts how many latencies were between hist_intvl to 2*hist_intvl 7361 * hist[2] counts how many latencies were more than 2*hist_intvl 7362 */ 7363 A_UINT32 hist_intvl; 7364 A_UINT32 hist[HTT_LATENCY_PROFILE_MAX_HIST]; 7365 /** max page faults in any 1 sampling window */ 7366 A_UINT32 page_fault_max; 7367 /** summed over all sampling windows */ 7368 A_UINT32 page_fault_total; 7369 /** ignored_latency_count: 7370 * ignore some of profile latency to avoid avg skewing 7371 */ 7372 A_UINT32 ignored_latency_count; 7373 /** interrupts_max: max interrupts within any single sampling window */ 7374 A_UINT32 interrupts_max; 7375 /** interrupts_hist: histogram of interrupt rate 7376 * bin0 contains the number of sampling windows that had 0 interrupts, 7377 * bin1 contains the number of sampling windows that had 1-4 interrupts, 7378 * bin2 contains the number of sampling windows that had > 4 interrupts 7379 */ 7380 A_UINT32 interrupts_hist[HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 7381 } htt_stats_latency_prof_stats_tlv; 7382 /* preserve old name alias for new name consistent with the tag name */ 7383 typedef htt_stats_latency_prof_stats_tlv htt_latency_prof_stats_tlv; 7384 7385 typedef struct { 7386 htt_tlv_hdr_t tlv_hdr; 7387 /** duration: 7388 * Time period over which counts were gathered, units = microseconds. 7389 */ 7390 A_UINT32 duration; 7391 A_UINT32 tx_msdu_cnt; 7392 A_UINT32 tx_mpdu_cnt; 7393 A_UINT32 tx_ppdu_cnt; 7394 A_UINT32 rx_msdu_cnt; 7395 A_UINT32 rx_mpdu_cnt; 7396 } htt_stats_latency_ctx_tlv; 7397 /* preserve old name alias for new name consistent with the tag name */ 7398 typedef htt_stats_latency_ctx_tlv htt_latency_prof_ctx_tlv; 7399 7400 typedef struct { 7401 htt_tlv_hdr_t tlv_hdr; 7402 /** count of enabled profiles */ 7403 A_UINT32 prof_enable_cnt; 7404 } htt_stats_latency_cnt_tlv; 7405 /* preserve old name alias for new name consistent with the tag name */ 7406 typedef htt_stats_latency_cnt_tlv htt_latency_prof_cnt_tlv; 7407 7408 /* STATS_TYPE : HTT_DBG_EXT_STATS_LATENCY_PROF_STATS 7409 * TLV_TAGS: 7410 * HTT_STATS_LATENCY_PROF_STATS_TAG / htt_latency_prof_stats_tlv 7411 * HTT_STATS_LATENCY_CTX_TAG / htt_latency_prof_ctx_tlv 7412 * HTT_STATS_LATENCY_CNT_TAG / htt_latency_prof_cnt_tlv 7413 */ 7414 /* NOTE: 7415 * This structure is for documentation, and cannot be safely used directly. 7416 * Instead, use the constituent TLV structures to fill/parse. 7417 */ 7418 typedef struct { 7419 htt_stats_latency_prof_stats_tlv latency_prof_stat; 7420 htt_stats_latency_ctx_tlv latency_ctx_stat; 7421 htt_stats_latency_cnt_tlv latency_cnt_stat; 7422 } htt_soc_latency_stats_t; 7423 7424 #define HTT_RX_MAX_PEAK_OCCUPANCY_INDEX 10 7425 #define HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX 10 7426 #define HTT_RX_SQUARE_INDEX 6 7427 #define HTT_RX_MAX_PEAK_SEARCH_INDEX 4 7428 #define HTT_RX_MAX_PENDING_SEARCH_INDEX 4 7429 7430 /* STATS_TYPE : HTT_DBG_EXT_RX_FSE_STATS 7431 * TLV_TAGS: 7432 * - HTT_STATS_RX_FSE_STATS_TAG 7433 */ 7434 typedef struct { 7435 htt_tlv_hdr_t tlv_hdr; 7436 7437 /** 7438 * Number of times host requested for fse enable/disable 7439 */ 7440 A_UINT32 fse_enable_cnt; 7441 A_UINT32 fse_disable_cnt; 7442 /** 7443 * Number of times host requested for fse cache invalidation 7444 * individual entries or full cache 7445 */ 7446 A_UINT32 fse_cache_invalidate_entry_cnt; 7447 A_UINT32 fse_full_cache_invalidate_cnt; 7448 7449 /** 7450 * Cache hits count will increase if there is a matching flow in the cache 7451 * There is no register for cache miss but the number of cache misses can 7452 * be calculated as 7453 * cache miss = (num_searches - cache_hits) 7454 * Thus, there is no need to have a separate variable for cache misses. 7455 * Num searches is flow search times done in the cache. 7456 */ 7457 A_UINT32 fse_num_cache_hits_cnt; 7458 A_UINT32 fse_num_searches_cnt; 7459 /** 7460 * Cache Occupancy holds 2 types of values: Peak and Current. 7461 * 10 bins are used to keep track of peak occupancy. 7462 * 8 of these bins represent ranges of values, while the first and last 7463 * bins represent the extreme cases of the cache being completely empty 7464 * or completely full. 7465 * For the non-extreme bins, the number of cache occupancy values per 7466 * bin is the maximum cache occupancy (128), divided by the number of 7467 * non-extreme bins (8), so 128/8 = 16 values per bin. 7468 * The range of values for each histogram bins is specified below: 7469 * Bin0 = Counter increments when cache occupancy is empty 7470 * Bin1 = Counter increments when cache occupancy is within [1 to 16] 7471 * Bin2 = Counter increments when cache occupancy is within [17 to 32] 7472 * Bin3 = Counter increments when cache occupancy is within [33 to 48] 7473 * Bin4 = Counter increments when cache occupancy is within [49 to 64] 7474 * Bin5 = Counter increments when cache occupancy is within [65 to 80] 7475 * Bin6 = Counter increments when cache occupancy is within [81 to 96] 7476 * Bin7 = Counter increments when cache occupancy is within [97 to 112] 7477 * Bin8 = Counter increments when cache occupancy is within [113 to 127] 7478 * Bin9 = Counter increments when cache occupancy is equal to 128 7479 * The above histogram bin definitions apply to both the peak-occupancy 7480 * histogram and the current-occupancy histogram. 7481 * 7482 * @fse_cache_occupancy_peak_cnt: 7483 * Array records periodically PEAK cache occupancy values. 7484 * Peak Occupancy will increment only if it is greater than current 7485 * occupancy value. 7486 * 7487 * @fse_cache_occupancy_curr_cnt: 7488 * Array records periodically current cache occupancy value. 7489 * Current Cache occupancy always holds instant snapshot of 7490 * current number of cache entries. 7491 **/ 7492 A_UINT32 fse_cache_occupancy_peak_cnt[HTT_RX_MAX_PEAK_OCCUPANCY_INDEX]; 7493 A_UINT32 fse_cache_occupancy_curr_cnt[HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX]; 7494 /** 7495 * Square stat is sum of squares of cache occupancy to better understand 7496 * any variation/deviation within each cache set, over a given time-window. 7497 * 7498 * Square stat is calculated this way: 7499 * Square = SUM(Squares of all Occupancy in a Set) / 8 7500 * The cache has 16-way set associativity, so the occupancy of a 7501 * set can vary from 0 to 16. There are 8 sets within the cache. 7502 * Therefore, the minimum possible square value is 0, and the maximum 7503 * possible square value is (8*16^2) / 8 = 256. 7504 * 7505 * 6 bins are used to keep track of square stats: 7506 * Bin0 = increments when square of current cache occupancy is zero 7507 * Bin1 = increments when square of current cache occupancy is within 7508 * [1 to 50] 7509 * Bin2 = increments when square of current cache occupancy is within 7510 * [51 to 100] 7511 * Bin3 = increments when square of current cache occupancy is within 7512 * [101 to 200] 7513 * Bin4 = increments when square of current cache occupancy is within 7514 * [201 to 255] 7515 * Bin5 = increments when square of current cache occupancy is 256 7516 */ 7517 A_UINT32 fse_search_stat_square_cnt[HTT_RX_SQUARE_INDEX]; 7518 /** 7519 * Search stats has 2 types of values: Peak Pending and Number of 7520 * Search Pending. 7521 * GSE command ring for FSE can hold maximum of 5 Pending searches 7522 * at any given time. 7523 * 7524 * 4 bins are used to keep track of search stats: 7525 * Bin0 = Counter increments when there are NO pending searches 7526 * (For peak, it will be number of pending searches greater 7527 * than GSE command ring FIFO outstanding requests. 7528 * For Search Pending, it will be number of pending search 7529 * inside GSE command ring FIFO.) 7530 * Bin1 = Counter increments when number of pending searches are within 7531 * [1 to 2] 7532 * Bin2 = Counter increments when number of pending searches are within 7533 * [3 to 4] 7534 * Bin3 = Counter increments when number of pending searches are 7535 * greater/equal to [ >= 5] 7536 */ 7537 A_UINT32 fse_search_stat_peak_cnt[HTT_RX_MAX_PEAK_SEARCH_INDEX]; 7538 A_UINT32 fse_search_stat_search_pending_cnt[HTT_RX_MAX_PENDING_SEARCH_INDEX]; 7539 } htt_stats_rx_fse_stats_tlv; 7540 /* preserve old name alias for new name consistent with the tag name */ 7541 typedef htt_stats_rx_fse_stats_tlv htt_rx_fse_stats_tlv; 7542 7543 /* NOTE: 7544 * This structure is for documentation, and cannot be safely used directly. 7545 * Instead, use the constituent TLV structures to fill/parse. 7546 */ 7547 typedef struct { 7548 htt_stats_rx_fse_stats_tlv rx_fse_stats; 7549 } htt_rx_fse_stats_t; 7550 7551 #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 7552 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 /* 20, 40, 80, 160, 320 */ 7553 7554 #define HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES 2/* 0: Half, 1: Quarter */ 7555 7556 typedef struct { 7557 htt_tlv_hdr_t tlv_hdr; 7558 /** SU TxBF TX MCS stats */ 7559 A_UINT32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7560 /** Implicit BF TX MCS stats */ 7561 A_UINT32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7562 /** Open loop TX MCS stats */ 7563 A_UINT32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7564 /** SU TxBF TX NSS stats */ 7565 A_UINT32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7566 /** Implicit BF TX NSS stats */ 7567 A_UINT32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7568 /** Open loop TX NSS stats */ 7569 A_UINT32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7570 /** SU TxBF TX BW stats */ 7571 A_UINT32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7572 /** Implicit BF TX BW stats */ 7573 A_UINT32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7574 /** Open loop TX BW stats */ 7575 A_UINT32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7576 /** Legacy and OFDM TX rate stats */ 7577 A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 7578 /** SU TxBF TX BW stats */ 7579 A_UINT32 reduced_tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7580 /** Implicit BF TX BW stats */ 7581 A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7582 /** Open loop TX BW stats */ 7583 A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 7584 /** Txbf flag reason stats */ 7585 A_UINT32 txbf_flag_set_mu_mode; 7586 A_UINT32 txbf_flag_set_final_status; 7587 A_UINT32 txbf_flag_not_set_verified_txbf_mode; 7588 A_UINT32 txbf_flag_not_set_disable_p2p_access; 7589 A_UINT32 txbf_flag_not_set_max_nss_reached_in_he160; 7590 A_UINT32 txbf_flag_not_set_disable_ul_dl_ofdma; 7591 A_UINT32 txbf_flag_not_set_mcs_threshold_value; 7592 A_UINT32 txbf_flag_not_set_final_status; 7593 } htt_stats_pdev_tx_rate_txbf_stats_tlv; 7594 /* preserve old name alias for new name consistent with the tag name */ 7595 typedef htt_stats_pdev_tx_rate_txbf_stats_tlv htt_tx_pdev_txbf_rate_stats_tlv; 7596 7597 typedef enum { 7598 HTT_STATS_RC_MODE_DLSU = 0, 7599 HTT_STATS_RC_MODE_DLMUMIMO = 1, 7600 HTT_STATS_RC_MODE_DLOFDMA = 2, 7601 HTT_STATS_RC_MODE_ULMUMIMO = 3, 7602 HTT_STATS_RC_MODE_ULOFDMA = 4, 7603 } htt_stats_rc_mode; 7604 7605 typedef struct { 7606 A_UINT32 ppdus_tried; 7607 A_UINT32 ppdus_ack_failed; 7608 A_UINT32 mpdus_tried; 7609 A_UINT32 mpdus_failed; 7610 } htt_tx_rate_stats_t; 7611 7612 typedef enum { 7613 HTT_RC_MODE_SU_OL, 7614 HTT_RC_MODE_SU_BF, 7615 HTT_RC_MODE_MU1_INTF, 7616 HTT_RC_MODE_MU2_INTF, 7617 HTT_Rc_MODE_MU3_INTF, 7618 HTT_RC_MODE_MU4_INTF, 7619 HTT_RC_MODE_MU5_INTF, 7620 HTT_RC_MODE_MU6_INTF, 7621 HTT_RC_MODE_MU7_INTF, 7622 HTT_RC_MODE_2D_COUNT, 7623 } HTT_RC_MODE; 7624 7625 typedef enum { 7626 HTT_STATS_RU_TYPE_INVALID = 0, 7627 HTT_STATS_RU_TYPE_SINGLE_RU_ONLY = 1, 7628 HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2, 7629 } htt_stats_ru_type; 7630 7631 typedef struct { 7632 htt_tlv_hdr_t tlv_hdr; 7633 7634 /** HTT_STATS_RC_MODE_XX */ 7635 A_UINT32 rc_mode; 7636 7637 A_UINT32 last_probed_mcs; 7638 7639 A_UINT32 last_probed_nss; 7640 7641 A_UINT32 last_probed_bw; 7642 7643 htt_tx_rate_stats_t per_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 7644 7645 htt_tx_rate_stats_t per_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7646 7647 htt_tx_rate_stats_t per_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 7648 7649 /** 320MHz extension for PER */ 7650 htt_tx_rate_stats_t per_bw320; 7651 7652 A_UINT32 probe_cnt_per_rcmode[HTT_RC_MODE_2D_COUNT]; 7653 7654 A_UINT32 ru_type; /* refer to htt_stats_ru_type enum */ 7655 htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; 7656 } htt_stats_per_rate_stats_tlv; 7657 /* preserve old name alias for new name consistent with the tag name */ 7658 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv; 7659 7660 /* NOTE: 7661 * This structure is for documentation, and cannot be safely used directly. 7662 * Instead, use the constituent TLV structures to fill/parse. 7663 */ 7664 typedef struct { 7665 htt_stats_pdev_tx_rate_txbf_stats_tlv txbf_rate_stats; 7666 } htt_pdev_txbf_rate_stats_t; 7667 7668 typedef struct { 7669 htt_stats_per_rate_stats_tlv per_stats; 7670 } htt_tx_pdev_per_stats_t; 7671 7672 typedef enum { 7673 HTT_ULTRIG_QBOOST_TRIGGER = 0, 7674 HTT_ULTRIG_PSPOLL_TRIGGER, 7675 HTT_ULTRIG_UAPSD_TRIGGER, 7676 HTT_ULTRIG_11AX_TRIGGER, 7677 HTT_ULTRIG_11AX_WILDCARD_TRIGGER, 7678 HTT_ULTRIG_11AX_UNASSOC_WILDCARD_TRIGGER, 7679 HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, 7680 } HTT_STA_UL_OFDMA_RX_TRIG_TYPE; 7681 7682 typedef enum { 7683 HTT_11AX_TRIGGER_BASIC_E = 0, 7684 HTT_11AX_TRIGGER_BRPOLL_E = 1, 7685 HTT_11AX_TRIGGER_MU_BAR_E = 2, 7686 HTT_11AX_TRIGGER_MU_RTS_E = 3, 7687 HTT_11AX_TRIGGER_BUFFER_SIZE_E = 4, 7688 HTT_11AX_TRIGGER_GCR_MU_BAR_E = 5, 7689 HTT_11AX_TRIGGER_BQRP_E = 6, 7690 HTT_11AX_TRIGGER_NDP_FB_REPORT_POLL_E = 7, 7691 HTT_11AX_TRIGGER_RESERVED_8_E = 8, 7692 HTT_11AX_TRIGGER_RESERVED_9_E = 9, 7693 HTT_11AX_TRIGGER_RESERVED_10_E = 10, 7694 HTT_11AX_TRIGGER_RESERVED_11_E = 11, 7695 HTT_11AX_TRIGGER_RESERVED_12_E = 12, 7696 HTT_11AX_TRIGGER_RESERVED_13_E = 13, 7697 HTT_11AX_TRIGGER_RESERVED_14_E = 14, 7698 HTT_11AX_TRIGGER_RESERVED_15_E = 15, 7699 HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE, 7700 } HTT_STA_UL_OFDMA_11AX_TRIG_TYPE; 7701 7702 /* UL RESP Queues 0 - HIPRI, 1 - LOPRI & 2 - BSR */ 7703 #define HTT_STA_UL_OFDMA_NUM_UL_QUEUES 3 7704 /* Actual resp type sent by STA for trigger 7705 * 0 - HE TB PPDU, 1 - NULL Delimiter */ 7706 #define HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE 2 7707 /* Counter for MCS 0-13 */ 7708 #define HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS 14 7709 /* Counters BW 20,40,80,160,320 */ 7710 #define HTT_STA_UL_OFDMA_NUM_BW_COUNTERS 5 7711 #define HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ 7712 7713 /* STATS_TYPE : HTT_DBG_EXT_STA_11AX_UL_STATS 7714 * TLV_TAGS: 7715 * - HTT_STATS_STA_UL_OFDMA_STATS_TAG 7716 */ 7717 typedef struct { 7718 htt_tlv_hdr_t tlv_hdr; 7719 7720 A_UINT32 pdev_id; 7721 7722 /** 7723 * Trigger Type reported by HWSCH on RX reception 7724 * Each index populate enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE 7725 */ 7726 A_UINT32 rx_trigger_type[HTT_STA_UL_OFDMA_NUM_TRIG_TYPE]; 7727 /** 7728 * 11AX Trigger Type on RX reception 7729 * Each index populate enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE 7730 */ 7731 A_UINT32 ax_trigger_type[HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE]; 7732 7733 /** Num data PPDUs/Delims responded to trigs. per HWQ for UL RESP */ 7734 A_UINT32 num_data_ppdu_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; 7735 A_UINT32 num_null_delimiters_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; 7736 /** 7737 * Overall UL STA RESP Status 0 - HE TB PPDU, 1 - NULL Delimiter 7738 * Super set of num_data_ppdu_responded_per_hwq, 7739 * num_null_delimiters_responded_per_hwq 7740 */ 7741 A_UINT32 num_total_trig_responses[HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE]; 7742 7743 /** 7744 * Time interval between current time ms and last successful trigger RX 7745 * 0xFFFFFFFF denotes no trig received / timestamp roll back 7746 */ 7747 A_UINT32 last_trig_rx_time_delta_ms; 7748 7749 /** 7750 * Rate Statistics for UL OFDMA 7751 * UL TB PPDU TX MCS, NSS, GI, BW from STA HWQ 7752 */ 7753 A_UINT32 ul_ofdma_tx_mcs[HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; 7754 A_UINT32 ul_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 7755 A_UINT32 ul_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; 7756 A_UINT32 ul_ofdma_tx_ldpc; 7757 A_UINT32 ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; 7758 7759 /** Trig based PPDU TX/ RBO based PPDU TX Count */ 7760 A_UINT32 trig_based_ppdu_tx; 7761 A_UINT32 rbo_based_ppdu_tx; 7762 /** Switch MU EDCA to SU EDCA Count */ 7763 A_UINT32 mu_edca_to_su_edca_switch_count; 7764 /** Num MU EDCA applied Count */ 7765 A_UINT32 num_mu_edca_param_apply_count; 7766 7767 /** 7768 * Current MU EDCA Parameters for WMM ACs 7769 * Mode - 0 - SU EDCA, 1- MU EDCA 7770 */ 7771 A_UINT32 current_edca_hwq_mode[HTT_NUM_AC_WMM]; 7772 /** Contention Window minimum. Range: 1 - 10 */ 7773 A_UINT32 current_cw_min[HTT_NUM_AC_WMM]; 7774 /** Contention Window maximum. Range: 1 - 10 */ 7775 A_UINT32 current_cw_max[HTT_NUM_AC_WMM]; 7776 /** AIFS value - 0 -255 */ 7777 A_UINT32 current_aifs[HTT_NUM_AC_WMM]; 7778 A_UINT32 reduced_ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES][HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; 7779 } htt_stats_sta_ul_ofdma_stats_tlv; 7780 /* preserve old name alias for new name consistent with the tag name */ 7781 typedef htt_stats_sta_ul_ofdma_stats_tlv htt_sta_ul_ofdma_stats_tlv; 7782 7783 /* NOTE: 7784 * This structure is for documentation, and cannot be safely used directly. 7785 * Instead, use the constituent TLV structures to fill/parse. 7786 */ 7787 typedef struct { 7788 htt_stats_sta_ul_ofdma_stats_tlv ul_ofdma_sta_stats; 7789 } htt_sta_11ax_ul_stats_t; 7790 7791 typedef struct { 7792 htt_tlv_hdr_t tlv_hdr; 7793 /** No of Fine Timing Measurement frames transmitted successfully */ 7794 A_UINT32 tx_ftm_suc; 7795 /** 7796 * No of Fine Timing Measurement frames transmitted successfully 7797 * after retry 7798 */ 7799 A_UINT32 tx_ftm_suc_retry; 7800 /** No of Fine Timing Measurement frames not transmitted successfully */ 7801 A_UINT32 tx_ftm_fail; 7802 /** 7803 * No of Fine Timing Measurement Request frames received, 7804 * including initial, non-initial, and duplicates 7805 */ 7806 A_UINT32 rx_ftmr_cnt; 7807 /** 7808 * No of duplicate Fine Timing Measurement Request frames received, 7809 * including both initial and non-initial 7810 */ 7811 A_UINT32 rx_ftmr_dup_cnt; 7812 /** No of initial Fine Timing Measurement Request frames received */ 7813 A_UINT32 rx_iftmr_cnt; 7814 /** 7815 * No of duplicate initial Fine Timing Measurement Request frames received 7816 */ 7817 A_UINT32 rx_iftmr_dup_cnt; 7818 /** No of responder sessions rejected when initiator was active */ 7819 A_UINT32 initiator_active_responder_rejected_cnt; 7820 /** Responder terminate count */ 7821 A_UINT32 responder_terminate_cnt; 7822 A_UINT32 vdev_id; 7823 } htt_stats_vdev_rtt_resp_stats_tlv; 7824 /* preserve old name alias for new name consistent with the tag name */ 7825 typedef htt_stats_vdev_rtt_resp_stats_tlv htt_vdev_rtt_resp_stats_tlv; 7826 7827 typedef struct { 7828 htt_stats_vdev_rtt_resp_stats_tlv vdev_rtt_resp_stats; 7829 } htt_vdev_rtt_resp_stats_t; 7830 7831 typedef struct { 7832 htt_tlv_hdr_t tlv_hdr; 7833 7834 A_UINT32 vdev_id; 7835 /** 7836 * No of Fine Timing Measurement request frames transmitted successfully 7837 */ 7838 A_UINT32 tx_ftmr_cnt; 7839 /** 7840 * No of Fine Timing Measurement request frames not transmitted successfully 7841 */ 7842 A_UINT32 tx_ftmr_fail; 7843 /** 7844 * No of Fine Timing Measurement request frames transmitted successfully 7845 * after retry 7846 */ 7847 A_UINT32 tx_ftmr_suc_retry; 7848 /** 7849 * No of Fine Timing Measurement frames received, including initial, 7850 * non-initial, and duplicates 7851 */ 7852 A_UINT32 rx_ftm_cnt; 7853 /** Initiator Terminate count */ 7854 A_UINT32 initiator_terminate_cnt; 7855 /** Debug count to check the Measurement request from host */ 7856 A_UINT32 tx_meas_req_count; 7857 } htt_stats_vdev_rtt_init_stats_tlv; 7858 /* preserve old name alias for new name consistent with the tag name */ 7859 typedef htt_stats_vdev_rtt_init_stats_tlv htt_vdev_rtt_init_stats_tlv; 7860 7861 typedef struct { 7862 htt_stats_vdev_rtt_init_stats_tlv vdev_rtt_init_stats; 7863 } htt_vdev_rtt_init_stats_t; 7864 7865 7866 #define HTT_STATS_MAX_SCH_CMD_RESULT 25 7867 7868 /* TXSEND self generated frames */ 7869 typedef enum { 7870 HTT_TXSEND_FTYPE_SGEN_TF_POLL, 7871 HTT_TXSEND_FTYPE_SGEN_TF_SOUND, 7872 HTT_TXSEND_FTYPE_SGEN_TBR_NDPA, 7873 HTT_TXSEND_FTYPE_SGEN_TBR_NDP, 7874 HTT_TXSEND_FTYPE_SGEN_TBR_LMR, 7875 HTT_TXSEND_FTYPE_SGEN_TF_REPORT, 7876 7877 HTT_TXSEND_FTYPE_MAX 7878 } 7879 htt_stats_txsend_ftype_t; 7880 7881 typedef struct { 7882 htt_tlv_hdr_t tlv_hdr; 7883 /* 11AZ TBR SU Stats */ 7884 A_UINT32 tbr_su_ftype_queued[HTT_TXSEND_FTYPE_MAX]; 7885 /* 11AZ TBR MU Stats */ 7886 A_UINT32 tbr_mu_ftype_queued[HTT_TXSEND_FTYPE_MAX]; 7887 } htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv; 7888 7889 typedef struct { 7890 htt_tlv_hdr_t tlv_hdr; 7891 /** tbr_num_sch_cmd_result_buckets: 7892 * Number of sch cmd results buckets in use per chip 7893 * Each bucket contains the counter of the number of times that bucket 7894 * index was seen in the sch_cmd_result. The last bucket will capture 7895 * the count of sch_cmd_result matching the last bucket index and the 7896 * count of all the sch_cmd_results that exceeded the last bucket index 7897 * value. 7898 * tbr_num_sch_cmd_result_buckets must be <= HTT_STATS_MAX_SCH_CMD_RESULT 7899 */ 7900 A_UINT32 tbr_num_sch_cmd_result_buckets; 7901 /* cmd result status for SU frames in case of TB ranging */ 7902 A_UINT32 opaque_tbr_su_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; 7903 /* cmd result status for MU frames in case of TB ranging */ 7904 A_UINT32 opaque_tbr_mu_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; 7905 } htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv; 7906 7907 typedef struct { 7908 htt_tlv_hdr_t tlv_hdr; 7909 /** ista_ranging_ndpa_cnt: 7910 * Indicates the number of Ranging NDPA sent successfully. 7911 */ 7912 A_UINT32 ista_ranging_ndpa_cnt; 7913 /** ista_ranging_ndp_cnt: 7914 * Indicates the number of Ranging NDP sent successfully. 7915 */ 7916 A_UINT32 ista_ranging_ndp_cnt; 7917 /** ista_ranging_i2r_lmr_cnt: 7918 * Indicates the number of Ranging I2R LMR sent successfully. 7919 */ 7920 A_UINT32 ista_ranging_i2r_lmr_cnt; 7921 /** rtsa_ranging_resp_cnt 7922 * Indicates the number of times RXPCU initiates a Ranging response 7923 * as a RSTA. 7924 */ 7925 A_UINT32 rtsa_ranging_resp_cnt; 7926 /** rtsa_ranging_ndp_cnt: 7927 * Indicates the number of Ranging NDP response sent successfully. 7928 */ 7929 A_UINT32 rtsa_ranging_ndp_cnt; 7930 /** rsta_ranging_lmr_cnt: 7931 * Indicates the number of Ranging R2I LMR response sent successfully. 7932 */ 7933 A_UINT32 rsta_ranging_lmr_cnt; 7934 /** tb_ranging_cts2s_rcvd_cnt: 7935 * Indicates the number of expected CTS2S response received for TF Poll 7936 * sent. 7937 */ 7938 A_UINT32 tb_ranging_cts2s_rcvd_cnt; 7939 /** tb_ranging_ndp_rcvd_cnt: 7940 * Indicates the number of expected NDP response received for TF Sound 7941 * or Secure Sound sent. 7942 */ 7943 A_UINT32 tb_ranging_ndp_rcvd_cnt; 7944 /** tb_ranging_lmr_rcvd_cnt: 7945 * Indicates the number of expected LMR response received for TF Report 7946 * sent. 7947 */ 7948 A_UINT32 tb_ranging_lmr_rcvd_cnt; 7949 /** tb_ranging_tf_poll_resp_sent_cnt: 7950 * Indicates the number of successful responses sent for TF Poll 7951 * received. 7952 */ 7953 A_UINT32 tb_ranging_tf_poll_resp_sent_cnt; 7954 /** tb_ranging_tf_sound_resp_sent_cnt: 7955 * Indicates the number of successful responses sent for TF Sound 7956 * (or Secure) received. 7957 */ 7958 A_UINT32 tb_ranging_tf_sound_resp_sent_cnt; 7959 /** tb_ranging_tf_report_resp_sent_cnt: 7960 * Indicates the number of successful responses sent for TF Report 7961 * received. 7962 */ 7963 A_UINT32 tb_ranging_tf_report_resp_sent_cnt; 7964 } htt_stats_pdev_rtt_hw_stats_tlv; 7965 7966 typedef struct { 7967 htt_tlv_hdr_t tlv_hdr; 7968 A_UINT32 pdev_id; 7969 /** tx_11mc_ftm_suc: 7970 * Number of 11mc Fine Timing Measurement frames transmitted successfully. 7971 */ 7972 A_UINT32 tx_11mc_ftm_suc; 7973 /** tx_11mc_ftm_suc_retry: 7974 * Number of Fine Timing Measurement frames transmitted successfully 7975 * after retrying. 7976 */ 7977 A_UINT32 tx_11mc_ftm_suc_retry; 7978 /** tx_11mc_ftm_fail: 7979 * Number of Fine Timing Measurement frames not transmitted successfully. 7980 */ 7981 A_UINT32 tx_11mc_ftm_fail; 7982 /** rx_11mc_ftmr_cnt: 7983 * Number of FTMR frames received, including initial, non-initial, 7984 * and duplicates. 7985 */ 7986 A_UINT32 rx_11mc_ftmr_cnt; 7987 /** rx_11mc_ftmr_dup_cnt: 7988 * Number of duplicate Fine Timing Measurement Request frames received, 7989 * including both initial and non-initial. 7990 */ 7991 A_UINT32 rx_11mc_ftmr_dup_cnt; 7992 /** rx_11mc_iftmr_cnt: 7993 * Number of initial Fine Timing Measurement Request frames received. 7994 */ 7995 A_UINT32 rx_11mc_iftmr_cnt; 7996 /** rx_11mc_iftmr_dup_cnt: 7997 * Number of duplicate initial Fine Timing Measurement Request frames 7998 * received. 7999 */ 8000 A_UINT32 rx_11mc_iftmr_dup_cnt; 8001 /** ftmr_drop_11mc_resp_role_not_enabled_cnt: 8002 * Number of FTMR frames dropped as 11mc is not supported for this VAP. 8003 */ 8004 A_UINT32 ftmr_drop_11mc_resp_role_not_enabled_cnt; 8005 /** initiator_active_responder_rejected_cnt: 8006 * Number of responder sessions rejected when initiator was active. 8007 */ 8008 A_UINT32 initiator_active_responder_rejected_cnt; 8009 /** responder_terminate_cnt: 8010 * Number of times Responder session got terminated. 8011 */ 8012 A_UINT32 responder_terminate_cnt; 8013 /** active_rsta_open: 8014 * Number of active responder contexts in open mode. 8015 */ 8016 A_UINT32 active_rsta_open; 8017 /** active_rsta_mac: 8018 * Number of active responder contexts in mac security mode. 8019 */ 8020 A_UINT32 active_rsta_mac; 8021 /** active_rsta_mac_phy: 8022 * Number of active responder contexts in mac_phy security mode. 8023 */ 8024 A_UINT32 active_rsta_mac_phy; 8025 /** num_assoc_ranging_peers: 8026 * Number of active associated ISTA ranging peers. 8027 */ 8028 A_UINT32 num_assoc_ranging_peers; 8029 /** num_unassoc_ranging_peers: 8030 * Number of active un-associated ISTA ranging peers. 8031 */ 8032 A_UINT32 num_unassoc_ranging_peers; 8033 /** responder_alloc_cnt: 8034 * Number of responder contexts allocated. 8035 */ 8036 A_UINT32 responder_alloc_cnt; 8037 /** responder_alloc_failure: 8038 * Number of times responder context failed to be allocated. 8039 */ 8040 A_UINT32 responder_alloc_failure; 8041 /** pn_check_failure_cnt: 8042 * Number of times PN check failed. 8043 */ 8044 A_UINT32 pn_check_failure_cnt; 8045 /** pasn_m1_auth_recv_cnt: 8046 * Num of M1 auth frames received for PASN over the air from iSTA. 8047 */ 8048 A_UINT32 pasn_m1_auth_recv_cnt; 8049 /** pasn_m1_auth_drop_cnt: 8050 * Number of M1 auth frames received for PASN over the air from iSTA 8051 * but dropped in FW due to any reason (such as unavailability of 8052 * responder ctxt or any other check). 8053 */ 8054 A_UINT32 pasn_m1_auth_drop_cnt; 8055 /** pasn_m2_auth_recv_cnt: 8056 * Number of M2 auth frames received in FW for PASN from Host driver. 8057 */ 8058 A_UINT32 pasn_m2_auth_recv_cnt; 8059 /** pasn_m2_auth_tx_fail_cnt: 8060 * Number of M2 auth frames received in FW but Tx failed. 8061 */ 8062 A_UINT32 pasn_m2_auth_tx_fail_cnt; 8063 /** pasn_m3_auth_recv_cnt: 8064 * Number of M3 auth frames received for PASN. 8065 */ 8066 A_UINT32 pasn_m3_auth_recv_cnt; 8067 /** pasn_m3_auth_drop_cnt: 8068 * Number of M3 auth frames received for PASN over the air from iSTA but 8069 * dropped in FW due to any reason. 8070 */ 8071 A_UINT32 pasn_m3_auth_drop_cnt; 8072 /** pasn_peer_create_request_cnt: 8073 * Number of times FW requested PASN peer create request to Host. 8074 */ 8075 A_UINT32 pasn_peer_create_request_cnt; 8076 /** pasn_peer_create_timeout_cnt: 8077 * Number of times PASN peer was not created within timeout period. 8078 */ 8079 A_UINT32 pasn_peer_create_timeout_cnt; 8080 /** pasn_peer_created_cnt: 8081 * Number of times Host sent PASN peer create request to FW. 8082 */ 8083 A_UINT32 pasn_peer_created_cnt; 8084 /** sec_ranging_not_supported_mfp_not_setup: 8085 * management frame protection not setup, drop secure ranging request. 8086 */ 8087 A_UINT32 sec_ranging_not_supported_mfp_not_setup; 8088 /** non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set: 8089 * Non secured ranging request discarded for Assoc peer with MFPR set. 8090 */ 8091 A_UINT32 non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set; 8092 /** open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer: 8093 * Failure in case non-secured frame is received for PASN peer and 8094 * URNM_MFPR is set. 8095 */ 8096 A_UINT32 open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer; 8097 /** unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR: 8098 * Failure in case non-assoc/non-PASN sta is sending open FTMR and 8099 * RSTA does not support un-secured ranging. 8100 */ 8101 A_UINT32 unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR; 8102 /** num_req_bw_20_MHz: 8103 * Number of requests with BW 20 MHz. 8104 */ 8105 A_UINT32 num_req_bw_20_MHz; 8106 /** num_req_bw_40_MHz: 8107 * Number of requests with BW 40 MHz. 8108 */ 8109 A_UINT32 num_req_bw_40_MHz; 8110 /** num_req_bw_80_MHz: 8111 * Number of requests with BW 80 MHz. 8112 */ 8113 A_UINT32 num_req_bw_80_MHz; 8114 /** num_req_bw_160_MHz: 8115 * Number of requests with BW 160 MHz. 8116 */ 8117 A_UINT32 num_req_bw_160_MHz; 8118 /** tx_11az_ftm_successful: 8119 * Number of 11AZ FTM frames transmitted successfully. 8120 */ 8121 A_UINT32 tx_11az_ftm_successful; 8122 /** tx_11az_ftm_failed: 8123 * Number of 11AZ FTM frames for which Tx failed. 8124 */ 8125 A_UINT32 tx_11az_ftm_failed; 8126 /** rx_11az_ftmr_cnt: 8127 * Number of 11AZ FTM frames received. 8128 */ 8129 A_UINT32 rx_11az_ftmr_cnt; 8130 /** rx_11az_ftmr_dup_cnt: 8131 * Number of duplicate 11az ftmr frames dropped. 8132 */ 8133 A_UINT32 rx_11az_ftmr_dup_cnt; 8134 /** rx_11az_iftmr_dup_cnt: 8135 * Number of duplicate 11az iftmr frames dropped. 8136 */ 8137 A_UINT32 rx_11az_iftmr_dup_cnt; 8138 /** malformed_ftmr: 8139 * Number of malformed FTMR frames received from client leading to 8140 * frame parse error. 8141 */ 8142 A_UINT32 malformed_ftmr; 8143 /** ftmr_drop_ntb_resp_role_not_enabled_cnt: 8144 * Number of FTMR frames dropped as NTB is not supported for this VAP. 8145 */ 8146 A_UINT32 ftmr_drop_ntb_resp_role_not_enabled_cnt; 8147 /** ftmr_drop_tb_resp_role_not_enabled_cnt: 8148 * Number of FTMR frames dropped as TB is not supported for this VAP. 8149 */ 8150 A_UINT32 ftmr_drop_tb_resp_role_not_enabled_cnt; 8151 /** invalid_ftm_request_params: 8152 * Number of FTMR frames received with invalid params. 8153 */ 8154 A_UINT32 invalid_ftm_request_params; 8155 /** requested_bw_format_not_supported: 8156 * FTMR rejected as requested format is lower or higher than AP's 8157 * capability, or unknown. 8158 */ 8159 A_UINT32 requested_bw_format_not_supported; 8160 /** ntb_unsec_unassoc_mode_ranging_peer_alloc_failed: 8161 * AST entry creation failed for NTB unsecured mode. 8162 */ 8163 A_UINT32 ntb_unsec_unassoc_mode_ranging_peer_alloc_failed; 8164 /** tb_unassoc_unsec_mode_pasn_peer_creation_failed: 8165 * PASN peer creation failed for unsecured mode TBR. 8166 */ 8167 A_UINT32 tb_unassoc_unsec_mode_pasn_peer_creation_failed; 8168 /** num_ranging_sequences_processed: 8169 * Number of ranging sequences processed for NTB and TB. 8170 */ 8171 A_UINT32 num_ranging_sequences_processed; 8172 /** Number of NDPs transmitted for NTBR */ 8173 A_UINT32 ntb_tx_ndp; 8174 A_UINT32 ndp_rx_cnt; 8175 /** Number of NDPAs received for 11AZ NTB ranging */ 8176 A_UINT32 num_ntb_ranging_NDPAs_recv; 8177 /** Number of LMR frames received */ 8178 A_UINT32 recv_lmr; 8179 /** invalid_ftmr_cnt: 8180 * Number of invalid FTMR frames received 8181 * iftmr with null ie element is invalid 8182 * The Frame is valid if any of the following combination is present: 8183 * a. LCI sub ie + parameter ie 8184 * b. LCR sub ie + parameter ie 8185 * c. parameter ie 8186 * d. LCI sub ie + LCR sub ie + parameter ie 8187 */ 8188 A_UINT32 invalid_ftmr_cnt; 8189 /** Number of times the 'max time b/w measurement' timer got expired */ 8190 A_UINT32 max_time_bw_meas_exp_cnt; 8191 } htt_stats_pdev_rtt_resp_stats_tlv; 8192 8193 /* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_RESP_STATS 8194 * TLV_TAGS: 8195 * HTT_STATS_PDEV_RTT_RESP_STATS_TAG 8196 * HTT_STATS_PDEV_RTT_HW_STATS_TAG 8197 * HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG 8198 * HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG 8199 */ 8200 typedef struct { 8201 htt_stats_pdev_rtt_resp_stats_tlv pdev_rtt_resp_stats; 8202 htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; 8203 htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv pdev_rtt_tbr_selfgen_queued_stats; 8204 htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv pdev_rtt_tbr_cmd_result_stats; 8205 } htt_pdev_rtt_resp_stats_t; 8206 8207 typedef struct { 8208 htt_tlv_hdr_t tlv_hdr; 8209 A_UINT32 pdev_id; 8210 /** tx_11mc_ftmr_cnt: 8211 * Number of 11mc Fine Timing Measurement request frames transmitted 8212 * successfully. 8213 */ 8214 A_UINT32 tx_11mc_ftmr_cnt; 8215 /** tx_11mc_ftmr_fail: 8216 * Number of 11mc Fine Timing Measurement request frames not transmitted 8217 * successfully. 8218 */ 8219 A_UINT32 tx_11mc_ftmr_fail; 8220 /** tx_11mc_ftmr_suc_retry: 8221 * Number of 11mc Fine Timing Measurement request frames transmitted 8222 * successfully after retrying. 8223 */ 8224 A_UINT32 tx_11mc_ftmr_suc_retry; 8225 /** rx_11mc_ftm_cnt: 8226 * Number of 11mc Fine Timing Measurement frames received, including 8227 * initial, non-initial, and duplicates. 8228 */ 8229 A_UINT32 rx_11mc_ftm_cnt; 8230 /** Count of Ranging Measurement requests received from host */ 8231 A_UINT32 tx_meas_req_count; 8232 /** Initiator role not supported on the vdev */ 8233 A_UINT32 init_role_not_enabled; 8234 /** Number of times Initiator context got terminated */ 8235 A_UINT32 initiator_terminate_cnt; 8236 /** Number of times Tx of FTMR failed */ 8237 A_UINT32 tx_11az_ftmr_fail; 8238 /** tx_11az_ftmr_start: 8239 * Number of Fine Timing Measurement start requests transmitted 8240 * successfully. 8241 */ 8242 A_UINT32 tx_11az_ftmr_start; 8243 /** tx_11az_ftmr_stop: 8244 * Number of Fine Timing Measurement stop requests transmitted 8245 * successfully. 8246 */ 8247 A_UINT32 tx_11az_ftmr_stop; 8248 /** Number of FTM frames received successfully */ 8249 A_UINT32 rx_11az_ftm_cnt; 8250 /** Number of active ISTA sessions */ 8251 A_UINT32 active_ista; 8252 /** HE preamble not enabled on Initiator side */ 8253 A_UINT32 invalid_preamble; 8254 /** Initiator invalid channel bw format */ 8255 A_UINT32 invalid_chan_bw_format; 8256 /* mgmt_buff_alloc_fail_cnt Management Buffer allocation failure count */ 8257 A_UINT32 mgmt_buff_alloc_fail_cnt; 8258 /** ftm_parse_failure: 8259 * Count of FTM frame IE parse failure or RSTA sending measurement 8260 * negotiation failure. 8261 */ 8262 A_UINT32 ftm_parse_failure; 8263 /** Count of NTB/TB ranging negotiation completed successfully */ 8264 A_UINT32 ranging_negotiation_successful_cnt; 8265 /** incompatible_ftm_params: 8266 * Number of occurrences of failure due to incompatible parameters 8267 * suggested by rSTA during negotiation. 8268 */ 8269 A_UINT32 incompatible_ftm_params; 8270 /** sec_ranging_req_in_open_mode: 8271 * Number of occurrences of failure if BSS peer exists in open mode and 8272 * secured mode RTT ranging is requested. 8273 */ 8274 A_UINT32 sec_ranging_req_in_open_mode; 8275 /** ftmr_tx_failed_null_11az_peer: 8276 * Number of occurrences where FTMR was not transmitted as there was 8277 * no 11AZ peer. 8278 */ 8279 A_UINT32 ftmr_tx_failed_null_11az_peer; 8280 /** Number of times ftmr retry timed out */ 8281 A_UINT32 ftmr_retry_timeout; 8282 /** Number of times the 'max time b/w measurement' timer got expired */ 8283 A_UINT32 max_time_bw_meas_exp_cnt; 8284 /** tb_meas_duration_expiry_cnt: 8285 * Number of times TBR measurement duration expired. 8286 */ 8287 A_UINT32 tb_meas_duration_expiry_cnt; 8288 /** num_tb_ranging_requests: 8289 * Number of TB ranging requests ready for negotiation. 8290 */ 8291 A_UINT32 num_tb_ranging_requests; 8292 /** Number of times NTB ranging was triggered successfully */ 8293 A_UINT32 ntbr_triggered_successfully; 8294 /** Number of times NTB ranging failed to be triggered */ 8295 A_UINT32 ntbr_trigger_failed; 8296 /** No valid index found for programming vreg settings */ 8297 A_UINT32 invalid_or_no_vreg_idx; 8298 /** Number of times VREG setting failed */ 8299 A_UINT32 set_vreg_params_failed; 8300 /** Number of occurrences of SAC mismatch */ 8301 A_UINT32 sac_mismatch; 8302 /** pasn_m1_auth_recv_cnt: 8303 * Number of M1 auth frames received for PASN from Host. 8304 */ 8305 A_UINT32 pasn_m1_auth_recv_cnt; 8306 /** pasn_m1_auth_tx_fail_cnt: 8307 * Number of M1 auth frames received in FW but Tx failed. 8308 */ 8309 A_UINT32 pasn_m1_auth_tx_fail_cnt; 8310 /** pasn_m2_auth_recv_cnt: 8311 * Number of M2 auth frames received in FW for PASN over the air from rSTA. 8312 */ 8313 A_UINT32 pasn_m2_auth_recv_cnt; 8314 /** pasn_m2_auth_drop_cnt: 8315 * Number of M2 auth frames received in FW but dropped due to any reason. 8316 */ 8317 A_UINT32 pasn_m2_auth_drop_cnt; 8318 /** pasn_m3_auth_recv_cnt: 8319 * Number of M3 auth frames received for PASN from Host. 8320 */ 8321 A_UINT32 pasn_m3_auth_recv_cnt; 8322 /** pasn_m3_auth_tx_fail_cnt: 8323 * Number of M3 auth frames received in FW but Tx failed. 8324 */ 8325 A_UINT32 pasn_m3_auth_tx_fail_cnt; 8326 /** pasn_peer_create_request_cnt: 8327 * Number of times FW requested PASN peer create request to Host. 8328 */ 8329 A_UINT32 pasn_peer_create_request_cnt; 8330 /** pasn_peer_create_timeout_cnt: 8331 * Number of times PASN peer was not created within timeout period. 8332 */ 8333 A_UINT32 pasn_peer_create_timeout_cnt; 8334 /** pasn_peer_created_cnt: 8335 * Number of times Host sent PASN peer create request to FW. 8336 */ 8337 A_UINT32 pasn_peer_created_cnt; 8338 /** Number of occurrences of Tx of NDPA failing */ 8339 A_UINT32 ntbr_ndpa_failed; 8340 /** ntbr_sequence_successful: 8341 * The NDPA, NDP and LMR exchanges are successful and sched cmd status 8342 * is 0. 8343 */ 8344 A_UINT32 ntbr_sequence_successful; 8345 /** ntbr_ndp_failed: 8346 * Number of occurrences of NDPA being transmitted successfully 8347 * but NDP failing for NTB ranging. 8348 */ 8349 A_UINT32 ntbr_ndp_failed; 8350 /** sch_cmd_status_cnts: 8351 * Elements 0-7 count the number of times the sch_cmd_status was equal to 8352 * the corresponding value of the index of the array sch_cmd_status_cnts[], 8353 * and element 8 counts the numbers of times the status was some other 8354 * value >=8. 8355 */ 8356 A_UINT32 sch_cmd_status_cnts[9]; 8357 /** Number of times LMR reception timed out */ 8358 A_UINT32 lmr_timeout; 8359 /** Number of LMR frames received */ 8360 A_UINT32 lmr_recv; 8361 /** Number of trigger frames received */ 8362 A_UINT32 num_trigger_frames_received; 8363 /** Number of NDPAs received for TBR */ 8364 A_UINT32 num_tb_ranging_NDPAs_recv; 8365 /** Number of ranging NDPs received for NTBR/TB */ 8366 A_UINT32 ndp_rx_cnt; 8367 } htt_stats_pdev_rtt_init_stats_tlv; 8368 8369 /* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS 8370 * TLV_TAGS: 8371 * HTT_STATS_PDEV_RTT_INIT_STATS_TAG 8372 * HTT_STATS_PDEV_RTT_HW_STATS_TAG 8373 */ 8374 typedef struct { 8375 htt_stats_pdev_rtt_init_stats_tlv pdev_rtt_init_stats; 8376 htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; 8377 } htt_pdev_rtt_init_stats_t; 8378 8379 8380 /* STATS_TYPE : HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS 8381 * TLV_TAGS: 8382 * - HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG 8383 */ 8384 /* NOTE: 8385 * This structure is for documentation, and cannot be safely used directly. 8386 * Instead, use the constituent TLV structures to fill/parse. 8387 */ 8388 typedef struct { 8389 htt_tlv_hdr_t tlv_hdr; 8390 8391 /** No of pktlog payloads that were dropped in htt_ppdu_stats path */ 8392 A_UINT32 pktlog_lite_drop_cnt; 8393 /** No of pktlog payloads that were dropped in TQM path */ 8394 A_UINT32 pktlog_tqm_drop_cnt; 8395 /** No of pktlog ppdu stats payloads that were dropped */ 8396 A_UINT32 pktlog_ppdu_stats_drop_cnt; 8397 /** No of pktlog ppdu ctrl payloads that were dropped */ 8398 A_UINT32 pktlog_ppdu_ctrl_drop_cnt; 8399 /** No of pktlog sw events payloads that were dropped */ 8400 A_UINT32 pktlog_sw_events_drop_cnt; 8401 } htt_stats_pktlog_and_htt_ring_stats_tlv; 8402 /* preserve old name alias for new name consistent with the tag name */ 8403 typedef htt_stats_pktlog_and_htt_ring_stats_tlv 8404 htt_pktlog_and_htt_ring_stats_tlv; 8405 8406 #define HTT_DLPAGER_STATS_MAX_HIST 10 8407 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF 8408 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0 8409 #define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M 0x0000FF00 8410 #define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S 8 8411 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_M 0x0000FFFF 8412 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_S 0 8413 #define HTT_DLPAGER_TOTAL_FREE_PAGES_M 0xFFFF0000 8414 #define HTT_DLPAGER_TOTAL_FREE_PAGES_S 16 8415 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M 0x0000FFFF 8416 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S 0 8417 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M 0xFFFF0000 8418 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S 16 8419 8420 #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) \ 8421 (((_var) & HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M) >> \ 8422 HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S) 8423 8424 #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ 8425 do { \ 8426 HTT_CHECK_SET_VAL(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT, _val); \ 8427 ((_var) &= ~(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M));\ 8428 ((_var) |= ((_val) << HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S)); \ 8429 } while (0) 8430 8431 #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) \ 8432 (((_var) & HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M) >> \ 8433 HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S) 8434 8435 #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ 8436 do { \ 8437 HTT_CHECK_SET_VAL(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT, _val); \ 8438 ((_var) &= ~(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M));\ 8439 ((_var) |= ((_val) << HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S)); \ 8440 } while (0) 8441 8442 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) \ 8443 (((_var) & HTT_DLPAGER_TOTAL_LOCKED_PAGES_M) >> \ 8444 HTT_DLPAGER_TOTAL_LOCKED_PAGES_S) 8445 8446 #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_SET(_var, _val) \ 8447 do { \ 8448 HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_LOCKED_PAGES, _val); \ 8449 ((_var) &= ~(HTT_DLPAGER_TOTAL_LOCKED_PAGES_M)); \ 8450 ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_LOCKED_PAGES_S)); \ 8451 } while (0) 8452 8453 #define HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) \ 8454 (((_var) & HTT_DLPAGER_TOTAL_FREE_PAGES_M) >> \ 8455 HTT_DLPAGER_TOTAL_FREE_PAGES_S) 8456 8457 #define HTT_DLPAGER_TOTAL_FREE_PAGES_SET(_var, _val) \ 8458 do { \ 8459 HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_FREE_PAGES, _val); \ 8460 ((_var) &= ~(HTT_DLPAGER_TOTAL_FREE_PAGES_M)); \ 8461 ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_FREE_PAGES_S)); \ 8462 } while (0) 8463 8464 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) \ 8465 (((_var) & HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M) >> \ 8466 HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S) 8467 8468 #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_SET(_var, _val) \ 8469 do { \ 8470 HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX, _val); \ 8471 ((_var) &= ~(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M)); \ 8472 ((_var) |= ((_val) << HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S)); \ 8473 } while (0) 8474 8475 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ 8476 (((_var) & HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M) >> \ 8477 HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S) 8478 8479 #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_SET(_var, _val) \ 8480 do { \ 8481 HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX, _val); \ 8482 ((_var) &= ~(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M)); \ 8483 ((_var) |= ((_val) << HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S)); \ 8484 } while (0) 8485 8486 enum { 8487 HTT_STATS_PAGE_LOCKED = 0, 8488 HTT_STATS_PAGE_UNLOCKED = 1, 8489 HTT_STATS_NUM_PAGE_LOCK_STATES 8490 }; 8491 8492 /* dlPagerStats structure 8493 * Number of lock/unlock pages with last 10 lock/unlock occurrences are recorded */ 8494 typedef struct{ 8495 /** msg_dword_1 bitfields: 8496 * async_lock : 8, 8497 * sync_lock : 8, 8498 * reserved : 16; 8499 */ 8500 A_UINT32 msg_dword_1; 8501 /** mst_dword_2 bitfields: 8502 * total_locked_pages : 16, 8503 * total_free_pages : 16; 8504 */ 8505 A_UINT32 msg_dword_2; 8506 /** msg_dword_3 bitfields: 8507 * last_locked_page_idx : 16, 8508 * last_unlocked_page_idx : 16; 8509 */ 8510 A_UINT32 msg_dword_3; 8511 8512 struct { 8513 A_UINT32 page_num; 8514 A_UINT32 num_of_pages; 8515 /** timestamp is in microsecond units, from SoC timer clock */ 8516 A_UINT32 timestamp_lsbs; 8517 A_UINT32 timestamp_msbs; 8518 } last_pages_info[HTT_STATS_NUM_PAGE_LOCK_STATES][HTT_DLPAGER_STATS_MAX_HIST]; 8519 } htt_dl_pager_stats_tlv; 8520 8521 /* NOTE: 8522 * This structure is for documentation, and cannot be safely used directly. 8523 * Instead, use the constituent TLV structures to fill/parse. 8524 * STATS_TYPE : HTT_DBG_EXT_STATS_DLPAGER_STATS 8525 * TLV_TAGS: 8526 * - HTT_STATS_DLPAGER_STATS_TAG 8527 */ 8528 typedef struct { 8529 htt_tlv_hdr_t tlv_hdr; 8530 htt_dl_pager_stats_tlv dl_pager_stats; 8531 } htt_stats_dlpager_stats_tlv; 8532 /* preserve old name alias for new name consistent with the tag name */ 8533 typedef htt_stats_dlpager_stats_tlv htt_dlpager_stats_t; 8534 8535 /*======= PHY STATS ====================*/ 8536 /* 8537 * STATS TYPE : HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS 8538 * TLV_TAGS: 8539 * - HTT_STATS_PHY_COUNTERS_TAG 8540 * - HTT_STATS_PHY_STATS_TAG 8541 */ 8542 8543 #define HTT_MAX_RX_PKT_CNT 8 8544 #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 8545 #define HTT_MAX_PER_BLK_ERR_CNT 20 8546 #define HTT_MAX_RX_OTA_ERR_CNT 14 8547 #define HTT_MAX_RX_PKT_CNT_EXT 4 8548 #define HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT 4 8549 #define HTT_MAX_RX_PKT_MU_CNT 14 8550 #define HTT_MAX_TX_PKT_CNT 10 8551 #define HTT_MAX_PHY_TX_ABORT_CNT 10 8552 8553 typedef enum { 8554 HTT_STATS_CHANNEL_HALF_RATE = 0x0001, /* Half rate */ 8555 HTT_STATS_CHANNEL_QUARTER_RATE = 0x0002, /* Quarter rate */ 8556 HTT_STATS_CHANNEL_DFS = 0x0004, /* Enable radar event reporting */ 8557 HTT_STATS_CHANNEL_HOME = 0x0008, /* Home channel */ 8558 HTT_STATS_CHANNEL_PASSIVE_SCAN = 0x0010, /*Passive Scan */ 8559 HTT_STATS_CHANNEL_DFS_SAP_NOT_UP = 0x0020, /* set when VDEV_START_REQUEST, clear when VDEV_UP */ 8560 HTT_STATS_CHANNEL_PASSIVE_SCAN_CAL = 0x0040, /* need to do passive scan calibration to avoid "spikes" */ 8561 HTT_STATS_CHANNEL_DFS_SAP_UP = 0x0080, /* DFS master */ 8562 HTT_STATS_CHANNEL_DFS_CFREQ2 = 0x0100, /* Enable radar event reporting for sec80 in VHT80p80 */ 8563 HTT_STATS_CHANNEL_DTIM_SYNTH = 0x0200, /* Enable DTIM */ 8564 HTT_STATS_CHANNEL_FORCE_GAIN = 0x0400, /* Force gain mmode (only used for FTM) */ 8565 HTT_STATS_CHANNEL_PERFORM_NF_CAL = 0x0800, /* Perform NF cal in channel change (only used for FTM) */ 8566 HTT_STATS_CHANNEL_165_MODE_0 = 0x1000, /* 165 MHz mode 0 */ 8567 HTT_STATS_CHANNEL_165_MODE_1 = 0x2000, /* 165 MHz mode 1 */ 8568 HTT_STATS_CHANNEL_165_MODE_2 = 0x3000, /* 165 MHz mode 2 */ 8569 HTT_STATS_CHANNEL_165_MODE_MASK = 0x3000, /* 165 MHz 2-bit mode mask */ 8570 } HTT_STATS_CHANNEL_FLAGS; 8571 8572 typedef enum { 8573 HTT_STATS_RF_MODE_MIN = 0, 8574 HTT_STATS_RF_MODE_PHYA_ONLY = 0, // only PHYA is active 8575 HTT_STATS_RF_MODE_DBS = 1, // PHYA/5G and PHYB/2G 8576 HTT_STATS_RF_MODE_SBS = 2, // PHYA/5G and PHYB/5G in HL/NPR; PHYA0/5G and PHYA1/5G in HK 8577 HTT_STATS_RF_MODE_PHYB_ONLY = 3, // only PHYB is active 8578 HTT_STATS_RF_MODE_DBS_SBS = 4, // PHYA0/5G, PHYA1/5G and PHYB/2G in HK (the 2 5G are in different channel) 8579 HTT_STATS_RF_MODE_DBS_OR_SBS = 5, // PHYA0/5G, PHYA1/5G and PHYB/5G or 2G in HK 8580 HTT_STATS_RF_MODE_INVALID = 0xff, 8581 } HTT_STATS_RF_MODE; 8582 8583 typedef enum { 8584 HTT_STATS_RESET_CAUSE_FIRST_RESET = 0x00000001, /* First reset by application */ 8585 HTT_STATS_RESET_CAUSE_ERROR = 0x00000002, /* Triggered due to error */ 8586 HTT_STATS_RESET_CAUSE_DEEP_SLEEP = 0x00000004, /* Reset after deep sleep */ 8587 HTT_STATS_RESET_CAUSE_FULL_RESET = 0x00000008, /* Full reset without any optimizations */ 8588 HTT_STATS_RESET_CAUSE_CHANNEL_CHANGE = 0x00000010, /* For normal channel change */ 8589 HTT_STATS_RESET_CAUSE_BAND_CHANGE = 0x00000020, /* Triggered due to band change */ 8590 HTT_STATS_RESET_CAUSE_DO_CAL = 0x00000040, /* Triggered due to calibrations */ 8591 HTT_STATS_RESET_CAUSE_MCI_ERROR = 0x00000080, /* Triggered due to MCI ERROR */ 8592 HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE = 0x00000100, /* Triggered due to channel width change */ 8593 HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Triggered due to warm reset we want to just restore calibrations */ 8594 HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Triggered due to cold reset we want to just restore calibrations */ 8595 HTT_STATS_RESET_CAUSE_PHY_WARM_RESET = 0x00000800, /* Triggered due to phy warm reset we want to just restore calibrations */ 8596 HTT_STATS_RESET_CAUSE_M3_SSR = 0x00001000, /* Triggered due to SSR Restart */ 8597 HTT_STATS_RESET_CAUSE_FORCE_CAL = 0x00002000, /* Reset to force the calibration */ 8598 /* 0x00004000, 0x00008000 reserved */ 8599 HTT_STATS_NO_RESET_CHANNEL_CHANGE = 0x00010000, /* No reset, normal channel change */ 8600 HTT_STATS_NO_RESET_BAND_CHANGE = 0x00020000, /* No reset, channel change across band */ 8601 HTT_STATS_NO_RESET_CHWIDTH_CHANGE = 0x00040000, /* No reset, channel change across channel width */ 8602 HTT_STATS_NO_RESET_CHAINMASK_CHANGE = 0x00080000, /* No reset, chainmask change */ 8603 HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Triggered due to phy warm reset we want to just restore calibrations */ 8604 HTT_STATS_RESET_CAUSE_PHY_OFF_TIMEOUT_RESET = 0x00200000, /* Reset ucode because phy off ack timeout*/ 8605 HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset triggered due to NOC Address/Slave error originating at LMAC */ 8606 HTT_STATS_NO_RESET_SCAN_BACK_TO_SAME_HOME_CHANNEL_CHANGE = 0x00800000, /* No reset, scan to home channel change */ 8607 } HTT_STATS_RESET_CAUSE; 8608 8609 typedef enum { 8610 HTT_CHANNEL_RATE_FULL, 8611 HTT_CHANNEL_RATE_HALF, 8612 HTT_CHANNEL_RATE_QUARTER, 8613 8614 HTT_CHANNEL_RATE_COUNT 8615 } HTT_CHANNEL_RATE; 8616 8617 typedef enum { 8618 HTT_PHY_BW_IDX_20MHz = 0, 8619 HTT_PHY_BW_IDX_40MHz = 1, 8620 HTT_PHY_BW_IDX_80MHz = 2, 8621 HTT_PHY_BW_IDX_80Plus80 = 3, 8622 HTT_PHY_BW_IDX_160MHz = 4, 8623 HTT_PHY_BW_IDX_10MHz = 5, 8624 HTT_PHY_BW_IDX_5MHz = 6, 8625 HTT_PHY_BW_IDX_165MHz = 7, 8626 8627 } HTT_PHY_BW_IDX; 8628 8629 typedef enum { 8630 HTT_WHAL_CONFIG_NONE = 0x00000000, 8631 HTT_WHAL_CONFIG_NF_WAR = 0x00000001, 8632 HTT_WHAL_CONFIG_CAL_WAR = 0x00000002, 8633 HTT_WHAL_CONFIG_DO_NF_CAL = 0x00000004, 8634 HTT_WHAL_CONFIG_SET_WAIT_FOR_NF_CAL = 0x00000008, 8635 HTT_WHAL_CONFIG_FORCED_TX_PWR = 0x00000010, 8636 HTT_WHAL_CONFIG_FORCED_GAIN_IDX = 0x00000020, 8637 HTT_WHAL_CONFIG_FORCED_PER_CHAIN = 0x00000040, 8638 } HTT_WHAL_CONFIG; 8639 8640 typedef struct { 8641 htt_tlv_hdr_t tlv_hdr; 8642 /** number of RXTD OFDMA OTA error counts except power surge and drop */ 8643 A_UINT32 rx_ofdma_timing_err_cnt; 8644 /** rx_cck_fail_cnt: 8645 * number of cck error counts due to rx reception failure because of 8646 * timing error in cck 8647 */ 8648 A_UINT32 rx_cck_fail_cnt; 8649 /** number of times tx abort initiated by mac */ 8650 A_UINT32 mactx_abort_cnt; 8651 /** number of times rx abort initiated by mac */ 8652 A_UINT32 macrx_abort_cnt; 8653 /** number of times tx abort initiated by phy */ 8654 A_UINT32 phytx_abort_cnt; 8655 /** number of times rx abort initiated by phy */ 8656 A_UINT32 phyrx_abort_cnt; 8657 /** number of rx deferred count initiated by phy */ 8658 A_UINT32 phyrx_defer_abort_cnt; 8659 /** number of sizing events generated at LSTF */ 8660 A_UINT32 rx_gain_adj_lstf_event_cnt; /* a.k.a sizing1 */ 8661 /** number of sizing events generated at non-legacy LTF */ 8662 A_UINT32 rx_gain_adj_non_legacy_cnt; /* a.k.a sizing2 */ 8663 /** rx_pkt_cnt - 8664 * Received EOP (end-of-packet) count per packet type; 8665 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 8666 * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE 8667 */ 8668 A_UINT32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; 8669 /** rx_pkt_crc_pass_cnt - 8670 * Received EOP (end-of-packet) count per packet type; 8671 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 8672 * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE 8673 */ 8674 A_UINT32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; 8675 /** per_blk_err_cnt - 8676 * Error count per error source; 8677 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; 8678 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; 8679 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF 8680 * [13-19]=RSVD 8681 */ 8682 A_UINT32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; 8683 /** rx_ota_err_cnt - 8684 * RXTD OTA (over-the-air) error count per error reason; 8685 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; 8686 * [3] = cck fail; [4] = power surge; [5] = power drop; 8687 * [6] = btcf timing timeout error; [7] = btcf packet detect error; 8688 * [8] = coarse timing timeout error 8689 * [9-13]=RSVD 8690 */ 8691 A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; 8692 /** rx_pkt_cnt_ext - 8693 * Received EOP (end-of-packet) count per packet type for BE; 8694 * [0] = WUR; [1] = AZ; [2-3]=RVSD 8695 */ 8696 A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT]; 8697 /** rx_pkt_crc_pass_cnt_ext - 8698 * Received EOP (end-of-packet) count per packet type for BE; 8699 * [0] = WUR; [1] = AZ; [2-3]=RVSD 8700 */ 8701 A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT]; 8702 /** rx_pkt_mu_cnt - 8703 * RX MU MIMO+OFDMA packet count per packet type for BE; 8704 * [0] = 11ax OFDMA; [1] = 11ax OFDMA+MUMIMO; [2] = 11be OFDMA; 8705 * [3] = 11be OFDMA+MUMIMO; [4] = 11ax MIMO; [5] = 11be MIMO; 8706 * [6] = 11ax OFDMA; [7] = 11ax OFDMA+MUMIMO; [8] = 11be OFDMA; 8707 * [9] = 11be OFDMA+MUMIMO; [10] = 11ax MIMO; [11] = 11be MIMO; 8708 * [12-13]=RSVD 8709 */ 8710 A_UINT32 rx_pkt_mu_cnt[HTT_MAX_RX_PKT_MU_CNT]; 8711 /** tx_pkt_cnt - 8712 * num of transfered packet count per packet type; 8713 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF; 8714 * [6]= EHT; [7] = WUR; [8] = AZ; [9]=RSVD; [6-8] = Applicable only for BE 8715 */ 8716 A_UINT32 tx_pkt_cnt[HTT_MAX_TX_PKT_CNT]; 8717 /** phy_tx_abort_cnt - 8718 * phy tx abort after each tlv; 8719 * [0] = PRE-PHY desc tlv; [1] = PHY desc tlv; [2] = LSIGA tlv; 8720 * [3] = LSIGB tlv; [4] = Per User tlv; [5] = HESIGB tlv; 8721 * [6] = Service tlv; [7] = Tx Packet End tlv; [8-9]=RSVD; 8722 */ 8723 A_UINT32 phy_tx_abort_cnt[HTT_MAX_PHY_TX_ABORT_CNT]; 8724 } htt_stats_phy_counters_tlv; 8725 /* preserve old name alias for new name consistent with the tag name */ 8726 typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; 8727 8728 typedef struct { 8729 htt_tlv_hdr_t tlv_hdr; 8730 /** per chain hw noise floor values in dBm */ 8731 A_INT32 nf_chain[HTT_STATS_MAX_CHAINS]; 8732 /** number of false radars detected */ 8733 A_UINT32 false_radar_cnt; 8734 /** number of channel switches happened due to radar detection */ 8735 A_UINT32 radar_cs_cnt; 8736 /** ani_level - 8737 * ANI level (noise interference) corresponds to the channel 8738 * the desense levels range from -5 to 15 in dB units, 8739 * higher values indicating more noise interference. 8740 */ 8741 A_INT32 ani_level; 8742 /** running time in minutes since FW boot */ 8743 A_UINT32 fw_run_time; 8744 /** per chain runtime noise floor values in dBm */ 8745 A_INT32 runTime_nf_chain[HTT_STATS_MAX_CHAINS]; 8746 8747 /** DFS SW based progressive stats - start **/ 8748 8749 /* current AP operating bandwidth (refer to WLAN_PHY_MODE) */ 8750 A_UINT32 current_OBW; 8751 /* current AP device bandwidth (refer to WLAN_PHY_MODE) */ 8752 A_UINT32 current_DBW; 8753 /* last_radar_type: last detected radar type 8754 * This last_radar_type field contains a value whose meaning is not 8755 * exposed to the host; this field is only provided for debug purposes. 8756 */ 8757 A_UINT32 last_radar_type; 8758 /* dfs_reg_domain: curent DFS regulatory domain 8759 * This dfs_reg_domain field contains a value whose meaning is not 8760 * exposed to the host; this field is only provided for debug purposes. 8761 */ 8762 A_UINT32 dfs_reg_domain; 8763 /* radar_mask_bit: Radar mask setting programmed in HW registers. 8764 * Each bit represents a 20 MHz portion of the channel. 8765 * Bit 0 represents the highest 20 MHz portion within the channel. 8766 * For example... 8767 * For a 80 MHz channel, bit0 = highest 20 MHz, bit3 = lowest 20 MHz 8768 * For a 320 MHz channel, bit0 = highest 20 MHz, bit15 = lowest 20 MHz 8769 */ 8770 A_UINT32 radar_mask_bit; 8771 /* DFS radar rssi threshold (units = dBm) */ 8772 A_INT32 radar_rssi; 8773 /* DFS global flags (refer to IEEE80211_CHAN_* defines) */ 8774 A_UINT32 radar_dfs_flags; 8775 /* band center frequency of operating bandwidth (units = MHz) */ 8776 A_UINT32 band_center_frequency_OBW; 8777 /* band center frequency of device bandwidth (units = MHz) */ 8778 A_UINT32 band_center_frequency_DBW; 8779 8780 /** DFS SW based progressive stats - end **/ 8781 } htt_stats_phy_stats_tlv; 8782 /* preserve old name alias for new name consistent with the tag name */ 8783 typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; 8784 8785 typedef struct { 8786 htt_tlv_hdr_t tlv_hdr; 8787 /** current pdev_id */ 8788 A_UINT32 pdev_id; 8789 /** current channel information */ 8790 A_UINT32 chan_mhz; 8791 /** center_freq1, center_freq2 in mhz */ 8792 A_UINT32 chan_band_center_freq1; 8793 A_UINT32 chan_band_center_freq2; 8794 /** chan_phy_mode - WLAN_PHY_MODE enum type */ 8795 A_UINT32 chan_phy_mode; 8796 /** chan_flags follows HTT_STATS_CHANNEL_FLAGS enum */ 8797 A_UINT32 chan_flags; 8798 /** channel Num updated to virtual phybase */ 8799 A_UINT32 chan_num; 8800 8801 /** Cause for the phy reset - HTT_STATS_RESET_CAUSE */ 8802 A_UINT32 reset_cause; 8803 /** Cause for the previous phy reset */ 8804 A_UINT32 prev_reset_cause; 8805 /** source for the phywarm reset - HTT_STATS_RESET_CAUSE */ 8806 A_UINT32 phy_warm_reset_src; 8807 /** rxGain Table selection mode - register settings 8808 * 0 - Auto, 1/2 - Forced with and without BT override respectively 8809 */ 8810 A_UINT32 rx_gain_tbl_mode; 8811 /** current xbar value - perchain analog to digital idx mapping */ 8812 A_UINT32 xbar_val; 8813 /** Flag to indicate forced calibration */ 8814 A_UINT32 force_calibration; 8815 /** current RF mode (e.g. SBS/DBS) - follows HTT_STATS_RF_MODE enum */ 8816 A_UINT32 phyrf_mode; 8817 8818 /* PDL phyInput stats */ 8819 /** homechannel flag 8820 * 1- Homechan, 0 - scan channel 8821 */ 8822 A_UINT32 phy_homechan; 8823 /** Tx and Rx chainmask */ 8824 A_UINT32 phy_tx_ch_mask; 8825 A_UINT32 phy_rx_ch_mask; 8826 /** INI masks - to decide the INI registers to be loaded on a reset */ 8827 A_UINT32 phybb_ini_mask; 8828 A_UINT32 phyrf_ini_mask; 8829 8830 /** DFS,ADFS/Spectral scan enable masks */ 8831 A_UINT32 phy_dfs_en_mask; 8832 A_UINT32 phy_sscan_en_mask; 8833 A_UINT32 phy_synth_sel_mask; 8834 A_UINT32 phy_adfs_freq; 8835 8836 /** CCK FIR settings 8837 * register settings - filter coefficients for Iqs conversion 8838 * [31:24] = FIR_COEFF_3_0 8839 * [23:16] = FIR_COEFF_2_0 8840 * [15:8] = FIR_COEFF_1_0 8841 * [7:0] = FIR_COEFF_0_0 8842 */ 8843 A_UINT32 cck_fir_settings; 8844 /** dynamic primary channel index 8845 * primary 20MHz channel index on the current channel BW 8846 */ 8847 A_UINT32 phy_dyn_pri_chan; 8848 8849 /** 8850 * Current CCA detection threshold 8851 * dB above noisefloor req for CCA 8852 * Register settings for all subbands 8853 */ 8854 A_UINT32 cca_thresh; 8855 /** 8856 * status for dynamic CCA adjustment 8857 * 0-disabled, 1-enabled 8858 */ 8859 A_UINT32 dyn_cca_status; 8860 /** RXDEAF Register value 8861 * rxdesense_thresh_sw - VREG Register 8862 * rxdesense_thresh_hw - PHY Register 8863 */ 8864 A_UINT32 rxdesense_thresh_sw; 8865 A_UINT32 rxdesense_thresh_hw; 8866 /** Current PHY Bandwidth - 8867 * values are specified by the HTT_PHY_BW_IDX enum type 8868 */ 8869 A_UINT32 phy_bw_code; 8870 /** Current channel operating rate - 8871 * values are specified by the HTT_CHANNEL_RATE enum type 8872 */ 8873 A_UINT32 phy_rate_mode; 8874 /** current channel operating band 8875 * 0 - 5G; 1 - 2G; 2 -6G 8876 */ 8877 A_UINT32 phy_band_code; 8878 /** microcode processor virtual phy base address - 8879 * provided only for debug 8880 */ 8881 A_UINT32 phy_vreg_base; 8882 /** microcode processor virtual phy base ext address - 8883 * provided only for debug 8884 */ 8885 A_UINT32 phy_vreg_base_ext; 8886 /** HW LUT table configuration for home/scan channel - 8887 * provided only for debug 8888 */ 8889 A_UINT32 cur_table_index; 8890 /** SW configuration flag for PHY reset and Calibrations - 8891 * values are specified by the HTT_WHAL_CONFIG enum type 8892 */ 8893 A_UINT32 whal_config_flag; 8894 /** nfcal_iteration_counts: 8895 * iteration count for Home/Scan/Periodic Noise Floor calibrations 8896 * nfcal_iteration_counts[0] - home NF iteration counter 8897 * nfcal_iteration_counts[1] - scan NF iteration counter 8898 * nfcal_iteration_counts[2] - periodic NF iteration counter 8899 * These counters are not reset automatically; they are only reset 8900 * when explicitly requested by the host. 8901 */ 8902 A_UINT32 nfcal_iteration_counts[3]; 8903 } htt_stats_phy_reset_stats_tlv; 8904 /* preserve old name alias for new name consistent with the tag name */ 8905 typedef htt_stats_phy_reset_stats_tlv htt_phy_reset_stats_tlv; 8906 8907 typedef struct { 8908 htt_tlv_hdr_t tlv_hdr; 8909 8910 /** current pdev_id */ 8911 A_UINT32 pdev_id; 8912 /** ucode PHYOFF pass/failure count */ 8913 A_UINT32 cf_active_low_fail_cnt; 8914 A_UINT32 cf_active_low_pass_cnt; 8915 8916 /** PHYOFF count attempted through ucode VREG */ 8917 A_UINT32 phy_off_through_vreg_cnt; 8918 8919 /** Force calibration count */ 8920 A_UINT32 force_calibration_cnt; 8921 8922 /** phyoff count during rfmode switch */ 8923 A_UINT32 rf_mode_switch_phy_off_cnt; 8924 8925 /** Temperature based recalibration count */ 8926 A_UINT32 temperature_recal_cnt; 8927 } htt_stats_phy_reset_counters_tlv; 8928 /* preserve old name alias for new name consistent with the tag name */ 8929 typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; 8930 8931 /* Considering 320 MHz maximum 16 power levels */ 8932 #define HTT_MAX_CH_PWR_INFO_SIZE 16 8933 8934 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff 8935 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0 8936 8937 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ 8938 (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \ 8939 HTT_PHY_TPC_STATS_CTL_REGION_GRP_S) 8940 #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \ 8941 do { \ 8942 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \ 8943 ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \ 8944 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \ 8945 } while (0) 8946 8947 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00 8948 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8 8949 8950 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ 8951 (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \ 8952 HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S) 8953 #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \ 8954 do { \ 8955 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \ 8956 ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \ 8957 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \ 8958 } while (0) 8959 8960 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000 8961 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16 8962 8963 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \ 8964 (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \ 8965 HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S) 8966 #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \ 8967 do { \ 8968 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \ 8969 ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \ 8970 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \ 8971 } while (0) 8972 8973 #define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000 8974 #define HTT_PHY_TPC_STATS_CTL_FLAG_S 24 8975 8976 #define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ 8977 (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \ 8978 HTT_PHY_TPC_STATS_CTL_FLAG_S) 8979 #define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \ 8980 do { \ 8981 HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \ 8982 ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \ 8983 ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \ 8984 } while (0) 8985 8986 typedef struct { 8987 htt_tlv_hdr_t tlv_hdr; 8988 8989 /** current pdev_id */ 8990 A_UINT32 pdev_id; 8991 8992 /** Tranmsit power control scaling related configurations */ 8993 A_UINT32 tx_power_scale; 8994 A_UINT32 tx_power_scale_db; 8995 8996 /** Minimum negative tx power supported by the target */ 8997 A_INT32 min_negative_tx_power; 8998 8999 /** current configured CTL domain */ 9000 A_UINT32 reg_ctl_domain; 9001 9002 /** Regulatory power information for the current channel */ 9003 A_INT32 max_reg_allowed_power[HTT_STATS_MAX_CHAINS]; 9004 A_INT32 max_reg_allowed_power_6g[HTT_STATS_MAX_CHAINS]; 9005 /** channel max regulatory power in 0.5dB */ 9006 A_UINT32 twice_max_rd_power; 9007 9008 /** current channel and home channel's maximum possible tx power */ 9009 A_INT32 max_tx_power; 9010 A_INT32 home_max_tx_power; 9011 9012 /** channel's Power Spectral Density */ 9013 A_UINT32 psd_power; 9014 /** channel's EIRP power */ 9015 A_UINT32 eirp_power; 9016 /** 6G channel power mode 9017 * 0-LPI, 1-SP, 2-VLPI and 3-SP_CLIENT power mode 9018 */ 9019 A_UINT32 power_type_6ghz; 9020 9021 /** sub-band channels and corresponding Tx-power */ 9022 A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE]; 9023 A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE]; 9024 9025 /** array_gain_cap: 9026 * CTL Array Gain cap, units are dB 9027 * The lower-triangular portion of this square matrix is stored, i.e. 9028 * array element 0 stores matrix element (0,0) 9029 * array element 1 stores matrix element (1,0) 9030 * array element 2 stores matrix element (1,1) 9031 * array element 3 stores matrix element (2,0) 9032 * ... 9033 * array element 35 stores matrix element (7,7) 9034 */ 9035 A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; 9036 union { 9037 struct { 9038 A_UINT32 9039 ctl_region_grp:8, /** Group to which the ctl region belongs */ 9040 sub_band_index:8, /** Frequency subband index */ 9041 /** Array Gain Cap Ext2 feature enablement status */ 9042 array_gain_cap_ext2_enabled:8, 9043 /** ctl_flag: 9044 * 1st bit ULOFDMA supported 9045 * 2nd bit DLOFDMA shared Exception supported 9046 */ 9047 ctl_flag:8; 9048 }; 9049 A_UINT32 ctl_args; 9050 }; 9051 } htt_stats_phy_tpc_stats_tlv; 9052 /* preserve old name alias for new name consistent with the tag name */ 9053 typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv; 9054 9055 /* NOTE: 9056 * This structure is for documentation, and cannot be safely used directly. 9057 * Instead, use the constituent TLV structures to fill/parse. 9058 */ 9059 typedef struct { 9060 htt_stats_phy_counters_tlv phy_counters; 9061 htt_stats_phy_stats_tlv phy_stats; 9062 htt_stats_phy_reset_counters_tlv phy_reset_counters; 9063 htt_stats_phy_reset_stats_tlv phy_reset_stats; 9064 htt_stats_phy_tpc_stats_tlv phy_tpc_stats; 9065 } htt_phy_counters_and_phy_stats_t; 9066 9067 /* NOTE: 9068 * This structure is for documentation, and cannot be safely used directly. 9069 * Instead, use the constituent TLV structures to fill/parse. 9070 */ 9071 typedef struct { 9072 htt_stats_soc_txrx_stats_common_tlv soc_common_stats; 9073 htt_stats_vdev_txrx_stats_hw_stats_tlv vdev_hw_stats[1/*or more*/]; 9074 } htt_vdevs_txrx_stats_t; 9075 9076 typedef struct { 9077 A_UINT32 9078 success: 16, 9079 fail: 16; 9080 } htt_stats_strm_gen_mpdus_cntr_t; 9081 9082 typedef struct { 9083 /* MSDU queue identification */ 9084 A_UINT32 9085 peer_id: 16, 9086 tid: 4, /* only TIDs 0-7 actually expected to be used */ 9087 htt_qtype: 4, /* refer to HTT_MSDUQ_INDEX */ 9088 reserved: 8; 9089 } htt_stats_strm_msdu_queue_id; 9090 9091 typedef struct { 9092 htt_tlv_hdr_t tlv_hdr; 9093 htt_stats_strm_msdu_queue_id queue_id; 9094 htt_stats_strm_gen_mpdus_cntr_t svc_interval; 9095 htt_stats_strm_gen_mpdus_cntr_t burst_size; 9096 } htt_stats_strm_gen_mpdus_tlv; 9097 /* preserve old name alias for new name consistent with the tag name */ 9098 typedef htt_stats_strm_gen_mpdus_tlv htt_stats_strm_gen_mpdus_tlv_t; 9099 9100 typedef struct { 9101 htt_tlv_hdr_t tlv_hdr; 9102 htt_stats_strm_msdu_queue_id queue_id; 9103 struct { 9104 A_UINT32 9105 timestamp_prior_ms: 16, 9106 timestamp_now_ms: 16; 9107 A_UINT32 9108 interval_spec_ms: 16, 9109 margin_ms: 16; 9110 } svc_interval; 9111 struct { 9112 A_UINT32 9113 /* consumed_bytes_orig: 9114 * Raw count (actually estimate) of how many bytes were removed 9115 * from the MSDU queue by the GEN_MPDUS operation. 9116 */ 9117 consumed_bytes_orig: 16, 9118 /* consumed_bytes_final: 9119 * Adjusted count of removed bytes that incorporates normalizing 9120 * by the actual service interval compared to the expected 9121 * service interval. 9122 * This allows the burst size computation to be independent of 9123 * whether the target is doing GEN_MPDUS at only the service 9124 * interval, or substantially more often than the service 9125 * interval. 9126 * consumed_bytes_final = consumed_bytes_orig / 9127 * (svc_interval / ref_svc_interval) 9128 */ 9129 consumed_bytes_final: 16; 9130 A_UINT32 9131 remaining_bytes: 16, 9132 reserved: 16; 9133 A_UINT32 9134 burst_size_spec: 16, 9135 margin_bytes: 16; 9136 } burst_size; 9137 } htt_stats_strm_gen_mpdus_details_tlv; 9138 /* preserve old name alias for new name consistent with the tag name */ 9139 typedef htt_stats_strm_gen_mpdus_details_tlv 9140 htt_stats_strm_gen_mpdus_details_tlv_t; 9141 9142 typedef struct { 9143 htt_tlv_hdr_t tlv_hdr; 9144 A_UINT32 reset_count; 9145 /** lower portion (bits 31:0) of reset time, in milliseconds */ 9146 A_UINT32 reset_time_lo_ms; 9147 /** upper portion (bits 63:32) of reset time, in milliseconds */ 9148 A_UINT32 reset_time_hi_ms; 9149 /** lower portion (bits 31:0) of disengage time, in milliseconds */ 9150 A_UINT32 disengage_time_lo_ms; 9151 /** upper portion (bits 63:32) of disengage time, in milliseconds */ 9152 A_UINT32 disengage_time_hi_ms; 9153 /** lower portion (bits 31:0) of engage time, in milliseconds */ 9154 A_UINT32 engage_time_lo_ms; 9155 /** upper portion (bits 63:32) of engage time, in milliseconds */ 9156 A_UINT32 engage_time_hi_ms; 9157 A_UINT32 disengage_count; 9158 A_UINT32 engage_count; 9159 A_UINT32 drain_dest_ring_mask; 9160 } htt_stats_dmac_reset_stats_tlv; 9161 /* preserve old name alias for new name consistent with the tag name */ 9162 typedef htt_stats_dmac_reset_stats_tlv htt_dmac_reset_stats_tlv; 9163 9164 9165 /* Support up to 640 MHz mode for future expansion */ 9166 #define HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT 32 9167 9168 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_M 0x000000ff 9169 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_S 0 9170 9171 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_GET(_var) \ 9172 (((_var) & HTT_PDEV_PUNCTURE_STATS_MAC_ID_M) >> \ 9173 HTT_PDEV_PUNCTURE_STATS_MAC_ID_S) 9174 9175 #define HTT_PDEV_PUNCTURE_STATS_MAC_ID_SET(_var, _val) \ 9176 do { \ 9177 HTT_CHECK_SET_VAL(HTT_PDEV_PUNCTURE_STATS_MAC_ID, _val); \ 9178 ((_var) |= ((_val) << HTT_PDEV_PUNCTURE_STATS_MAC_ID_S)); \ 9179 } while (0) 9180 9181 /* 9182 * TLV used to provide puncturing related stats for TX/RX and each PPDU type. 9183 */ 9184 typedef struct { 9185 htt_tlv_hdr_t tlv_hdr; 9186 9187 /** 9188 * BIT [ 7 : 0] :- mac_id 9189 * BIT [31 : 8] :- reserved 9190 */ 9191 union { 9192 struct { 9193 A_UINT32 mac_id: 8, 9194 reserved: 24; 9195 }; 9196 A_UINT32 mac_id__word; 9197 }; 9198 9199 /* 9200 * Stats direction (TX/RX). Enum value from HTT_STATS_DIRECTION. 9201 */ 9202 A_UINT32 direction; 9203 9204 /* 9205 * Preamble type. Enum value from HTT_STATS_PREAM_TYPE. 9206 * 9207 * Note that for although OFDM rates don't technically support 9208 * "puncturing", this TLV can be used to indicate the 20 MHz sub-bands 9209 * utilized for OFDM legacy duplicate packets, which are also used during 9210 * puncturing sequences. 9211 */ 9212 A_UINT32 preamble; 9213 9214 /* 9215 * Stats PPDU type. Enum value from HTT_STATS_PPDU_TYPE. 9216 */ 9217 A_UINT32 ppdu_type; 9218 9219 /* 9220 * Indicates the number of valid elements in the 9221 * "num_subbands_used_cnt" array, and must be <= 9222 * HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT. 9223 * 9224 * Also indicates how many bits in the last_used_pattern_mask may be 9225 * non-zero. 9226 */ 9227 A_UINT32 subband_count; 9228 9229 /* 9230 * The last used transmit 20 MHz subband mask. Bit 0 represents the lowest 9231 * 20 MHz subband mask, bit 1 the second lowest, and so on. 9232 * 9233 * All 32 bits are valid and will be used for expansion to higher BW modes. 9234 */ 9235 A_UINT32 last_used_pattern_mask; 9236 9237 9238 /* 9239 * Number of array elements with valid values is equal to "subband_count". 9240 * If subband_count is < HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT, the 9241 * remaining elements will be implicitly set to 0x0. 9242 * 9243 * The array index is the number of 20 MHz subbands utilized during TX/RX, 9244 * and the counter value at that index is the number of times that subband 9245 * count was used. 9246 * 9247 * The count is incremented once for each OTA PPDU transmitted / received. 9248 */ 9249 A_UINT32 num_subbands_used_cnt[HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT]; 9250 } htt_stats_pdev_puncture_stats_tlv; 9251 /* preserve old name alias for new name consistent with the tag name */ 9252 typedef htt_stats_pdev_puncture_stats_tlv htt_pdev_puncture_stats_tlv; 9253 9254 enum { 9255 HTT_STATS_CAL_PROF_COLD_BOOT = 0, 9256 HTT_STATS_CAL_PROF_FULL_CHAN_SWITCH = 1, 9257 HTT_STATS_CAL_PROF_SCAN_CHAN_SWITCH = 2, 9258 HTT_STATS_CAL_PROF_DPD_SPLIT_CAL = 3, 9259 9260 HTT_STATS_MAX_PROF_CAL = 4, 9261 }; 9262 9263 #define HTT_STATS_MAX_CAL_IDX_CNT 8 9264 typedef struct { /* DEPRECATED */ 9265 9266 htt_tlv_hdr_t tlv_hdr; 9267 9268 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 9269 9270 /** To verify whether prof cal is enabled or not */ 9271 A_UINT32 enable; 9272 9273 /** current pdev_id */ 9274 A_UINT32 pdev_id; 9275 9276 /** The cnt is incremented when each time the calindex takes place */ 9277 A_UINT32 cnt[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9278 9279 /** Minimum time taken to complete the calibration - in us */ 9280 A_UINT32 min[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9281 9282 /** Maximum time taken to complete the calibration -in us */ 9283 A_UINT32 max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9284 9285 /** Time taken by the cal for its final time execution - in us */ 9286 A_UINT32 last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9287 9288 /** Total time taken - in us */ 9289 A_UINT32 tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9290 9291 /** hist_intvl - by default will be set to 2000 us */ 9292 A_UINT32 hist_intvl[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9293 9294 /** 9295 * If last is less than hist_intvl, then hist[0]++, 9296 * If last is less than hist_intvl << 1, then hist[1]++, 9297 * otherwise hist[2]++. 9298 */ 9299 A_UINT32 hist[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT][HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 9300 9301 /** Pf_last will log the current no of page faults */ 9302 A_UINT32 pf_last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9303 9304 /** Sum of all page faults happened */ 9305 A_UINT32 pf_tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9306 9307 /** If pf_last > pf_max then pf_max = pf_last */ 9308 A_UINT32 pf_max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9309 9310 /** 9311 * For each cal profile, only certain no of cal indices were invoked, 9312 * this member will store what all the indices got invoked per each 9313 * cal profile 9314 */ 9315 A_UINT32 enabledCalIdx[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9316 9317 /** No of indices invoked per each cal profile */ 9318 A_UINT32 CalCnt[HTT_STATS_MAX_PROF_CAL]; 9319 } htt_stats_latency_prof_cal_stats_tlv; /* DEPRECATED */ 9320 /* preserve old name alias for new name consistent with the tag name */ 9321 typedef htt_stats_latency_prof_cal_stats_tlv htt_latency_prof_cal_stats_tlv; /* DEPRECATED */ 9322 9323 typedef struct { 9324 /** The cnt is incremented when each time the calindex takes place */ 9325 A_UINT32 cnt; 9326 9327 /** Minimum time taken to complete the calibration - in us */ 9328 A_UINT32 min; 9329 9330 /** Maximum time taken to complete the calibration -in us */ 9331 A_UINT32 max; 9332 9333 /** Time taken by the cal for its final time execution - in us */ 9334 A_UINT32 last; 9335 9336 /** Total time taken - in us */ 9337 A_UINT32 tot; 9338 9339 /** hist_intvl - in us, by default will be set to 2000 us */ 9340 A_UINT32 hist_intvl; 9341 9342 /** 9343 * If last is less than hist_intvl, then hist[0]++, 9344 * If last is less than hist_intvl << 1, then hist[1]++, 9345 * otherwise hist[2]++. 9346 */ 9347 A_UINT32 hist[HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; 9348 9349 /** pf_last will log the current no of page faults */ 9350 A_UINT32 pf_last; 9351 9352 /** Sum of all page faults happened */ 9353 A_UINT32 pf_tot; 9354 9355 /** If pf_last > pf_max then pf_max = pf_last */ 9356 A_UINT32 pf_max; 9357 9358 /** 9359 * For each cal profile, only certain no of cal indices were invoked, 9360 * this member will store what all the indices got invoked per each 9361 * cal profile 9362 */ 9363 A_UINT32 enabled_cal_idx; 9364 9365 /* 9366 * NOTE: due to backwards-compatibility requirements, 9367 * no fields can be added to this struct. 9368 */ 9369 } htt_stats_latency_prof_cal_data; 9370 9371 typedef struct { 9372 9373 htt_tlv_hdr_t tlv_hdr; 9374 9375 /** To verify whether prof cal is enabled or not */ 9376 A_UINT32 enable; 9377 9378 /** current pdev_id */ 9379 A_UINT32 pdev_id; 9380 9381 /** No of indices invoked per each cal profile */ 9382 A_UINT32 cal_cnt[HTT_STATS_MAX_PROF_CAL]; 9383 9384 /** Latency Cal Profile name */ 9385 A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 9386 9387 /** Latency Cal data */ 9388 htt_stats_latency_prof_cal_data latency_data[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; 9389 } htt_stats_latency_prof_cal_data_tlv; 9390 9391 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F 9392 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0 9393 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M 0x00000FC0 9394 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S 6 9395 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000 9396 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12 9397 9398 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ 9399 (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ 9400 HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) 9401 9402 #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_SET(_var, _val) \ 9403 do { \ 9404 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD, _val); \ 9405 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M)); \ 9406 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S)); \ 9407 } while (0) 9408 9409 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ 9410 (((_var) & HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M) >> \ 9411 HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S) 9412 9413 #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_SET(_var, _val) \ 9414 do { \ 9415 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD, _val); \ 9416 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M)); \ 9417 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S)); \ 9418 } while (0) 9419 9420 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ 9421 (((_var) & HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M) >> \ 9422 HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S) 9423 9424 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_SET(_var, _val) \ 9425 do { \ 9426 HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX, _val); \ 9427 ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M)); \ 9428 ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \ 9429 } while (0) 9430 9431 typedef struct { 9432 htt_tlv_hdr_t tlv_hdr; 9433 union { 9434 struct { 9435 A_UINT32 peer_assoc_ipc_recvd : 6, 9436 sched_peer_delete_recvd : 6, 9437 mld_ast_index : 16, 9438 reserved : 4; 9439 }; 9440 A_UINT32 msg_dword_1; 9441 }; 9442 } htt_stats_ml_peer_ext_details_tlv; 9443 /* preserve old name alias for new name consistent with the tag name */ 9444 typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; 9445 9446 #define HTT_ML_LINK_INFO_VALID_M 0x00000001 9447 #define HTT_ML_LINK_INFO_VALID_S 0 9448 #define HTT_ML_LINK_INFO_ACTIVE_M 0x00000002 9449 #define HTT_ML_LINK_INFO_ACTIVE_S 1 9450 #define HTT_ML_LINK_INFO_PRIMARY_M 0x00000004 9451 #define HTT_ML_LINK_INFO_PRIMARY_S 2 9452 #define HTT_ML_LINK_INFO_ASSOC_LINK_M 0x00000008 9453 #define HTT_ML_LINK_INFO_ASSOC_LINK_S 3 9454 #define HTT_ML_LINK_INFO_CHIP_ID_M 0x00000070 9455 #define HTT_ML_LINK_INFO_CHIP_ID_S 4 9456 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_M 0x00007F80 9457 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_S 7 9458 #define HTT_ML_LINK_INFO_HW_LINK_ID_M 0x00038000 9459 #define HTT_ML_LINK_INFO_HW_LINK_ID_S 15 9460 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M 0x000C0000 9461 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S 18 9462 #define HTT_ML_LINK_INFO_MASTER_LINK_M 0x00100000 9463 #define HTT_ML_LINK_INFO_MASTER_LINK_S 20 9464 #define HTT_ML_LINK_INFO_ANCHOR_LINK_M 0x00200000 9465 #define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21 9466 #define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000 9467 #define HTT_ML_LINK_INFO_INITIALIZED_S 22 9468 9469 #define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff 9470 #define HTT_ML_LINK_INFO_SW_PEER_ID_S 0 9471 #define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000 9472 #define HTT_ML_LINK_INFO_VDEV_ID_S 16 9473 9474 #define HTT_ML_LINK_INFO_VALID_GET(_var) \ 9475 (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ 9476 HTT_ML_LINK_INFO_VALID_S) 9477 9478 #define HTT_ML_LINK_INFO_VALID_SET(_var, _val) \ 9479 do { \ 9480 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VALID, _val); \ 9481 ((_var) &= ~(HTT_ML_LINK_INFO_VALID_M)); \ 9482 ((_var) |= ((_val) << HTT_ML_LINK_INFO_VALID_S)); \ 9483 } while (0) 9484 9485 #define HTT_ML_LINK_INFO_ACTIVE_GET(_var) \ 9486 (((_var) & HTT_ML_LINK_INFO_ACTIVE_M) >> \ 9487 HTT_ML_LINK_INFO_ACTIVE_S) 9488 9489 #define HTT_ML_LINK_INFO_ACTIVE_SET(_var, _val) \ 9490 do { \ 9491 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ACTIVE, _val); \ 9492 ((_var) &= ~(HTT_ML_LINK_INFO_ACTIVE_M)); \ 9493 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ACTIVE_S)); \ 9494 } while (0) 9495 9496 #define HTT_ML_LINK_INFO_PRIMARY_GET(_var) \ 9497 (((_var) & HTT_ML_LINK_INFO_PRIMARY_M) >> \ 9498 HTT_ML_LINK_INFO_PRIMARY_S) 9499 9500 #define HTT_ML_LINK_INFO_PRIMARY_SET(_var, _val) \ 9501 do { \ 9502 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_PRIMARY, _val); \ 9503 ((_var) &= ~(HTT_ML_LINK_INFO_PRIMARY_M)); \ 9504 ((_var) |= ((_val) << HTT_ML_LINK_INFO_PRIMARY_S)); \ 9505 } while (0) 9506 9507 #define HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) \ 9508 (((_var) & HTT_ML_LINK_INFO_ASSOC_LINK_M) >> \ 9509 HTT_ML_LINK_INFO_ASSOC_LINK_S) 9510 9511 #define HTT_ML_LINK_INFO_ASSOC_LINK_SET(_var, _val) \ 9512 do { \ 9513 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ASSOC_LINK, _val); \ 9514 ((_var) &= ~(HTT_ML_LINK_INFO_ASSOC_LINK_M)); \ 9515 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ASSOC_LINK_S)); \ 9516 } while (0) 9517 9518 #define HTT_ML_LINK_INFO_CHIP_ID_GET(_var) \ 9519 (((_var) & HTT_ML_LINK_INFO_CHIP_ID_M) >> \ 9520 HTT_ML_LINK_INFO_CHIP_ID_S) 9521 9522 #define HTT_ML_LINK_INFO_CHIP_ID_SET(_var, _val) \ 9523 do { \ 9524 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_CHIP_ID, _val); \ 9525 ((_var) &= ~(HTT_ML_LINK_INFO_CHIP_ID_M)); \ 9526 ((_var) |= ((_val) << HTT_ML_LINK_INFO_CHIP_ID_S)); \ 9527 } while (0) 9528 9529 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) \ 9530 (((_var) & HTT_ML_LINK_INFO_IEEE_LINK_ID_M) >> \ 9531 HTT_ML_LINK_INFO_IEEE_LINK_ID_S) 9532 9533 #define HTT_ML_LINK_INFO_IEEE_LINK_ID_SET(_var, _val) \ 9534 do { \ 9535 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_IEEE_LINK_ID, _val); \ 9536 ((_var) &= ~(HTT_ML_LINK_INFO_IEEE_LINK_ID_M)); \ 9537 ((_var) |= ((_val) << HTT_ML_LINK_INFO_IEEE_LINK_ID_S)); \ 9538 } while (0) 9539 9540 #define HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) \ 9541 (((_var) & HTT_ML_LINK_INFO_HW_LINK_ID_M) >> \ 9542 HTT_ML_LINK_INFO_HW_LINK_ID_S) 9543 9544 #define HTT_ML_LINK_INFO_HW_LINK_ID_SET(_var, _val) \ 9545 do { \ 9546 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_HW_LINK_ID, _val); \ 9547 ((_var) &= ~(HTT_ML_LINK_INFO_HW_LINK_ID_M)); \ 9548 ((_var) |= ((_val) << HTT_ML_LINK_INFO_HW_LINK_ID_S)); \ 9549 } while (0) 9550 9551 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) \ 9552 (((_var) & HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M) >> \ 9553 HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S) 9554 9555 #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_SET(_var, _val) \ 9556 do { \ 9557 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_LOGICAL_LINK_ID, _val); \ 9558 ((_var) &= ~(HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M)); \ 9559 ((_var) |= ((_val) << HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S)); \ 9560 } while (0) 9561 9562 #define HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) \ 9563 (((_var) & HTT_ML_LINK_INFO_MASTER_LINK_M) >> \ 9564 HTT_ML_LINK_INFO_MASTER_LINK_S) 9565 9566 #define HTT_ML_LINK_INFO_MASTER_LINK_SET(_var, _val) \ 9567 do { \ 9568 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_MASTER_LINK, _val); \ 9569 ((_var) &= ~(HTT_ML_LINK_INFO_MASTER_LINK_M)); \ 9570 ((_var) |= ((_val) << HTT_ML_LINK_INFO_MASTER_LINK_S)); \ 9571 } while (0) 9572 9573 #define HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) \ 9574 (((_var) & HTT_ML_LINK_INFO_ANCHOR_LINK_M) >> \ 9575 HTT_ML_LINK_INFO_ANCHOR_LINK_S) 9576 9577 #define HTT_ML_LINK_INFO_ANCHOR_LINK_SET(_var, _val) \ 9578 do { \ 9579 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ANCHOR_LINK, _val); \ 9580 ((_var) &= ~(HTT_ML_LINK_INFO_ANCHOR_LINK_M)); \ 9581 ((_var) |= ((_val) << HTT_ML_LINK_INFO_ANCHOR_LINK_S)); \ 9582 } while (0) 9583 9584 #define HTT_ML_LINK_INFO_INITIALIZED_GET(_var) \ 9585 (((_var) & HTT_ML_LINK_INFO_INITIALIZED_M) >> \ 9586 HTT_ML_LINK_INFO_INITIALIZED_S) 9587 9588 #define HTT_ML_LINK_INFO_INITIALIZED_SET(_var, _val) \ 9589 do { \ 9590 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_INITIALIZED, _val); \ 9591 ((_var) &= ~(HTT_ML_LINK_INFO_INITIALIZED_M)); \ 9592 ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \ 9593 } while (0) 9594 9595 #define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ 9596 (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ 9597 HTT_ML_LINK_INFO_SW_PEER_ID_S) 9598 9599 #define HTT_ML_LINK_INFO_SW_PEER_ID_SET(_var, _val) \ 9600 do { \ 9601 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_SW_PEER_ID, _val); \ 9602 ((_var) &= ~(HTT_ML_LINK_INFO_SW_PEER_ID_M)); \ 9603 ((_var) |= ((_val) << HTT_ML_LINK_INFO_SW_PEER_ID_S)); \ 9604 } while (0) 9605 9606 #define HTT_ML_LINK_INFO_VDEV_ID_GET(_var) \ 9607 (((_var) & HTT_ML_LINK_INFO_VDEV_ID_M) >> \ 9608 HTT_ML_LINK_INFO_VDEV_ID_S) 9609 9610 #define HTT_ML_LINK_INFO_VDEV_ID_SET(_var, _val) \ 9611 do { \ 9612 HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VDEV_ID, _val); \ 9613 ((_var) &= ~(HTT_ML_LINK_INFO_VDEV_ID_M)); \ 9614 ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \ 9615 } while (0) 9616 9617 typedef struct { 9618 htt_tlv_hdr_t tlv_hdr; 9619 union { 9620 struct { 9621 A_UINT32 valid : 1, 9622 active : 1, 9623 primary : 1, 9624 assoc_link : 1, 9625 chip_id : 3, 9626 ieee_link_id : 8, 9627 hw_link_id : 3, 9628 logical_link_id : 2, 9629 master_link : 1, 9630 anchor_link : 1, 9631 initialized : 1, 9632 reserved : 9; 9633 }; 9634 A_UINT32 msg_dword_1; 9635 }; 9636 9637 union { 9638 struct { 9639 A_UINT32 sw_peer_id : 16, 9640 vdev_id : 8, 9641 reserved1 : 8; 9642 }; 9643 A_UINT32 msg_dword_2; 9644 }; 9645 9646 A_UINT32 primary_tid_mask; 9647 } htt_stats_ml_link_info_details_tlv; 9648 /* preserve old name alias for new name consistent with the tag name */ 9649 typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; 9650 9651 #define HTT_ML_PEER_DETAILS_NUM_LINKS_M 0x00000003 9652 #define HTT_ML_PEER_DETAILS_NUM_LINKS_S 0 9653 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_M 0x00003FFC 9654 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_S 2 9655 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M 0x0001C000 9656 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S 14 9657 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M 0x00060000 9658 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S 17 9659 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M 0x00380000 9660 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S 19 9661 #define HTT_ML_PEER_DETAILS_NON_STR_M 0x00400000 9662 #define HTT_ML_PEER_DETAILS_NON_STR_S 22 9663 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M 0x00800000 9664 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S 23 9665 /* for backwards compatibility, retain the old EMLSR name of the bitfield */ 9666 #define HTT_ML_PEER_DETAILS_EMLSR_M HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M 9667 #define HTT_ML_PEER_DETAILS_EMLSR_S HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S 9668 #define HTT_ML_PEER_DETAILS_IS_STA_KO_M 0x01000000 9669 #define HTT_ML_PEER_DETAILS_IS_STA_KO_S 24 9670 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M 0x06000000 9671 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S 25 9672 #define HTT_ML_PEER_DETAILS_ALLOCATED_M 0x08000000 9673 #define HTT_ML_PEER_DETAILS_ALLOCATED_S 27 9674 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M 0x10000000 9675 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S 28 9676 9677 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff 9678 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0 9679 9680 #define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ 9681 (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ 9682 HTT_ML_PEER_DETAILS_NUM_LINKS_S) 9683 9684 #define HTT_ML_PEER_DETAILS_NUM_LINKS_SET(_var, _val) \ 9685 do { \ 9686 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LINKS, _val); \ 9687 ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LINKS_M)); \ 9688 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LINKS_S)); \ 9689 } while (0) 9690 9691 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ 9692 (((_var) & HTT_ML_PEER_DETAILS_ML_PEER_ID_M) >> \ 9693 HTT_ML_PEER_DETAILS_ML_PEER_ID_S) 9694 9695 #define HTT_ML_PEER_DETAILS_ML_PEER_ID_SET(_var, _val) \ 9696 do { \ 9697 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ML_PEER_ID, _val); \ 9698 ((_var) &= ~(HTT_ML_PEER_DETAILS_ML_PEER_ID_M)); \ 9699 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ML_PEER_ID_S)); \ 9700 } while (0) 9701 9702 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ 9703 (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M) >> \ 9704 HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S) 9705 9706 #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_SET(_var, _val) \ 9707 do { \ 9708 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX, _val); \ 9709 ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M)); \ 9710 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S)); \ 9711 } while (0) 9712 9713 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ 9714 (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M) >> \ 9715 HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S) 9716 9717 #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_SET(_var, _val) \ 9718 do { \ 9719 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID, _val); \ 9720 ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M)); \ 9721 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S)); \ 9722 } while (0) 9723 9724 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ 9725 (((_var) & HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M) >> \ 9726 HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S) 9727 9728 #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_SET(_var, _val) \ 9729 do { \ 9730 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT, _val); \ 9731 ((_var) &= ~(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M)); \ 9732 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S)); \ 9733 } while (0) 9734 9735 #define HTT_ML_PEER_DETAILS_NON_STR_GET(_var) \ 9736 (((_var) & HTT_ML_PEER_DETAILS_NON_STR_M) >> \ 9737 HTT_ML_PEER_DETAILS_NON_STR_S) 9738 9739 #define HTT_ML_PEER_DETAILS_NON_STR_SET(_var, _val) \ 9740 do { \ 9741 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NON_STR, _val); \ 9742 ((_var) &= ~(HTT_ML_PEER_DETAILS_NON_STR_M)); \ 9743 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NON_STR_S)); \ 9744 } while (0) 9745 9746 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) \ 9747 (((_var) & HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M) >> \ 9748 HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S) 9749 9750 #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_SET(_var, _val) \ 9751 do { \ 9752 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE, _val); \ 9753 ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M)); \ 9754 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S)); \ 9755 } while (0) 9756 9757 /* start deprecated: 9758 * For backwards compatibility, retain a macro definition that uses 9759 * the old EMLSR name of the bitfield 9760 */ 9761 #define HTT_ML_PEER_DETAILS_EMLSR_GET(_var) \ 9762 (((_var) & HTT_ML_PEER_DETAILS_EMLSR_M) >> \ 9763 HTT_ML_PEER_DETAILS_EMLSR_S) 9764 #define HTT_ML_PEER_DETAILS_EMLSR_SET(_var, _val) \ 9765 do { \ 9766 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR, _val); \ 9767 ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_M)); \ 9768 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_S)); \ 9769 } while (0) 9770 /* end deprecated */ 9771 9772 #define HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ 9773 (((_var) & HTT_ML_PEER_DETAILS_IS_STA_KO_M) >> \ 9774 HTT_ML_PEER_DETAILS_IS_STA_KO_S) 9775 9776 #define HTT_ML_PEER_DETAILS_IS_STA_KO_SET(_var, _val) \ 9777 do { \ 9778 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_STA_KO, _val); \ 9779 ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_STA_KO_M)); \ 9780 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_STA_KO_S)); \ 9781 } while (0) 9782 9783 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ 9784 (((_var) & HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M) >> \ 9785 HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S) 9786 9787 #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_SET(_var, _val) \ 9788 do { \ 9789 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS, _val); \ 9790 ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M)); \ 9791 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S)); \ 9792 } while (0) 9793 9794 #define HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ 9795 (((_var) & HTT_ML_PEER_DETAILS_ALLOCATED_M) >> \ 9796 HTT_ML_PEER_DETAILS_ALLOCATED_S) 9797 9798 #define HTT_ML_PEER_DETAILS_ALLOCATED_SET(_var, _val) \ 9799 do { \ 9800 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ALLOCATED, _val); \ 9801 ((_var) &= ~(HTT_ML_PEER_DETAILS_ALLOCATED_M)); \ 9802 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ALLOCATED_S)); \ 9803 } while (0) 9804 9805 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) \ 9806 (((_var) & HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M) >> \ 9807 HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S) 9808 9809 #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_SET(_var, _val) \ 9810 do { \ 9811 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR_SUPPORT, _val); \ 9812 ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M)); \ 9813 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S)); \ 9814 } while (0) 9815 9816 9817 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ 9818 (((_var) & HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M) >> \ 9819 HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S) 9820 9821 #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_SET(_var, _val) \ 9822 do { \ 9823 HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP, _val); \ 9824 ((_var) &= ~(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M)); \ 9825 ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \ 9826 } while (0) 9827 9828 typedef struct { 9829 htt_tlv_hdr_t tlv_hdr; 9830 htt_mac_addr remote_mld_mac_addr; 9831 union { 9832 struct { 9833 A_UINT32 num_links : 2, 9834 ml_peer_id : 12, 9835 primary_link_idx : 3, 9836 primary_chip_id : 2, 9837 link_init_count : 3, 9838 non_str : 1, 9839 is_emlsr_active : 1, 9840 is_sta_ko : 1, 9841 num_local_links : 2, 9842 allocated : 1, 9843 emlsr_support : 1, 9844 reserved : 3; 9845 }; 9846 struct { 9847 /* 9848 * For backwards compatibility, use a dummy union element to 9849 * retain the old "emlsr" name for the "is_emlsr_active" bitfield. 9850 */ 9851 A_UINT32 dummy1 : 23, 9852 emlsr : 1, 9853 dummy2 : 8; 9854 }; 9855 A_UINT32 msg_dword_1; 9856 }; 9857 9858 union { 9859 struct { 9860 A_UINT32 participating_chips_bitmap : 8, 9861 reserved1 : 24; 9862 }; 9863 A_UINT32 msg_dword_2; 9864 }; 9865 /* 9866 * ml_peer_flags is an opaque field that cannot be interpreted by 9867 * the host; it is only for off-line debug. 9868 */ 9869 A_UINT32 ml_peer_flags; 9870 } htt_stats_ml_peer_details_tlv; 9871 /* preserve old name alias for new name consistent with the tag name */ 9872 typedef htt_stats_ml_peer_details_tlv htt_ml_peer_details_tlv; 9873 9874 /* STATS_TYPE : HTT_DBG_EXT_STATS_ML_PEERS_INFO 9875 * TLV_TAGS: 9876 * - HTT_STATS_ML_PEER_DETAILS_TAG 9877 * - HTT_STATS_ML_LINK_INFO_DETAILS_TAG 9878 * - HTT_STATS_ML_PEER_EXT_DETAILS_TAG (multiple) 9879 */ 9880 /* NOTE: 9881 * This structure is for documentation, and cannot be safely used directly. 9882 * Instead, use the constituent TLV structures to fill/parse. 9883 */ 9884 typedef struct _htt_ml_peer_stats { 9885 htt_stats_ml_peer_details_tlv ml_peer_details; 9886 htt_stats_ml_peer_ext_details_tlv ml_peer_ext_details; 9887 htt_stats_ml_link_info_details_tlv ml_link_info[1]; 9888 } htt_ml_peer_stats_t; 9889 9890 /* 9891 * ODD Mandatory Stats are grouped together from all the existing different 9892 * stats, to form a set of stats that will be used by the ODD application to 9893 * post the stats to the cloud instead of polling for the individual stats. 9894 * This is done to avoid non-mandatory stats to be polled as the data will not 9895 * be required in the recipes derivation. 9896 * Rather than the host simply printing the ODD stats, the ODD application 9897 * will take the buffer and map it to the odd_mandatory_stats data structure. 9898 */ 9899 typedef struct { 9900 htt_tlv_hdr_t tlv_hdr; 9901 A_UINT32 hw_queued; 9902 A_UINT32 hw_reaped; 9903 A_UINT32 hw_paused; 9904 A_UINT32 hw_filt; 9905 A_UINT32 seq_posted; 9906 A_UINT32 seq_completed; 9907 A_UINT32 underrun; 9908 A_UINT32 hw_flush; 9909 A_UINT32 next_seq_posted_dsr; 9910 A_UINT32 seq_posted_isr; 9911 A_UINT32 mpdu_cnt_fcs_ok; 9912 A_UINT32 mpdu_cnt_fcs_err; 9913 A_UINT32 msdu_count_tqm; 9914 A_UINT32 mpdu_count_tqm; 9915 A_UINT32 mpdus_ack_failed; 9916 A_UINT32 num_data_ppdus_tried_ota; 9917 A_UINT32 ppdu_ok; 9918 A_UINT32 num_total_ppdus_tried_ota; 9919 A_UINT32 thermal_suspend_cnt; 9920 A_UINT32 dfs_suspend_cnt; 9921 A_UINT32 tx_abort_suspend_cnt; 9922 A_UINT32 suspended_txq_mask; 9923 A_UINT32 last_suspend_reason; 9924 A_UINT32 seq_failed_queueing; 9925 A_UINT32 seq_restarted; 9926 A_UINT32 seq_txop_repost_stop; 9927 A_UINT32 next_seq_cancel; 9928 A_UINT32 seq_min_msdu_repost_stop; 9929 A_UINT32 total_phy_err_cnt; 9930 A_UINT32 ppdu_recvd; 9931 A_UINT32 tcp_msdu_cnt; 9932 A_UINT32 tcp_ack_msdu_cnt; 9933 A_UINT32 udp_msdu_cnt; 9934 A_UINT32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 9935 A_UINT32 fw_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 9936 A_UINT32 fw_ring_mpdu_err[HTT_RX_STATS_RXDMA_MAX_ERR]; 9937 A_UINT32 urrn_stats[HTT_TX_PDEV_MAX_URRN_STATS]; 9938 A_UINT32 sifs_status[HTT_TX_PDEV_MAX_SIFS_BURST_STATS]; 9939 A_UINT32 sifs_hist_status[HTT_TX_PDEV_SIFS_BURST_HIST_STATS]; 9940 A_UINT32 rx_suspend_cnt; 9941 A_UINT32 rx_suspend_fail_cnt; 9942 A_UINT32 rx_resume_cnt; 9943 A_UINT32 rx_resume_fail_cnt; 9944 A_UINT32 hwq_beacon_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 9945 A_UINT32 hwq_voice_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 9946 A_UINT32 hwq_video_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 9947 A_UINT32 hwq_best_effort_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; 9948 A_UINT32 hwq_beacon_mpdu_tried_cnt; 9949 A_UINT32 hwq_voice_mpdu_tried_cnt; 9950 A_UINT32 hwq_video_mpdu_tried_cnt; 9951 A_UINT32 hwq_best_effort_mpdu_tried_cnt; 9952 A_UINT32 hwq_beacon_mpdu_queued_cnt; 9953 A_UINT32 hwq_voice_mpdu_queued_cnt; 9954 A_UINT32 hwq_video_mpdu_queued_cnt; 9955 A_UINT32 hwq_best_effort_mpdu_queued_cnt; 9956 A_UINT32 hwq_beacon_mpdu_ack_fail_cnt; 9957 A_UINT32 hwq_voice_mpdu_ack_fail_cnt; 9958 A_UINT32 hwq_video_mpdu_ack_fail_cnt; 9959 A_UINT32 hwq_best_effort_mpdu_ack_fail_cnt; 9960 A_UINT32 pdev_resets; 9961 A_UINT32 phy_warm_reset; 9962 A_UINT32 hwsch_reset_count; 9963 A_UINT32 phy_warm_reset_ucode_trig; 9964 A_UINT32 mac_cold_reset; 9965 A_UINT32 mac_warm_reset; 9966 A_UINT32 mac_warm_reset_restore_cal; 9967 A_UINT32 phy_warm_reset_m3_ssr; 9968 A_UINT32 fw_rx_rings_reset; 9969 A_UINT32 tx_flush; 9970 A_UINT32 hwsch_dev_reset_war; 9971 A_UINT32 mac_cold_reset_restore_cal; 9972 A_UINT32 mac_only_reset; 9973 A_UINT32 mac_sfm_reset; 9974 A_UINT32 tx_ldpc; /* Number of tx PPDUs with LDPC coding */ 9975 A_UINT32 rx_ldpc; /* Number of rx PPDUs with LDPC coding */ 9976 A_UINT32 gen_mpdu_end_reason[HTT_TX_TQM_MAX_GEN_MPDU_END_REASON]; 9977 A_UINT32 list_mpdu_end_reason[HTT_TX_TQM_MAX_LIST_MPDU_END_REASON]; 9978 A_UINT32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 9979 A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 9980 A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 9981 A_UINT32 half_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 9982 A_UINT32 quarter_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 9983 A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 9984 A_UINT32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 9985 A_UINT32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 9986 A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 9987 A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 9988 A_UINT32 rts_cnt; 9989 A_UINT32 rts_success; 9990 } htt_stats_odd_pdev_mandatory_tlv; 9991 /* preserve old name alias for new name consistent with the tag name */ 9992 typedef htt_stats_odd_pdev_mandatory_tlv htt_odd_mandatory_pdev_stats_tlv; 9993 9994 typedef struct _htt_odd_mandatory_mumimo_pdev_stats_tlv { 9995 htt_tlv_hdr_t tlv_hdr; 9996 A_UINT32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 9997 A_UINT32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 9998 A_UINT32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 9999 A_UINT32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10000 A_UINT32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 10001 A_UINT32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 10002 A_UINT32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 10003 A_UINT32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; 10004 A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 10005 A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10006 A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10007 A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10008 } htt_dbg_odd_mandatory_mumimo_tlv; 10009 /* preserve old name alias for new name consistent with the tag name */ 10010 typedef htt_dbg_odd_mandatory_mumimo_tlv 10011 htt_odd_mandatory_mumimo_pdev_stats_tlv; 10012 10013 typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv { 10014 htt_tlv_hdr_t tlv_hdr; 10015 A_UINT32 mu_ofdma_seq_posted; 10016 A_UINT32 ul_mu_ofdma_seq_posted; 10017 A_UINT32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10018 A_UINT32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10019 A_UINT32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10020 A_UINT32 ofdma_tx_ldpc; 10021 A_UINT32 ul_ofdma_rx_ldpc; 10022 A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 10023 A_UINT32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 10024 A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 10025 A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10026 A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10027 A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 10028 A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 10029 A_UINT32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 10030 A_UINT32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; 10031 } htt_dbg_odd_mandatory_muofdma_tlv; 10032 /* preserve old name alias for new name consistent with the tag name */ 10033 typedef htt_dbg_odd_mandatory_muofdma_tlv 10034 htt_odd_mandatory_muofdma_pdev_stats_tlv; 10035 10036 10037 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M 0x000000ff 10038 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S 0 10039 10040 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_GET(_var) \ 10041 (((_var) & HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_M) >> \ 10042 HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S) 10043 10044 #define HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_SET(_var, _val) \ 10045 do { \ 10046 HTT_CHECK_SET_VAL(HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID, _val); \ 10047 ((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \ 10048 } while (0) 10049 10050 typedef enum { 10051 HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */ 10052 HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */ 10053 HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */ 10054 HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */ 10055 HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */ 10056 HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */ 10057 HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */ 10058 HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */ 10059 HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX, 10060 } htt_stats_sched_ofdma_txbf_ineligibility_t; 10061 10062 #define HTT_MAX_NUM_CHAN_ACC_LAT_INTR 9 10063 10064 typedef struct { 10065 htt_tlv_hdr_t tlv_hdr; 10066 /** 10067 * BIT [ 7 : 0] :- mac_id 10068 * BIT [31 : 8] :- reserved 10069 */ 10070 union { 10071 struct { 10072 A_UINT32 mac_id: 8, 10073 reserved: 24; 10074 }; 10075 A_UINT32 mac_id__word; 10076 }; 10077 10078 /** Num of instances where rate based DL OFDMA status = ENABLED */ 10079 A_UINT32 rate_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; 10080 /** Num of instances where rate based DL OFDMA status = DISABLED */ 10081 A_UINT32 rate_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; 10082 /** Num of instances where rate based DL OFDMA status = PROBING */ 10083 A_UINT32 rate_based_dlofdma_probing_count[HTT_NUM_AC_WMM]; 10084 /** Num of instances where rate based DL OFDMA status = MONITORING */ 10085 A_UINT32 rate_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; 10086 /** Num of instances where avg. channel access latency based DL OFDMA status = ENABLED */ 10087 A_UINT32 chan_acc_lat_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; 10088 /** Num of instances where avg. channel access latency based DL OFDMA status = DISABLED */ 10089 A_UINT32 chan_acc_lat_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; 10090 /** Num of instances where avg. channel access latency based DL OFDMA status = MONITORING */ 10091 A_UINT32 chan_acc_lat_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; 10092 /** Num of instances where dl ofdma is disabled due to ru allocation failure */ 10093 A_UINT32 downgrade_to_dl_su_ru_alloc_fail[HTT_NUM_AC_WMM]; 10094 /** Num of instances where dl ofdma is disabled because we have only one user in candidate list */ 10095 A_UINT32 candidate_list_single_user_disable_ofdma[HTT_NUM_AC_WMM]; 10096 /** Num of instances where ul is chosen over dl based on qos weight not specific to OFDMA */ 10097 A_UINT32 dl_cand_list_dropped_high_ul_qos_weight[HTT_NUM_AC_WMM]; 10098 /** Num of instances where dl ofdma is disabled due to pipelining */ 10099 A_UINT32 ax_dlofdma_disabled_due_to_pipelining[HTT_NUM_AC_WMM]; 10100 /** Num of instances where dl ofdma is disabled as the tid is su only eligible */ 10101 A_UINT32 dlofdma_disabled_su_only_eligible[HTT_NUM_AC_WMM]; 10102 /** Num of instances where dl ofdma is disabled because there are no mpdus tried consecutively */ 10103 A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM]; 10104 /** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */ 10105 A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM]; 10106 A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX]; 10107 /** Average channel access latency histogram stats 10108 * 10109 * avg_chan_acc_lat_hist[0]: channel access latency is < 100 us 10110 * avg_chan_acc_lat_hist[1]: 100 us <= channel access latency < 200 us 10111 * avg_chan_acc_lat_hist[2]: 200 us <= channel access latency < 300 us 10112 * avg_chan_acc_lat_hist[3]: 300 us <= channel access latency < 400 us 10113 * avg_chan_acc_lat_hist[4]: 400 us <= channel access latency < 500 us 10114 * avg_chan_acc_lat_hist[5]: 500 us <= channel access latency < 1000 us 10115 * avg_chan_acc_lat_hist[6]: 1000 us <= channel access latency < 1500 us 10116 * avg_chan_acc_lat_hist[7]: 1500 us <= channel access latency < 2000 us 10117 * avg_chan_acc_lat_hist[8]: channel access latency is >= 2000 us 10118 */ 10119 A_UINT32 avg_chan_acc_lat_hist[HTT_MAX_NUM_CHAN_ACC_LAT_INTR]; 10120 } htt_stats_pdev_sched_algo_ofdma_stats_tlv; 10121 /* preserve old name alias for new name consistent with the tag name */ 10122 typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv 10123 htt_pdev_sched_algo_ofdma_stats_tlv; 10124 10125 typedef struct { 10126 htt_tlv_hdr_t tlv_hdr; 10127 /** mac_id__word: 10128 * BIT [ 7 : 0] :- mac_id 10129 * Use the HTT_STATS_CMN_MAC_ID_GET,_SET macros to 10130 * read/write this bitfield. 10131 * BIT [31 : 8] :- reserved 10132 */ 10133 A_UINT32 mac_id__word; 10134 A_UINT32 basic_trigger_across_bss; 10135 A_UINT32 basic_trigger_within_bss; 10136 A_UINT32 bsr_trigger_across_bss; 10137 A_UINT32 bsr_trigger_within_bss; 10138 A_UINT32 mu_rts_across_bss; 10139 A_UINT32 mu_rts_within_bss; 10140 A_UINT32 ul_mumimo_trigger_across_bss; 10141 A_UINT32 ul_mumimo_trigger_within_bss; 10142 } htt_stats_pdev_mbssid_ctrl_frame_stats_tlv; 10143 /* preserve old name alias for new name consistent with the tag name */ 10144 typedef htt_stats_pdev_mbssid_ctrl_frame_stats_tlv 10145 htt_pdev_mbssid_ctrl_frame_stats_tlv; 10146 10147 typedef struct { 10148 htt_tlv_hdr_t tlv_hdr; 10149 /** 10150 * BIT [ 7 : 0] :- mac_id 10151 * Use the HTT_STATS_TDMA_MAC_ID_GET macro to extract 10152 * this bitfield. 10153 * BIT [31 : 8] :- reserved 10154 */ 10155 union { 10156 struct { 10157 A_UINT32 mac_id: 8, 10158 reserved: 24; 10159 }; 10160 A_UINT32 mac_id__word; 10161 }; 10162 10163 /** Num of Active TDMA schedules */ 10164 A_UINT32 num_tdma_active_schedules; 10165 /** Num of Reserved TDMA schedules */ 10166 A_UINT32 num_tdma_reserved_schedules; 10167 /** Num of Restricted TDMA schedules */ 10168 A_UINT32 num_tdma_restricted_schedules; 10169 /** Num of Unconfigured TDMA schedules */ 10170 A_UINT32 num_tdma_unconfigured_schedules; 10171 /** Num of TDMA slot switches */ 10172 A_UINT32 num_tdma_slot_switches; 10173 /** Num of TDMA EDCA switches */ 10174 A_UINT32 num_tdma_edca_switches; 10175 } htt_stats_pdev_tdma_tlv; 10176 /* preserve old name alias for new name consistent with the tag name */ 10177 typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; 10178 10179 #define HTT_STATS_TDMA_MAC_ID_M 0x000000ff 10180 #define HTT_STATS_TDMA_MAC_ID_S 0 10181 10182 #define HTT_STATS_TDMA_MAC_ID_GET(_var) \ 10183 (((_var) & HTT_STATS_TDMA_MAC_ID_M) >> \ 10184 HTT_STATS_TDMA_MAC_ID_S) 10185 10186 10187 /*======= Bandwidth Manager stats ====================*/ 10188 10189 #define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff 10190 #define HTT_BW_MGR_STATS_MAC_ID_S 0 10191 10192 #define HTT_BW_MGR_STATS_PRI20_IDX_M 0x0000ff00 10193 #define HTT_BW_MGR_STATS_PRI20_IDX_S 8 10194 10195 #define HTT_BW_MGR_STATS_PRI20_FREQ_M 0xffff0000 10196 #define HTT_BW_MGR_STATS_PRI20_FREQ_S 16 10197 10198 #define HTT_BW_MGR_STATS_CENTER_FREQ1_M 0x0000ffff 10199 #define HTT_BW_MGR_STATS_CENTER_FREQ1_S 0 10200 10201 #define HTT_BW_MGR_STATS_CENTER_FREQ2_M 0xffff0000 10202 #define HTT_BW_MGR_STATS_CENTER_FREQ2_S 16 10203 10204 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_M 0x000000ff 10205 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_S 0 10206 10207 #define HTT_BW_MGR_STATS_STATIC_PATTERN_M 0x00ffff00 10208 #define HTT_BW_MGR_STATS_STATIC_PATTERN_S 8 10209 10210 #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \ 10211 (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \ 10212 HTT_BW_MGR_STATS_MAC_ID_S) 10213 10214 #define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \ 10215 do { \ 10216 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_MAC_ID, _val); \ 10217 ((_var) |= ((_val) << HTT_BW_MGR_STATS_MAC_ID_S)); \ 10218 } while (0) 10219 10220 10221 #define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \ 10222 (((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \ 10223 HTT_BW_MGR_STATS_PRI20_IDX_S) 10224 10225 #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \ 10226 do { \ 10227 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \ 10228 ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \ 10229 } while (0) 10230 10231 10232 #define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \ 10233 (((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \ 10234 HTT_BW_MGR_STATS_PRI20_FREQ_S) 10235 10236 #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \ 10237 do { \ 10238 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \ 10239 ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \ 10240 } while (0) 10241 10242 10243 #define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \ 10244 (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \ 10245 HTT_BW_MGR_STATS_CENTER_FREQ1_S) 10246 10247 #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \ 10248 do { \ 10249 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \ 10250 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \ 10251 } while (0) 10252 10253 10254 #define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \ 10255 (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \ 10256 HTT_BW_MGR_STATS_CENTER_FREQ2_S) 10257 10258 #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \ 10259 do { \ 10260 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \ 10261 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \ 10262 } while (0) 10263 10264 10265 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \ 10266 (((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \ 10267 HTT_BW_MGR_STATS_CHAN_PHY_MODE_S) 10268 10269 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \ 10270 do { \ 10271 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \ 10272 ((_var) |= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \ 10273 } while (0) 10274 10275 10276 #define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ 10277 (((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \ 10278 HTT_BW_MGR_STATS_STATIC_PATTERN_S) 10279 10280 #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \ 10281 do { \ 10282 HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \ 10283 ((_var) |= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \ 10284 } while (0) 10285 10286 10287 typedef struct { 10288 htt_tlv_hdr_t tlv_hdr; 10289 10290 /* BIT [ 7 : 0] :- mac_id 10291 * BIT [ 15 : 8] :- pri20_index 10292 * BIT [ 31 : 16] :- pri20_freq in Mhz 10293 */ 10294 A_UINT32 mac_id__pri20_idx__freq; 10295 10296 /* BIT [ 15 : 0] :- centre_freq1 10297 * BIT [ 31 : 16] :- centre_freq2 10298 */ 10299 A_UINT32 centre_freq1__freq2; 10300 10301 /* BIT [ 7 : 0] :- channel_phy_mode 10302 * BIT [ 23 : 8] :- static_pattern 10303 */ 10304 A_UINT32 phy_mode__static_pattern; 10305 } htt_stats_pdev_bw_mgr_stats_tlv; 10306 /* preserve old name alias for new name consistent with the tag name */ 10307 typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv; 10308 10309 10310 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_BW_MGR 10311 * TLV_TAGS: 10312 * - HTT_STATS_PDEV_BW_MGR_STATS_TAG 10313 */ 10314 /* NOTE: 10315 * This structure is for documentation, and cannot be safely used directly. 10316 * Instead, use the constituent TLV structures to fill/parse. 10317 */ 10318 typedef struct { 10319 htt_stats_pdev_bw_mgr_stats_tlv bw_mgr_tlv; 10320 } htt_pdev_bw_mgr_stats_t; 10321 10322 10323 /*============= start MLO UMAC SSR stats ============= { */ 10324 10325 typedef enum { 10326 HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0, 10327 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH, 10328 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS, 10329 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI, 10330 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC, 10331 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL, 10332 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM, 10333 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM, 10334 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO, 10335 HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST, 10336 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES, 10337 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET, 10338 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET, 10339 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET, 10340 HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS, 10341 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST, 10342 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS, 10343 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM, 10344 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO, 10345 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM, 10346 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC, 10347 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD, 10348 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI, 10349 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS, 10350 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH, 10351 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL, 10352 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ, 10353 HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED, 10354 /* The below debug point values are reserved for future expansion. */ 10355 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28, 10356 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29, 10357 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30, 10358 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31, 10359 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32, 10360 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33, 10361 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34, 10362 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35, 10363 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36, 10364 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37, 10365 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38, 10366 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39, 10367 HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40, 10368 /* 10369 * Due to backwards compatibility requirements, no futher DBG_POINT values 10370 * can be added (but the above reserved values can be repurposed). 10371 */ 10372 HTT_MLO_UMAC_SSR_DBG_POINT_MAX, 10373 } HTT_MLO_UMAC_SSR_DBG_POINTS; 10374 10375 typedef enum { 10376 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0, 10377 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET, 10378 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START, 10379 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE, 10380 /* The below recovery handshake values are reserved for future expansion. */ 10381 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4, 10382 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5, 10383 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6, 10384 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7, 10385 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8, 10386 /* 10387 * Due to backwards compatibility requirements, no futher 10388 * RECOVERY_HANDSHAKE values can be added (but the above 10389 * reserved values can be repurposed). 10390 */ 10391 HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT, 10392 } HTT_MLO_UMAC_RECOVERY_HANDSHAKES; 10393 10394 typedef struct { 10395 htt_tlv_hdr_t tlv_hdr; 10396 A_UINT32 start_ms; 10397 A_UINT32 end_ms; 10398 A_UINT32 delta_ms; 10399 A_UINT32 reserved; 10400 A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */ 10401 A_UINT32 tqm_hw_tstamp; 10402 } htt_stats_mlo_umac_ssr_dbg_tlv; 10403 /* preserve old name alias for new name consistent with the tag name */ 10404 typedef htt_stats_mlo_umac_ssr_dbg_tlv htt_mlo_umac_ssr_dbg_tlv; 10405 10406 typedef struct { 10407 A_UINT32 last_mlo_htt_handshake_delta_ms; 10408 A_UINT32 max_mlo_htt_handshake_delta_ms; 10409 union { 10410 A_UINT32 umac_recovery_done_mask; 10411 struct { 10412 A_UINT32 pre_reset_disable_rxdma_prefetch : 1, 10413 pre_reset_pmacs_hwmlos : 1, 10414 pre_reset_global_wsi : 1, 10415 pre_reset_pmacs_dmac : 1, 10416 pre_reset_tcl : 1, 10417 pre_reset_tqm : 1, 10418 pre_reset_wbm : 1, 10419 pre_reset_reo : 1, 10420 pre_reset_host : 1, 10421 reset_prerequisites : 1, 10422 reset_pre_ring_reset : 1, 10423 reset_apply_soft_reset : 1, 10424 reset_post_ring_reset : 1, 10425 reset_fw_tqm_cmdqs : 1, 10426 post_reset_host : 1, 10427 post_reset_umac_interrupts : 1, 10428 post_reset_wbm : 1, 10429 post_reset_reo : 1, 10430 post_reset_tqm : 1, 10431 post_reset_pmacs_dmac : 1, 10432 post_reset_tqm_sync_cmd : 1, 10433 post_reset_global_wsi : 1, 10434 post_reset_pmacs_hwmlos : 1, 10435 post_reset_enable_rxdma_prefetch : 1, 10436 post_reset_tcl : 1, 10437 post_reset_host_enq : 1, 10438 post_reset_verify_umac_recovered : 1, 10439 reserved : 5; 10440 } done_mask; 10441 }; 10442 } htt_mlo_umac_ssr_mlo_stats_t; 10443 10444 typedef struct { 10445 htt_tlv_hdr_t tlv_hdr; 10446 htt_mlo_umac_ssr_mlo_stats_t mlo; 10447 } htt_stats_mlo_umac_ssr_mlo_tlv; 10448 /* preserve old name alias for new name consistent with the tag name */ 10449 typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; 10450 10451 /* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ 10452 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 10453 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 10454 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ 10455 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ 10456 HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) 10457 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ 10458 do { \ 10459 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ 10460 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\ 10461 } while (0) 10462 10463 /* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */ 10464 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2 10465 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1 10466 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ 10467 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ 10468 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) 10469 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ 10470 do { \ 10471 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ 10472 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\ 10473 } while (0) 10474 10475 /* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */ 10476 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4 10477 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2 10478 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ 10479 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ 10480 HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) 10481 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ 10482 do { \ 10483 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ 10484 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\ 10485 } while (0) 10486 10487 /* dword0 - b'3 - PRE_RESET_PMACS_DMAC */ 10488 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8 10489 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3 10490 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ 10491 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ 10492 HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) 10493 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ 10494 do { \ 10495 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ 10496 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\ 10497 } while (0) 10498 10499 /* dword0 - b'4 - PRE_RESET_TCL */ 10500 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10 10501 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4 10502 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ 10503 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ 10504 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) 10505 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ 10506 do { \ 10507 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ 10508 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\ 10509 } while (0) 10510 10511 /* dword0 - b'5 - PRE_RESET_TQM */ 10512 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20 10513 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5 10514 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ 10515 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ 10516 HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) 10517 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ 10518 do { \ 10519 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ 10520 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\ 10521 } while (0) 10522 10523 /* dword0 - b'6 - PRE_RESET_WBM */ 10524 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40 10525 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6 10526 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ 10527 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ 10528 HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) 10529 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ 10530 do { \ 10531 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ 10532 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\ 10533 } while (0) 10534 10535 /* dword0 - b'7 - PRE_RESET_REO */ 10536 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80 10537 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7 10538 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ 10539 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ 10540 HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) 10541 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ 10542 do { \ 10543 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ 10544 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\ 10545 } while (0) 10546 10547 /* dword0 - b'8 - PRE_RESET_HOST */ 10548 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100 10549 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8 10550 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ 10551 (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ 10552 HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) 10553 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ 10554 do { \ 10555 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ 10556 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\ 10557 } while (0) 10558 10559 /* dword0 - b'9 - RESET_PREREQUISITES */ 10560 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200 10561 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9 10562 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ 10563 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ 10564 HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) 10565 #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ 10566 do { \ 10567 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ 10568 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\ 10569 } while (0) 10570 10571 /* dword0 - b'10 - RESET_PRE_RING_RESET */ 10572 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400 10573 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10 10574 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ 10575 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ 10576 HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) 10577 #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ 10578 do { \ 10579 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ 10580 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\ 10581 } while (0) 10582 10583 /* dword0 - b'11 - RESET_APPLY_SOFT_RESET */ 10584 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800 10585 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11 10586 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ 10587 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ 10588 HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) 10589 #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ 10590 do { \ 10591 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ 10592 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\ 10593 } while (0) 10594 10595 /* dword0 - b'12 - RESET_POST_RING_RESET */ 10596 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000 10597 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12 10598 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ 10599 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ 10600 HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) 10601 #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ 10602 do { \ 10603 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ 10604 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\ 10605 } while (0) 10606 10607 /* dword0 - b'13 - RESET_FW_TQM_CMDQS */ 10608 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000 10609 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13 10610 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ 10611 (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ 10612 HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) 10613 #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ 10614 do { \ 10615 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ 10616 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\ 10617 } while (0) 10618 10619 /* dword0 - b'14 - POST_RESET_HOST */ 10620 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000 10621 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14 10622 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ 10623 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ 10624 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) 10625 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ 10626 do { \ 10627 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ 10628 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\ 10629 } while (0) 10630 10631 /* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */ 10632 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000 10633 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15 10634 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ 10635 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ 10636 HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) 10637 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ 10638 do { \ 10639 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ 10640 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\ 10641 } while (0) 10642 10643 /* dword0 - b'16 - POST_RESET_WBM */ 10644 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000 10645 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16 10646 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ 10647 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ 10648 HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) 10649 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ 10650 do { \ 10651 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ 10652 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\ 10653 } while (0) 10654 10655 /* dword0 - b'17 - POST_RESET_REO */ 10656 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000 10657 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17 10658 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ 10659 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ 10660 HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) 10661 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ 10662 do { \ 10663 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ 10664 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\ 10665 } while (0) 10666 10667 /* dword0 - b'18 - POST_RESET_TQM */ 10668 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000 10669 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18 10670 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ 10671 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ 10672 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) 10673 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ 10674 do { \ 10675 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ 10676 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\ 10677 } while (0) 10678 10679 /* dword0 - b'19 - POST_RESET_PMACS_DMAC */ 10680 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000 10681 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19 10682 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ 10683 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ 10684 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) 10685 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ 10686 do { \ 10687 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ 10688 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\ 10689 } while (0) 10690 10691 /* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */ 10692 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000 10693 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20 10694 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ 10695 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ 10696 HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) 10697 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ 10698 do { \ 10699 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ 10700 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\ 10701 } while (0) 10702 10703 /* dword0 - b'21 - POST_RESET_GLOBAL_WSI */ 10704 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000 10705 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21 10706 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ 10707 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ 10708 HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) 10709 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ 10710 do { \ 10711 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ 10712 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\ 10713 } while (0) 10714 10715 /* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */ 10716 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000 10717 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22 10718 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ 10719 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ 10720 HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) 10721 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ 10722 do { \ 10723 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ 10724 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\ 10725 } while (0) 10726 10727 /* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */ 10728 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000 10729 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23 10730 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ 10731 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ 10732 HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) 10733 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ 10734 do { \ 10735 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ 10736 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\ 10737 } while (0) 10738 10739 /* dword0 - b'24 - POST_RESET_TCL */ 10740 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000 10741 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24 10742 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ 10743 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ 10744 HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) 10745 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ 10746 do { \ 10747 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ 10748 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\ 10749 } while (0) 10750 10751 /* dword0 - b'25 - POST_RESET_HOST_ENQ */ 10752 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000 10753 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25 10754 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ 10755 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ 10756 HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) 10757 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ 10758 do { \ 10759 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ 10760 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\ 10761 } while (0) 10762 10763 /* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */ 10764 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000 10765 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26 10766 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ 10767 (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ 10768 HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) 10769 #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ 10770 do { \ 10771 HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ 10772 ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\ 10773 } while (0) 10774 10775 typedef struct { 10776 htt_tlv_hdr_t tlv_hdr; 10777 A_UINT32 last_trigger_request_ms; 10778 A_UINT32 last_start_ms; 10779 A_UINT32 last_start_disengage_umac_ms; 10780 A_UINT32 last_enter_ssr_platform_thread_ms; 10781 A_UINT32 last_exit_ssr_platform_thread_ms; 10782 A_UINT32 last_start_engage_umac_ms; 10783 A_UINT32 last_done_successful_ms; 10784 A_UINT32 post_reset_tqm_sync_cmd_completion_ms; 10785 A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; 10786 A_UINT32 htt_sync_do_pre_reset_ms; 10787 A_UINT32 htt_sync_do_post_reset_start_ms; 10788 A_UINT32 htt_sync_do_post_reset_complete_ms; 10789 } htt_stats_mlo_umac_ssr_kpi_tstmp_tlv; 10790 /* preserve old name alias for new name consistent with the tag name */ 10791 typedef htt_stats_mlo_umac_ssr_kpi_tstmp_tlv 10792 htt_mlo_umac_ssr_kpi_tstamp_stats_tlv; 10793 10794 typedef struct { 10795 htt_tlv_hdr_t tlv_hdr; 10796 A_UINT32 htt_sync_start_ms; 10797 A_UINT32 htt_sync_delta_ms; 10798 A_UINT32 post_t2h_start_ms; 10799 A_UINT32 post_t2h_delta_ms; 10800 A_UINT32 post_t2h_msg_read_shmem_ms; 10801 A_UINT32 post_t2h_msg_write_shmem_ms; 10802 A_UINT32 post_t2h_msg_send_msg_to_host_ms; 10803 } htt_stats_mlo_umac_ssr_handshake_tlv; 10804 /* preserve old name alias for new name consistent with the tag name */ 10805 typedef htt_stats_mlo_umac_ssr_handshake_tlv 10806 htt_mlo_umac_htt_handshake_stats_tlv; 10807 10808 typedef struct { 10809 /* 10810 * Note that the host cannot use this struct directly, but instead needs 10811 * to use the TLV header within each element of each of the arrays in 10812 * this struct to determine where the subsequent item resides. 10813 */ 10814 htt_stats_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; 10815 htt_stats_mlo_umac_ssr_handshake_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; 10816 } htt_mlo_umac_ssr_kpi_delta_stats_t; 10817 10818 typedef struct { 10819 /* 10820 * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own 10821 * TLV header, and since no additional fields are added in this struct 10822 * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional 10823 * TLV header is needed. 10824 * 10825 * Note that the host cannot use this struct directly, but instead needs 10826 * to use the TLV header within each item inside the 10827 * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent 10828 * item resides. 10829 */ 10830 htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; 10831 } htt_mlo_umac_ssr_kpi_delta_stats_tlv; 10832 10833 typedef struct { 10834 A_UINT32 last_e2e_delta_ms; 10835 A_UINT32 max_e2e_delta_ms; 10836 A_UINT32 per_handshake_max_allowed_delta_ms; 10837 /* Total done count */ 10838 A_UINT32 total_success_runs_cnt; 10839 A_UINT32 umac_recovery_in_progress; 10840 /* Count of Disengaged in Pre reset */ 10841 A_UINT32 umac_disengaged_count; 10842 /* Count of UMAC Soft/Control Reset */ 10843 A_UINT32 umac_soft_reset_count; 10844 /* Count of Engaged in Post reset */ 10845 A_UINT32 umac_engaged_count; 10846 } htt_mlo_umac_ssr_common_stats_t; 10847 10848 typedef struct { 10849 htt_tlv_hdr_t tlv_hdr; 10850 htt_mlo_umac_ssr_common_stats_t cmn; 10851 } htt_stats_mlo_umac_ssr_cmn_tlv; 10852 /* preserve old name alias for new name consistent with the tag name */ 10853 typedef htt_stats_mlo_umac_ssr_cmn_tlv htt_mlo_umac_ssr_common_stats_tlv; 10854 10855 typedef struct { 10856 A_UINT32 trigger_requests_count; 10857 A_UINT32 trigger_count_for_umac_hang; 10858 A_UINT32 trigger_count_for_mlo_target_recovery_mode1; 10859 A_UINT32 trigger_count_for_unknown_signature; 10860 A_UINT32 total_trig_dropped; 10861 A_UINT32 trigger_count_for_unit_test_direct_trigger; 10862 A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout; 10863 A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout; 10864 A_UINT32 trigger_count_for_reo_hang; 10865 A_UINT32 trigger_count_for_tqm_hang; 10866 A_UINT32 trigger_count_for_tcl_hang; 10867 A_UINT32 trigger_count_for_wbm_hang; 10868 } htt_mlo_umac_ssr_trigger_stats_t; 10869 10870 typedef struct { 10871 htt_tlv_hdr_t tlv_hdr; 10872 htt_mlo_umac_ssr_trigger_stats_t trigger; 10873 } htt_stats_mlo_umac_ssr_trigger_tlv; 10874 /* preserve old name alias for new name consistent with the tag name */ 10875 typedef htt_stats_mlo_umac_ssr_trigger_tlv htt_mlo_umac_ssr_trigger_stats_tlv; 10876 10877 typedef struct { 10878 /* 10879 * Note that the host cannot use this struct directly, but instead needs 10880 * to use the TLV header within each element to determine where the 10881 * subsequent element resides. 10882 */ 10883 htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; 10884 htt_stats_mlo_umac_ssr_kpi_tstmp_tlv kpi_tstamp_tlv; 10885 } htt_mlo_umac_ssr_kpi_stats_t; 10886 10887 typedef struct { 10888 /* 10889 * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv 10890 * has its own TLV header, and since no additional fields are added in 10891 * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional 10892 * TLV header is needed. 10893 * 10894 * Note that the host cannot use this struct directly, but instead needs 10895 * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct 10896 * to determine how much data is present for this struct. 10897 */ 10898 htt_mlo_umac_ssr_kpi_stats_t kpi; 10899 } htt_mlo_umac_ssr_kpi_stats_tlv; 10900 10901 typedef struct { 10902 /* 10903 * Note that the host cannot use this struct directly, but instead needs 10904 * to use the TLV header within each element to determine where the 10905 * subsequent element resides. 10906 */ 10907 htt_stats_mlo_umac_ssr_trigger_tlv trigger_tlv; 10908 htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv; 10909 htt_stats_mlo_umac_ssr_mlo_tlv mlo_tlv; 10910 htt_stats_mlo_umac_ssr_cmn_tlv cmn_tlv; 10911 } htt_mlo_umac_ssr_stats_tlv; 10912 10913 /*============= end MLO UMAC SSR stats ============= } */ 10914 10915 typedef struct { 10916 A_UINT32 total_done; 10917 A_UINT32 trigger_requests_count; 10918 A_UINT32 total_trig_dropped; 10919 A_UINT32 umac_disengaged_count; 10920 A_UINT32 umac_soft_reset_count; 10921 A_UINT32 umac_engaged_count; 10922 A_UINT32 last_trigger_request_ms; 10923 A_UINT32 last_start_ms; 10924 A_UINT32 last_start_disengage_umac_ms; 10925 A_UINT32 last_enter_ssr_platform_thread_ms; 10926 A_UINT32 last_exit_ssr_platform_thread_ms; 10927 A_UINT32 last_start_engage_umac_ms; 10928 A_UINT32 last_done_successful_ms; 10929 A_UINT32 last_e2e_delta_ms; 10930 A_UINT32 max_e2e_delta_ms; 10931 A_UINT32 trigger_count_for_umac_hang; 10932 A_UINT32 trigger_count_for_mlo_quick_ssr; 10933 A_UINT32 trigger_count_for_unknown_signature; 10934 A_UINT32 post_reset_tqm_sync_cmd_completion_ms; 10935 A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; 10936 A_UINT32 htt_sync_do_pre_reset_ms; 10937 A_UINT32 htt_sync_do_post_reset_start_ms; 10938 A_UINT32 htt_sync_do_post_reset_complete_ms; 10939 } htt_umac_ssr_stats_t; 10940 10941 typedef struct { 10942 htt_tlv_hdr_t tlv_hdr; 10943 htt_umac_ssr_stats_t stats; 10944 } htt_stats_umac_ssr_tlv; 10945 /* preserve old name alias for new name consistent with the tag name */ 10946 typedef htt_stats_umac_ssr_tlv htt_umac_ssr_stats_tlv; 10947 10948 typedef struct { 10949 htt_tlv_hdr_t tlv_hdr; 10950 A_UINT32 svc_class_id; 10951 /* codel_drops: 10952 * How many times have MSDU queues belonging to this service class 10953 * dropped their head MSDU due to the queue's latency being above 10954 * the CoDel latency limit specified for the service class throughout 10955 * the full CoDel latency statistics collection window. 10956 */ 10957 A_UINT32 codel_drops; 10958 /* codel_no_drops: 10959 * How many times have MSDU queues belonging to this service class 10960 * completed a CoDel latency statistics collection window and 10961 * concluded that no head MSDU drop is needed, due to the MSDU queue's 10962 * latency being under the limit specified for the service class at 10963 * some point during the window. 10964 */ 10965 A_UINT32 codel_no_drops; 10966 } htt_stats_codel_svc_class_tlv; 10967 /* preserve old name alias for new name consistent with the tag name */ 10968 typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; 10969 10970 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M 0x0000FFFF 10971 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S 0 10972 10973 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ 10974 (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ 10975 HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) 10976 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ 10977 do { \ 10978 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ 10979 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S)); \ 10980 } while (0) 10981 10982 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M 0x00FF0000 10983 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S 16 10984 10985 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ 10986 (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ 10987 HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) 10988 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ 10989 do { \ 10990 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ 10991 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S)); \ 10992 } while (0) 10993 10994 #define HTT_CODEL_MSDUQ_STATS_DROPS_M 0x0000FFFF 10995 #define HTT_CODEL_MSDUQ_STATS_DROPS_S 0 10996 10997 #define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ 10998 (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ 10999 HTT_CODEL_MSDUQ_STATS_DROPS_S) 11000 #define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ 11001 do { \ 11002 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ 11003 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_DROPS_S)); \ 11004 } while (0) 11005 11006 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_M 0xFFFF0000 11007 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_S 16 11008 11009 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ 11010 (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ 11011 HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) 11012 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ 11013 do { \ 11014 HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ 11015 ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_NO_DROPS_S)); \ 11016 } while (0) 11017 11018 typedef struct { 11019 htt_tlv_hdr_t tlv_hdr; 11020 union { 11021 A_UINT32 id__word; 11022 struct { 11023 A_UINT32 tx_flow_num: 16, /* FW's MSDU queue ID */ 11024 svc_class_id: 8, 11025 reserved: 8; 11026 }; 11027 }; 11028 union { 11029 A_UINT32 stats__word; 11030 struct { 11031 A_UINT32 11032 codel_drops: 16, 11033 codel_no_drops: 16; 11034 }; 11035 }; 11036 } htt_stats_codel_msduq_tlv; 11037 /* preserve old name alias for new name consistent with the tag name */ 11038 typedef htt_stats_codel_msduq_tlv htt_codel_msduq_stats_tlv; 11039 11040 /*===================== start MLO stats ====================*/ 11041 11042 typedef struct { 11043 htt_tlv_hdr_t tlv_hdr; 11044 A_UINT32 pref_link_num_sec_link_sched; 11045 A_UINT32 pref_link_num_pref_link_timeout; 11046 A_UINT32 pref_link_num_pref_link_sch_delay_ipc; 11047 A_UINT32 pref_link_num_pref_link_timeout_ipc; 11048 } htt_stats_mlo_sched_stats_tlv; 11049 /* preserve old name alias for new name consistent with the tag name */ 11050 typedef htt_stats_mlo_sched_stats_tlv htt_mlo_sched_stats_tlv; 11051 11052 /* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS 11053 * TLV_TAGS: 11054 * - HTT_STATS_MLO_SCHED_STATS_TAG 11055 */ 11056 /* NOTE: 11057 * This structure is for documentation, and cannot be safely used directly. 11058 * Instead, use the constituent TLV structures to fill/parse. 11059 */ 11060 typedef struct _htt_mlo_sched_stats { 11061 htt_stats_mlo_sched_stats_tlv preferred_link_stats; 11062 } htt_mlo_sched_stats_t; 11063 11064 #define HTT_STATS_HWMLO_MAX_LINKS 6 11065 #define HTT_STATS_MLO_MAX_IPC_RINGS 7 11066 11067 typedef struct { 11068 htt_tlv_hdr_t tlv_hdr; 11069 A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS]; 11070 } htt_stats_pdev_mlo_ipc_stats_tlv; 11071 /* preserve old name alias for new name consistent with the tag name */ 11072 typedef htt_stats_pdev_mlo_ipc_stats_tlv htt_pdev_mlo_ipc_stats_tlv; 11073 11074 /* STATS_TYPE : HTT_DBG_MLO_IPC_STATS 11075 * TLV_TAGS: 11076 * - HTT_STATS_PDEV_MLO_IPC_STATS_TAG 11077 */ 11078 /* NOTE: 11079 * This structure is for documentation, and cannot be safely used directly. 11080 * Instead, use the constituent TLV structures to fill/parse. 11081 */ 11082 typedef struct _htt_mlo_ipc_stats { 11083 htt_stats_pdev_mlo_ipc_stats_tlv mlo_ipc_stats; 11084 } htt_pdev_mlo_ipc_stats_t; 11085 11086 /*===================== end MLO stats ======================*/ 11087 11088 typedef enum { 11089 HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0, 11090 HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1, 11091 HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2, 11092 HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3, 11093 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4, 11094 HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5, 11095 HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6, 11096 HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7, 11097 HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8, 11098 HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9, 11099 HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa, 11100 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb, 11101 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc, 11102 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd, 11103 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe, 11104 HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf, 11105 HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10, 11106 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11, 11107 HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12, 11108 HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13, 11109 HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14, 11110 HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15, 11111 HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16, 11112 HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, 11113 HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, 11114 HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR = 0x19, 11115 11116 /* add new cal types above this line */ 11117 HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF 11118 } htt_ctrl_path_stats_cal_type_ids; 11119 11120 #define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str); 11121 11122 #define HTT_GET_BITS(_val, _index, _num_bits) \ 11123 (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) 11124 11125 #define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \ 11126 HTT_GET_BITS(cal_info, 0, 8) 11127 11128 /* 11129 * Used by some hosts to print names of cal type, based on 11130 * htt_ctrl_path_cal_type_ids values specified in 11131 * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg. 11132 */ 11133 #ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS 11134 static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) 11135 { 11136 switch (cal_type_id) 11137 { 11138 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC); 11139 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC); 11140 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS); 11141 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR); 11142 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO); 11143 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ); 11144 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO); 11145 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ); 11146 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ); 11147 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2); 11148 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA); 11149 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO); 11150 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ); 11151 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS); 11152 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY); 11153 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF); 11154 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL); 11155 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ); 11156 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM); 11157 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL); 11158 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ); 11159 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER); 11160 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF); 11161 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP); 11162 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); 11163 HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR); 11164 } 11165 11166 return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; 11167 } 11168 #endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */ 11169 11170 11171 #endif /* __HTT_STATS_H__ */ 11172