1 /* 2 * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 6 * 7 * 8 * Permission to use, copy, modify, and/or distribute this software for 9 * any purpose with or without fee is hereby granted, provided that the 10 * above copyright notice and this permission notice appear in all 11 * copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 14 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 15 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 16 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 17 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 18 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * This file was originally distributed by Qualcomm Atheros, Inc. 25 * under proprietary terms before Copyright ownership was assigned 26 * to the Linux Foundation. 27 */ 28 29 /** 30 * @file htt.h 31 * 32 * @details the public header file of HTT layer 33 */ 34 35 #ifndef _HTT_H_ 36 #define _HTT_H_ 37 38 #include <htt_deps.h> 39 #include <htt_common.h> 40 41 /* 42 * Unless explicitly specified to use 64 bits to represent physical addresses 43 * (or more precisely, bus addresses), default to 32 bits. 44 */ 45 #ifndef HTT_PADDR64 46 #define HTT_PADDR64 0 47 #endif 48 49 #ifndef offsetof 50 #define offsetof(type, field) ((unsigned int)(&((type *)0)->field)) 51 #endif 52 53 /* 54 * HTT version history: 55 * 1.0 initial numbered version 56 * 1.1 modifications to STATS messages. 57 * These modifications are not backwards compatible, but since the 58 * STATS messages themselves are non-essential (they are for debugging), 59 * the 1.1 version of the HTT message library as a whole is compatible 60 * with the 1.0 version. 61 * 1.2 reset mask IE added to STATS_REQ message 62 * 1.3 stat config IE added to STATS_REQ message 63 *---- 64 * 2.0 FW rx PPDU desc added to RX_IND message 65 * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0 66 *---- 67 * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message 68 * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message 69 * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG, 70 * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages 71 * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message 72 * 3.4 Added tx_compl_req flag in HTT tx descriptor 73 * 3.5 Added flush and fail stats in rx_reorder stats structure 74 * 3.6 Added frag flag in HTT RX INORDER PADDR IND header 75 * 3.7 Made changes to support EOS Mac_core 3.0 76 * 3.8 Added txq_group information element definition; 77 * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message 78 * 3.9 Added HTT_T2H CHAN_CHANGE message; 79 * Allow buffer addresses in bus-address format to be stored as 80 * either 32 bits or 64 bits. 81 * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF 82 * messages to specify which HTT options to use. 83 * Initial TLV options cover: 84 * - whether to use 32 or 64 bits to represent LL bus addresses 85 * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems 86 * - how many tx queue groups to use 87 * 3.11 Expand rx debug stats: 88 * - Expand the rx_reorder_stats struct with stats about successful and 89 * failed rx buffer allcoations. 90 * - Add a new rx_remote_buffer_mgmt_stats struct with stats about 91 * the supply, allocation, use, and recycling of rx buffers for the 92 * "remote ring" of rx buffers in host member in LL systems. 93 * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats. 94 * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype 95 * 3.13 Add constants + macros to support 64-bit address format for the 96 * tx fragments descriptor, the rx ring buffer, and the rx ring 97 * index shadow register. 98 * 3.14 Add a method for the host to provide detailed per-frame tx specs: 99 * - Add htt_tx_msdu_desc_ext_t struct def. 100 * - Add TLV to specify whether the target supports the HTT tx MSDU 101 * extension descriptor. 102 * - Change a reserved bit in the HTT tx MSDU descriptor to an 103 * "extension" bit, to specify whether a HTT tx MSDU extension 104 * descriptor is present. 105 * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg. 106 * (This allows the host to obtain key information about the MSDU 107 * from a memory location already in the cache, rather than taking a 108 * cache miss for each MSDU by reading the HW rx descs.) 109 * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate 110 * whether a copy-engine classification result is appended to TX_FRM. 111 * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG 112 * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of 113 * tx frames in the target after the peer has already been deleted. 114 * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2 115 * 3.20 Expand rx_reorder_stats. 116 * 3.21 Add optional rx channel spec to HL RX_IND. 117 * 3.22 Expand rx_reorder_stats 118 * (distinguish duplicates within vs. outside block ack window) 119 * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate. 120 * The justified rate is calculated by two steps. The first is to multiply 121 * user-rate by (1 - PER) and the other is to smooth the step 1's result 122 * by a low pass filter. 123 * This change allows HL download scheduling to consider the WLAN rate 124 * that will be used for transmitting the downloaded frames. 125 * 3.24 Expand rx_reorder_stats 126 * (add counter for decrypt / MIC errors) 127 * 3.25 Expand rx_reorder_stats 128 * (add counter of frames received into both local + remote rings) 129 * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames 130 * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats) 131 * 3.27 Add a new interface for flow-control. The following t2h messages have 132 * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and 133 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 134 * 3.28 Add a new interface for ring interface change. The following two h2t 135 * and one t2h messages have been included: 136 * HTT_H2T_MSG_TYPE_SRING_SETUP, HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 137 * and HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 138 * 3.29 Add definitions of htt_tx_msdu_desc_ext2_t descriptor and other 139 * information elements passed from the host to a Lithium target, 140 * Add definitions of the HTT_H2T ADD_WDS_ENTRY and DELETE_WDS_ENTRY 141 * messages and the HTT_T2H MAP_FLOW_INFO message (for use with Lithium 142 * targets). 143 * 3.30 Add pktlog flag inside HTT_T2H RX_IN_ORD_PADDR_IND message 144 * 3.31 Add HTT_H2T_MSG_TYPE_RFS_CONFIG 145 * 3.32 Add HTT_WDI_IPA_OPCODE_SHARING_STATS, HTT_WDI_IPA_OPCODE_SET_QUOTA and 146 * HTT_WDI_IPA_OPCODE_IND_QUOTA for getting quota and reporting WiFi 147 * sharing stats 148 * 3.33 Add HTT_TX_COMPL_IND_STAT_DROP and HTT_TX_COMPL_IND_STAT_HOST_INSPECT 149 * 3.34 Add HW_PEER_ID field to PEER_MAP 150 * 3.35 Revise bitfield defs of HTT_SRING_SETUP message 151 * (changes are not backwards compatible, but HTT_SRING_SETUP message is 152 * not yet in use) 153 * 3.36 Add HTT_H2T_MSG_TYPE_EXT_STATS_REQ and HTT_T2H_MSG_TYPE_EXT_STATS_CONF 154 * 3.37 Add HTT_PEER_TYPE and htt_mac_addr defs 155 * 3.38 Add holes_no_filled field to rx_reorder_stats 156 * 3.39 Add host_inspected flag to htt_tx_tcl_vdev_metadata 157 * 3.40 Add optional timestamps in the HTT tx completion 158 * 3.41 Add optional tx power spec in the HTT tx completion (for DSRC use) 159 * 3.42 Add PPDU_STATS_CFG + PPDU_STATS_IND 160 * 3.43 Add HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR defs 161 * 3.44 Add htt_tx_wbm_completion_v2 162 * 3.45 Add host_tx_desc_pool flag in htt_tx_msdu_desc_ext2_t 163 * 3.46 Add MAC ID and payload size fields to HTT_T2H_MSG_TYPE_PKTLOG header 164 * 3.47 Add HTT_T2H PEER_MAP_V2 and PEER_UNMAP_V2 165 * 3.48 Add pdev ID field to HTT_T2H_MSG_TYPE_PPDU_STATS_IND and 166 * HTT_T2H_MSG_TYPE_PKTLOG 167 * 3.49 Add HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND def 168 * 3.50 Add learning_frame flag to htt_tx_msdu_desc_ext2_t 169 * 3.51 Add SW peer ID and TID num to HTT TX WBM COMPLETION 170 * 3.52 Add HTT_T2H FLOW_POOL_RESIZE msg def 171 * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def 172 * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status 173 * 3.55 Add initiator / responder flags to RX_DELBA indication 174 * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs 175 * 3.57 Add support for in-band data within HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 176 * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg 177 * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def 178 * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def 179 * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg 180 * 3.62 Add antenna mask to reserved space in htt_rx_ppdu_desc_t 181 * 3.63 Add HTT_HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND def 182 * 3.64 Add struct htt_tx_compl_ind_append_tx_tsf64 and add tx_tsf64 183 * array to the end of HTT_T2H TX_COMPL_IND msg 184 * 3.65 Add fields in htt_tx_msdu_desc_ext2_t to allow the host to provide 185 * a "cookie" to identify a MSDU, and to specify to not apply aggregation 186 * for a MSDU. 187 * 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg. 188 * Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg. 189 * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg. 190 * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP 191 * 3.69 Add htt_ul_ofdma_user_info_v0 defs 192 * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg 193 * 3.71 Add rx offload engine / flow search engine htt setup message defs for 194 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 195 * 3.72 Add tx_retry_cnt fields to htt_tx_offload_deliver_ind_hdr_t and 196 * htt_tx_data_hdr_information 197 * 3.73 Add channel pre-calibration data upload and download messages defs for 198 * HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA 199 * 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg. 200 * 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG. 201 * 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg. 202 * 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg. 203 * 3.78 Add htt_ppdu_id def. 204 * 3.79 Add HTT_NUM_AC_WMM def. 205 * 3.80 Add add WDS_FREE_COUNT bitfield in T2H PEER_UNMAP_V2 msg. 206 * 3.81 Add ppdu_start_tsf field in HTT_TX_WBM_COMPLETION_V2. 207 * 3.82 Add WIN_SIZE field to HTT_T2H_MSG_TYPE_RX_DELBA msg. 208 * 3.83 Shrink seq_idx field in HTT PPDU ID from 3 bits to 2. 209 * 3.84 Add fisa_control_bits_v2 def. 210 * 3.85 Add HTT_RX_PEER_META_DATA defs. 211 * 3.86 Add HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND def. 212 * 3.87 Add on-chip AST index field to PEER_MAP_V2 msg. 213 * 3.88 Add HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE def. 214 * 3.89 Add MSDU queue enumerations. 215 * 3.90 Add HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND def. 216 * 3.91 Add HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP, _UNMAP defs. 217 * 3.92 Add HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG def. 218 * 3.93 Add HTT_T2H_MSG_TYPE_PEER_MAP_V3 def. 219 * 3.94 Add HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 220 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND defs. 221 * 3.95 Add HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 222 * 3.96 Modify HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 223 * 3.97 Add tx MSDU drop byte count fields in vdev_txrx_stats_hw_stats TLV. 224 * 3.98 Add htt_tx_tcl_metadata_v2 def. 225 * 3.99 Add HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ, _UNMAP_REQ, _MAP_REPORT_REQ and 226 * HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF defs. 227 * 3.100 Add htt_tx_wbm_completion_v3 def. 228 * 3.101 Add HTT_UL_OFDMA_USER_INFO_V1_BITMAP defs. 229 * 3.102 Add HTT_H2T_MSG_TYPE_MSI_SETUP def. 230 * 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs. 231 * 3.104 Add mgmt/ctrl/data specs in rx ring cfg. 232 * 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs. 233 * 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def. 234 * 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t. 235 * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def. 236 * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs. 237 * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t. 238 * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg. 239 * 3.112 Add logical_link_id field in rx_peer_metadata_v1. 240 * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t 241 * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. 242 * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and 243 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. 244 * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. 245 * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. 246 * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. 247 * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. 248 * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. 249 * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. 250 * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg 251 * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. 252 * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. 253 * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. 254 * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. 255 * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. 256 * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND 257 * msg defs 258 * 3.129 Add HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT def. 259 */ 260 #define HTT_CURRENT_VERSION_MAJOR 3 261 #define HTT_CURRENT_VERSION_MINOR 129 262 263 #define HTT_NUM_TX_FRAG_DESC 1024 264 265 #define HTT_WIFI_IP_VERSION(x,y) ((x) == (y)) 266 267 #define HTT_CHECK_SET_VAL(field, val) \ 268 A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) 269 270 /* macros to assist in sign-extending fields from HTT messages */ 271 #define HTT_SIGN_BIT_MASK(field) \ 272 ((field ## _M + (1 << field ## _S)) >> 1) 273 #define HTT_SIGN_BIT(_val, field) \ 274 (_val & HTT_SIGN_BIT_MASK(field)) 275 #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ 276 (HTT_SIGN_BIT(_val, field) >> field ## _S) 277 #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ 278 (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) 279 #define HTT_SIGN_BIT_EXTENSION(_val, field) \ 280 (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ 281 HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) 282 #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ 283 (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) 284 285 286 /* 287 * TEMPORARY: 288 * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for 289 * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code 290 * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been 291 * updated. 292 */ 293 #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX 294 295 /* 296 * TEMPORARY: 297 * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for 298 * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code 299 * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been 300 * updated. 301 */ 302 #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND 303 304 /** 305 * htt_dbg_stats_type - 306 * bit positions for each stats type within a stats type bitmask 307 * The bitmask contains 24 bits. 308 */ 309 enum htt_dbg_stats_type { 310 HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ 311 HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ 312 HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ 313 HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ 314 HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ 315 HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ 316 HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ 317 HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ 318 HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ 319 HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ 320 HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ 321 HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ 322 HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ 323 HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ 324 HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ 325 HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ 326 /* bits 16-23 currently reserved */ 327 328 /* keep this last */ 329 HTT_DBG_NUM_STATS 330 }; 331 332 /*=== HTT option selection TLVs === 333 * Certain HTT messages have alternatives or options. 334 * For such cases, the host and target need to agree on which option to use. 335 * Option specification TLVs can be appended to the VERSION_REQ and 336 * VERSION_CONF messages to select options other than the default. 337 * These TLVs are entirely optional - if they are not provided, there is a 338 * well-defined default for each option. If they are provided, they can be 339 * provided in any order. Each TLV can be present or absent independent of 340 * the presence / absence of other TLVs. 341 * 342 * The HTT option selection TLVs use the following format: 343 * |31 16|15 8|7 0| 344 * |---------------------------------+----------------+----------------| 345 * | value (payload) | length | tag | 346 * |-------------------------------------------------------------------| 347 * The value portion need not be only 2 bytes; it can be extended by any 348 * integer number of 4-byte units. The total length of the TLV, including 349 * the tag and length fields, must be a multiple of 4 bytes. The length 350 * field specifies the total TLV size in 4-byte units. Thus, the typical 351 * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value 352 * field, would store 0x1 in its length field, to show that the TLV occupies 353 * a single 4-byte unit. 354 */ 355 356 /*--- TLV header format - applies to all HTT option TLVs ---*/ 357 358 enum HTT_OPTION_TLV_TAGS { 359 HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, 360 HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, 361 HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, 362 HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, 363 HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, 364 /* TCL_METADATA_VER: added to support V2 and higher of the TCL Data Cmd */ 365 HTT_OPTION_TLV_TAG_TCL_METADATA_VER = 0x5, 366 }; 367 368 #define HTT_TCL_METADATA_VER_SZ 4 369 370 PREPACK struct htt_option_tlv_header_t { 371 A_UINT8 tag; 372 A_UINT8 length; 373 } POSTPACK; 374 375 #define HTT_OPTION_TLV_TAG_M 0x000000ff 376 #define HTT_OPTION_TLV_TAG_S 0 377 #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00 378 #define HTT_OPTION_TLV_LENGTH_S 8 379 /* 380 * value0 - 16 bit value field stored in word0 381 * The TLV's value field may be longer than 2 bytes, in which case 382 * the remainder of the value is stored in word1, word2, etc. 383 */ 384 #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 385 #define HTT_OPTION_TLV_VALUE0_S 16 386 387 #define HTT_OPTION_TLV_TAG_SET(word, tag) \ 388 do { \ 389 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ 390 (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ 391 } while (0) 392 #define HTT_OPTION_TLV_TAG_GET(word) \ 393 (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) 394 395 #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ 396 do { \ 397 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ 398 (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ 399 } while (0) 400 #define HTT_OPTION_TLV_LENGTH_GET(word) \ 401 (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) 402 403 #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ 404 do { \ 405 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ 406 (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ 407 } while (0) 408 #define HTT_OPTION_TLV_VALUE0_GET(word) \ 409 (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) 410 411 /*--- format of specific HTT option TLVs ---*/ 412 413 /* 414 * HTT option TLV for specifying LL bus address size 415 * Some chips require bus addresses used by the target to access buffers 416 * within the host's memory to be 32 bits; others require bus addresses 417 * used by the target to access buffers within the host's memory to be 418 * 64 bits. 419 * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as 420 * a suffix to the VERSION_CONF message to specify which bus address format 421 * the target requires. 422 * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should 423 * default to providing bus addresses to the target in 32-bit format. 424 */ 425 enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { 426 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, 427 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, 428 }; 429 PREPACK struct htt_option_tlv_ll_bus_addr_size_t { 430 struct htt_option_tlv_header_t hdr; 431 A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ 432 } POSTPACK; 433 434 /* 435 * HTT option TLV for specifying whether HL systems should indicate 436 * over-the-air tx completion for individual frames, or should instead 437 * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly 438 * requests an OTA tx completion for a particular tx frame. 439 * This option does not apply to LL systems, where the TX_COMPL_IND 440 * is mandatory. 441 * This option is primarily intended for HL systems in which the tx frame 442 * downloads over the host --> target bus are as slow as or slower than 443 * the transmissions over the WLAN PHY. For cases where the bus is faster 444 * than the WLAN PHY, the target will transmit relatively large A-MPDUs, 445 * and consequently will send one TX_COMPL_IND message that covers several 446 * tx frames. For cases where the WLAN PHY is faster than the bus, 447 * the target will end up transmitting very short A-MPDUs, and consequently 448 * sending many TX_COMPL_IND messages, which each cover a very small number 449 * of tx frames. 450 * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as 451 * a suffix to the VERSION_REQ message to request whether the host desires to 452 * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then 453 * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the 454 * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used 455 * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the 456 * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of 457 * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV 458 * back to the host confirming use of TX_CREDIT_UPDATE_IND. 459 * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or 460 * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that 461 * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the 462 * TLV. 463 */ 464 enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { 465 HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, 466 HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, 467 }; 468 PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { 469 struct htt_option_tlv_header_t hdr; 470 A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */ 471 } POSTPACK; 472 473 /* 474 * HTT option TLV for specifying how many tx queue groups the target 475 * may establish. 476 * This TLV specifies the maximum value the target may send in the 477 * txq_group_id field of any TXQ_GROUP information elements sent by 478 * the target to the host. This allows the host to pre-allocate an 479 * appropriate number of tx queue group structs. 480 * 481 * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as 482 * a suffix to the VERSION_REQ message to specify whether the host supports 483 * tx queue groups at all, and if so if there is any limit on the number of 484 * tx queue groups that the host supports. 485 * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as 486 * a suffix to the VERSION_CONF message. If the host has specified in the 487 * VER_REQ message a limit on the number of tx queue groups the host can 488 * support, the target shall limit its specification of the maximum tx groups 489 * to be no larger than this host-specified limit. 490 * 491 * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host 492 * shall preallocate 4 tx queue group structs, and the target shall not 493 * specify a txq_group_id larger than 3. 494 */ 495 enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { 496 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, 497 /* 498 * values 1 through N specify the max number of tx queue groups 499 * the sender supports 500 */ 501 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, 502 }; 503 /* TEMPORARY backwards-compatibility alias for a typo fix - 504 * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected 505 * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided 506 * to support the old name (with the typo) until all references to the 507 * old name are replaced with the new name. 508 */ 509 #define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t 510 PREPACK struct htt_option_tlv_max_tx_queue_groups_t { 511 struct htt_option_tlv_header_t hdr; 512 A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ 513 } POSTPACK; 514 515 /* 516 * HTT option TLV for specifying whether the target supports an extended 517 * version of the HTT tx descriptor. If the target provides this TLV 518 * and specifies in the TLV that the target supports an extended version 519 * of the HTT tx descriptor, the target must check the "extension" bit in 520 * the HTT tx descriptor, and if the extension bit is set, to expect a 521 * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU 522 * descriptor. Furthermore, the target must provide room for the HTT 523 * tx MSDU extension descriptor in the target's TX_FRM buffer. 524 * This option is intended for systems where the host needs to explicitly 525 * control the transmission parameters such as tx power for individual 526 * tx frames. 527 * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host 528 * as a suffix to the VERSION_CONF message to explicitly specify whether 529 * the target supports the HTT tx MSDU extension descriptor. 530 * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted 531 * by the host as lack of target support for the HTT tx MSDU extension 532 * descriptor; the host shall provide HTT tx MSDU extension descriptors in 533 * the HTT_H2T TX_FRM messages only if the target indicates it supports 534 * the HTT tx MSDU extension descriptor. 535 * The host is not required to provide the HTT tx MSDU extension descriptor 536 * just because the target supports it; the target must check the 537 * "extension" bit in the HTT tx MSDU descriptor to determine whether an 538 * extension descriptor is present. 539 */ 540 enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { 541 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, 542 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, 543 }; 544 PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { 545 struct htt_option_tlv_header_t hdr; 546 A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */ 547 } POSTPACK; 548 549 /* 550 * For the tcl data command V2 and higher support added a new 551 * version tag HTT_OPTION_TLV_TAG_TCL_METADATA_VER. 552 * This will be used as a TLV in HTT_H2T_MSG_TYPE_VERSION_REQ and 553 * HTT_T2H_MSG_TYPE_VERSION_CONF. 554 * HTT option TLV for specifying which version of the TCL metadata struct 555 * should be used: 556 * V1 -> use htt_tx_tcl_metadata struct 557 * V2 -> use htt_tx_tcl_metadata_v2 struct 558 * Old FW will only support V1. 559 * New FW will support V2. New FW will still support V1, at least during 560 * a transition period. 561 * Similarly, old host will only support V1, and new host will support V1 + V2. 562 * 563 * The host can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 564 * HTT_H2T_MSG_TYPE_VERSION_REQ to indicate to the target which version(s) 565 * of TCL metadata the host supports. If the host doesn't provide a 566 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_REQ message, it 567 * is implicitly understood that the host only supports V1. 568 * The target can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 569 * HTT_T2H_MSG_TYPE_VERSION_CONF to indicate which version of TCL metadata 570 * the host shall use. The target shall only select one of the versions 571 * supported by the host. If the target doesn't provide a 572 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it 573 * is implicitly understood that the V1 TCL metadata shall be used. 574 * 575 * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 576 * read as version 2.1. We added support for Dynamic AST Index Allocation 577 * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 578 * we will retain older behavior of making sure the AST Index for SAWF 579 * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 580 * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and 581 * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index 582 * in TCLV2 command and do the dynamic AST allocations. 583 */ 584 enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { 585 HTT_OPTION_TLV_TCL_METADATA_V1 = 1, 586 HTT_OPTION_TLV_TCL_METADATA_V2 = 2, 587 /* values 3-20 reserved */ 588 HTT_OPTION_TLV_TCL_METADATA_V21 = 21, 589 }; 590 591 PREPACK struct htt_option_tlv_tcl_metadata_ver_t { 592 struct htt_option_tlv_header_t hdr; 593 A_UINT16 tcl_metadata_ver; /* TCL_METADATA_VER_VALUES enum */ 594 } POSTPACK; 595 596 #define HTT_OPTION_TLV_TCL_METADATA_VER_SET(word, value) \ 597 HTT_OPTION_TLV_VALUE0_SET(word, value) 598 #define HTT_OPTION_TLV_TCL_METADATA_VER_GET(word) \ 599 HTT_OPTION_TLV_VALUE0_GET(word) 600 601 typedef struct { 602 union { 603 /* BIT [11 : 0] :- tag 604 * BIT [23 : 12] :- length 605 * BIT [31 : 24] :- reserved 606 */ 607 A_UINT32 tag__length; 608 /* 609 * The following struct is not endian-portable. 610 * It is suitable for use within the target, which is known to be 611 * little-endian. 612 * The host should use the above endian-portable macros to access 613 * the tag and length bitfields in an endian-neutral manner. 614 */ 615 struct { 616 A_UINT32 tag : 12, /* BIT [11 : 0] */ 617 length : 12, /* BIT [23 : 12] */ 618 reserved : 8; /* BIT [31 : 24] */ 619 }; 620 }; 621 } htt_tlv_hdr_t; 622 623 /** HTT stats TLV tag values */ 624 typedef enum { 625 HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */ 626 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */ 627 HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */ 628 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */ 629 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */ 630 HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv, PUBLISH_FUNC=get_sring_name_data */ 631 HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv, PUBLISH_CODE=#inbound_req->tx_hwq_id_mac_id_word = ((htt_tx_hwq_stats_cmn_tlv *)tag_buf)->mac_id__hwq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 632 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */ 633 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 634 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 635 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */ 636 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */ 637 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */ 638 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */ 639 HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */ 640 HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */ 641 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */ 642 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */ 643 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */ 644 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */ 645 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */ 646 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */ 647 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */ 648 HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */ 649 HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */ 650 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */ 651 HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */ 652 HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv, PUBLISH_FUNC=create_json_response_for_sring_stats */ 653 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */ 654 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */ 655 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */ 656 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */ 657 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */ 658 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */ 659 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */ 660 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */ 661 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv, PUBLISH_CODE=#inbound_req->tx_sched_txq_id_mac_id_word = ((htt_tx_pdev_stats_sched_per_txq_tlv *)tag_buf)->mac_id__txq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 662 HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv, PUBLISH_SKIP */ 663 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */ 664 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 665 HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */ 666 HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v, PUBLISH_FUNC=create_json_response_for_sfm_client */ 667 HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv, PUBLISH_FUNC=create_json_response_for_sfm_client */ 668 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */ 669 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 670 HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */ 671 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */ 672 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */ 673 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */ 674 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */ 675 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */ 676 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */ 677 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */ 678 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */ 679 HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv, PUBLISH_FUNC=create_json_response_for_hwstats_intr_misc */ 680 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */ 681 HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */ 682 HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */ 683 HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */ 684 HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */ 685 HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */ 686 HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */ 687 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */ 688 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv, TOPIC=advanced */ 689 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */ 690 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */ 691 HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */ 692 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */ 693 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */ 694 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */ 695 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 696 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 697 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv, PUBLISH_FUNC=update_htt_pdev_cca_stat_context */ 698 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_cca_stat */ 699 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_pdev_mpdu_stat */ 700 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */ 701 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */ 702 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */ 703 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */ 704 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */ 705 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, /* htt_tx_sounding_stats_tlv */ 706 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, /* htt_tx_pdev_stats_tx_ppdu_stats_tlv_v */ 707 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, /* htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v */ 708 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, /* htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v */ 709 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, /* htt_tx_hwq_txop_used_cnt_hist_tlv_v */ 710 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, /* htt_tx_de_fw2wbm_ring_full_hist_tlv */ 711 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, /* htt_sched_txq_sched_order_su_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 712 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, /* htt_sched_txq_sched_eligibility_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 713 HTT_STATS_PDEV_OBSS_PD_TAG = 88, /* htt_pdev_obss_pd_stats_tlv */ 714 HTT_STATS_HW_WAR_TAG = 89, /* htt_hw_war_stats_tlv */ 715 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, /* htt_ring_backpressure_stats_tlv, PUBLISH_FUNC=create_json_response_for_ring_bkp_pressure_stats */ 716 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, /* htt_latency_prof_stats_tlv, PUBLISH_FUNC=create_json_response_for_latency_prof_stats */ 717 HTT_STATS_LATENCY_CTX_TAG = 92, /* htt_latency_prof_ctx_tlv */ 718 HTT_STATS_LATENCY_CNT_TAG = 93, /* htt_latency_prof_cnt_tlv */ 719 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, /* htt_rx_pdev_ul_trigger_stats_tlv */ 720 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, /* htt_rx_pdev_ul_ofdma_user_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_rx_pdev_ul_ofdma_user_stat */ 721 HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG = 96, /* htt_rx_pdev_ul_mimo_user_stats_tlv */ 722 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, /* htt_rx_pdev_ul_mumimo_trig_stats_tlv */ 723 HTT_STATS_RX_FSE_STATS_TAG = 98, /* htt_rx_fse_stats_tlv */ 724 HTT_STATS_PEER_SCHED_STATS_TAG = 99, /* htt_peer_sched_stats_tlv, TOPIC=peer */ 725 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, /* htt_sched_txq_supercycle_triggers_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */ 726 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, /* htt_peer_ctrl_path_txrx_stats_tlv */ 727 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, /* htt_pdev_ctrl_path_tx_stats_tlv */ 728 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, /* htt_rx_pdev_rate_ext_stats_tlv, PUBLISH_FUNC=create_json_response_for_rx_pdev_rate_ext */ 729 HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, /* htt_tx_pdev_dl_mu_mimo_sch_stats_tlv */ 730 HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, /* htt_tx_pdev_ul_mu_mimo_sch_stats_tlv */ 731 HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, /* htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv */ 732 HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, /* htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv */ 733 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, /* htt_tx_peer_rate_txbf_stats_tlv */ 734 HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, /* htt_stats_error_tlv_v */ 735 HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, /* htt_stats_error_tlv_v */ 736 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, /* htt_tx_selfgen_ac_sched_status_stats_tlv */ 737 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, /* htt_tx_selfgen_ax_sched_status_stats_tlv */ 738 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, /* htt_txbf_ofdma_ndpa_stats_tlv - DEPRECATED */ 739 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, /* htt_txbf_ofdma_ndp_stats_tlv - DEPRECATED */ 740 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, /* htt_txbf_ofdma_brp_stats_tlv - DEPRECATED */ 741 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, /* htt_txbf_ofdma_steer_stats_tlv - DEPRECATED */ 742 HTT_STATS_STA_UL_OFDMA_STATS_TAG = 117, /* htt_sta_ul_ofdma_stats_tlv */ 743 HTT_STATS_VDEV_RTT_RESP_STATS_TAG = 118, /* htt_vdev_rtt_resp_stats_tlv */ 744 HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG = 119, /* htt_pktlog_and_htt_ring_stats_tlv */ 745 HTT_STATS_DLPAGER_STATS_TAG = 120, /* htt_dlpager_stats_tlv */ 746 HTT_STATS_PHY_COUNTERS_TAG = 121, /* htt_phy_counters_tlv */ 747 HTT_STATS_PHY_STATS_TAG = 122, /* htt_phy_stats_tlv */ 748 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, /* htt_phy_reset_counters_tlv */ 749 HTT_STATS_PHY_RESET_STATS_TAG = 124, /* htt_phy_reset_stats_tlv */ 750 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, /* htt_t2h_soc_txrx_stats_common_tlv */ 751 HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, /* htt_t2h_vdev_txrx_stats_hw_stats_tlv */ 752 HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, /* htt_vdev_rtt_init_stats_tlv */ 753 HTT_STATS_PER_RATE_STATS_TAG = 128, /* htt_tx_rate_stats_per_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_rate_stats_per */ 754 HTT_STATS_MU_PPDU_DIST_TAG = 129, /* htt_pdev_mu_ppdu_dist_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_mu_ppdu */ 755 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, /* htt_tx_pdev_mumimo_grp_stats_tlv */ 756 HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG = 131, /* htt_tx_pdev_rate_stats_be_tlv, TOPIC=advanced */ 757 HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */ 758 HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ 759 HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ 760 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */ 761 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv, TOPIC=advanced */ 762 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv, TOPIC=advanced */ 763 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv, TOPIC=advanced */ 764 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv, TOPIC=advanced */ 765 HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ 766 HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ 767 HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ 768 HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv, TOPIC=advanced */ 769 HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv, TOPIC=advanced */ 770 HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */ 771 HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */ 772 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, /* htt_txbf_ofdma_ax_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 773 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, /* htt_txbf_ofdma_ax_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 774 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, /* htt_txbf_ofdma_ax_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 775 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, /* htt_txbf_ofdma_ax_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 776 HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG = 151, /* htt_txbf_ofdma_be_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 777 HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG = 152, /* htt_txbf_ofdma_be_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 778 HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, /* htt_txbf_ofdma_be_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 779 HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, /* htt_txbf_ofdma_be_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */ 780 HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */ 781 HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv, TOPIC=advanced */ 782 HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */ 783 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */ 784 HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */ 785 HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */ 786 HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */ 787 HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */ 788 HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */ 789 HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */ 790 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_sched_algo_ofdma_stats */ 791 HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */ 792 HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */ 793 HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */ 794 HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */ 795 HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */ 796 HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */ 797 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */ 798 HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */ 799 HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ 800 HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */ 801 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ 802 HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ 803 HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ 804 HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ 805 HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ 806 HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ 807 HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ 808 HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ 809 HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ 810 HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ 811 HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ 812 HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ 813 HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ 814 HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ 815 HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ 816 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ 817 HTT_STATS_WHAL_WSI_TAG = 192, /* htt_stats_whal_wsi_tlv */ 818 819 820 HTT_STATS_MAX_TAG, 821 } htt_stats_tlv_tag_t; 822 /* retain deprecated enum name as an alias for the current enum name */ 823 typedef htt_stats_tlv_tag_t htt_tlv_tag_t; 824 825 #define HTT_STATS_TLV_TAG_M 0x00000fff 826 #define HTT_STATS_TLV_TAG_S 0 827 #define HTT_STATS_TLV_LENGTH_M 0x00fff000 828 #define HTT_STATS_TLV_LENGTH_S 12 829 830 #define HTT_STATS_TLV_TAG_GET(_var) \ 831 (((_var) & HTT_STATS_TLV_TAG_M) >> \ 832 HTT_STATS_TLV_TAG_S) 833 834 #define HTT_STATS_TLV_TAG_SET(_var, _val) \ 835 do { \ 836 HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \ 837 ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \ 838 } while (0) 839 840 #define HTT_STATS_TLV_LENGTH_GET(_var) \ 841 (((_var) & HTT_STATS_TLV_LENGTH_M) >> \ 842 HTT_STATS_TLV_LENGTH_S) 843 #define HTT_STATS_TLV_LENGTH_SET(_var, _val) \ 844 do { \ 845 HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \ 846 ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \ 847 } while (0) 848 849 850 /*=== host -> target messages ===============================================*/ 851 852 enum htt_h2t_msg_type { 853 HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, 854 HTT_H2T_MSG_TYPE_TX_FRM = 0x1, 855 HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, 856 HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, 857 HTT_H2T_MSG_TYPE_SYNC = 0x4, 858 HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, 859 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, 860 DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ 861 HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, 862 HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, 863 HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ 864 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 865 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 866 HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, 867 HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, 868 HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, 869 HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, 870 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 871 HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, 872 HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, 873 HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, 874 HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, 875 HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, 876 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 877 HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, 878 HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, 879 HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, 880 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 881 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, 882 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, 883 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, 884 HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, 885 HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, 886 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, 887 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, 888 HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, 889 HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, 890 HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, 891 892 /* keep this last */ 893 HTT_H2T_NUM_MSGS 894 }; 895 896 /* 897 * HTT host to target message type - 898 * stored in bits 7:0 of the first word of the message 899 */ 900 #define HTT_H2T_MSG_TYPE_M 0xff 901 #define HTT_H2T_MSG_TYPE_S 0 902 903 #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ 904 do { \ 905 HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ 906 (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ 907 } while (0) 908 #define HTT_H2T_MSG_TYPE_GET(word) \ 909 (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) 910 911 /** 912 * @brief host -> target version number request message definition 913 * 914 * MSG_TYPE => HTT_H2T_MSG_TYPE_VERSION_REQ 915 * 916 * 917 * |31 24|23 16|15 8|7 0| 918 * |----------------+----------------+----------------+----------------| 919 * | reserved | msg type | 920 * |-------------------------------------------------------------------| 921 * : option request TLV (optional) | 922 * :...................................................................: 923 * 924 * The VER_REQ message may consist of a single 4-byte word, or may be 925 * extended with TLVs that specify which HTT options the host is requesting 926 * from the target. 927 * The following option TLVs may be appended to the VER_REQ message: 928 * - HL_SUPPRESS_TX_COMPL_IND 929 * - HL_MAX_TX_QUEUE_GROUPS 930 * These TLVs may appear in an arbitrary order. Any number of these TLVs 931 * may be appended to the VER_REQ message (but only one TLV of each type). 932 * 933 * Header fields: 934 * - MSG_TYPE 935 * Bits 7:0 936 * Purpose: identifies this as a version number request message 937 * Value: 0x0 (HTT_H2T_MSG_TYPE_VERSION_REQ) 938 */ 939 940 #define HTT_VER_REQ_BYTES 4 941 942 /* TBDXXX: figure out a reasonable number */ 943 #define HTT_HL_DATA_SVC_PIPE_DEPTH 24 944 #define HTT_LL_DATA_SVC_PIPE_DEPTH 64 945 946 /** 947 * @brief HTT tx MSDU descriptor 948 * 949 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_FRM 950 * 951 * @details 952 * The HTT tx MSDU descriptor is created by the host HTT SW for each 953 * tx MSDU. The HTT tx MSDU descriptor contains the information that 954 * the target firmware needs for the FW's tx processing, particularly 955 * for creating the HW msdu descriptor. 956 * The same HTT tx descriptor is used for HL and LL systems, though 957 * a few fields within the tx descriptor are used only by LL or 958 * only by HL. 959 * The HTT tx descriptor is defined in two manners: by a struct with 960 * bitfields, and by a series of [dword offset, bit mask, bit shift] 961 * definitions. 962 * The target should use the struct def, for simplicitly and clarity, 963 * but the host shall use the bit-mast + bit-shift defs, to be endian- 964 * neutral. Specifically, the host shall use the get/set macros built 965 * around the mask + shift defs. 966 */ 967 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0 968 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1 969 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1 970 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2 971 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2 972 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4 973 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3 974 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8 975 976 #define HTT_TX_VDEV_ID_WORD 0 977 #define HTT_TX_VDEV_ID_MASK 0x3f 978 #define HTT_TX_VDEV_ID_SHIFT 16 979 980 #define HTT_TX_L3_CKSUM_OFFLOAD 1 981 #define HTT_TX_L4_CKSUM_OFFLOAD 2 982 983 #define HTT_TX_MSDU_LEN_DWORD 1 984 #define HTT_TX_MSDU_LEN_MASK 0xffff; 985 986 /* 987 * HTT_VAR_PADDR macros 988 * Allow physical / bus addresses to be either a single 32-bit value, 989 * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts 990 */ 991 #define HTT_VAR_PADDR32(var_name) \ 992 A_UINT32 var_name 993 #define HTT_VAR_PADDR64_LE(var_name) \ 994 struct { \ 995 /* little-endian: lo precedes hi */ \ 996 A_UINT32 lo; \ 997 A_UINT32 hi; \ 998 } var_name 999 1000 /* 1001 * TEMPLATE_HTT_TX_MSDU_DESC_T: 1002 * This macro defines a htt_tx_msdu_descXXX_t in which any physical 1003 * addresses are stored in a XXX-bit field. 1004 * This macro is used to define both htt_tx_msdu_desc32_t and 1005 * htt_tx_msdu_desc64_t structs. 1006 */ 1007 #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ 1008 PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ 1009 { \ 1010 /* DWORD 0: flags and meta-data */ \ 1011 A_UINT32 \ 1012 msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ 1013 \ 1014 /* pkt_subtype - \ 1015 * Detailed specification of the tx frame contents, extending the \ 1016 * general specification provided by pkt_type. \ 1017 * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ 1018 * pkt_type | pkt_subtype \ 1019 * ============================================================== \ 1020 * 802.3 | bit 0:3 - Reserved \ 1021 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1022 * | not appended to the HTT message \ 1023 * | 0x1 - Copy-Engine Classification Results \ 1024 * | appended to the HTT message in the \ 1025 * | format: \ 1026 * | [HTT tx desc, frame header, \ 1027 * | CE classification results] \ 1028 * | The CE classification results begin \ 1029 * | at the next 4-byte boundary after \ 1030 * | the frame header. \ 1031 * ------------+------------------------------------------------- \ 1032 * Eth2 | bit 0:3 - Reserved \ 1033 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1034 * | not appended to the HTT message \ 1035 * | 0x1 - Copy-Engine Classification Results \ 1036 * | appended to the HTT message. \ 1037 * | See the above specification of the \ 1038 * | CE classification results location. \ 1039 * ------------+------------------------------------------------- \ 1040 * native WiFi | bit 0:3 - Reserved \ 1041 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1042 * | not appended to the HTT message \ 1043 * | 0x1 - Copy-Engine Classification Results \ 1044 * | appended to the HTT message. \ 1045 * | See the above specification of the \ 1046 * | CE classification results location. \ 1047 * ------------+------------------------------------------------- \ 1048 * mgmt | 0x0 - 802.11 MAC header absent \ 1049 * | 0x1 - 802.11 MAC header present \ 1050 * ------------+------------------------------------------------- \ 1051 * raw | bit 0: 0x0 - 802.11 MAC header absent \ 1052 * | 0x1 - 802.11 MAC header present \ 1053 * | bit 1: 0x0 - allow aggregation \ 1054 * | 0x1 - don't allow aggregation \ 1055 * | bit 2: 0x0 - perform encryption \ 1056 * | 0x1 - don't perform encryption \ 1057 * | bit 3: 0x0 - perform tx classification / queuing \ 1058 * | 0x1 - don't perform tx classification; \ 1059 * | insert the frame into the "misc" \ 1060 * | tx queue \ 1061 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1062 * | not appended to the HTT message \ 1063 * | 0x1 - Copy-Engine Classification Results \ 1064 * | appended to the HTT message. \ 1065 * | See the above specification of the \ 1066 * | CE classification results location. \ 1067 */ \ 1068 pkt_subtype: 5, \ 1069 \ 1070 /* pkt_type - \ 1071 * General specification of the tx frame contents. \ 1072 * The htt_pkt_type enum should be used to specify and check the \ 1073 * value of this field. \ 1074 */ \ 1075 pkt_type: 3, \ 1076 \ 1077 /* vdev_id - \ 1078 * ID for the vdev that is sending this tx frame. \ 1079 * For certain non-standard packet types, e.g. pkt_type == raw \ 1080 * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ 1081 * This field is used primarily for determining where to queue \ 1082 * broadcast and multicast frames. \ 1083 */ \ 1084 vdev_id: 6, \ 1085 /* ext_tid - \ 1086 * The extended traffic ID. \ 1087 * If the TID is unknown, the extended TID is set to \ 1088 * HTT_TX_EXT_TID_INVALID. \ 1089 * If the tx frame is QoS data, then the extended TID has the 0-15 \ 1090 * value of the QoS TID. \ 1091 * If the tx frame is non-QoS data, then the extended TID is set to \ 1092 * HTT_TX_EXT_TID_NON_QOS. \ 1093 * If the tx frame is multicast or broadcast, then the extended TID \ 1094 * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ 1095 */ \ 1096 ext_tid: 5, \ 1097 \ 1098 /* postponed - \ 1099 * This flag indicates whether the tx frame has been downloaded to \ 1100 * the target before but discarded by the target, and now is being \ 1101 * downloaded again; or if this is a new frame that is being \ 1102 * downloaded for the first time. \ 1103 * This flag allows the target to determine the correct order for \ 1104 * transmitting new vs. old frames. \ 1105 * value: 0 -> new frame, 1 -> re-send of a previously sent frame \ 1106 * This flag only applies to HL systems, since in LL systems, \ 1107 * the tx flow control is handled entirely within the target. \ 1108 */ \ 1109 postponed: 1, \ 1110 \ 1111 /* extension - \ 1112 * This flag indicates whether a HTT tx MSDU extension descriptor \ 1113 * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \ 1114 * \ 1115 * 0x0 - no extension MSDU descriptor is present \ 1116 * 0x1 - an extension MSDU descriptor immediately follows the \ 1117 * regular MSDU descriptor \ 1118 */ \ 1119 extension: 1, \ 1120 \ 1121 /* cksum_offload - \ 1122 * This flag indicates whether checksum offload is enabled or not \ 1123 * for this frame. Target FW use this flag to turn on HW checksumming \ 1124 * 0x0 - No checksum offload \ 1125 * 0x1 - L3 header checksum only \ 1126 * 0x2 - L4 checksum only \ 1127 * 0x3 - L3 header checksum + L4 checksum \ 1128 */ \ 1129 cksum_offload: 2, \ 1130 \ 1131 /* tx_comp_req - \ 1132 * This flag indicates whether Tx Completion \ 1133 * from fw is required or not. \ 1134 * This flag is only relevant if tx completion is not \ 1135 * universally enabled. \ 1136 * For all LL systems, tx completion is mandatory, \ 1137 * so this flag will be irrelevant. \ 1138 * For HL systems tx completion is optional, but HL systems in which \ 1139 * the bus throughput exceeds the WLAN throughput will \ 1140 * probably want to always use tx completion, and thus \ 1141 * would not check this flag. \ 1142 * This flag is required when tx completions are not used universally, \ 1143 * but are still required for certain tx frames for which \ 1144 * an OTA delivery acknowledgment is needed by the host. \ 1145 * In practice, this would be for HL systems in which the \ 1146 * bus throughput is less than the WLAN throughput. \ 1147 * \ 1148 * 0x0 - Tx Completion Indication from Fw not required \ 1149 * 0x1 - Tx Completion Indication from Fw is required \ 1150 */ \ 1151 tx_compl_req: 1; \ 1152 \ 1153 \ 1154 /* DWORD 1: MSDU length and ID */ \ 1155 A_UINT32 \ 1156 len: 16, /* MSDU length, in bytes */ \ 1157 id: 16; /* MSDU ID used to identify the MSDU to the host, \ 1158 * and this id is used to calculate fragmentation \ 1159 * descriptor pointer inside the target based on \ 1160 * the base address, configured inside the target. \ 1161 */ \ 1162 \ 1163 /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ 1164 /* frags_desc_ptr - \ 1165 * The fragmentation descriptor pointer tells the HW's MAC DMA \ 1166 * where the tx frame's fragments reside in memory. \ 1167 * This field only applies to LL systems, since in HL systems the \ 1168 * (degenerate single-fragment) fragmentation descriptor is created \ 1169 * within the target. \ 1170 */ \ 1171 _paddr__frags_desc_ptr_; \ 1172 \ 1173 /* DWORD 3 (or 4): peerid, chanfreq */ \ 1174 /* \ 1175 * Peer ID : Target can use this value to know which peer-id packet \ 1176 * destined to. \ 1177 * It's intended to be specified by host in case of NAWDS. \ 1178 */ \ 1179 A_UINT16 peerid; \ 1180 \ 1181 /* \ 1182 * Channel frequency: This identifies the desired channel \ 1183 * frequency (in mhz) for tx frames. This is used by FW to help \ 1184 * determine when it is safe to transmit or drop frames for \ 1185 * off-channel operation. \ 1186 * The default value of zero indicates to FW that the corresponding \ 1187 * VDEV's home channel (if there is one) is the desired channel \ 1188 * frequency. \ 1189 */ \ 1190 A_UINT16 chanfreq; \ 1191 \ 1192 /* Reason reserved is commented is increasing the htt structure size \ 1193 * leads to some weird issues. \ 1194 * A_UINT32 reserved_dword3_bits0_31; \ 1195 */ \ 1196 } POSTPACK 1197 /* define a htt_tx_msdu_desc32_t type */ 1198 TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); 1199 /* define a htt_tx_msdu_desc64_t type */ 1200 TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); 1201 /* 1202 * Make htt_tx_msdu_desc_t be an alias for either 1203 * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t 1204 */ 1205 #if HTT_PADDR64 1206 #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t 1207 #else 1208 #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t 1209 #endif 1210 1211 /* decriptor information for Management frame*/ 1212 /* 1213 * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT. 1214 * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t. 1215 */ 1216 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 1217 extern A_UINT32 mgmt_hdr_len; 1218 PREPACK struct htt_mgmt_tx_desc_t { 1219 A_UINT32 msg_type; 1220 #if HTT_PADDR64 1221 A_UINT64 frag_paddr; /* DMAble address of the data */ 1222 #else 1223 A_UINT32 frag_paddr; /* DMAble address of the data */ 1224 #endif 1225 A_UINT32 desc_id; /* returned to host during completion 1226 * to free the meory*/ 1227 A_UINT32 len; /* Fragment length */ 1228 A_UINT32 vdev_id; /* virtual device ID*/ 1229 A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ 1230 } POSTPACK; 1231 1232 PREPACK struct htt_mgmt_tx_compl_ind { 1233 A_UINT32 desc_id; 1234 A_UINT32 status; 1235 } POSTPACK; 1236 1237 /* 1238 * This SDU header size comes from the summation of the following: 1239 * 1. Max of: 1240 * a. Native WiFi header, for native WiFi frames: 24 bytes 1241 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4) 1242 * b. 802.11 header, for raw frames: 36 bytes 1243 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4, 1244 * QoS header, HT header) 1245 * c. 802.3 header, for ethernet frames: 14 bytes 1246 * (destination address, source address, ethertype / length) 1247 * 2. Max of: 1248 * a. IPv4 header, up through the DiffServ Code Point: 2 bytes 1249 * b. IPv6 header, up through the Traffic Class: 2 bytes 1250 * 3. 802.1Q VLAN header: 4 bytes 1251 * 4. LLC/SNAP header: 8 bytes 1252 */ 1253 #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30 1254 #define HTT_TX_HDR_SIZE_802_11_RAW 36 1255 #define HTT_TX_HDR_SIZE_ETHERNET 14 1256 1257 #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW 1258 A_COMPILE_TIME_ASSERT( 1259 htt_encap_hdr_size_max_check_nwifi, 1260 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI); 1261 A_COMPILE_TIME_ASSERT( 1262 htt_encap_hdr_size_max_check_enet, 1263 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET); 1264 1265 #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ 1266 #define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ 1267 1268 #define HTT_TX_HDR_SIZE_802_1Q 4 1269 #define HTT_TX_HDR_SIZE_LLC_SNAP 8 1270 1271 1272 #define HTT_COMMON_TX_FRM_HDR_LEN \ 1273 (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ 1274 HTT_TX_HDR_SIZE_802_1Q + \ 1275 HTT_TX_HDR_SIZE_LLC_SNAP) 1276 1277 #define HTT_HL_TX_FRM_HDR_LEN \ 1278 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) 1279 1280 #define HTT_LL_TX_FRM_HDR_LEN \ 1281 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) 1282 1283 #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) 1284 1285 /* dword 0 */ 1286 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0 1287 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0 1288 #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00 1289 #define HTT_TX_DESC_PKT_SUBTYPE_S 8 1290 1291 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0 1292 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0 1293 #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400 1294 #define HTT_TX_DESC_NO_ENCRYPT_S 10 1295 1296 #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0 1297 #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0 1298 #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000 1299 #define HTT_TX_DESC_PKT_TYPE_S 13 1300 1301 #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0 1302 #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0 1303 #define HTT_TX_DESC_VDEV_ID_M 0x003f0000 1304 #define HTT_TX_DESC_VDEV_ID_S 16 1305 1306 #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0 1307 #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0 1308 #define HTT_TX_DESC_EXT_TID_M 0x07c00000 1309 #define HTT_TX_DESC_EXT_TID_S 22 1310 1311 #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0 1312 #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0 1313 #define HTT_TX_DESC_POSTPONED_M 0x08000000 1314 #define HTT_TX_DESC_POSTPONED_S 27 1315 1316 #define HTT_TX_DESC_EXTENSION_OFFSET_BYTE 0 1317 #define HTT_TX_DESC_EXTENSION_OFFSET_DWORD 0 1318 #define HTT_TX_DESC_EXTENSION_M 0x10000000 1319 #define HTT_TX_DESC_EXTENSION_S 28 1320 1321 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0 1322 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0 1323 #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000 1324 #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29 1325 1326 #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0 1327 #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0 1328 #define HTT_TX_DESC_TX_COMP_M 0x80000000 1329 #define HTT_TX_DESC_TX_COMP_S 31 1330 1331 /* dword 1 */ 1332 #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4 1333 #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1 1334 #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff 1335 #define HTT_TX_DESC_FRM_LEN_S 0 1336 1337 #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4 1338 #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1 1339 #define HTT_TX_DESC_FRM_ID_M 0xffff0000 1340 #define HTT_TX_DESC_FRM_ID_S 16 1341 1342 /* dword 2 */ 1343 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8 1344 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2 1345 /* for systems using 64-bit format for bus addresses */ 1346 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff 1347 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0 1348 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff 1349 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0 1350 /* for systems using 32-bit format for bus addresses */ 1351 #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff 1352 #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0 1353 1354 /* dword 3 */ 1355 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 1356 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 1357 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ 1358 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) 1359 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ 1360 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) 1361 1362 #if HTT_PADDR64 1363 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 1364 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 1365 #else 1366 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 1367 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 1368 #endif 1369 1370 #define HTT_TX_DESC_PEER_ID_M 0x0000ffff 1371 #define HTT_TX_DESC_PEER_ID_S 0 1372 /* 1373 * TEMPORARY: 1374 * The original definitions for the PEER_ID fields contained typos 1375 * (with _DESC_PADDR appended to this PEER_ID field name). 1376 * Retain deprecated original names for PEER_ID fields until all code that 1377 * refers to them has been updated. 1378 */ 1379 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ 1380 HTT_TX_DESC_PEER_ID_OFFSET_BYTES 1381 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ 1382 HTT_TX_DESC_PEER_ID_OFFSET_DWORD 1383 #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ 1384 HTT_TX_DESC_PEER_ID_M 1385 #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ 1386 HTT_TX_DESC_PEER_ID_S 1387 1388 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */ 1389 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */ 1390 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ 1391 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) 1392 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ 1393 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) 1394 1395 #if HTT_PADDR64 1396 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 1397 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 1398 #else 1399 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 1400 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 1401 #endif 1402 1403 #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 1404 #define HTT_TX_DESC_CHAN_FREQ_S 16 1405 1406 #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ 1407 (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) 1408 #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ 1409 do { \ 1410 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ 1411 ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ 1412 } while (0) 1413 1414 #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ 1415 (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) 1416 #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ 1417 do { \ 1418 HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ 1419 ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ 1420 } while (0) 1421 1422 #define HTT_TX_DESC_PKT_TYPE_GET(_var) \ 1423 (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) 1424 #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ 1425 do { \ 1426 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ 1427 ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ 1428 } while (0) 1429 1430 #define HTT_TX_DESC_VDEV_ID_GET(_var) \ 1431 (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) 1432 #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ 1433 do { \ 1434 HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ 1435 ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ 1436 } while (0) 1437 1438 #define HTT_TX_DESC_EXT_TID_GET(_var) \ 1439 (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) 1440 #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ 1441 do { \ 1442 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ 1443 ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ 1444 } while (0) 1445 1446 #define HTT_TX_DESC_POSTPONED_GET(_var) \ 1447 (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) 1448 #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ 1449 do { \ 1450 HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ 1451 ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ 1452 } while (0) 1453 1454 #define HTT_TX_DESC_EXTENSION_GET(_var) \ 1455 (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S) 1456 #define HTT_TX_DESC_EXTENSION_SET(_var, _val) \ 1457 do { \ 1458 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \ 1459 ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \ 1460 } while (0) 1461 1462 #define HTT_TX_DESC_FRM_LEN_GET(_var) \ 1463 (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) 1464 #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ 1465 do { \ 1466 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ 1467 ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ 1468 } while (0) 1469 1470 #define HTT_TX_DESC_FRM_ID_GET(_var) \ 1471 (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) 1472 #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ 1473 do { \ 1474 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ 1475 ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ 1476 } while (0) 1477 1478 #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ 1479 (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) 1480 #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ 1481 do { \ 1482 HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ 1483 ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ 1484 } while (0) 1485 1486 #define HTT_TX_DESC_TX_COMP_GET(_var) \ 1487 (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) 1488 #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ 1489 do { \ 1490 HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ 1491 ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ 1492 } while (0) 1493 1494 #define HTT_TX_DESC_PEER_ID_GET(_var) \ 1495 (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) 1496 #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ 1497 do { \ 1498 HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ 1499 ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ 1500 } while (0) 1501 1502 #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ 1503 (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) 1504 #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ 1505 do { \ 1506 HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ 1507 ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ 1508 } while (0) 1509 1510 1511 /* enums used in the HTT tx MSDU extension descriptor */ 1512 enum { 1513 htt_tx_guard_interval_regular = 0, 1514 htt_tx_guard_interval_short = 1, 1515 }; 1516 1517 enum { 1518 htt_tx_preamble_type_ofdm = 0, 1519 htt_tx_preamble_type_cck = 1, 1520 htt_tx_preamble_type_ht = 2, 1521 htt_tx_preamble_type_vht = 3, 1522 }; 1523 1524 enum { 1525 htt_tx_bandwidth_5MHz = 0, 1526 htt_tx_bandwidth_10MHz = 1, 1527 htt_tx_bandwidth_20MHz = 2, 1528 htt_tx_bandwidth_40MHz = 3, 1529 htt_tx_bandwidth_80MHz = 4, 1530 htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ 1531 }; 1532 1533 /** 1534 * @brief HTT tx MSDU extension descriptor 1535 * @details 1536 * If the target supports HTT tx MSDU extension descriptors, the host has 1537 * the option of appending the following struct following the regular 1538 * HTT tx MSDU descriptor (and setting the "extension" flag in the regular 1539 * HTT tx MSDU descriptor, to show that the extension descriptor is present). 1540 * The HTT tx MSDU extension descriptors allows the host to provide detailed 1541 * tx specs for each frame. 1542 */ 1543 PREPACK struct htt_tx_msdu_desc_ext_t { 1544 /* DWORD 0: flags */ 1545 A_UINT32 1546 valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */ 1547 valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */ 1548 valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */ 1549 valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/ 1550 valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */ 1551 valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */ 1552 valid_retries: 1, /* bit 6: if set, tx retries spec is valid */ 1553 valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */ 1554 valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/ 1555 is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */ 1556 reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */ 1557 1558 /* DWORD 1: tx power, tx rate, tx BW */ 1559 A_UINT32 1560 /* pwr - 1561 * Specify what power the tx frame needs to be transmitted at. 1562 * The power a signed (two's complement) value is in units of 0.5 dBm. 1563 * The value needs to be appropriately sign-extended when extracting 1564 * the value from the message and storing it in a variable that is 1565 * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro 1566 * automatically handles this sign-extension.) 1567 * If the transmission uses multiple tx chains, this power spec is 1568 * the total transmit power, assuming incoherent combination of 1569 * per-chain power to produce the total power. 1570 */ 1571 pwr: 8, 1572 1573 /* mcs_mask - 1574 * Specify the allowable values for MCS index (modulation and coding) 1575 * to use for transmitting the frame. 1576 * 1577 * For HT / VHT preamble types, this mask directly corresponds to 1578 * the HT or VHT MCS indices that are allowed. For each bit N set 1579 * within the mask, MCS index N is allowed for transmitting the frame. 1580 * For legacy CCK and OFDM rates, separate bits are provided for CCK 1581 * rates versus OFDM rates, so the host has the option of specifying 1582 * that the target must transmit the frame with CCK or OFDM rates 1583 * (not HT or VHT), but leaving the decision to the target whether 1584 * to use CCK or OFDM. 1585 * 1586 * For CCK and OFDM, the bits within this mask are interpreted as 1587 * follows: 1588 * bit 0 -> CCK 1 Mbps rate is allowed 1589 * bit 1 -> CCK 2 Mbps rate is allowed 1590 * bit 2 -> CCK 5.5 Mbps rate is allowed 1591 * bit 3 -> CCK 11 Mbps rate is allowed 1592 * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed 1593 * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed 1594 * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed 1595 * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed 1596 * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed 1597 * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed 1598 * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed 1599 * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed 1600 * 1601 * The MCS index specification needs to be compatible with the 1602 * bandwidth mask specification. For example, a MCS index == 9 1603 * specification is inconsistent with a preamble type == VHT, 1604 * Nss == 1, and channel bandwidth == 20 MHz. 1605 * 1606 * Furthermore, the host has only a limited ability to specify to 1607 * the target to select from HT + legacy rates, or VHT + legacy rates, 1608 * since this mcs_mask can specify either HT/VHT rates or legacy rates. 1609 */ 1610 mcs_mask: 12, 1611 1612 /* nss_mask - 1613 * Specify which numbers of spatial streams (MIMO factor) are permitted. 1614 * Each bit in this mask corresponds to a Nss value: 1615 * bit 0: if set, Nss = 1 (non-MIMO) is permitted 1616 * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted 1617 * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted 1618 * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted 1619 * The values in the Nss mask must be suitable for the recipient, e.g. 1620 * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a 1621 * recipient which only supports 2x2 MIMO. 1622 */ 1623 nss_mask: 4, 1624 1625 /* guard_interval - 1626 * Specify a htt_tx_guard_interval enum value to indicate whether 1627 * the transmission should use a regular guard interval or a 1628 * short guard interval. 1629 */ 1630 guard_interval: 1, 1631 1632 /* preamble_type_mask - 1633 * Specify which preamble types (CCK, OFDM, HT, VHT) the target 1634 * may choose from for transmitting this frame. 1635 * The bits in this mask correspond to the values in the 1636 * htt_tx_preamble_type enum. For example, to allow the target 1637 * to transmit the frame as either CCK or OFDM, this field would 1638 * be set to 1639 * (1 << htt_tx_preamble_type_ofdm) | 1640 * (1 << htt_tx_preamble_type_cck) 1641 */ 1642 preamble_type_mask: 4, 1643 1644 reserved1_31_29: 3; /* unused, set to 0x0 */ 1645 1646 /* DWORD 2: tx chain mask, tx retries */ 1647 A_UINT32 1648 /* chain_mask - specify which chains to transmit from */ 1649 chain_mask: 4, 1650 1651 /* retry_limit - 1652 * Specify the maximum number of transmissions, including the 1653 * initial transmission, to attempt before giving up if no ack 1654 * is received. 1655 * If the tx rate is specified, then all retries shall use the 1656 * same rate as the initial transmission. 1657 * If no tx rate is specified, the target can choose whether to 1658 * retain the original rate during the retransmissions, or to 1659 * fall back to a more robust rate. 1660 */ 1661 retry_limit: 4, 1662 1663 /* bandwidth_mask - 1664 * Specify what channel widths may be used for the transmission. 1665 * A value of zero indicates "don't care" - the target may choose 1666 * the transmission bandwidth. 1667 * The bits within this mask correspond to the htt_tx_bandwidth 1668 * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. 1669 * The bandwidth_mask must be consistent with the preamble_type_mask 1670 * and mcs_mask specs, if they are provided. For example, 80 MHz and 1671 * 160 MHz can only be enabled in the mask if preamble_type == VHT. 1672 */ 1673 bandwidth_mask: 6, 1674 1675 reserved2_31_14: 18; /* unused, set to 0x0 */ 1676 1677 /* DWORD 3: tx expiry time (TSF) LSBs */ 1678 A_UINT32 expire_tsf_lo; 1679 1680 /* DWORD 4: tx expiry time (TSF) MSBs */ 1681 A_UINT32 expire_tsf_hi; 1682 1683 A_UINT32 reserved_for_future_expansion_set_to_zero[3]; 1684 } POSTPACK; 1685 1686 /* DWORD 0 */ 1687 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001 1688 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0 1689 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 1690 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1 1691 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 1692 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2 1693 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008 1694 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3 1695 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010 1696 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4 1697 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020 1698 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5 1699 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040 1700 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6 1701 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080 1702 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7 1703 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100 1704 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8 1705 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200 1706 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9 1707 1708 /* DWORD 1 */ 1709 #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff 1710 #define HTT_TX_MSDU_EXT_DESC_PWR_S 0 1711 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00 1712 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8 1713 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000 1714 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20 1715 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000 1716 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24 1717 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000 1718 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25 1719 1720 /* DWORD 2 */ 1721 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f 1722 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0 1723 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0 1724 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4 1725 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00 1726 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8 1727 1728 1729 /* DWORD 0 */ 1730 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ 1731 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 1732 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) 1733 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 1734 do { \ 1735 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ 1736 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ 1737 } while (0) 1738 1739 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 1740 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ 1741 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) 1742 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 1743 do { \ 1744 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ 1745 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ 1746 } while (0) 1747 1748 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 1749 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 1750 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) 1751 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 1752 do { \ 1753 HTT_CHECK_SET_VAL( \ 1754 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 1755 ((_var) |= ((_val) \ 1756 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 1757 } while (0) 1758 1759 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ 1760 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \ 1761 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) 1762 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1763 do { \ 1764 HTT_CHECK_SET_VAL( \ 1765 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ 1766 ((_var) |= ((_val) \ 1767 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ 1768 } while (0) 1769 1770 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 1771 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 1772 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) 1773 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 1774 do { \ 1775 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 1776 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 1777 } while (0) 1778 1779 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ 1780 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ 1781 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) 1782 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 1783 do { \ 1784 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ 1785 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ 1786 } while (0) 1787 1788 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ 1789 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ 1790 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) 1791 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ 1792 do { \ 1793 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ 1794 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ 1795 } while (0) 1796 1797 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 1798 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 1799 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) 1800 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 1801 do { \ 1802 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 1803 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 1804 } while (0) 1805 1806 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ 1807 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ 1808 HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) 1809 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 1810 do { \ 1811 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ 1812 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ 1813 } while (0) 1814 1815 1816 /* DWORD 1 */ 1817 #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ 1818 (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ 1819 HTT_TX_MSDU_EXT_DESC_PWR_S) 1820 #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ 1821 (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ 1822 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) 1823 #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ 1824 ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ 1825 HTT_TX_MSDU_EXT_DESC_PWR_M) 1826 1827 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ 1828 (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ 1829 HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) 1830 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ 1831 do { \ 1832 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ 1833 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ 1834 } while (0) 1835 1836 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ 1837 (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ 1838 HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) 1839 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ 1840 do { \ 1841 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ 1842 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ 1843 } while (0) 1844 1845 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ 1846 (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ 1847 HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) 1848 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ 1849 do { \ 1850 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ 1851 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ 1852 } while (0) 1853 1854 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ 1855 (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ 1856 HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) 1857 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1858 do { \ 1859 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \ 1860 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ 1861 } while (0) 1862 1863 1864 /* DWORD 2 */ 1865 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ 1866 (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ 1867 HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) 1868 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ 1869 do { \ 1870 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ 1871 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ 1872 } while (0) 1873 1874 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ 1875 (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ 1876 HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) 1877 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ 1878 do { \ 1879 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ 1880 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ 1881 } while (0) 1882 1883 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ 1884 (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ 1885 HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) 1886 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ 1887 do { \ 1888 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ 1889 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ 1890 } while (0) 1891 1892 1893 typedef enum { 1894 HTT_11AX_HE_LTF_SUBTYPE_1X, 1895 HTT_11AX_HE_LTF_SUBTYPE_2X, 1896 HTT_11AX_HE_LTF_SUBTYPE_4X, 1897 } htt_11ax_ltf_subtype_t; 1898 1899 typedef enum { 1900 HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM, 1901 HTT_TX_MSDU_EXT2_DESC_PREAM_CCK, 1902 HTT_TX_MSDU_EXT2_DESC_PREAM_HT , 1903 HTT_TX_MSDU_EXT2_DESC_PREAM_VHT, 1904 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU, 1905 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU, 1906 } htt_tx_ext2_preamble_type_t; 1907 1908 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_M 0x00000001 1909 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_S 0 1910 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_M 0x00000002 1911 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_S 1 1912 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_M 0x00000004 1913 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_S 2 1914 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_M 0x00000008 1915 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_S 3 1916 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_M 0x00000010 1917 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_S 4 1918 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_M 0x00000020 1919 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_S 5 1920 1921 /** 1922 * @brief HTT tx MSDU extension descriptor v2 1923 * @details 1924 * In Lithium, if htt_tx_tcl_metadata->valid_htt_ext is set, this structure 1925 * is received as tcl_exit_base->host_meta_info in firmware. 1926 * Also there is no htt_tx_msdu_desc_t in Lithium since most of those fields 1927 * are already part of tcl_exit_base. 1928 */ 1929 PREPACK struct htt_tx_msdu_desc_ext2_t { 1930 /* DWORD 0: flags */ 1931 A_UINT32 1932 valid_pwr : 1, /* if set, tx pwr spec is valid */ 1933 valid_mcs_mask : 1, /* if set, tx MCS mask is valid */ 1934 valid_nss_mask : 1, /* if set, tx Nss mask is valid */ 1935 valid_preamble_type : 1, /* if set, tx preamble spec is valid */ 1936 valid_retries : 1, /* if set, tx retries spec is valid */ 1937 valid_bw_info : 1, /* if set, tx dyn_bw and bw_mask are valid */ 1938 valid_guard_interval : 1, /* if set, tx guard intv spec is valid */ 1939 valid_chainmask : 1, /* if set, tx chainmask is valid */ 1940 valid_encrypt_type : 1, /* if set, encrypt type is valid */ 1941 valid_key_flags : 1, /* if set, key flags is valid */ 1942 valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */ 1943 valid_chanfreq : 1, /* if set, chanfreq is valid */ 1944 is_dsrc : 1, /* if set, MSDU is a DSRC frame */ 1945 guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */ 1946 encrypt_type : 2, /* 0 = NO_ENCRYPT, 1947 1 = ENCRYPT, 1948 2 ~ 3 - Reserved */ 1949 /* retry_limit - 1950 * Specify the maximum number of transmissions, including the 1951 * initial transmission, to attempt before giving up if no ack 1952 * is received. 1953 * If the tx rate is specified, then all retries shall use the 1954 * same rate as the initial transmission. 1955 * If no tx rate is specified, the target can choose whether to 1956 * retain the original rate during the retransmissions, or to 1957 * fall back to a more robust rate. 1958 */ 1959 retry_limit : 4, 1960 use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation. 1961 * Valid only for 11ax preamble types HE_SU 1962 * and HE_EXT_SU 1963 */ 1964 ltf_subtype_11ax : 2, /* Takes enum values of htt_11ax_ltf_subtype_t 1965 * Valid only for 11ax preamble types HE_SU 1966 * and HE_EXT_SU 1967 */ 1968 dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */ 1969 bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw). 1970 * (Bit mask of 5, 10, 20, 40, 80, 160Mhz. 1971 * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.) 1972 */ 1973 host_tx_desc_pool : 1; /* If set, Firmware allocates tx_descriptors 1974 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead 1975 * of WAL_BUFFERID_TX_TCL_DATA_EXP. 1976 * Use cases: 1977 * Any time firmware uses TQM-BYPASS for Data 1978 * TID, firmware expect host to set this bit. 1979 */ 1980 1981 /* DWORD 1: tx power, tx rate */ 1982 A_UINT32 1983 power : 8, /* unit of the power field is 0.5 dbm 1984 * similar to pwr field in htt_tx_msdu_desc_ext_t 1985 * signed value ranging from -64dbm to 63.5 dbm 1986 */ 1987 mcs_mask : 12, /* mcs bit mask of 0 ~ 11 1988 * Setting more than one MCS isn't currently 1989 * supported by the target (but is supported 1990 * in the interface in case in the future 1991 * the target supports specifications of 1992 * a limited set of MCS values. 1993 */ 1994 nss_mask : 8, /* Nss bit mask 0 ~ 7 1995 * Setting more than one Nss isn't currently 1996 * supported by the target (but is supported 1997 * in the interface in case in the future 1998 * the target supports specifications of 1999 * a limited set of Nss values. 2000 */ 2001 pream_type : 3, /* Takes enum values of htt_tx_ext2_preamble_type_t */ 2002 update_peer_cache : 1; /* When set these custom values will be 2003 * used for all packets, until the next 2004 * update via this ext header. 2005 * This is to make sure not all packets 2006 * need to include this header. 2007 */ 2008 2009 /* DWORD 2: tx chain mask, tx retries */ 2010 A_UINT32 2011 /* chain_mask - specify which chains to transmit from */ 2012 chain_mask : 8, 2013 2014 key_flags : 8, /* Key Index and related flags - used in mesh mode 2015 * TODO: Update Enum values for key_flags 2016 */ 2017 2018 /* 2019 * Channel frequency: This identifies the desired channel 2020 * frequency (in MHz) for tx frames. This is used by FW to help 2021 * determine when it is safe to transmit or drop frames for 2022 * off-channel operation. 2023 * The default value of zero indicates to FW that the corresponding 2024 * VDEV's home channel (if there is one) is the desired channel 2025 * frequency. 2026 */ 2027 chanfreq : 16; 2028 2029 /* DWORD 3: tx expiry time (TSF) LSBs */ 2030 A_UINT32 expire_tsf_lo; 2031 2032 /* DWORD 4: tx expiry time (TSF) MSBs */ 2033 A_UINT32 expire_tsf_hi; 2034 2035 /* DWORD 5: flags to control routing / processing of the MSDU */ 2036 A_UINT32 2037 /* learning_frame 2038 * When this flag is set, this frame will be dropped by FW 2039 * rather than being enqueued to the Transmit Queue Manager (TQM) HW. 2040 */ 2041 learning_frame : 1, 2042 /* send_as_standalone 2043 * This will indicate if the msdu needs to be sent as a singleton PPDU, 2044 * i.e. with no A-MSDU or A-MPDU aggregation. 2045 * The scope is extended to other use-cases. 2046 */ 2047 send_as_standalone : 1, 2048 /* is_host_opaque_valid 2049 * Host should set this bit to 1 if the host_opaque_cookie is populated 2050 * with valid information. 2051 */ 2052 is_host_opaque_valid : 1, 2053 traffic_end_indication: 1, 2054 rsvd0 : 28; 2055 2056 /* DWORD 6 : Host opaque cookie for special frames */ 2057 A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */ 2058 rsvd1 : 16; 2059 2060 /* 2061 * This structure can be expanded further up to 40 bytes 2062 * by adding further DWORDs as needed. 2063 */ 2064 } POSTPACK; 2065 2066 /* DWORD 0 */ 2067 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_M 0x00000001 2068 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S 0 2069 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 2070 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S 1 2071 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 2072 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S 2 2073 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M 0x00000008 2074 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S 3 2075 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M 0x00000010 2076 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S 4 2077 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M 0x00000020 2078 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S 5 2079 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000040 2080 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S 6 2081 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000080 2082 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S 7 2083 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M 0x00000100 2084 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S 8 2085 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M 0x00000200 2086 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S 9 2087 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000400 2088 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S 10 2089 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M 0x00000800 2090 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S 11 2091 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M 0x00001000 2092 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S 12 2093 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M 0x00006000 2094 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S 13 2095 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M 0x00018000 2096 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S 15 2097 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M 0x001e0000 2098 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S 17 2099 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M 0x00200000 2100 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S 21 2101 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M 0x00c00000 2102 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S 22 2103 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_M 0x01000000 2104 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_S 24 2105 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_M 0x7e000000 2106 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_S 25 2107 2108 /* DWORD 1 */ 2109 #define HTT_TX_MSDU_EXT2_DESC_PWR_M 0x000000ff 2110 #define HTT_TX_MSDU_EXT2_DESC_PWR_S 0 2111 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M 0x000fff00 2112 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S 8 2113 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M 0x0ff00000 2114 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S 20 2115 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_M 0x70000000 2116 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_S 28 2117 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_M 0x80000000 2118 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_S 31 2119 2120 /* DWORD 2 */ 2121 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M 0x000000ff 2122 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S 0 2123 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_M 0x0000ff00 2124 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S 8 2125 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_M 0xffff0000 2126 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_S 16 2127 2128 /* DWORD 5 */ 2129 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M 0x00000001 2130 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S 0 2131 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M 0x00000002 2132 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S 1 2133 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M 0x00000004 2134 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S 2 2135 2136 /* DWORD 6 */ 2137 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M 0x0000FFFF 2138 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S 0 2139 2140 2141 /* DWORD 0 */ 2142 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \ 2143 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 2144 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S) 2145 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 2146 do { \ 2147 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \ 2148 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)); \ 2149 } while (0) 2150 2151 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 2152 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \ 2153 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S) 2154 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 2155 do { \ 2156 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK, _val); \ 2157 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \ 2158 } while (0) 2159 2160 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_GET(_var) \ 2161 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \ 2162 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S) 2163 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_SET(_var, _val) \ 2164 do { \ 2165 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK, _val); \ 2166 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \ 2167 } while (0) 2168 2169 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_GET(_var) \ 2170 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \ 2171 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S) 2172 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_SET(_var, _val) \ 2173 do { \ 2174 HTT_CHECK_SET_VAL( \ 2175 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \ 2176 ((_var) |= ((_val) \ 2177 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \ 2178 } while (0) 2179 2180 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_GET(_var) \ 2181 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \ 2182 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S) 2183 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 2184 do { \ 2185 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES, _val); \ 2186 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \ 2187 } while (0) 2188 2189 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \ 2190 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \ 2191 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S) 2192 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \ 2193 do { \ 2194 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO, _val); \ 2195 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \ 2196 } while (0) 2197 2198 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 2199 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 2200 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S) 2201 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 2202 do { \ 2203 HTT_CHECK_SET_VAL( \ 2204 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 2205 ((_var) |= ((_val) \ 2206 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 2207 } while (0) 2208 2209 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 2210 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 2211 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S) 2212 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 2213 do { \ 2214 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 2215 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 2216 } while (0) 2217 2218 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \ 2219 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \ 2220 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S) 2221 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_SET(_var, _val) \ 2222 do { \ 2223 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \ 2224 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\ 2225 } while (0) 2226 2227 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \ 2228 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \ 2229 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S) 2230 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \ 2231 do { \ 2232 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \ 2233 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\ 2234 } while (0) 2235 2236 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 2237 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 2238 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S) 2239 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 2240 do { \ 2241 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 2242 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 2243 } while (0) 2244 2245 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \ 2246 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \ 2247 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S) 2248 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \ 2249 do { \ 2250 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ, _val); \ 2251 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)); \ 2252 } while (0) 2253 2254 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \ 2255 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \ 2256 HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S) 2257 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 2258 do { \ 2259 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val); \ 2260 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)); \ 2261 } while (0) 2262 2263 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \ 2264 (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \ 2265 HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S) 2266 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \ 2267 do { \ 2268 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val); \ 2269 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)); \ 2270 } while (0) 2271 2272 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \ 2273 (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \ 2274 HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S) 2275 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \ 2276 do { \ 2277 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val); \ 2278 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)); \ 2279 } while (0) 2280 2281 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \ 2282 (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \ 2283 HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S) 2284 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \ 2285 do { \ 2286 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val); \ 2287 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)); \ 2288 } while (0) 2289 2290 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \ 2291 (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \ 2292 HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S) 2293 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \ 2294 do { \ 2295 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val); \ 2296 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)); \ 2297 } while (0) 2298 2299 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \ 2300 (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \ 2301 HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S) 2302 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \ 2303 do { \ 2304 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX, _val); \ 2305 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \ 2306 } while (0) 2307 2308 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \ 2309 (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \ 2310 HTT_TX_MSDU_EXT2_DESC_BW_MASK_S) 2311 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \ 2312 do { \ 2313 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \ 2314 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)); \ 2315 } while (0) 2316 2317 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \ 2318 (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \ 2319 HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S) 2320 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \ 2321 do { \ 2322 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val); \ 2323 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \ 2324 } while (0) 2325 2326 /* DWORD 1 */ 2327 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \ 2328 (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \ 2329 HTT_TX_MSDU_EXT2_DESC_PWR_S) 2330 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \ 2331 (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \ 2332 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR)) 2333 #define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \ 2334 ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \ 2335 HTT_TX_MSDU_EXT2_DESC_PWR_M) 2336 2337 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \ 2338 (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \ 2339 HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S) 2340 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \ 2341 do { \ 2342 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val); \ 2343 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)); \ 2344 } while (0) 2345 2346 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \ 2347 (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \ 2348 HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S) 2349 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \ 2350 do { \ 2351 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val); \ 2352 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)); \ 2353 } while (0) 2354 2355 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \ 2356 (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \ 2357 HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S) 2358 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \ 2359 do { \ 2360 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val); \ 2361 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)); \ 2362 } while (0) 2363 2364 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_GET(_var) \ 2365 (((_var) & HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_M) >> \ 2366 HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S) 2367 #define HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_SET(_var, _val) \ 2368 do { \ 2369 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE, _val); \ 2370 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S)); \ 2371 } while (0) 2372 2373 /* DWORD 2 */ 2374 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \ 2375 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \ 2376 HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S) 2377 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \ 2378 do { \ 2379 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val); \ 2380 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)); \ 2381 } while (0) 2382 2383 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \ 2384 (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \ 2385 HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S) 2386 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \ 2387 do { \ 2388 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val); \ 2389 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)); \ 2390 } while (0) 2391 2392 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \ 2393 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \ 2394 HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S) 2395 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \ 2396 do { \ 2397 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val); \ 2398 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)); \ 2399 } while (0) 2400 2401 /* DWORD 5 */ 2402 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_GET(_var) \ 2403 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M) >> \ 2404 HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S) 2405 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_SET(_var, _val) \ 2406 do { \ 2407 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME, _val); \ 2408 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)); \ 2409 } while (0) 2410 2411 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_GET(_var) \ 2412 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M) >> \ 2413 HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S) 2414 2415 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET(_var, _val) \ 2416 do { \ 2417 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE, _val); \ 2418 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)); \ 2419 } while (0) 2420 2421 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_GET(_var) \ 2422 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M) >> \ 2423 HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S) 2424 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET(_var, _val) \ 2425 do { \ 2426 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID, _val); \ 2427 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)); \ 2428 } while (0) 2429 2430 /* DWORD 6 */ 2431 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_GET(_var) \ 2432 (((_var) & HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M) >> \ 2433 HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S) 2434 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET(_var, _val) \ 2435 do { \ 2436 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE, _val); \ 2437 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)); \ 2438 } while (0) 2439 2440 2441 typedef enum { 2442 HTT_TCL_METADATA_TYPE_PEER_BASED = 0, 2443 HTT_TCL_METADATA_TYPE_VDEV_BASED = 1, 2444 } htt_tcl_metadata_type; 2445 2446 /** 2447 * @brief HTT TCL command number format 2448 * @details 2449 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2450 * available to firmware as tcl_exit_base->tcl_status_number. 2451 * For regular / multicast packets host will send vdev and mac id and for 2452 * NAWDS packets, host will send peer id. 2453 * A_UINT32 is used to avoid endianness conversion problems. 2454 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2455 */ 2456 2457 typedef struct { 2458 A_UINT32 2459 type: 1, /* vdev_id based or peer_id based */ 2460 rsvd: 31; 2461 } htt_tx_tcl_vdev_or_peer_t; 2462 2463 typedef struct { 2464 A_UINT32 2465 type: 1, /* vdev_id based or peer_id based */ 2466 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2467 vdev_id: 8, 2468 pdev_id: 2, 2469 host_inspected:1, 2470 rsvd: 19; 2471 } htt_tx_tcl_vdev_metadata; 2472 2473 typedef struct { 2474 A_UINT32 2475 type: 1, /* vdev_id based or peer_id based */ 2476 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2477 peer_id: 14, 2478 rsvd: 16; 2479 } htt_tx_tcl_peer_metadata; 2480 2481 PREPACK struct htt_tx_tcl_metadata { 2482 union { 2483 htt_tx_tcl_vdev_or_peer_t vdev_or_peer; 2484 htt_tx_tcl_vdev_metadata vdev_meta; 2485 htt_tx_tcl_peer_metadata peer_meta; 2486 }; 2487 } POSTPACK; 2488 2489 /* DWORD 0 */ 2490 #define HTT_TX_TCL_METADATA_TYPE_M 0x00000001 2491 #define HTT_TX_TCL_METADATA_TYPE_S 0 2492 #define HTT_TX_TCL_METADATA_VALID_HTT_M 0x00000002 2493 #define HTT_TX_TCL_METADATA_VALID_HTT_S 1 2494 2495 /* VDEV metadata */ 2496 #define HTT_TX_TCL_METADATA_VDEV_ID_M 0x000003fc 2497 #define HTT_TX_TCL_METADATA_VDEV_ID_S 2 2498 #define HTT_TX_TCL_METADATA_PDEV_ID_M 0x00000c00 2499 #define HTT_TX_TCL_METADATA_PDEV_ID_S 10 2500 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_M 0x00001000 2501 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_S 12 2502 2503 /* PEER metadata */ 2504 #define HTT_TX_TCL_METADATA_PEER_ID_M 0x0000fffc 2505 #define HTT_TX_TCL_METADATA_PEER_ID_S 2 2506 2507 #define HTT_TX_TCL_METADATA_TYPE_GET(_var) \ 2508 (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \ 2509 HTT_TX_TCL_METADATA_TYPE_S) 2510 #define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \ 2511 do { \ 2512 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val); \ 2513 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S)); \ 2514 } while (0) 2515 2516 #define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \ 2517 (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \ 2518 HTT_TX_TCL_METADATA_VALID_HTT_S) 2519 #define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \ 2520 do { \ 2521 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val); \ 2522 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S)); \ 2523 } while (0) 2524 2525 #define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \ 2526 (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \ 2527 HTT_TX_TCL_METADATA_VDEV_ID_S) 2528 #define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \ 2529 do { \ 2530 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val); \ 2531 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S)); \ 2532 } while (0) 2533 2534 #define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \ 2535 (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \ 2536 HTT_TX_TCL_METADATA_PDEV_ID_S) 2537 #define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \ 2538 do { \ 2539 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val); \ 2540 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S)); \ 2541 } while (0) 2542 2543 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_GET(_var) \ 2544 (((_var) & HTT_TX_TCL_METADATA_HOST_INSPECTED_M) >> \ 2545 HTT_TX_TCL_METADATA_HOST_INSPECTED_S) 2546 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \ 2547 do { \ 2548 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_HOST_INSPECTED, _val); \ 2549 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_HOST_INSPECTED_S)); \ 2550 } while (0) 2551 2552 #define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \ 2553 (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \ 2554 HTT_TX_TCL_METADATA_PEER_ID_S) 2555 #define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \ 2556 do { \ 2557 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val); \ 2558 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S)); \ 2559 } while (0) 2560 2561 /*------------------------------------------------------------------ 2562 * V2 Version of TCL Data Command 2563 * V2 Version to support peer_id, vdev_id, svc_class_id and 2564 * MLO global_seq all flavours of TCL Data Cmd. 2565 *-----------------------------------------------------------------*/ 2566 2567 typedef enum { 2568 HTT_TCL_METADATA_V2_TYPE_PEER_BASED = 0, 2569 HTT_TCL_METADATA_V2_TYPE_VDEV_BASED = 1, 2570 HTT_TCL_METADATA_V2_TYPE_SVC_ID_BASED = 2, 2571 HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED = 3, 2572 } htt_tcl_metadata_type_v2; 2573 2574 /** 2575 * @brief HTT TCL command number format 2576 * @details 2577 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2578 * available to firmware as tcl_exit_base->tcl_status_number. 2579 * A_UINT32 is used to avoid endianness conversion problems. 2580 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2581 */ 2582 typedef struct { 2583 A_UINT32 2584 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2585 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2586 vdev_id: 8, 2587 pdev_id: 2, 2588 host_inspected:1, 2589 rsvd: 2, 2590 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2591 } htt_tx_tcl_vdev_metadata_v2; 2592 2593 typedef struct { 2594 A_UINT32 2595 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2596 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2597 peer_id: 13, 2598 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2599 } htt_tx_tcl_peer_metadata_v2; 2600 2601 typedef struct { 2602 A_UINT32 2603 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2604 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2605 svc_class_id: 8, 2606 ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ 2607 rsvd: 2, 2608 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2609 } htt_tx_tcl_svc_class_id_metadata; 2610 2611 typedef struct { 2612 A_UINT32 2613 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2614 host_inspected: 1, 2615 global_seq_no: 12, 2616 rsvd: 1, 2617 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2618 } htt_tx_tcl_global_seq_metadata; 2619 2620 PREPACK struct htt_tx_tcl_metadata_v2 { 2621 union { 2622 htt_tx_tcl_vdev_metadata_v2 vdev_meta_v2; 2623 htt_tx_tcl_peer_metadata_v2 peer_meta_v2; 2624 htt_tx_tcl_svc_class_id_metadata svc_class_id_meta; 2625 htt_tx_tcl_global_seq_metadata global_seq_meta; 2626 }; 2627 } POSTPACK; 2628 2629 /* DWORD 0 */ 2630 #define HTT_TX_TCL_METADATA_TYPE_V2_M 0x00000003 2631 #define HTT_TX_TCL_METADATA_TYPE_V2_S 0 2632 2633 /* Valid htt ext for V2 tcl data cmd used by VDEV, PEER and SVC_ID meta */ 2634 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M 0x00000004 2635 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S 2 2636 2637 /* VDEV V2 metadata */ 2638 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_M 0x000007f8 2639 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_S 3 2640 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_M 0x00001800 2641 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_S 11 2642 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M 0x00002000 2643 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S 13 2644 2645 /* PEER V2 metadata */ 2646 #define HTT_TX_TCL_METADATA_V2_PEER_ID_M 0x0000fff8 2647 #define HTT_TX_TCL_METADATA_V2_PEER_ID_S 3 2648 2649 /* SVC_CLASS_ID metadata */ 2650 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_M 0x000007f8 2651 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_S 3 2652 2653 /* Global Seq no metadata */ 2654 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M 0x00000004 2655 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S 2 2656 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M 0x00007ff8 2657 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S 3 2658 2659 2660 /*----- Get and Set V2 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */ 2661 #define HTT_TX_TCL_METADATA_TYPE_V2_GET(_var) \ 2662 (((_var) & HTT_TX_TCL_METADATA_TYPE_V2_M) >> \ 2663 HTT_TX_TCL_METADATA_TYPE_V2_S) 2664 #define HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val) \ 2665 do { \ 2666 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V2, _val); \ 2667 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V2_S)); \ 2668 } while (0) 2669 2670 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_GET(_var) \ 2671 (((_var) & HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M) >> \ 2672 HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S) 2673 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val) \ 2674 do { \ 2675 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID, _val); \ 2676 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S)); \ 2677 } while (0) 2678 2679 /*----- Get and Set V2 type field in Vdev meta fields ----*/ 2680 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_GET(_var) \ 2681 (((_var) & HTT_TX_TCL_METADATA_V2_VDEV_ID_M) >> \ 2682 HTT_TX_TCL_METADATA_V2_VDEV_ID_S) 2683 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val) \ 2684 do { \ 2685 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VDEV_ID, _val); \ 2686 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VDEV_ID_S)); \ 2687 } while (0) 2688 2689 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_GET(_var) \ 2690 (((_var) & HTT_TX_TCL_METADATA_V2_PDEV_ID_M) >> \ 2691 HTT_TX_TCL_METADATA_V2_PDEV_ID_S) 2692 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val) \ 2693 do { \ 2694 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PDEV_ID, _val); \ 2695 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PDEV_ID_S)); \ 2696 } while (0) 2697 2698 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_GET(_var) \ 2699 (((_var) & HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M) >> \ 2700 HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S) 2701 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val) \ 2702 do { \ 2703 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_HOST_INSPECTED, _val); \ 2704 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S)); \ 2705 } while (0) 2706 2707 /*----- Get and Set V2 type field in Peer meta fields ----*/ 2708 #define HTT_TX_TCL_METADATA_V2_PEER_ID_GET(_var) \ 2709 (((_var) & HTT_TX_TCL_METADATA_V2_PEER_ID_M) >> \ 2710 HTT_TX_TCL_METADATA_V2_PEER_ID_S) 2711 #define HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val) \ 2712 do { \ 2713 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PEER_ID, _val); \ 2714 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PEER_ID_S)); \ 2715 } while (0) 2716 2717 /*----- Get and Set V2 type field in Service Class fields ----*/ 2718 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_GET(_var) \ 2719 (((_var) & HTT_TX_TCL_METADATA_SVC_CLASS_ID_M) >> \ 2720 HTT_TX_TCL_METADATA_SVC_CLASS_ID_S) 2721 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_SET(_var, _val) \ 2722 do { \ 2723 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_SVC_CLASS_ID, _val); \ 2724 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_SVC_CLASS_ID_S)); \ 2725 } while (0) 2726 2727 /*----- Get and Set V2 type field in Global sequence fields ----*/ 2728 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_GET(_var) \ 2729 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M) >> \ 2730 HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S) 2731 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \ 2732 do { \ 2733 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED, _val); \ 2734 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S)); \ 2735 } while (0) 2736 2737 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_GET(_var) \ 2738 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M) >> \ 2739 HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S) 2740 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(_var, _val) \ 2741 do { \ 2742 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_NO, _val); \ 2743 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S)); \ 2744 } while (0) 2745 2746 /*------------------------------------------------------------------ 2747 * End V2 Version of TCL Data Command 2748 *-----------------------------------------------------------------*/ 2749 2750 typedef enum { 2751 HTT_TX_FW2WBM_TX_STATUS_OK, 2752 HTT_TX_FW2WBM_TX_STATUS_DROP, 2753 HTT_TX_FW2WBM_TX_STATUS_TTL, 2754 HTT_TX_FW2WBM_TX_STATUS_REINJECT, 2755 HTT_TX_FW2WBM_TX_STATUS_INSPECT, 2756 HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, 2757 HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH, 2758 2759 HTT_TX_FW2WBM_TX_STATUS_MAX 2760 } htt_tx_fw2wbm_tx_status_t; 2761 2762 typedef enum { 2763 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, /* deprecated */ 2764 HTT_TX_FW2WBM_REINJECT_REASON_RAW_ENCAP_EXP /* current */ = 2765 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, 2766 HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP, 2767 HTT_TX_FW2WBM_REINJECT_REASON_MCAST, 2768 HTT_TX_FW2WBM_REINJECT_REASON_ARP, 2769 HTT_TX_FW2WBM_REINJECT_REASON_DHCP, 2770 HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL, 2771 HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST, 2772 HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT, 2773 2774 HTT_TX_FW2WBM_REINJECT_REASON_MAX, 2775 } htt_tx_fw2wbm_reinject_reason_t; 2776 2777 /** 2778 * @brief HTT TX WBM Completion from firmware to host 2779 * @details 2780 * This structure is passed from firmware to host overlaid on wbm_release_ring 2781 * DWORD 3 and 4 for software based completions (Exception frames and 2782 * TQM bypass frames) 2783 * For software based completions, wbm_release_ring->release_source_module will 2784 * be set to release_source_fw 2785 */ 2786 PREPACK struct htt_tx_wbm_completion { 2787 A_UINT32 2788 sch_cmd_id: 24, 2789 exception_frame: 1, /* If set, this packet was queued via exception path */ 2790 rsvd0_31_25: 7; 2791 2792 A_UINT32 2793 ack_frame_rssi: 8, /* If this frame is removed as the result of the 2794 * reception of an ACK or BA, this field indicates 2795 * the RSSI of the received ACK or BA frame. 2796 * When the frame is removed as result of a direct 2797 * remove command from the SW, this field is set 2798 * to 0x0 (which is never a valid value when real 2799 * RSSI is available). 2800 * Units: dB w.r.t noise floor 2801 */ 2802 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2803 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2804 rsvd1_31_16: 16; 2805 } POSTPACK; 2806 2807 /* DWORD 0 */ 2808 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M 0x00ffffff 2809 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S 0 2810 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_M 0x01000000 2811 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_S 24 2812 2813 /* DWORD 1 */ 2814 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_M 0x000000ff 2815 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_S 0 2816 #define HTT_TX_WBM_COMPLETION_TX_STATUS_M 0x00000f00 2817 #define HTT_TX_WBM_COMPLETION_TX_STATUS_S 8 2818 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_M 0x0000f000 2819 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_S 12 2820 2821 /* DWORD 0 */ 2822 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \ 2823 (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \ 2824 HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S) 2825 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \ 2826 do { \ 2827 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val); \ 2828 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)); \ 2829 } while (0) 2830 2831 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \ 2832 (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \ 2833 HTT_TX_WBM_COMPLETION_EXP_FRAME_S) 2834 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \ 2835 do { \ 2836 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val); \ 2837 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S)); \ 2838 } while (0) 2839 2840 /* DWORD 1 */ 2841 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \ 2842 (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \ 2843 HTT_TX_WBM_COMPLETION_ACK_RSSI_S) 2844 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \ 2845 do { \ 2846 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val); \ 2847 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S)); \ 2848 } while (0) 2849 2850 #define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \ 2851 (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \ 2852 HTT_TX_WBM_COMPLETION_TX_STATUS_S) 2853 #define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \ 2854 do { \ 2855 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val); \ 2856 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S)); \ 2857 } while (0) 2858 2859 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \ 2860 (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \ 2861 HTT_TX_WBM_COMPLETION_REINJECT_REASON_S) 2862 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \ 2863 do { \ 2864 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val); \ 2865 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \ 2866 } while (0) 2867 2868 /** 2869 * @brief HTT TX WBM Completion from firmware to host 2870 * @details 2871 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 2872 * (WBM) offload HW. 2873 * This structure is passed from firmware to host overlaid on wbm_release_ring 2874 * For software based completions, release_source_module will 2875 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 2876 * struct wbm_release_ring and then switch to this after looking at 2877 * release_source_module. 2878 */ 2879 PREPACK struct htt_tx_wbm_completion_v2 { 2880 A_UINT32 2881 used_by_hw0; /* Refer to struct wbm_release_ring */ 2882 A_UINT32 2883 used_by_hw1; /* Refer to struct wbm_release_ring */ 2884 A_UINT32 2885 used_by_hw2: 9, /* Refer to struct wbm_release_ring */ 2886 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2887 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2888 exception_frame: 1, 2889 transmit_count: 7, /* Refer to struct wbm_release_ring */ 2890 rsvd0: 5, /* For future use */ 2891 used_by_hw4: 1, /* wbm_internal_error bit being used by HW */ 2892 rsvd1: 1; /* For future use */ 2893 A_UINT32 2894 data0: 32; /* data0,1 and 2 changes based on tx_status type 2895 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 2896 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 2897 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 2898 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 2899 */ 2900 A_UINT32 2901 data1: 32; 2902 A_UINT32 2903 data2: 32; 2904 A_UINT32 2905 used_by_hw3; /* Refer to struct wbm_release_ring */ 2906 } POSTPACK; 2907 2908 /* DWORD 1, 2 and part of 3 are accessed via HW header files */ 2909 /* DWORD 3 */ 2910 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M 0x00001e00 2911 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S 9 2912 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M 0x0001e000 2913 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13 2914 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000 2915 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17 2916 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000 2917 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18 2918 2919 /* DWORD 3 */ 2920 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \ 2921 (((_var) & HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M) >> \ 2922 HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S) 2923 2924 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_SET(_var, _val) \ 2925 do { \ 2926 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TX_STATUS, _val); \ 2927 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S)); \ 2928 } while (0) 2929 2930 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(_var) \ 2931 (((_var) & HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M) >> \ 2932 HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S) 2933 2934 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_SET(_var, _val) \ 2935 do { \ 2936 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON, _val); \ 2937 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S)); \ 2938 } while (0) 2939 2940 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_GET(_var) \ 2941 (((_var) & HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M) >> \ 2942 HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S) 2943 2944 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_SET(_var, _val) \ 2945 do { \ 2946 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_EXP_FRAME, _val); \ 2947 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \ 2948 } while (0) 2949 2950 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \ 2951 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \ 2952 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S) 2953 2954 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \ 2955 do { \ 2956 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \ 2957 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \ 2958 } while (0) 2959 2960 /** 2961 * @brief HTT TX WBM Completion from firmware to host (V3) 2962 * @details 2963 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 2964 * (WBM) offload HW. 2965 * This structure is passed from firmware to host overlaid on wbm_release_ring 2966 * For software based completions, release_source_module will 2967 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 2968 * struct wbm_release_ring and then switch to this after looking at 2969 * release_source_module. 2970 * Due to overlap with WBM block, htt_tx_wbm_completion_v3 will be used 2971 * by new generations of targets. 2972 */ 2973 PREPACK struct htt_tx_wbm_completion_v3 { 2974 A_UINT32 2975 used_by_hw0; /* Refer to struct wbm_release_ring */ 2976 A_UINT32 2977 used_by_hw1; /* Refer to struct wbm_release_ring */ 2978 A_UINT32 2979 used_by_hw2: 13, /* Refer to struct wbm_release_ring */ 2980 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2981 used_by_hw3: 15; 2982 A_UINT32 2983 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2984 exception_frame: 1, 2985 transmit_count: 7, /* Refer to struct wbm_release_ring */ 2986 rsvd0: 20; /* For future use */ 2987 A_UINT32 2988 data0: 32; /* data0,1 and 2 changes based on tx_status type 2989 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 2990 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 2991 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 2992 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 2993 */ 2994 A_UINT32 2995 data1: 32; 2996 A_UINT32 2997 data2: 32; 2998 A_UINT32 2999 rsvd1: 20, 3000 used_by_hw4: 12; /* Refer to struct wbm_release_ring */ 3001 } POSTPACK; 3002 3003 /* DWORD 3 */ 3004 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000 3005 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13 3006 3007 /* DWORD 4 */ 3008 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F 3009 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0 3010 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010 3011 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4 3012 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0 3013 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5 3014 3015 3016 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \ 3017 (((_var) & HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M) >> \ 3018 HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S) 3019 3020 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_SET(_var, _val) \ 3021 do { \ 3022 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TX_STATUS, _val); \ 3023 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)); \ 3024 } while (0) 3025 3026 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(_var) \ 3027 (((_var) & HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M) >> \ 3028 HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S) 3029 3030 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_SET(_var, _val) \ 3031 do { \ 3032 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON, _val); \ 3033 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)); \ 3034 } while (0) 3035 3036 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_GET(_var) \ 3037 (((_var) & HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M) >> \ 3038 HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S) 3039 3040 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_SET(_var, _val) \ 3041 do { \ 3042 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_EXP_FRAME, _val); \ 3043 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \ 3044 } while (0) 3045 3046 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \ 3047 (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \ 3048 HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S) 3049 3050 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \ 3051 do { \ 3052 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \ 3053 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \ 3054 } while (0) 3055 3056 3057 typedef enum { 3058 TX_FRAME_TYPE_UNDEFINED = 0, 3059 TX_FRAME_TYPE_EAPOL = 1, 3060 } htt_tx_wbm_status_frame_type; 3061 3062 /** 3063 * @brief HTT TX WBM transmit status from firmware to host 3064 * @details 3065 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3066 * (WBM) offload HW. 3067 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3068 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 3069 * or HTT_TX_FW2WBM_TX_STATUS_TTL 3070 */ 3071 PREPACK struct htt_tx_wbm_transmit_status { 3072 A_UINT32 3073 sch_cmd_id: 24, 3074 ack_frame_rssi: 8; /* If this frame is removed as the result of the 3075 * reception of an ACK or BA, this field indicates 3076 * the RSSI of the received ACK or BA frame. 3077 * When the frame is removed as result of a direct 3078 * remove command from the SW, this field is set 3079 * to 0x0 (which is never a valid value when real 3080 * RSSI is available). 3081 * Units: dB w.r.t noise floor 3082 */ 3083 A_UINT32 3084 sw_peer_id: 16, 3085 tid_num: 5, 3086 valid: 1, /* If this "valid" flag is set, the sw_peer_id 3087 * and tid_num fields contain valid data. 3088 * If this "valid" flag is not set, the 3089 * sw_peer_id and tid_num fields must be ignored. 3090 */ 3091 mcast: 1, 3092 mcast_valid: 1, /* If this "mcast_valid" is set, the mcast field 3093 * contains valid data. 3094 */ 3095 frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */ 3096 transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the 3097 * transmit_count field in struct 3098 * htt_tx_wbm_completion_vx has valid data. 3099 */ 3100 reserved: 3; 3101 A_UINT32 3102 ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast 3103 * packets in the wbm completion path 3104 */ 3105 } POSTPACK; 3106 3107 /* DWORD 4 */ 3108 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M 0x00ffffff 3109 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S 0 3110 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M 0xff000000 3111 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S 24 3112 3113 /* DWORD 5 */ 3114 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M 0x0000ffff 3115 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S 0 3116 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_M 0x001f0000 3117 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_S 16 3118 #define HTT_TX_WBM_COMPLETION_V2_VALID_M 0x00200000 3119 #define HTT_TX_WBM_COMPLETION_V2_VALID_S 21 3120 #define HTT_TX_WBM_COMPLETION_V2_MCAST_M 0x00400000 3121 #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22 3122 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000 3123 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23 3124 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000 3125 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24 3126 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000 3127 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28 3128 3129 /* DWORD 4 */ 3130 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \ 3131 (((_var) & HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M) >> \ 3132 HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S) 3133 3134 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_SET(_var, _val) \ 3135 do { \ 3136 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID, _val); \ 3137 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S)); \ 3138 } while (0) 3139 3140 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var) \ 3141 (((_var) & HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M) >> \ 3142 HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S) 3143 3144 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_SET(_var, _val) \ 3145 do { \ 3146 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI, _val); \ 3147 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)); \ 3148 } while (0) 3149 3150 /* DWORD 5 */ 3151 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var) \ 3152 (((_var) & HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M) >> \ 3153 HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S) 3154 3155 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_SET(_var, _val) \ 3156 do { \ 3157 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID, _val); \ 3158 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)); \ 3159 } while (0) 3160 3161 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var) \ 3162 (((_var) & HTT_TX_WBM_COMPLETION_V2_TID_NUM_M) >> \ 3163 HTT_TX_WBM_COMPLETION_V2_TID_NUM_S) 3164 3165 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_SET(_var, _val) \ 3166 do { \ 3167 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TID_NUM, _val); \ 3168 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)); \ 3169 } while (0) 3170 3171 #define HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var) \ 3172 (((_var) & HTT_TX_WBM_COMPLETION_V2_VALID_M) >> \ 3173 HTT_TX_WBM_COMPLETION_V2_VALID_S) 3174 3175 #define HTT_TX_WBM_COMPLETION_V2_VALID_SET(_var, _val) \ 3176 do { \ 3177 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VALID, _val); \ 3178 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VALID_S)); \ 3179 } while (0) 3180 3181 #define HTT_TX_WBM_COMPLETION_V2_MCAST_GET(_var) \ 3182 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_M) >> \ 3183 HTT_TX_WBM_COMPLETION_V2_MCAST_S) 3184 3185 #define HTT_TX_WBM_COMPLETION_V2_MCAST_SET(_var, _val) \ 3186 do { \ 3187 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST, _val); \ 3188 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_S)); \ 3189 } while (0) 3190 3191 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_GET(_var) \ 3192 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M) >> \ 3193 HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S) 3194 3195 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_SET(_var, _val) \ 3196 do { \ 3197 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3198 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \ 3199 } while (0) 3200 3201 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \ 3202 (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \ 3203 HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S) 3204 3205 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \ 3206 do { \ 3207 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \ 3208 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \ 3209 3210 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \ 3211 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \ 3212 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S) 3213 3214 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \ 3215 do { \ 3216 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3217 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \ 3218 } while (0) 3219 3220 3221 /** 3222 * @brief HTT TX WBM reinject status from firmware to host 3223 * @details 3224 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3225 * (WBM) offload HW. 3226 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3227 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT. 3228 */ 3229 PREPACK struct htt_tx_wbm_reinject_status { 3230 A_UINT32 3231 sw_peer_id : 16, 3232 data_length : 16; 3233 A_UINT32 3234 tid : 5, 3235 msduq_idx : 4, 3236 reserved1 : 23; 3237 A_UINT32 3238 reserved2: 32; 3239 } POSTPACK; 3240 3241 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_M 0x0000ffff 3242 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_S 0 3243 #define HTT_TX_WBM_REINJECT_DATA_LEN_M 0xffff0000 3244 #define HTT_TX_WBM_REINJECT_DATA_LEN_S 16 3245 3246 #define HTT_TX_WBM_REINJECT_TID_M 0x0000001f 3247 #define HTT_TX_WBM_REINJECT_TID_S 0 3248 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_M 0x000001e0 3249 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_S 5 3250 3251 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_GET(_var)\ 3252 (((_var) & HTT_TX_WBM_REINJECT_SW_PEER_ID_M) >>\ 3253 HTT_TX_WBM_REINJECT_SW_PEER_ID_S)\ 3254 3255 #define HTT_TX_WBM_REINJECT_SW_PEER_ID_SET(_var, _val)\ 3256 do {\ 3257 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_SW_PEER_ID, _val); \ 3258 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_SW_PEER_ID_S));\ 3259 } while(0) 3260 3261 #define HTT_TX_WBM_REINJECT_DATA_LEN_GET(_var)\ 3262 (((_var) & HTT_TX_WBM_REINJECT_DATA_LEN_M) >>\ 3263 HTT_TX_WBM_REINJECT_DATA_LEN_S)\ 3264 3265 #define HTT_TX_WBM_REINJECT_DATA_LEN_SET(_var, _val)\ 3266 do {\ 3267 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_DATA_LEN, _val); \ 3268 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_DATA_LEN_S));\ 3269 } while(0) 3270 3271 #define HTT_TX_WBM_REINJECT_TID_GET(_var)\ 3272 (((_var) & HTT_TX_WBM_REINJECT_TID_M) >>\ 3273 HTT_TX_WBM_REINJECT_TID_S)\ 3274 3275 #define HTT_TX_WBM_REINJECT_TID_SET(_var, _val)\ 3276 do {\ 3277 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_TID, _val); \ 3278 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_TID_S));\ 3279 } while(0) 3280 3281 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_GET(_var)\ 3282 (((_var) & HTT_TX_WBM_REINJECT_MSDUQ_ID_M) >>\ 3283 HTT_TX_WBM_REINJECT_MSDUQ_ID_S)\ 3284 3285 #define HTT_TX_WBM_REINJECT_MSDUQ_ID_SET(_var, _val)\ 3286 do {\ 3287 HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_MSDUQ_ID, _val); \ 3288 ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_MSDUQ_ID_S));\ 3289 } while(0) 3290 3291 3292 3293 3294 3295 3296 3297 /** 3298 * @brief HTT TX WBM multicast echo check notification from firmware to host 3299 * @details 3300 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3301 * (WBM) offload HW. 3302 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3303 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY. 3304 * FW sends SA addresses to host for all multicast/broadcast packets received on 3305 * STA side. 3306 */ 3307 PREPACK struct htt_tx_wbm_mec_addr_notify { 3308 A_UINT32 3309 mec_sa_addr_31_0; 3310 A_UINT32 3311 mec_sa_addr_47_32: 16, 3312 sa_ast_index: 16; 3313 A_UINT32 3314 vdev_id: 8, 3315 reserved0: 24; 3316 3317 } POSTPACK; 3318 3319 /* DWORD 4 - mec_sa_addr_31_0 */ 3320 /* DWORD 5 */ 3321 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M 0x0000ffff 3322 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S 0 3323 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M 0xffff0000 3324 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S 16 3325 3326 /* DWORD 6 */ 3327 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M 0x000000ff 3328 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S 0 3329 3330 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_GET(_var) \ 3331 (((_var) & HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M) >> \ 3332 HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S) 3333 3334 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_SET(_var, _val) \ 3335 do { \ 3336 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32, _val); \ 3337 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S)); \ 3338 } while (0) 3339 3340 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_GET(_var) \ 3341 (((_var) & HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M) >> \ 3342 HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S) 3343 3344 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_SET(_var, _val) \ 3345 do { \ 3346 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX, _val); \ 3347 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S)); \ 3348 } while (0) 3349 3350 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var) \ 3351 (((_var) & HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M) >> \ 3352 HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S) 3353 3354 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_SET(_var, _val) \ 3355 do { \ 3356 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VDEV_ID, _val); \ 3357 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S)); \ 3358 } while (0) 3359 3360 typedef enum { 3361 TX_FLOW_PRIORITY_BE, 3362 TX_FLOW_PRIORITY_HIGH, 3363 TX_FLOW_PRIORITY_LOW, 3364 } htt_tx_flow_priority_t; 3365 3366 typedef enum { 3367 TX_FLOW_LATENCY_SENSITIVE, 3368 TX_FLOW_LATENCY_INSENSITIVE, 3369 } htt_tx_flow_latency_t; 3370 3371 typedef enum { 3372 TX_FLOW_BEST_EFFORT_TRAFFIC, 3373 TX_FLOW_INTERACTIVE_TRAFFIC, 3374 TX_FLOW_PERIODIC_TRAFFIC, 3375 TX_FLOW_BURSTY_TRAFFIC, 3376 TX_FLOW_OVER_SUBSCRIBED_TRAFFIC, 3377 } htt_tx_flow_traffic_pattern_t; 3378 3379 /** 3380 * @brief HTT TX Flow search metadata format 3381 * @details 3382 * Host will set this metadata in flow table's flow search entry along with 3383 * to_tqm_if_m0_fw. It indicates to forward the first MSDU to both the 3384 * firmware and TQM ring if the flow search entry wins. 3385 * This metadata is available to firmware in that first MSDU's 3386 * tcl_exit_base->meta_data_fse. Firmware uses this metadata to map a new flow 3387 * to one of the available flows for specific tid and returns the tqm flow 3388 * pointer as part of htt_tx_map_flow_info message. 3389 */ 3390 PREPACK struct htt_tx_flow_metadata { 3391 A_UINT32 3392 rsvd0_1_0: 2, 3393 tid: 4, 3394 priority: 3, /* Takes enum values of htt_tx_flow_priority_t */ 3395 traffic_pattern: 3, /* Takes enum values of htt_tx_flow_traffic_pattern_t */ 3396 tid_override: 1, /* If set, tid field in this struct is the final tid. 3397 * Else choose final tid based on latency, priority. 3398 */ 3399 dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */ 3400 latency_sensitive: 2, /* Takes enum values of htt_tx_flow_latency_t */ 3401 host_flow_identifier: 16; /* Used by host to map flow metadata with flow entry */ 3402 } POSTPACK; 3403 3404 /* DWORD 0 */ 3405 #define HTT_TX_FLOW_METADATA_TID_M 0x0000003c 3406 #define HTT_TX_FLOW_METADATA_TID_S 2 3407 #define HTT_TX_FLOW_METADATA_PRIORITY_M 0x000001c0 3408 #define HTT_TX_FLOW_METADATA_PRIORITY_S 6 3409 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M 0x00000e00 3410 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S 9 3411 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_M 0x00001000 3412 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_S 12 3413 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M 0x00002000 3414 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S 13 3415 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M 0x0000c000 3416 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S 14 3417 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M 0xffff0000 3418 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S 16 3419 3420 /* DWORD 0 */ 3421 #define HTT_TX_FLOW_METADATA_TID_GET(_var) \ 3422 (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \ 3423 HTT_TX_FLOW_METADATA_TID_S) 3424 #define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \ 3425 do { \ 3426 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \ 3427 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \ 3428 } while (0) 3429 3430 #define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \ 3431 (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \ 3432 HTT_TX_FLOW_METADATA_PRIORITY_S) 3433 #define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \ 3434 do { \ 3435 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \ 3436 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S)); \ 3437 } while (0) 3438 3439 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \ 3440 (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \ 3441 HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S) 3442 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \ 3443 do { \ 3444 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val); \ 3445 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)); \ 3446 } while (0) 3447 3448 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \ 3449 (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \ 3450 HTT_TX_FLOW_METADATA_TID_OVERRIDE_S) 3451 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \ 3452 do { \ 3453 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val); \ 3454 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)); \ 3455 } while (0) 3456 3457 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \ 3458 (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \ 3459 HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S) 3460 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \ 3461 do { \ 3462 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val); \ 3463 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)); \ 3464 } while (0) 3465 3466 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \ 3467 (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \ 3468 HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S) 3469 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \ 3470 do { \ 3471 HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \ 3472 ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S)); \ 3473 } while (0) 3474 3475 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \ 3476 (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \ 3477 HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S) 3478 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \ 3479 do { \ 3480 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val); \ 3481 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)); \ 3482 } while (0) 3483 3484 3485 /** 3486 * @brief host -> target ADD WDS Entry 3487 * 3488 * MSG_TYPE => HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY 3489 * 3490 * @brief host -> target DELETE WDS Entry 3491 * 3492 * MSG_TYPE => HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY 3493 * 3494 * @details 3495 * HTT wds entry from source port learning 3496 * Host will learn wds entries from rx and send this message to firmware 3497 * to enable firmware to configure/delete AST entries for wds clients. 3498 * Firmware creates Source address's AST entry with Transmit MAC's peer_id 3499 * and when SA's entry is deleted, firmware removes this AST entry 3500 * 3501 * The message would appear as follows: 3502 * 3503 * |31 30|29 |17 16|15 8|7 0| 3504 * |----------------+----------------+----------------+----------------| 3505 * | rsvd0 |PDVID| vdev_id | msg_type | 3506 * |-------------------------------------------------------------------| 3507 * | sa_addr_31_0 | 3508 * |-------------------------------------------------------------------| 3509 * | | ta_peer_id | sa_addr_47_32 | 3510 * |-------------------------------------------------------------------| 3511 * Where PDVID = pdev_id 3512 * 3513 * The message is interpreted as follows: 3514 * 3515 * dword0 - b'0:7 - msg_type: This will be set to 3516 * 0xd (HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY) or 3517 * 0xe (HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY) 3518 * 3519 * dword0 - b'8:15 - vdev_id 3520 * 3521 * dword0 - b'16:17 - pdev_id 3522 * 3523 * dword0 - b'18:31 - rsvd10: Reserved for future use 3524 * 3525 * dword1 - b'0:31 - sa_addr_31_0: Lower 32 bits of source mac address 3526 * 3527 * dword2 - b'0:15 - sa_addr_47_32: Upper 16 bits of source mac address 3528 * 3529 * dword2 - b'16:19 - ta_peer_id: peer id of Transmit MAC 3530 */ 3531 3532 PREPACK struct htt_wds_entry { 3533 A_UINT32 3534 msg_type: 8, 3535 vdev_id: 8, 3536 pdev_id: 2, 3537 rsvd0: 14; 3538 A_UINT32 sa_addr_31_0; 3539 A_UINT32 3540 sa_addr_47_32: 16, 3541 ta_peer_id: 14, 3542 rsvd2: 2; 3543 } POSTPACK; 3544 3545 /* DWORD 0 */ 3546 #define HTT_WDS_ENTRY_VDEV_ID_M 0x0000ff00 3547 #define HTT_WDS_ENTRY_VDEV_ID_S 8 3548 #define HTT_WDS_ENTRY_PDEV_ID_M 0x00030000 3549 #define HTT_WDS_ENTRY_PDEV_ID_S 16 3550 3551 /* DWORD 2 */ 3552 #define HTT_WDS_ENTRY_SA_ADDR_47_32_M 0x0000ffff 3553 #define HTT_WDS_ENTRY_SA_ADDR_47_32_S 0 3554 #define HTT_WDS_ENTRY_TA_PEER_ID_M 0x3fff0000 3555 #define HTT_WDS_ENTRY_TA_PEER_ID_S 16 3556 3557 /* DWORD 0 */ 3558 #define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \ 3559 (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \ 3560 HTT_WDS_ENTRY_VDEV_ID_S) 3561 #define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \ 3562 do { \ 3563 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \ 3564 ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \ 3565 } while (0) 3566 3567 #define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \ 3568 (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \ 3569 HTT_WDS_ENTRY_PDEV_ID_S) 3570 #define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \ 3571 do { \ 3572 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \ 3573 ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \ 3574 } while (0) 3575 3576 /* DWORD 2 */ 3577 #define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \ 3578 (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \ 3579 HTT_WDS_ENTRY_SA_ADDR_47_32_S) 3580 #define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \ 3581 do { \ 3582 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \ 3583 ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \ 3584 } while (0) 3585 3586 #define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \ 3587 (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \ 3588 HTT_WDS_ENTRY_TA_PEER_ID_S) 3589 #define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \ 3590 do { \ 3591 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \ 3592 ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \ 3593 } while (0) 3594 3595 3596 /** 3597 * @brief MAC DMA rx ring setup specification 3598 * 3599 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_CFG 3600 * 3601 * @details 3602 * To allow for dynamic rx ring reconfiguration and to avoid race 3603 * conditions, the host SW never directly programs the MAC DMA rx ring(s) 3604 * it uses. Instead, it sends this message to the target, indicating how 3605 * the rx ring used by the host should be set up and maintained. 3606 * The message consists of a 4-octet header followed by 1 or 2 rx ring setup 3607 * specifications. 3608 * 3609 * |31 16|15 8|7 0| 3610 * |---------------------------------------------------------------| 3611 * header: | reserved | num rings | msg type | 3612 * |---------------------------------------------------------------| 3613 * payload 1: | FW_IDX shadow register physical address (bits 31:0) | 3614 #if HTT_PADDR64 3615 * | FW_IDX shadow register physical address (bits 63:32) | 3616 #endif 3617 * |---------------------------------------------------------------| 3618 * | rx ring base physical address (bits 31:0) | 3619 #if HTT_PADDR64 3620 * | rx ring base physical address (bits 63:32) | 3621 #endif 3622 * |---------------------------------------------------------------| 3623 * | rx ring buffer size | rx ring length | 3624 * |---------------------------------------------------------------| 3625 * | FW_IDX initial value | enabled flags | 3626 * |---------------------------------------------------------------| 3627 * | MSDU payload offset | 802.11 header offset | 3628 * |---------------------------------------------------------------| 3629 * | PPDU end offset | PPDU start offset | 3630 * |---------------------------------------------------------------| 3631 * | MPDU end offset | MPDU start offset | 3632 * |---------------------------------------------------------------| 3633 * | MSDU end offset | MSDU start offset | 3634 * |---------------------------------------------------------------| 3635 * | frag info offset | rx attention offset | 3636 * |---------------------------------------------------------------| 3637 * payload 2, if present, has the same format as payload 1 3638 * Header fields: 3639 * - MSG_TYPE 3640 * Bits 7:0 3641 * Purpose: identifies this as an rx ring configuration message 3642 * Value: 0x2 (HTT_H2T_MSG_TYPE_RX_RING_CFG) 3643 * - NUM_RINGS 3644 * Bits 15:8 3645 * Purpose: indicates whether the host is setting up one rx ring or two 3646 * Value: 1 or 2 3647 * Payload: 3648 * for systems using 64-bit format for bus addresses: 3649 * - IDX_SHADOW_REG_PADDR_LO 3650 * Bits 31:0 3651 * Value: lower 4 bytes of physical address of the host's 3652 * FW_IDX shadow register 3653 * - IDX_SHADOW_REG_PADDR_HI 3654 * Bits 31:0 3655 * Value: upper 4 bytes of physical address of the host's 3656 * FW_IDX shadow register 3657 * - RING_BASE_PADDR_LO 3658 * Bits 31:0 3659 * Value: lower 4 bytes of physical address of the host's rx ring 3660 * - RING_BASE_PADDR_HI 3661 * Bits 31:0 3662 * Value: uppper 4 bytes of physical address of the host's rx ring 3663 * for systems using 32-bit format for bus addresses: 3664 * - IDX_SHADOW_REG_PADDR 3665 * Bits 31:0 3666 * Value: physical address of the host's FW_IDX shadow register 3667 * - RING_BASE_PADDR 3668 * Bits 31:0 3669 * Value: physical address of the host's rx ring 3670 * - RING_LEN 3671 * Bits 15:0 3672 * Value: number of elements in the rx ring 3673 * - RING_BUF_SZ 3674 * Bits 31:16 3675 * Value: size of the buffers referenced by the rx ring, in byte units 3676 * - ENABLED_FLAGS 3677 * Bits 15:0 3678 * Value: 1-bit flags to show whether different rx fields are enabled 3679 * bit 0: 802.11 header enabled (1) or disabled (0) 3680 * bit 1: MSDU payload enabled (1) or disabled (0) 3681 * bit 2: PPDU start enabled (1) or disabled (0) 3682 * bit 3: PPDU end enabled (1) or disabled (0) 3683 * bit 4: MPDU start enabled (1) or disabled (0) 3684 * bit 5: MPDU end enabled (1) or disabled (0) 3685 * bit 6: MSDU start enabled (1) or disabled (0) 3686 * bit 7: MSDU end enabled (1) or disabled (0) 3687 * bit 8: rx attention enabled (1) or disabled (0) 3688 * bit 9: frag info enabled (1) or disabled (0) 3689 * bit 10: unicast rx enabled (1) or disabled (0) 3690 * bit 11: multicast rx enabled (1) or disabled (0) 3691 * bit 12: ctrl rx enabled (1) or disabled (0) 3692 * bit 13: mgmt rx enabled (1) or disabled (0) 3693 * bit 14: null rx enabled (1) or disabled (0) 3694 * bit 15: phy data rx enabled (1) or disabled (0) 3695 * - IDX_INIT_VAL 3696 * Bits 31:16 3697 * Purpose: Specify the initial value for the FW_IDX. 3698 * Value: the number of buffers initially present in the host's rx ring 3699 * - OFFSET_802_11_HDR 3700 * Bits 15:0 3701 * Value: offset in QUAD-bytes of 802.11 header from the buffer start 3702 * - OFFSET_MSDU_PAYLOAD 3703 * Bits 31:16 3704 * Value: offset in QUAD-bytes of MSDU payload from the buffer start 3705 * - OFFSET_PPDU_START 3706 * Bits 15:0 3707 * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start 3708 * - OFFSET_PPDU_END 3709 * Bits 31:16 3710 * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start 3711 * - OFFSET_MPDU_START 3712 * Bits 15:0 3713 * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start 3714 * - OFFSET_MPDU_END 3715 * Bits 31:16 3716 * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start 3717 * - OFFSET_MSDU_START 3718 * Bits 15:0 3719 * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start 3720 * - OFFSET_MSDU_END 3721 * Bits 31:16 3722 * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start 3723 * - OFFSET_RX_ATTN 3724 * Bits 15:0 3725 * Value: offset in QUAD-bytes of rx attention word from the buffer start 3726 * - OFFSET_FRAG_INFO 3727 * Bits 31:16 3728 * Value: offset in QUAD-bytes of frag info table 3729 */ 3730 /* header fields */ 3731 #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00 3732 #define HTT_RX_RING_CFG_NUM_RINGS_S 8 3733 3734 /* payload fields */ 3735 /* for systems using a 64-bit format for bus addresses */ 3736 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff 3737 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0 3738 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff 3739 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0 3740 #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff 3741 #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0 3742 #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff 3743 #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0 3744 3745 /* for systems using a 32-bit format for bus addresses */ 3746 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff 3747 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0 3748 #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff 3749 #define HTT_RX_RING_CFG_BASE_PADDR_S 0 3750 3751 #define HTT_RX_RING_CFG_LEN_M 0xffff 3752 #define HTT_RX_RING_CFG_LEN_S 0 3753 #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000 3754 #define HTT_RX_RING_CFG_BUF_SZ_S 16 3755 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1 3756 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0 3757 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2 3758 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1 3759 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4 3760 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2 3761 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8 3762 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3 3763 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10 3764 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4 3765 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20 3766 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5 3767 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40 3768 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6 3769 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80 3770 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7 3771 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100 3772 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8 3773 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200 3774 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9 3775 #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400 3776 #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10 3777 #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800 3778 #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11 3779 #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000 3780 #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12 3781 #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000 3782 #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13 3783 #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000 3784 #define HTT_RX_RING_CFG_ENABLED_NULL_S 14 3785 #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000 3786 #define HTT_RX_RING_CFG_ENABLED_PHY_S 15 3787 #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000 3788 #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16 3789 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff 3790 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0 3791 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000 3792 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16 3793 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff 3794 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0 3795 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000 3796 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16 3797 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff 3798 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0 3799 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000 3800 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16 3801 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff 3802 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0 3803 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000 3804 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16 3805 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff 3806 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0 3807 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000 3808 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16 3809 3810 #define HTT_RX_RING_CFG_HDR_BYTES 4 3811 #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 3812 #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 3813 #if HTT_PADDR64 3814 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 3815 #else 3816 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 3817 #endif 3818 #define HTT_RX_RING_CFG_BYTES(num_rings) \ 3819 (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) 3820 3821 3822 #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ 3823 (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) 3824 #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ 3825 do { \ 3826 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ 3827 ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ 3828 } while (0) 3829 3830 /* degenerate case for 32-bit fields */ 3831 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) 3832 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ 3833 ((_var) = (_val)) 3834 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) 3835 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ 3836 ((_var) = (_val)) 3837 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) 3838 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ 3839 ((_var) = (_val)) 3840 3841 /* degenerate case for 32-bit fields */ 3842 #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) 3843 #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) \ 3844 ((_var) = (_val)) 3845 #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) 3846 #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) \ 3847 ((_var) = (_val)) 3848 #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) 3849 #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) \ 3850 ((_var) = (_val)) 3851 3852 #define HTT_RX_RING_CFG_LEN_GET(_var) \ 3853 (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) 3854 #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ 3855 do { \ 3856 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ 3857 ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ 3858 } while (0) 3859 3860 #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ 3861 (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) 3862 #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ 3863 do { \ 3864 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ 3865 ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ 3866 } while (0) 3867 3868 #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ 3869 (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ 3870 HTT_RX_RING_CFG_IDX_INIT_VAL_S) 3871 #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ 3872 do { \ 3873 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ 3874 ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ 3875 } while (0) 3876 3877 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ 3878 (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ 3879 HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) 3880 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ 3881 do { \ 3882 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ 3883 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ 3884 } while (0) 3885 3886 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ 3887 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ 3888 HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) 3889 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ 3890 do { \ 3891 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ 3892 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ 3893 } while (0) 3894 3895 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ 3896 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ 3897 HTT_RX_RING_CFG_ENABLED_PPDU_START_S) 3898 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ 3899 do { \ 3900 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ 3901 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ 3902 } while (0) 3903 3904 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ 3905 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ 3906 HTT_RX_RING_CFG_ENABLED_PPDU_END_S) 3907 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ 3908 do { \ 3909 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ 3910 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ 3911 } while (0) 3912 3913 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ 3914 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ 3915 HTT_RX_RING_CFG_ENABLED_MPDU_START_S) 3916 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ 3917 do { \ 3918 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ 3919 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ 3920 } while (0) 3921 3922 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ 3923 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ 3924 HTT_RX_RING_CFG_ENABLED_MPDU_END_S) 3925 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ 3926 do { \ 3927 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ 3928 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ 3929 } while (0) 3930 3931 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ 3932 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ 3933 HTT_RX_RING_CFG_ENABLED_MSDU_START_S) 3934 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ 3935 do { \ 3936 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ 3937 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ 3938 } while (0) 3939 3940 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ 3941 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ 3942 HTT_RX_RING_CFG_ENABLED_MSDU_END_S) 3943 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ 3944 do { \ 3945 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ 3946 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ 3947 } while (0) 3948 3949 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ 3950 (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ 3951 HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) 3952 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ 3953 do { \ 3954 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ 3955 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ 3956 } while (0) 3957 3958 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ 3959 (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ 3960 HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) 3961 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ 3962 do { \ 3963 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ 3964 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ 3965 } while (0) 3966 3967 #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ 3968 (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ 3969 HTT_RX_RING_CFG_ENABLED_UCAST_S) 3970 #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ 3971 do { \ 3972 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ 3973 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ 3974 } while (0) 3975 3976 #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ 3977 (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ 3978 HTT_RX_RING_CFG_ENABLED_MCAST_S) 3979 #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ 3980 do { \ 3981 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ 3982 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ 3983 } while (0) 3984 #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ 3985 (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ 3986 HTT_RX_RING_CFG_ENABLED_CTRL_S) 3987 #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ 3988 do { \ 3989 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ 3990 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ 3991 } while (0) 3992 #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ 3993 (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ 3994 HTT_RX_RING_CFG_ENABLED_MGMT_S) 3995 #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ 3996 do { \ 3997 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ 3998 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ 3999 } while (0) 4000 #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ 4001 (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ 4002 HTT_RX_RING_CFG_ENABLED_NULL_S) 4003 #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ 4004 do { \ 4005 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ 4006 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ 4007 } while (0) 4008 #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ 4009 (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ 4010 HTT_RX_RING_CFG_ENABLED_PHY_S) 4011 #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ 4012 do { \ 4013 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ 4014 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ 4015 } while (0) 4016 4017 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ 4018 (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ 4019 HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) 4020 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ 4021 do { \ 4022 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ 4023 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ 4024 } while (0) 4025 4026 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ 4027 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ 4028 HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) 4029 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ 4030 do { \ 4031 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ 4032 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ 4033 } while (0) 4034 4035 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ 4036 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ 4037 HTT_RX_RING_CFG_OFFSET_PPDU_START_S) 4038 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ 4039 do { \ 4040 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ 4041 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ 4042 } while (0) 4043 4044 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ 4045 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ 4046 HTT_RX_RING_CFG_OFFSET_PPDU_END_S) 4047 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ 4048 do { \ 4049 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ 4050 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ 4051 } while (0) 4052 4053 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ 4054 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ 4055 HTT_RX_RING_CFG_OFFSET_MPDU_START_S) 4056 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ 4057 do { \ 4058 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ 4059 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ 4060 } while (0) 4061 4062 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ 4063 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ 4064 HTT_RX_RING_CFG_OFFSET_MPDU_END_S) 4065 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ 4066 do { \ 4067 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ 4068 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ 4069 } while (0) 4070 4071 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ 4072 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ 4073 HTT_RX_RING_CFG_OFFSET_MSDU_START_S) 4074 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ 4075 do { \ 4076 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ 4077 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ 4078 } while (0) 4079 4080 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ 4081 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ 4082 HTT_RX_RING_CFG_OFFSET_MSDU_END_S) 4083 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ 4084 do { \ 4085 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ 4086 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ 4087 } while (0) 4088 4089 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ 4090 (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ 4091 HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) 4092 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ 4093 do { \ 4094 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ 4095 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ 4096 } while (0) 4097 4098 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ 4099 (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ 4100 HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) 4101 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ 4102 do { \ 4103 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ 4104 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ 4105 } while (0) 4106 4107 /** 4108 * @brief host -> target FW statistics retrieve 4109 * 4110 * MSG_TYPE => HTT_H2T_MSG_TYPE_STATS_REQ 4111 * 4112 * @details 4113 * The following field definitions describe the format of the HTT host 4114 * to target FW stats retrieve message. The message specifies the type of 4115 * stats host wants to retrieve. 4116 * 4117 * |31 24|23 16|15 8|7 0| 4118 * |-----------------------------------------------------------| 4119 * | stats types request bitmask | msg type | 4120 * |-----------------------------------------------------------| 4121 * | stats types reset bitmask | reserved | 4122 * |-----------------------------------------------------------| 4123 * | stats type | config value | 4124 * |-----------------------------------------------------------| 4125 * | cookie LSBs | 4126 * |-----------------------------------------------------------| 4127 * | cookie MSBs | 4128 * |-----------------------------------------------------------| 4129 * Header fields: 4130 * - MSG_TYPE 4131 * Bits 7:0 4132 * Purpose: identifies this is a stats upload request message 4133 * Value: 0x3 (HTT_H2T_MSG_TYPE_STATS_REQ) 4134 * - UPLOAD_TYPES 4135 * Bits 31:8 4136 * Purpose: identifies which types of FW statistics to upload 4137 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4138 * - RESET_TYPES 4139 * Bits 31:8 4140 * Purpose: identifies which types of FW statistics to reset 4141 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4142 * - CFG_VAL 4143 * Bits 23:0 4144 * Purpose: give an opaque configuration value to the specified stats type 4145 * Value: stats-type specific configuration value 4146 * if stats type == tx PPDU log, then CONFIG_VAL has the format: 4147 * bits 7:0 - how many per-MPDU byte counts to include in a record 4148 * bits 15:8 - how many per-MPDU MSDU counts to include in a record 4149 * bits 23:16 - how many per-MSDU byte counts to include in a record 4150 * - CFG_STAT_TYPE 4151 * Bits 31:24 4152 * Purpose: specify which stats type (if any) the config value applies to 4153 * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have 4154 * a valid configuration specification 4155 * - COOKIE_LSBS 4156 * Bits 31:0 4157 * Purpose: Provide a mechanism to match a target->host stats confirmation 4158 * message with its preceding host->target stats request message. 4159 * Value: LSBs of the opaque cookie specified by the host-side requestor 4160 * - COOKIE_MSBS 4161 * Bits 31:0 4162 * Purpose: Provide a mechanism to match a target->host stats confirmation 4163 * message with its preceding host->target stats request message. 4164 * Value: MSBs of the opaque cookie specified by the host-side requestor 4165 */ 4166 4167 #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ 4168 4169 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 4170 4171 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00 4172 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8 4173 4174 #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00 4175 #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8 4176 4177 #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff 4178 #define HTT_H2T_STATS_REQ_CFG_VAL_S 0 4179 4180 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 4181 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 4182 4183 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ 4184 (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ 4185 HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) 4186 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ 4187 do { \ 4188 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ 4189 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ 4190 } while (0) 4191 4192 #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ 4193 (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ 4194 HTT_H2T_STATS_REQ_RESET_TYPES_S) 4195 #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ 4196 do { \ 4197 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ 4198 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ 4199 } while (0) 4200 4201 #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ 4202 (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ 4203 HTT_H2T_STATS_REQ_CFG_VAL_S) 4204 #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ 4205 do { \ 4206 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ 4207 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ 4208 } while (0) 4209 4210 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ 4211 (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ 4212 HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) 4213 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ 4214 do { \ 4215 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ 4216 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ 4217 } while (0) 4218 4219 /** 4220 * @brief host -> target HTT out-of-band sync request 4221 * 4222 * MSG_TYPE => HTT_H2T_MSG_TYPE_SYNC 4223 * 4224 * @details 4225 * The HTT SYNC tells the target to suspend processing of subsequent 4226 * HTT host-to-target messages until some other target agent locally 4227 * informs the target HTT FW that the current sync counter is equal to 4228 * or greater than (in a modulo sense) the sync counter specified in 4229 * the SYNC message. 4230 * This allows other host-target components to synchronize their operation 4231 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 4232 * security key has been downloaded to and activated by the target. 4233 * In the absence of any explicit synchronization counter value 4234 * specification, the target HTT FW will use zero as the default current 4235 * sync value. 4236 * 4237 * |31 24|23 16|15 8|7 0| 4238 * |-----------------------------------------------------------| 4239 * | reserved | sync count | msg type | 4240 * |-----------------------------------------------------------| 4241 * Header fields: 4242 * - MSG_TYPE 4243 * Bits 7:0 4244 * Purpose: identifies this as a sync message 4245 * Value: 0x4 (HTT_H2T_MSG_TYPE_SYNC) 4246 * - SYNC_COUNT 4247 * Bits 15:8 4248 * Purpose: specifies what sync value the HTT FW will wait for from 4249 * an out-of-band specification to resume its operation 4250 * Value: in-band sync counter value to compare against the out-of-band 4251 * counter spec. 4252 * The HTT target FW will suspend its host->target message processing 4253 * as long as 4254 * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128 4255 */ 4256 4257 #define HTT_H2T_SYNC_MSG_SZ 4 4258 4259 #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 4260 #define HTT_H2T_SYNC_COUNT_S 8 4261 4262 #define HTT_H2T_SYNC_COUNT_GET(_var) \ 4263 (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ 4264 HTT_H2T_SYNC_COUNT_S) 4265 #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ 4266 do { \ 4267 HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ 4268 ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ 4269 } while (0) 4270 4271 4272 /** 4273 * @brief host -> target HTT aggregation configuration 4274 * 4275 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG 4276 */ 4277 #define HTT_AGGR_CFG_MSG_SZ 4 4278 4279 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00 4280 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8 4281 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 4282 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 4283 4284 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ 4285 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ 4286 HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) 4287 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ 4288 do { \ 4289 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ 4290 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ 4291 } while (0) 4292 4293 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4294 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4295 HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) 4296 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4297 do { \ 4298 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ 4299 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ 4300 } while (0) 4301 4302 4303 /** 4304 * @brief host -> target HTT configure max amsdu info per vdev 4305 * 4306 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG_EX 4307 * 4308 * @details 4309 * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev 4310 * 4311 * |31 21|20 16|15 8|7 0| 4312 * |-----------------------------------------------------------| 4313 * | reserved | vdev id | max amsdu | msg type | 4314 * |-----------------------------------------------------------| 4315 * Header fields: 4316 * - MSG_TYPE 4317 * Bits 7:0 4318 * Purpose: identifies this as a aggr cfg ex message 4319 * Value: 0xa (HTT_H2T_MSG_TYPE_AGGR_CFG_EX) 4320 * - MAX_NUM_AMSDU_SUBFRM 4321 * Bits 15:8 4322 * Purpose: max MSDUs per A-MSDU 4323 * - VDEV_ID 4324 * Bits 20:16 4325 * Purpose: ID of the vdev to which this limit is applied 4326 */ 4327 #define HTT_AGGR_CFG_EX_MSG_SZ 4 4328 4329 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00 4330 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8 4331 #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 4332 #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 4333 4334 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4335 (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4336 HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) 4337 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4338 do { \ 4339 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ 4340 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ 4341 } while (0) 4342 4343 #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ 4344 (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ 4345 HTT_AGGR_CFG_EX_VDEV_ID_S) 4346 #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ 4347 do { \ 4348 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ 4349 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ 4350 } while (0) 4351 4352 /** 4353 * @brief HTT WDI_IPA Config Message 4354 * 4355 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_CFG 4356 * 4357 * @details 4358 * The HTT WDI_IPA config message is created/sent by host at driver 4359 * init time. It contains information about data structures used on 4360 * WDI_IPA TX and RX path. 4361 * TX CE ring is used for pushing packet metadata from IPA uC 4362 * to WLAN FW 4363 * TX Completion ring is used for generating TX completions from 4364 * WLAN FW to IPA uC 4365 * RX Indication ring is used for indicating RX packets from FW 4366 * to IPA uC 4367 * RX Ring2 is used as either completion ring or as second 4368 * indication ring. when Ring2 is used as completion ring, IPA uC 4369 * puts completed RX packet meta data to Ring2. when Ring2 is used 4370 * as second indication ring, RX packets for LTE-WLAN aggregation are 4371 * indicated in Ring2, other RX packets (e.g. hotspot related) are 4372 * indicated in RX Indication ring. Please see WDI_IPA specification 4373 * for more details. 4374 * |31 24|23 16|15 8|7 0| 4375 * |----------------+----------------+----------------+----------------| 4376 * | tx pkt pool size | Rsvd | msg_type | 4377 * |-------------------------------------------------------------------| 4378 * | tx comp ring base (bits 31:0) | 4379 #if HTT_PADDR64 4380 * | tx comp ring base (bits 63:32) | 4381 #endif 4382 * |-------------------------------------------------------------------| 4383 * | tx comp ring size | 4384 * |-------------------------------------------------------------------| 4385 * | tx comp WR_IDX physical address (bits 31:0) | 4386 #if HTT_PADDR64 4387 * | tx comp WR_IDX physical address (bits 63:32) | 4388 #endif 4389 * |-------------------------------------------------------------------| 4390 * | tx CE WR_IDX physical address (bits 31:0) | 4391 #if HTT_PADDR64 4392 * | tx CE WR_IDX physical address (bits 63:32) | 4393 #endif 4394 * |-------------------------------------------------------------------| 4395 * | rx indication ring base (bits 31:0) | 4396 #if HTT_PADDR64 4397 * | rx indication ring base (bits 63:32) | 4398 #endif 4399 * |-------------------------------------------------------------------| 4400 * | rx indication ring size | 4401 * |-------------------------------------------------------------------| 4402 * | rx ind RD_IDX physical address (bits 31:0) | 4403 #if HTT_PADDR64 4404 * | rx ind RD_IDX physical address (bits 63:32) | 4405 #endif 4406 * |-------------------------------------------------------------------| 4407 * | rx ind WR_IDX physical address (bits 31:0) | 4408 #if HTT_PADDR64 4409 * | rx ind WR_IDX physical address (bits 63:32) | 4410 #endif 4411 * |-------------------------------------------------------------------| 4412 * |-------------------------------------------------------------------| 4413 * | rx ring2 base (bits 31:0) | 4414 #if HTT_PADDR64 4415 * | rx ring2 base (bits 63:32) | 4416 #endif 4417 * |-------------------------------------------------------------------| 4418 * | rx ring2 size | 4419 * |-------------------------------------------------------------------| 4420 * | rx ring2 RD_IDX physical address (bits 31:0) | 4421 #if HTT_PADDR64 4422 * | rx ring2 RD_IDX physical address (bits 63:32) | 4423 #endif 4424 * |-------------------------------------------------------------------| 4425 * | rx ring2 WR_IDX physical address (bits 31:0) | 4426 #if HTT_PADDR64 4427 * | rx ring2 WR_IDX physical address (bits 63:32) | 4428 #endif 4429 * |-------------------------------------------------------------------| 4430 * 4431 * Header fields: 4432 * Header fields: 4433 * - MSG_TYPE 4434 * Bits 7:0 4435 * Purpose: Identifies this as WDI_IPA config message 4436 * value: = 0x8 (HTT_H2T_MSG_TYPE_WDI_IPA_CFG) 4437 * - TX_PKT_POOL_SIZE 4438 * Bits 15:0 4439 * Purpose: Total number of TX packet buffer pool allocated by Host for 4440 * WDI_IPA TX path 4441 * For systems using 32-bit format for bus addresses: 4442 * - TX_COMP_RING_BASE_ADDR 4443 * Bits 31:0 4444 * Purpose: TX Completion Ring base address in DDR 4445 * - TX_COMP_RING_SIZE 4446 * Bits 31:0 4447 * Purpose: TX Completion Ring size (must be power of 2) 4448 * - TX_COMP_WR_IDX_ADDR 4449 * Bits 31:0 4450 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4451 * updates the Write Index for WDI_IPA TX completion ring 4452 * - TX_CE_WR_IDX_ADDR 4453 * Bits 31:0 4454 * Purpose: DDR address where IPA uC 4455 * updates the WR Index for TX CE ring 4456 * (needed for fusion platforms) 4457 * - RX_IND_RING_BASE_ADDR 4458 * Bits 31:0 4459 * Purpose: RX Indication Ring base address in DDR 4460 * - RX_IND_RING_SIZE 4461 * Bits 31:0 4462 * Purpose: RX Indication Ring size 4463 * - RX_IND_RD_IDX_ADDR 4464 * Bits 31:0 4465 * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA 4466 * RX indication ring 4467 * - RX_IND_WR_IDX_ADDR 4468 * Bits 31:0 4469 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4470 * updates the Write Index for WDI_IPA RX indication ring 4471 * - RX_RING2_BASE_ADDR 4472 * Bits 31:0 4473 * Purpose: Second RX Ring(Indication or completion)base address in DDR 4474 * - RX_RING2_SIZE 4475 * Bits 31:0 4476 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4477 * - RX_RING2_RD_IDX_ADDR 4478 * Bits 31:0 4479 * Purpose: If Second RX ring is Indication ring, DDR address where 4480 * IPA uC updates the Read Index for Ring2. 4481 * If Second RX ring is completion ring, this is NOT used 4482 * - RX_RING2_WR_IDX_ADDR 4483 * Bits 31:0 4484 * Purpose: If Second RX ring is Indication ring, DDR address where 4485 * WIFI FW updates the Write Index for WDI_IPA RX ring2 4486 * If second RX ring is completion ring, DDR address where 4487 * IPA uC updates the Write Index for Ring 2. 4488 * For systems using 64-bit format for bus addresses: 4489 * - TX_COMP_RING_BASE_ADDR_LO 4490 * Bits 31:0 4491 * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR 4492 * - TX_COMP_RING_BASE_ADDR_HI 4493 * Bits 31:0 4494 * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR 4495 * - TX_COMP_RING_SIZE 4496 * Bits 31:0 4497 * Purpose: TX Completion Ring size (must be power of 2) 4498 * - TX_COMP_WR_IDX_ADDR_LO 4499 * Bits 31:0 4500 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4501 * Lower 4 bytes of DDR address where WIFI FW 4502 * updates the Write Index for WDI_IPA TX completion ring 4503 * - TX_COMP_WR_IDX_ADDR_HI 4504 * Bits 31:0 4505 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4506 * Higher 4 bytes of DDR address where WIFI FW 4507 * updates the Write Index for WDI_IPA TX completion ring 4508 * - TX_CE_WR_IDX_ADDR_LO 4509 * Bits 31:0 4510 * Purpose: Lower 4 bytes of DDR address where IPA uC 4511 * updates the WR Index for TX CE ring 4512 * (needed for fusion platforms) 4513 * - TX_CE_WR_IDX_ADDR_HI 4514 * Bits 31:0 4515 * Purpose: Higher 4 bytes of DDR address where IPA uC 4516 * updates the WR Index for TX CE ring 4517 * (needed for fusion platforms) 4518 * - RX_IND_RING_BASE_ADDR_LO 4519 * Bits 31:0 4520 * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR 4521 * - RX_IND_RING_BASE_ADDR_HI 4522 * Bits 31:0 4523 * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR 4524 * - RX_IND_RING_SIZE 4525 * Bits 31:0 4526 * Purpose: RX Indication Ring size 4527 * - RX_IND_RD_IDX_ADDR_LO 4528 * Bits 31:0 4529 * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index 4530 * for WDI_IPA RX indication ring 4531 * - RX_IND_RD_IDX_ADDR_HI 4532 * Bits 31:0 4533 * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index 4534 * for WDI_IPA RX indication ring 4535 * - RX_IND_WR_IDX_ADDR_LO 4536 * Bits 31:0 4537 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4538 * Lower 4 bytes of DDR address where WIFI FW 4539 * updates the Write Index for WDI_IPA RX indication ring 4540 * - RX_IND_WR_IDX_ADDR_HI 4541 * Bits 31:0 4542 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4543 * Higher 4 bytes of DDR address where WIFI FW 4544 * updates the Write Index for WDI_IPA RX indication ring 4545 * - RX_RING2_BASE_ADDR_LO 4546 * Bits 31:0 4547 * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4548 * - RX_RING2_BASE_ADDR_HI 4549 * Bits 31:0 4550 * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4551 * - RX_RING2_SIZE 4552 * Bits 31:0 4553 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4554 * - RX_RING2_RD_IDX_ADDR_LO 4555 * Bits 31:0 4556 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4557 * DDR address where IPA uC updates the Read Index for Ring2. 4558 * If Second RX ring is completion ring, this is NOT used 4559 * - RX_RING2_RD_IDX_ADDR_HI 4560 * Bits 31:0 4561 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4562 * DDR address where IPA uC updates the Read Index for Ring2. 4563 * If Second RX ring is completion ring, this is NOT used 4564 * - RX_RING2_WR_IDX_ADDR_LO 4565 * Bits 31:0 4566 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4567 * DDR address where WIFI FW updates the Write Index 4568 * for WDI_IPA RX ring2 4569 * If second RX ring is completion ring, lower 4 bytes of 4570 * DDR address where IPA uC updates the Write Index for Ring 2. 4571 * - RX_RING2_WR_IDX_ADDR_HI 4572 * Bits 31:0 4573 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4574 * DDR address where WIFI FW updates the Write Index 4575 * for WDI_IPA RX ring2 4576 * If second RX ring is completion ring, higher 4 bytes of 4577 * DDR address where IPA uC updates the Write Index for Ring 2. 4578 */ 4579 4580 #if HTT_PADDR64 4581 #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ 4582 #else 4583 #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ 4584 #endif 4585 4586 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 4587 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16 4588 4589 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff 4590 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0 4591 4592 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff 4593 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0 4594 4595 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff 4596 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0 4597 4598 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff 4599 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0 4600 4601 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff 4602 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0 4603 4604 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff 4605 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0 4606 4607 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff 4608 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0 4609 4610 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff 4611 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0 4612 4613 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff 4614 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0 4615 4616 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff 4617 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0 4618 4619 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff 4620 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0 4621 4622 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff 4623 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0 4624 4625 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff 4626 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0 4627 4628 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff 4629 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0 4630 4631 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff 4632 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0 4633 4634 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff 4635 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0 4636 4637 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff 4638 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0 4639 4640 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff 4641 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0 4642 4643 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff 4644 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0 4645 4646 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff 4647 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0 4648 4649 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff 4650 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0 4651 4652 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff 4653 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0 4654 4655 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff 4656 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0 4657 4658 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff 4659 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0 4660 4661 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff 4662 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0 4663 4664 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff 4665 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0 4666 4667 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff 4668 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0 4669 4670 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff 4671 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0 4672 4673 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff 4674 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0 4675 4676 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff 4677 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 4678 4679 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ 4680 (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) 4681 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ 4682 do { \ 4683 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ 4684 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ 4685 } while (0) 4686 4687 /* for systems using 32-bit format for bus addr */ 4688 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ 4689 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) 4690 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ 4691 do { \ 4692 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \ 4693 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ 4694 } while (0) 4695 4696 /* for systems using 64-bit format for bus addr */ 4697 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ 4698 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) 4699 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ 4700 do { \ 4701 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \ 4702 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ 4703 } while (0) 4704 4705 /* for systems using 64-bit format for bus addr */ 4706 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ 4707 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) 4708 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ 4709 do { \ 4710 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ 4711 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ 4712 } while (0) 4713 4714 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ 4715 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) 4716 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ 4717 do { \ 4718 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ 4719 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ 4720 } while (0) 4721 4722 /* for systems using 32-bit format for bus addr */ 4723 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ 4724 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) 4725 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ 4726 do { \ 4727 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ 4728 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ 4729 } while (0) 4730 4731 /* for systems using 64-bit format for bus addr */ 4732 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ 4733 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) 4734 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ 4735 do { \ 4736 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ 4737 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ 4738 } while (0) 4739 4740 /* for systems using 64-bit format for bus addr */ 4741 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ 4742 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) 4743 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ 4744 do { \ 4745 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ 4746 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ 4747 } while (0) 4748 4749 4750 /* for systems using 32-bit format for bus addr */ 4751 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ 4752 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) 4753 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ 4754 do { \ 4755 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ 4756 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ 4757 } while (0) 4758 4759 /* for systems using 64-bit format for bus addr */ 4760 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ 4761 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) 4762 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ 4763 do { \ 4764 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ 4765 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ 4766 } while (0) 4767 4768 /* for systems using 64-bit format for bus addr */ 4769 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ 4770 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) 4771 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ 4772 do { \ 4773 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ 4774 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ 4775 } while (0) 4776 4777 /* for systems using 32-bit format for bus addr */ 4778 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ 4779 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) 4780 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ 4781 do { \ 4782 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ 4783 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ 4784 } while (0) 4785 4786 /* for systems using 64-bit format for bus addr */ 4787 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ 4788 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) 4789 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ 4790 do { \ 4791 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ 4792 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ 4793 } while (0) 4794 4795 /* for systems using 64-bit format for bus addr */ 4796 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ 4797 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) 4798 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ 4799 do { \ 4800 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ 4801 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ 4802 } while (0) 4803 4804 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ 4805 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) 4806 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ 4807 do { \ 4808 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ 4809 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ 4810 } while (0) 4811 4812 /* for systems using 32-bit format for bus addr */ 4813 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ 4814 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) 4815 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ 4816 do { \ 4817 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ 4818 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ 4819 } while (0) 4820 4821 /* for systems using 64-bit format for bus addr */ 4822 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ 4823 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) 4824 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ 4825 do { \ 4826 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ 4827 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ 4828 } while (0) 4829 4830 /* for systems using 64-bit format for bus addr */ 4831 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ 4832 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) 4833 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ 4834 do { \ 4835 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ 4836 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ 4837 } while (0) 4838 4839 /* for systems using 32-bit format for bus addr */ 4840 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ 4841 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) 4842 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ 4843 do { \ 4844 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ 4845 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ 4846 } while (0) 4847 4848 /* for systems using 64-bit format for bus addr */ 4849 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ 4850 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) 4851 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ 4852 do { \ 4853 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ 4854 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ 4855 } while (0) 4856 4857 /* for systems using 64-bit format for bus addr */ 4858 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ 4859 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) 4860 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ 4861 do { \ 4862 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ 4863 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ 4864 } while (0) 4865 4866 /* for systems using 32-bit format for bus addr */ 4867 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ 4868 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) 4869 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ 4870 do { \ 4871 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ 4872 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ 4873 } while (0) 4874 4875 /* for systems using 64-bit format for bus addr */ 4876 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ 4877 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) 4878 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ 4879 do { \ 4880 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ 4881 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ 4882 } while (0) 4883 4884 /* for systems using 64-bit format for bus addr */ 4885 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ 4886 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) 4887 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ 4888 do { \ 4889 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ 4890 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ 4891 } while (0) 4892 4893 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ 4894 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) 4895 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ 4896 do { \ 4897 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ 4898 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ 4899 } while (0) 4900 4901 /* for systems using 32-bit format for bus addr */ 4902 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ 4903 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) 4904 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ 4905 do { \ 4906 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ 4907 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ 4908 } while (0) 4909 4910 /* for systems using 64-bit format for bus addr */ 4911 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ 4912 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) 4913 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ 4914 do { \ 4915 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ 4916 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ 4917 } while (0) 4918 4919 /* for systems using 64-bit format for bus addr */ 4920 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ 4921 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) 4922 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ 4923 do { \ 4924 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ 4925 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ 4926 } while (0) 4927 4928 /* for systems using 32-bit format for bus addr */ 4929 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ 4930 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) 4931 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ 4932 do { \ 4933 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ 4934 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ 4935 } while (0) 4936 4937 /* for systems using 64-bit format for bus addr */ 4938 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ 4939 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) 4940 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ 4941 do { \ 4942 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ 4943 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ 4944 } while (0) 4945 4946 /* for systems using 64-bit format for bus addr */ 4947 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ 4948 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) 4949 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ 4950 do { \ 4951 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ 4952 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ 4953 } while (0) 4954 4955 /* 4956 * TEMPLATE_HTT_WDI_IPA_CONFIG_T: 4957 * This macro defines a htt_wdi_ipa_configXXX_t in which any physical 4958 * addresses are stored in a XXX-bit field. 4959 * This macro is used to define both htt_wdi_ipa_config32_t and 4960 * htt_wdi_ipa_config64_t structs. 4961 */ 4962 #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ 4963 _paddr__tx_comp_ring_base_addr_, \ 4964 _paddr__tx_comp_wr_idx_addr_, \ 4965 _paddr__tx_ce_wr_idx_addr_, \ 4966 _paddr__rx_ind_ring_base_addr_, \ 4967 _paddr__rx_ind_rd_idx_addr_, \ 4968 _paddr__rx_ind_wr_idx_addr_, \ 4969 _paddr__rx_ring2_base_addr_,\ 4970 _paddr__rx_ring2_rd_idx_addr_,\ 4971 _paddr__rx_ring2_wr_idx_addr_) \ 4972 PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ 4973 { \ 4974 /* DWORD 0: flags and meta-data */ \ 4975 A_UINT32 \ 4976 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ 4977 reserved: 8, \ 4978 tx_pkt_pool_size: 16;\ 4979 /* DWORD 1 */\ 4980 _paddr__tx_comp_ring_base_addr_;\ 4981 /* DWORD 2 (or 3)*/\ 4982 A_UINT32 tx_comp_ring_size;\ 4983 /* DWORD 3 (or 4)*/\ 4984 _paddr__tx_comp_wr_idx_addr_;\ 4985 /* DWORD 4 (or 6)*/\ 4986 _paddr__tx_ce_wr_idx_addr_;\ 4987 /* DWORD 5 (or 8)*/\ 4988 _paddr__rx_ind_ring_base_addr_;\ 4989 /* DWORD 6 (or 10)*/\ 4990 A_UINT32 rx_ind_ring_size;\ 4991 /* DWORD 7 (or 11)*/\ 4992 _paddr__rx_ind_rd_idx_addr_;\ 4993 /* DWORD 8 (or 13)*/\ 4994 _paddr__rx_ind_wr_idx_addr_;\ 4995 /* DWORD 9 (or 15)*/\ 4996 _paddr__rx_ring2_base_addr_;\ 4997 /* DWORD 10 (or 17) */\ 4998 A_UINT32 rx_ring2_size;\ 4999 /* DWORD 11 (or 18) */\ 5000 _paddr__rx_ring2_rd_idx_addr_;\ 5001 /* DWORD 12 (or 20) */\ 5002 _paddr__rx_ring2_wr_idx_addr_;\ 5003 } POSTPACK 5004 5005 /* define a htt_wdi_ipa_config32_t type */ 5006 TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); 5007 5008 /* define a htt_wdi_ipa_config64_t type */ 5009 TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); 5010 5011 #if HTT_PADDR64 5012 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t 5013 #else 5014 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t 5015 #endif 5016 5017 enum htt_wdi_ipa_op_code { 5018 HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, 5019 HTT_WDI_IPA_OPCODE_TX_RESUME = 1, 5020 HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, 5021 HTT_WDI_IPA_OPCODE_RX_RESUME = 3, 5022 HTT_WDI_IPA_OPCODE_DBG_STATS = 4, 5023 HTT_WDI_IPA_OPCODE_GET_SHARING_STATS = 5, 5024 HTT_WDI_IPA_OPCODE_SET_QUOTA = 6, 5025 HTT_WDI_IPA_OPCODE_IND_QUOTA = 7, 5026 /* keep this last */ 5027 HTT_WDI_IPA_OPCODE_MAX 5028 }; 5029 5030 /** 5031 * @brief HTT WDI_IPA Operation Request Message 5032 * 5033 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ 5034 * 5035 * @details 5036 * HTT WDI_IPA Operation Request message is sent by host 5037 * to either suspend or resume WDI_IPA TX or RX path. 5038 * |31 24|23 16|15 8|7 0| 5039 * |----------------+----------------+----------------+----------------| 5040 * | op_code | Rsvd | msg_type | 5041 * |-------------------------------------------------------------------| 5042 * 5043 * Header fields: 5044 * - MSG_TYPE 5045 * Bits 7:0 5046 * Purpose: Identifies this as WDI_IPA Operation Request message 5047 * value: = 0x9 (HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ) 5048 * - OP_CODE 5049 * Bits 31:16 5050 * Purpose: Identifies operation host is requesting (e.g. TX suspend) 5051 * value: = enum htt_wdi_ipa_op_code 5052 */ 5053 5054 PREPACK struct htt_wdi_ipa_op_request_t 5055 { 5056 /* DWORD 0: flags and meta-data */ 5057 A_UINT32 5058 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ 5059 reserved: 8, 5060 op_code: 16; 5061 } POSTPACK; 5062 5063 #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ 5064 5065 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 5066 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 5067 5068 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ 5069 (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) 5070 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ 5071 do { \ 5072 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ 5073 ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ 5074 } while (0) 5075 5076 /* 5077 * @brief host -> target HTT_MSI_SETUP message 5078 * 5079 * MSG_TYPE => HTT_H2T_MSG_TYPE_MSI_SETUP 5080 * 5081 * @details 5082 * After target is booted up, host can send MSI setup message so that 5083 * target sets up HW registers based on setup message. 5084 * 5085 * The message would appear as follows: 5086 * |31 24|23 16|15|14 8|7 0| 5087 * |---------------+-----------------+-----------------+-----------------| 5088 * | reserved | msi_type | pdev_id | msg_type | 5089 * |---------------------------------------------------------------------| 5090 * | msi_addr_lo | 5091 * |---------------------------------------------------------------------| 5092 * | msi_addr_hi | 5093 * |---------------------------------------------------------------------| 5094 * | msi_data | 5095 * |---------------------------------------------------------------------| 5096 * 5097 * The message is interpreted as follows: 5098 * dword0 - b'0:7 - msg_type: This will be set to 5099 * 0x1f (HTT_H2T_MSG_TYPE_MSI_SETUP) 5100 * b'8:15 - pdev_id: 5101 * 0 (for rings at SOC/UMAC level), 5102 * 1/2/3 mac id (for rings at LMAC level) 5103 * b'16:23 - msi_type: identify which msi registers need to be setup 5104 * more details can be got from enum htt_msi_setup_type 5105 * b'24:31 - reserved 5106 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5107 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5108 * dword10 - b'0:31 - ring_msi_data: MSI data configured by host 5109 */ 5110 PREPACK struct htt_msi_setup_t { 5111 A_UINT32 msg_type: 8, 5112 pdev_id: 8, 5113 msi_type: 8, 5114 reserved: 8; 5115 A_UINT32 msi_addr_lo; 5116 A_UINT32 msi_addr_hi; 5117 A_UINT32 msi_data; 5118 } POSTPACK; 5119 5120 enum htt_msi_setup_type { 5121 HTT_PPDU_END_MSI_SETUP_TYPE, 5122 5123 /* Insert new types here*/ 5124 }; 5125 5126 #define HTT_MSI_SETUP_SZ (sizeof(struct htt_msi_setup_t)) 5127 #define HTT_MSI_SETUP_PDEV_ID_M 0x0000ff00 5128 #define HTT_MSI_SETUP_PDEV_ID_S 8 5129 #define HTT_MSI_SETUP_PDEV_ID_GET(_var) \ 5130 (((_var) & HTT_MSI_SETUP_PDEV_ID_M) >> \ 5131 HTT_MSI_SETUP_PDEV_ID_S) 5132 #define HTT_MSI_SETUP_PDEV_ID_SET(_var, _val) \ 5133 do { \ 5134 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_PDEV_ID, _val); \ 5135 ((_var) |= ((_val) << HTT_MSI_SETUP_PDEV_ID_S)); \ 5136 } while (0) 5137 5138 #define HTT_MSI_SETUP_MSI_TYPE_M 0x00ff0000 5139 #define HTT_MSI_SETUP_MSI_TYPE_S 16 5140 #define HTT_MSI_SETUP_MSI_TYPE_GET(_var) \ 5141 (((_var) & HTT_MSI_SETUP_MSI_TYPE_M) >> \ 5142 HTT_MSI_SETUP_MSI_TYPE_S) 5143 #define HTT_MSI_SETUP_MSI_TYPE_SET(_var, _val) \ 5144 do { \ 5145 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_TYPE, _val); \ 5146 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_TYPE_S)); \ 5147 } while (0) 5148 5149 #define HTT_MSI_SETUP_MSI_ADDR_LO_M 0xffffffff 5150 #define HTT_MSI_SETUP_MSI_ADDR_LO_S 0 5151 #define HTT_MSI_SETUP_MSI_ADDR_LO_GET(_var) \ 5152 (((_var) & HTT_MSI_SETUP_MSI_ADDR_LO_M) >> \ 5153 HTT_MSI_SETUP_MSI_ADDR_LO_S) 5154 #define HTT_MSI_SETUP_MSI_ADDR_LO_SET(_var, _val) \ 5155 do { \ 5156 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_LO, _val); \ 5157 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_LO_S)); \ 5158 } while (0) 5159 5160 #define HTT_MSI_SETUP_MSI_ADDR_HI_M 0xffffffff 5161 #define HTT_MSI_SETUP_MSI_ADDR_HI_S 0 5162 #define HTT_MSI_SETUP_MSI_ADDR_HI_GET(_var) \ 5163 (((_var) & HTT_MSI_SETUP_MSI_ADDR_HI_M) >> \ 5164 HTT_MSI_SETUP_MSI_ADDR_HI_S) 5165 #define HTT_MSI_SETUP_MSI_ADDR_HI_SET(_var, _val) \ 5166 do { \ 5167 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_HI, _val); \ 5168 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_HI_S)); \ 5169 } while (0) 5170 5171 #define HTT_MSI_SETUP_MSI_DATA_M 0xffffffff 5172 #define HTT_MSI_SETUP_MSI_DATA_S 0 5173 #define HTT_MSI_SETUP_MSI_DATA_GET(_var) \ 5174 (((_var) & HTT_MSI_SETUP_MSI_DATA_M) >> \ 5175 HTT_MSI_SETUP_MSI_DATA_S) 5176 #define HTT_MSI_SETUP_MSI_DATA_SET(_var, _val) \ 5177 do { \ 5178 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_DATA, _val); \ 5179 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_DATA_S)); \ 5180 } while (0) 5181 5182 /* 5183 * @brief host -> target HTT_SRING_SETUP message 5184 * 5185 * MSG_TYPE => HTT_H2T_MSG_TYPE_SRING_SETUP 5186 * 5187 * @details 5188 * After target is booted up, Host can send SRING setup message for 5189 * each host facing LMAC SRING. Target setups up HW registers based 5190 * on setup message and confirms back to Host if response_required is set. 5191 * Host should wait for confirmation message before sending new SRING 5192 * setup message 5193 * 5194 * The message would appear as follows: 5195 * |31 24|23 21|20|19|18 16|15|14 8|7 0| 5196 * |--------------- +-----------------+-----------------+-----------------| 5197 * | ring_type | ring_id | pdev_id | msg_type | 5198 * |----------------------------------------------------------------------| 5199 * | ring_base_addr_lo | 5200 * |----------------------------------------------------------------------| 5201 * | ring_base_addr_hi | 5202 * |----------------------------------------------------------------------| 5203 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 5204 * |----------------------------------------------------------------------| 5205 * | ring_head_offset32_remote_addr_lo | 5206 * |----------------------------------------------------------------------| 5207 * | ring_head_offset32_remote_addr_hi | 5208 * |----------------------------------------------------------------------| 5209 * | ring_tail_offset32_remote_addr_lo | 5210 * |----------------------------------------------------------------------| 5211 * | ring_tail_offset32_remote_addr_hi | 5212 * |----------------------------------------------------------------------| 5213 * | ring_msi_addr_lo | 5214 * |----------------------------------------------------------------------| 5215 * | ring_msi_addr_hi | 5216 * |----------------------------------------------------------------------| 5217 * | ring_msi_data | 5218 * |----------------------------------------------------------------------| 5219 * | intr_timer_th |IM| intr_batch_counter_th | 5220 * |----------------------------------------------------------------------| 5221 * | reserved |ID|RR| PTCF| intr_low_threshold | 5222 * |----------------------------------------------------------------------| 5223 * | reserved |IPA drop thres hi|IPA drop thres lo| 5224 * |----------------------------------------------------------------------| 5225 * Where 5226 * IM = sw_intr_mode 5227 * RR = response_required 5228 * PTCF = prefetch_timer_cfg 5229 * IP = IPA drop flag 5230 * 5231 * The message is interpreted as follows: 5232 * dword0 - b'0:7 - msg_type: This will be set to 5233 * 0xb (HTT_H2T_MSG_TYPE_SRING_SETUP) 5234 * b'8:15 - pdev_id: 5235 * 0 (for rings at SOC/UMAC level), 5236 * 1/2/3 mac id (for rings at LMAC level) 5237 * b'16:23 - ring_id: identify which ring is to setup, 5238 * more details can be got from enum htt_srng_ring_id 5239 * b'24:31 - ring_type: identify type of host rings, 5240 * more details can be got from enum htt_srng_ring_type 5241 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 5242 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 5243 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 5244 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 5245 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 5246 * SW_TO_HW_RING. 5247 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 5248 * dword4 - b'0:31 - ring_head_offset32_remote_addr_lo: 5249 * Lower 32 bits of memory address of the remote variable 5250 * storing the 4-byte word offset that identifies the head 5251 * element within the ring. 5252 * (The head offset variable has type A_UINT32.) 5253 * Valid for HW_TO_SW and SW_TO_SW rings. 5254 * dword5 - b'0:31 - ring_head_offset32_remote_addr_hi: 5255 * Upper 32 bits of memory address of the remote variable 5256 * storing the 4-byte word offset that identifies the head 5257 * element within the ring. 5258 * (The head offset variable has type A_UINT32.) 5259 * Valid for HW_TO_SW and SW_TO_SW rings. 5260 * dword6 - b'0:31 - ring_tail_offset32_remote_addr_lo: 5261 * Lower 32 bits of memory address of the remote variable 5262 * storing the 4-byte word offset that identifies the tail 5263 * element within the ring. 5264 * (The tail offset variable has type A_UINT32.) 5265 * Valid for HW_TO_SW and SW_TO_SW rings. 5266 * dword7 - b'0:31 - ring_tail_offset32_remote_addr_hi: 5267 * Upper 32 bits of memory address of the remote variable 5268 * storing the 4-byte word offset that identifies the tail 5269 * element within the ring. 5270 * (The tail offset variable has type A_UINT32.) 5271 * Valid for HW_TO_SW and SW_TO_SW rings. 5272 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5273 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5274 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5275 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5276 * dword10 - b'0:31 - ring_msi_data: MSI data 5277 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 5278 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5279 * dword11 - b'0:14 - intr_batch_counter_th: 5280 * batch counter threshold is in units of 4-byte words. 5281 * HW internally maintains and increments batch count. 5282 * (see SRING spec for detail description). 5283 * When batch count reaches threshold value, an interrupt 5284 * is generated by HW. 5285 * b'15 - sw_intr_mode: 5286 * This configuration shall be static. 5287 * Only programmed at power up. 5288 * 0: generate pulse style sw interrupts 5289 * 1: generate level style sw interrupts 5290 * b'16:31 - intr_timer_th: 5291 * The timer init value when timer is idle or is 5292 * initialized to start downcounting. 5293 * In 8us units (to cover a range of 0 to 524 ms) 5294 * dword12 - b'0:15 - intr_low_threshold: 5295 * Used only by Consumer ring to generate ring_sw_int_p. 5296 * Ring entries low threshold water mark, that is used 5297 * in combination with the interrupt timer as well as 5298 * the the clearing of the level interrupt. 5299 * b'16:18 - prefetch_timer_cfg: 5300 * Used only by Consumer ring to set timer mode to 5301 * support Application prefetch handling. 5302 * The external tail offset/pointer will be updated 5303 * at following intervals: 5304 * 3'b000: (Prefetch feature disabled; used only for debug) 5305 * 3'b001: 1 usec 5306 * 3'b010: 4 usec 5307 * 3'b011: 8 usec (default) 5308 * 3'b100: 16 usec 5309 * Others: Reserved 5310 * b'19 - response_required: 5311 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 5312 * b'20 - ipa_drop_flag: 5313 Indicates that host will config ipa drop threshold percentage 5314 * b'21:31 - reserved: reserved for future use 5315 * dword13 - b'0:7 - ipa drop low threshold percentage: 5316 * b'8:15 - ipa drop high threshold percentage: 5317 * b'16:31 - Reserved 5318 */ 5319 PREPACK struct htt_sring_setup_t { 5320 A_UINT32 msg_type: 8, 5321 pdev_id: 8, 5322 ring_id: 8, 5323 ring_type: 8; 5324 A_UINT32 ring_base_addr_lo; 5325 A_UINT32 ring_base_addr_hi; 5326 A_UINT32 ring_size: 16, 5327 ring_entry_size: 8, 5328 ring_misc_cfg_flag: 8; 5329 A_UINT32 ring_head_offset32_remote_addr_lo; 5330 A_UINT32 ring_head_offset32_remote_addr_hi; 5331 A_UINT32 ring_tail_offset32_remote_addr_lo; 5332 A_UINT32 ring_tail_offset32_remote_addr_hi; 5333 A_UINT32 ring_msi_addr_lo; 5334 A_UINT32 ring_msi_addr_hi; 5335 A_UINT32 ring_msi_data; 5336 A_UINT32 intr_batch_counter_th: 15, 5337 sw_intr_mode: 1, 5338 intr_timer_th: 16; 5339 A_UINT32 intr_low_threshold: 16, 5340 prefetch_timer_cfg: 3, 5341 response_required: 1, 5342 ipa_drop_flag: 1, 5343 reserved1: 11; 5344 A_UINT32 ipa_drop_low_threshold: 8, 5345 ipa_drop_high_threshold: 8, 5346 reserved: 16; 5347 } POSTPACK; 5348 5349 enum htt_srng_ring_type { 5350 HTT_HW_TO_SW_RING = 0, 5351 HTT_SW_TO_HW_RING, 5352 HTT_SW_TO_SW_RING, 5353 /* Insert new ring types above this line */ 5354 }; 5355 5356 enum htt_srng_ring_id { 5357 HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */ 5358 HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */ 5359 HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */ 5360 HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ 5361 HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */ 5362 HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */ 5363 HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */ 5364 HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */ 5365 HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */ 5366 HTT_TX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5367 HTT_TX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5368 HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5369 HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5370 HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ 5371 HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ 5372 /* Add Other SRING which can't be directly configured by host software above this line */ 5373 }; 5374 5375 #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t)) 5376 5377 #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00 5378 #define HTT_SRING_SETUP_PDEV_ID_S 8 5379 #define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ 5380 (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ 5381 HTT_SRING_SETUP_PDEV_ID_S) 5382 #define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ 5383 do { \ 5384 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ 5385 ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ 5386 } while (0) 5387 5388 #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000 5389 #define HTT_SRING_SETUP_RING_ID_S 16 5390 #define HTT_SRING_SETUP_RING_ID_GET(_var) \ 5391 (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ 5392 HTT_SRING_SETUP_RING_ID_S) 5393 #define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ 5394 do { \ 5395 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ 5396 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ 5397 } while (0) 5398 5399 #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000 5400 #define HTT_SRING_SETUP_RING_TYPE_S 24 5401 #define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ 5402 (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ 5403 HTT_SRING_SETUP_RING_TYPE_S) 5404 #define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ 5405 do { \ 5406 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ 5407 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ 5408 } while (0) 5409 5410 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff 5411 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0 5412 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ 5413 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ 5414 HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) 5415 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ 5416 do { \ 5417 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \ 5418 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \ 5419 } while (0) 5420 5421 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff 5422 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0 5423 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ 5424 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ 5425 HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) 5426 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ 5427 do { \ 5428 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \ 5429 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \ 5430 } while (0) 5431 5432 #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff 5433 #define HTT_SRING_SETUP_RING_SIZE_S 0 5434 #define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ 5435 (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ 5436 HTT_SRING_SETUP_RING_SIZE_S) 5437 #define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ 5438 do { \ 5439 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ 5440 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ 5441 } while (0) 5442 5443 #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff0000 5444 #define HTT_SRING_SETUP_ENTRY_SIZE_S 16 5445 #define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ 5446 (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ 5447 HTT_SRING_SETUP_ENTRY_SIZE_S) 5448 #define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ 5449 do { \ 5450 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ 5451 ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ 5452 } while (0) 5453 5454 #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff000000 5455 #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24 5456 #define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \ 5457 (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ 5458 HTT_SRING_SETUP_MISC_CFG_FLAG_S) 5459 #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \ 5460 do { \ 5461 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ 5462 ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ 5463 } while (0) 5464 5465 /* This control bit is applicable to only Producer, which updates Ring ID field 5466 * of each descriptor before pushing into the ring. 5467 * 0: updates ring_id(default) 5468 * 1: ring_id updating disabled */ 5469 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M 0x01000000 5470 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S 24 5471 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \ 5472 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \ 5473 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S) 5474 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_SET(_var, _val) \ 5475 do { \ 5476 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val); \ 5477 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \ 5478 } while (0) 5479 5480 /* This control bit is applicable to only Producer, which updates Loopcnt field 5481 * of each descriptor before pushing into the ring. 5482 * 0: updates Loopcnt(default) 5483 * 1: Loopcnt updating disabled */ 5484 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M 0x02000000 5485 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S 25 5486 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_GET(_var) \ 5487 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \ 5488 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S) 5489 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_SET(_var, _val) \ 5490 do { \ 5491 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \ 5492 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \ 5493 } while (0) 5494 5495 /* Secured access enable/disable bit. SRNG drives value of this register bit 5496 * into security_id port of GXI/AXI. */ 5497 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M 0x04000000 5498 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S 26 5499 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_GET(_var) \ 5500 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \ 5501 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S) 5502 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_SET(_var, _val) \ 5503 do { \ 5504 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY, _val); \ 5505 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)); \ 5506 } while (0) 5507 5508 /* During MSI write operation, SRNG drives value of this register bit into 5509 * swap bit of GXI/AXI. */ 5510 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M 0x08000000 5511 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S 27 5512 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_GET(_var) \ 5513 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ 5514 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) 5515 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ 5516 do { \ 5517 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ 5518 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ 5519 } while (0) 5520 5521 /* During Pointer write operation, SRNG drives value of this register bit into 5522 * swap bit of GXI/AXI. */ 5523 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M 0x10000000 5524 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S 28 5525 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_GET(_var) \ 5526 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \ 5527 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S) 5528 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_SET(_var, _val) \ 5529 do { \ 5530 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \ 5531 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \ 5532 } while (0) 5533 5534 /* During any data or TLV write operation, SRNG drives value of this register 5535 * bit into swap bit of GXI/AXI. */ 5536 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M 0x20000000 5537 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S 29 5538 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_GET(_var) \ 5539 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \ 5540 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S) 5541 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_SET(_var, _val) \ 5542 do { \ 5543 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP, _val); \ 5544 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)); \ 5545 } while (0) 5546 5547 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED1 0x40000000 5548 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED2 0x80000000 5549 5550 5551 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5552 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5553 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5554 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5555 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5556 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5557 do { \ 5558 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5559 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5560 } while (0) 5561 5562 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5563 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5564 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5565 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5566 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5567 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5568 do { \ 5569 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5570 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5571 } while (0) 5572 5573 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5574 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5575 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5576 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5577 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5578 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5579 do { \ 5580 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5581 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5582 } while (0) 5583 5584 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5585 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5586 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5587 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5588 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5589 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5590 do { \ 5591 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5592 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5593 } while (0) 5594 5595 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_M 0xffffffff 5596 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_S 0 5597 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_GET(_var) \ 5598 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \ 5599 HTT_SRING_SETUP_RING_MSI_ADDR_LO_S) 5600 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_SET(_var, _val) \ 5601 do { \ 5602 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \ 5603 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \ 5604 } while (0) 5605 5606 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_M 0xffffffff 5607 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_S 0 5608 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_GET(_var) \ 5609 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \ 5610 HTT_SRING_SETUP_RING_MSI_ADDR_HI_S) 5611 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_SET(_var, _val) \ 5612 do { \ 5613 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \ 5614 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \ 5615 } while (0) 5616 5617 #define HTT_SRING_SETUP_RING_MSI_DATA_M 0xffffffff 5618 #define HTT_SRING_SETUP_RING_MSI_DATA_S 0 5619 #define HTT_SRING_SETUP_RING_MSI_DATA_GET(_var) \ 5620 (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \ 5621 HTT_SRING_SETUP_RING_MSI_DATA_S) 5622 #define HTT_SRING_SETUP_RING_MSI_DATA_SET(_var, _val) \ 5623 do { \ 5624 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \ 5625 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \ 5626 } while (0) 5627 5628 5629 5630 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M 0x00007fff 5631 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S 0 5632 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_GET(_var) \ 5633 (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \ 5634 HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S) 5635 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_SET(_var, _val) \ 5636 do { \ 5637 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \ 5638 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \ 5639 } while (0) 5640 5641 #define HTT_SRING_SETUP_SW_INTR_MODE_M 0x00008000 5642 #define HTT_SRING_SETUP_SW_INTR_MODE_S 15 5643 #define HTT_SRING_SETUP_SW_INTR_MODE_GET(_var) \ 5644 (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \ 5645 HTT_SRING_SETUP_SW_INTR_MODE_S) 5646 #define HTT_SRING_SETUP_SW_INTR_MODE_SET(_var, _val) \ 5647 do { \ 5648 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \ 5649 ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \ 5650 } while (0) 5651 5652 #define HTT_SRING_SETUP_INTR_TIMER_TH_M 0xffff0000 5653 #define HTT_SRING_SETUP_INTR_TIMER_TH_S 16 5654 #define HTT_SRING_SETUP_INTR_TIMER_TH_GET(_var) \ 5655 (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \ 5656 HTT_SRING_SETUP_INTR_TIMER_TH_S) 5657 #define HTT_SRING_SETUP_INTR_TIMER_TH_SET(_var, _val) \ 5658 do { \ 5659 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \ 5660 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \ 5661 } while (0) 5662 5663 #define HTT_SRING_SETUP_INTR_LOW_TH_M 0x0000ffff 5664 #define HTT_SRING_SETUP_INTR_LOW_TH_S 0 5665 #define HTT_SRING_SETUP_INTR_LOW_TH_GET(_var) \ 5666 (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \ 5667 HTT_SRING_SETUP_INTR_LOW_TH_S) 5668 #define HTT_SRING_SETUP_INTR_LOW_TH_SET(_var, _val) \ 5669 do { \ 5670 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \ 5671 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \ 5672 } while (0) 5673 5674 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M 0x00070000 5675 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S 16 5676 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_GET(_var) \ 5677 (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \ 5678 HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S) 5679 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_SET(_var, _val) \ 5680 do { \ 5681 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \ 5682 ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \ 5683 } while (0) 5684 5685 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_M 0x00080000 5686 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_S 19 5687 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_GET(_var) \ 5688 (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \ 5689 HTT_SRING_SETUP_RESPONSE_REQUIRED_S) 5690 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_SET(_var, _val) \ 5691 do { \ 5692 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \ 5693 ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ 5694 } while (0) 5695 5696 5697 /** 5698 * @brief host -> target RX ring selection config message 5699 * 5700 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 5701 * 5702 * @details 5703 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 5704 * configure RXDMA rings. 5705 * The configuration is per ring based and includes both packet subtypes 5706 * and PPDU/MPDU TLVs. 5707 * 5708 * The message would appear as follows: 5709 * 5710 * |31 28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0| 5711 * |-----+--+--+--+--+-----------------+----+---+---+---+---------------| 5712 * |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 5713 * |-----------------------+-----+-----+--------------------------------| 5714 * |rsvd2|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | 5715 * |--------------------------------------------------------------------| 5716 * | packet_type_enable_flags_0 | 5717 * |--------------------------------------------------------------------| 5718 * | packet_type_enable_flags_1 | 5719 * |--------------------------------------------------------------------| 5720 * | packet_type_enable_flags_2 | 5721 * |--------------------------------------------------------------------| 5722 * | packet_type_enable_flags_3 | 5723 * |--------------------------------------------------------------------| 5724 * | tlv_filter_in_flags | 5725 * |-----------------------------------+--------------------------------| 5726 * | rx_header_offset | rx_packet_offset | 5727 * |-----------------------------------+--------------------------------| 5728 * | rx_mpdu_start_offset | rx_mpdu_end_offset | 5729 * |-----------------------------------+--------------------------------| 5730 * | rx_msdu_start_offset | rx_msdu_end_offset | 5731 * |-----------------------------------+--------------------------------| 5732 * | rsvd3 | rx_attention_offset | 5733 * |--------------------------------------------------------------------| 5734 * | rsvd4 | mo| fp| rx_drop_threshold | 5735 * | |ndp|ndp| | 5736 * |--------------------------------------------------------------------| 5737 * Where: 5738 * PS = pkt_swap 5739 * SS = status_swap 5740 * OV = rx_offsets_valid 5741 * DT = drop_thresh_valid 5742 * CLM = config_length_mgmt 5743 * CLC = config_length_ctrl 5744 * CLD = config_length_data 5745 * RXHDL = rx_hdr_len 5746 * RX = rxpcu_filter_enable_flag 5747 * The message is interpreted as follows: 5748 * dword0 - b'0:7 - msg_type: This will be set to 5749 * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG) 5750 * b'8:15 - pdev_id: 5751 * 0 (for rings at SOC/UMAC level), 5752 * 1/2/3 mac id (for rings at LMAC level) 5753 * b'16:23 - ring_id : Identify the ring to configure. 5754 * More details can be got from enum htt_srng_ring_id 5755 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 5756 * BUF_RING_CFG_0 defs within HW .h files, 5757 * e.g. wmac_top_reg_seq_hwioreg.h 5758 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 5759 * BUF_RING_CFG_0 defs within HW .h files, 5760 * e.g. wmac_top_reg_seq_hwioreg.h 5761 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 5762 * configuration fields are valid 5763 * b'27 - drop_thresh_valid (DT): flag to indicate if the 5764 * rx_drop_threshold field is valid 5765 * b'28 - rx_mon_global_en: Enable/Disable global register 5766 8 configuration in Rx monitor module. 5767 * b'29:31 - rsvd1: reserved for future use 5768 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 5769 * in byte units. 5770 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5771 * b'16:18 - config_length_mgmt (MGMT): 5772 * Represents the length of mpdu bytes for mgmt pkt. 5773 * valid values: 5774 * 001 - 64bytes 5775 * 010 - 128bytes 5776 * 100 - 256bytes 5777 * 111 - Full mpdu bytes 5778 * b'19:21 - config_length_ctrl (CTRL): 5779 * Represents the length of mpdu bytes for ctrl pkt. 5780 * valid values: 5781 * 001 - 64bytes 5782 * 010 - 128bytes 5783 * 100 - 256bytes 5784 * 111 - Full mpdu bytes 5785 * b'22:24 - config_length_data (DATA): 5786 * Represents the length of mpdu bytes for data pkt. 5787 * valid values: 5788 * 001 - 64bytes 5789 * 010 - 128bytes 5790 * 100 - 256bytes 5791 * 111 - Full mpdu bytes 5792 * b'25:26 - rx_hdr_len: 5793 * Specifies the number of bytes of recvd packet to copy 5794 * into the rx_hdr tlv. 5795 * supported values for now by host: 5796 * 01 - 64bytes 5797 * 10 - 128bytes 5798 * 11 - 256bytes 5799 * default - 128 bytes 5800 * b'27 - rxpcu_filter_enable_flag 5801 * For Scan Radio Host CPU utilization is very high. 5802 * In order to reduce CPU utilization we need to filter out 5803 * certain configured MAC frames. 5804 * To filter out configured MAC address frames, RxPCU should 5805 * be zero which means allow all frames for MD at RxOLE 5806 * host wil fiter out frames. 5807 * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out) 5808 * b'28:31 - rsvd2: Reserved for future use 5809 * dword2 - b'0:31 - packet_type_enable_flags_0: 5810 * Enable MGMT packet from 0b0000 to 0b1001 5811 * bits from low to high: FP, MD, MO - 3 bits 5812 * FP: Filter_Pass 5813 * MD: Monitor_Direct 5814 * MO: Monitor_Other 5815 * 10 mgmt subtypes * 3 bits -> 30 bits 5816 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 5817 * dword3 - b'0:31 - packet_type_enable_flags_1: 5818 * Enable MGMT packet from 0b1010 to 0b1111 5819 * bits from low to high: FP, MD, MO - 3 bits 5820 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 5821 * dword4 - b'0:31 - packet_type_enable_flags_2: 5822 * Enable CTRL packet from 0b0000 to 0b1001 5823 * bits from low to high: FP, MD, MO - 3 bits 5824 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 5825 * dword5 - b'0:31 - packet_type_enable_flags_3: 5826 * Enable CTRL packet from 0b1010 to 0b1111, 5827 * MCAST_DATA, UCAST_DATA, NULL_DATA 5828 * bits from low to high: FP, MD, MO - 3 bits 5829 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 5830 * dword6 - b'0:31 - tlv_filter_in_flags: 5831 * Filter in Attention/MPDU/PPDU/Header/User tlvs 5832 * Refer to CFG_TLV_FILTER_IN_FLAG defs 5833 * dword7 - b'0:15 - rx_packet_offset: rx_packet_offset in byte units 5834 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5835 * A value of 0 will be considered as ignore this config. 5836 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5837 * e.g. wmac_top_reg_seq_hwioreg.h 5838 * - b'16:31 - rx_header_offset: rx_header_offset in byte units 5839 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5840 * A value of 0 will be considered as ignore this config. 5841 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5842 * e.g. wmac_top_reg_seq_hwioreg.h 5843 * dword8 - b'0:15 - rx_mpdu_end_offset: rx_mpdu_end_offset in byte units 5844 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5845 * A value of 0 will be considered as ignore this config. 5846 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5847 * e.g. wmac_top_reg_seq_hwioreg.h 5848 * - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units 5849 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5850 * A value of 0 will be considered as ignore this config. 5851 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5852 * e.g. wmac_top_reg_seq_hwioreg.h 5853 * dword9 - b'0:15 - rx_msdu_end_offset: rx_msdu_end_offset in byte units 5854 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5855 * A value of 0 will be considered as ignore this config. 5856 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5857 * e.g. wmac_top_reg_seq_hwioreg.h 5858 * - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units 5859 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5860 * A value of 0 will be considered as ignore this config. 5861 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5862 * e.g. wmac_top_reg_seq_hwioreg.h 5863 * dword10- b'0:15 - rx_attention_offset: rx_attention_offset in byte units 5864 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5865 * A value of 0 will be considered as ignore this config. 5866 * Refer to BUF_RING_CFG_4 defs within HW .h files, 5867 * e.g. wmac_top_reg_seq_hwioreg.h 5868 * - b'16:31 - rsvd3 for future use 5869 * dword11- b'9:0 - rx_drop_threshold: Threshold configured in monitor mode 5870 * to source rings. Consumer drops packets if the available 5871 * words in the ring falls below the configured threshold 5872 * value. 5873 * - b'10 - fp_ndp: Flag to indicate FP NDP status tlv is subscribed 5874 * by host. 1 -> subscribed 5875 * - b'11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed 5876 * by host. 1 -> subscribed 5877 * - b'12 - fp_phy_err: Flag to indicate FP PHY status tlv is 5878 * subscribed by host. 1 -> subscribed 5879 * - b'13:14 - fp_phy_err_buf_src: This indicates the source ring 5880 * selection for the FP PHY ERR status tlv. 5881 * 0 - wbm2rxdma_buf_source_ring 5882 * 1 - fw2rxdma_buf_source_ring 5883 * 2 - sw2rxdma_buf_source_ring 5884 * 3 - no_buffer_ring 5885 * - b'15:16 - fp_phy_err_buf_dest: This indicates the destination ring 5886 * selection for the FP PHY ERR status tlv. 5887 * 0 - rxdma_release_ring 5888 * 1 - rxdma2fw_ring 5889 * 2 - rxdma2sw_ring 5890 * 3 - rxdma2reo_ring 5891 * - b'17:19 - pkt_type_en_msdu_or_mpdu_logging 5892 * b'17 - Enables MSDU/MPDU logging for frames of MGMT type 5893 * b'18 - Enables MSDU/MPDU logging for frames of CTRL type 5894 * b'19 - Enables MSDU/MPDU logging for frames of DATA type 5895 * - b'20 - dma_mpdu_mgmt: 1: MPDU level logging 5896 * 0: MSDU level logging 5897 * - b'21 - dma_mpdu_ctrl: 1: MPDU level logging 5898 * 0: MSDU level logging 5899 * - b'22 - dma_mpdu_data: 1: MPDU level logging 5900 * 0: MSDU level logging 5901 * - b'23 - word_mask_compaction: enable/disable word mask for 5902 * mpdu/msdu start/end tlvs 5903 * - b'24 - rbm_override_enable: enabling/disabling return buffer 5904 * manager override 5905 * - b'25:28 - rbm_override_val: return buffer manager override value 5906 * dword12- b'0:31 - phy_err_mask: This field is to select the fp phy errors 5907 * which have to be posted to host from phy. 5908 * Corresponding to errors defined in 5909 * phyrx_abort_request_reason enums 0 to 31. 5910 * Refer to RXPCU register definition header files for the 5911 * phyrx_abort_request_reason enum definition. 5912 * dword13- b'0:31 - phy_err_mask_cont: This field is to select the fp phy 5913 * errors which have to be posted to host from phy. 5914 * Corresponding to errors defined in 5915 * phyrx_abort_request_reason enums 32 to 63. 5916 * Refer to RXPCU register definition header files for the 5917 * phyrx_abort_request_reason enum definition. 5918 * dword14- b'0:15 - rx_mpdu_start_word_mask: word mask for rx mpdu start, 5919 * applicable if word mask enabled 5920 * - b'16:18 - rx_mpdu_end_word_mask: word mask value for rx mpdu end, 5921 * applicable if word mask enabled 5922 * - b'19:31 - rsvd7 5923 * dword15- b'0:16 - rx_msdu_end_word_mask 5924 * - b'17:31 - rsvd5 5925 * dword17- b'0 - en_rx_tlv_pkt_offset: 5926 * 0: RX_PKT TLV logging at offset 0 for the subsequent 5927 * buffer 5928 * 1: RX_PKT TLV logging at specified offset for the 5929 * subsequent buffer 5930 * b`15:1 - rx_pkt_tlv_offset: Qword offset for rx_packet TLVs. 5931 */ 5932 PREPACK struct htt_rx_ring_selection_cfg_t { 5933 A_UINT32 msg_type: 8, 5934 pdev_id: 8, 5935 ring_id: 8, 5936 status_swap: 1, 5937 pkt_swap: 1, 5938 rx_offsets_valid: 1, 5939 drop_thresh_valid: 1, 5940 rx_mon_global_en: 1, 5941 rsvd1: 3; 5942 A_UINT32 ring_buffer_size: 16, 5943 config_length_mgmt:3, 5944 config_length_ctrl:3, 5945 config_length_data:3, 5946 rx_hdr_len: 2, 5947 rxpcu_filter_enable_flag:1, 5948 rsvd2: 4; 5949 A_UINT32 packet_type_enable_flags_0; 5950 A_UINT32 packet_type_enable_flags_1; 5951 A_UINT32 packet_type_enable_flags_2; 5952 A_UINT32 packet_type_enable_flags_3; 5953 A_UINT32 tlv_filter_in_flags; 5954 A_UINT32 rx_packet_offset: 16, 5955 rx_header_offset: 16; 5956 A_UINT32 rx_mpdu_end_offset: 16, 5957 rx_mpdu_start_offset: 16; 5958 A_UINT32 rx_msdu_end_offset: 16, 5959 rx_msdu_start_offset: 16; 5960 A_UINT32 rx_attn_offset: 16, 5961 rsvd3: 16; 5962 A_UINT32 rx_drop_threshold: 10, 5963 fp_ndp: 1, 5964 mo_ndp: 1, 5965 fp_phy_err: 1, 5966 fp_phy_err_buf_src: 2, 5967 fp_phy_err_buf_dest: 2, 5968 pkt_type_enable_msdu_or_mpdu_logging:3, 5969 dma_mpdu_mgmt: 1, 5970 dma_mpdu_ctrl: 1, 5971 dma_mpdu_data: 1, 5972 word_mask_compaction_enable:1, 5973 rbm_override_enable: 1, 5974 rbm_override_val: 4, 5975 rsvd4: 3; 5976 A_UINT32 phy_err_mask; 5977 A_UINT32 phy_err_mask_cont; 5978 A_UINT32 rx_mpdu_start_word_mask:16, 5979 rx_mpdu_end_word_mask: 3, 5980 rsvd7: 13; 5981 A_UINT32 rx_msdu_end_word_mask: 17, 5982 rsvd5: 15; 5983 A_UINT32 en_rx_tlv_pkt_offset: 1, 5984 rx_pkt_tlv_offset: 15, 5985 rsvd6: 16; 5986 A_UINT32 rx_mpdu_start_word_mask_v2: 20, 5987 rx_mpdu_end_word_mask_v2: 8, 5988 rsvd8: 4; 5989 A_UINT32 rx_msdu_end_word_mask_v2: 20, 5990 rsvd9: 12; 5991 A_UINT32 rx_ppdu_end_usr_stats_word_mask_v2: 20, 5992 rsvd10: 12; 5993 A_UINT32 packet_type_enable_fpmo_flags0; 5994 A_UINT32 packet_type_enable_fpmo_flags1; 5995 } POSTPACK; 5996 5997 #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) 5998 5999 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 6000 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_S 8 6001 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_GET(_var) \ 6002 (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \ 6003 HTT_RX_RING_SELECTION_CFG_PDEV_ID_S) 6004 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_SET(_var, _val) \ 6005 do { \ 6006 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \ 6007 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \ 6008 } while (0) 6009 6010 #define HTT_RX_RING_SELECTION_CFG_RING_ID_M 0x00ff0000 6011 #define HTT_RX_RING_SELECTION_CFG_RING_ID_S 16 6012 #define HTT_RX_RING_SELECTION_CFG_RING_ID_GET(_var) \ 6013 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \ 6014 HTT_RX_RING_SELECTION_CFG_RING_ID_S) 6015 #define HTT_RX_RING_SELECTION_CFG_RING_ID_SET(_var, _val) \ 6016 do { \ 6017 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \ 6018 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \ 6019 } while (0) 6020 6021 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M 0x01000000 6022 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S 24 6023 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_GET(_var) \ 6024 (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \ 6025 HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S) 6026 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(_var, _val) \ 6027 do { \ 6028 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP, _val); \ 6029 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \ 6030 } while (0) 6031 6032 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M 0x02000000 6033 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S 25 6034 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_GET(_var) \ 6035 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \ 6036 HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S) 6037 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(_var, _val) \ 6038 do { \ 6039 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP, _val); \ 6040 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \ 6041 } while (0) 6042 6043 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M 0x04000000 6044 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S 26 6045 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \ 6046 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \ 6047 HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S) 6048 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \ 6049 do { \ 6050 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \ 6051 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \ 6052 } while (0) 6053 6054 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M 0x08000000 6055 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S 27 6056 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_GET(_var) \ 6057 (((_var) & HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M) >> \ 6058 HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S) 6059 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_SET(_var, _val) \ 6060 do { \ 6061 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID, _val); \ 6062 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \ 6063 } while (0) 6064 6065 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M 0x10000000 6066 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S 28 6067 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_GET(_var) \ 6068 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M) >> \ 6069 HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S) 6070 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_SET(_var, _val) \ 6071 do { \ 6072 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN, _val); \ 6073 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \ 6074 } while (0) 6075 6076 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff 6077 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 6078 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ 6079 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \ 6080 HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S) 6081 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 6082 do { \ 6083 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE, _val); \ 6084 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \ 6085 } while (0) 6086 6087 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 6088 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S 16 6089 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 6090 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M) >> \ 6091 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S) 6092 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 6093 do { \ 6094 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT, _val); \ 6095 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)); \ 6096 } while (0) 6097 6098 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 6099 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S 19 6100 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 6101 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M) >> \ 6102 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S) 6103 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 6104 do { \ 6105 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL, _val); \ 6106 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S)); \ 6107 } while (0) 6108 6109 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 6110 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S 22 6111 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 6112 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M) >> \ 6113 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S) 6114 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 6115 do { \ 6116 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA, _val); \ 6117 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S)); \ 6118 } while (0) 6119 6120 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000 6121 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25 6122 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \ 6123 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ 6124 HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) 6125 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \ 6126 do { \ 6127 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \ 6128 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\ 6129 } while(0) 6130 6131 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000 6132 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27 6133 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \ 6134 (((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \ 6135 HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S) 6136 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \ 6137 do { \ 6138 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \ 6139 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S));\ 6140 } while(0) 6141 6142 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff 6143 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0 6144 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \ 6145 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \ 6146 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S) 6147 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_SET(_var, _val) \ 6148 do { \ 6149 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, _val); \ 6150 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \ 6151 } while (0) 6152 6153 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M 0xffffffff 6154 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S 0 6155 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_GET(_var) \ 6156 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \ 6157 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S) 6158 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_SET(_var, _val) \ 6159 do { \ 6160 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val); \ 6161 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \ 6162 } while (0) 6163 6164 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M 0xffffffff 6165 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S 0 6166 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_GET(_var) \ 6167 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \ 6168 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S) 6169 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_SET(_var, _val) \ 6170 do { \ 6171 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val); \ 6172 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \ 6173 } while (0) 6174 6175 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M 0xffffffff 6176 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S 0 6177 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_GET(_var) \ 6178 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \ 6179 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S) 6180 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_SET(_var, _val) \ 6181 do { \ 6182 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val); \ 6183 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \ 6184 } while (0) 6185 6186 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M 0xffffffff 6187 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S 0 6188 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \ 6189 (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \ 6190 HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S) 6191 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_SET(_var, _val) \ 6192 do { \ 6193 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \ 6194 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \ 6195 } while (0) 6196 6197 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M 0x0000ffff 6198 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S 0 6199 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \ 6200 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \ 6201 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S) 6202 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \ 6203 do { \ 6204 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \ 6205 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \ 6206 } while (0) 6207 6208 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M 0xffff0000 6209 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S 16 6210 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \ 6211 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \ 6212 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S) 6213 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \ 6214 do { \ 6215 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \ 6216 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \ 6217 } while (0) 6218 6219 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M 0x0000ffff 6220 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S 0 6221 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \ 6222 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \ 6223 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S) 6224 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \ 6225 do { \ 6226 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \ 6227 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \ 6228 } while (0) 6229 6230 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M 0xffff0000 6231 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S 16 6232 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \ 6233 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \ 6234 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S) 6235 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \ 6236 do { \ 6237 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \ 6238 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \ 6239 } while (0) 6240 6241 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M 0x0000ffff 6242 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S 0 6243 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \ 6244 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \ 6245 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S) 6246 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \ 6247 do { \ 6248 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \ 6249 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \ 6250 } while (0) 6251 6252 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M 0xffff0000 6253 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S 16 6254 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \ 6255 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \ 6256 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S) 6257 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \ 6258 do { \ 6259 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \ 6260 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \ 6261 } while (0) 6262 6263 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M 0x0000ffff 6264 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S 0 6265 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \ 6266 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \ 6267 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S) 6268 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \ 6269 do { \ 6270 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \ 6271 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \ 6272 } while (0) 6273 6274 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M 0x000003ff 6275 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S 0 6276 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_GET(_var) \ 6277 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M) >> \ 6278 HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S) 6279 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(_var, _val) \ 6280 do { \ 6281 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD, _val); \ 6282 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \ 6283 } while (0) 6284 6285 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_M 0x00000400 6286 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_S 10 6287 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_GET(_var) \ 6288 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_NDP_M) >> \ 6289 HTT_RX_RING_SELECTION_CFG_FP_NDP_S) 6290 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_SET(_var, _val) \ 6291 do { \ 6292 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_NDP, _val); \ 6293 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_NDP_S)); \ 6294 } while (0) 6295 6296 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_M 0x00000800 6297 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_S 11 6298 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_GET(_var) \ 6299 (((_var) & HTT_RX_RING_SELECTION_CFG_MO_NDP_M) >> \ 6300 HTT_RX_RING_SELECTION_CFG_MO_NDP_S) 6301 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_SET(_var, _val) \ 6302 do { \ 6303 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_MO_NDP, _val); \ 6304 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \ 6305 } while (0) 6306 6307 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M 0x00001000 6308 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S 12 6309 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_GET(_var) \ 6310 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M) >> \ 6311 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S) 6312 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_SET(_var, _val) \ 6313 do { \ 6314 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR, _val); \ 6315 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)); \ 6316 } while (0) 6317 6318 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M 0x00006000 6319 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S 13 6320 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_GET(_var) \ 6321 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M) >> \ 6322 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S) 6323 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_SET(_var, _val) \ 6324 do { \ 6325 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC, _val); \ 6326 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)); \ 6327 } while (0) 6328 6329 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M 0x00018000 6330 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S 15 6331 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_GET(_var) \ 6332 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M) >> \ 6333 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S) 6334 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_SET(_var, _val) \ 6335 do { \ 6336 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST, _val); \ 6337 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)); \ 6338 } while (0) 6339 6340 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M 0x000E0000 6341 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S 17 6342 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_GET(_var) \ 6343 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M) >> \ 6344 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S) 6345 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_SET(_var, _val) \ 6346 do { \ 6347 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING, _val); \ 6348 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S)); \ 6349 } while (0) 6350 6351 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M 0x00100000 6352 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S 20 6353 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_GET(_var) \ 6354 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M) >> \ 6355 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S) 6356 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 6357 do { \ 6358 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT, _val); \ 6359 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S)); \ 6360 } while (0) 6361 6362 6363 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M 0x00200000 6364 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S 21 6365 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_GET(_var) \ 6366 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M) >> \ 6367 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S) 6368 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 6369 do { \ 6370 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL, _val); \ 6371 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S)); \ 6372 } while (0) 6373 6374 6375 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M 0x00400000 6376 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S 22 6377 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_GET(_var) \ 6378 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M) >> \ 6379 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S) 6380 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 6381 do { \ 6382 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA, _val); \ 6383 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S)); \ 6384 } while (0) 6385 6386 6387 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00800000 6388 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S 23 6389 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 6390 (((_var) & HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 6391 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S) 6392 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 6393 do { \ 6394 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 6395 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 6396 } while (0) 6397 6398 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M 0x01000000 6399 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S 24 6400 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_GET(_var) \ 6401 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M) >> \ 6402 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S) 6403 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_SET(_var, _val) \ 6404 do { \ 6405 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE, _val);\ 6406 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S)); \ 6407 } while (0) 6408 6409 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M 0x1E000000 6410 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S 25 6411 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_GET(_var) \ 6412 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M) >> \ 6413 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S) 6414 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_SET(_var, _val) \ 6415 do { \ 6416 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE, _val);\ 6417 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S));\ 6418 } while (0) 6419 6420 6421 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M 0xffffffff 6422 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S 0 6423 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_GET(_var) \ 6424 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M) >> \ 6425 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S) 6426 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_SET(_var, _val) \ 6427 do { \ 6428 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK, _val); \ 6429 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)); \ 6430 } while (0) 6431 6432 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M 0xffffffff 6433 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S 0 6434 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_GET(_var) \ 6435 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M) >> \ 6436 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S) 6437 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_SET(_var, _val) \ 6438 do { \ 6439 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT, _val); \ 6440 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)); \ 6441 } while (0) 6442 6443 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M 0x0000FFFF 6444 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S 0 6445 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_GET(_var) \ 6446 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M)>> \ 6447 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S) 6448 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(_var, _val) \ 6449 do { \ 6450 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK, _val);\ 6451 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \ 6452 } while (0) 6453 6454 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0x00070000 6455 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S 16 6456 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_GET(_var) \ 6457 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M)>> \ 6458 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S) 6459 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(_var, _val) \ 6460 do { \ 6461 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK, _val);\ 6462 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)); \ 6463 } while (0) 6464 6465 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M 0x0001FFFF 6466 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S 0 6467 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_GET(_var) \ 6468 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M)>> \ 6469 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S) 6470 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(_var, _val) \ 6471 do { \ 6472 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK, _val);\ 6473 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S)); \ 6474 } while (0) 6475 6476 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M 0x00000001 6477 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S 0 6478 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_GET(_var) \ 6479 (((_var) & HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M)>> \ 6480 HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S) 6481 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6482 do { \ 6483 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET, _val); \ 6484 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S)); \ 6485 } while (0) 6486 6487 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M 0x0000FFFE 6488 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S 1 6489 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_GET(_var) \ 6490 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M)>> \ 6491 HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S) 6492 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6493 do { \ 6494 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET, _val); \ 6495 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)); \ 6496 } while (0) 6497 6498 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M 0x000FFFFF 6499 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S 0 6500 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_GET(_var) \ 6501 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M)>> \ 6502 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S) 6503 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_SET(_var, _val) \ 6504 do { \ 6505 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2, _val);\ 6506 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)); \ 6507 } while (0) 6508 6509 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M 0x0FF00000 6510 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S 20 6511 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_GET(_var) \ 6512 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M)>> \ 6513 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S) 6514 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_SET(_var, _val) \ 6515 do { \ 6516 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2, _val);\ 6517 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)); \ 6518 } while (0) 6519 6520 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M 0x000FFFFF 6521 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S 0 6522 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_GET(_var) \ 6523 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M)>> \ 6524 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S) 6525 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_SET(_var, _val) \ 6526 do { \ 6527 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2, _val);\ 6528 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)); \ 6529 } while (0) 6530 6531 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M 0x000FFFFF 6532 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S 0 6533 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_GET(_var) \ 6534 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M)>> \ 6535 HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S) 6536 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_SET(_var, _val) \ 6537 do { \ 6538 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2, _val);\ 6539 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)); \ 6540 } while (0) 6541 6542 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M 0xFFFFFFFF 6543 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S 0 6544 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_GET(_var) \ 6545 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M)>> \ 6546 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S) 6547 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_SET(_var, _val) \ 6548 do { \ 6549 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0, _val); \ 6550 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)); \ 6551 } while (0) 6552 6553 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M 0xFFFFFFFF 6554 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S 0 6555 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_GET(_var) \ 6556 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M)>> \ 6557 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S) 6558 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_SET(_var, _val) \ 6559 do { \ 6560 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1, _val); \ 6561 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \ 6562 } while (0) 6563 6564 /* 6565 * Subtype based MGMT frames enable bits. 6566 * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other 6567 */ 6568 /* association request */ 6569 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M 0x00000001 6570 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_S 0 6571 6572 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M 0x00000002 6573 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_S 1 6574 6575 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M 0x00000004 6576 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_S 2 6577 6578 /* association response */ 6579 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M 0x00000008 6580 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_S 3 6581 6582 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M 0x00000010 6583 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_S 4 6584 6585 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M 0x00000020 6586 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_S 5 6587 6588 /* Reassociation request */ 6589 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M 0x00000040 6590 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_S 6 6591 6592 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M 0x00000080 6593 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_S 7 6594 6595 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M 0x00000100 6596 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_S 8 6597 6598 /* Reassociation response */ 6599 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M 0x00000200 6600 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_S 9 6601 6602 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M 0x00000400 6603 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_S 10 6604 6605 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M 0x00000800 6606 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_S 11 6607 6608 /* Probe request */ 6609 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M 0x00001000 6610 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_S 12 6611 6612 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M 0x00002000 6613 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_S 13 6614 6615 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M 0x00004000 6616 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_S 14 6617 6618 /* Probe response */ 6619 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M 0x00008000 6620 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_S 15 6621 6622 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M 0x00010000 6623 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_S 16 6624 6625 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M 0x00020000 6626 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_S 17 6627 6628 /* Timing Advertisement */ 6629 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M 0x00040000 6630 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_S 18 6631 6632 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M 0x00080000 6633 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_S 19 6634 6635 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M 0x00100000 6636 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_S 20 6637 6638 /* Reserved */ 6639 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M 0x00200000 6640 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_S 21 6641 6642 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M 0x00400000 6643 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_S 22 6644 6645 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M 0x00800000 6646 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23 6647 6648 /* Beacon */ 6649 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000 6650 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24 6651 6652 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000 6653 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25 6654 6655 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000 6656 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26 6657 6658 /* ATIM */ 6659 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000 6660 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27 6661 6662 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000 6663 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28 6664 6665 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000 6666 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29 6667 6668 /* Disassociation */ 6669 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M 0x00000001 6670 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_S 0 6671 6672 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M 0x00000002 6673 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_S 1 6674 6675 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M 0x00000004 6676 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_S 2 6677 6678 /* Authentication */ 6679 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M 0x00000008 6680 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_S 3 6681 6682 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M 0x00000010 6683 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_S 4 6684 6685 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M 0x00000020 6686 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_S 5 6687 6688 /* Deauthentication */ 6689 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M 0x00000040 6690 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_S 6 6691 6692 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M 0x00000080 6693 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_S 7 6694 6695 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M 0x00000100 6696 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_S 8 6697 6698 /* Action */ 6699 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M 0x00000200 6700 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_S 9 6701 6702 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M 0x00000400 6703 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_S 10 6704 6705 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M 0x00000800 6706 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_S 11 6707 6708 /* Action No Ack */ 6709 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M 0x00001000 6710 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_S 12 6711 6712 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M 0x00002000 6713 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_S 13 6714 6715 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M 0x00004000 6716 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_S 14 6717 6718 /* Reserved */ 6719 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M 0x00008000 6720 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_S 15 6721 6722 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M 0x00010000 6723 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_S 16 6724 6725 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M 0x00020000 6726 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_S 17 6727 6728 /* 6729 * Subtype based CTRL frames enable bits. 6730 * FP: Filter_Pass, MD: Monitor_Direct, MO: Monitor_Other 6731 */ 6732 /* Reserved */ 6733 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M 0x00000001 6734 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_S 0 6735 6736 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M 0x00000002 6737 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_S 1 6738 6739 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M 0x00000004 6740 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_S 2 6741 6742 /* Reserved */ 6743 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M 0x00000008 6744 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_S 3 6745 6746 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M 0x00000010 6747 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_S 4 6748 6749 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M 0x00000020 6750 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_S 5 6751 6752 /* Reserved */ 6753 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M 0x00000040 6754 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_S 6 6755 6756 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M 0x00000080 6757 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_S 7 6758 6759 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M 0x00000100 6760 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_S 8 6761 6762 /* Reserved */ 6763 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M 0x00000200 6764 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_S 9 6765 6766 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M 0x00000400 6767 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_S 10 6768 6769 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M 0x00000800 6770 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_S 11 6771 6772 /* Reserved */ 6773 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M 0x00001000 6774 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_S 12 6775 6776 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M 0x00002000 6777 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_S 13 6778 6779 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M 0x00004000 6780 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_S 14 6781 6782 /* Reserved */ 6783 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M 0x00008000 6784 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_S 15 6785 6786 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M 0x00010000 6787 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_S 16 6788 6789 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M 0x00020000 6790 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_S 17 6791 6792 /* Reserved */ 6793 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M 0x00040000 6794 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_S 18 6795 6796 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M 0x00080000 6797 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_S 19 6798 6799 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M 0x00100000 6800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_S 20 6801 6802 /* Control Wrapper */ 6803 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M 0x00200000 6804 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_S 21 6805 6806 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M 0x00400000 6807 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_S 22 6808 6809 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M 0x00800000 6810 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_S 23 6811 6812 /* Block Ack Request */ 6813 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M 0x01000000 6814 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_S 24 6815 6816 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M 0x02000000 6817 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_S 25 6818 6819 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M 0x04000000 6820 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_S 26 6821 6822 /* Block Ack*/ 6823 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M 0x08000000 6824 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_S 27 6825 6826 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M 0x10000000 6827 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_S 28 6828 6829 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M 0x20000000 6830 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_S 29 6831 6832 /* PS-POLL */ 6833 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M 0x00000001 6834 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_S 0 6835 6836 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M 0x00000002 6837 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_S 1 6838 6839 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M 0x00000004 6840 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_S 2 6841 6842 /* RTS */ 6843 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M 0x00000008 6844 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_S 3 6845 6846 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M 0x00000010 6847 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_S 4 6848 6849 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M 0x00000020 6850 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_S 5 6851 6852 /* CTS */ 6853 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M 0x00000040 6854 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_S 6 6855 6856 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M 0x00000080 6857 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_S 7 6858 6859 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M 0x00000100 6860 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_S 8 6861 6862 /* ACK */ 6863 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M 0x00000200 6864 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_S 9 6865 6866 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M 0x00000400 6867 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_S 10 6868 6869 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M 0x00000800 6870 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_S 11 6871 6872 /* CF-END */ 6873 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M 0x00001000 6874 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_S 12 6875 6876 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M 0x00002000 6877 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_S 13 6878 6879 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M 0x00004000 6880 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_S 14 6881 6882 /* CF-END + CF-ACK */ 6883 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M 0x00008000 6884 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_S 15 6885 6886 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M 0x00010000 6887 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_S 16 6888 6889 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M 0x00020000 6890 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_S 17 6891 6892 /* Multicast data */ 6893 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M 0x00040000 6894 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_S 18 6895 6896 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M 0x00080000 6897 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_S 19 6898 6899 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M 0x00100000 6900 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_S 20 6901 6902 /* Unicast data */ 6903 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M 0x00200000 6904 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_S 21 6905 6906 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M 0x00400000 6907 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_S 22 6908 6909 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M 0x00800000 6910 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_S 23 6911 6912 /* NULL data */ 6913 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M 0x01000000 6914 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_S 24 6915 6916 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M 0x02000000 6917 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_S 25 6918 6919 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000 6920 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26 6921 6922 /* FPMO mode flags */ 6923 /* MGMT */ 6924 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_M 0x00000001 6925 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_S 0 6926 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_M 0x00000002 6927 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_S 1 6928 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_M 0x00000004 6929 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_S 2 6930 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_M 0x00000008 6931 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_S 3 6932 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_M 0x00000010 6933 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_S 4 6934 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_M 0x00000020 6935 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_S 5 6936 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_M 0x00000040 6937 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_S 6 6938 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_M 0x00000080 6939 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_S 7 6940 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_M 0x00000100 6941 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_S 8 6942 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_M 0x00000200 6943 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_S 9 6944 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_M 0x00000400 6945 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_S 10 6946 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_M 0x00000800 6947 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_S 11 6948 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_M 0x00001000 6949 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_S 12 6950 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_M 0x00002000 6951 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_S 13 6952 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_M 0x00004000 6953 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_S 14 6954 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_M 0x00008000 6955 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_S 15 6956 6957 /* CTRL */ 6958 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_M 0x00010000 6959 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_S 16 6960 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_M 0x00020000 6961 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_S 17 6962 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_M 0x00040000 6963 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_S 18 6964 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_M 0x00080000 6965 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_S 19 6966 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_M 0x00100000 6967 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_S 20 6968 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_M 0x00200000 6969 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_S 21 6970 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_M 0x00400000 6971 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_S 22 6972 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_M 0x00800000 6973 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_S 23 6974 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_M 0x01000000 6975 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_S 24 6976 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_M 0x02000000 6977 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_S 25 6978 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_M 0x04000000 6979 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_S 26 6980 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_M 0x08000000 6981 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_S 27 6982 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_M 0x10000000 6983 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_S 28 6984 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_M 0x20000000 6985 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_S 29 6986 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_M 0x40000000 6987 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_S 30 6988 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_M 0x80000000 6989 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_S 31 6990 6991 /* DATA */ 6992 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_M 0x00000001 6993 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_S 0 6994 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_M 0x00000002 6995 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_S 1 6996 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_M 0x00000004 6997 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_S 2 6998 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_M 0x00000008 6999 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_S 3 7000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_M 0x00000010 7001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_S 4 7002 7003 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \ 7004 do { \ 7005 HTT_CHECK_SET_VAL(httsym, value); \ 7006 (word) |= (value) << httsym##_S; \ 7007 } while (0) 7008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word, httsym) \ 7009 (((word) & httsym##_M) >> httsym##_S) 7010 7011 #define htt_rx_ring_pkt_enable_subtype_set( \ 7012 word, flag, mode, type, subtype, val) \ 7013 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET( \ 7014 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype, val) 7015 7016 #define htt_rx_ring_pkt_enable_subtype_get( \ 7017 word, flag, mode, type, subtype) \ 7018 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET( \ 7019 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype) 7020 7021 /* Definition to filter in TLVs */ 7022 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001 7023 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0 7024 7025 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002 7026 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1 7027 7028 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004 7029 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2 7030 7031 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008 7032 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3 7033 7034 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010 7035 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4 7036 7037 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M 0x00000020 7038 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5 7039 7040 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040 7041 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6 7042 7043 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080 7044 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7 7045 7046 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100 7047 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8 7048 7049 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200 7050 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9 7051 7052 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M 0x00000400 7053 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10 7054 7055 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800 7056 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_S 11 7057 7058 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M 0x00001000 7059 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S 12 7060 7061 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_M 0x00002000 7062 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_S 13 7063 7064 #define HTT_RX_RING_TLV_ENABLE_SET(word, httsym, enable) \ 7065 do { \ 7066 HTT_CHECK_SET_VAL(httsym, enable); \ 7067 (word) |= (enable) << httsym##_S; \ 7068 } while (0) 7069 #define HTT_RX_RING_TLV_ENABLE_GET(word, httsym) \ 7070 (((word) & httsym##_M) >> httsym##_S) 7071 7072 #define htt_rx_ring_tlv_filter_in_enable_set(word, tlv, enable) \ 7073 HTT_RX_RING_TLV_ENABLE_SET( \ 7074 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable) 7075 7076 #define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \ 7077 HTT_RX_RING_TLV_ENABLE_GET( \ 7078 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv) 7079 7080 /** 7081 * @brief host -> target TX monitor config message 7082 * 7083 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_MONITOR_CFG 7084 * 7085 * @details 7086 * HTT_H2T_MSG_TYPE_TX_MONITOR_CFG message is sent by host to 7087 * configure RXDMA rings. 7088 * The configuration is per ring based and includes both packet types 7089 * and PPDU/MPDU TLVs. 7090 * 7091 * The message would appear as follows: 7092 * 7093 * |31 26|25|24|23 22|21|20|19|18 16|15|14|13|12|11|10|9|8|7|6|5|4|3|2 0| 7094 * |--------+--+--+-----+--+--+--+-----+--+--+--+--+--+--+-+-+-+-+-+-+-+----| 7095 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 7096 * |-----------+--------+--------+-----+------------------------------------| 7097 * | rsvd2 | DATA | CTRL | MGMT| ring_buffer_size | 7098 * |--------------------------------------+--+--+--+--+--+-+-+-+-+-+-+-+----| 7099 * | | M| M| M| M| M|M|M|M|M|M|M|M| | 7100 * | | S| S| S| P| P|P|S|S|S|P|P|P| | 7101 * | | E| E| E| E| E|E|S|S|S|S|S|S| | 7102 * | rsvd3 | D| C| M| D| C|M|D|C|M|D|C|M| E | 7103 * |------------------------------------------------------------------------| 7104 * | tlv_filter_mask_in0 | 7105 * |------------------------------------------------------------------------| 7106 * | tlv_filter_mask_in1 | 7107 * |------------------------------------------------------------------------| 7108 * | tlv_filter_mask_in2 | 7109 * |------------------------------------------------------------------------| 7110 * | tlv_filter_mask_in3 | 7111 * |-----------------+-----------------+---------------------+--------------| 7112 * | tx_msdu_start_wm| tx_queue_ext_wm | tx_peer_entry_wm |tx_fes_stup_wm| 7113 * |------------------------------------------------------------------------| 7114 * | pcu_ppdu_setup_word_mask | 7115 * |--------------------+--+--+--+-----+---------------------+--------------| 7116 * | rsvd4 | D| C| M| PT | rxpcu_usrsetp_wm |tx_mpdu_srt_wm| 7117 * |------------------------------------------------------------------------| 7118 * 7119 * Where: 7120 * PS = pkt_swap 7121 * SS = status_swap 7122 * The message is interpreted as follows: 7123 * dword0 - b'0:7 - msg_type: This will be set to 7124 * 0x1b (HTT_H2T_MSG_TYPE_TX_MONITOR_CFG) 7125 * b'8:15 - pdev_id: 7126 * 0 (for rings at SOC level), 7127 * 1/2/3 mac id (for rings at LMAC level) 7128 * b'16:23 - ring_id : Identify the ring to configure. 7129 * More details can be got from enum htt_srng_ring_id 7130 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 7131 * BUF_RING_CFG_0 defs within HW .h files, 7132 * e.g. wmac_top_reg_seq_hwioreg.h 7133 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 7134 * BUF_RING_CFG_0 defs within HW .h files, 7135 * e.g. wmac_top_reg_seq_hwioreg.h 7136 * b'26 - tx_mon_global_en: Enable/Disable global register 7137 * configuration in Tx monitor module. 7138 * b'27:31 - rsvd1: reserved for future use 7139 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 7140 * in byte units. 7141 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 7142 * b'16:18 - config_length_mgmt(MGMT) for MGMT: Each bit set represent 7143 * 64, 128, 256. 7144 * If all 3 bits are set config length is > 256. 7145 * if val is '0', then ignore this field. 7146 * b'19:21 - config_length_ctrl(CTRL) for CTRL: Each bit set represent 7147 * 64, 128, 256. 7148 * If all 3 bits are set config length is > 256. 7149 * if val is '0', then ignore this field. 7150 * b'22:24 - config_length_data(DATA) for DATA: Each bit set represent 7151 * 64, 128, 256. 7152 * If all 3 bits are set config length is > 256. 7153 * If val is '0', then ignore this field. 7154 * - b'25:31 - rsvd2: Reserved for future use 7155 * dword2 - b'0:2 - packet_type_enable_flags(E): MGMT, CTRL, DATA 7156 * b'3 - filter_in_tx_mpdu_start_mgmt(MPSM): 7157 * If packet_type_enable_flags is '1' for MGMT type, 7158 * monitor will ignore this bit and allow this TLV. 7159 * If packet_type_enable_flags is '0' for MGMT type, 7160 * monitor will use this bit to enable/disable logging 7161 * of this TLV. 7162 * b'4 - filter_in_tx_mpdu_start_ctrl(MPSC) 7163 * If packet_type_enable_flags is '1' for CTRL type, 7164 * monitor will ignore this bit and allow this TLV. 7165 * If packet_type_enable_flags is '0' for CTRL type, 7166 * monitor will use this bit to enable/disable logging 7167 * of this TLV. 7168 * b'5 - filter_in_tx_mpdu_start_data(MPSD) 7169 * If packet_type_enable_flags is '1' for DATA type, 7170 * monitor will ignore this bit and allow this TLV. 7171 * If packet_type_enable_flags is '0' for DATA type, 7172 * monitor will use this bit to enable/disable logging 7173 * of this TLV. 7174 * b'6 - filter_in_tx_msdu_start_mgmt(MSSM) 7175 * If packet_type_enable_flags is '1' for MGMT type, 7176 * monitor will ignore this bit and allow this TLV. 7177 * If packet_type_enable_flags is '0' for MGMT type, 7178 * monitor will use this bit to enable/disable logging 7179 * of this TLV. 7180 * b'7 - filter_in_tx_msdu_start_ctrl(MSSC) 7181 * If packet_type_enable_flags is '1' for CTRL type, 7182 * monitor will ignore this bit and allow this TLV. 7183 * If packet_type_enable_flags is '0' for CTRL type, 7184 * monitor will use this bit to enable/disable logging 7185 * of this TLV. 7186 * b'8 - filter_in_tx_msdu_start_data(MSSD) 7187 * If packet_type_enable_flags is '1' for DATA type, 7188 * monitor will ignore this bit and allow this TLV. 7189 * If packet_type_enable_flags is '0' for DATA type, 7190 * monitor will use this bit to enable/disable logging 7191 * of this TLV. 7192 * b'9 - filter_in_tx_mpdu_end_mgmt(MPEM) 7193 * If packet_type_enable_flags is '1' for MGMT type, 7194 * monitor will ignore this bit and allow this TLV. 7195 * If packet_type_enable_flags is '0' for MGMT type, 7196 * monitor will use this bit to enable/disable logging 7197 * of this TLV. 7198 * If filter_in_TX_MPDU_START = 1 it is recommended 7199 * to set this bit. 7200 * b'10 - filter_in_tx_mpdu_end_ctrl(MPEC) 7201 * If packet_type_enable_flags is '1' for CTRL type, 7202 * monitor will ignore this bit and allow this TLV. 7203 * If packet_type_enable_flags is '0' for CTRL type, 7204 * monitor will use this bit to enable/disable logging 7205 * of this TLV. 7206 * If filter_in_TX_MPDU_START = 1 it is recommended 7207 * to set this bit. 7208 * b'11 - filter_in_tx_mpdu_end_data(MPED) 7209 * If packet_type_enable_flags is '1' for DATA type, 7210 * monitor will ignore this bit and allow this TLV. 7211 * If packet_type_enable_flags is '0' for DATA type, 7212 * monitor will use this bit to enable/disable logging 7213 * of this TLV. 7214 * If filter_in_TX_MPDU_START = 1 it is recommended 7215 * to set this bit. 7216 * b'12 - filter_in_tx_msdu_end_mgmt(MSEM) 7217 * If packet_type_enable_flags is '1' for MGMT type, 7218 * monitor will ignore this bit and allow this TLV. 7219 * If packet_type_enable_flags is '0' for MGMT type, 7220 * monitor will use this bit to enable/disable logging 7221 * of this TLV. 7222 * If filter_in_TX_MSDU_START = 1 it is recommended 7223 * to set this bit. 7224 * b'13 - filter_in_tx_msdu_end_ctrl(MSEC) 7225 * If packet_type_enable_flags is '1' for CTRL type, 7226 * monitor will ignore this bit and allow this TLV. 7227 * If packet_type_enable_flags is '0' for CTRL type, 7228 * monitor will use this bit to enable/disable logging 7229 * of this TLV. 7230 * If filter_in_TX_MSDU_START = 1 it is recommended 7231 * to set this bit. 7232 * b'14 - filter_in_tx_msdu_end_data(MSED) 7233 * If packet_type_enable_flags is '1' for DATA type, 7234 * monitor will ignore this bit and allow this TLV. 7235 * If packet_type_enable_flags is '0' for DATA type, 7236 * monitor will use this bit to enable/disable logging 7237 * of this TLV. 7238 * If filter_in_TX_MSDU_START = 1 it is recommended 7239 * to set this bit. 7240 * b'15:31 - rsvd3: Reserved for future use 7241 * dword3 - b'0:31 - tlv_filter_mask_in0: 7242 * dword4 - b'0:31 - tlv_filter_mask_in1: 7243 * dword5 - b'0:31 - tlv_filter_mask_in2: 7244 * dword6 - b'0:31 - tlv_filter_mask_in3: 7245 * dword7 - b'0:7 - tx_fes_setup_word_mask: 7246 * - b'8:15 - tx_peer_entry_word_mask: 7247 * - b'16:23 - tx_queue_ext_word_mask: 7248 * - b'24:31 - tx_msdu_start_word_mask: 7249 * dword8 - b'0:31 - pcu_ppdu_setup_word_mask: 7250 * dword9 - b'0:7 - tx_mpdu_start_word_mask: 7251 * - b'8:15 - rxpcu_user_setup_word_mask: 7252 * - b'16:18 - pkt_type_enable_msdu_or_mpdu_logging (PT): 7253 * MGMT, CTRL, DATA 7254 * - b'19 - dma_mpdu_mgmt(M): For MGMT 7255 * 0 -> MSDU level logging is enabled 7256 * (valid only if bit is set in 7257 * pkt_type_enable_msdu_or_mpdu_logging) 7258 * 1 -> MPDU level logging is enabled 7259 * (valid only if bit is set in 7260 * pkt_type_enable_msdu_or_mpdu_logging) 7261 * - b'20 - dma_mpdu_ctrl(C) : For CTRL 7262 * 0 -> MSDU level logging is enabled 7263 * (valid only if bit is set in 7264 * pkt_type_enable_msdu_or_mpdu_logging) 7265 * 1 -> MPDU level logging is enabled 7266 * (valid only if bit is set in 7267 * pkt_type_enable_msdu_or_mpdu_logging) 7268 * - b'21 - dma_mpdu_data(D) : For DATA 7269 * 0 -> MSDU level logging is enabled 7270 * (valid only if bit is set in 7271 * pkt_type_enable_msdu_or_mpdu_logging) 7272 * 1 -> MPDU level logging is enabled 7273 * (valid only if bit is set in 7274 * pkt_type_enable_msdu_or_mpdu_logging) 7275 * - b'22:31 - rsvd4 for future use 7276 */ 7277 PREPACK struct htt_tx_monitor_cfg_t { 7278 A_UINT32 msg_type: 8, 7279 pdev_id: 8, 7280 ring_id: 8, 7281 status_swap: 1, 7282 pkt_swap: 1, 7283 tx_mon_global_en: 1, 7284 rsvd1: 5; 7285 A_UINT32 ring_buffer_size: 16, 7286 config_length_mgmt: 3, 7287 config_length_ctrl: 3, 7288 config_length_data: 3, 7289 rsvd2: 7; 7290 A_UINT32 pkt_type_enable_flags: 3, 7291 filter_in_tx_mpdu_start_mgmt: 1, 7292 filter_in_tx_mpdu_start_ctrl: 1, 7293 filter_in_tx_mpdu_start_data: 1, 7294 filter_in_tx_msdu_start_mgmt: 1, 7295 filter_in_tx_msdu_start_ctrl: 1, 7296 filter_in_tx_msdu_start_data: 1, 7297 filter_in_tx_mpdu_end_mgmt: 1, 7298 filter_in_tx_mpdu_end_ctrl: 1, 7299 filter_in_tx_mpdu_end_data: 1, 7300 filter_in_tx_msdu_end_mgmt: 1, 7301 filter_in_tx_msdu_end_ctrl: 1, 7302 filter_in_tx_msdu_end_data: 1, 7303 word_mask_compaction_enable: 1, 7304 rsvd3: 16; 7305 A_UINT32 tlv_filter_mask_in0; 7306 A_UINT32 tlv_filter_mask_in1; 7307 A_UINT32 tlv_filter_mask_in2; 7308 A_UINT32 tlv_filter_mask_in3; 7309 A_UINT32 tx_fes_setup_word_mask: 8, 7310 tx_peer_entry_word_mask: 8, 7311 tx_queue_ext_word_mask: 8, 7312 tx_msdu_start_word_mask: 8; 7313 A_UINT32 pcu_ppdu_setup_word_mask; 7314 A_UINT32 tx_mpdu_start_word_mask: 8, 7315 rxpcu_user_setup_word_mask: 8, 7316 pkt_type_enable_msdu_or_mpdu_logging: 3, 7317 dma_mpdu_mgmt: 1, 7318 dma_mpdu_ctrl: 1, 7319 dma_mpdu_data: 1, 7320 rsvd4: 10; 7321 A_UINT32 tx_queue_ext_v2_word_mask: 12, 7322 tx_peer_entry_v2_word_mask: 12, 7323 rsvd5: 8; 7324 A_UINT32 fes_status_end_word_mask: 16, 7325 response_end_status_word_mask: 16; 7326 A_UINT32 fes_status_prot_word_mask: 11, 7327 rsvd6: 21; 7328 } POSTPACK; 7329 7330 #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t)) 7331 7332 #define HTT_TX_MONITOR_CFG_PDEV_ID_M 0x0000ff00 7333 #define HTT_TX_MONITOR_CFG_PDEV_ID_S 8 7334 #define HTT_TX_MONITOR_CFG_PDEV_ID_GET(_var) \ 7335 (((_var) & HTT_TX_MONITOR_CFG_PDEV_ID_M) >> \ 7336 HTT_TX_MONITOR_CFG_PDEV_ID_S) 7337 #define HTT_TX_MONITOR_CFG_PDEV_ID_SET(_var, _val) \ 7338 do { \ 7339 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDEV_ID, _val); \ 7340 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDEV_ID_S)); \ 7341 } while (0) 7342 7343 #define HTT_TX_MONITOR_CFG_RING_ID_M 0x00ff0000 7344 #define HTT_TX_MONITOR_CFG_RING_ID_S 16 7345 #define HTT_TX_MONITOR_CFG_RING_ID_GET(_var) \ 7346 (((_var) & HTT_TX_MONITOR_CFG_RING_ID_M) >> \ 7347 HTT_TX_MONITOR_CFG_RING_ID_S) 7348 #define HTT_TX_MONITOR_CFG_RING_ID_SET(_var, _val) \ 7349 do { \ 7350 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_ID, _val); \ 7351 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_ID_S)); \ 7352 } while (0) 7353 7354 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_M 0x01000000 7355 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_S 24 7356 #define HTT_TX_MONITOR_CFG_STATUS_TLV_GET(_var) \ 7357 (((_var) & HTT_TX_MONITOR_CFG_STATUS_SWAP_M) >> \ 7358 HTT_TX_MONITOR_CFG_STATUS_SWAP_S) 7359 #define HTT_TX_MONITOR_CFG_STATUS_TLV_SET(_var, _val) \ 7360 do { \ 7361 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_STATUS_SWAP, _val); \ 7362 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_STATUS_SWAP_S)); \ 7363 } while (0) 7364 7365 #define HTT_TX_MONITOR_CFG_PKT_SWAP_M 0x02000000 7366 #define HTT_TX_MONITOR_CFG_PKT_SWAP_S 25 7367 #define HTT_TX_MONITOR_CFG_PKT_TLV_GET(_var) \ 7368 (((_var) & HTT_TX_MONITOR_CFG_PKT_SWAP_M) >> \ 7369 HTT_TX_MONITOR_CFG_PKT_SWAP_S) 7370 #define HTT_TX_MONITOR_CFG_PKT_TLV_SET(_var, _val) \ 7371 do { \ 7372 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_SWAP, _val); \ 7373 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \ 7374 } while (0) 7375 7376 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M 0x04000000 7377 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S 26 7378 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_GET(_var) \ 7379 (((_var) & HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M) >> \ 7380 HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S) 7381 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_SET(_var, _val) \ 7382 do { \ 7383 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN, _val); \ 7384 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)); \ 7385 } while (0) 7386 7387 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff 7388 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 7389 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ 7390 (((_var) & HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M) >> \ 7391 HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S) 7392 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 7393 do { \ 7394 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE, _val); \ 7395 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)); \ 7396 } while (0) 7397 7398 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 7399 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S 16 7400 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 7401 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M) >> \ 7402 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S) 7403 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 7404 do { \ 7405 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT, _val); \ 7406 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \ 7407 } while (0) 7408 7409 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 7410 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S 19 7411 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 7412 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M) >> \ 7413 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S) 7414 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 7415 do { \ 7416 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL, _val); \ 7417 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)); \ 7418 } while (0) 7419 7420 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 7421 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S 22 7422 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 7423 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M) >> \ 7424 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S) 7425 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 7426 do { \ 7427 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA, _val); \ 7428 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)); \ 7429 } while (0) 7430 7431 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M 0x00000007 7432 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S 0 7433 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_GET(_var) \ 7434 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M) >> \ 7435 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S) 7436 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_SET(_var, _val) \ 7437 do { \ 7438 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS, _val); \ 7439 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)); \ 7440 } while (0) 7441 7442 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M 0x00000008 7443 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S 3 7444 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_GET(_var) \ 7445 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M) >> \ 7446 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S) 7447 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_SET(_var, _val) \ 7448 do { \ 7449 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT, _val); \ 7450 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S)); \ 7451 } while (0) 7452 7453 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M 0x00000010 7454 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S 4 7455 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_GET(_var) \ 7456 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M) >> \ 7457 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S) 7458 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_SET(_var, _val) \ 7459 do { \ 7460 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL, _val); \ 7461 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)); \ 7462 } while (0) 7463 7464 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M 0x00000020 7465 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S 5 7466 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_GET(_var) \ 7467 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M) >> \ 7468 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S) 7469 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_SET(_var, _val) \ 7470 do { \ 7471 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA, _val); \ 7472 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S)); \ 7473 } while (0) 7474 7475 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M 0x00000040 7476 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S 6 7477 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_GET(_var) \ 7478 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M) >> \ 7479 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S) 7480 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_SET(_var, _val) \ 7481 do { \ 7482 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT, _val); \ 7483 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S)); \ 7484 } while (0) 7485 7486 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M 0x00000080 7487 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S 7 7488 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_GET(_var) \ 7489 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M) >> \ 7490 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S) 7491 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_SET(_var, _val) \ 7492 do { \ 7493 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL, _val); \ 7494 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)); \ 7495 } while (0) 7496 7497 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M 0x00000100 7498 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S 8 7499 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_GET(_var) \ 7500 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M) >> \ 7501 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S) 7502 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_SET(_var, _val) \ 7503 do { \ 7504 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA, _val); \ 7505 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S)); \ 7506 } while (0) 7507 7508 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M 0x00000200 7509 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S 9 7510 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_GET(_var) \ 7511 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M) >> \ 7512 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S) 7513 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_SET(_var, _val) \ 7514 do { \ 7515 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT, _val); \ 7516 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S)); \ 7517 } while (0) 7518 7519 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M 0x00000400 7520 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S 10 7521 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_GET(_var) \ 7522 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M) >> \ 7523 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S) 7524 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_SET(_var, _val) \ 7525 do { \ 7526 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL, _val); \ 7527 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)); \ 7528 } while (0) 7529 7530 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M 0x00000800 7531 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S 11 7532 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_GET(_var) \ 7533 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M) >> \ 7534 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S) 7535 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_SET(_var, _val) \ 7536 do { \ 7537 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA, _val); \ 7538 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S)); \ 7539 } while (0) 7540 7541 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M 0x00001000 7542 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S 12 7543 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_GET(_var) \ 7544 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M) >> \ 7545 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S) 7546 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_SET(_var, _val) \ 7547 do { \ 7548 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT, _val); \ 7549 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S)); \ 7550 } while (0) 7551 7552 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M 0x00002000 7553 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S 13 7554 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_GET(_var) \ 7555 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M) >> \ 7556 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S) 7557 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_SET(_var, _val) \ 7558 do { \ 7559 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL, _val); \ 7560 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)); \ 7561 } while (0) 7562 7563 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M 0x00004000 7564 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S 14 7565 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_GET(_var) \ 7566 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M) >> \ 7567 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S) 7568 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_SET(_var, _val) \ 7569 do { \ 7570 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA, _val); \ 7571 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \ 7572 } while (0) 7573 7574 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000 7575 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15 7576 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 7577 (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 7578 HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S) 7579 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 7580 do { \ 7581 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 7582 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 7583 } while (0) 7584 7585 7586 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff 7587 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0 7588 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \ 7589 (((_var) & HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M) >> \ 7590 HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S) 7591 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_SET(_var, _val) \ 7592 do { \ 7593 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TLV_FILTER_MASK, _val); \ 7594 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)); \ 7595 } while (0) 7596 7597 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M 0x000000ff 7598 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S 0 7599 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_GET(_var) \ 7600 (((_var) & HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M) >> \ 7601 HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S) 7602 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_SET(_var, _val) \ 7603 do { \ 7604 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK, _val); \ 7605 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)); \ 7606 } while (0) 7607 7608 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M 0x0000ff00 7609 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S 8 7610 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_GET(_var) \ 7611 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M) >> \ 7612 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S) 7613 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_SET(_var, _val) \ 7614 do { \ 7615 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK, _val); \ 7616 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)); \ 7617 } while (0) 7618 7619 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M 0x00ff0000 7620 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S 16 7621 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_GET(_var) \ 7622 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M) >> \ 7623 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S) 7624 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_SET(_var, _val) \ 7625 do { \ 7626 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK, _val); \ 7627 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)); \ 7628 } while (0) 7629 7630 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M 0xff000000 7631 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S 24 7632 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_GET(_var) \ 7633 (((_var) & HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M) >> \ 7634 HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S) 7635 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_SET(_var, _val) \ 7636 do { \ 7637 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK, _val); \ 7638 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)); \ 7639 } while (0) 7640 7641 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M 0xffffffff 7642 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S 0 7643 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_GET(_var) \ 7644 (((_var) & HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M) >> \ 7645 HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S) 7646 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_SET(_var, _val) \ 7647 do { \ 7648 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK, _val); \ 7649 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)); \ 7650 } while (0) 7651 7652 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M 0x000000ff 7653 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S 0 7654 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_GET(_var) \ 7655 (((_var) & HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M) >> \ 7656 HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S) 7657 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_SET(_var, _val) \ 7658 do { \ 7659 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK, _val); \ 7660 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)); \ 7661 } while (0) 7662 7663 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M 0x0000ff00 7664 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S 8 7665 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_GET(_var) \ 7666 (((_var) & HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M) >> \ 7667 HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S) 7668 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_SET(_var, _val) \ 7669 do { \ 7670 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK, _val); \ 7671 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)); \ 7672 } while (0) 7673 7674 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00070000 7675 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S 16 7676 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \ 7677 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \ 7678 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S) 7679 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \ 7680 do { \ 7681 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK, _val); \ 7682 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)); \ 7683 } while (0) 7684 7685 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M 0x00080000 7686 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S 19 7687 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_GET(_var) \ 7688 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M) >> \ 7689 HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S) 7690 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 7691 do { \ 7692 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT, _val); \ 7693 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S)); \ 7694 } while (0) 7695 7696 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M 0x00100000 7697 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S 20 7698 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_GET(_var) \ 7699 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M) >> \ 7700 HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S) 7701 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 7702 do { \ 7703 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL, _val); \ 7704 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S)); \ 7705 } while (0) 7706 7707 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M 0x00200000 7708 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S 21 7709 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_GET(_var) \ 7710 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M) >> \ 7711 HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S) 7712 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 7713 do { \ 7714 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_DATA, _val); \ 7715 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \ 7716 } while (0) 7717 7718 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M 0x00000fff 7719 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S 0 7720 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \ 7721 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \ 7722 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S) 7723 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \ 7724 do { \ 7725 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \ 7726 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \ 7727 } while (0) 7728 7729 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M 0x00fff000 7730 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S 12 7731 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \ 7732 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \ 7733 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S) 7734 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \ 7735 do { \ 7736 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \ 7737 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \ 7738 } while (0) 7739 7740 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M 0x0000ffff 7741 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S 0 7742 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \ 7743 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \ 7744 HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S) 7745 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \ 7746 do { \ 7747 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \ 7748 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \ 7749 } while (0) 7750 7751 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M 0xffff0000 7752 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S 16 7753 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \ 7754 (((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \ 7755 HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S) 7756 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \ 7757 do { \ 7758 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \ 7759 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \ 7760 } while (0) 7761 7762 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M 0x000007ff 7763 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S 0 7764 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \ 7765 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \ 7766 HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S) 7767 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \ 7768 do { \ 7769 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \ 7770 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \ 7771 } while (0) 7772 7773 /* 7774 * pkt_type_enable_flags 7775 */ 7776 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_M 0x00000001 7777 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_S 0 7778 7779 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_M 0x00000002 7780 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_S 1 7781 7782 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_M 0x00000004 7783 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_S 2 7784 7785 /* 7786 * PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING 7787 */ 7788 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_M 0x00010000 7789 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_S 16 7790 7791 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_M 0x00020000 7792 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_S 17 7793 7794 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_M 0x00040000 7795 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_S 18 7796 7797 #define HTT_TX_MONITOR_CFG_PKT_TYPE_SET(word, httsym, value) \ 7798 do { \ 7799 HTT_CHECK_SET_VAL(httsym, value); \ 7800 (word) |= (value) << httsym##_S; \ 7801 } while (0) 7802 #define HTT_TX_MONITOR_CFG_PKT_TYPE_GET(word, httsym) \ 7803 (((word) & httsym##_M) >> httsym##_S) 7804 7805 /* mode -> ENABLE_FLAGS, ENABLE_MSDU_OR_MPDU_LOGGING 7806 * type -> MGMT, CTRL, DATA*/ 7807 7808 #define htt_tx_ring_pkt_type_set( \ 7809 word, mode, type, val) \ 7810 HTT_TX_MONITOR_CFG_PKT_TYPE_SET( \ 7811 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type, val) 7812 7813 #define htt_tx_ring_pkt_type_get( \ 7814 word, mode, type) \ 7815 HTT_TX_MONITOR_CFG_PKT_TYPE_GET( \ 7816 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type) 7817 7818 /* Definition to filter in TLVs */ 7819 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_M 0x00000001 7820 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_S 0 7821 7822 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_M 0x00000002 7823 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_S 1 7824 7825 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_M 0x00000004 7826 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_S 2 7827 7828 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_M 0x00000008 7829 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_S 3 7830 7831 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_M 0x00000010 7832 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_S 4 7833 7834 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_M 0x00000020 7835 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_S 5 7836 7837 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_M 0x00000040 7838 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_S 6 7839 7840 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_M 0x00000080 7841 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_S 7 7842 7843 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_M 0x00000100 7844 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_S 8 7845 7846 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_M 0x00000200 7847 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_S 9 7848 7849 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_M 0x00000400 7850 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_S 10 7851 7852 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_M 0x00000800 7853 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_S 11 7854 7855 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_M 0x00001000 7856 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_S 12 7857 7858 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_M 0x00002000 7859 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_S 13 7860 7861 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_M 0x00004000 7862 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_S 14 7863 7864 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_M 0x00008000 7865 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_S 15 7866 7867 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_M 0x00010000 7868 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_S 16 7869 7870 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_M 0x00020000 7871 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_S 17 7872 7873 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_M 0x00040000 7874 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_S 18 7875 7876 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_M 0x00080000 7877 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_S 19 7878 7879 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_M 0x00100000 7880 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_S 20 7881 7882 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_M 0x00200000 7883 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_S 21 7884 7885 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_M 0x00400000 7886 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_S 22 7887 7888 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_M 0x00800000 7889 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_S 23 7890 7891 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_M 0x01000000 7892 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_S 24 7893 7894 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_M 0x02000000 7895 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_S 25 7896 7897 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_M 0x04000000 7898 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_S 26 7899 7900 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_M 0x08000000 7901 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_S 27 7902 7903 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_M 0x10000000 7904 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_S 28 7905 7906 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_M 0x20000000 7907 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_S 29 7908 7909 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_M 0x40000000 7910 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_S 30 7911 7912 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_M 0x80000000 7913 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_S 31 7914 7915 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET(word, httsym, enable) \ 7916 do { \ 7917 HTT_CHECK_SET_VAL(httsym, enable); \ 7918 (word) |= (enable) << httsym##_S; \ 7919 } while (0) 7920 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET(word, httsym) \ 7921 (((word) & httsym##_M) >> httsym##_S) 7922 7923 #define htt_tx_monitor_tlv_filter_in0_enable_set(word, tlv, enable) \ 7924 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET( \ 7925 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv, enable) 7926 7927 #define htt_tx_monitor_tlv_filter_in0_enable_get(word, tlv) \ 7928 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET( \ 7929 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv) 7930 7931 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_M 0x00000001 7932 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_S 0 7933 7934 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_M 0x00000002 7935 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_S 1 7936 7937 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_M 0x00000004 7938 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_S 2 7939 7940 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_M 0x00000008 7941 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_S 3 7942 7943 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_M 0x00000010 7944 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_S 4 7945 7946 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_M 0x00000020 7947 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_S 5 7948 7949 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_M 0x00000040 7950 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_S 6 7951 7952 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_M 0x00000080 7953 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_S 7 7954 7955 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_M 0x00000100 7956 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_S 8 7957 7958 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_M 0x00000200 7959 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_S 9 7960 7961 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_M 0x00000400 7962 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_S 10 7963 7964 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_M 0x00000800 7965 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_S 11 7966 7967 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_M 0x00001000 7968 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_S 12 7969 7970 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_M 0x00002000 7971 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_S 13 7972 7973 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_M 0x00004000 7974 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_S 14 7975 7976 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_M 0x00008000 7977 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_S 15 7978 7979 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_M 0x00010000 7980 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_S 16 7981 7982 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_M 0x00020000 7983 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_S 17 7984 7985 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_M 0x00040000 7986 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_S 18 7987 7988 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_M 0x00080000 7989 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_S 19 7990 7991 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_M 0x00100000 7992 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_S 20 7993 7994 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_M 0x00200000 7995 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_S 21 7996 7997 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_M 0x00400000 7998 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_S 22 7999 8000 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_M 0x00800000 8001 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_S 23 8002 8003 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_M 0x01000000 8004 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_S 24 8005 8006 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_M 0x02000000 8007 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_S 25 8008 8009 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_M 0x04000000 8010 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_S 26 8011 8012 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_M 0x08000000 8013 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_S 27 8014 8015 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_M 0x10000000 8016 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_S 28 8017 8018 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_M 0x20000000 8019 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_S 29 8020 8021 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_M 0x40000000 8022 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_S 30 8023 8024 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_M 0x80000000 8025 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_S 31 8026 8027 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET(word, httsym, enable) \ 8028 do { \ 8029 HTT_CHECK_SET_VAL(httsym, enable); \ 8030 (word) |= (enable) << httsym##_S; \ 8031 } while (0) 8032 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET(word, httsym) \ 8033 (((word) & httsym##_M) >> httsym##_S) 8034 8035 #define htt_tx_monitor_tlv_filter_in1_enable_set(word, tlv, enable) \ 8036 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET( \ 8037 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv, enable) 8038 8039 #define htt_tx_monitor_tlv_filter_in1_enable_get(word, tlv) \ 8040 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET( \ 8041 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv) 8042 8043 8044 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_M 0x00000001 8045 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_S 0 8046 8047 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_M 0x00000002 8048 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_S 1 8049 8050 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_M 0x00000004 8051 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_S 2 8052 8053 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_M 0x00000008 8054 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_S 3 8055 8056 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_M 0x00000010 8057 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_S 4 8058 8059 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_M 0x00000020 8060 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_S 5 8061 8062 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_M 0x00000040 8063 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_S 6 8064 8065 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_M 0x00000080 8066 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_S 7 8067 8068 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_M 0x00000100 8069 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_S 8 8070 8071 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_M 0x00000200 8072 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_S 9 8073 8074 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_M 0x00000400 8075 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_S 10 8076 8077 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_M 0x00000800 8078 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_S 11 8079 8080 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_M 0x00001000 8081 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_S 12 8082 8083 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_M 0x00002000 8084 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_S 13 8085 8086 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_M 0x00004000 8087 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_S 14 8088 8089 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_M 0x00008000 8090 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_S 15 8091 8092 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_M 0x00010000 8093 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_S 16 8094 8095 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_M 0x00020000 8096 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_S 17 8097 8098 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_M 0x00040000 8099 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_S 18 8100 8101 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_M 0x00080000 8102 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_S 19 8103 8104 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_M 0x00100000 8105 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_S 20 8106 8107 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_M 0x00200000 8108 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_S 21 8109 8110 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_M 0x00400000 8111 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_S 22 8112 8113 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_M 0x00800000 8114 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_S 23 8115 8116 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_M 0x01000000 8117 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_S 24 8118 8119 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_M 0x02000000 8120 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_S 25 8121 8122 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_M 0x04000000 8123 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_S 26 8124 8125 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_M 0x08000000 8126 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_S 27 8127 8128 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_M 0x10000000 8129 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_S 28 8130 8131 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_M 0x20000000 8132 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_S 29 8133 8134 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_M 0x40000000 8135 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_S 30 8136 8137 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_M 0x80000000 8138 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_S 31 8139 8140 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET(word, httsym, enable) \ 8141 do { \ 8142 HTT_CHECK_SET_VAL(httsym, enable); \ 8143 (word) |= (enable) << httsym##_S; \ 8144 } while (0) 8145 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET(word, httsym) \ 8146 (((word) & httsym##_M) >> httsym##_S) 8147 8148 #define htt_tx_monitor_tlv_filter_in2_enable_set(word, tlv, enable) \ 8149 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET( \ 8150 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv, enable) 8151 8152 #define htt_tx_monitor_tlv_filter_in2_enable_get(word, tlv) \ 8153 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET( \ 8154 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv) 8155 8156 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_M 0x00000001 8157 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_S 0 8158 8159 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_M 0x00000002 8160 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_S 1 8161 8162 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_M 0x00000004 8163 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_S 2 8164 8165 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_M 0x00000008 8166 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_S 3 8167 8168 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_M 0x00000010 8169 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_S 4 8170 8171 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_M 0x00000020 8172 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_S 5 8173 8174 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_M 0x00000040 8175 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_S 6 8176 8177 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_M 0x00000080 8178 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_S 7 8179 8180 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_M 0x00000100 8181 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_S 8 8182 8183 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_M 0x00000200 8184 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_S 9 8185 8186 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_M 0x00000400 8187 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_S 10 8188 8189 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_M 0x00000800 8190 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_S 11 8191 8192 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_M 0x00001000 8193 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_S 12 8194 8195 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_M 0x00002000 8196 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_S 13 8197 8198 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_M 0x00004000 8199 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_S 14 8200 8201 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_M 0x00008000 8202 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_S 15 8203 8204 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_M 0x00010000 8205 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_S 16 8206 8207 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_M 0x00020000 8208 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_S 17 8209 8210 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_M 0x00040000 8211 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_S 18 8212 8213 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_M 0x00080000 8214 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_S 19 8215 8216 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_M 0x00100000 8217 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_S 20 8218 8219 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_M 0x00200000 8220 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_S 21 8221 8222 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET(word, httsym, enable) \ 8223 do { \ 8224 HTT_CHECK_SET_VAL(httsym, enable); \ 8225 (word) |= (enable) << httsym##_S; \ 8226 } while (0) 8227 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET(word, httsym) \ 8228 (((word) & httsym##_M) >> httsym##_S) 8229 8230 #define htt_tx_monitor_tlv_filter_in3_enable_set(word, tlv, enable) \ 8231 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET( \ 8232 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv, enable) 8233 8234 #define htt_tx_monitor_tlv_filter_in3_enable_get(word, tlv) \ 8235 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET( \ 8236 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv) 8237 8238 /** 8239 * @brief host --> target Receive Flow Steering configuration message definition 8240 * 8241 * MSG_TYPE => HTT_H2T_MSG_TYPE_RFS_CONFIG 8242 * 8243 * host --> target Receive Flow Steering configuration message definition. 8244 * Host must send this message before sending HTT_H2T_MSG_TYPE_RX_RING_CFG. 8245 * The reason for this is we want RFS to be configured and ready before MAC 8246 * remote ring is enabled via HTT_H2T_MSG_TYPE_RX_RING_CFG. 8247 * 8248 * |31 24|23 16|15 9|8|7 0| 8249 * |----------------+----------------+----------------+----------------| 8250 * | reserved |E| msg type | 8251 * |-------------------------------------------------------------------| 8252 * Where E = RFS enable flag 8253 * 8254 * The RFS_CONFIG message consists of a single 4-byte word. 8255 * 8256 * Header fields: 8257 * - MSG_TYPE 8258 * Bits 7:0 8259 * Purpose: identifies this as a RFS config msg 8260 * Value: 0xf (HTT_H2T_MSG_TYPE_RFS_CONFIG) 8261 * - RFS_CONFIG 8262 * Bit 8 8263 * Purpose: Tells target whether to enable (1) or disable (0) 8264 * flow steering feature when sending rx indication messages to host 8265 */ 8266 #define HTT_H2T_RFS_CONFIG_M 0x100 8267 #define HTT_H2T_RFS_CONFIG_S 8 8268 #define HTT_RX_RFS_CONFIG_GET(_var) \ 8269 (((_var) & HTT_H2T_RFS_CONFIG_M) >> \ 8270 HTT_H2T_RFS_CONFIG_S) 8271 #define HTT_RX_RFS_CONFIG_SET(_var, _val) \ 8272 do { \ 8273 HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \ 8274 ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \ 8275 } while (0) 8276 8277 #define HTT_RFS_CFG_REQ_BYTES 4 8278 8279 8280 /** 8281 * @brief host -> target FW extended statistics request 8282 * 8283 * MSG_TYPE => HTT_H2T_MSG_TYPE_EXT_STATS_REQ 8284 * 8285 * @details 8286 * The following field definitions describe the format of the HTT host 8287 * to target FW extended stats retrieve message. 8288 * The message specifies the type of stats the host wants to retrieve. 8289 * 8290 * |31 24|23 16|15 8|7 0| 8291 * |-----------------------------------------------------------| 8292 * | reserved | stats type | pdev_mask | msg type | 8293 * |-----------------------------------------------------------| 8294 * | config param [0] | 8295 * |-----------------------------------------------------------| 8296 * | config param [1] | 8297 * |-----------------------------------------------------------| 8298 * | config param [2] | 8299 * |-----------------------------------------------------------| 8300 * | config param [3] | 8301 * |-----------------------------------------------------------| 8302 * | reserved | 8303 * |-----------------------------------------------------------| 8304 * | cookie LSBs | 8305 * |-----------------------------------------------------------| 8306 * | cookie MSBs | 8307 * |-----------------------------------------------------------| 8308 * Header fields: 8309 * - MSG_TYPE 8310 * Bits 7:0 8311 * Purpose: identifies this is a extended stats upload request message 8312 * Value: 0x10 (HTT_H2T_MSG_TYPE_EXT_STATS_REQ) 8313 * - PDEV_MASK 8314 * Bits 8:15 8315 * Purpose: identifies the mask of PDEVs to retrieve stats from 8316 * Value: This is a overloaded field, refer to usage and interpretation of 8317 * PDEV in interface document. 8318 * Bit 8 : Reserved for SOC stats 8319 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8320 * Indicates MACID_MASK in DBS 8321 * - STATS_TYPE 8322 * Bits 23:16 8323 * Purpose: identifies which FW statistics to upload 8324 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8325 * - Reserved 8326 * Bits 31:24 8327 * - CONFIG_PARAM [0] 8328 * Bits 31:0 8329 * Purpose: give an opaque configuration value to the specified stats type 8330 * Value: stats-type specific configuration value 8331 * Refer to htt_stats.h for interpretation for each stats sub_type 8332 * - CONFIG_PARAM [1] 8333 * Bits 31:0 8334 * Purpose: give an opaque configuration value to the specified stats type 8335 * Value: stats-type specific configuration value 8336 * Refer to htt_stats.h for interpretation for each stats sub_type 8337 * - CONFIG_PARAM [2] 8338 * Bits 31:0 8339 * Purpose: give an opaque configuration value to the specified stats type 8340 * Value: stats-type specific configuration value 8341 * Refer to htt_stats.h for interpretation for each stats sub_type 8342 * - CONFIG_PARAM [3] 8343 * Bits 31:0 8344 * Purpose: give an opaque configuration value to the specified stats type 8345 * Value: stats-type specific configuration value 8346 * Refer to htt_stats.h for interpretation for each stats sub_type 8347 * - Reserved [31:0] for future use. 8348 * - COOKIE_LSBS 8349 * Bits 31:0 8350 * Purpose: Provide a mechanism to match a target->host stats confirmation 8351 * message with its preceding host->target stats request message. 8352 * Value: LSBs of the opaque cookie specified by the host-side requestor 8353 * - COOKIE_MSBS 8354 * Bits 31:0 8355 * Purpose: Provide a mechanism to match a target->host stats confirmation 8356 * message with its preceding host->target stats request message. 8357 * Value: MSBs of the opaque cookie specified by the host-side requestor 8358 */ 8359 8360 #define HTT_H2T_EXT_STATS_REQ_MSG_SZ 32 /* bytes */ 8361 8362 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M 0x0000ff00 8363 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S 8 8364 8365 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M 0x00ff0000 8366 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S 16 8367 8368 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M 0xffffffff 8369 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S 0 8370 8371 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_GET(_var) \ 8372 (((_var) & HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M) >> \ 8373 HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S) 8374 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_SET(_var, _val) \ 8375 do { \ 8376 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_PDEV_MASK, _val); \ 8377 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S)); \ 8378 } while (0) 8379 8380 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_GET(_var) \ 8381 (((_var) & HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M) >> \ 8382 HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S) 8383 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8384 do { \ 8385 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_STATS_TYPE, _val); \ 8386 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S)); \ 8387 } while (0) 8388 8389 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_GET(_var) \ 8390 (((_var) & HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M) >> \ 8391 HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S) 8392 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_SET(_var, _val) \ 8393 do { \ 8394 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM, _val); \ 8395 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S)); \ 8396 } while (0) 8397 8398 /** 8399 * @brief host -> target FW streaming statistics request 8400 * 8401 * MSG_TYPE => HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ 8402 * 8403 * @details 8404 * The following field definitions describe the format of the HTT host 8405 * to target message that requests the target to start or stop producing 8406 * ongoing stats of the specified type. 8407 * 8408 * |31|30 |23 16|15 8|7 0| 8409 * |-----------------------------------------------------------| 8410 * |EN| reserved | stats type | reserved | msg type | 8411 * |-----------------------------------------------------------| 8412 * | config param [0] | 8413 * |-----------------------------------------------------------| 8414 * | config param [1] | 8415 * |-----------------------------------------------------------| 8416 * | config param [2] | 8417 * |-----------------------------------------------------------| 8418 * | config param [3] | 8419 * |-----------------------------------------------------------| 8420 * Where: 8421 * - EN is an enable/disable flag 8422 * Header fields: 8423 * - MSG_TYPE 8424 * Bits 7:0 8425 * Purpose: identifies this is a streaming stats upload request message 8426 * Value: 0x20 (HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ) 8427 * - STATS_TYPE 8428 * Bits 23:16 8429 * Purpose: identifies which FW statistics to upload 8430 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8431 * Only the htt_dbg_ext_stats_type values identified as streaming 8432 * stats are valid to specify in this STEAMING_STATS_REQ message. 8433 * - ENABLE 8434 * Bit 31 8435 * Purpose: enable/disable the target's ongoing stats of the specified type 8436 * Value: 8437 * 0 - disable ongoing production of the specified stats type 8438 * 1 - enable ongoing production of the specified stats type 8439 * - CONFIG_PARAM [0] 8440 * Bits 31:0 8441 * Purpose: give an opaque configuration value to the specified stats type 8442 * Value: stats-type specific configuration value 8443 * Refer to htt_stats.h for interpretation for each stats sub_type 8444 * - CONFIG_PARAM [1] 8445 * Bits 31:0 8446 * Purpose: give an opaque configuration value to the specified stats type 8447 * Value: stats-type specific configuration value 8448 * Refer to htt_stats.h for interpretation for each stats sub_type 8449 * - CONFIG_PARAM [2] 8450 * Bits 31:0 8451 * Purpose: give an opaque configuration value to the specified stats type 8452 * Value: stats-type specific configuration value 8453 * Refer to htt_stats.h for interpretation for each stats sub_type 8454 * - CONFIG_PARAM [3] 8455 * Bits 31:0 8456 * Purpose: give an opaque configuration value to the specified stats type 8457 * Value: stats-type specific configuration value 8458 * Refer to htt_stats.h for interpretation for each stats sub_type 8459 */ 8460 8461 #define HTT_H2T_STREAMING_STATS_REQ_MSG_SZ 20 /* bytes */ 8462 8463 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M 0x00ff0000 8464 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S 16 8465 8466 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_M 0x80000000 8467 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_S 31 8468 8469 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_GET(_var) \ 8470 (((_var) & HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M) >> \ 8471 HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S) 8472 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8473 do { \ 8474 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE, _val); \ 8475 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S)); \ 8476 } while (0) 8477 8478 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_GET(_var) \ 8479 (((_var) & HTT_H2T_STREAMING_STATS_REQ_ENABLE_M) >> \ 8480 HTT_H2T_STREAMING_STATS_REQ_ENABLE_S) 8481 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_SET(_var, _val) \ 8482 do { \ 8483 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_ENABLE, _val); \ 8484 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_ENABLE_S)); \ 8485 } while (0) 8486 8487 /** 8488 * @brief host -> target FW PPDU_STATS request message 8489 * 8490 * MSG_TYPE => HTT_H2T_MSG_TYPE_PPDU_STATS_CFG 8491 * 8492 * @details 8493 * The following field definitions describe the format of the HTT host 8494 * to target FW for PPDU_STATS_CFG msg. 8495 * The message allows the host to configure the PPDU_STATS_IND messages 8496 * produced by the target. 8497 * 8498 * |31 24|23 16|15 8|7 0| 8499 * |-----------------------------------------------------------| 8500 * | REQ bit mask | pdev_mask | msg type | 8501 * |-----------------------------------------------------------| 8502 * Header fields: 8503 * - MSG_TYPE 8504 * Bits 7:0 8505 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 8506 * Value: 0x11 (HTT_H2T_MSG_TYPE_PPDU_STATS_CFG) 8507 * - PDEV_MASK 8508 * Bits 8:15 8509 * Purpose: identifies which pdevs this PPDU stats configuration applies to 8510 * Value: This is a overloaded field, refer to usage and interpretation of 8511 * PDEV in interface document. 8512 * Bit 8 : Reserved for SOC stats 8513 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8514 * Indicates MACID_MASK in DBS 8515 * - REQ_TLV_BIT_MASK 8516 * Bits 16:31 8517 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 8518 * needs to be included in the target's PPDU_STATS_IND messages. 8519 * Value: refer htt_ppdu_stats_tlv_tag_t 8520 * 8521 */ 8522 #define HTT_H2T_PPDU_STATS_CFG_MSG_SZ 4 /* bytes */ 8523 8524 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M 0x0000ff00 8525 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S 8 8526 8527 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M 0xffff0000 8528 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S 16 8529 8530 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_GET(_var) \ 8531 (((_var) & HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M) >> \ 8532 HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S) 8533 8534 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_SET(_var, _val) \ 8535 do { \ 8536 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_PDEV_MASK, _val); \ 8537 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S)); \ 8538 } while (0) 8539 8540 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_GET(_var) \ 8541 (((_var) & HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M) >> \ 8542 HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S) 8543 8544 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_SET(_var, _val) \ 8545 do { \ 8546 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK, _val); \ 8547 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \ 8548 } while (0) 8549 8550 /** 8551 * @brief Host-->target HTT RX FSE setup message 8552 * 8553 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG 8554 * 8555 * @details 8556 * Through this message, the host will provide details of the flow tables 8557 * in host DDR along with hash keys. 8558 * This message can be sent per SOC or per PDEV, which is differentiated 8559 * by pdev id values. 8560 * The host will allocate flow search table and sends table size, 8561 * physical DMA address of flow table, and hash keys to firmware to 8562 * program into the RXOLE FSE HW block. 8563 * 8564 * The following field definitions describe the format of the RX FSE setup 8565 * message sent from the host to target 8566 * 8567 * Header fields: 8568 * dword0 - b'7:0 - msg_type: This will be set to 8569 * 0x12 (HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG) 8570 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8571 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8572 * pdev's LMAC ring. 8573 * b'31:16 - reserved : Reserved for future use 8574 * dword1 - b'19:0 - number of records: This field indicates the number of 8575 * entries in the flow table. For example: 8k number of 8576 * records is equivalent to 8577 * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT) 8578 * b'27:20 - max search: This field specifies the skid length to FSE 8579 * parser HW module whenever match is not found at the 8580 * exact index pointed by hash. 8581 * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used. 8582 * Refer htt_ip_da_sa_prefix below for more details. 8583 * b'31:30 - reserved: Reserved for future use 8584 * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow 8585 * table allocated by host in DDR 8586 * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow 8587 * table allocated by host in DDR 8588 * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table 8589 * entry hashing 8590 * 8591 * 8592 * |31 30|29 28|27|26|25 20|19 16|15 8|7 0| 8593 * |---------------------------------------------------------------| 8594 * | reserved | pdev_id | MSG_TYPE | 8595 * |---------------------------------------------------------------| 8596 * |resvd|IPDSA| max_search | Number of records | 8597 * |---------------------------------------------------------------| 8598 * | base address lo | 8599 * |---------------------------------------------------------------| 8600 * | base address high | 8601 * |---------------------------------------------------------------| 8602 * | toeplitz key 31_0 | 8603 * |---------------------------------------------------------------| 8604 * | toeplitz key 63_32 | 8605 * |---------------------------------------------------------------| 8606 * | toeplitz key 95_64 | 8607 * |---------------------------------------------------------------| 8608 * | toeplitz key 127_96 | 8609 * |---------------------------------------------------------------| 8610 * | toeplitz key 159_128 | 8611 * |---------------------------------------------------------------| 8612 * | toeplitz key 191_160 | 8613 * |---------------------------------------------------------------| 8614 * | toeplitz key 223_192 | 8615 * |---------------------------------------------------------------| 8616 * | toeplitz key 255_224 | 8617 * |---------------------------------------------------------------| 8618 * | toeplitz key 287_256 | 8619 * |---------------------------------------------------------------| 8620 * | reserved | toeplitz key 314_288(26:0 bits) | 8621 * |---------------------------------------------------------------| 8622 * where: 8623 * IPDSA = ip_da_sa 8624 */ 8625 8626 /** 8627 * @brief: htt_ip_da_sa_prefix 8628 * 0x0 -> Prefix is 0x20010db8_00000000_00000000 8629 * IPv6 addresses beginning with 0x20010db8 are reserved for 8630 * documentation per RFC3849 8631 * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6 8632 * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6 8633 * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix 8634 */ 8635 8636 enum htt_ip_da_sa_prefix { 8637 HTT_RX_IPV6_20010db8, 8638 HTT_RX_IPV4_MAPPED_IPV6, 8639 HTT_RX_IPV4_COMPATIBLE_IPV6, 8640 HTT_RX_IPV6_64FF9B, 8641 }; 8642 8643 8644 /** 8645 * @brief Host-->target HTT RX FISA configure and enable 8646 * 8647 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FISA_CFG 8648 * 8649 * @details 8650 * The host will send this command down to configure and enable the FISA 8651 * operational params. 8652 * Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH 8653 * register. 8654 * Should configure both the MACs. 8655 * 8656 * dword0 - b'7:0 - msg_type: 8657 * This will be set to 0x15 (HTT_H2T_MSG_TYPE_RX_FISA_CFG) 8658 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8659 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8660 * pdev's LMAC ring. 8661 * b'31:16 - reserved : Reserved for future use 8662 * 8663 * dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable 8664 * b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC 8665 * packets. 1 flow search will be skipped 8666 * b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non 8667 * tcp,udp packets 8668 * b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length 8669 * calculation 8670 * b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length 8671 * calculation 8672 * b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length 8673 * calculation 8674 * b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation 8675 * b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP 8676 * length 8677 * 0 L4 checksum will be provided in the RX_MSDU_END tlv 8678 * 1 IPV4 hdr checksum after adjusting for cumulative IP 8679 * length 8680 * b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence 8681 * num jump 8682 * b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence 8683 * num jump 8684 * b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos 8685 * data type switch has happened for MPDU Sequence num jump 8686 * b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type 8687 * for MPDU Sequence num jump 8688 * b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands 8689 * for decrypt errors 8690 * b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop 8691 * while aggregating a msdu 8692 * b'17:14 - LIMIT, Aggregtion limit for number of MSDUs. 8693 * The aggregation is done until (number of MSDUs aggregated 8694 * < LIMIT + 1) 8695 * b'31:18 - Reserved 8696 * 8697 * fisa_control_value - 32bit value FW can write to register 8698 * 8699 * dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation 8700 * Threshold value for FISA timeout (units are microseconds). 8701 * When the global timestamp exceeds this threshold, FISA 8702 * aggregation will be restarted. 8703 * A value of 0 means timeout is disabled. 8704 * Compare the threshold register with timestamp field in 8705 * flow entry to generate timeout for the flow. 8706 * 8707 * |31 18 |17 16|15 8|7 0| 8708 * |-------------------------------------------------------------| 8709 * | reserved | pdev_mask | msg type | 8710 * |-------------------------------------------------------------| 8711 * | reserved | FISA_CTRL | 8712 * |-------------------------------------------------------------| 8713 * | FISA_TIMEOUT_THRESH | 8714 * |-------------------------------------------------------------| 8715 */ 8716 PREPACK struct htt_h2t_msg_type_fisa_config_t { 8717 A_UINT32 msg_type:8, 8718 pdev_id:8, 8719 reserved0:16; 8720 8721 /** 8722 * @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register 8723 * [17:0] 8724 */ 8725 union { 8726 /* 8727 * fisa_control_bits structure is deprecated. 8728 * Please use fisa_control_bits_v2 going forward. 8729 */ 8730 struct { 8731 A_UINT32 fisa_enable: 1, 8732 ipsec_skip_search: 1, 8733 nontcp_skip_search: 1, 8734 add_ipv4_fixed_hdr_len: 1, 8735 add_ipv6_fixed_hdr_len: 1, 8736 add_tcp_fixed_hdr_len: 1, 8737 add_udp_hdr_len: 1, 8738 chksum_cum_ip_len_en: 1, 8739 disable_tid_check: 1, 8740 disable_ta_check: 1, 8741 disable_qos_check: 1, 8742 disable_raw_check: 1, 8743 disable_decrypt_err_check: 1, 8744 disable_msdu_drop_check: 1, 8745 fisa_aggr_limit: 4, 8746 reserved: 14; 8747 } fisa_control_bits; 8748 struct { 8749 A_UINT32 fisa_enable: 1, 8750 fisa_aggr_limit: 6, 8751 reserved: 25; 8752 } fisa_control_bits_v2; 8753 8754 A_UINT32 fisa_control_value; 8755 } u_fisa_control; 8756 8757 /** 8758 * @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA 8759 * timeout threshold for aggregation. Unit in usec. 8760 * [31:0] 8761 */ 8762 A_UINT32 fisa_timeout_threshold; 8763 } POSTPACK; 8764 8765 8766 /* DWord 0: pdev-ID */ 8767 #define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00 8768 #define HTT_RX_FISA_CONFIG_PDEV_ID_S 8 8769 #define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \ 8770 (((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \ 8771 HTT_RX_FISA_CONFIG_PDEV_ID_S) 8772 #define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \ 8773 do { \ 8774 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \ 8775 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \ 8776 } while (0) 8777 8778 /* Dword 1: fisa_control_value fisa config */ 8779 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001 8780 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0 8781 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \ 8782 (((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \ 8783 HTT_RX_FISA_CONFIG_FISA_ENABLE_S) 8784 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \ 8785 do { \ 8786 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \ 8787 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \ 8788 } while (0) 8789 8790 /* Dword 1: fisa_control_value ipsec_skip_search */ 8791 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002 8792 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1 8793 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \ 8794 (((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \ 8795 HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S) 8796 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \ 8797 do { \ 8798 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \ 8799 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \ 8800 } while (0) 8801 8802 /* Dword 1: fisa_control_value non_tcp_skip_search */ 8803 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004 8804 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2 8805 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \ 8806 (((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \ 8807 HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S) 8808 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \ 8809 do { \ 8810 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \ 8811 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \ 8812 } while (0) 8813 8814 /* Dword 1: fisa_control_value add_ipv4_fixed_hdr */ 8815 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008 8816 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3 8817 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \ 8818 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \ 8819 HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S) 8820 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \ 8821 do { \ 8822 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \ 8823 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \ 8824 } while (0) 8825 8826 /* Dword 1: fisa_control_value add_ipv6_fixed_hdr */ 8827 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010 8828 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4 8829 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \ 8830 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \ 8831 HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S) 8832 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \ 8833 do { \ 8834 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \ 8835 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \ 8836 } while (0) 8837 8838 /* Dword 1: fisa_control_value tcp_fixed_hdr_len */ 8839 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020 8840 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5 8841 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \ 8842 (((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \ 8843 HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S) 8844 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \ 8845 do { \ 8846 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \ 8847 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \ 8848 } while (0) 8849 8850 /* Dword 1: fisa_control_value add_udp_hdr_len */ 8851 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040 8852 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6 8853 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \ 8854 (((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \ 8855 HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S) 8856 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \ 8857 do { \ 8858 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \ 8859 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \ 8860 } while (0) 8861 8862 /* Dword 1: fisa_control_value chksum_cum_ip_len_en */ 8863 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080 8864 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7 8865 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \ 8866 (((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \ 8867 HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S) 8868 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \ 8869 do { \ 8870 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \ 8871 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \ 8872 } while (0) 8873 8874 /* Dword 1: fisa_control_value disable_tid_check */ 8875 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100 8876 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8 8877 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \ 8878 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \ 8879 HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S) 8880 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \ 8881 do { \ 8882 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \ 8883 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \ 8884 } while (0) 8885 8886 /* Dword 1: fisa_control_value disable_ta_check */ 8887 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200 8888 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9 8889 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \ 8890 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \ 8891 HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S) 8892 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \ 8893 do { \ 8894 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \ 8895 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \ 8896 } while (0) 8897 8898 /* Dword 1: fisa_control_value disable_qos_check */ 8899 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400 8900 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10 8901 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \ 8902 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \ 8903 HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S) 8904 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \ 8905 do { \ 8906 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \ 8907 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \ 8908 } while (0) 8909 8910 /* Dword 1: fisa_control_value disable_raw_check */ 8911 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800 8912 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11 8913 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \ 8914 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \ 8915 HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S) 8916 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \ 8917 do { \ 8918 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \ 8919 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \ 8920 } while (0) 8921 8922 /* Dword 1: fisa_control_value disable_decrypt_err_check */ 8923 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000 8924 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12 8925 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \ 8926 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \ 8927 HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S) 8928 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \ 8929 do { \ 8930 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \ 8931 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \ 8932 } while (0) 8933 8934 /* Dword 1: fisa_control_value disable_msdu_drop_check */ 8935 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000 8936 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13 8937 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \ 8938 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \ 8939 HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S) 8940 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \ 8941 do { \ 8942 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \ 8943 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \ 8944 } while (0) 8945 8946 /* Dword 1: fisa_control_value fisa_aggr_limit */ 8947 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000 8948 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14 8949 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \ 8950 (((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \ 8951 HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S) 8952 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \ 8953 do { \ 8954 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \ 8955 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \ 8956 } while (0) 8957 8958 /* Dword 1: fisa_control_value fisa config */ 8959 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M 0x00000001 8960 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S 0 8961 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_GET(_var) \ 8962 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M) >> \ 8963 HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S) 8964 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_SET(_var, _val) \ 8965 do { \ 8966 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_ENABLE, _val); \ 8967 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S)); \ 8968 } while (0) 8969 8970 /* Dword 1: fisa_control_value fisa_aggr_limit */ 8971 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e 8972 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1 8973 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \ 8974 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \ 8975 HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S) 8976 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_SET(_var, _val) \ 8977 do { \ 8978 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT, _val); \ 8979 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S)); \ 8980 } while (0) 8981 8982 PREPACK struct htt_h2t_msg_rx_fse_setup_t { 8983 A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */ 8984 pdev_id:8, 8985 reserved0:16; 8986 A_UINT32 num_records:20, 8987 max_search:8, 8988 ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */ 8989 reserved1:2; 8990 A_UINT32 base_addr_lo; 8991 A_UINT32 base_addr_hi; 8992 A_UINT32 toeplitz31_0; 8993 A_UINT32 toeplitz63_32; 8994 A_UINT32 toeplitz95_64; 8995 A_UINT32 toeplitz127_96; 8996 A_UINT32 toeplitz159_128; 8997 A_UINT32 toeplitz191_160; 8998 A_UINT32 toeplitz223_192; 8999 A_UINT32 toeplitz255_224; 9000 A_UINT32 toeplitz287_256; 9001 A_UINT32 toeplitz314_288:27, 9002 reserved2:5; 9003 } POSTPACK; 9004 9005 #define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t)) 9006 #define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t)) 9007 #define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t)) 9008 9009 #define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff 9010 #define HTT_RX_FSE_SETUP_HASH_314_288_S 0 9011 9012 /* DWORD 0: Pdev ID */ 9013 #define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00 9014 #define HTT_RX_FSE_SETUP_PDEV_ID_S 8 9015 #define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \ 9016 (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \ 9017 HTT_RX_FSE_SETUP_PDEV_ID_S) 9018 #define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \ 9019 do { \ 9020 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \ 9021 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \ 9022 } while (0) 9023 9024 /* DWORD 1:num of records */ 9025 #define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff 9026 #define HTT_RX_FSE_SETUP_NUM_REC_S 0 9027 #define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \ 9028 (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \ 9029 HTT_RX_FSE_SETUP_NUM_REC_S) 9030 #define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \ 9031 do { \ 9032 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \ 9033 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \ 9034 } while (0) 9035 9036 /* DWORD 1:max_search */ 9037 #define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000 9038 #define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20 9039 #define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \ 9040 (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \ 9041 HTT_RX_FSE_SETUP_MAX_SEARCH_S) 9042 #define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \ 9043 do { \ 9044 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \ 9045 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \ 9046 } while (0) 9047 9048 /* DWORD 1:ip_da_sa prefix */ 9049 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000 9050 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28 9051 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \ 9052 (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \ 9053 HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S) 9054 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \ 9055 do { \ 9056 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \ 9057 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \ 9058 } while (0) 9059 9060 /* DWORD 2: Base Address LO */ 9061 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff 9062 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0 9063 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \ 9064 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \ 9065 HTT_RX_FSE_SETUP_BASE_ADDR_LO_S) 9066 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \ 9067 do { \ 9068 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \ 9069 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \ 9070 } while (0) 9071 9072 /* DWORD 3: Base Address High */ 9073 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff 9074 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0 9075 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \ 9076 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \ 9077 HTT_RX_FSE_SETUP_BASE_ADDR_HI_S) 9078 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \ 9079 do { \ 9080 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \ 9081 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \ 9082 } while (0) 9083 9084 /* DWORD 4-12: Hash Value */ 9085 #define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff 9086 #define HTT_RX_FSE_SETUP_HASH_VALUE_S 0 9087 #define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \ 9088 (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \ 9089 HTT_RX_FSE_SETUP_HASH_VALUE_S) 9090 #define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \ 9091 do { \ 9092 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \ 9093 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \ 9094 } while (0) 9095 9096 /* DWORD 13: Hash Value 314:288 bits */ 9097 #define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \ 9098 (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \ 9099 HTT_RX_FSE_SETUP_HASH_314_288_S) 9100 #define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \ 9101 do { \ 9102 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \ 9103 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \ 9104 } while (0) 9105 9106 /** 9107 * @brief Host-->target HTT RX FSE operation message 9108 * 9109 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 9110 * 9111 * @details 9112 * The host will send this Flow Search Engine (FSE) operation message for 9113 * every flow add/delete operation. 9114 * The FSE operation includes FSE full cache invalidation or individual entry 9115 * invalidation. 9116 * This message can be sent per SOC or per PDEV which is differentiated 9117 * by pdev id values. 9118 * 9119 * |31 16|15 8|7 1|0| 9120 * |-------------------------------------------------------------| 9121 * | reserved | pdev_id | MSG_TYPE | 9122 * |-------------------------------------------------------------| 9123 * | reserved | operation |I| 9124 * |-------------------------------------------------------------| 9125 * | ip_src_addr_31_0 | 9126 * |-------------------------------------------------------------| 9127 * | ip_src_addr_63_32 | 9128 * |-------------------------------------------------------------| 9129 * | ip_src_addr_95_64 | 9130 * |-------------------------------------------------------------| 9131 * | ip_src_addr_127_96 | 9132 * |-------------------------------------------------------------| 9133 * | ip_dst_addr_31_0 | 9134 * |-------------------------------------------------------------| 9135 * | ip_dst_addr_63_32 | 9136 * |-------------------------------------------------------------| 9137 * | ip_dst_addr_95_64 | 9138 * |-------------------------------------------------------------| 9139 * | ip_dst_addr_127_96 | 9140 * |-------------------------------------------------------------| 9141 * | l4_dst_port | l4_src_port | 9142 * | (32-bit SPI incase of IPsec) | 9143 * |-------------------------------------------------------------| 9144 * | reserved | l4_proto | 9145 * |-------------------------------------------------------------| 9146 * 9147 * where I is 1-bit ipsec_valid. 9148 * 9149 * The following field definitions describe the format of the RX FSE operation 9150 * message sent from the host to target for every add/delete flow entry to flow 9151 * table. 9152 * 9153 * Header fields: 9154 * dword0 - b'7:0 - msg_type: This will be set to 9155 * 0x13 (HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG) 9156 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9157 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9158 * specified pdev's LMAC ring. 9159 * b'31:16 - reserved : Reserved for future use 9160 * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec 9161 * (Internet Protocol Security). 9162 * IPsec describes the framework for providing security at 9163 * IP layer. IPsec is defined for both versions of IP: 9164 * IPV4 and IPV6. 9165 * Please refer to htt_rx_flow_proto enumeration below for 9166 * more info. 9167 * ipsec_valid = 1 for IPSEC packets 9168 * ipsec_valid = 0 for IP Packets 9169 * b'7:1 - operation: This indicates types of FSE operation. 9170 * Refer to htt_rx_fse_operation enumeration: 9171 * 0 - No Cache Invalidation required 9172 * 1 - Cache invalidate only one entry given by IP 9173 * src/dest address at DWORD[2:9] 9174 * 2 - Complete FSE Cache Invalidation 9175 * 3 - FSE Disable 9176 * 4 - FSE Enable 9177 * b'31:8 - reserved: Reserved for future use 9178 * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address 9179 * for per flow addition/deletion 9180 * For IPV4 src/dest addresses, the first A_UINT32 is used 9181 * and the subsequent 3 A_UINT32 will be padding bytes. 9182 * For IPV6 src/dest Addresses, all A_UINT32 are used. 9183 * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range 9184 * from 0 to 65535 but only 0 to 1023 are designated as 9185 * well-known ports. Refer to [RFC1700] for more details. 9186 * This field is valid only if 9187 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9188 * - L4 dest port (31:16): 16-bit Destination Port numbers 9189 * range from 0 to 65535 but only 0 to 1023 are designated 9190 * as well-known ports. Refer to [RFC1700] for more details. 9191 * This field is valid only if 9192 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9193 * - SPI (31:0): Security Parameters Index is an 9194 * identification tag added to the header while using IPsec 9195 * for tunneling the IP traffici. 9196 * Valid only if IPSec_valid bit (in DWORD1) is set to 1. 9197 * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are 9198 * Assigned Internet Protocol Numbers. 9199 * l4_proto numbers for standard protocol like UDP/TCP 9200 * protocol at l4 layer, e.g. l4_proto = 6 for TCP, 9201 * l4_proto = 17 for UDP etc. 9202 * b'31:8 - reserved: Reserved for future use. 9203 * 9204 */ 9205 9206 PREPACK struct htt_h2t_msg_rx_fse_operation_t { 9207 A_UINT32 msg_type:8, 9208 pdev_id:8, 9209 reserved0:16; 9210 A_UINT32 ipsec_valid:1, 9211 operation:7, 9212 reserved1:24; 9213 A_UINT32 ip_src_addr_31_0; 9214 A_UINT32 ip_src_addr_63_32; 9215 A_UINT32 ip_src_addr_95_64; 9216 A_UINT32 ip_src_addr_127_96; 9217 A_UINT32 ip_dest_addr_31_0; 9218 A_UINT32 ip_dest_addr_63_32; 9219 A_UINT32 ip_dest_addr_95_64; 9220 A_UINT32 ip_dest_addr_127_96; 9221 union { 9222 A_UINT32 spi; 9223 struct { 9224 A_UINT32 l4_src_port:16, 9225 l4_dest_port:16; 9226 } ip; 9227 } u; 9228 A_UINT32 l4_proto:8, 9229 reserved:24; 9230 } POSTPACK; 9231 9232 /** 9233 * @brief Host-->target HTT RX Full monitor mode register configuration message 9234 * 9235 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE 9236 * 9237 * @details 9238 * The host will send this Full monitor mode register configuration message. 9239 * This message can be sent per SOC or per PDEV which is differentiated 9240 * by pdev id values. 9241 * 9242 * |31 16|15 11|10 8|7 3|2|1|0| 9243 * |-------------------------------------------------------------| 9244 * | reserved | pdev_id | MSG_TYPE | 9245 * |-------------------------------------------------------------| 9246 * | reserved |Release Ring |N|Z|E| 9247 * |-------------------------------------------------------------| 9248 * 9249 * where E is 1-bit full monitor mode enable/disable. 9250 * Z is 1-bit additional descriptor for zero mpdu enable/disable 9251 * N is 1-bit additional descriptor for non zero mdpu enable/disable 9252 * 9253 * The following field definitions describe the format of the full monitor 9254 * mode configuration message sent from the host to target for each pdev. 9255 * 9256 * Header fields: 9257 * dword0 - b'7:0 - msg_type: This will be set to 9258 * 0x17 (HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE) 9259 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9260 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9261 * specified pdev's LMAC ring. 9262 * b'31:16 - reserved : Reserved for future use. 9263 * dword1 - b'0 - full_monitor_mode enable: This indicates that the full 9264 * monitor mode rxdma register is to be enabled or disabled. 9265 * b'1 - addnl_descs_zero_mpdus_end: This indicates that the 9266 * additional descriptors at ppdu end for zero mpdus 9267 * enabled or disabled. 9268 * b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the 9269 * additional descriptors at ppdu end for non zero mpdus 9270 * enabled or disabled. 9271 * b'10:3 - release_ring: This indicates the destination ring 9272 * selection for the descriptor at the end of PPDU 9273 * 0 - REO ring select 9274 * 1 - FW ring select 9275 * 2 - SW ring select 9276 * 3 - Release ring select 9277 * Refer to htt_rx_full_mon_release_ring. 9278 * b'31:11 - reserved for future use 9279 */ 9280 PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t { 9281 A_UINT32 msg_type:8, 9282 pdev_id:8, 9283 reserved0:16; 9284 A_UINT32 full_monitor_mode_enable:1, 9285 addnl_descs_zero_mpdus_end:1, 9286 addnl_descs_non_zero_mpdus_end:1, 9287 release_ring:8, 9288 reserved1:21; 9289 } POSTPACK; 9290 9291 /** 9292 * Enumeration for full monitor mode destination ring select 9293 * 0 - REO destination ring select 9294 * 1 - FW destination ring select 9295 * 2 - SW destination ring select 9296 * 3 - Release destination ring select 9297 */ 9298 enum htt_rx_full_mon_release_ring { 9299 HTT_RX_MON_RING_REO, 9300 HTT_RX_MON_RING_FW, 9301 HTT_RX_MON_RING_SW, 9302 HTT_RX_MON_RING_RELEASE, 9303 }; 9304 9305 #define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t)) 9306 /* DWORD 0: Pdev ID */ 9307 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00 9308 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8 9309 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \ 9310 (((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \ 9311 HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S) 9312 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \ 9313 do { \ 9314 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \ 9315 ((_var) |= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \ 9316 } while (0) 9317 9318 /* DWORD 1:ENABLE */ 9319 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001 9320 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0 9321 9322 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \ 9323 do { \ 9324 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \ 9325 (word) |= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \ 9326 } while (0) 9327 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \ 9328 (((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S) 9329 9330 /* DWORD 1:ZERO_MPDU */ 9331 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002 9332 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1 9333 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \ 9334 do { \ 9335 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \ 9336 (word) |= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \ 9337 } while (0) 9338 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \ 9339 (((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S) 9340 9341 9342 /* DWORD 1:NON_ZERO_MPDU */ 9343 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004 9344 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2 9345 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \ 9346 do { \ 9347 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \ 9348 (word) |= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \ 9349 } while (0) 9350 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \ 9351 (((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S) 9352 9353 /* DWORD 1:RELEASE_RINGS */ 9354 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8 9355 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3 9356 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \ 9357 do { \ 9358 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \ 9359 (word) |= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \ 9360 } while (0) 9361 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \ 9362 (((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S) 9363 9364 /** 9365 * Enumeration for IP Protocol or IPSEC Protocol 9366 * IPsec describes the framework for providing security at IP layer. 9367 * IPsec is defined for both versions of IP: IPV4 and IPV6. 9368 */ 9369 enum htt_rx_flow_proto { 9370 HTT_RX_FLOW_IP_PROTO, 9371 HTT_RX_FLOW_IPSEC_PROTO, 9372 }; 9373 9374 /** 9375 * Enumeration for FSE Cache Invalidation 9376 * 0 - No Cache Invalidation required 9377 * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9 9378 * 2 - Complete FSE Cache Invalidation 9379 * 3 - FSE Disable 9380 * 4 - FSE Enable 9381 */ 9382 enum htt_rx_fse_operation { 9383 HTT_RX_FSE_CACHE_INVALIDATE_NONE, 9384 HTT_RX_FSE_CACHE_INVALIDATE_ENTRY, 9385 HTT_RX_FSE_CACHE_INVALIDATE_FULL, 9386 HTT_RX_FSE_DISABLE, 9387 HTT_RX_FSE_ENABLE, 9388 }; 9389 9390 /* DWORD 0: Pdev ID */ 9391 #define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00 9392 #define HTT_RX_FSE_OPERATION_PDEV_ID_S 8 9393 #define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \ 9394 (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \ 9395 HTT_RX_FSE_OPERATION_PDEV_ID_S) 9396 #define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \ 9397 do { \ 9398 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \ 9399 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \ 9400 } while (0) 9401 9402 /* DWORD 1:IP PROTO or IPSEC */ 9403 #define HTT_RX_FSE_IPSEC_VALID_M 0x00000001 9404 #define HTT_RX_FSE_IPSEC_VALID_S 0 9405 9406 #define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \ 9407 do { \ 9408 HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \ 9409 (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \ 9410 } while (0) 9411 #define HTT_RX_FSE_IPSEC_VALID_GET(word) \ 9412 (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S) 9413 9414 /* DWORD 1:FSE Operation */ 9415 #define HTT_RX_FSE_OPERATION_M 0x000000fe 9416 #define HTT_RX_FSE_OPERATION_S 1 9417 9418 #define HTT_RX_FSE_OPERATION_SET(word, op_val) \ 9419 do { \ 9420 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \ 9421 (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \ 9422 } while (0) 9423 #define HTT_RX_FSE_OPERATION_GET(word) \ 9424 (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S) 9425 9426 /* DWORD 2-9:IP Address */ 9427 #define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff 9428 #define HTT_RX_FSE_OPERATION_IP_ADDR_S 0 9429 #define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \ 9430 (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \ 9431 HTT_RX_FSE_OPERATION_IP_ADDR_S) 9432 #define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \ 9433 do { \ 9434 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \ 9435 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \ 9436 } while (0) 9437 9438 /* DWORD 10:Source Port Number */ 9439 #define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff 9440 #define HTT_RX_FSE_SOURCEPORT_S 0 9441 9442 #define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \ 9443 do { \ 9444 HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \ 9445 (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \ 9446 } while (0) 9447 #define HTT_RX_FSE_SOURCEPORT_GET(word) \ 9448 (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S) 9449 9450 9451 /* DWORD 11:Destination Port Number */ 9452 #define HTT_RX_FSE_DESTPORT_M 0xffff0000 9453 #define HTT_RX_FSE_DESTPORT_S 16 9454 9455 #define HTT_RX_FSE_DESTPORT_SET(word, dport) \ 9456 do { \ 9457 HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \ 9458 (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \ 9459 } while (0) 9460 #define HTT_RX_FSE_DESTPORT_GET(word) \ 9461 (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S) 9462 9463 /* DWORD 10-11:SPI (In case of IPSEC) */ 9464 #define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff 9465 #define HTT_RX_FSE_OPERATION_SPI_S 0 9466 #define HTT_RX_FSE_OPERATION_SPI_GET(_var) \ 9467 (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \ 9468 HTT_RX_FSE_OPERATION_SPI_ADDR_S) 9469 #define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \ 9470 do { \ 9471 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \ 9472 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \ 9473 } while (0) 9474 9475 /* DWORD 12:L4 PROTO */ 9476 #define HTT_RX_FSE_L4_PROTO_M 0x000000ff 9477 #define HTT_RX_FSE_L4_PROTO_S 0 9478 9479 #define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \ 9480 do { \ 9481 HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \ 9482 (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \ 9483 } while (0) 9484 #define HTT_RX_FSE_L4_PROTO_GET(word) \ 9485 (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S) 9486 9487 9488 /** 9489 * @brief host --> target Receive to configure the RxOLE 3-tuple Hash 9490 * 9491 * MSG_TYPE => HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG 9492 * 9493 * |31 24|23 |15 8|7 2|1|0| 9494 * |----------------+----------------+----------------+----------------| 9495 * | reserved | pdev_id | msg_type | 9496 * |---------------------------------+----------------+----------------| 9497 * | reserved |E|F| 9498 * |---------------------------------+----------------+----------------| 9499 * Where E = Configure the target to provide the 3-tuple hash value in 9500 * toeplitz_hash_2_or_4 field of rx_msdu_start tlv 9501 * F = Configure the target to provide the 3-tuple hash value in 9502 * flow_id_toeplitz field of rx_msdu_start tlv 9503 * 9504 * The following field definitions describe the format of the 3 tuple hash value 9505 * message sent from the host to target as part of initialization sequence. 9506 * 9507 * Header fields: 9508 * dword0 - b'7:0 - msg_type: This will be set to 9509 * 0x16 (HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG) 9510 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9511 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9512 * specified pdev's LMAC ring. 9513 * b'31:16 - reserved : Reserved for future use 9514 * dword1 - b'0 - flow_id_toeplitz_field_enable 9515 * b'1 - toeplitz_hash_2_or_4_field_enable 9516 * b'31:2 - reserved : Reserved for future use 9517 * ---------+------+---------------------------------------------------------- 9518 * bit1 | bit0 | Functionality 9519 * ---------+------+---------------------------------------------------------- 9520 * 0 | 1 | Configure the target to provide the 3 tuple hash value 9521 * | | in flow_id_toeplitz field 9522 * ---------+------+---------------------------------------------------------- 9523 * 1 | 0 | Configure the target to provide the 3 tuple hash value 9524 * | | in toeplitz_hash_2_or_4 field 9525 * ---------+------+---------------------------------------------------------- 9526 * 1 | 1 | Configure the target to provide the 3 tuple hash value 9527 * | | in both flow_id_toeplitz & toeplitz_hash_2_or_4 field 9528 * ---------+------+---------------------------------------------------------- 9529 * 0 | 0 | Configure the target to provide the 5 tuple hash value 9530 * | | in flow_id_toeplitz field 2 or 4 tuple has value in 9531 * | | toeplitz_hash_2_or_4 field 9532 *---------------------------------------------------------------------------- 9533 */ 9534 PREPACK struct htt_h2t_msg_rx_3_tuple_hash_cfg_t { 9535 A_UINT32 msg_type :8, 9536 pdev_id :8, 9537 reserved0 :16; 9538 A_UINT32 flow_id_toeplitz_field_enable :1, 9539 toeplitz_hash_2_or_4_field_enable :1, 9540 reserved1 :30; 9541 } POSTPACK; 9542 9543 /* DWORD0 : pdev_id configuration Macros */ 9544 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_M 0xff00 9545 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_S 8 9546 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_GET(_var) \ 9547 (((_var) & HTT_H2T_3_TUPLE_HASH_PDEV_ID_M) >> \ 9548 HTT_H2T_3_TUPLE_HASH_PDEV_ID_S) 9549 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_SET(_var, _val) \ 9550 do { \ 9551 HTT_CHECK_SET_VAL(HTT_H2T_3_TUPLE_HASH_PDEV_ID, _val); \ 9552 ((_var) |= ((_val) << HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)); \ 9553 } while (0) 9554 9555 /* DWORD1: rx 3 tuple hash value reception field configuration Macros */ 9556 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M 0x1 9557 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S 0 9558 #define HTT_FLOW_ID_TOEPLITZ_FIELD_CONFIG_GET(_var) \ 9559 (((_var) & HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M) >> \ 9560 HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S) 9561 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_SET(_var, _val) \ 9562 do { \ 9563 HTT_CHECK_SET_VAL(HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG, _val); \ 9564 ((_var) |= ((_val) << HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)); \ 9565 } while (0) 9566 9567 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M 0x2 9568 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S 1 9569 #define HTT_TOEPLITZ_2_OR_4_FIELD_CONFIG_GET(_var) \ 9570 (((_var) & HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M) >> \ 9571 HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S) 9572 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_SET(_var, _val) \ 9573 do { \ 9574 HTT_CHECK_SET_VAL(HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG, _val); \ 9575 ((_var) |= ((_val) << HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)); \ 9576 } while (0) 9577 9578 #define HTT_3_TUPLE_HASH_CFG_REQ_BYTES 8 9579 9580 /** 9581 * @brief host --> target Host PA Address Size 9582 * 9583 * MSG_TYPE => HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE 9584 * 9585 * @details 9586 * The HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE message is sent by the host to 9587 * provide the physical start address and size of each of the memory 9588 * areas within host DDR that the target FW may need to access. 9589 * 9590 * For example, the host can use this message to allow the target FW 9591 * to set up access to the host's pools of TQM link descriptors. 9592 * The message would appear as follows: 9593 * 9594 * |31 24|23 16|15 8|7 0| 9595 * |----------------+----------------+----------------+----------------| 9596 * | reserved | num_entries | msg_type | 9597 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9598 * | mem area 0 size | 9599 * |----------------+----------------+----------------+----------------| 9600 * | mem area 0 physical_address_lo | 9601 * |----------------+----------------+----------------+----------------| 9602 * | mem area 0 physical_address_hi | 9603 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9604 * | mem area 1 size | 9605 * |----------------+----------------+----------------+----------------| 9606 * | mem area 1 physical_address_lo | 9607 * |----------------+----------------+----------------+----------------| 9608 * | mem area 1 physical_address_hi | 9609 * |----------------+----------------+----------------+----------------| 9610 * ... 9611 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9612 * | mem area N size | 9613 * |----------------+----------------+----------------+----------------| 9614 * | mem area N physical_address_lo | 9615 * |----------------+----------------+----------------+----------------| 9616 * | mem area N physical_address_hi | 9617 * |----------------+----------------+----------------+----------------| 9618 * 9619 * The message is interpreted as follows: 9620 * dword0 - b'0:7 - msg_type: This will be set to 9621 * 0x18 (HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE) 9622 * b'8:15 - number_entries: Indicated the number of host memory 9623 * areas specified within the remainder of the message 9624 * b'16:31 - reserved. 9625 * dword1 - b'0:31 - memory area 0 size in bytes 9626 * dword2 - b'0:31 - memory area 0 physical address, lower 32 bits 9627 * dword3 - b'0:31 - memory area 0 physical address, upper 32 bits 9628 * and similar for memory area 1 through memory area N. 9629 */ 9630 9631 PREPACK struct htt_h2t_host_paddr_size { 9632 A_UINT32 msg_type: 8, 9633 num_entries: 8, 9634 reserved: 16; 9635 } POSTPACK; 9636 9637 PREPACK struct htt_h2t_host_paddr_size_entry_t { 9638 A_UINT32 size; 9639 A_UINT32 physical_address_lo; 9640 A_UINT32 physical_address_hi; 9641 } POSTPACK; 9642 9643 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE \ 9644 (sizeof(struct htt_h2t_host_paddr_size_entry_t)) 9645 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_DWORDS \ 9646 (HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE >> 2) 9647 9648 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M 0x0000FF00 9649 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S 8 9650 9651 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_GET(_var) \ 9652 (((_var) & HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M) >> \ 9653 HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S) 9654 9655 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_SET(_var, _val) \ 9656 do { \ 9657 HTT_CHECK_SET_VAL(HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES, _val); \ 9658 ((_var) |= ((_val) << HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S)); \ 9659 } while (0) 9660 9661 /** 9662 * @brief host --> target Host RXDMA RXOLE PPE register configuration 9663 * 9664 * MSG_TYPE => HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG 9665 * 9666 * @details 9667 * The HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG message is sent by the host to 9668 * provide the PPE DS register confiuration for RXOLE and RXDMA. 9669 * 9670 * The message would appear as follows: 9671 * 9672 * |31 19|18 |17 |16 |15 |14 |13 9|8|7 0| 9673 * |---------------------------------+---+---+----------+-+-----------| 9674 * | reserved |IFO|DNO|DRO|IBO|MIO| RDI |O| msg_type | 9675 * |---------------------+---+---+---+---+---+----------+-+-----------| 9676 * 9677 * 9678 * The message is interpreted as follows: 9679 * dword0 - b'0:7 - msg_type: This will be set to 9680 * 0x19 (HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG) 9681 * b'8 - override bit to drive MSDUs to PPE ring 9682 * b'9:13 - REO destination ring indication 9683 * b'14 - Multi buffer msdu override enable bit 9684 * b'15 - Intra BSS override 9685 * b'16 - Decap raw override 9686 * b'17 - Decap Native wifi override 9687 * b'18 - IP frag override 9688 * b'19:31 - reserved 9689 */ 9690 PREPACK struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg_t { 9691 A_UINT32 msg_type: 8, /* HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG */ 9692 override: 1, 9693 reo_destination_indication: 5, 9694 multi_buffer_msdu_override_en: 1, 9695 intra_bss_override: 1, 9696 decap_raw_override: 1, 9697 decap_nwifi_override: 1, 9698 ip_frag_override: 1, 9699 reserved: 13; 9700 } POSTPACK; 9701 9702 /* DWORD 0: Override */ 9703 #define HTT_PPE_CFG_OVERRIDE_M 0x00000100 9704 #define HTT_PPE_CFG_OVERRIDE_S 8 9705 #define HTT_PPE_CFG_OVERRIDE_GET(_var) \ 9706 (((_var) & HTT_PPE_CFG_OVERRIDE_M) >> \ 9707 HTT_PPE_CFG_OVERRIDE_S) 9708 #define HTT_PPE_CFG_OVERRIDE_SET(_var, _val) \ 9709 do { \ 9710 HTT_CHECK_SET_VAL(HTT_PPE_CFG_OVERRIDE, _val); \ 9711 ((_var) |= ((_val) << HTT_PPE_CFG_OVERRIDE_S)); \ 9712 } while (0) 9713 9714 /* DWORD 0: REO Destination Indication*/ 9715 #define HTT_PPE_CFG_REO_DEST_IND_M 0x00003E00 9716 #define HTT_PPE_CFG_REO_DEST_IND_S 9 9717 #define HTT_PPE_CFG_REO_DEST_IND_GET(_var) \ 9718 (((_var) & HTT_PPE_CFG_REO_DEST_IND_M) >> \ 9719 HTT_PPE_CFG_REO_DEST_IND_S) 9720 #define HTT_PPE_CFG_REO_DEST_IND_SET(_var, _val) \ 9721 do { \ 9722 HTT_CHECK_SET_VAL(HTT_PPE_CFG_REO_DEST_IND, _val); \ 9723 ((_var) |= ((_val) << HTT_PPE_CFG_REO_DEST_IND_S)); \ 9724 } while (0) 9725 9726 /* DWORD 0: Multi buffer MSDU override */ 9727 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M 0x00004000 9728 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S 14 9729 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_GET(_var) \ 9730 (((_var) & HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M) >> \ 9731 HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S) 9732 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_SET(_var, _val) \ 9733 do { \ 9734 HTT_CHECK_SET_VAL(HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN, _val); \ 9735 ((_var) |= ((_val) << HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S)); \ 9736 } while (0) 9737 9738 /* DWORD 0: Intra BSS override */ 9739 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M 0x00008000 9740 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S 15 9741 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_GET(_var) \ 9742 (((_var) & HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M) >> \ 9743 HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S) 9744 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_SET(_var, _val) \ 9745 do { \ 9746 HTT_CHECK_SET_VAL(HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN, _val); \ 9747 ((_var) |= ((_val) << HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S)); \ 9748 } while (0) 9749 9750 /* DWORD 0: Decap RAW override */ 9751 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M 0x00010000 9752 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S 16 9753 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_GET(_var) \ 9754 (((_var) & HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M) >> \ 9755 HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S) 9756 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_SET(_var, _val) \ 9757 do { \ 9758 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN, _val); \ 9759 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S)); \ 9760 } while (0) 9761 9762 /* DWORD 0: Decap NWIFI override */ 9763 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M 0x00020000 9764 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S 17 9765 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_GET(_var) \ 9766 (((_var) & HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M) >> \ 9767 HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S) 9768 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_SET(_var, _val) \ 9769 do { \ 9770 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN, _val); \ 9771 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S)); \ 9772 } while (0) 9773 9774 /* DWORD 0: IP frag override */ 9775 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M 0x00040000 9776 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S 18 9777 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_GET(_var) \ 9778 (((_var) & HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M) >> \ 9779 HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S) 9780 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_SET(_var, _val) \ 9781 do { \ 9782 HTT_CHECK_SET_VAL(HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN, _val); \ 9783 ((_var) |= ((_val) << HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S)); \ 9784 } while (0) 9785 9786 /* 9787 * MSG_TYPE => HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG 9788 * 9789 * @details 9790 * The following field definitions describe the format of the HTT host 9791 * to target FW VDEV TX RX stats retrieve message. 9792 * The message specifies the type of stats the host wants to retrieve. 9793 * 9794 * |31 27|26 25|24 17|16|15 8|7 0| 9795 * |-----------------------------------------------------------| 9796 * | rsvd | R | Periodic Int| E| pdev_id | msg type | 9797 * |-----------------------------------------------------------| 9798 * | vdev_id lower bitmask | 9799 * |-----------------------------------------------------------| 9800 * | vdev_id upper bitmask | 9801 * |-----------------------------------------------------------| 9802 * Header fields: 9803 * Where: 9804 * dword0 - b'7:0 - msg_type: This will be set to 9805 * 0x1a (HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG) 9806 * b'15:8 - pdev id 9807 * b'16(E) - Enable/Disable the vdev HW stats 9808 * b'17:24(PI) - Periodic Interval, units = 8 ms, e.g. 125 -> 1000 ms 9809 * b'25:26(R) - Reset stats bits 9810 * 0: don't reset stats 9811 * 1: reset stats once 9812 * 2: reset stats at the start of each periodic interval 9813 * b'27:31 - reserved for future use 9814 * dword1 - b'0:31 - vdev_id lower bitmask 9815 * dword2 - b'0:31 - vdev_id upper bitmask 9816 */ 9817 9818 PREPACK struct htt_h2t_vdevs_txrx_stats_cfg { 9819 A_UINT32 msg_type :8, 9820 pdev_id :8, 9821 enable :1, 9822 periodic_interval :8, 9823 reset_stats_bits :2, 9824 reserved0 :5; 9825 A_UINT32 vdev_id_lower_bitmask; 9826 A_UINT32 vdev_id_upper_bitmask; 9827 } POSTPACK; 9828 9829 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M 0xFF00 9830 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S 8 9831 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_GET(_var) \ 9832 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M) >> \ 9833 HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S) 9834 #define HTT_RX_VDEVS_TXRX_STATS_PDEV_ID_SET(_var, _val) \ 9835 do { \ 9836 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID, _val); \ 9837 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S)); \ 9838 } while (0) 9839 9840 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M 0x10000 9841 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S 16 9842 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_GET(_var) \ 9843 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M) >> \ 9844 HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S) 9845 #define HTT_RX_VDEVS_TXRX_STATS_ENABLE_SET(_var, _val) \ 9846 do { \ 9847 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_ENABLE, _val); \ 9848 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S)); \ 9849 } while (0) 9850 9851 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M 0x1FE0000 9852 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S 17 9853 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_GET(_var) \ 9854 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M) >> \ 9855 HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S) 9856 #define HTT_RX_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_SET(_var, _val) \ 9857 do { \ 9858 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL, _val); \ 9859 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S)); \ 9860 } while (0) 9861 9862 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M 0x6000000 9863 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S 25 9864 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_GET(_var) \ 9865 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M) >> \ 9866 HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S) 9867 #define HTT_RX_VDEVS_TXRX_STATS_RESET_STATS_BITS_SET(_var, _val) \ 9868 do { \ 9869 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS, _val); \ 9870 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S)); \ 9871 } while (0) 9872 9873 9874 /* 9875 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ 9876 * 9877 * @details 9878 * The SAWF_DEF_QUEUES_MAP_REQ message is sent by the host to link 9879 * the default MSDU queues for one of the TIDs within the specified peer 9880 * to the specified service class. 9881 * The TID is indirectly specified - each service class is associated 9882 * with a TID. All default MSDU queues for this peer-TID will be 9883 * linked to the service class in question. 9884 * 9885 * |31 16|15 8|7 0| 9886 * |------------------------------+--------------+--------------| 9887 * | peer ID | svc class ID | msg type | 9888 * |------------------------------------------------------------| 9889 * Header fields: 9890 * dword0 - b'7:0 - msg_type: This will be set to 9891 * 0x1c (HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ) 9892 * b'15:8 - service class ID 9893 * b'31:16 - peer ID 9894 */ 9895 9896 PREPACK struct htt_h2t_sawf_def_queues_map_req { 9897 A_UINT32 msg_type :8, 9898 svc_class_id :8, 9899 peer_id :16; 9900 } POSTPACK; 9901 9902 #define HTT_SAWF_DEF_QUEUES_MAP_REQ_BYTES 4 9903 9904 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M 0x0000FF00 9905 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S 8 9906 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_GET(_var) \ 9907 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M) >> \ 9908 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S) 9909 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_SET(_var, _val) \ 9910 do { \ 9911 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID, _val); \ 9912 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S));\ 9913 } while (0) 9914 9915 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M 0xFFFF0000 9916 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S 16 9917 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_GET(_var) \ 9918 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M) >> \ 9919 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S) 9920 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_SET(_var, _val) \ 9921 do { \ 9922 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID, _val); \ 9923 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S)); \ 9924 } while (0) 9925 9926 9927 /* 9928 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ 9929 * 9930 * @details 9931 * The SAWF_DEF_QUEUES_UNMAP_REQ message is sent by the host to 9932 * remove the linkage of the specified peer-TID's MSDU queues to 9933 * service classes. 9934 * 9935 * |31 16|15 8|7 0| 9936 * |------------------------------+--------------+--------------| 9937 * | peer ID | svc class ID | msg type | 9938 * |------------------------------------------------------------| 9939 * Header fields: 9940 * dword0 - b'7:0 - msg_type: This will be set to 9941 * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ) 9942 * b'15:8 - service class ID 9943 * b'31:16 - peer ID 9944 * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 9945 * value for peer ID indicates that the target should 9946 * apply the UNMAP_REQ to all peers. 9947 */ 9948 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 0xff 9949 PREPACK struct htt_h2t_sawf_def_queues_unmap_req { 9950 A_UINT32 msg_type :8, 9951 svc_class_id :8, 9952 peer_id :16; 9953 } POSTPACK; 9954 9955 #define HTT_SAWF_DEF_QUEUES_UNMAP_REQ_BYTES 4 9956 9957 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M 0x0000FF00 9958 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S 8 9959 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(word0) \ 9960 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \ 9961 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S) 9962 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(word0, _val) \ 9963 do { \ 9964 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID, _val); \ 9965 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \ 9966 } while (0) 9967 9968 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M 0xFFFF0000 9969 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S 16 9970 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(word0) \ 9971 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \ 9972 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S) 9973 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(word0, _val) \ 9974 do { \ 9975 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID, _val); \ 9976 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \ 9977 } while (0) 9978 9979 /* 9980 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ 9981 * 9982 * @details 9983 * The SAWF_DEF_QUEUES_MAP_REPORT_REQ message is sent by the host to 9984 * request the target to report what service class the default MSDU queues 9985 * of the specified TIDs within the peer are linked to. 9986 * The target will respond with a SAWF_DEF_QUEUES_MAP_REPORT_CONF message 9987 * to report what service class (if any) the default MSDU queues for 9988 * each of the specified TIDs are linked to. 9989 * 9990 * |31 16|15 8|7 1| 0| 9991 * |------------------------------+--------------+--------------| 9992 * | peer ID | TID mask | msg type | 9993 * |------------------------------------------------------------| 9994 * | reserved |ETO| 9995 * |------------------------------------------------------------| 9996 * Header fields: 9997 * dword0 - b'7:0 - msg_type: This will be set to 9998 * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ) 9999 * b'15:8 - TID mask 10000 * b'31:16 - peer ID 10001 * dword1 - b'0 - "Existing Tids Only" flag 10002 * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF 10003 * message generated by this REQ will only show the 10004 * mapping for TIDs that actually exist in the target's 10005 * peer object. 10006 * Any TIDs that are covered by a MAP_REQ but which 10007 * do not actually exist will be shown as being 10008 * unmapped (i.e. svc class ID 0xff). 10009 * If this flag is cleared, the MAP_REPORT_CONF message 10010 * will consider not only the mapping of TIDs currently 10011 * existing in the peer, but also the mapping that will 10012 * be applied for any TID objects created within this 10013 * peer in the future. 10014 * b'31:1 - reserved for future use 10015 */ 10016 10017 PREPACK struct htt_h2t_sawf_def_queues_map_report_req { 10018 A_UINT32 msg_type :8, 10019 tid_mask :8, 10020 peer_id :16; 10021 A_UINT32 existing_tids_only:1, 10022 reserved :31; 10023 } POSTPACK; 10024 10025 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 8 10026 10027 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M 0x0000FF00 10028 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S 8 10029 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(word0) \ 10030 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \ 10031 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S) 10032 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(word0, _val) \ 10033 do { \ 10034 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK, _val); \ 10035 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\ 10036 } while (0) 10037 10038 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M 0xFFFF0000 10039 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S 16 10040 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(word0) \ 10041 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \ 10042 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S) 10043 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(word0, _val) \ 10044 do { \ 10045 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID, _val); \ 10046 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \ 10047 } while (0) 10048 10049 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M 0x00000001 10050 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S 0 10051 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_GET(word1) \ 10052 (((word1) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M) >> \ 10053 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S) 10054 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_SET(word1, _val) \ 10055 do { \ 10056 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY, _val); \ 10057 ((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \ 10058 } while (0) 10059 10060 /** 10061 * @brief Format of shared memory between Host and Target 10062 * for UMAC recovery feature messaging. 10063 * @details 10064 * This is shared memory between Host and Target allocated 10065 * and used in chips where UMAC recovery feature is supported. 10066 * This shared memory is allocated per SOC level by Host since each 10067 * SOC's target Q6FW needs to communicate independently to the Host 10068 * through its own shared memory. 10069 * If target sets a bit in t2h_msg (provided it's valid bit offset) 10070 * then host interprets it as a new message from target. 10071 * Host clears that particular read bit in t2h_msg after each read 10072 * operation. It is vice versa for h2t_msg. At any given point 10073 * of time there is expected to be only one bit set 10074 * either in t2h_msg or h2t_msg (referring to valid bit offset). 10075 * 10076 * The message is interpreted as follows: 10077 * dword0 - b'0:31 - magic_num: Magic number for the shared memory region 10078 * added for debuggability purpose. 10079 * dword1 - b'0 - do_pre_reset 10080 * b'1 - do_post_reset_start 10081 * b'2 - do_post_reset_complete 10082 * b'3 - initiate_umac_recovery 10083 * b'4 - initiate_target_recovery_sync_using_umac 10084 * b'5:31 - rsvd_t2h 10085 * dword2 - b'0 - pre_reset_done 10086 * b'1 - post_reset_start_done 10087 * b'2 - post_reset_complete_done 10088 * b'3 - start_pre_reset (deprecated) 10089 * b'4:31 - rsvd_h2t 10090 */ 10091 PREPACK typedef struct { 10092 /** Magic number added for debuggability. */ 10093 A_UINT32 magic_num; 10094 union { 10095 /* 10096 * BIT [0] :- T2H msg to do pre-reset 10097 * BIT [1] :- T2H msg to do post-reset start 10098 * BIT [2] :- T2H msg to do post-reset complete 10099 * BIT [3] :- T2H msg to indicate to Host that 10100 * a trigger request for MLO UMAC Recovery 10101 * is received for UMAC hang. 10102 * BIT [4] :- T2H msg to indicate to Host that 10103 * a trigger request for MLO UMAC Recovery 10104 * is received for Mode-1 Target Recovery. 10105 * BIT [31 : 5] :- reserved 10106 */ 10107 A_UINT32 t2h_msg; 10108 struct { 10109 A_UINT32 10110 do_pre_reset: 1, /* BIT [0] */ 10111 do_post_reset_start: 1, /* BIT [1] */ 10112 do_post_reset_complete: 1, /* BIT [2] */ 10113 initiate_umac_recovery: 1, /* BIT [3] */ 10114 initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ 10115 rsvd_t2h: 27; /* BIT [31:5] */ 10116 }; 10117 }; 10118 10119 union { 10120 /* 10121 * BIT [0] :- H2T msg to send pre-reset done 10122 * BIT [1] :- H2T msg to send post-reset start done 10123 * BIT [2] :- H2T msg to send post-reset complete done 10124 * BIT [3] :- H2T msg to start pre-reset. This is deprecated. 10125 * BIT [31 : 4] :- reserved 10126 */ 10127 A_UINT32 h2t_msg; 10128 struct { 10129 A_UINT32 pre_reset_done : 1, /* BIT [0] */ 10130 post_reset_start_done : 1, /* BIT [1] */ 10131 post_reset_complete_done : 1, /* BIT [2] */ 10132 start_pre_reset : 1, /* BIT [3] */ 10133 rsvd_h2t : 28; /* BIT [31 : 4] */ 10134 }; 10135 }; 10136 } POSTPACK htt_umac_hang_recovery_msg_shmem_t; 10137 10138 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES \ 10139 (sizeof(htt_umac_hang_recovery_msg_shmem_t)) 10140 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DWORDS \ 10141 (HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES >> 2) 10142 10143 /* dword1 - b'0 - do_pre_reset */ 10144 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M 0x00000001 10145 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S 0 10146 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_GET(word1) \ 10147 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M) >> \ 10148 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S) 10149 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_SET(word1, _val) \ 10150 do { \ 10151 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET, _val); \ 10152 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S));\ 10153 } while (0) 10154 10155 /* dword1 - b'1 - do_post_reset_start */ 10156 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M 0x00000002 10157 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S 1 10158 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_GET(word1) \ 10159 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M) >> \ 10160 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S) 10161 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_SET(word1, _val) \ 10162 do { \ 10163 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START, _val); \ 10164 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S));\ 10165 } while (0) 10166 10167 /* dword1 - b'2 - do_post_reset_complete */ 10168 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M 0x00000004 10169 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S 2 10170 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_GET(word1) \ 10171 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M) >> \ 10172 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S) 10173 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_SET(word1, _val) \ 10174 do { \ 10175 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE, _val); \ 10176 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\ 10177 } while (0) 10178 10179 /* dword1 - b'3 - initiate_umac_recovery */ 10180 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 10181 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 10182 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ 10183 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ 10184 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) 10185 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ 10186 do { \ 10187 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY, _val); \ 10188 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ 10189 } while (0) 10190 10191 /* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ 10192 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 10193 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 10194 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ 10195 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ 10196 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) 10197 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ 10198 do { \ 10199 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ 10200 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ 10201 } while (0) 10202 10203 /* dword2 - b'0 - pre_reset_done */ 10204 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 10205 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 10206 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_GET(word2) \ 10207 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M) >> \ 10208 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S) 10209 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_SET(word2, _val) \ 10210 do { \ 10211 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE, _val); \ 10212 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S));\ 10213 } while (0) 10214 10215 /* dword2 - b'1 - post_reset_start_done */ 10216 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M 0x00000002 10217 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S 1 10218 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_GET(word2) \ 10219 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M) >> \ 10220 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S) 10221 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_SET(word2, _val) \ 10222 do { \ 10223 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE, _val); \ 10224 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S));\ 10225 } while (0) 10226 10227 /* dword2 - b'2 - post_reset_complete_done */ 10228 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M 0x00000004 10229 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S 2 10230 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_GET(word2) \ 10231 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M) >> \ 10232 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S) 10233 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_SET(word2, _val) \ 10234 do { \ 10235 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE, _val); \ 10236 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\ 10237 } while (0) 10238 10239 /* dword2 - b'3 - start_pre_reset */ 10240 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M 0x00000008 10241 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S 3 10242 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_GET(word2) \ 10243 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M) >> \ 10244 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S) 10245 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_SET(word2, _val) \ 10246 do { \ 10247 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET, _val); \ 10248 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S));\ 10249 } while (0) 10250 10251 /** 10252 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message 10253 * 10254 * @details 10255 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent 10256 * by the host to provide prerequisite info to target for the UMAC hang 10257 * recovery feature. 10258 * The info sent in this H2T message are T2H message method, H2T message 10259 * method, T2H MSI interrupt number and physical start address, size of 10260 * the shared memory (refers to the shared memory dedicated for messaging 10261 * between host and target when the DUT is in UMAC hang recovery mode). 10262 * This H2T message is expected to be only sent if the WMI service bit 10263 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target. 10264 * 10265 * |31 16|15 12|11 8|7 0| 10266 * |-------------------------------+--------------+--------------+------------| 10267 * | reserved |h2t msg method|t2h msg method| msg_type | 10268 * |--------------------------------------------------------------------------| 10269 * | t2h msi interrupt number | 10270 * |--------------------------------------------------------------------------| 10271 * | shared memory area size | 10272 * |--------------------------------------------------------------------------| 10273 * | shared memory area physical address low | 10274 * |--------------------------------------------------------------------------| 10275 * | shared memory area physical address high | 10276 * |--------------------------------------------------------------------------| 10277 * 10278 * The message is interpreted as follows: 10279 * dword0 - b'0:7 - msg_type 10280 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP) 10281 * b'8:11 - t2h_msg_method: indicates method to be used for 10282 * T2H communication in UMAC hang recovery mode. 10283 * Value zero indicates MSI interrupt (default method). 10284 * Refer to htt_umac_hang_recovery_msg_method enum. 10285 * b'12:15 - h2t_msg_method: indicates method to be used for 10286 * H2T communication in UMAC hang recovery mode. 10287 * Value zero indicates polling by target for this h2t msg 10288 * during UMAC hang recovery mode. 10289 * Refer to htt_umac_hang_recovery_msg_method enum. 10290 * b'16:31 - reserved. 10291 * dword1 - b'0:31 - t2h_msi_data: MSI data to be used for 10292 * T2H communication in UMAC hang recovery mode. 10293 * dword2 - b'0:31 - size: size of shared memory dedicated for messaging 10294 * only when in UMAC hang recovery mode. 10295 * This refers to size in bytes. 10296 * dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address 10297 * of the shared memory dedicated for messaging only when 10298 * in UMAC hang recovery mode. 10299 * dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address 10300 * of the shared memory dedicated for messaging only when 10301 * in UMAC hang recovery mode. 10302 */ 10303 10304 /* t2h_msg_method and h2t_msg_method */ 10305 enum htt_umac_hang_recovery_msg_method { 10306 htt_umac_hang_recovery_msg_t2h_msi_and_h2t_polling = 0, 10307 }; 10308 10309 PREPACK typedef struct { 10310 A_UINT32 msg_type : 8, 10311 t2h_msg_method : 4, 10312 h2t_msg_method : 4, 10313 reserved : 16; 10314 A_UINT32 t2h_msi_data; 10315 /* size bytes and physical address of shared memory. */ 10316 struct htt_h2t_host_paddr_size_entry_t msg_shared_mem; 10317 } POSTPACK htt_h2t_umac_hang_recovery_prerequisite_setup_t; 10318 10319 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES \ 10320 (sizeof(htt_h2t_umac_hang_recovery_prerequisite_setup_t)) 10321 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_DWORDS \ 10322 (HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES >> 2) 10323 10324 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M 0x00000F00 10325 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S 8 10326 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_GET(word0) \ 10327 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M) >> \ 10328 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S) 10329 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_SET(word0, _val) \ 10330 do { \ 10331 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD, _val); \ 10332 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S));\ 10333 } while (0) 10334 10335 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M 0x0000F000 10336 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S 12 10337 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_GET(word0) \ 10338 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M) >> \ 10339 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S) 10340 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_SET(word0, _val) \ 10341 do { \ 10342 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD, _val); \ 10343 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\ 10344 } while (0) 10345 10346 /** 10347 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET message 10348 * 10349 * @details 10350 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level 10351 * HTT message sent by the host to indicate that the target needs to start the 10352 * UMAC hang recovery feature from the point of pre-reset routine. 10353 * The purpose of this H2T message is to have host synchronize and trigger 10354 * UMAC recovery across all targets. 10355 * The info sent in this H2T message is the flag to indicate whether the 10356 * target needs to execute UMAC-recovery in context of the Initiator or 10357 * Non-Initiator. 10358 * This H2T message is expected to be sent as response to the 10359 * initiate_umac_recovery indication from the Initiator target attached to 10360 * this same host. 10361 * This H2T message is expected to be only sent if the WMI service bit 10362 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target 10363 * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent 10364 * beforehand. 10365 * 10366 * |31 10|9|8|7 0| 10367 * |-----------------------------------------------------------| 10368 * | reserved |U|I| msg_type | 10369 * |-----------------------------------------------------------| 10370 * Where: 10371 * I = is_initiator 10372 * U = is_umac_hang 10373 * 10374 * The message is interpreted as follows: 10375 * dword0 - b'0:7 - msg_type 10376 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET) 10377 * b'8 - is_initiator: indicates whether the target needs to 10378 * execute the UMAC-recovery in context of the Initiator or 10379 * Non-Initiator. 10380 * The value zero indicates this target is Non-Initiator. 10381 * b'9 - is_umac_hang: indicates whether MLO UMAC recovery 10382 * executed in context of UMAC hang or Target recovery. 10383 * b'10:31 - reserved. 10384 */ 10385 10386 PREPACK typedef struct { 10387 A_UINT32 msg_type : 8, 10388 is_initiator : 1, 10389 is_umac_hang : 1, 10390 reserved : 22; 10391 } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; 10392 10393 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ 10394 (sizeof(htt_h2t_umac_hang_recovery_start_pre_reset_t)) 10395 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_DWORDS \ 10396 (HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES >> 2) 10397 10398 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M 0x00000100 10399 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S 8 10400 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_GET(word0) \ 10401 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M) >> \ 10402 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S) 10403 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_SET(word0, _val) \ 10404 do { \ 10405 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR, _val); \ 10406 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ 10407 } while (0) 10408 10409 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 10410 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 10411 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ 10412 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ 10413 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) 10414 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ 10415 do { \ 10416 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ 10417 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ 10418 } while (0) 10419 10420 10421 /* 10422 * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message 10423 * 10424 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP 10425 * 10426 * @details 10427 * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request, 10428 * install or uninstall rx cce super rules to match certain kind of packets 10429 * with specific parameters. Target sets up HW registers based on setup message 10430 * and always confirms back to Host. 10431 * 10432 * The message would appear as follows: 10433 * |31 24|23 16|15 8|7 0| 10434 * |-----------------+-----------------+-----------------+-----------------| 10435 * | reserved | operation | pdev_id | msg_type | 10436 * |-----------------------------------------------------------------------| 10437 * | cce_super_rule_param[0] | 10438 * |-----------------------------------------------------------------------| 10439 * | cce_super_rule_param[1] | 10440 * |-----------------------------------------------------------------------| 10441 * 10442 * The message is interpreted as follows: 10443 * dword0 - b'0:7 - msg_type: This will be set to 10444 * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) 10445 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for 10446 * b'16:23 - operation: Identify operation to be taken, 10447 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 10448 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL 10449 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE 10450 * b'24:31 - reserved 10451 * dword1~10 - cce_super_rule_param[0]: 10452 * contains parameters used to setup RX_CCE_SUPER_RULE_0 10453 * dword11~20 - cce_super_rule_param[1]: 10454 * contains parameters used to setup RX_CCE_SUPER_RULE_1 10455 * 10456 * Each cce_super_rule_param structure would appear as follows: 10457 * |31 24|23 16|15 8|7 0| 10458 * |-----------------+-----------------+-----------------+-----------------| 10459 * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | 10460 * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| 10461 * |-----------------------------------------------------------------------| 10462 * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | 10463 * |-----------------------------------------------------------------------| 10464 * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | 10465 * |-----------------------------------------------------------------------| 10466 * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| 10467 * |-----------------------------------------------------------------------| 10468 * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | 10469 * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| 10470 * |-----------------------------------------------------------------------| 10471 * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | 10472 * |-----------------------------------------------------------------------| 10473 * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | 10474 * |-----------------------------------------------------------------------| 10475 * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| 10476 * |-----------------------------------------------------------------------| 10477 * | is_valid | l4_type | l3_type | 10478 * |-----------------------------------------------------------------------| 10479 * | l4_dst_port | l4_src_port | 10480 * |-----------------------------------------------------------------------| 10481 * 10482 * The cce_super_rule_param[0] structure is interpreted as follows: 10483 * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address 10484 * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address, 10485 * in case of ipv4) 10486 * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address 10487 * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address, 10488 * in case of ipv4) 10489 * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address 10490 * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address, 10491 * in case of ipv4) 10492 * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address 10493 * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address, 10494 * in case of ipv4) 10495 * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address 10496 * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address 10497 * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address 10498 * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address 10499 * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address 10500 * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address 10501 * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address 10502 * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address 10503 * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address 10504 * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address 10505 * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address 10506 * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address 10507 * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address 10508 * (or dst_ipv4_addr[0]: b'24:31 of destination 10509 * ipv4 address, in case of ipv4) 10510 * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address 10511 * (or dst_ipv4_addr[1]: b'16:23 of destination 10512 * ipv4 address, in case of ipv4) 10513 * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address 10514 * (or dst_ipv4_addr[2]: b'8:15 of destination 10515 * ipv4 address, in case of ipv4) 10516 * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address 10517 * (or dst_ipv4_addr[3]: b'0:7 of destination 10518 * ipv4 address, in case of ipv4) 10519 * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address 10520 * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address 10521 * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address 10522 * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address 10523 * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address 10524 * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address 10525 * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address 10526 * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address 10527 * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address 10528 * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address 10529 * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address 10530 * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address 10531 * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used 10532 * 0x0008: ipv4 10533 * 0xdd86: ipv6 10534 * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used 10535 * 6: TCP 10536 * 17: UDP 10537 * b'24:31 - is_valid: indicate whether this parameter is valid 10538 * 0: invalid 10539 * 1: valid 10540 * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field 10541 * b'16:31 - l4_dst_port: TCP/UDP destination port field 10542 * 10543 * The cce_super_rule_param[1] structure is similar. 10544 */ 10545 #define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2 10546 10547 enum htt_rx_cce_super_rule_setup_operation { 10548 HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0, 10549 HTT_RX_CCE_SUPER_RULE_INSTALL, 10550 HTT_RX_CCE_SUPER_RULE_RELEASE, 10551 10552 /* All operation should be before this */ 10553 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION, 10554 }; 10555 10556 typedef struct { 10557 union { 10558 A_UINT8 src_ipv4_addr[4]; 10559 A_UINT8 src_ipv6_addr[16]; 10560 }; 10561 union { 10562 A_UINT8 dst_ipv4_addr[4]; 10563 A_UINT8 dst_ipv6_addr[16]; 10564 }; 10565 A_UINT32 l3_type: 16, 10566 l4_type: 8, 10567 is_valid: 8; 10568 A_UINT32 l4_src_port: 16, 10569 l4_dst_port: 16; 10570 } htt_rx_cce_super_rule_param_t; 10571 10572 PREPACK struct htt_rx_cce_super_rule_setup_t { 10573 A_UINT32 msg_type: 8, 10574 pdev_id: 8, 10575 operation: 8, 10576 reserved: 8; 10577 htt_rx_cce_super_rule_param_t 10578 cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM]; 10579 } POSTPACK; 10580 10581 #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ 10582 (sizeof(struct htt_rx_cce_super_rule_setup_t)) 10583 10584 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 10585 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 10586 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ 10587 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ 10588 HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) 10589 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ 10590 do { \ 10591 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ 10592 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ 10593 } while (0) 10594 10595 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 10596 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16 10597 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ 10598 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \ 10599 HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S) 10600 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ 10601 do { \ 10602 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \ 10603 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \ 10604 } while (0) 10605 10606 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff 10607 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0 10608 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ 10609 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ 10610 HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S) 10611 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ 10612 do { \ 10613 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ 10614 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ 10615 } while (0) 10616 10617 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 10618 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16 10619 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ 10620 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ 10621 HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S) 10622 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ 10623 do { \ 10624 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ 10625 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ 10626 } while (0) 10627 10628 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 10629 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24 10630 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ 10631 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ 10632 HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S) 10633 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ 10634 do { \ 10635 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \ 10636 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \ 10637 } while (0) 10638 10639 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff 10640 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 10641 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ 10642 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ 10643 HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) 10644 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ 10645 do { \ 10646 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ 10647 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ 10648 } while (0) 10649 10650 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 10651 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 10652 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ 10653 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ 10654 HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S) 10655 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ 10656 do { \ 10657 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ 10658 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ 10659 } while (0) 10660 10661 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ 10662 do { \ 10663 A_MEMCPY(_array, _ptr, 4); \ 10664 } while (0) 10665 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ 10666 do { \ 10667 A_MEMCPY(_ptr, _array, 4); \ 10668 } while (0) 10669 10670 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ 10671 do { \ 10672 A_MEMCPY(_array, _ptr, 16); \ 10673 } while (0) 10674 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ 10675 do { \ 10676 A_MEMCPY(_ptr, _array, 16); \ 10677 } while (0) 10678 10679 10680 /** 10681 * htt_h2t_primary_link_peer_status_type - 10682 * Unique number for each status or reasons 10683 * The status reasons can go up to 255 max 10684 */ 10685 enum htt_h2t_primary_link_peer_status_type { 10686 /* Host Primary Link Peer migration Success */ 10687 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, 10688 10689 10690 /* keep this last */ 10691 /* Host Primary Link Peer migration Fail */ 10692 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, 10693 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 10694 }; 10695 10696 10697 /** 10698 * @brief host -> Primary peer migration completion message from host 10699 * 10700 * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP 10701 * 10702 * @details 10703 * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to 10704 * target Confirming that primary link peer migration has completed, 10705 * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 10706 * message from the target. 10707 * 10708 * The message would appear as follows: 10709 * 10710 * |31 25|24|23 16|15 12|11 8|7 0| 10711 * |----------------------------+----------+---------+--------------| 10712 * | vdev ID | pdev ID | chip ID | msg type | 10713 * |----------------------------+----------+---------+--------------| 10714 * | ML peer ID | SW peer ID | 10715 * |------------+--+------------+--------------------+--------------| 10716 * | reserved |SV| src_info | status | 10717 * |------------+--+---------------------------------+--------------| 10718 * Where: 10719 * SV = src_info_valid flag 10720 * 10721 * The message is interpreted as follows: 10722 * dword0 - b'0:7 - msg_type: This will be set to 0x24 10723 * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) 10724 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 10725 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 10726 * as primary 10727 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 10728 * as primary 10729 * 10730 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 10731 * chosen as primary 10732 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 10733 * primary peer belongs. 10734 * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration 10735 * b'8:23 - src_info: Indicates New Virtual port number through 10736 * which Rx Pipe connects to the correct PPE. 10737 * b'24 - src_info_valid: Indicates src_info is valid. 10738 */ 10739 10740 typedef struct { 10741 A_UINT32 msg_type: 8, /* bits 7:0 */ 10742 chip_id: 4, /* bits 11:8 */ 10743 pdev_id: 4, /* bits 15:12 */ 10744 vdev_id: 16; /* bits 31:16 */ 10745 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 10746 ml_peer_id: 16; /* bits 31:16 */ 10747 A_UINT32 status: 8, /* bits 7:0 */ 10748 src_info: 16, /* bits 23:8 */ 10749 src_info_valid: 1, /* bit 24 */ 10750 reserved: 7; /* bits 31:25 */ 10751 } htt_h2t_primary_link_peer_migrate_resp_t; 10752 10753 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 10754 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 10755 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 10756 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 10757 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 10758 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 10759 do { \ 10760 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 10761 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 10762 } while (0) 10763 10764 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 10765 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 10766 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 10767 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 10768 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 10769 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 10770 do { \ 10771 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 10772 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 10773 } while (0) 10774 10775 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 10776 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 10777 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 10778 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 10779 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 10780 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 10781 do { \ 10782 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 10783 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 10784 } while (0) 10785 10786 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 10787 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 10788 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 10789 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 10790 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 10791 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 10792 do { \ 10793 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 10794 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 10795 } while (0) 10796 10797 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 10798 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 10799 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 10800 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 10801 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 10802 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 10803 do { \ 10804 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 10805 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 10806 } while (0) 10807 10808 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF 10809 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 10810 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ 10811 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ 10812 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) 10813 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ 10814 do { \ 10815 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ 10816 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ 10817 } while (0) 10818 10819 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 10820 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 10821 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ 10822 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ 10823 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) 10824 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ 10825 do { \ 10826 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ 10827 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ 10828 } while (0) 10829 10830 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 10831 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 10832 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ 10833 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ 10834 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) 10835 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ 10836 do { \ 10837 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ 10838 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ 10839 } while (0) 10840 10841 10842 /** 10843 * @brief host -> tgt msg to configure params for PPDU tx latency stats report 10844 * 10845 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG 10846 * 10847 * @details 10848 * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to 10849 * configure the parameters needed for FW to report PPDU tx latency stats 10850 * for latency prediction in user space. 10851 * 10852 * The message would appear as follows: 10853 * |31 28|27 12|11|10 8|7 0| 10854 * |-----------+-------------------+--+-------+--------------| 10855 * |granularity| periodic interval | E|vdev ID| msg type | 10856 * |-----------+-------------------+--+-------+--------------| 10857 * Where: E = enable 10858 * 10859 * The message is interpreted as follows: 10860 * dword0 - b'0:7 - msg_type: This will be set to 0x25 10861 * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG) 10862 * b'8:10 - vdev_id: Indicate which vdev is configuration is for 10863 * b'11 - enable: Indicate this message is to enable/disable 10864 * PPDU latency report from FW 10865 * b'12:27 - periodic_interval: Indicate the report interval in MS 10866 * b'28:31 - granularity: Indicate the granularity of the latency 10867 * stats report, in ms 10868 */ 10869 10870 /* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */ 10871 PREPACK struct htt_h2t_tx_latency_stats_cfg { 10872 A_UINT32 msg_type :8, 10873 vdev_id :3, 10874 enable :1, 10875 periodic_interval :16, 10876 granularity :4; 10877 } POSTPACK; 10878 10879 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700 10880 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8 10881 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \ 10882 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \ 10883 HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S) 10884 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \ 10885 do { \ 10886 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \ 10887 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \ 10888 } while (0) 10889 10890 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800 10891 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11 10892 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \ 10893 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \ 10894 HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S) 10895 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \ 10896 do { \ 10897 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \ 10898 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \ 10899 } while (0) 10900 10901 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000 10902 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12 10903 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \ 10904 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \ 10905 HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S) 10906 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \ 10907 do { \ 10908 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \ 10909 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \ 10910 } while (0) 10911 10912 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000 10913 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28 10914 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \ 10915 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \ 10916 HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S) 10917 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \ 10918 do { \ 10919 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \ 10920 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \ 10921 } while (0) 10922 10923 10924 10925 /*=== target -> host messages ===============================================*/ 10926 10927 10928 enum htt_t2h_msg_type { 10929 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 10930 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 10931 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 10932 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 10933 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 10934 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 10935 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 10936 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 10937 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 10938 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 10939 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 10940 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 10941 DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* no longer used */ 10942 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 10943 HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 10944 /* only used for HL, add HTT MSG for HTT CREDIT update */ 10945 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 10946 HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, 10947 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 10948 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 10949 /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ 10950 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 10951 HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 10952 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 10953 HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, 10954 HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, 10955 HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, 10956 HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a, 10957 HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b, 10958 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 10959 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 10960 HTT_T2H_MSG_TYPE_PEER_MAP_V2 = 0x1e, 10961 HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f, 10962 HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20, 10963 HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21, 10964 HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22, 10965 HTT_T2H_MSG_TYPE_PEER_STATS_IND = 0x23, 10966 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 10967 /* TX_OFFLOAD_DELIVER_IND: 10968 * Forward the target's locally-generated packets to the host, 10969 * to provide to the monitor mode interface. 10970 */ 10971 HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25, 10972 HTT_T2H_MSG_TYPE_CHAN_CALDATA = 0x26, 10973 HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND = 0x27, 10974 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 10975 HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29, 10976 HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP = 0x2a, 10977 HTT_T2H_MSG_TYPE_PEER_MAP_V3 = 0x2b, 10978 HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND = 0x2c, 10979 HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, 10980 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, /* alias */ 10981 HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e, 10982 HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */ 10983 HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f, 10984 HTT_T2H_PPDU_ID_FMT_IND = 0x30, 10985 HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, 10986 HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, 10987 HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, 10988 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */ 10989 HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, 10990 HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, 10991 HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, 10992 HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, 10993 HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, 10994 HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a, 10995 10996 10997 HTT_T2H_MSG_TYPE_TEST, 10998 /* keep this last */ 10999 HTT_T2H_NUM_MSGS 11000 }; 11001 11002 /* 11003 * HTT target to host message type - 11004 * stored in bits 7:0 of the first word of the message 11005 */ 11006 #define HTT_T2H_MSG_TYPE_M 0xff 11007 #define HTT_T2H_MSG_TYPE_S 0 11008 11009 #define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ 11010 do { \ 11011 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ 11012 (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ 11013 } while (0) 11014 #define HTT_T2H_MSG_TYPE_GET(word) \ 11015 (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) 11016 11017 /** 11018 * @brief target -> host version number confirmation message definition 11019 * 11020 * MSG_TYPE => HTT_T2H_MSG_TYPE_VERSION_CONF 11021 * 11022 * |31 24|23 16|15 8|7 0| 11023 * |----------------+----------------+----------------+----------------| 11024 * | reserved | major number | minor number | msg type | 11025 * |-------------------------------------------------------------------| 11026 * : option request TLV (optional) | 11027 * :...................................................................: 11028 * 11029 * The VER_CONF message may consist of a single 4-byte word, or may be 11030 * extended with TLVs that specify HTT options selected by the target. 11031 * The following option TLVs may be appended to the VER_CONF message: 11032 * - LL_BUS_ADDR_SIZE 11033 * - HL_SUPPRESS_TX_COMPL_IND 11034 * - MAX_TX_QUEUE_GROUPS 11035 * These TLVs may appear in an arbitrary order. Any number of these TLVs 11036 * may be appended to the VER_CONF message (but only one TLV of each type). 11037 * 11038 * Header fields: 11039 * - MSG_TYPE 11040 * Bits 7:0 11041 * Purpose: identifies this as a version number confirmation message 11042 * Value: 0x0 (HTT_T2H_MSG_TYPE_VERSION_CONF) 11043 * - VER_MINOR 11044 * Bits 15:8 11045 * Purpose: Specify the minor number of the HTT message library version 11046 * in use by the target firmware. 11047 * The minor number specifies the specific revision within a range 11048 * of fundamentally compatible HTT message definition revisions. 11049 * Compatible revisions involve adding new messages or perhaps 11050 * adding new fields to existing messages, in a backwards-compatible 11051 * manner. 11052 * Incompatible revisions involve changing the message type values, 11053 * or redefining existing messages. 11054 * Value: minor number 11055 * - VER_MAJOR 11056 * Bits 15:8 11057 * Purpose: Specify the major number of the HTT message library version 11058 * in use by the target firmware. 11059 * The major number specifies the family of minor revisions that are 11060 * fundamentally compatible with each other, but not with prior or 11061 * later families. 11062 * Value: major number 11063 */ 11064 11065 #define HTT_VER_CONF_MINOR_M 0x0000ff00 11066 #define HTT_VER_CONF_MINOR_S 8 11067 #define HTT_VER_CONF_MAJOR_M 0x00ff0000 11068 #define HTT_VER_CONF_MAJOR_S 16 11069 11070 11071 #define HTT_VER_CONF_MINOR_SET(word, value) \ 11072 do { \ 11073 HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ 11074 (word) |= (value) << HTT_VER_CONF_MINOR_S; \ 11075 } while (0) 11076 #define HTT_VER_CONF_MINOR_GET(word) \ 11077 (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) 11078 11079 #define HTT_VER_CONF_MAJOR_SET(word, value) \ 11080 do { \ 11081 HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ 11082 (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ 11083 } while (0) 11084 #define HTT_VER_CONF_MAJOR_GET(word) \ 11085 (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) 11086 11087 11088 #define HTT_VER_CONF_BYTES 4 11089 11090 11091 /** 11092 * @brief - target -> host HTT Rx In order indication message 11093 * 11094 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND 11095 * 11096 * @details 11097 * 11098 * |31 24|23 |15|14|13|12|11|10|9|8|7|6|5|4 0| 11099 * |----------------+-------------------+---------------------+---------------| 11100 * | peer ID | P| F| O| ext TID | msg type | 11101 * |--------------------------------------------------------------------------| 11102 * | MSDU count | Reserved | vdev id | 11103 * |--------------------------------------------------------------------------| 11104 * | MSDU 0 bus address (bits 31:0) | 11105 #if HTT_PADDR64 11106 * | MSDU 0 bus address (bits 63:32) | 11107 #endif 11108 * |--------------------------------------------------------------------------| 11109 * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length | 11110 * |--------------------------------------------------------------------------| 11111 * | MSDU 1 bus address (bits 31:0) | 11112 #if HTT_PADDR64 11113 * | MSDU 1 bus address (bits 63:32) | 11114 #endif 11115 * |--------------------------------------------------------------------------| 11116 * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length | 11117 * |--------------------------------------------------------------------------| 11118 */ 11119 11120 11121 /** @brief - MSDU info byte for TCP_CHECKSUM_OFFLOAD use 11122 * 11123 * @details 11124 * bits 11125 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 11126 * |-----+----+-------+--------+--------+---------+---------+-----------| 11127 * | reserved | is IP | is UDP | is TCP | is IPv6 |IP chksum| TCP/UDP | 11128 * | | frag | | | | fail |chksum fail| 11129 * |-----+----+-------+--------+--------+---------+---------+-----------| 11130 * (see fw_rx_msdu_info def in wal_rx_desc.h) 11131 */ 11132 11133 struct htt_rx_in_ord_paddr_ind_hdr_t 11134 { 11135 A_UINT32 /* word 0 */ 11136 msg_type: 8, 11137 ext_tid: 5, 11138 offload: 1, 11139 frag: 1, 11140 pktlog: 1, /* tell host whether to store MSDUs referenced in this message in pktlog */ 11141 peer_id: 16; 11142 11143 A_UINT32 /* word 1 */ 11144 vap_id: 8, 11145 /* NOTE: 11146 * This reserved_1 field is not truly reserved - certain targets use 11147 * this field internally to store debug information, and do not zero 11148 * out the contents of the field before uploading the message to the 11149 * host. Thus, any host-target communication supported by this field 11150 * is limited to using values that are never used by the debug 11151 * information stored by certain targets in the reserved_1 field. 11152 * In particular, the targets in question don't use the value 0x3 11153 * within bits 7:6 of this field (i.e. bits 15:14 of the A_UINT32), 11154 * so this previously-unused value within these bits is available to 11155 * use as the host / target PKT_CAPTURE_MODE flag. 11156 */ 11157 reserved_1: 8, /* reserved_1a: 6, pkt_capture_mode: 2, */ 11158 /* if pkt_capture_mode == 0x3, host should 11159 * send rx frames to monitor mode interface 11160 */ 11161 msdu_cnt: 16; 11162 }; 11163 11164 struct htt_rx_in_ord_paddr_ind_msdu32_t 11165 { 11166 A_UINT32 dma_addr; 11167 A_UINT32 11168 length: 16, 11169 fw_desc: 8, 11170 msdu_info:8; 11171 }; 11172 struct htt_rx_in_ord_paddr_ind_msdu64_t 11173 { 11174 A_UINT32 dma_addr_lo; 11175 A_UINT32 dma_addr_hi; 11176 A_UINT32 11177 length: 16, 11178 fw_desc: 8, 11179 msdu_info:8; 11180 }; 11181 #if HTT_PADDR64 11182 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t 11183 #else 11184 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t 11185 #endif 11186 11187 11188 #define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) 11189 #define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) 11190 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES 11191 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS 11192 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) 11193 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) 11194 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) 11195 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) 11196 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) 11197 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) 11198 11199 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00 11200 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8 11201 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M 0x00002000 11202 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S 13 11203 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_M 0x00004000 11204 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_S 14 11205 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M 0x00008000 11206 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S 15 11207 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M 0xffff0000 11208 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16 11209 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff 11210 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0 11211 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M 0x0000c000 11212 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S 14 11213 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000 11214 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16 11215 /* for systems using 64-bit format for bus addresses */ 11216 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M 0xffffffff 11217 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S 0 11218 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M 0xffffffff 11219 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S 0 11220 /* for systems using 32-bit format for bus addresses */ 11221 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_M 0xffffffff 11222 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_S 0 11223 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M 0x0000ffff 11224 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S 0 11225 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M 0x00ff0000 11226 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S 16 11227 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M 0xff000000 11228 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24 11229 11230 11231 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ 11232 do { \ 11233 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ 11234 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ 11235 } while (0) 11236 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ 11237 (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) 11238 11239 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ 11240 do { \ 11241 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ 11242 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ 11243 } while (0) 11244 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ 11245 (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) 11246 11247 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ 11248 do { \ 11249 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ 11250 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ 11251 } while (0) 11252 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ 11253 (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) 11254 11255 /* 11256 * If the PKT_CAPTURE_MODE flags value is MONITOR (0x3), the host should 11257 * deliver the rx frames to the monitor mode interface. 11258 * The HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET macro 11259 * sets the PKT_CAPTURE_MODE flags value to MONITOR, and the 11260 * HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET macro 11261 * checks whether the PKT_CAPTURE_MODE flags value is MONITOR. 11262 */ 11263 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR 0x3 11264 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET(word) \ 11265 do { \ 11266 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE, HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR); \ 11267 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S; \ 11268 } while (0) 11269 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET(word) \ 11270 ((((word) & HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M) >> HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S) == \ 11271 HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR) 11272 11273 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ 11274 do { \ 11275 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ 11276 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ 11277 } while (0) 11278 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ 11279 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) 11280 11281 /* for systems using 64-bit format for bus addresses */ 11282 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ 11283 do { \ 11284 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ 11285 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ 11286 } while (0) 11287 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ 11288 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) 11289 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ 11290 do { \ 11291 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ 11292 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ 11293 } while (0) 11294 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ 11295 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) 11296 11297 /* for systems using 32-bit format for bus addresses */ 11298 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ 11299 do { \ 11300 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ 11301 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ 11302 } while (0) 11303 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ 11304 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_S) 11305 11306 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ 11307 do { \ 11308 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value); \ 11309 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ 11310 } while (0) 11311 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \ 11312 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) 11313 11314 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ 11315 do { \ 11316 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ 11317 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ 11318 } while (0) 11319 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ 11320 (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) 11321 11322 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ 11323 do { \ 11324 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value); \ 11325 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S; \ 11326 } while (0) 11327 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \ 11328 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) 11329 11330 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ 11331 do { \ 11332 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value); \ 11333 (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ 11334 } while (0) 11335 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ 11336 (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) 11337 11338 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ 11339 do { \ 11340 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ 11341 (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ 11342 } while (0) 11343 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ 11344 (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> HTT_RX_IN_ORD_PADDR_IND_FRAG_S) 11345 11346 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_SET(word, value) \ 11347 do { \ 11348 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \ 11349 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \ 11350 } while (0) 11351 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \ 11352 (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S) 11353 11354 11355 /* definitions used within target -> host rx indication message */ 11356 11357 PREPACK struct htt_rx_ind_hdr_prefix_t 11358 { 11359 A_UINT32 /* word 0 */ 11360 msg_type: 8, 11361 ext_tid: 5, 11362 release_valid: 1, 11363 flush_valid: 1, 11364 reserved0: 1, 11365 peer_id: 16; 11366 11367 A_UINT32 /* word 1 */ 11368 flush_start_seq_num: 6, 11369 flush_end_seq_num: 6, 11370 release_start_seq_num: 6, 11371 release_end_seq_num: 6, 11372 num_mpdu_ranges: 8; 11373 } POSTPACK; 11374 11375 #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t)) 11376 #define HTT_RX_IND_HDR_PREFIX_SIZE32 (HTT_RX_IND_HDR_PREFIX_BYTES >> 2) 11377 11378 #define HTT_TGT_RSSI_INVALID 0x80 11379 11380 PREPACK struct htt_rx_ppdu_desc_t 11381 { 11382 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 11383 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 11384 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 11385 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 11386 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 11387 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 11388 #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 11389 #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 11390 A_UINT32 /* word 0 */ 11391 rssi_cmb: 8, 11392 timestamp_submicrosec: 8, 11393 phy_err_code: 8, 11394 phy_err: 1, 11395 legacy_rate: 4, 11396 legacy_rate_sel: 1, 11397 end_valid: 1, 11398 start_valid: 1; 11399 11400 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 11401 union { 11402 A_UINT32 /* word 1 */ 11403 rssi0_pri20: 8, 11404 rssi0_ext20: 8, 11405 rssi0_ext40: 8, 11406 rssi0_ext80: 8; 11407 A_UINT32 rssi0; /* access all 20/40/80 per-bandwidth RSSIs together */ 11408 } u0; 11409 11410 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 11411 union { 11412 A_UINT32 /* word 2 */ 11413 rssi1_pri20: 8, 11414 rssi1_ext20: 8, 11415 rssi1_ext40: 8, 11416 rssi1_ext80: 8; 11417 A_UINT32 rssi1; /* access all 20/40/80 per-bandwidth RSSIs together */ 11418 } u1; 11419 11420 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 11421 union { 11422 A_UINT32 /* word 3 */ 11423 rssi2_pri20: 8, 11424 rssi2_ext20: 8, 11425 rssi2_ext40: 8, 11426 rssi2_ext80: 8; 11427 A_UINT32 rssi2; /* access all 20/40/80 per-bandwidth RSSIs together */ 11428 } u2; 11429 11430 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 11431 union { 11432 A_UINT32 /* word 4 */ 11433 rssi3_pri20: 8, 11434 rssi3_ext20: 8, 11435 rssi3_ext40: 8, 11436 rssi3_ext80: 8; 11437 A_UINT32 rssi3; /* access all 20/40/80 per-bandwidth RSSIs together */ 11438 } u3; 11439 11440 #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 11441 A_UINT32 tsf32; /* word 5 */ 11442 11443 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 11444 A_UINT32 timestamp_microsec; /* word 6 */ 11445 11446 #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 11447 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 11448 A_UINT32 /* word 7 */ 11449 vht_sig_a1: 24, 11450 preamble_type: 8; 11451 11452 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 11453 #define HTT_RX_IND_PPDU_OFFSET_WORD_SA_ANT_MATRIX 8 11454 A_UINT32 /* word 8 */ 11455 vht_sig_a2: 24, 11456 /* sa_ant_matrix 11457 * For cases where a single rx chain has options to be connected to 11458 * different rx antennas, show which rx antennas were in use during 11459 * receipt of a given PPDU. 11460 * This sa_ant_matrix provides a bitmask of the antennas used while 11461 * receiving this frame. 11462 */ 11463 sa_ant_matrix: 8; 11464 } POSTPACK; 11465 11466 #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t)) 11467 #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2) 11468 11469 PREPACK struct htt_rx_ind_hdr_suffix_t 11470 { 11471 A_UINT32 /* word 0 */ 11472 fw_rx_desc_bytes: 16, 11473 reserved0: 16; 11474 } POSTPACK; 11475 11476 #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t)) 11477 #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2) 11478 11479 PREPACK struct htt_rx_ind_hdr_t 11480 { 11481 struct htt_rx_ind_hdr_prefix_t prefix; 11482 struct htt_rx_ppdu_desc_t rx_ppdu_desc; 11483 struct htt_rx_ind_hdr_suffix_t suffix; 11484 } POSTPACK; 11485 11486 #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t)) 11487 #define HTT_RX_IND_HDR_SIZE32 (HTT_RX_IND_HDR_BYTES >> 2) 11488 11489 /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */ 11490 A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, 11491 (HTT_RX_IND_HDR_BYTES & 0x3) == 0); 11492 11493 /* 11494 * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET: 11495 * the offset into the HTT rx indication message at which the 11496 * FW rx PPDU descriptor resides 11497 */ 11498 #define HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET HTT_RX_IND_HDR_PREFIX_BYTES 11499 11500 /* 11501 * HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET: 11502 * the offset into the HTT rx indication message at which the 11503 * header suffix (FW rx MSDU byte count) resides 11504 */ 11505 #define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ 11506 (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) 11507 11508 /* 11509 * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET: 11510 * the offset into the HTT rx indication message at which the per-MSDU 11511 * information starts 11512 * Bytes 0-7 are the message header; bytes 8-11 contain the length of the 11513 * per-MSDU information portion of the message. The per-MSDU info itself 11514 * starts at byte 12. 11515 */ 11516 #define HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET HTT_RX_IND_HDR_BYTES 11517 11518 11519 /** 11520 * @brief target -> host rx indication message definition 11521 * 11522 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IND 11523 * 11524 * @details 11525 * The following field definitions describe the format of the rx indication 11526 * message sent from the target to the host. 11527 * The message consists of three major sections: 11528 * 1. a fixed-length header 11529 * 2. a variable-length list of firmware rx MSDU descriptors 11530 * 3. one or more 4-octet MPDU range information elements 11531 * The fixed length header itself has two sub-sections 11532 * 1. the message meta-information, including identification of the 11533 * sender and type of the received data, and a 4-octet flush/release IE 11534 * 2. the firmware rx PPDU descriptor 11535 * 11536 * The format of the message is depicted below. 11537 * in this depiction, the following abbreviations are used for information 11538 * elements within the message: 11539 * - SV - start valid: this flag is set if the FW rx PPDU descriptor 11540 * elements associated with the PPDU start are valid. 11541 * Specifically, the following fields are valid only if SV is set: 11542 * RSSI (all variants), L, legacy rate, preamble type, service, 11543 * VHT-SIG-A 11544 * - EV - end valid: this flag is set if the FW rx PPDU descriptor 11545 * elements associated with the PPDU end are valid. 11546 * Specifically, the following fields are valid only if EV is set: 11547 * P, PHY err code, TSF, microsec / sub-microsec timestamp 11548 * - L - Legacy rate selector - if legacy rates are used, this flag 11549 * indicates whether the rate is from a CCK (L == 1) or OFDM 11550 * (L == 0) PHY. 11551 * - P - PHY error flag - boolean indication of whether the rx frame had 11552 * a PHY error 11553 * 11554 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 11555 * |----------------+-------------------+---------------------+---------------| 11556 * | peer ID | |RV|FV| ext TID | msg type | 11557 * |--------------------------------------------------------------------------| 11558 * | num | release | release | flush | flush | 11559 * | MPDU | end | start | end | start | 11560 * | ranges | seq num | seq num | seq num | seq num | 11561 * |==========================================================================| 11562 * |S|E|L| legacy |P| PHY err code | sub-microsec | combined | 11563 * |V|V| | rate | | | timestamp | RSSI | 11564 * |--------------------------------------------------------------------------| 11565 * | RSSI rx0 ext80 | RSSI rx0 ext40 | RSSI rx0 ext20 | RSSI rx0 pri20| 11566 * |--------------------------------------------------------------------------| 11567 * | RSSI rx1 ext80 | RSSI rx1 ext40 | RSSI rx1 ext20 | RSSI rx1 pri20| 11568 * |--------------------------------------------------------------------------| 11569 * | RSSI rx2 ext80 | RSSI rx2 ext40 | RSSI rx2 ext20 | RSSI rx2 pri20| 11570 * |--------------------------------------------------------------------------| 11571 * | RSSI rx3 ext80 | RSSI rx3 ext40 | RSSI rx3 ext20 | RSSI rx3 pri20| 11572 * |--------------------------------------------------------------------------| 11573 * | TSF LSBs | 11574 * |--------------------------------------------------------------------------| 11575 * | microsec timestamp | 11576 * |--------------------------------------------------------------------------| 11577 * | preamble type | HT-SIG / VHT-SIG-A1 | 11578 * |--------------------------------------------------------------------------| 11579 * | service | HT-SIG / VHT-SIG-A2 | 11580 * |==========================================================================| 11581 * | reserved | FW rx desc bytes | 11582 * |--------------------------------------------------------------------------| 11583 * | MSDU Rx | MSDU Rx | MSDU Rx | MSDU Rx | 11584 * | desc B3 | desc B2 | desc B1 | desc B0 | 11585 * |--------------------------------------------------------------------------| 11586 * : : : 11587 * |--------------------------------------------------------------------------| 11588 * | alignment | MSDU Rx | 11589 * | padding | desc Bn | 11590 * |--------------------------------------------------------------------------| 11591 * | reserved | MPDU range status | MPDU count | 11592 * |--------------------------------------------------------------------------| 11593 * : reserved : MPDU range status : MPDU count : 11594 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : 11595 * 11596 * Header fields: 11597 * - MSG_TYPE 11598 * Bits 7:0 11599 * Purpose: identifies this as an rx indication message 11600 * Value: 0x1 (HTT_T2H_MSG_TYPE_RX_IND) 11601 * - EXT_TID 11602 * Bits 12:8 11603 * Purpose: identify the traffic ID of the rx data, including 11604 * special "extended" TID values for multicast, broadcast, and 11605 * non-QoS data frames 11606 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 11607 * - FLUSH_VALID (FV) 11608 * Bit 13 11609 * Purpose: indicate whether the flush IE (start/end sequence numbers) 11610 * is valid 11611 * Value: 11612 * 1 -> flush IE is valid and needs to be processed 11613 * 0 -> flush IE is not valid and should be ignored 11614 * - REL_VALID (RV) 11615 * Bit 13 11616 * Purpose: indicate whether the release IE (start/end sequence numbers) 11617 * is valid 11618 * Value: 11619 * 1 -> release IE is valid and needs to be processed 11620 * 0 -> release IE is not valid and should be ignored 11621 * - PEER_ID 11622 * Bits 31:16 11623 * Purpose: Identify, by ID, which peer sent the rx data 11624 * Value: ID of the peer who sent the rx data 11625 * - FLUSH_SEQ_NUM_START 11626 * Bits 5:0 11627 * Purpose: Indicate the start of a series of MPDUs to flush 11628 * Not all MPDUs within this series are necessarily valid - the host 11629 * must check each sequence number within this range to see if the 11630 * corresponding MPDU is actually present. 11631 * This field is only valid if the FV bit is set. 11632 * Value: 11633 * The sequence number for the first MPDUs to check to flush. 11634 * The sequence number is masked by 0x3f. 11635 * - FLUSH_SEQ_NUM_END 11636 * Bits 11:6 11637 * Purpose: Indicate the end of a series of MPDUs to flush 11638 * Value: 11639 * The sequence number one larger than the sequence number of the 11640 * last MPDU to check to flush. 11641 * The sequence number is masked by 0x3f. 11642 * Not all MPDUs within this series are necessarily valid - the host 11643 * must check each sequence number within this range to see if the 11644 * corresponding MPDU is actually present. 11645 * This field is only valid if the FV bit is set. 11646 * - REL_SEQ_NUM_START 11647 * Bits 17:12 11648 * Purpose: Indicate the start of a series of MPDUs to release. 11649 * All MPDUs within this series are present and valid - the host 11650 * need not check each sequence number within this range to see if 11651 * the corresponding MPDU is actually present. 11652 * This field is only valid if the RV bit is set. 11653 * Value: 11654 * The sequence number for the first MPDUs to check to release. 11655 * The sequence number is masked by 0x3f. 11656 * - REL_SEQ_NUM_END 11657 * Bits 23:18 11658 * Purpose: Indicate the end of a series of MPDUs to release. 11659 * Value: 11660 * The sequence number one larger than the sequence number of the 11661 * last MPDU to check to release. 11662 * The sequence number is masked by 0x3f. 11663 * All MPDUs within this series are present and valid - the host 11664 * need not check each sequence number within this range to see if 11665 * the corresponding MPDU is actually present. 11666 * This field is only valid if the RV bit is set. 11667 * - NUM_MPDU_RANGES 11668 * Bits 31:24 11669 * Purpose: Indicate how many ranges of MPDUs are present. 11670 * Each MPDU range consists of a series of contiguous MPDUs within the 11671 * rx frame sequence which all have the same MPDU status. 11672 * Value: 1-63 (typically a small number, like 1-3) 11673 * 11674 * Rx PPDU descriptor fields: 11675 * - RSSI_CMB 11676 * Bits 7:0 11677 * Purpose: Combined RSSI from all active rx chains, across the active 11678 * bandwidth. 11679 * Value: RSSI dB units w.r.t. noise floor 11680 * - TIMESTAMP_SUBMICROSEC 11681 * Bits 15:8 11682 * Purpose: high-resolution timestamp 11683 * Value: 11684 * Sub-microsecond time of PPDU reception. 11685 * This timestamp ranges from [0,MAC clock MHz). 11686 * This timestamp can be used in conjunction with TIMESTAMP_MICROSEC 11687 * to form a high-resolution, large range rx timestamp. 11688 * - PHY_ERR_CODE 11689 * Bits 23:16 11690 * Purpose: 11691 * If the rx frame processing resulted in a PHY error, indicate what 11692 * type of rx PHY error occurred. 11693 * Value: 11694 * This field is valid if the "P" (PHY_ERR) flag is set. 11695 * TBD: document/specify the values for this field 11696 * - PHY_ERR 11697 * Bit 24 11698 * Purpose: indicate whether the rx PPDU had a PHY error 11699 * Value: 0 -> no rx PHY error, 1 -> rx PHY error encountered 11700 * - LEGACY_RATE 11701 * Bits 28:25 11702 * Purpose: 11703 * If the rx frame used a legacy rate rather than a HT or VHT rate, 11704 * specify which rate was used. 11705 * Value: 11706 * The LEGACY_RATE field's value depends on the "L" (LEGACY_RATE_SEL) 11707 * flag. 11708 * If LEGACY_RATE_SEL is 0: 11709 * 0x8: OFDM 48 Mbps 11710 * 0x9: OFDM 24 Mbps 11711 * 0xA: OFDM 12 Mbps 11712 * 0xB: OFDM 6 Mbps 11713 * 0xC: OFDM 54 Mbps 11714 * 0xD: OFDM 36 Mbps 11715 * 0xE: OFDM 18 Mbps 11716 * 0xF: OFDM 9 Mbps 11717 * If LEGACY_RATE_SEL is 1: 11718 * 0x8: CCK 11 Mbps long preamble 11719 * 0x9: CCK 5.5 Mbps long preamble 11720 * 0xA: CCK 2 Mbps long preamble 11721 * 0xB: CCK 1 Mbps long preamble 11722 * 0xC: CCK 11 Mbps short preamble 11723 * 0xD: CCK 5.5 Mbps short preamble 11724 * 0xE: CCK 2 Mbps short preamble 11725 * - LEGACY_RATE_SEL 11726 * Bit 29 11727 * Purpose: if rx used a legacy rate, specify whether it was OFDM or CCK 11728 * Value: 11729 * This field is valid if the PREAMBLE_TYPE field indicates the rx 11730 * used a legacy rate. 11731 * 0 -> OFDM, 1 -> CCK 11732 * - END_VALID 11733 * Bit 30 11734 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 11735 * the start of the PPDU are valid. Specifically, the following 11736 * fields are only valid if END_VALID is set: 11737 * PHY_ERR, PHY_ERR_CODE, TSF32, TIMESTAMP_MICROSEC, 11738 * TIMESTAMP_SUBMICROSEC 11739 * Value: 11740 * 0 -> rx PPDU desc end fields are not valid 11741 * 1 -> rx PPDU desc end fields are valid 11742 * - START_VALID 11743 * Bit 31 11744 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 11745 * the end of the PPDU are valid. Specifically, the following 11746 * fields are only valid if START_VALID is set: 11747 * RSSI, LEGACY_RATE_SEL, LEGACY_RATE, PREAMBLE_TYPE, SERVICE, 11748 * VHT-SIG-A 11749 * Value: 11750 * 0 -> rx PPDU desc start fields are not valid 11751 * 1 -> rx PPDU desc start fields are valid 11752 * - RSSI0_PRI20 11753 * Bits 7:0 11754 * Purpose: RSSI from chain 0 on the primary 20 MHz channel 11755 * Value: RSSI dB units w.r.t. noise floor 11756 * 11757 * - RSSI0_EXT20 11758 * Bits 7:0 11759 * Purpose: RSSI from chain 0 on the bonded extension 20 MHz channel 11760 * (if the rx bandwidth was >= 40 MHz) 11761 * Value: RSSI dB units w.r.t. noise floor 11762 * - RSSI0_EXT40 11763 * Bits 7:0 11764 * Purpose: RSSI from chain 0 on the bonded extension 40 MHz channel 11765 * (if the rx bandwidth was >= 80 MHz) 11766 * Value: RSSI dB units w.r.t. noise floor 11767 * - RSSI0_EXT80 11768 * Bits 7:0 11769 * Purpose: RSSI from chain 0 on the bonded extension 80 MHz channel 11770 * (if the rx bandwidth was >= 160 MHz) 11771 * Value: RSSI dB units w.r.t. noise floor 11772 * 11773 * - RSSI1_PRI20 11774 * Bits 7:0 11775 * Purpose: RSSI from chain 1 on the primary 20 MHz channel 11776 * Value: RSSI dB units w.r.t. noise floor 11777 * - RSSI1_EXT20 11778 * Bits 7:0 11779 * Purpose: RSSI from chain 1 on the bonded extension 20 MHz channel 11780 * (if the rx bandwidth was >= 40 MHz) 11781 * Value: RSSI dB units w.r.t. noise floor 11782 * - RSSI1_EXT40 11783 * Bits 7:0 11784 * Purpose: RSSI from chain 1 on the bonded extension 40 MHz channel 11785 * (if the rx bandwidth was >= 80 MHz) 11786 * Value: RSSI dB units w.r.t. noise floor 11787 * - RSSI1_EXT80 11788 * Bits 7:0 11789 * Purpose: RSSI from chain 1 on the bonded extension 80 MHz channel 11790 * (if the rx bandwidth was >= 160 MHz) 11791 * Value: RSSI dB units w.r.t. noise floor 11792 * 11793 * - RSSI2_PRI20 11794 * Bits 7:0 11795 * Purpose: RSSI from chain 2 on the primary 20 MHz channel 11796 * Value: RSSI dB units w.r.t. noise floor 11797 * - RSSI2_EXT20 11798 * Bits 7:0 11799 * Purpose: RSSI from chain 2 on the bonded extension 20 MHz channel 11800 * (if the rx bandwidth was >= 40 MHz) 11801 * Value: RSSI dB units w.r.t. noise floor 11802 * - RSSI2_EXT40 11803 * Bits 7:0 11804 * Purpose: RSSI from chain 2 on the bonded extension 40 MHz channel 11805 * (if the rx bandwidth was >= 80 MHz) 11806 * Value: RSSI dB units w.r.t. noise floor 11807 * - RSSI2_EXT80 11808 * Bits 7:0 11809 * Purpose: RSSI from chain 2 on the bonded extension 80 MHz channel 11810 * (if the rx bandwidth was >= 160 MHz) 11811 * Value: RSSI dB units w.r.t. noise floor 11812 * 11813 * - RSSI3_PRI20 11814 * Bits 7:0 11815 * Purpose: RSSI from chain 3 on the primary 20 MHz channel 11816 * Value: RSSI dB units w.r.t. noise floor 11817 * - RSSI3_EXT20 11818 * Bits 7:0 11819 * Purpose: RSSI from chain 3 on the bonded extension 20 MHz channel 11820 * (if the rx bandwidth was >= 40 MHz) 11821 * Value: RSSI dB units w.r.t. noise floor 11822 * - RSSI3_EXT40 11823 * Bits 7:0 11824 * Purpose: RSSI from chain 3 on the bonded extension 40 MHz channel 11825 * (if the rx bandwidth was >= 80 MHz) 11826 * Value: RSSI dB units w.r.t. noise floor 11827 * - RSSI3_EXT80 11828 * Bits 7:0 11829 * Purpose: RSSI from chain 3 on the bonded extension 80 MHz channel 11830 * (if the rx bandwidth was >= 160 MHz) 11831 * Value: RSSI dB units w.r.t. noise floor 11832 * 11833 * - TSF32 11834 * Bits 31:0 11835 * Purpose: specify the time the rx PPDU was received, in TSF units 11836 * Value: 32 LSBs of the TSF 11837 * - TIMESTAMP_MICROSEC 11838 * Bits 31:0 11839 * Purpose: specify the time the rx PPDU was received, in microsecond units 11840 * Value: PPDU rx time, in microseconds 11841 * - VHT_SIG_A1 11842 * Bits 23:0 11843 * Purpose: Provide the HT-SIG (initial 24 bits) or VHT-SIG-A1 field 11844 * from the rx PPDU 11845 * Value: 11846 * If PREAMBLE_TYPE specifies VHT, then this field contains the 11847 * VHT-SIG-A1 data. 11848 * If PREAMBLE_TYPE specifies HT, then this field contains the 11849 * first 24 bits of the HT-SIG data. 11850 * Otherwise, this field is invalid. 11851 * Refer to the the 802.11 protocol for the definition of the 11852 * HT-SIG and VHT-SIG-A1 fields 11853 * - VHT_SIG_A2 11854 * Bits 23:0 11855 * Purpose: Provide the HT-SIG (final 24 bits) or VHT-SIG-A2 field 11856 * from the rx PPDU 11857 * Value: 11858 * If PREAMBLE_TYPE specifies VHT, then this field contains the 11859 * VHT-SIG-A2 data. 11860 * If PREAMBLE_TYPE specifies HT, then this field contains the 11861 * last 24 bits of the HT-SIG data. 11862 * Otherwise, this field is invalid. 11863 * Refer to the the 802.11 protocol for the definition of the 11864 * HT-SIG and VHT-SIG-A2 fields 11865 * - PREAMBLE_TYPE 11866 * Bits 31:24 11867 * Purpose: indicate the PHY format of the received burst 11868 * Value: 11869 * 0x4: Legacy (OFDM/CCK) 11870 * 0x8: HT 11871 * 0x9: HT with TxBF 11872 * 0xC: VHT 11873 * 0xD: VHT with TxBF 11874 * - SERVICE 11875 * Bits 31:24 11876 * Purpose: TBD 11877 * Value: TBD 11878 * 11879 * Rx MSDU descriptor fields: 11880 * - FW_RX_DESC_BYTES 11881 * Bits 15:0 11882 * Purpose: Indicate how many bytes in the Rx indication are used for 11883 * FW Rx descriptors 11884 * 11885 * Payload fields: 11886 * - MPDU_COUNT 11887 * Bits 7:0 11888 * Purpose: Indicate how many sequential MPDUs share the same status. 11889 * All MPDUs within the indicated list are from the same RA-TA-TID. 11890 * - MPDU_STATUS 11891 * Bits 15:8 11892 * Purpose: Indicate whether the (group of sequential) MPDU(s) were 11893 * received successfully. 11894 * Value: 11895 * 0x1: success 11896 * 0x2: FCS error 11897 * 0x3: duplicate error 11898 * 0x4: replay error 11899 * 0x5: invalid peer 11900 */ 11901 /* header fields */ 11902 #define HTT_RX_IND_EXT_TID_M 0x1f00 11903 #define HTT_RX_IND_EXT_TID_S 8 11904 #define HTT_RX_IND_FLUSH_VALID_M 0x2000 11905 #define HTT_RX_IND_FLUSH_VALID_S 13 11906 #define HTT_RX_IND_REL_VALID_M 0x4000 11907 #define HTT_RX_IND_REL_VALID_S 14 11908 #define HTT_RX_IND_PEER_ID_M 0xffff0000 11909 #define HTT_RX_IND_PEER_ID_S 16 11910 11911 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_M 0x3f 11912 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_S 0 11913 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_M 0xfc0 11914 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_S 6 11915 #define HTT_RX_IND_REL_SEQ_NUM_START_M 0x3f000 11916 #define HTT_RX_IND_REL_SEQ_NUM_START_S 12 11917 #define HTT_RX_IND_REL_SEQ_NUM_END_M 0xfc0000 11918 #define HTT_RX_IND_REL_SEQ_NUM_END_S 18 11919 #define HTT_RX_IND_NUM_MPDU_RANGES_M 0xff000000 11920 #define HTT_RX_IND_NUM_MPDU_RANGES_S 24 11921 11922 /* rx PPDU descriptor fields */ 11923 #define HTT_RX_IND_RSSI_CMB_M 0x000000ff 11924 #define HTT_RX_IND_RSSI_CMB_S 0 11925 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M 0x0000ff00 11926 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S 8 11927 #define HTT_RX_IND_PHY_ERR_CODE_M 0x00ff0000 11928 #define HTT_RX_IND_PHY_ERR_CODE_S 16 11929 #define HTT_RX_IND_PHY_ERR_M 0x01000000 11930 #define HTT_RX_IND_PHY_ERR_S 24 11931 #define HTT_RX_IND_LEGACY_RATE_M 0x1e000000 11932 #define HTT_RX_IND_LEGACY_RATE_S 25 11933 #define HTT_RX_IND_LEGACY_RATE_SEL_M 0x20000000 11934 #define HTT_RX_IND_LEGACY_RATE_SEL_S 29 11935 #define HTT_RX_IND_END_VALID_M 0x40000000 11936 #define HTT_RX_IND_END_VALID_S 30 11937 #define HTT_RX_IND_START_VALID_M 0x80000000 11938 #define HTT_RX_IND_START_VALID_S 31 11939 11940 #define HTT_RX_IND_RSSI_PRI20_M 0x000000ff 11941 #define HTT_RX_IND_RSSI_PRI20_S 0 11942 #define HTT_RX_IND_RSSI_EXT20_M 0x0000ff00 11943 #define HTT_RX_IND_RSSI_EXT20_S 8 11944 #define HTT_RX_IND_RSSI_EXT40_M 0x00ff0000 11945 #define HTT_RX_IND_RSSI_EXT40_S 16 11946 #define HTT_RX_IND_RSSI_EXT80_M 0xff000000 11947 #define HTT_RX_IND_RSSI_EXT80_S 24 11948 11949 #define HTT_RX_IND_VHT_SIG_A1_M 0x00ffffff 11950 #define HTT_RX_IND_VHT_SIG_A1_S 0 11951 #define HTT_RX_IND_VHT_SIG_A2_M 0x00ffffff 11952 #define HTT_RX_IND_VHT_SIG_A2_S 0 11953 #define HTT_RX_IND_PREAMBLE_TYPE_M 0xff000000 11954 #define HTT_RX_IND_PREAMBLE_TYPE_S 24 11955 #define HTT_RX_IND_SERVICE_M 0xff000000 11956 #define HTT_RX_IND_SERVICE_S 24 11957 #define HTT_RX_IND_SA_ANT_MATRIX_M 0xff000000 11958 #define HTT_RX_IND_SA_ANT_MATRIX_S 24 11959 11960 /* rx MSDU descriptor fields */ 11961 #define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff 11962 #define HTT_RX_IND_FW_RX_DESC_BYTES_S 0 11963 11964 /* payload fields */ 11965 #define HTT_RX_IND_MPDU_COUNT_M 0xff 11966 #define HTT_RX_IND_MPDU_COUNT_S 0 11967 #define HTT_RX_IND_MPDU_STATUS_M 0xff00 11968 #define HTT_RX_IND_MPDU_STATUS_S 8 11969 11970 11971 #define HTT_RX_IND_EXT_TID_SET(word, value) \ 11972 do { \ 11973 HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ 11974 (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ 11975 } while (0) 11976 #define HTT_RX_IND_EXT_TID_GET(word) \ 11977 (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) 11978 11979 #define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ 11980 do { \ 11981 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ 11982 (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ 11983 } while (0) 11984 #define HTT_RX_IND_FLUSH_VALID_GET(word) \ 11985 (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) 11986 11987 #define HTT_RX_IND_REL_VALID_SET(word, value) \ 11988 do { \ 11989 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ 11990 (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ 11991 } while (0) 11992 #define HTT_RX_IND_REL_VALID_GET(word) \ 11993 (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) 11994 11995 #define HTT_RX_IND_PEER_ID_SET(word, value) \ 11996 do { \ 11997 HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ 11998 (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ 11999 } while (0) 12000 #define HTT_RX_IND_PEER_ID_GET(word) \ 12001 (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) 12002 12003 12004 #define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ 12005 do { \ 12006 HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ 12007 (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ 12008 } while (0) 12009 #define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ 12010 (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> HTT_RX_IND_FW_RX_DESC_BYTES_S) 12011 12012 12013 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ 12014 do { \ 12015 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ 12016 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ 12017 } while (0) 12018 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ 12019 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ 12020 HTT_RX_IND_FLUSH_SEQ_NUM_START_S) 12021 12022 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ 12023 do { \ 12024 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ 12025 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ 12026 } while (0) 12027 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ 12028 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ 12029 HTT_RX_IND_FLUSH_SEQ_NUM_END_S) 12030 12031 #define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ 12032 do { \ 12033 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ 12034 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ 12035 } while (0) 12036 #define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ 12037 (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ 12038 HTT_RX_IND_REL_SEQ_NUM_START_S) 12039 12040 #define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ 12041 do { \ 12042 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ 12043 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ 12044 } while (0) 12045 #define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ 12046 (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ 12047 HTT_RX_IND_REL_SEQ_NUM_END_S) 12048 12049 #define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ 12050 do { \ 12051 HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ 12052 (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ 12053 } while (0) 12054 #define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ 12055 (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ 12056 HTT_RX_IND_NUM_MPDU_RANGES_S) 12057 12058 /* FW rx PPDU descriptor fields */ 12059 #define HTT_RX_IND_RSSI_CMB_SET(word, value) \ 12060 do { \ 12061 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ 12062 (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ 12063 } while (0) 12064 #define HTT_RX_IND_RSSI_CMB_GET(word) \ 12065 (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ 12066 HTT_RX_IND_RSSI_CMB_S) 12067 12068 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ 12069 do { \ 12070 HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ 12071 (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ 12072 } while (0) 12073 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ 12074 (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ 12075 HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) 12076 12077 #define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ 12078 do { \ 12079 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ 12080 (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ 12081 } while (0) 12082 #define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ 12083 (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ 12084 HTT_RX_IND_PHY_ERR_CODE_S) 12085 12086 #define HTT_RX_IND_PHY_ERR_SET(word, value) \ 12087 do { \ 12088 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ 12089 (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ 12090 } while (0) 12091 #define HTT_RX_IND_PHY_ERR_GET(word) \ 12092 (((word) & HTT_RX_IND_PHY_ERR_M) >> \ 12093 HTT_RX_IND_PHY_ERR_S) 12094 12095 #define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ 12096 do { \ 12097 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ 12098 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ 12099 } while (0) 12100 #define HTT_RX_IND_LEGACY_RATE_GET(word) \ 12101 (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ 12102 HTT_RX_IND_LEGACY_RATE_S) 12103 12104 #define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ 12105 do { \ 12106 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ 12107 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ 12108 } while (0) 12109 #define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ 12110 (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ 12111 HTT_RX_IND_LEGACY_RATE_SEL_S) 12112 12113 #define HTT_RX_IND_END_VALID_SET(word, value) \ 12114 do { \ 12115 HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ 12116 (word) |= (value) << HTT_RX_IND_END_VALID_S; \ 12117 } while (0) 12118 #define HTT_RX_IND_END_VALID_GET(word) \ 12119 (((word) & HTT_RX_IND_END_VALID_M) >> \ 12120 HTT_RX_IND_END_VALID_S) 12121 12122 #define HTT_RX_IND_START_VALID_SET(word, value) \ 12123 do { \ 12124 HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ 12125 (word) |= (value) << HTT_RX_IND_START_VALID_S; \ 12126 } while (0) 12127 #define HTT_RX_IND_START_VALID_GET(word) \ 12128 (((word) & HTT_RX_IND_START_VALID_M) >> \ 12129 HTT_RX_IND_START_VALID_S) 12130 12131 #define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ 12132 do { \ 12133 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ 12134 (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ 12135 } while (0) 12136 #define HTT_RX_IND_RSSI_PRI20_GET(word) \ 12137 (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ 12138 HTT_RX_IND_RSSI_PRI20_S) 12139 12140 #define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ 12141 do { \ 12142 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ 12143 (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ 12144 } while (0) 12145 #define HTT_RX_IND_RSSI_EXT20_GET(word) \ 12146 (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ 12147 HTT_RX_IND_RSSI_EXT20_S) 12148 12149 #define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ 12150 do { \ 12151 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ 12152 (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ 12153 } while (0) 12154 #define HTT_RX_IND_RSSI_EXT40_GET(word) \ 12155 (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ 12156 HTT_RX_IND_RSSI_EXT40_S) 12157 12158 #define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ 12159 do { \ 12160 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ 12161 (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ 12162 } while (0) 12163 #define HTT_RX_IND_RSSI_EXT80_GET(word) \ 12164 (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ 12165 HTT_RX_IND_RSSI_EXT80_S) 12166 12167 #define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ 12168 do { \ 12169 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ 12170 (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ 12171 } while (0) 12172 #define HTT_RX_IND_VHT_SIG_A1_GET(word) \ 12173 (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ 12174 HTT_RX_IND_VHT_SIG_A1_S) 12175 12176 #define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ 12177 do { \ 12178 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ 12179 (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ 12180 } while (0) 12181 #define HTT_RX_IND_VHT_SIG_A2_GET(word) \ 12182 (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ 12183 HTT_RX_IND_VHT_SIG_A2_S) 12184 12185 #define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ 12186 do { \ 12187 HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ 12188 (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ 12189 } while (0) 12190 #define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ 12191 (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ 12192 HTT_RX_IND_PREAMBLE_TYPE_S) 12193 12194 #define HTT_RX_IND_SERVICE_SET(word, value) \ 12195 do { \ 12196 HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ 12197 (word) |= (value) << HTT_RX_IND_SERVICE_S; \ 12198 } while (0) 12199 #define HTT_RX_IND_SERVICE_GET(word) \ 12200 (((word) & HTT_RX_IND_SERVICE_M) >> \ 12201 HTT_RX_IND_SERVICE_S) 12202 12203 #define HTT_RX_IND_SA_ANT_MATRIX_SET(word, value) \ 12204 do { \ 12205 HTT_CHECK_SET_VAL(HTT_RX_IND_SA_ANT_MATRIX, value); \ 12206 (word) |= (value) << HTT_RX_IND_SA_ANT_MATRIX_S; \ 12207 } while (0) 12208 #define HTT_RX_IND_SA_ANT_MATRIX_GET(word) \ 12209 (((word) & HTT_RX_IND_SA_ANT_MATRIX_M) >> \ 12210 HTT_RX_IND_SA_ANT_MATRIX_S) 12211 12212 #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \ 12213 do { \ 12214 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ 12215 (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ 12216 } while (0) 12217 #define HTT_RX_IND_MPDU_COUNT_GET(word) \ 12218 (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) 12219 12220 #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \ 12221 do { \ 12222 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ 12223 (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ 12224 } while (0) 12225 #define HTT_RX_IND_MPDU_STATUS_GET(word) \ 12226 (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) 12227 12228 12229 #define HTT_RX_IND_HL_BYTES \ 12230 (HTT_RX_IND_HDR_BYTES + \ 12231 4 /* single FW rx MSDU descriptor */ + \ 12232 4 /* single MPDU range information element */) 12233 #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2) 12234 12235 /* Could we use one macro entry? */ 12236 #define HTT_WORD_SET(word, field, value) \ 12237 do { \ 12238 HTT_CHECK_SET_VAL(field, value); \ 12239 (word) |= ((value) << field ## _S); \ 12240 } while (0) 12241 #define HTT_WORD_GET(word, field) \ 12242 (((word) & field ## _M) >> field ## _S) 12243 12244 PREPACK struct hl_htt_rx_ind_base { 12245 A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; /* align with LL case rx indication message, but reduced to 5 words */ 12246 } POSTPACK; 12247 12248 /* 12249 * HTT_RX_IND_HL_RX_DESC_BASE_OFFSET 12250 * Currently, we use a resv field in hl_htt_rx_ind_base to store some 12251 * HL host needed info; refer to fw_rx_desc_base in wal_rx_desc.h. 12252 * The field is just after the MSDU FW rx desc, and 1 byte ahead of 12253 * htt_rx_ind_hl_rx_desc_t. 12254 */ 12255 #define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) 12256 struct htt_rx_ind_hl_rx_desc_t { 12257 A_UINT8 ver; 12258 A_UINT8 len; 12259 struct { 12260 A_UINT8 12261 first_msdu: 1, 12262 last_msdu: 1, 12263 c3_failed: 1, 12264 c4_failed: 1, 12265 ipv6: 1, 12266 tcp: 1, 12267 udp: 1, 12268 reserved: 1; 12269 } flags; 12270 /* NOTE: no reserved space - don't append any new fields here */ 12271 }; 12272 12273 #define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ 12274 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12275 + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) 12276 #define HTT_RX_IND_HL_RX_DESC_VER 0 12277 12278 #define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ 12279 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12280 + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) 12281 12282 #define HTT_RX_IND_HL_FLAG_OFFSET \ 12283 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12284 + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) 12285 12286 #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0) 12287 #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1) 12288 #define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ 12289 #define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ 12290 #define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or else ipv4 */ 12291 #define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ 12292 #define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ 12293 /* This structure is used in HL, the basic descriptor information 12294 * used by host. the structure is translated by FW from HW desc 12295 * or generated by FW. But in HL monitor mode, the host would use 12296 * the same structure with LL. 12297 */ 12298 PREPACK struct hl_htt_rx_desc_base { 12299 A_UINT32 12300 seq_num:12, 12301 encrypted:1, 12302 chan_info_present:1, 12303 resv0:2, 12304 mcast_bcast:1, 12305 fragment:1, 12306 key_id_oct:8, 12307 resv1:6; 12308 A_UINT32 12309 pn_31_0; 12310 union { 12311 struct { 12312 A_UINT16 pn_47_32; 12313 A_UINT16 pn_63_48; 12314 } pn16; 12315 A_UINT32 pn_63_32; 12316 } u0; 12317 A_UINT32 12318 pn_95_64; 12319 A_UINT32 12320 pn_127_96; 12321 } POSTPACK; 12322 12323 12324 /* 12325 * Channel information can optionally be appended after hl_htt_rx_desc_base. 12326 * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly, 12327 * and the chan_info_present flag in hl_htt_rx_desc_base will be set. 12328 * Please see htt_chan_change_t for description of the fields. 12329 */ 12330 PREPACK struct htt_chan_info_t 12331 { 12332 A_UINT32 primary_chan_center_freq_mhz: 16, 12333 contig_chan1_center_freq_mhz: 16; 12334 A_UINT32 contig_chan2_center_freq_mhz: 16, 12335 phy_mode: 8, 12336 reserved: 8; 12337 } POSTPACK; 12338 12339 #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t) 12340 12341 #define HL_RX_DESC_SIZE (sizeof(struct hl_htt_rx_desc_base)) 12342 #define HL_RX_DESC_SIZE_DWORD (HL_RX_STD_DESC_SIZE >> 2) 12343 12344 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_M 0xfff 12345 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_S 0 12346 #define HTT_HL_RX_DESC_MPDU_ENC_M 0x1000 12347 #define HTT_HL_RX_DESC_MPDU_ENC_S 12 12348 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_M 0x2000 12349 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_S 13 12350 #define HTT_HL_RX_DESC_MCAST_BCAST_M 0x10000 12351 #define HTT_HL_RX_DESC_MCAST_BCAST_S 16 12352 #define HTT_HL_RX_DESC_FRAGMENT_M 0x20000 12353 #define HTT_HL_RX_DESC_FRAGMENT_S 17 12354 #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000 12355 #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18 12356 12357 #define HTT_HL_RX_DESC_PN_OFFSET offsetof(struct hl_htt_rx_desc_base, pn_31_0) 12358 #define HTT_HL_RX_DESC_PN_WORD_OFFSET (HTT_HL_RX_DESC_PN_OFFSET >> 2) 12359 12360 12361 /* Channel information */ 12362 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff 12363 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S 0 12364 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M 0xffff0000 12365 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S 16 12366 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M 0x0000ffff 12367 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S 0 12368 #define HTT_CHAN_INFO_PHY_MODE_M 0x00ff0000 12369 #define HTT_CHAN_INFO_PHY_MODE_S 16 12370 12371 12372 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ 12373 do { \ 12374 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ 12375 (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ 12376 } while (0) 12377 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ 12378 (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) 12379 12380 12381 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ 12382 do { \ 12383 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ 12384 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ 12385 } while (0) 12386 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ 12387 (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) 12388 12389 12390 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ 12391 do { \ 12392 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ 12393 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ 12394 } while (0) 12395 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ 12396 (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) 12397 12398 12399 #define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ 12400 do { \ 12401 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ 12402 (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ 12403 } while (0) 12404 #define HTT_CHAN_INFO_PHY_MODE_GET(word) \ 12405 (((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S) 12406 12407 /* 12408 * @brief target -> host message definition for FW offloaded pkts 12409 * 12410 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND 12411 * 12412 * @details 12413 * The following field definitions describe the format of the firmware 12414 * offload deliver message sent from the target to the host. 12415 * 12416 * definition for struct htt_tx_offload_deliver_ind_hdr_t 12417 * 12418 * |31 20|19 16|15 13|12 8|7 5|4|3|2 0| 12419 * |----------------------------+--------+-----+---------------+-----+-+-+----| 12420 * | reserved_1 | msg type | 12421 * |--------------------------------------------------------------------------| 12422 * | phy_timestamp_l32 | 12423 * |--------------------------------------------------------------------------| 12424 * | WORD2 (see below) | 12425 * |--------------------------------------------------------------------------| 12426 * | seqno | framectrl | 12427 * |--------------------------------------------------------------------------| 12428 * | reserved_3 | vdev_id | tid_num| 12429 * |--------------------------------------------------------------------------| 12430 * | reserved_4 | tx_mpdu_bytes |F|STAT| 12431 * |--------------------------------------------------------------------------| 12432 * 12433 * where: 12434 * STAT = status 12435 * F = format (802.3 vs. 802.11) 12436 * 12437 * definition for word 2 12438 * 12439 * |31 26|25| 24 |23 | 22 |21 19|18 17|16 9|8 6|5 2|1 0| 12440 * |--------+--+----+---+----+-----+-----+---------------------+----+-----+---| 12441 * |reserv_2|BF|LDPC|SGI|STBC| BW | NSS | RSSI |RATE| MCS |PR | 12442 * |--------------------------------------------------------------------------| 12443 * 12444 * where: 12445 * PR = preamble 12446 * BF = beamformed 12447 */ 12448 12449 PREPACK struct htt_tx_offload_deliver_ind_hdr_t 12450 { 12451 A_UINT32 /* word 0 */ 12452 msg_type:8, /* [ 7: 0] */ 12453 reserved_1:24; /* [31: 8] */ 12454 A_UINT32 phy_timestamp_l32; /* word 1 [31:0] */ 12455 A_UINT32 /* word 2 */ 12456 /* preamble: 12457 * 0-OFDM, 12458 * 1-CCk, 12459 * 2-HT, 12460 * 3-VHT 12461 */ 12462 preamble: 2, /* [1:0] */ 12463 /* mcs: 12464 * In case of HT preamble interpret 12465 * MCS along with NSS. 12466 * Valid values for HT are 0 to 7. 12467 * HT mcs 0 with NSS 2 is mcs 8. 12468 * Valid values for VHT are 0 to 9. 12469 */ 12470 mcs: 4, /* [5:2] */ 12471 /* rate: 12472 * This is applicable only for 12473 * CCK and OFDM preamble type 12474 * rate 0: OFDM 48 Mbps, 12475 * 1: OFDM 24 Mbps, 12476 * 2: OFDM 12 Mbps 12477 * 3: OFDM 6 Mbps 12478 * 4: OFDM 54 Mbps 12479 * 5: OFDM 36 Mbps 12480 * 6: OFDM 18 Mbps 12481 * 7: OFDM 9 Mbps 12482 * rate 0: CCK 11 Mbps Long 12483 * 1: CCK 5.5 Mbps Long 12484 * 2: CCK 2 Mbps Long 12485 * 3: CCK 1 Mbps Long 12486 * 4: CCK 11 Mbps Short 12487 * 5: CCK 5.5 Mbps Short 12488 * 6: CCK 2 Mbps Short 12489 */ 12490 rate : 3, /* [ 8: 6] */ 12491 rssi : 8, /* [16: 9] units=dBm */ 12492 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 12493 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 12494 stbc : 1, /* [22] */ 12495 sgi : 1, /* [23] */ 12496 ldpc : 1, /* [24] */ 12497 beamformed: 1, /* [25] */ 12498 reserved_2: 6; /* [31:26] */ 12499 A_UINT32 /* word 3 */ 12500 framectrl:16, /* [15: 0] */ 12501 seqno:16; /* [31:16] */ 12502 A_UINT32 /* word 4 */ 12503 tid_num:5, /* [ 4: 0] actual TID number */ 12504 vdev_id:8, /* [12: 5] */ 12505 reserved_3:19; /* [31:13] */ 12506 A_UINT32 /* word 5 */ 12507 /* status: 12508 * 0: tx_ok 12509 * 1: retry 12510 * 2: drop 12511 * 3: filtered 12512 * 4: abort 12513 * 5: tid delete 12514 * 6: sw abort 12515 * 7: dropped by peer migration 12516 */ 12517 status:3, /* [2:0] */ 12518 format:1, /* [3] 0: 802.3 format, 1: 802.11 format */ 12519 tx_mpdu_bytes:16, /* [19:4] */ 12520 /* Indicates retry count of offloaded/local generated Data tx frames */ 12521 tx_retry_cnt:6, /* [25:20] */ 12522 reserved_4:6; /* [31:26] */ 12523 } POSTPACK; 12524 12525 /* FW offload deliver ind message header fields */ 12526 12527 /* DWORD one */ 12528 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M 0xffffffff 12529 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S 0 12530 12531 /* DWORD two */ 12532 #define HTT_FW_OFFLOAD_IND_PREAMBLE_M 0x00000003 12533 #define HTT_FW_OFFLOAD_IND_PREAMBLE_S 0 12534 #define HTT_FW_OFFLOAD_IND_MCS_M 0x0000003c 12535 #define HTT_FW_OFFLOAD_IND_MCS_S 2 12536 #define HTT_FW_OFFLOAD_IND_RATE_M 0x000001c0 12537 #define HTT_FW_OFFLOAD_IND_RATE_S 6 12538 #define HTT_FW_OFFLOAD_IND_RSSI_M 0x0001fe00 12539 #define HTT_FW_OFFLOAD_IND_RSSI_S 9 12540 #define HTT_FW_OFFLOAD_IND_NSS_M 0x00060000 12541 #define HTT_FW_OFFLOAD_IND_NSS_S 17 12542 #define HTT_FW_OFFLOAD_IND_BW_M 0x00380000 12543 #define HTT_FW_OFFLOAD_IND_BW_S 19 12544 #define HTT_FW_OFFLOAD_IND_STBC_M 0x00400000 12545 #define HTT_FW_OFFLOAD_IND_STBC_S 22 12546 #define HTT_FW_OFFLOAD_IND_SGI_M 0x00800000 12547 #define HTT_FW_OFFLOAD_IND_SGI_S 23 12548 #define HTT_FW_OFFLOAD_IND_LDPC_M 0x01000000 12549 #define HTT_FW_OFFLOAD_IND_LDPC_S 24 12550 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_M 0x02000000 12551 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_S 25 12552 12553 /* DWORD three*/ 12554 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_M 0x0000ffff 12555 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_S 0 12556 #define HTT_FW_OFFLOAD_IND_SEQNO_M 0xffff0000 12557 #define HTT_FW_OFFLOAD_IND_SEQNO_S 16 12558 12559 /* DWORD four */ 12560 #define HTT_FW_OFFLOAD_IND_TID_NUM_M 0x0000001f 12561 #define HTT_FW_OFFLOAD_IND_TID_NUM_S 0 12562 #define HTT_FW_OFFLOAD_IND_VDEV_ID_M 0x00001fe0 12563 #define HTT_FW_OFFLOAD_IND_VDEV_ID_S 5 12564 12565 /* DWORD five */ 12566 #define HTT_FW_OFFLOAD_IND_STATUS_M 0x00000007 12567 #define HTT_FW_OFFLOAD_IND_STATUS_S 0 12568 #define HTT_FW_OFFLOAD_IND_FORMAT_M 0x00000008 12569 #define HTT_FW_OFFLOAD_IND_FORMAT_S 3 12570 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M 0x000ffff0 12571 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S 4 12572 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M 0x03f00000 12573 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S 20 12574 12575 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_SET(word, value) \ 12576 do { \ 12577 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32, value); \ 12578 (word) |= (value) << HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S; \ 12579 } while (0) 12580 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_GET(word) \ 12581 (((word) & HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M) >> HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S) 12582 12583 #define HTT_FW_OFFLOAD_IND_PREAMBLE_SET(word, value) \ 12584 do { \ 12585 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PREAMBLE, value); \ 12586 (word) |= (value) << HTT_FW_OFFLOAD_IND_PREAMBLE_S; \ 12587 } while (0) 12588 #define HTT_FW_OFFLOAD_IND_PREAMBLE_GET(word) \ 12589 (((word) & HTT_FW_OFFLOAD_IND_PREAMBLE_M) >> HTT_FW_OFFLOAD_IND_PREAMBLE_S) 12590 12591 #define HTT_FW_OFFLOAD_IND_MCS_SET(word, value) \ 12592 do { \ 12593 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_MCS, value); \ 12594 (word) |= (value) << HTT_FW_OFFLOAD_IND_MCS_S; \ 12595 } while (0) 12596 #define HTT_FW_OFFLOAD_IND_MCS_GET(word) \ 12597 (((word) & HTT_FW_OFFLOAD_IND_MCS_M) >> HTT_FW_OFFLOAD_IND_MCS_S) 12598 12599 #define HTT_FW_OFFLOAD_IND_RATE_SET(word, value) \ 12600 do { \ 12601 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RATE, value); \ 12602 (word) |= (value) << HTT_FW_OFFLOAD_IND_RATE_S; \ 12603 } while (0) 12604 #define HTT_FW_OFFLOAD_IND_RATE_GET(word) \ 12605 (((word) & HTT_FW_OFFLOAD_IND_RATE_M) >> HTT_FW_OFFLOAD_IND_RATE_S) 12606 12607 #define HTT_FW_OFFLOAD_IND_RSSI_SET(word, value) \ 12608 do { \ 12609 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RSSI, value); \ 12610 (word) |= (value) << HTT_FW_OFFLOAD_IND_RSSI_S; \ 12611 } while (0) 12612 #define HTT_FW_OFFLOAD_IND_RSSI_GET(word) \ 12613 (((word) & HTT_FW_OFFLOAD_IND_RSSI_M) >> HTT_FW_OFFLOAD_IND_RSSI_S) 12614 12615 12616 #define HTT_FW_OFFLOAD_IND_NSS_SET(word, value) \ 12617 do { \ 12618 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_NSS, value); \ 12619 (word) |= (value) << HTT_FW_OFFLOAD_IND_NSS_S; \ 12620 } while (0) 12621 #define HTT_FW_OFFLOAD_IND_NSS_GET(word) \ 12622 (((word) & HTT_FW_OFFLOAD_IND_NSS_M) >> HTT_FW_OFFLOAD_IND_NSS_S) 12623 12624 #define HTT_FW_OFFLOAD_IND_BW_SET(word, value) \ 12625 do { \ 12626 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BW, value); \ 12627 (word) |= (value) << HTT_FW_OFFLOAD_IND_BW_S; \ 12628 } while (0) 12629 #define HTT_FW_OFFLOAD_IND_BW_GET(word) \ 12630 (((word) & HTT_FW_OFFLOAD_IND_BW_M) >> HTT_FW_OFFLOAD_IND_BW_S) 12631 12632 12633 #define HTT_FW_OFFLOAD_IND_STBC_SET(word, value) \ 12634 do { \ 12635 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STBC, value); \ 12636 (word) |= (value) << HTT_FW_OFFLOAD_IND_STBC_S; \ 12637 } while (0) 12638 #define HTT_FW_OFFLOAD_IND_STBC_GET(word) \ 12639 (((word) & HTT_FW_OFFLOAD_IND_STBC_M) >> HTT_FW_OFFLOAD_IND_STBC_S) 12640 12641 12642 #define HTT_FW_OFFLOAD_IND_SGI_SET(word, value) \ 12643 do { \ 12644 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SGI, value); \ 12645 (word) |= (value) << HTT_FW_OFFLOAD_IND_SGI_S; \ 12646 } while (0) 12647 #define HTT_FW_OFFLOAD_IND_SGI_GET(word) \ 12648 (((word) & HTT_FW_OFFLOAD_IND_SGI_M) >> HTT_FW_OFFLOAD_IND_SGI_S) 12649 12650 #define HTT_FW_OFFLOAD_IND_LDPC_SET(word, value) \ 12651 do { \ 12652 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_LDPC, value); \ 12653 (word) |= (value) << HTT_FW_OFFLOAD_IND_LDPC_S; \ 12654 } while (0) 12655 #define HTT_FW_OFFLOAD_IND_LDPC_GET(word) \ 12656 (((word) & HTT_FW_OFFLOAD_IND_LDPC_M) >> HTT_FW_OFFLOAD_IND_LDPC_S) 12657 12658 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_SET(word, value) \ 12659 do { \ 12660 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BEAMFORMED, value); \ 12661 (word) |= (value) << HTT_FW_OFFLOAD_IND_BEAMFORMED_S; \ 12662 } while (0) 12663 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_GET(word) \ 12664 (((word) & HTT_FW_OFFLOAD_IND_BEAMFORMED_M) >> HTT_FW_OFFLOAD_IND_BEAMFORMED_S) 12665 12666 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_SET(word, value) \ 12667 do { \ 12668 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FRAMECTRL, value); \ 12669 (word) |= (value) << HTT_FW_OFFLOAD_IND_FRAMECTRL_S; \ 12670 } while (0) 12671 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_GET(word) \ 12672 (((word) & HTT_FW_OFFLOAD_IND_FRAMECTRL_M) >> HTT_FW_OFFLOAD_IND_FRAMECTRL_S) 12673 12674 12675 #define HTT_FW_OFFLOAD_IND_SEQNO_SET(word, value) \ 12676 do { \ 12677 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SEQNO, value); \ 12678 (word) |= (value) << HTT_FW_OFFLOAD_IND_SEQNO_S; \ 12679 } while (0) 12680 #define HTT_FW_OFFLOAD_IND_SEQNO_GET(word) \ 12681 (((word) & HTT_FW_OFFLOAD_IND_SEQNO_M) >> HTT_FW_OFFLOAD_IND_SEQNO_S) 12682 12683 #define HTT_FW_OFFLOAD_IND_TID_NUM_SET(word, value) \ 12684 do { \ 12685 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TID_NUM, value); \ 12686 (word) |= (value) << HTT_FW_OFFLOAD_IND_TID_NUM_S; \ 12687 } while (0) 12688 #define HTT_FW_OFFLOAD_IND_TID_NUM_GET(word) \ 12689 (((word) & HTT_FW_OFFLOAD_IND_TID_NUM_M) >> HTT_FW_OFFLOAD_IND_TID_NUM_S) 12690 12691 #define HTT_FW_OFFLOAD_IND_VDEV_ID_SET(word, value) \ 12692 do { \ 12693 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_VDEV_ID, value); \ 12694 (word) |= (value) << HTT_FW_OFFLOAD_IND_VDEV_ID_S; \ 12695 } while (0) 12696 #define HTT_FW_OFFLOAD_IND_VDEV_ID_GET(word) \ 12697 (((word) & HTT_FW_OFFLOAD_IND_VDEV_ID_M) >> HTT_FW_OFFLOAD_IND_VDEV_ID_S) 12698 12699 #define HTT_FW_OFFLOAD_IND_STATUS_SET(word, value) \ 12700 do { \ 12701 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STATUS, value); \ 12702 (word) |= (value) << HTT_FW_OFFLOAD_IND_STATUS_S; \ 12703 } while (0) 12704 #define HTT_FW_OFFLOAD_IND_STATUS_GET(word) \ 12705 (((word) & HTT_FW_OFFLOAD_IND_STATUS_M) >> HTT_FW_OFFLOAD_IND_STATUS_M) 12706 12707 12708 #define HTT_FW_OFFLOAD_IND_FORMAT_SET(word, value) \ 12709 do { \ 12710 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FORMAT, value); \ 12711 (word) |= (value) << HTT_FW_OFFLOAD_IND_FORMAT_S; \ 12712 } while (0) 12713 #define HTT_FW_OFFLOAD_IND_FORMAT_GET(word) \ 12714 (((word) & HTT_FW_OFFLOAD_IND_FORMAT_M) >> HTT_FW_OFFLOAD_IND_FORMAT_S) 12715 12716 12717 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_SET(word, value) \ 12718 do { \ 12719 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES, value); \ 12720 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S; \ 12721 } while (0) 12722 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_GET(word) \ 12723 (((word) & HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M) >> HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S) 12724 12725 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_SET(word, value) \ 12726 do { \ 12727 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_RETRY_CNT, value); \ 12728 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S; \ 12729 } while (0) 12730 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_GET(word) \ 12731 (((word) & HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M) >> HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S) 12732 12733 12734 /* 12735 * @brief target -> host rx reorder flush message definition 12736 * 12737 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FLUSH 12738 * 12739 * @details 12740 * The following field definitions describe the format of the rx flush 12741 * message sent from the target to the host. 12742 * The message consists of a 4-octet header, followed by one or more 12743 * 4-octet payload information elements. 12744 * 12745 * |31 24|23 8|7 0| 12746 * |--------------------------------------------------------------| 12747 * | TID | peer ID | msg type | 12748 * |--------------------------------------------------------------| 12749 * | seq num end | seq num start | MPDU status | reserved | 12750 * |--------------------------------------------------------------| 12751 * First DWORD: 12752 * - MSG_TYPE 12753 * Bits 7:0 12754 * Purpose: identifies this as an rx flush message 12755 * Value: 0x2 (HTT_T2H_MSG_TYPE_RX_FLUSH) 12756 * - PEER_ID 12757 * Bits 23:8 (only bits 18:8 actually used) 12758 * Purpose: identify which peer's rx data is being flushed 12759 * Value: (rx) peer ID 12760 * - TID 12761 * Bits 31:24 (only bits 27:24 actually used) 12762 * Purpose: Specifies which traffic identifier's rx data is being flushed 12763 * Value: traffic identifier 12764 * Second DWORD: 12765 * - MPDU_STATUS 12766 * Bits 15:8 12767 * Purpose: 12768 * Indicate whether the flushed MPDUs should be discarded or processed. 12769 * Value: 12770 * 0x1: send the MPDUs from the rx reorder buffer to subsequent 12771 * stages of rx processing 12772 * other: discard the MPDUs 12773 * It is anticipated that flush messages will always have 12774 * MPDU status == 1, but the status flag is included for 12775 * flexibility. 12776 * - SEQ_NUM_START 12777 * Bits 23:16 12778 * Purpose: 12779 * Indicate the start of a series of consecutive MPDUs being flushed. 12780 * Not all MPDUs within this range are necessarily valid - the host 12781 * must check each sequence number within this range to see if the 12782 * corresponding MPDU is actually present. 12783 * Value: 12784 * The sequence number for the first MPDU in the sequence. 12785 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12786 * - SEQ_NUM_END 12787 * Bits 30:24 12788 * Purpose: 12789 * Indicate the end of a series of consecutive MPDUs being flushed. 12790 * Value: 12791 * The sequence number one larger than the sequence number of the 12792 * last MPDU being flushed. 12793 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12794 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] inclusive 12795 * are to be released for further rx processing. 12796 * Not all MPDUs within this range are necessarily valid - the host 12797 * must check each sequence number within this range to see if the 12798 * corresponding MPDU is actually present. 12799 */ 12800 /* first DWORD */ 12801 #define HTT_RX_FLUSH_PEER_ID_M 0xffff00 12802 #define HTT_RX_FLUSH_PEER_ID_S 8 12803 #define HTT_RX_FLUSH_TID_M 0xff000000 12804 #define HTT_RX_FLUSH_TID_S 24 12805 /* second DWORD */ 12806 #define HTT_RX_FLUSH_MPDU_STATUS_M 0x0000ff00 12807 #define HTT_RX_FLUSH_MPDU_STATUS_S 8 12808 #define HTT_RX_FLUSH_SEQ_NUM_START_M 0x00ff0000 12809 #define HTT_RX_FLUSH_SEQ_NUM_START_S 16 12810 #define HTT_RX_FLUSH_SEQ_NUM_END_M 0xff000000 12811 #define HTT_RX_FLUSH_SEQ_NUM_END_S 24 12812 12813 #define HTT_RX_FLUSH_BYTES 8 12814 12815 #define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ 12816 do { \ 12817 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ 12818 (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ 12819 } while (0) 12820 #define HTT_RX_FLUSH_PEER_ID_GET(word) \ 12821 (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) 12822 12823 #define HTT_RX_FLUSH_TID_SET(word, value) \ 12824 do { \ 12825 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ 12826 (word) |= (value) << HTT_RX_FLUSH_TID_S; \ 12827 } while (0) 12828 #define HTT_RX_FLUSH_TID_GET(word) \ 12829 (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) 12830 12831 #define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ 12832 do { \ 12833 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ 12834 (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ 12835 } while (0) 12836 #define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ 12837 (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) 12838 12839 #define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ 12840 do { \ 12841 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ 12842 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ 12843 } while (0) 12844 #define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ 12845 (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> HTT_RX_FLUSH_SEQ_NUM_START_S) 12846 12847 #define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ 12848 do { \ 12849 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ 12850 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ 12851 } while (0) 12852 #define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ 12853 (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) 12854 12855 /* 12856 * @brief target -> host rx pn check indication message 12857 * 12858 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_PN_IND 12859 * 12860 * @details 12861 * The following field definitions describe the format of the Rx PN check 12862 * indication message sent from the target to the host. 12863 * The message consists of a 4-octet header, followed by the start and 12864 * end sequence numbers to be released, followed by the PN IEs. Each PN 12865 * IE is one octet containing the sequence number that failed the PN 12866 * check. 12867 * 12868 * |31 24|23 8|7 0| 12869 * |--------------------------------------------------------------| 12870 * | TID | peer ID | msg type | 12871 * |--------------------------------------------------------------| 12872 * | Reserved | PN IE count | seq num end | seq num start| 12873 * |--------------------------------------------------------------| 12874 * l : PN IE 2 | PN IE 1 | PN IE 0 | 12875 * |--------------------------------------------------------------| 12876 12877 * First DWORD: 12878 * - MSG_TYPE 12879 * Bits 7:0 12880 * Purpose: Identifies this as an rx pn check indication message 12881 * Value: 0x10 (HTT_T2H_MSG_TYPE_RX_PN_IND) 12882 * - PEER_ID 12883 * Bits 23:8 (only bits 18:8 actually used) 12884 * Purpose: identify which peer 12885 * Value: (rx) peer ID 12886 * - TID 12887 * Bits 31:24 (only bits 27:24 actually used) 12888 * Purpose: identify traffic identifier 12889 * Value: traffic identifier 12890 * Second DWORD: 12891 * - SEQ_NUM_START 12892 * Bits 7:0 12893 * Purpose: 12894 * Indicates the starting sequence number of the MPDU in this 12895 * series of MPDUs that went though PN check. 12896 * Value: 12897 * The sequence number for the first MPDU in the sequence. 12898 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12899 * - SEQ_NUM_END 12900 * Bits 15:8 12901 * Purpose: 12902 * Indicates the ending sequence number of the MPDU in this 12903 * series of MPDUs that went though PN check. 12904 * Value: 12905 * The sequence number one larger then the sequence number of the last 12906 * MPDU being flushed. 12907 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12908 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] have been checked 12909 * for invalid PN numbers and are ready to be released for further processing. 12910 * Not all MPDUs within this range are necessarily valid - the host 12911 * must check each sequence number within this range to see if the 12912 * corresponding MPDU is actually present. 12913 * - PN_IE_COUNT 12914 * Bits 23:16 12915 * Purpose: 12916 * Used to determine the variable number of PN information elements in this 12917 * message 12918 * 12919 * PN information elements: 12920 * - PN_IE_x- 12921 * Purpose: 12922 * Each PN information element contains the sequence number of the MPDU that 12923 * has failed the target PN check. 12924 * Value: 12925 * Contains the 6 LSBs of the 802.11 sequence number corresponding to the MPDU 12926 * that failed the PN check. 12927 */ 12928 /* first DWORD */ 12929 #define HTT_RX_PN_IND_PEER_ID_M 0xffff00 12930 #define HTT_RX_PN_IND_PEER_ID_S 8 12931 #define HTT_RX_PN_IND_TID_M 0xff000000 12932 #define HTT_RX_PN_IND_TID_S 24 12933 /* second DWORD */ 12934 #define HTT_RX_PN_IND_SEQ_NUM_START_M 0x000000ff 12935 #define HTT_RX_PN_IND_SEQ_NUM_START_S 0 12936 #define HTT_RX_PN_IND_SEQ_NUM_END_M 0x0000ff00 12937 #define HTT_RX_PN_IND_SEQ_NUM_END_S 8 12938 #define HTT_RX_PN_IND_PN_IE_CNT_M 0x00ff0000 12939 #define HTT_RX_PN_IND_PN_IE_CNT_S 16 12940 12941 #define HTT_RX_PN_IND_BYTES 8 12942 12943 #define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ 12944 do { \ 12945 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ 12946 (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ 12947 } while (0) 12948 #define HTT_RX_PN_IND_PEER_ID_GET(word) \ 12949 (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) 12950 12951 #define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ 12952 do { \ 12953 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ 12954 (word) |= (value) << HTT_RX_PN_IND_TID_S; \ 12955 } while (0) 12956 #define HTT_RX_PN_IND_EXT_TID_GET(word) \ 12957 (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) 12958 12959 #define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ 12960 do { \ 12961 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ 12962 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ 12963 } while (0) 12964 #define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ 12965 (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> HTT_RX_PN_IND_SEQ_NUM_START_S) 12966 12967 #define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ 12968 do { \ 12969 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ 12970 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ 12971 } while (0) 12972 #define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ 12973 (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) 12974 12975 #define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ 12976 do { \ 12977 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ 12978 (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ 12979 } while (0) 12980 #define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ 12981 (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) 12982 12983 /* 12984 * @brief target -> host rx offload deliver message for LL system 12985 * 12986 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND 12987 * 12988 * @details 12989 * In a low latency system this message is sent whenever the offload 12990 * manager flushes out the packets it has coalesced in its coalescing buffer. 12991 * The DMA of the actual packets into host memory is done before sending out 12992 * this message. This message indicates only how many MSDUs to reap. The 12993 * peer ID, vdev ID, tid and MSDU length are copied inline into the header 12994 * portion of the MSDU while DMA'ing into the host memory. Unlike the packets 12995 * DMA'd by the MAC directly into host memory these packets do not contain 12996 * the MAC descriptors in the header portion of the packet. Instead they contain 12997 * the peer ID, vdev ID, tid and MSDU length. Also when the host receives this 12998 * message, the packets are delivered directly to the NW stack without going 12999 * through the regular reorder buffering and PN checking path since it has 13000 * already been done in target. 13001 * 13002 * |31 24|23 16|15 8|7 0| 13003 * |-----------------------------------------------------------------------| 13004 * | Total MSDU count | reserved | msg type | 13005 * |-----------------------------------------------------------------------| 13006 * 13007 * @brief target -> host rx offload deliver message for HL system 13008 * 13009 * @details 13010 * In a high latency system this message is sent whenever the offload manager 13011 * flushes out the packets it has coalesced in its coalescing buffer. The 13012 * actual packets are also carried along with this message. When the host 13013 * receives this message, it is expected to deliver these packets to the NW 13014 * stack directly instead of routing them through the reorder buffering and 13015 * PN checking path since it has already been done in target. 13016 * 13017 * |31 24|23 16|15 8|7 0| 13018 * |-----------------------------------------------------------------------| 13019 * | Total MSDU count | reserved | msg type | 13020 * |-----------------------------------------------------------------------| 13021 * | peer ID | MSDU length | 13022 * |-----------------------------------------------------------------------| 13023 * | MSDU payload | FW Desc | tid | vdev ID | 13024 * |-----------------------------------------------------------------------| 13025 * | MSDU payload contd. | 13026 * |-----------------------------------------------------------------------| 13027 * | peer ID | MSDU length | 13028 * |-----------------------------------------------------------------------| 13029 * | MSDU payload | FW Desc | tid | vdev ID | 13030 * |-----------------------------------------------------------------------| 13031 * | MSDU payload contd. | 13032 * |-----------------------------------------------------------------------| 13033 * 13034 */ 13035 /* first DWORD */ 13036 #define HTT_RX_OFFLOAD_DELIVER_IND_HDR_BYTES 4 13037 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_HDR_BYTES 7 13038 13039 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M 0xffff0000 13040 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S 16 13041 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M 0x0000ffff 13042 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S 0 13043 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M 0xffff0000 13044 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S 16 13045 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M 0x000000ff 13046 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S 0 13047 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M 0x0000ff00 13048 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S 8 13049 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000 13050 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16 13051 13052 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ 13053 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) 13054 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ 13055 do { \ 13056 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ 13057 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ 13058 } while (0) 13059 13060 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ 13061 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) 13062 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ 13063 do { \ 13064 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ 13065 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ 13066 } while (0) 13067 13068 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ 13069 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) 13070 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ 13071 do { \ 13072 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ 13073 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ 13074 } while (0) 13075 13076 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ 13077 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) 13078 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ 13079 do { \ 13080 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ 13081 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ 13082 } while (0) 13083 13084 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ 13085 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) 13086 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ 13087 do { \ 13088 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ 13089 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ 13090 } while (0) 13091 13092 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ 13093 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) 13094 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ 13095 do { \ 13096 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ 13097 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ 13098 } while (0) 13099 13100 /** 13101 * @brief target -> host rx peer map/unmap message definition 13102 * 13103 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP 13104 * 13105 * @details 13106 * The following diagram shows the format of the rx peer map message sent 13107 * from the target to the host. This layout assumes the target operates 13108 * as little-endian. 13109 * 13110 * This message always contains a SW peer ID. The main purpose of the 13111 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13112 * with, so that the host can use that peer ID to determine which peer 13113 * transmitted the rx frame. This SW peer ID is sometimes also used for 13114 * other purposes, such as identifying during tx completions which peer 13115 * the tx frames in question were transmitted to. 13116 * 13117 * In certain generations of chips, the peer map message also contains 13118 * a HW peer ID. This HW peer ID is used during rx --> tx frame forwarding 13119 * to identify which peer the frame needs to be forwarded to (i.e. the 13120 * peer associated with the Destination MAC Address within the packet), 13121 * and particularly which vdev needs to transmit the frame (for cases 13122 * of inter-vdev rx --> tx forwarding). The HW peer id here is the same 13123 * meaning as AST_INDEX_0. 13124 * This DA-based peer ID that is provided for certain rx frames 13125 * (the rx frames that need to be re-transmitted as tx frames) 13126 * is the ID that the HW uses for referring to the peer in question, 13127 * rather than the peer ID that the SW+FW use to refer to the peer. 13128 * 13129 * 13130 * |31 24|23 16|15 8|7 0| 13131 * |-----------------------------------------------------------------------| 13132 * | SW peer ID | VDEV ID | msg type | 13133 * |-----------------------------------------------------------------------| 13134 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13135 * |-----------------------------------------------------------------------| 13136 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13137 * |-----------------------------------------------------------------------| 13138 * 13139 * 13140 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP 13141 * 13142 * The following diagram shows the format of the rx peer unmap message sent 13143 * from the target to the host. 13144 * 13145 * |31 24|23 16|15 8|7 0| 13146 * |-----------------------------------------------------------------------| 13147 * | SW peer ID | VDEV ID | msg type | 13148 * |-----------------------------------------------------------------------| 13149 * 13150 * The following field definitions describe the format of the rx peer map 13151 * and peer unmap messages sent from the target to the host. 13152 * - MSG_TYPE 13153 * Bits 7:0 13154 * Purpose: identifies this as an rx peer map or peer unmap message 13155 * Value: peer map -> 0x3 (HTT_T2H_MSG_TYPE_PEER_MAP), 13156 * peer unmap -> 0x4 (HTT_T2H_MSG_TYPE_PEER_UNMAP) 13157 * - VDEV_ID 13158 * Bits 15:8 13159 * Purpose: Indicates which virtual device the peer is associated 13160 * with. 13161 * Value: vdev ID (used in the host to look up the vdev object) 13162 * - PEER_ID (a.k.a. SW_PEER_ID) 13163 * Bits 31:16 13164 * Purpose: The peer ID (index) that WAL is allocating (map) or 13165 * freeing (unmap) 13166 * Value: (rx) peer ID 13167 * - MAC_ADDR_L32 (peer map only) 13168 * Bits 31:0 13169 * Purpose: Identifies which peer node the peer ID is for. 13170 * Value: lower 4 bytes of peer node's MAC address 13171 * - MAC_ADDR_U16 (peer map only) 13172 * Bits 15:0 13173 * Purpose: Identifies which peer node the peer ID is for. 13174 * Value: upper 2 bytes of peer node's MAC address 13175 * - HW_PEER_ID 13176 * Bits 31:16 13177 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13178 * address, so for rx frames marked for rx --> tx forwarding, the 13179 * host can determine from the HW peer ID provided as meta-data with 13180 * the rx frame which peer the frame is supposed to be forwarded to. 13181 * Value: ID used by the MAC HW to identify the peer 13182 */ 13183 #define HTT_RX_PEER_MAP_VDEV_ID_M 0xff00 13184 #define HTT_RX_PEER_MAP_VDEV_ID_S 8 13185 #define HTT_RX_PEER_MAP_PEER_ID_M 0xffff0000 13186 #define HTT_RX_PEER_MAP_PEER_ID_S 16 13187 #define HTT_RX_PEER_MAP_SW_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M /* alias */ 13188 #define HTT_RX_PEER_MAP_SW_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S /* alias */ 13189 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 13190 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_S 0 13191 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff 13192 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0 13193 #define HTT_RX_PEER_MAP_HW_PEER_ID_M 0xffff0000 13194 #define HTT_RX_PEER_MAP_HW_PEER_ID_S 16 13195 13196 #define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ 13197 #define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ 13198 do { \ 13199 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ 13200 (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ 13201 } while (0) 13202 #define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ 13203 #define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ 13204 (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) 13205 13206 #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \ 13207 do { \ 13208 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 13209 (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ 13210 } while (0) 13211 #define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ 13212 (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) 13213 #define HTT_RX_PEER_MAP_SW_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET /* alias */ 13214 #define HTT_RX_PEER_MAP_SW_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET /* alias */ 13215 13216 #define HTT_RX_PEER_MAP_HW_PEER_ID_SET(word, value) \ 13217 do { \ 13218 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_HW_PEER_ID, value); \ 13219 (word) |= (value) << HTT_RX_PEER_MAP_HW_PEER_ID_S; \ 13220 } while (0) 13221 #define HTT_RX_PEER_MAP_HW_PEER_ID_GET(word) \ 13222 (((word) & HTT_RX_PEER_MAP_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_HW_PEER_ID_S) 13223 13224 #define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 13225 #define HTT_RX_PEER_MAP_HW_PEER_ID_OFFSET 8 /* bytes */ 13226 13227 #define HTT_RX_PEER_MAP_BYTES 12 13228 13229 13230 #define HTT_RX_PEER_UNMAP_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M 13231 #define HTT_RX_PEER_UNMAP_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S 13232 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_M HTT_RX_PEER_MAP_SW_PEER_ID_M 13233 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_S HTT_RX_PEER_MAP_SW_PEER_ID_S 13234 13235 #define HTT_RX_PEER_UNMAP_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET 13236 #define HTT_RX_PEER_UNMAP_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET 13237 13238 #define HTT_RX_PEER_UNMAP_VDEV_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET 13239 #define HTT_RX_PEER_UNMAP_VDEV_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET 13240 13241 #define HTT_RX_PEER_UNMAP_BYTES 4 13242 13243 13244 /** 13245 * @brief target -> host rx peer map V2 message definition 13246 * 13247 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V2 13248 * 13249 * @details 13250 * The following diagram shows the format of the rx peer map v2 message sent 13251 * from the target to the host. This layout assumes the target operates 13252 * as little-endian. 13253 * 13254 * This message always contains a SW peer ID. The main purpose of the 13255 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13256 * with, so that the host can use that peer ID to determine which peer 13257 * transmitted the rx frame. This SW peer ID is sometimes also used for 13258 * other purposes, such as identifying during tx completions which peer 13259 * the tx frames in question were transmitted to. 13260 * 13261 * The peer map v2 message also contains a HW peer ID. This HW peer ID 13262 * is used during rx --> tx frame forwarding to identify which peer the 13263 * frame needs to be forwarded to (i.e. the peer associated with the 13264 * Destination MAC Address within the packet), and particularly which vdev 13265 * needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding). 13266 * This DA-based peer ID that is provided for certain rx frames 13267 * (the rx frames that need to be re-transmitted as tx frames) 13268 * is the ID that the HW uses for referring to the peer in question, 13269 * rather than the peer ID that the SW+FW use to refer to the peer. 13270 * 13271 * The HW peer id here is the same meaning as AST_INDEX_0. 13272 * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1, 13273 * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through 13274 * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension 13275 * AST is valid. 13276 * 13277 * |31 28|27 24|23 21|20|19 17|16|15 8|7 0| 13278 * |-------------------------------------------------------------------------| 13279 * | SW peer ID | VDEV ID | msg type | 13280 * |-------------------------------------------------------------------------| 13281 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13282 * |-------------------------------------------------------------------------| 13283 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13284 * |-------------------------------------------------------------------------| 13285 * | Reserved_21_31 |OA|ASTVM|NH| AST Hash Value | 13286 * |-------------------------------------------------------------------------| 13287 * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 | 13288 * |-------------------------------------------------------------------------| 13289 * |TID valid low pri| TID valid hi pri | AST index 2 | 13290 * |-------------------------------------------------------------------------| 13291 * | LMAC/PMAC_RXPCU AST index | AST index 3 | 13292 * |-------------------------------------------------------------------------| 13293 * | Reserved_2 | 13294 * |-------------------------------------------------------------------------| 13295 * Where: 13296 * NH = Next Hop 13297 * ASTVM = AST valid mask 13298 * OA = on-chip AST valid bit 13299 * ASTFM = AST flow mask 13300 * 13301 * The following field definitions describe the format of the rx peer map v2 13302 * messages sent from the target to the host. 13303 * - MSG_TYPE 13304 * Bits 7:0 13305 * Purpose: identifies this as an rx peer map v2 message 13306 * Value: peer map v2 -> 0x1e (HTT_T2H_MSG_TYPE_PEER_MAP_V2) 13307 * - VDEV_ID 13308 * Bits 15:8 13309 * Purpose: Indicates which virtual device the peer is associated with. 13310 * Value: vdev ID (used in the host to look up the vdev object) 13311 * - SW_PEER_ID 13312 * Bits 31:16 13313 * Purpose: The peer ID (index) that WAL is allocating 13314 * Value: (rx) peer ID 13315 * - MAC_ADDR_L32 13316 * Bits 31:0 13317 * Purpose: Identifies which peer node the peer ID is for. 13318 * Value: lower 4 bytes of peer node's MAC address 13319 * - MAC_ADDR_U16 13320 * Bits 15:0 13321 * Purpose: Identifies which peer node the peer ID is for. 13322 * Value: upper 2 bytes of peer node's MAC address 13323 * - HW_PEER_ID / AST_INDEX_0 13324 * Bits 31:16 13325 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13326 * address, so for rx frames marked for rx --> tx forwarding, the 13327 * host can determine from the HW peer ID provided as meta-data with 13328 * the rx frame which peer the frame is supposed to be forwarded to. 13329 * Value: ID used by the MAC HW to identify the peer 13330 * - AST_HASH_VALUE 13331 * Bits 15:0 13332 * Purpose: Indicates AST Hash value is required for the TCL AST index 13333 * override feature. 13334 * - NEXT_HOP 13335 * Bit 16 13336 * Purpose: Bit indicates that a next_hop AST entry is used for WDS 13337 * (Wireless Distribution System). 13338 * - AST_VALID_MASK 13339 * Bits 19:17 13340 * Purpose: Indicate if the AST 1 through AST 3 are valid 13341 * - ONCHIP_AST_VALID_FLAG 13342 * Bit 20 13343 * Purpose: Indicate if the on-chip AST index field (ONCHIP_AST_IDX) 13344 * is valid. 13345 * - AST_INDEX_1 13346 * Bits 15:0 13347 * Purpose: indicate the second AST index for this peer 13348 * - AST_0_FLOW_MASK 13349 * Bits 19:16 13350 * Purpose: identify the which flow the AST 0 entry corresponds to. 13351 * - AST_1_FLOW_MASK 13352 * Bits 23:20 13353 * Purpose: identify the which flow the AST 1 entry corresponds to. 13354 * - AST_2_FLOW_MASK 13355 * Bits 27:24 13356 * Purpose: identify the which flow the AST 2 entry corresponds to. 13357 * - AST_3_FLOW_MASK 13358 * Bits 31:28 13359 * Purpose: identify the which flow the AST 3 entry corresponds to. 13360 * - AST_INDEX_2 13361 * Bits 15:0 13362 * Purpose: indicate the third AST index for this peer 13363 * - TID_VALID_HI_PRI 13364 * Bits 23:16 13365 * Purpose: identify if this peer's TIDs 0-7 support HI priority flow 13366 * - TID_VALID_LOW_PRI 13367 * Bits 31:24 13368 * Purpose: identify if this peer's TIDs 0-7 support Low priority flow 13369 * - AST_INDEX_3 13370 * Bits 15:0 13371 * Purpose: indicate the fourth AST index for this peer 13372 * - ONCHIP_AST_IDX / RESERVED 13373 * Bits 31:16 13374 * Purpose: This field is valid only when split AST feature is enabled. 13375 * The ONCHIP_AST_VALID_FLAG identifies whether this field is valid. 13376 * If valid, identifies the HW peer ID corresponding to the peer MAC 13377 * address, this ast_idx is used for LMAC modules for RXPCU. 13378 * Value: ID used by the LMAC HW to identify the peer 13379 */ 13380 #define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00 13381 #define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8 13382 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 0xffff0000 13383 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 16 13384 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 0xffffffff 13385 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 0 13386 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 0xffff 13387 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 0 13388 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_M 0xffff0000 13389 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_S 16 13390 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M 0x0000ffff 13391 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0 13392 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000 13393 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16 13394 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000 13395 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17 13396 13397 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M 0x00100000 13398 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S 20 13399 13400 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff 13401 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0 13402 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000 13403 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16 13404 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000 13405 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20 13406 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000 13407 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24 13408 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000 13409 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28 13410 13411 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff 13412 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0 13413 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000 13414 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16 13415 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000 13416 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24 13417 13418 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff 13419 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0 13420 13421 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M 0xffff0000 13422 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S 16 13423 13424 #define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \ 13425 do { \ 13426 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_VDEV_ID, value); \ 13427 (word) |= (value) << HTT_RX_PEER_MAP_V2_VDEV_ID_S; \ 13428 } while (0) 13429 #define HTT_RX_PEER_MAP_V2_VDEV_ID_GET(word) \ 13430 (((word) & HTT_RX_PEER_MAP_V2_VDEV_ID_M) >> HTT_RX_PEER_MAP_V2_VDEV_ID_S) 13431 13432 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET(word, value) \ 13433 do { \ 13434 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_SW_PEER_ID, value); \ 13435 (word) |= (value) << HTT_RX_PEER_MAP_V2_SW_PEER_ID_S; \ 13436 } while (0) 13437 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET(word) \ 13438 (((word) & HTT_RX_PEER_MAP_V2_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_SW_PEER_ID_S) 13439 13440 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_SET(word, value) \ 13441 do { \ 13442 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_HW_PEER_ID, value); \ 13443 (word) |= (value) << HTT_RX_PEER_MAP_V2_HW_PEER_ID_S; \ 13444 } while (0) 13445 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_GET(word) \ 13446 (((word) & HTT_RX_PEER_MAP_V2_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_HW_PEER_ID_S) 13447 13448 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_SET(word, value) \ 13449 do { \ 13450 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_HASH_VALUE, value); \ 13451 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S; \ 13452 } while (0) 13453 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_GET(word) \ 13454 (((word) & HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S) 13455 13456 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_SET(word, value) \ 13457 do { \ 13458 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M, value); \ 13459 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S; \ 13460 } while (0) 13461 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_GET(word) \ 13462 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S) 13463 13464 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_SET(word, value) \ 13465 do { \ 13466 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_NEXT_HOP, value); \ 13467 (word) |= (value) << HTT_RX_PEER_MAP_V2_NEXT_HOP_S; \ 13468 } while (0) 13469 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \ 13470 (((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S) 13471 13472 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \ 13473 do { \ 13474 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \ 13475 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \ 13476 } while (0) 13477 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \ 13478 (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S) 13479 13480 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 13481 do { \ 13482 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M, value); \ 13483 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S; \ 13484 } while (0) 13485 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_MASK_GET(word) \ 13486 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S) 13487 13488 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \ 13489 do { \ 13490 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \ 13491 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \ 13492 } while (0) 13493 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \ 13494 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S) 13495 13496 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \ 13497 do { \ 13498 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \ 13499 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \ 13500 } while (0) 13501 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \ 13502 (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S) 13503 13504 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \ 13505 do { \ 13506 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \ 13507 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \ 13508 } while (0) 13509 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \ 13510 (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S) 13511 13512 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \ 13513 do { \ 13514 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \ 13515 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \ 13516 } while (0) 13517 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \ 13518 (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S) 13519 13520 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \ 13521 do { \ 13522 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \ 13523 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \ 13524 } while (0) 13525 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \ 13526 (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S) 13527 13528 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \ 13529 do { \ 13530 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \ 13531 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \ 13532 } while (0) 13533 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \ 13534 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S) 13535 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \ 13536 do { \ 13537 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \ 13538 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \ 13539 } while (0) 13540 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \ 13541 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S) 13542 13543 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \ 13544 do { \ 13545 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \ 13546 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \ 13547 } while (0) 13548 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \ 13549 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S) 13550 13551 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \ 13552 do { \ 13553 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \ 13554 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \ 13555 } while (0) 13556 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \ 13557 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S) 13558 13559 13560 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 13561 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */ 13562 #define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */ 13563 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */ 13564 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */ 13565 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */ 13566 #define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */ 13567 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */ 13568 #define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */ 13569 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */ 13570 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */ 13571 13572 #define HTT_RX_PEER_MAP_V2_BYTES 32 13573 13574 /** 13575 * @brief target -> host rx peer map V3 message definition 13576 * 13577 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V3 13578 * 13579 * @details 13580 * The following diagram shows the format of the rx peer map v3 message sent 13581 * from the target to the host. 13582 * Format inherits HTT_T2H_MSG_TYPE_PEER_MAP_V2 published above 13583 * This layout assumes the target operates as little-endian. 13584 * 13585 * |31 24|23 20|19|18|17|16|15 8|7 0| 13586 * |-----------------+--------+--+--+--+--+-----------------+-----------------| 13587 * | SW peer ID | VDEV ID | msg type | 13588 * |-----------------+--------------------+-----------------+-----------------| 13589 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13590 * |-----------------+--------------------+-----------------+-----------------| 13591 * | Multicast SW peer ID | MAC addr 5 | MAC addr 4 | 13592 * |-----------------+--------+-----------+-----------------+-----------------| 13593 * | HTT_MSDU_IDX_ |RESERVED| CACHE_ | | 13594 * | VALID_MASK |(4bits) | SET_NUM | HW peer ID / AST index | 13595 * | (8bits) | | (4bits) | | 13596 * |-----------------+--------+--+--+--+--------------------------------------| 13597 * | RESERVED |E |O | | | 13598 * | (13bits) |A |A |NH| on-Chip PMAC_RXPCU AST index | 13599 * | |V |V | | | 13600 * |-----------------+--------------------+-----------------------------------| 13601 * | HTT_MSDU_IDX_ | RESERVED | | 13602 * | VALID_MASK_EXT | (8bits) | EXT AST index | 13603 * | (8bits) | | | 13604 * |-----------------+--------------------+-----------------------------------| 13605 * | Reserved_2 | 13606 * |--------------------------------------------------------------------------| 13607 * | Reserved_3 | 13608 * |--------------------------------------------------------------------------| 13609 * 13610 * Where: 13611 * EAV = EXT_AST_VALID flag, for "EXT AST index" 13612 * OAV = ONCHIP_AST_VALID flag, for "on-Chip PMAC_RXPCU AST index" 13613 * NH = Next Hop 13614 * The following field definitions describe the format of the rx peer map v3 13615 * messages sent from the target to the host. 13616 * - MSG_TYPE 13617 * Bits 7:0 13618 * Purpose: identifies this as a peer map v3 message 13619 * Value: 0x2b (HTT_T2H_MSG_TYPE_PEER_MAP_V3) 13620 * - VDEV_ID 13621 * Bits 15:8 13622 * Purpose: Indicates which virtual device the peer is associated with. 13623 * - SW_PEER_ID 13624 * Bits 31:16 13625 * Purpose: The peer ID (index) that WAL has allocated for this peer. 13626 * - MAC_ADDR_L32 13627 * Bits 31:0 13628 * Purpose: Identifies which peer node the peer ID is for. 13629 * Value: lower 4 bytes of peer node's MAC address 13630 * - MAC_ADDR_U16 13631 * Bits 15:0 13632 * Purpose: Identifies which peer node the peer ID is for. 13633 * Value: upper 2 bytes of peer node's MAC address 13634 * - MULTICAST_SW_PEER_ID 13635 * Bits 31:16 13636 * Purpose: The multicast peer ID (index) 13637 * Value: set to HTT_INVALID_PEER if not valid 13638 * - HW_PEER_ID / AST_INDEX 13639 * Bits 15:0 13640 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13641 * address, so for rx frames marked for rx --> tx forwarding, the 13642 * host can determine from the HW peer ID provided as meta-data with 13643 * the rx frame which peer the frame is supposed to be forwarded to. 13644 * - CACHE_SET_NUM 13645 * Bits 19:16 13646 * Purpose: Cache Set Number for AST_INDEX 13647 * Cache set number that should be used to cache the index based 13648 * search results, for address and flow search. 13649 * This value should be equal to LSB 4 bits of the hash value 13650 * of match data, in case of search index points to an entry which 13651 * may be used in content based search also. The value can be 13652 * anything when the entry pointed by search index will not be 13653 * used for content based search. 13654 * - HTT_MSDU_IDX_VALID_MASK 13655 * Bits 31:24 13656 * Purpose: Shows MSDU indexes valid mask for AST_INDEX 13657 * - ONCHIP_AST_IDX / RESERVED 13658 * Bits 15:0 13659 * Purpose: This field is valid only when split AST feature is enabled. 13660 * The ONCHIP_AST_VALID flag identifies whether this field is valid. 13661 * If valid, identifies the HW peer ID corresponding to the peer MAC 13662 * address, this ast_idx is used for LMAC modules for RXPCU. 13663 * - NEXT_HOP 13664 * Bits 16 13665 * Purpose: Flag indicates next_hop AST entry used for WDS 13666 * (Wireless Distribution System). 13667 * - ONCHIP_AST_VALID 13668 * Bits 17 13669 * Purpose: Flag indicates valid data behind of the ONCHIP_AST_IDX field 13670 * - EXT_AST_VALID 13671 * Bits 18 13672 * Purpose: Flag indicates valid data behind of the EXT_AST_INDEX field 13673 * - EXT_AST_INDEX 13674 * Bits 15:0 13675 * Purpose: This field describes Extended AST index 13676 * Valid if EXT_AST_VALID flag set 13677 * - HTT_MSDU_IDX_VALID_MASK_EXT 13678 * Bits 31:24 13679 * Purpose: Shows MSDU indexes valid mask for EXT_AST_INDEX 13680 */ 13681 /* dword 0 */ 13682 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_M 0xffff0000 13683 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_S 16 13684 #define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00 13685 #define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8 13686 /* dword 1 */ 13687 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_M 0xffffffff 13688 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_S 0 13689 /* dword 2 */ 13690 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_M 0x0000ffff 13691 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_S 0 13692 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M 0xffff0000 13693 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S 16 13694 /* dword 3 */ 13695 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M 0xff000000 13696 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S 24 13697 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000 13698 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16 13699 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff 13700 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0 13701 /* dword 4 */ 13702 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000 13703 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18 13704 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000 13705 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17 13706 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000 13707 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16 13708 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff 13709 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0 13710 /* dword 5 */ 13711 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M 0xff000000 13712 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S 24 13713 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff 13714 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0 13715 13716 #define HTT_RX_PEER_MAP_V3_VDEV_ID_SET(word, value) \ 13717 do { \ 13718 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_VDEV_ID, value); \ 13719 (word) |= (value) << HTT_RX_PEER_MAP_V3_VDEV_ID_S; \ 13720 } while (0) 13721 #define HTT_RX_PEER_MAP_V3_VDEV_ID_GET(word) \ 13722 (((word) & HTT_RX_PEER_MAP_V3_VDEV_ID_M) >> HTT_RX_PEER_MAP_V3_VDEV_ID_S) 13723 13724 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_SET(word, value) \ 13725 do { \ 13726 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_SW_PEER_ID, value); \ 13727 (word) |= (value) << HTT_RX_PEER_MAP_V3_SW_PEER_ID_S; \ 13728 } while (0) 13729 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_GET(word) \ 13730 (((word) & HTT_RX_PEER_MAP_V3_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_SW_PEER_ID_S) 13731 13732 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_SET(word, value) \ 13733 do { \ 13734 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID, value); \ 13735 (word) |= (value) << HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S; \ 13736 } while (0) 13737 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_GET(word) \ 13738 (((word) & HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S) 13739 13740 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_SET(word, value) \ 13741 do { \ 13742 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_HW_PEER_ID, value); \ 13743 (word) |= (value) << HTT_RX_PEER_MAP_V3_HW_PEER_ID_S; \ 13744 } while (0) 13745 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_GET(word) \ 13746 (((word) & HTT_RX_PEER_MAP_V3_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_HW_PEER_ID_S) 13747 13748 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_SET(word, value) \ 13749 do { \ 13750 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CACHE_SET_NUM, value); \ 13751 (word) |= (value) << HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S; \ 13752 } while (0) 13753 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_GET(word) \ 13754 (((word) & HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M) >> HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S) 13755 13756 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_SET(word, value) \ 13757 do { \ 13758 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST, value); \ 13759 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S; \ 13760 } while (0) 13761 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_GET(word) \ 13762 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S) 13763 13764 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_SET(word, value) \ 13765 do { \ 13766 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX, value); \ 13767 (word) |= (value) << HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S; \ 13768 } while (0) 13769 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_GET(word) \ 13770 (((word) & HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S) 13771 13772 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_SET(word, value) \ 13773 do { \ 13774 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_NEXT_HOP, value); \ 13775 (word) |= (value) << HTT_RX_PEER_MAP_V3_NEXT_HOP_S; \ 13776 } while (0) 13777 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_GET(word) \ 13778 (((word) & HTT_RX_PEER_MAP_V3_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V3_NEXT_HOP_S) 13779 13780 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 13781 do { \ 13782 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG, value); \ 13783 (word) |= (value) << HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S; \ 13784 } while (0) 13785 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_GET(word) \ 13786 (((word) & HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S) 13787 13788 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_SET(word, value) \ 13789 do { \ 13790 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG, value); \ 13791 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S; \ 13792 } while (0) 13793 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_GET(word) \ 13794 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S) 13795 13796 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_SET(word, value) \ 13797 do { \ 13798 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_IDX, value); \ 13799 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S; \ 13800 } while (0) 13801 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_GET(word) \ 13802 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S) 13803 13804 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_SET(word, value) \ 13805 do { \ 13806 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST, value); \ 13807 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S; \ 13808 } while (0) 13809 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_GET(word) \ 13810 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S) 13811 13812 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */ 13813 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */ 13814 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */ 13815 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */ 13816 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */ 13817 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */ 13818 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */ 13819 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */ 13820 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */ 13821 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */ 13822 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */ 13823 13824 #define HTT_RX_PEER_MAP_V3_BYTES 32 13825 13826 /** 13827 * @brief target -> host rx peer unmap V2 message definition 13828 * 13829 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 13830 * 13831 * The following diagram shows the format of the rx peer unmap message sent 13832 * from the target to the host. 13833 * 13834 * |31 24|23 16|15 8|7 0| 13835 * |-----------------------------------------------------------------------| 13836 * | SW peer ID | VDEV ID | msg type | 13837 * |-----------------------------------------------------------------------| 13838 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13839 * |-----------------------------------------------------------------------| 13840 * | Reserved_17_31 | Next Hop | MAC addr 5 | MAC addr 4 | 13841 * |-----------------------------------------------------------------------| 13842 * | Peer Delete Duration | 13843 * |-----------------------------------------------------------------------| 13844 * | Reserved_0 | WDS Free Count | 13845 * |-----------------------------------------------------------------------| 13846 * | Reserved_1 | 13847 * |-----------------------------------------------------------------------| 13848 * | Reserved_2 | 13849 * |-----------------------------------------------------------------------| 13850 * 13851 * 13852 * The following field definitions describe the format of the rx peer unmap 13853 * messages sent from the target to the host. 13854 * - MSG_TYPE 13855 * Bits 7:0 13856 * Purpose: identifies this as an rx peer unmap v2 message 13857 * Value: peer unmap v2 -> 0x1f (HTT_T2H_MSG_TYPE_PEER_UNMAP_V2) 13858 * - VDEV_ID 13859 * Bits 15:8 13860 * Purpose: Indicates which virtual device the peer is associated 13861 * with. 13862 * Value: vdev ID (used in the host to look up the vdev object) 13863 * - SW_PEER_ID 13864 * Bits 31:16 13865 * Purpose: The peer ID (index) that WAL is freeing 13866 * Value: (rx) peer ID 13867 * - MAC_ADDR_L32 13868 * Bits 31:0 13869 * Purpose: Identifies which peer node the peer ID is for. 13870 * Value: lower 4 bytes of peer node's MAC address 13871 * - MAC_ADDR_U16 13872 * Bits 15:0 13873 * Purpose: Identifies which peer node the peer ID is for. 13874 * Value: upper 2 bytes of peer node's MAC address 13875 * - NEXT_HOP 13876 * Bits 16 13877 * Purpose: Bit indicates next_hop AST entry used for WDS 13878 * (Wireless Distribution System). 13879 * - PEER_DELETE_DURATION 13880 * Bits 31:0 13881 * Purpose: Time taken to delete peer, in msec, 13882 * Used for monitoring / debugging PEER delete response delay 13883 * - PEER_WDS_FREE_COUNT 13884 * Bits 15:0 13885 * Purpose: Count of WDS entries deleted associated to peer deleted 13886 */ 13887 13888 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_M HTT_RX_PEER_MAP_V2_VDEV_ID_M 13889 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_S HTT_RX_PEER_MAP_V2_VDEV_ID_S 13890 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_M HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 13891 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_S HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 13892 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_M HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 13893 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_S HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 13894 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_M HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 13895 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_S HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 13896 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_M HTT_RX_PEER_MAP_V2_NEXT_HOP_M 13897 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_S HTT_RX_PEER_MAP_V2_NEXT_HOP_S 13898 13899 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M 0xffffffff 13900 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S 0 13901 13902 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M 0x0000ffff 13903 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S 0 13904 13905 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_SET HTT_RX_PEER_MAP_V2_VDEV_ID_SET 13906 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_GET HTT_RX_PEER_MAP_V2_VDEV_ID_GET 13907 13908 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_SET HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET 13909 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_GET HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET 13910 13911 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_SET HTT_RX_PEER_MAP_V2_NEXT_HOP_SET 13912 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_GET HTT_RX_PEER_MAP_V2_NEXT_HOP_GET 13913 13914 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_SET(word, value) \ 13915 do { \ 13916 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION, value); \ 13917 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S; \ 13918 } while (0) 13919 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_GET(word) \ 13920 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M) >> HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S) 13921 13922 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_SET(word, value) \ 13923 do { \ 13924 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT, value); \ 13925 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S; \ 13926 } while (0) 13927 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_GET(word) \ 13928 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M) >> HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S) 13929 13930 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 13931 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_OFFSET 8 /* bytes */ 13932 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_OFFSET 12 /* bytes */ 13933 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_OFFSET 16 /* bytes */ 13934 13935 #define HTT_RX_PEER_UNMAP_V2_BYTES 28 13936 13937 /** 13938 * @brief target -> host rx peer mlo map message definition 13939 * 13940 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP 13941 * 13942 * @details 13943 * The following diagram shows the format of the rx mlo peer map message sent 13944 * from the target to the host. This layout assumes the target operates 13945 * as little-endian. 13946 * 13947 * MCC: 13948 * One HTT_MLO_PEER_MAP is sent after PEER_ASSOC received on first LINK for both STA and SAP. 13949 * 13950 * WIN: 13951 * One HTT_MLO_PEER_MAP is sent after peers are created on all the links for both AP and STA. 13952 * It will be sent on the Assoc Link. 13953 * 13954 * This message always contains a MLO peer ID. The main purpose of the 13955 * MLO peer ID is to tell the host what peer ID rx packets will be tagged 13956 * with, so that the host can use that MLO peer ID to determine which peer 13957 * transmitted the rx frame. 13958 * 13959 * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0| 13960 * |-------------------------------------------------------------------------| 13961 * |RSVD | PRC |NUMLINK| MLO peer ID | msg type | 13962 * |-------------------------------------------------------------------------| 13963 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13964 * |-------------------------------------------------------------------------| 13965 * | RSVD_16_31 | MAC addr 5 | MAC addr 4 | 13966 * |-------------------------------------------------------------------------| 13967 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | 13968 * |-------------------------------------------------------------------------| 13969 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | 13970 * |-------------------------------------------------------------------------| 13971 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | 13972 * |-------------------------------------------------------------------------| 13973 * |RSVD | 13974 * |-------------------------------------------------------------------------| 13975 * |RSVD | 13976 * |-------------------------------------------------------------------------| 13977 * | htt_tlv_hdr_t | 13978 * |-------------------------------------------------------------------------| 13979 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13980 * |-------------------------------------------------------------------------| 13981 * | htt_tlv_hdr_t | 13982 * |-------------------------------------------------------------------------| 13983 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13984 * |-------------------------------------------------------------------------| 13985 * | htt_tlv_hdr_t | 13986 * |-------------------------------------------------------------------------| 13987 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13988 * |-------------------------------------------------------------------------| 13989 * 13990 * Where: 13991 * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26 13992 * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29 13993 * V (valid) - 1 Bit Bit17 13994 * CHIPID - 3 Bits 13995 * TIDMASK - 8 Bits 13996 * CACHE_SET_NUM - 8 Bits 13997 * 13998 * The following field definitions describe the format of the rx MLO peer map 13999 * messages sent from the target to the host. 14000 * - MSG_TYPE 14001 * Bits 7:0 14002 * Purpose: identifies this as an rx mlo peer map message 14003 * Value: 0x29 (HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP) 14004 * 14005 * - MLO_PEER_ID 14006 * Bits 23:8 14007 * Purpose: The MLO peer ID (index). 14008 * For MCC, FW will allocate it. For WIN, Host will allocate it. 14009 * Value: MLO peer ID 14010 * 14011 * - NUMLINK 14012 * Bits: 26:24 (3Bits) 14013 * Purpose: Indicate the max number of logical links supported per client. 14014 * Value: number of logical links 14015 * 14016 * - PRC 14017 * Bits: 29:27 (3Bits) 14018 * Purpose: Indicate the Primary REO CHIPID. The ID can be used to indicate 14019 * if there is migration of the primary chip. 14020 * Value: Primary REO CHIPID 14021 * 14022 * - MAC_ADDR_L32 14023 * Bits 31:0 14024 * Purpose: Identifies which mlo peer node the mlo peer ID is for. 14025 * Value: lower 4 bytes of peer node's MAC address 14026 * 14027 * - MAC_ADDR_U16 14028 * Bits 15:0 14029 * Purpose: Identifies which peer node the peer ID is for. 14030 * Value: upper 2 bytes of peer node's MAC address 14031 * 14032 * - PRIMARY_TCL_AST_IDX 14033 * Bits 15:0 14034 * Purpose: Primary TCL AST index for this peer. 14035 * 14036 * - V 14037 * 1 Bit Position 16 14038 * Purpose: If the ast idx is valid. 14039 * 14040 * - CHIPID 14041 * Bits 19:17 14042 * Purpose: Identifies which chip id of PRIMARY_TCL_AST_IDX 14043 * 14044 * - TIDMASK 14045 * Bits 27:20 14046 * Purpose: LINK to TID mapping for PRIMARY_TCL_AST_IDX 14047 * 14048 * - CACHE_SET_NUM 14049 * Bits 31:28 14050 * Purpose: Cache Set Number for PRIMARY_TCL_AST_IDX 14051 * Cache set number that should be used to cache the index based 14052 * search results, for address and flow search. 14053 * This value should be equal to LSB four bits of the hash value 14054 * of match data, in case of search index points to an entry which 14055 * may be used in content based search also. The value can be 14056 * anything when the entry pointed by search index will not be 14057 * used for content based search. 14058 * 14059 * - htt_tlv_hdr_t 14060 * Purpose: Provide link specific chip,vdev and sw_peer IDs 14061 * 14062 * Bits 11:0 14063 * Purpose: tag equal to MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS. 14064 * 14065 * Bits 23:12 14066 * Purpose: Length, Length of the value that follows the header 14067 * 14068 * Bits 31:28 14069 * Purpose: Reserved. 14070 * 14071 * 14072 * - SW_PEER_ID 14073 * Bits 15:0 14074 * Purpose: The peer ID (index) that WAL is allocating 14075 * Value: (rx) peer ID 14076 * 14077 * - VDEV_ID 14078 * Bits 23:16 14079 * Purpose: Indicates which virtual device the peer is associated with. 14080 * Value: vdev ID (used in the host to look up the vdev object) 14081 * 14082 * - CHIPID 14083 * Bits 26:24 14084 * Purpose: Indicates which Chip id the peer is associated with. 14085 * Value: chip ID (Provided by Host as part of QMI exchange) 14086 */ 14087 typedef enum { 14088 MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS, 14089 } MLO_PEER_MAP_TLV_TAG_ID; 14090 14091 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 0x00ffff00 14092 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 8 14093 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M 0x07000000 14094 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S 24 14095 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M 0x38000000 14096 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S 27 14097 14098 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 14099 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_S 0 14100 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff 14101 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0 14102 14103 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff 14104 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0 14105 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000 14106 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S 16 14107 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M 0x000E0000 14108 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S 17 14109 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M 0x00F00000 14110 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S 20 14111 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M 0xF0000000 14112 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S 28 14113 14114 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_M 0x00000fff 14115 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_S 0 14116 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M 0x00fff000 14117 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S 12 14118 14119 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M 0x0000ffff 14120 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S 0 14121 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_M 0x00ff0000 14122 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_S 16 14123 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_M 0x07000000 14124 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_S 24 14125 14126 14127 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET(word, value) \ 14128 do { \ 14129 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_MLO_PEER_ID, value); \ 14130 (word) |= (value) << HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S; \ 14131 } while (0) 14132 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET(word) \ 14133 (((word) & HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S) 14134 14135 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_SET(word, value) \ 14136 do { \ 14137 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS, value); \ 14138 (word) |= (value) << HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S; \ 14139 } while (0) 14140 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_GET(word) \ 14141 (((word) & HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M) >> HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S) 14142 14143 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \ 14144 do { \ 14145 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \ 14146 (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \ 14147 } while (0) 14148 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ 14149 (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) 14150 14151 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \ 14152 do { \ 14153 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \ 14154 (word) |= (value) << HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S; \ 14155 } while (0) 14156 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_GET(word) \ 14157 (((word) & HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S) 14158 14159 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_SET(word, value) \ 14160 do { \ 14161 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG, value); \ 14162 (word) |= (value) << HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S; \ 14163 } while (0) 14164 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_GET(word) \ 14165 (((word) & HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S) 14166 14167 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_SET(word, value) \ 14168 do { \ 14169 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX, value); \ 14170 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S; \ 14171 } while (0) 14172 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_GET(word) \ 14173 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S) 14174 14175 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_SET(word, value) \ 14176 do { \ 14177 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX, value); \ 14178 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S; \ 14179 } while (0) 14180 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_GET(word) \ 14181 (((word) & HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S) 14182 14183 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_SET(word, value) \ 14184 do { \ 14185 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX, value); \ 14186 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S; \ 14187 } while (0) 14188 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_GET(word) \ 14189 (((word) & HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S) 14190 14191 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_SET(word, value) \ 14192 do { \ 14193 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_TAG, value); \ 14194 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_TAG_S; \ 14195 } while (0) 14196 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_GET(word) \ 14197 (((word) & HTT_RX_MLO_PEER_MAP_TLV_TAG_M) >> HTT_RX_MLO_PEER_MAP_TLV_TAG_S) 14198 14199 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_SET(word, value) \ 14200 do { \ 14201 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_LENGTH, value); \ 14202 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S; \ 14203 } while (0) 14204 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_GET(word) \ 14205 (((word) & HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M) >> HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S) 14206 14207 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_SET(word, value) \ 14208 do { \ 14209 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_SW_PEER_ID, value); \ 14210 (word) |= (value) << HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S; \ 14211 } while (0) 14212 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_GET(word) \ 14213 (((word) & HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S) 14214 14215 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_SET(word, value) \ 14216 do { \ 14217 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_VDEV_ID, value); \ 14218 (word) |= (value) << HTT_RX_MLO_PEER_MAP_VDEV_ID_S; \ 14219 } while (0) 14220 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_GET(word) \ 14221 (((word) & HTT_RX_MLO_PEER_MAP_VDEV_ID_M) >> HTT_RX_MLO_PEER_MAP_VDEV_ID_S) 14222 14223 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_SET(word, value) \ 14224 do { \ 14225 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID, value); \ 14226 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_S; \ 14227 } while (0) 14228 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_GET(word) \ 14229 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_S) 14230 14231 14232 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 14233 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */ 14234 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */ 14235 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */ 14236 #define HTT_RX_MLO_PEER_MAP_TLV_OFFSET 32 /* bytes */ 14237 14238 #define HTT_RX_MLO_PEER_MAP_FIXED_BYTES 8*4 /* 8 Dwords. Does not include the TLV header and the TLV */ 14239 14240 14241 /* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP 14242 * 14243 * The following diagram shows the format of the rx mlo peer unmap message sent 14244 * from the target to the host. 14245 * 14246 * |31 24|23 16|15 8|7 0| 14247 * |-----------------------------------------------------------------------| 14248 * | RSVD_24_31 | MLO peer ID | msg type | 14249 * |-----------------------------------------------------------------------| 14250 */ 14251 14252 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_M HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 14253 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_S HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 14254 14255 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET 14256 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET 14257 14258 /** 14259 * @brief target -> host peer extended event for additional information 14260 * 14261 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT 14262 * 14263 * @details 14264 * The following diagram shows the format of the peer extended message sent 14265 * from the target to the host. This layout assumes the target operates 14266 * as little-endian. 14267 * 14268 * This message always contains a SW peer ID. The main purpose of the 14269 * SW peer ID is to tell the host what peer ID logical link id will be tagged 14270 * with, so that the host can use that peer ID to determine which link 14271 * transmitted the rx/tx frame. 14272 * 14273 * This message also contains MLO logical link id assigned to peer 14274 * with sw_peer_id if it is valid ML link peer. 14275 * 14276 * 14277 * |31 28|27 24|23 20|19|18 16|15 8|7 0| 14278 * |---------------------------------------------------------------------------| 14279 * | VDEV_ID | SW peer ID | msg type | 14280 * |---------------------------------------------------------------------------| 14281 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14282 * |---------------------------------------------------------------------------| 14283 * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 | 14284 * |---------------------------------------------------------------------------| 14285 * | Reserved | 14286 * |---------------------------------------------------------------------------| 14287 * | Reserved | 14288 * |---------------------------------------------------------------------------| 14289 * 14290 * Where: 14291 * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte 14292 * V (valid) - 1 Bit Bit19 of 3rd byte 14293 * 14294 * The following field definitions describe the format of the rx peer extended 14295 * event messages sent from the target to the host. 14296 * MSG_TYPE 14297 * Bits 7:0 14298 * Purpose: identifies this as an rx MLO peer extended information message 14299 * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT) 14300 * - PEER_ID (a.k.a. SW_PEER_ID) 14301 * Bits 8:23 14302 * Purpose: The peer ID (index) that WAL has allocated 14303 * Value: (rx) peer ID 14304 * - VDEV_ID 14305 * Bits 24:31 14306 * Purpose: Gives the vdev id of peer with peer_id as above. 14307 * Value: VDEV ID of wal_peer 14308 * 14309 * - MAC_ADDR_L32 14310 * Bits 31:0 14311 * Purpose: Identifies which peer node the peer ID is for. 14312 * Value: lower 4 bytes of peer node's MAC address 14313 * 14314 * - MAC_ADDR_U16 14315 * Bits 15:0 14316 * Purpose: Identifies which peer node the peer ID is for. 14317 * Value: upper 2 bytes of peer node's MAC address 14318 * Rest all bits are reserved for future expansion 14319 * - LOGICAL_LINK_ID 14320 * Bits 18:16 14321 * Purpose: Gives the logical link id of peer with peer_id as above. This 14322 * field should be taken alongwith LOGICAL_LINK_ID_VALID 14323 * Value: Logical link id used by wal_peer 14324 * - LOGICAL_LINK_ID_VALID 14325 * Bit 19 14326 * Purpose: Clarifies whether the logical link id of peer with peer_id as 14327 * is valid or not 14328 * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not 14329 */ 14330 #define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00 14331 #define HTT_RX_PEER_EXTENDED_PEER_ID_S 8 14332 #define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000 14333 #define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24 14334 14335 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff 14336 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0 14337 14338 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff 14339 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0 14340 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000 14341 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16 14342 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000 14343 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19 14344 14345 14346 #define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \ 14347 do { \ 14348 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 14349 (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \ 14350 } while (0) 14351 #define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \ 14352 (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S) 14353 14354 #define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \ 14355 do { \ 14356 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \ 14357 (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \ 14358 } while (0) 14359 #define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \ 14360 (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S) 14361 14362 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \ 14363 do { \ 14364 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \ 14365 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \ 14366 } while (0) 14367 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \ 14368 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S) 14369 14370 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \ 14371 do { \ 14372 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \ 14373 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \ 14374 } while (0) 14375 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \ 14376 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S) 14377 14378 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */ 14379 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */ 14380 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */ 14381 14382 #define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */ 14383 14384 /** 14385 * @brief target -> host message specifying security parameters 14386 * 14387 * MSG_TYPE => HTT_T2H_MSG_TYPE_SEC_IND 14388 * 14389 * @details 14390 * The following diagram shows the format of the security specification 14391 * message sent from the target to the host. 14392 * This security specification message tells the host whether a PN check is 14393 * necessary on rx data frames, and if so, how large the PN counter is. 14394 * This message also tells the host about the security processing to apply 14395 * to defragmented rx frames - specifically, whether a Message Integrity 14396 * Check is required, and the Michael key to use. 14397 * 14398 * |31 24|23 16|15|14 8|7 0| 14399 * |-----------------------------------------------------------------------| 14400 * | peer ID | U| security type | msg type | 14401 * |-----------------------------------------------------------------------| 14402 * | Michael Key K0 | 14403 * |-----------------------------------------------------------------------| 14404 * | Michael Key K1 | 14405 * |-----------------------------------------------------------------------| 14406 * | WAPI RSC Low0 | 14407 * |-----------------------------------------------------------------------| 14408 * | WAPI RSC Low1 | 14409 * |-----------------------------------------------------------------------| 14410 * | WAPI RSC Hi0 | 14411 * |-----------------------------------------------------------------------| 14412 * | WAPI RSC Hi1 | 14413 * |-----------------------------------------------------------------------| 14414 * 14415 * The following field definitions describe the format of the security 14416 * indication message sent from the target to the host. 14417 * - MSG_TYPE 14418 * Bits 7:0 14419 * Purpose: identifies this as a security specification message 14420 * Value: 0xb (HTT_T2H_MSG_TYPE_SEC_IND) 14421 * - SEC_TYPE 14422 * Bits 14:8 14423 * Purpose: specifies which type of security applies to the peer 14424 * Value: htt_sec_type enum value 14425 * - UNICAST 14426 * Bit 15 14427 * Purpose: whether this security is applied to unicast or multicast data 14428 * Value: 1 -> unicast, 0 -> multicast 14429 * - PEER_ID 14430 * Bits 31:16 14431 * Purpose: The ID number for the peer the security specification is for 14432 * Value: peer ID 14433 * - MICHAEL_KEY_K0 14434 * Bits 31:0 14435 * Purpose: 4-byte word that forms the 1st half of the TKIP Michael key 14436 * Value: Michael Key K0 (if security type is TKIP) 14437 * - MICHAEL_KEY_K1 14438 * Bits 31:0 14439 * Purpose: 4-byte word that forms the 2nd half of the TKIP Michael key 14440 * Value: Michael Key K1 (if security type is TKIP) 14441 * - WAPI_RSC_LOW0 14442 * Bits 31:0 14443 * Purpose: 4-byte word that forms the 1st quarter of the 16 byte WAPI RSC 14444 * Value: WAPI RSC Low0 (if security type is WAPI) 14445 * - WAPI_RSC_LOW1 14446 * Bits 31:0 14447 * Purpose: 4-byte word that forms the 2nd quarter of the 16 byte WAPI RSC 14448 * Value: WAPI RSC Low1 (if security type is WAPI) 14449 * - WAPI_RSC_HI0 14450 * Bits 31:0 14451 * Purpose: 4-byte word that forms the 3rd quarter of the 16 byte WAPI RSC 14452 * Value: WAPI RSC Hi0 (if security type is WAPI) 14453 * - WAPI_RSC_HI1 14454 * Bits 31:0 14455 * Purpose: 4-byte word that forms the 4th quarter of the 16 byte WAPI RSC 14456 * Value: WAPI RSC Hi1 (if security type is WAPI) 14457 */ 14458 14459 #define HTT_SEC_IND_SEC_TYPE_M 0x00007f00 14460 #define HTT_SEC_IND_SEC_TYPE_S 8 14461 #define HTT_SEC_IND_UNICAST_M 0x00008000 14462 #define HTT_SEC_IND_UNICAST_S 15 14463 #define HTT_SEC_IND_PEER_ID_M 0xffff0000 14464 #define HTT_SEC_IND_PEER_ID_S 16 14465 14466 #define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ 14467 do { \ 14468 HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ 14469 (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ 14470 } while (0) 14471 #define HTT_SEC_IND_SEC_TYPE_GET(word) \ 14472 (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) 14473 14474 #define HTT_SEC_IND_UNICAST_SET(word, value) \ 14475 do { \ 14476 HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ 14477 (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ 14478 } while (0) 14479 #define HTT_SEC_IND_UNICAST_GET(word) \ 14480 (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) 14481 14482 #define HTT_SEC_IND_PEER_ID_SET(word, value) \ 14483 do { \ 14484 HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ 14485 (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ 14486 } while (0) 14487 #define HTT_SEC_IND_PEER_ID_GET(word) \ 14488 (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) 14489 14490 14491 #define HTT_SEC_IND_BYTES 28 14492 14493 14494 /** 14495 * @brief target -> host rx ADDBA / DELBA message definitions 14496 * 14497 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA 14498 * 14499 * @details 14500 * The following diagram shows the format of the rx ADDBA message sent 14501 * from the target to the host: 14502 * 14503 * |31 20|19 16|15 8|7 0| 14504 * |---------------------------------------------------------------------| 14505 * | peer ID | TID | window size | msg type | 14506 * |---------------------------------------------------------------------| 14507 * 14508 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA 14509 * 14510 * The following diagram shows the format of the rx DELBA message sent 14511 * from the target to the host: 14512 * 14513 * |31 20|19 16|15 10|9 8|7 0| 14514 * |---------------------------------------------------------------------| 14515 * | peer ID | TID | window size | IR| msg type | 14516 * |---------------------------------------------------------------------| 14517 * 14518 * The following field definitions describe the format of the rx ADDBA 14519 * and DELBA messages sent from the target to the host. 14520 * - MSG_TYPE 14521 * Bits 7:0 14522 * Purpose: identifies this as an rx ADDBA or DELBA message 14523 * Value: ADDBA -> 0x5 (HTT_T2H_MSG_TYPE_RX_ADDBA), 14524 * DELBA -> 0x6 (HTT_T2H_MSG_TYPE_RX_DELBA) 14525 * - IR (initiator / recipient) 14526 * Bits 9:8 (DELBA only) 14527 * Purpose: specify whether the DELBA handshake was initiated by the 14528 * local STA/AP, or by the peer STA/AP 14529 * Value: 14530 * 0 - unspecified 14531 * 1 - initiator (a.k.a. originator) 14532 * 2 - recipient (a.k.a. responder) 14533 * 3 - unused / reserved 14534 * - WIN_SIZE 14535 * Bits 15:8 for ADDBA, bits 15:10 for DELBA 14536 * Purpose: Specifies the length of the block ack window (max = 64). 14537 * Value: 14538 * block ack window length specified by the received ADDBA/DELBA 14539 * management message. 14540 * - TID 14541 * Bits 19:16 14542 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 14543 * Value: 14544 * TID specified by the received ADDBA or DELBA management message. 14545 * - PEER_ID 14546 * Bits 31:20 14547 * Purpose: Identifies which peer sent the ADDBA / DELBA. 14548 * Value: 14549 * ID (hash value) used by the host for fast, direct lookup of 14550 * host SW peer info, including rx reorder states. 14551 */ 14552 #define HTT_RX_ADDBA_WIN_SIZE_M 0xff00 14553 #define HTT_RX_ADDBA_WIN_SIZE_S 8 14554 #define HTT_RX_ADDBA_TID_M 0xf0000 14555 #define HTT_RX_ADDBA_TID_S 16 14556 #define HTT_RX_ADDBA_PEER_ID_M 0xfff00000 14557 #define HTT_RX_ADDBA_PEER_ID_S 20 14558 14559 #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \ 14560 do { \ 14561 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ 14562 (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ 14563 } while (0) 14564 #define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ 14565 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 14566 14567 #define HTT_RX_ADDBA_TID_SET(word, value) \ 14568 do { \ 14569 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ 14570 (word) |= (value) << HTT_RX_ADDBA_TID_S; \ 14571 } while (0) 14572 #define HTT_RX_ADDBA_TID_GET(word) \ 14573 (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) 14574 14575 #define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ 14576 do { \ 14577 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ 14578 (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ 14579 } while (0) 14580 #define HTT_RX_ADDBA_PEER_ID_GET(word) \ 14581 (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) 14582 14583 #define HTT_RX_ADDBA_BYTES 4 14584 14585 14586 #define HTT_RX_DELBA_INITIATOR_M 0x00000300 14587 #define HTT_RX_DELBA_INITIATOR_S 8 14588 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 14589 #define HTT_RX_DELBA_WIN_SIZE_S 10 14590 #define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M 14591 #define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S 14592 #define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M 14593 #define HTT_RX_DELBA_PEER_ID_S HTT_RX_ADDBA_PEER_ID_S 14594 14595 #define HTT_RX_DELBA_TID_SET HTT_RX_ADDBA_TID_SET 14596 #define HTT_RX_DELBA_TID_GET HTT_RX_ADDBA_TID_GET 14597 #define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET 14598 #define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET 14599 14600 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 14601 do { \ 14602 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 14603 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 14604 } while (0) 14605 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 14606 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 14607 14608 #define HTT_RX_DELBA_WIN_SIZE_SET(word, value) \ 14609 do { \ 14610 HTT_CHECK_SET_VAL(HTT_RX_DELBA_WIN_SIZE, value); \ 14611 (word) |= (value) << HTT_RX_DELBA_WIN_SIZE_S; \ 14612 } while (0) 14613 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 14614 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 14615 14616 #define HTT_RX_DELBA_BYTES 4 14617 14618 14619 /** 14620 * @brief target -> host rx ADDBA / DELBA message definitions 14621 * 14622 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN 14623 * 14624 * @details 14625 * The following diagram shows the format of the rx ADDBA extn message sent 14626 * from the target to the host: 14627 * 14628 * |31 20|19 16|15 13|12 8|7 0| 14629 * |---------------------------------------------------------------------| 14630 * | peer ID | TID | reserved | msg type | 14631 * |---------------------------------------------------------------------| 14632 * | reserved | window size | 14633 * |---------------------------------------------------------------------| 14634 * 14635 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA_EXTN 14636 * 14637 * The following diagram shows the format of the rx DELBA message sent 14638 * from the target to the host: 14639 * 14640 * |31 20|19 16|15 13|12 10|9 8|7 0| 14641 * |---------------------------------------------------------------------| 14642 * | peer ID | TID | reserved | IR| msg type | 14643 * |---------------------------------------------------------------------| 14644 * | reserved | window size | 14645 * |---------------------------------------------------------------------| 14646 * 14647 * The following field definitions describe the format of the rx ADDBA 14648 * and DELBA messages sent from the target to the host. 14649 * - MSG_TYPE 14650 * Bits 7:0 14651 * Purpose: identifies this as an rx ADDBA or DELBA message 14652 * Value: ADDBA -> 0x31 (HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN), 14653 * DELBA -> 0x32 (HTT_T2H_MSG_TYPE_RX_DELBA_EXTN) 14654 * - IR (initiator / recipient) 14655 * Bits 9:8 (DELBA only) 14656 * Purpose: specify whether the DELBA handshake was initiated by the 14657 * local STA/AP, or by the peer STA/AP 14658 * Value: 14659 * 0 - unspecified 14660 * 1 - initiator (a.k.a. originator) 14661 * 2 - recipient (a.k.a. responder) 14662 * 3 - unused / reserved 14663 * Value: 14664 * block ack window length specified by the received ADDBA/DELBA 14665 * management message. 14666 * - TID 14667 * Bits 19:16 14668 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 14669 * Value: 14670 * TID specified by the received ADDBA or DELBA management message. 14671 * - PEER_ID 14672 * Bits 31:20 14673 * Purpose: Identifies which peer sent the ADDBA / DELBA. 14674 * Value: 14675 * ID (hash value) used by the host for fast, direct lookup of 14676 * host SW peer info, including rx reorder states. 14677 * == DWORD 1 14678 * - WIN_SIZE 14679 * Bits 12:0 for ADDBA, bits 12:0 for DELBA 14680 * Purpose: Specifies the length of the block ack window (max = 8191). 14681 */ 14682 14683 #define HTT_RX_ADDBA_EXTN_TID_M 0xf0000 14684 #define HTT_RX_ADDBA_EXTN_TID_S 16 14685 #define HTT_RX_ADDBA_EXTN_PEER_ID_M 0xfff00000 14686 #define HTT_RX_ADDBA_EXTN_PEER_ID_S 20 14687 14688 /*--- Dword 0 ---*/ 14689 #define HTT_RX_ADDBA_EXTN_TID_SET(word, value) \ 14690 do { \ 14691 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_TID, value); \ 14692 (word) |= (value) << HTT_RX_ADDBA_EXTN_TID_S; \ 14693 } while (0) 14694 #define HTT_RX_ADDBA_EXTN_TID_GET(word) \ 14695 (((word) & HTT_RX_ADDBA_EXTN_TID_M) >> HTT_RX_ADDBA_EXTN_TID_S) 14696 14697 #define HTT_RX_ADDBA_EXTN_PEER_ID_SET(word, value) \ 14698 do { \ 14699 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_PEER_ID, value); \ 14700 (word) |= (value) << HTT_RX_ADDBA_EXTN_PEER_ID_S; \ 14701 } while (0) 14702 #define HTT_RX_ADDBA_EXTN_PEER_ID_GET(word) \ 14703 (((word) & HTT_RX_ADDBA_EXTN_PEER_ID_M) >> HTT_RX_ADDBA_EXTN_PEER_ID_S) 14704 14705 /*--- Dword 1 ---*/ 14706 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_M 0x1fff 14707 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_S 0 14708 14709 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_SET(word, value) \ 14710 do { \ 14711 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_WIN_SIZE, value); \ 14712 (word) |= (value) << HTT_RX_ADDBA_EXTN_WIN_SIZE_S; \ 14713 } while (0) 14714 14715 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \ 14716 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 14717 14718 #define HTT_RX_ADDBA_EXTN_BYTES 8 14719 14720 14721 #define HTT_RX_DELBA_EXTN_INITIATOR_M 0x00000300 14722 #define HTT_RX_DELBA_EXTN_INITIATOR_S 8 14723 #define HTT_RX_DELBA_EXTN_TID_M 0xf0000 14724 #define HTT_RX_DELBA_EXTN_TID_S 16 14725 #define HTT_RX_DELBA_EXTN_PEER_ID_M 0xfff00000 14726 #define HTT_RX_DELBA_EXTN_PEER_ID_S 20 14727 14728 /*--- Dword 0 ---*/ 14729 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 14730 do { \ 14731 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 14732 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 14733 } while (0) 14734 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 14735 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 14736 14737 #define HTT_RX_DELBA_EXTN_TID_SET(word, value) \ 14738 do { \ 14739 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_TID, value); \ 14740 (word) |= (value) << HTT_RX_DELBA_EXTN_TID_S; \ 14741 } while (0) 14742 #define HTT_RX_DELBA_EXTN_TID_GET(word) \ 14743 (((word) & HTT_RX_DELBA_EXTN_TID_M) >> HTT_RX_DELBA_EXTN_TID_S) 14744 14745 #define HTT_RX_DELBA_EXTN_PEER_ID_SET(word, value) \ 14746 do { \ 14747 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_PEER_ID, value); \ 14748 (word) |= (value) << HTT_RX_DELBA_EXTN_PEER_ID_S; \ 14749 } while (0) 14750 #define HTT_RX_DELBA_EXTN_PEER_ID_GET(word) \ 14751 (((word) & HTT_RX_DELBA_EXTN_PEER_ID_M) >> HTT_RX_DELBA_EXTN_PEER_ID_S) 14752 14753 /*--- Dword 1 ---*/ 14754 #define HTT_RX_DELBA_EXTN_WIN_SIZE_M 0x1fff 14755 #define HTT_RX_DELBA_EXTN_WIN_SIZE_S 0 14756 14757 #define HTT_RX_DELBA_EXTN_WIN_SIZE_SET(word, value) \ 14758 do { \ 14759 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_WIN_SIZE, value); \ 14760 (word) |= (value) << HTT_RX_DELBA_EXTN_WIN_SIZE_S; \ 14761 } while (0) 14762 #define HTT_RX_DELBA_EXTN_WIN_SIZE_GET(word) \ 14763 (((word) & HTT_RX_DELBA_EXTN_WIN_SIZE_M) >> HTT_RX_DELBA_EXTN_WIN_SIZE_S) 14764 14765 #define HTT_RX_DELBA_EXTN_BYTES 8 14766 14767 14768 /** 14769 * @brief tx queue group information element definition 14770 * 14771 * @details 14772 * The following diagram shows the format of the tx queue group 14773 * information element, which can be included in target --> host 14774 * messages to specify the number of tx "credits" (tx descriptors 14775 * for LL, or tx buffers for HL) available to a particular group 14776 * of host-side tx queues, and which host-side tx queues belong to 14777 * the group. 14778 * 14779 * |31|30 24|23 16|15|14|13 0| 14780 * |------------------------------------------------------------------------| 14781 * | X| reserved | tx queue grp ID | A| S| credit count | 14782 * |------------------------------------------------------------------------| 14783 * | vdev ID mask | AC mask | 14784 * |------------------------------------------------------------------------| 14785 * 14786 * The following definitions describe the fields within the tx queue group 14787 * information element: 14788 * - credit_count 14789 * Bits 13:1 14790 * Purpose: specify how many tx credits are available to the tx queue group 14791 * Value: An absolute or relative, positive or negative credit value 14792 * The 'A' bit specifies whether the value is absolute or relative. 14793 * The 'S' bit specifies whether the value is positive or negative. 14794 * A negative value can only be relative, not absolute. 14795 * An absolute value replaces any prior credit value the host has for 14796 * the tx queue group in question. 14797 * A relative value is added to the prior credit value the host has for 14798 * the tx queue group in question. 14799 * - sign 14800 * Bit 14 14801 * Purpose: specify whether the credit count is positive or negative 14802 * Value: 0 -> positive, 1 -> negative 14803 * - absolute 14804 * Bit 15 14805 * Purpose: specify whether the credit count is absolute or relative 14806 * Value: 0 -> relative, 1 -> absolute 14807 * - txq_group_id 14808 * Bits 23:16 14809 * Purpose: indicate which tx queue group's credit and/or membership are 14810 * being specified 14811 * Value: 0 to max_tx_queue_groups-1 14812 * - reserved 14813 * Bits 30:16 14814 * Value: 0x0 14815 * - eXtension 14816 * Bit 31 14817 * Purpose: specify whether another tx queue group info element follows 14818 * Value: 0 -> no more tx queue group information elements 14819 * 1 -> another tx queue group information element immediately follows 14820 * - ac_mask 14821 * Bits 15:0 14822 * Purpose: specify which Access Categories belong to the tx queue group 14823 * Value: bit-OR of masks for the ACs (WMM and extension) that belong to 14824 * the tx queue group. 14825 * The AC bit-mask values are obtained by left-shifting by the 14826 * corresponding HTT_AC_WMM enum values, e.g. (1 << HTT_AC_WMM_BE) == 0x1 14827 * - vdev_id_mask 14828 * Bits 31:16 14829 * Purpose: specify which vdev's tx queues belong to the tx queue group 14830 * Value: bit-OR of masks based on the IDs of the vdevs whose tx queues 14831 * belong to the tx queue group. 14832 * For example, if vdev IDs 1 and 4 belong to a tx queue group, the 14833 * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12 14834 */ 14835 PREPACK struct htt_txq_group { 14836 A_UINT32 14837 credit_count: 14, 14838 sign: 1, 14839 absolute: 1, 14840 tx_queue_group_id: 8, 14841 reserved0: 7, 14842 extension: 1; 14843 A_UINT32 14844 ac_mask: 16, 14845 vdev_id_mask: 16; 14846 } POSTPACK; 14847 14848 /* first word */ 14849 #define HTT_TXQ_GROUP_CREDIT_COUNT_S 0 14850 #define HTT_TXQ_GROUP_CREDIT_COUNT_M 0x00003fff 14851 #define HTT_TXQ_GROUP_SIGN_S 14 14852 #define HTT_TXQ_GROUP_SIGN_M 0x00004000 14853 #define HTT_TXQ_GROUP_ABS_S 15 14854 #define HTT_TXQ_GROUP_ABS_M 0x00008000 14855 #define HTT_TXQ_GROUP_ID_S 16 14856 #define HTT_TXQ_GROUP_ID_M 0x00ff0000 14857 #define HTT_TXQ_GROUP_EXT_S 31 14858 #define HTT_TXQ_GROUP_EXT_M 0x80000000 14859 /* second word */ 14860 #define HTT_TXQ_GROUP_AC_MASK_S 0 14861 #define HTT_TXQ_GROUP_AC_MASK_M 0x0000ffff 14862 #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16 14863 #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000 14864 14865 #define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ 14866 do { \ 14867 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ 14868 ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ 14869 } while (0) 14870 #define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ 14871 (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> HTT_TXQ_GROUP_CREDIT_COUNT_S) 14872 14873 #define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ 14874 do { \ 14875 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ 14876 ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ 14877 } while (0) 14878 #define HTT_TXQ_GROUP_SIGN_GET(_info) \ 14879 (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) 14880 14881 #define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ 14882 do { \ 14883 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ 14884 ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ 14885 } while (0) 14886 #define HTT_TXQ_GROUP_ABS_GET(_info) \ 14887 (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) 14888 14889 #define HTT_TXQ_GROUP_ID_SET(_info, _val) \ 14890 do { \ 14891 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ 14892 ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ 14893 } while (0) 14894 #define HTT_TXQ_GROUP_ID_GET(_info) \ 14895 (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) 14896 14897 #define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ 14898 do { \ 14899 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ 14900 ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ 14901 } while (0) 14902 #define HTT_TXQ_GROUP_EXT_GET(_info) \ 14903 (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) 14904 14905 #define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ 14906 do { \ 14907 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ 14908 ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ 14909 } while (0) 14910 #define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ 14911 (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) 14912 14913 #define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ 14914 do { \ 14915 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ 14916 ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ 14917 } while (0) 14918 #define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ 14919 (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> HTT_TXQ_GROUP_VDEV_ID_MASK_S) 14920 14921 /** 14922 * @brief target -> host TX completion indication message definition 14923 * 14924 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_COMPL_IND 14925 * 14926 * @details 14927 * The following diagram shows the format of the TX completion indication sent 14928 * from the target to the host 14929 * 14930 * |31 30|29|28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 14931 * |-------------------------------------------------------------------| 14932 * header: |rsvd |A4|A3|A2|TP|A1|A0| num | t_i| tid |status| msg_type | 14933 * |-------------------------------------------------------------------| 14934 * payload:| MSDU1 ID | MSDU0 ID | 14935 * |-------------------------------------------------------------------| 14936 * : MSDU3 ID | MSDU2 ID : 14937 * |-------------------------------------------------------------------| 14938 * | struct htt_tx_compl_ind_append_retries | 14939 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14940 * | struct htt_tx_compl_ind_append_tx_tstamp | 14941 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14942 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 14943 * |-------------------------------------------------------------------| 14944 * : MSDU3 ACK RSSI | MSDU2 ACK RSSI : 14945 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14946 * | MSDU0 tx_tsf64_low | 14947 * |-------------------------------------------------------------------| 14948 * | MSDU0 tx_tsf64_high | 14949 * |-------------------------------------------------------------------| 14950 * | MSDU1 tx_tsf64_low | 14951 * |-------------------------------------------------------------------| 14952 * | MSDU1 tx_tsf64_high | 14953 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14954 * | phy_timestamp | 14955 * |-------------------------------------------------------------------| 14956 * | rate specs (see below) | 14957 * |-------------------------------------------------------------------| 14958 * | seqctrl | framectrl | 14959 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14960 * Where: 14961 * A0 = append (a.k.a. append0) 14962 * A1 = append1 14963 * TP = MSDU tx power presence 14964 * A2 = append2 14965 * A3 = append3 14966 * A4 = append4 14967 * 14968 * The following field definitions describe the format of the TX completion 14969 * indication sent from the target to the host 14970 * Header fields: 14971 * - msg_type 14972 * Bits 7:0 14973 * Purpose: identifies this as HTT TX completion indication 14974 * Value: 0x7 (HTT_T2H_MSG_TYPE_TX_COMPL_IND) 14975 * - status 14976 * Bits 10:8 14977 * Purpose: the TX completion status of payload fragmentations descriptors 14978 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 14979 * - tid 14980 * Bits 14:11 14981 * Purpose: the tid associated with those fragmentation descriptors. It is 14982 * valid or not, depending on the tid_invalid bit. 14983 * Value: 0 to 15 14984 * - tid_invalid 14985 * Bits 15:15 14986 * Purpose: this bit indicates whether the tid field is valid or not 14987 * Value: 0 indicates valid; 1 indicates invalid 14988 * - num 14989 * Bits 23:16 14990 * Purpose: the number of payload in this indication 14991 * Value: 1 to 255 14992 * - append (a.k.a. append0) 14993 * Bits 24:24 14994 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 14995 * the number of tx retries for one MSDU at the end of this message 14996 * Value: 0 indicates no appending; 1 indicates appending 14997 * - append1 14998 * Bits 25:25 14999 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 15000 * contains the timestamp info for each TX msdu id in payload. 15001 * The order of the timestamps matches the order of the MSDU IDs. 15002 * Note that a big-endian host needs to account for the reordering 15003 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 15004 * conversion) when determining which tx timestamp corresponds to 15005 * which MSDU ID. 15006 * Value: 0 indicates no appending; 1 indicates appending 15007 * - msdu_tx_power_presence 15008 * Bits 26:26 15009 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 15010 * for each MSDU referenced by the TX_COMPL_IND message. 15011 * The tx power is reported in 0.5 dBm units. 15012 * The order of the per-MSDU tx power reports matches the order 15013 * of the MSDU IDs. 15014 * Note that a big-endian host needs to account for the reordering 15015 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 15016 * conversion) when determining which Tx Power corresponds to 15017 * which MSDU ID. 15018 * Value: 0 indicates MSDU tx power reports are not appended, 15019 * 1 indicates MSDU tx power reports are appended 15020 * - append2 15021 * Bits 27:27 15022 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 15023 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 15024 * matches the order of the MSDU IDs. Although the ACK RSSI is the 15025 * same for all MSDUs within a single PPDU, the RSSI is duplicated 15026 * for each MSDU, for convenience. 15027 * The ACK RSSI values are valid when status is COMPLETE_OK (and 15028 * this append2 bit is set). 15029 * The ACK RSSI values are SNR in dB, i.e. are the RSSI in units of 15030 * dB above the noise floor. 15031 * Value: 0 indicates MSDU ACK RSSI values are not appended, 15032 * 1 indicates MSDU ACK RSSI values are appended. 15033 * - append3 15034 * Bits 28:28 15035 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tsf64 which 15036 * contains the tx tsf info based on wlan global TSF for 15037 * each TX msdu id in payload. 15038 * The order of the tx tsf matches the order of the MSDU IDs. 15039 * The struct htt_tx_compl_ind_append_tx_tsf64 contains two 32-bits 15040 * values to indicate the the lower 32 bits and higher 32 bits of 15041 * the tx tsf. 15042 * The tx_tsf64 here represents the time MSDU was acked and the 15043 * tx_tsf64 has microseconds units. 15044 * Value: 0 indicates no appending; 1 indicates appending 15045 * - append4 15046 * Bits 29:29 15047 * Purpose: Indicate whether data frame control fields and fields required 15048 * for radio tap header are appended for each MSDU in TX_COMP_IND 15049 * message. The order of the this message matches the order of 15050 * the MSDU IDs. 15051 * Value: 0 indicates frame control fields and fields required for 15052 * radio tap header values are not appended, 15053 * 1 indicates frame control fields and fields required for 15054 * radio tap header values are appended. 15055 * Payload fields: 15056 * - hmsdu_id 15057 * Bits 15:0 15058 * Purpose: this ID is used to track the Tx buffer in host 15059 * Value: 0 to "size of host MSDU descriptor pool - 1" 15060 */ 15061 15062 PREPACK struct htt_tx_data_hdr_information { 15063 A_UINT32 phy_timestamp_l32; /* word 0 [31:0] */ 15064 A_UINT32 /* word 1 */ 15065 /* preamble: 15066 * 0-OFDM, 15067 * 1-CCk, 15068 * 2-HT, 15069 * 3-VHT 15070 */ 15071 preamble: 2, /* [1:0] */ 15072 /* mcs: 15073 * In case of HT preamble interpret 15074 * MCS along with NSS. 15075 * Valid values for HT are 0 to 7. 15076 * HT mcs 0 with NSS 2 is mcs 8. 15077 * Valid values for VHT are 0 to 9. 15078 */ 15079 mcs: 4, /* [5:2] */ 15080 /* rate: 15081 * This is applicable only for 15082 * CCK and OFDM preamble type 15083 * rate 0: OFDM 48 Mbps, 15084 * 1: OFDM 24 Mbps, 15085 * 2: OFDM 12 Mbps 15086 * 3: OFDM 6 Mbps 15087 * 4: OFDM 54 Mbps 15088 * 5: OFDM 36 Mbps 15089 * 6: OFDM 18 Mbps 15090 * 7: OFDM 9 Mbps 15091 * rate 0: CCK 11 Mbps Long 15092 * 1: CCK 5.5 Mbps Long 15093 * 2: CCK 2 Mbps Long 15094 * 3: CCK 1 Mbps Long 15095 * 4: CCK 11 Mbps Short 15096 * 5: CCK 5.5 Mbps Short 15097 * 6: CCK 2 Mbps Short 15098 */ 15099 rate : 3, /* [ 8: 6] */ 15100 rssi : 8, /* [16: 9] units=dBm */ 15101 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 15102 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 15103 stbc : 1, /* [22] */ 15104 sgi : 1, /* [23] */ 15105 ldpc : 1, /* [24] */ 15106 beamformed: 1, /* [25] */ 15107 /* tx_retry_cnt: 15108 * Indicates retry count of data tx frames provided by the host. 15109 */ 15110 tx_retry_cnt: 6; /* [31:26] */ 15111 A_UINT32 /* word 2 */ 15112 framectrl:16, /* [15: 0] */ 15113 seqno:16; /* [31:16] */ 15114 } POSTPACK; 15115 15116 15117 #define HTT_TX_COMPL_IND_STATUS_S 8 15118 #define HTT_TX_COMPL_IND_STATUS_M 0x00000700 15119 #define HTT_TX_COMPL_IND_TID_S 11 15120 #define HTT_TX_COMPL_IND_TID_M 0x00007800 15121 #define HTT_TX_COMPL_IND_TID_INV_S 15 15122 #define HTT_TX_COMPL_IND_TID_INV_M 0x00008000 15123 #define HTT_TX_COMPL_IND_NUM_S 16 15124 #define HTT_TX_COMPL_IND_NUM_M 0x00ff0000 15125 #define HTT_TX_COMPL_IND_APPEND_S 24 15126 #define HTT_TX_COMPL_IND_APPEND_M 0x01000000 15127 #define HTT_TX_COMPL_IND_APPEND1_S 25 15128 #define HTT_TX_COMPL_IND_APPEND1_M 0x02000000 15129 #define HTT_TX_COMPL_IND_TX_POWER_S 26 15130 #define HTT_TX_COMPL_IND_TX_POWER_M 0x04000000 15131 #define HTT_TX_COMPL_IND_APPEND2_S 27 15132 #define HTT_TX_COMPL_IND_APPEND2_M 0x08000000 15133 #define HTT_TX_COMPL_IND_APPEND3_S 28 15134 #define HTT_TX_COMPL_IND_APPEND3_M 0x10000000 15135 #define HTT_TX_COMPL_IND_APPEND4_S 29 15136 #define HTT_TX_COMPL_IND_APPEND4_M 0x20000000 15137 15138 #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \ 15139 do { \ 15140 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ 15141 ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ 15142 } while (0) 15143 #define HTT_TX_COMPL_IND_STATUS_GET(_info) \ 15144 (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) 15145 #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \ 15146 do { \ 15147 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ 15148 ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ 15149 } while (0) 15150 #define HTT_TX_COMPL_IND_NUM_GET(_info) \ 15151 (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) 15152 #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \ 15153 do { \ 15154 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ 15155 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ 15156 } while (0) 15157 #define HTT_TX_COMPL_IND_TID_GET(_info) \ 15158 (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) 15159 #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \ 15160 do { \ 15161 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ 15162 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ 15163 } while (0) 15164 #define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ 15165 (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ 15166 HTT_TX_COMPL_IND_TID_INV_S) 15167 #define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ 15168 do { \ 15169 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ 15170 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ 15171 } while (0) 15172 #define HTT_TX_COMPL_IND_APPEND_GET(_info) \ 15173 (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) 15174 #define HTT_TX_COMPL_IND_APPEND1_SET(_info, _val) \ 15175 do { \ 15176 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND1, _val); \ 15177 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND1_S)); \ 15178 } while (0) 15179 #define HTT_TX_COMPL_IND_APPEND1_GET(_info) \ 15180 (((_info) & HTT_TX_COMPL_IND_APPEND1_M) >> HTT_TX_COMPL_IND_APPEND1_S) 15181 #define HTT_TX_COMPL_IND_TX_POWER_SET(_info, _val) \ 15182 do { \ 15183 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TX_POWER, _val); \ 15184 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TX_POWER_S)); \ 15185 } while (0) 15186 #define HTT_TX_COMPL_IND_TX_POWER_GET(_info) \ 15187 (((_info) & HTT_TX_COMPL_IND_TX_POWER_M) >> HTT_TX_COMPL_IND_TX_POWER_S) 15188 #define HTT_TX_COMPL_IND_APPEND2_SET(_info, _val) \ 15189 do { \ 15190 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND2, _val); \ 15191 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND2_S)); \ 15192 } while (0) 15193 #define HTT_TX_COMPL_IND_APPEND2_GET(_info) \ 15194 (((_info) & HTT_TX_COMPL_IND_APPEND2_M) >> HTT_TX_COMPL_IND_APPEND2_S) 15195 #define HTT_TX_COMPL_IND_APPEND3_SET(_info, _val) \ 15196 do { \ 15197 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND3, _val); \ 15198 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND3_S)); \ 15199 } while (0) 15200 #define HTT_TX_COMPL_IND_APPEND3_GET(_info) \ 15201 (((_info) & HTT_TX_COMPL_IND_APPEND3_M) >> HTT_TX_COMPL_IND_APPEND3_S) 15202 #define HTT_TX_COMPL_IND_APPEND4_SET(_info, _val) \ 15203 do { \ 15204 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND4, _val); \ 15205 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND4_S)); \ 15206 } while (0) 15207 #define HTT_TX_COMPL_IND_APPEND4_GET(_info) \ 15208 (((_info) & HTT_TX_COMPL_IND_APPEND4_M) >> HTT_TX_COMPL_IND_APPEND4_S) 15209 15210 #define HTT_TX_COMPL_INV_TX_POWER 0xffff 15211 15212 #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16) 15213 #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1) 15214 15215 #define HTT_TX_COMPL_INV_MSDU_ID 0xffff 15216 15217 #define HTT_TX_COMPL_IND_STAT_OK 0 15218 /* DISCARD: 15219 * current meaning: 15220 * MSDUs were queued for transmission but filtered by HW or SW 15221 * without any over the air attempts 15222 * legacy meaning (HL Rome): 15223 * MSDUs were discarded by the target FW without any over the air 15224 * attempts due to lack of space 15225 */ 15226 #define HTT_TX_COMPL_IND_STAT_DISCARD 1 15227 /* NO_ACK: 15228 * MSDUs were transmitted (repeatedly) but no ACK was received from the peer 15229 */ 15230 #define HTT_TX_COMPL_IND_STAT_NO_ACK 2 15231 /* POSTPONE: 15232 * temporarily-undeliverable MSDUs were deleted to free up space, but should 15233 * be downloaded again later (in the appropriate order), when they are 15234 * deliverable. 15235 */ 15236 #define HTT_TX_COMPL_IND_STAT_POSTPONE 3 15237 /* 15238 * The PEER_DEL tx completion status is used for HL cases 15239 * where the peer the frame is for has been deleted. 15240 * The host has already discarded its copy of the frame, but 15241 * it still needs the tx completion to restore its credit. 15242 */ 15243 #define HTT_TX_COMPL_IND_STAT_PEER_DEL 4 15244 /* DROP: MSDUs dropped due to lack of space (congestion control) */ 15245 #define HTT_TX_COMPL_IND_STAT_DROP 5 15246 #define HTT_TX_COMPL_IND_STAT_HOST_INSPECT 6 15247 15248 15249 #define HTT_TX_COMPL_IND_APPEND_SET_MORE_RETRY(f) ((f) |= 0x1) 15250 #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1)) 15251 15252 PREPACK struct htt_tx_compl_ind_base { 15253 A_UINT32 hdr; 15254 A_UINT16 payload[1/*or more*/]; 15255 } POSTPACK; 15256 15257 PREPACK struct htt_tx_compl_ind_append_retries { 15258 A_UINT16 msdu_id; 15259 A_UINT8 tx_retries; 15260 A_UINT8 flag; /* Bit 0, 1: another append_retries struct is appended 15261 0: this is the last append_retries struct */ 15262 } POSTPACK; 15263 15264 PREPACK struct htt_tx_compl_ind_append_tx_tstamp { 15265 A_UINT32 timestamp[1/*or more*/]; 15266 } POSTPACK; 15267 15268 PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { 15269 A_UINT32 tx_tsf64_low; 15270 A_UINT32 tx_tsf64_high; 15271 } POSTPACK; 15272 15273 /* htt_tx_data_hdr_information payload extension fields: */ 15274 15275 /* DWORD zero */ 15276 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M 0xffffffff 15277 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S 0 15278 15279 /* DWORD one */ 15280 #define HTT_FW_TX_DATA_HDR_PREAMBLE_M 0x00000003 15281 #define HTT_FW_TX_DATA_HDR_PREAMBLE_S 0 15282 #define HTT_FW_TX_DATA_HDR_MCS_M 0x0000003c 15283 #define HTT_FW_TX_DATA_HDR_MCS_S 2 15284 #define HTT_FW_TX_DATA_HDR_RATE_M 0x000001c0 15285 #define HTT_FW_TX_DATA_HDR_RATE_S 6 15286 #define HTT_FW_TX_DATA_HDR_RSSI_M 0x0001fe00 15287 #define HTT_FW_TX_DATA_HDR_RSSI_S 9 15288 #define HTT_FW_TX_DATA_HDR_NSS_M 0x00060000 15289 #define HTT_FW_TX_DATA_HDR_NSS_S 17 15290 #define HTT_FW_TX_DATA_HDR_BW_M 0x00380000 15291 #define HTT_FW_TX_DATA_HDR_BW_S 19 15292 #define HTT_FW_TX_DATA_HDR_STBC_M 0x00400000 15293 #define HTT_FW_TX_DATA_HDR_STBC_S 22 15294 #define HTT_FW_TX_DATA_HDR_SGI_M 0x00800000 15295 #define HTT_FW_TX_DATA_HDR_SGI_S 23 15296 #define HTT_FW_TX_DATA_HDR_LDPC_M 0x01000000 15297 #define HTT_FW_TX_DATA_HDR_LDPC_S 24 15298 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_M 0x02000000 15299 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_S 25 15300 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M 0xfc000000 15301 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S 26 15302 15303 /* DWORD two */ 15304 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_M 0x0000ffff 15305 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_S 0 15306 #define HTT_FW_TX_DATA_HDR_SEQNO_M 0xffff0000 15307 #define HTT_FW_TX_DATA_HDR_SEQNO_S 16 15308 15309 15310 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_SET(word, value) \ 15311 do { \ 15312 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32, value); \ 15313 (word) |= (value) << HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S; \ 15314 } while (0) 15315 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_GET(word) \ 15316 (((word) & HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M) >> HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S) 15317 15318 #define HTT_FW_TX_DATA_HDR_PREAMBLE_SET(word, value) \ 15319 do { \ 15320 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PREAMBLE, value); \ 15321 (word) |= (value) << HTT_FW_TX_DATA_HDR_PREAMBLE_S; \ 15322 } while (0) 15323 #define HTT_FW_TX_DATA_HDR_PREAMBLE_GET(word) \ 15324 (((word) & HTT_FW_TX_DATA_HDR_PREAMBLE_M) >> HTT_FW_TX_DATA_HDR_PREAMBLE_S) 15325 15326 #define HTT_FW_TX_DATA_HDR_MCS_SET(word, value) \ 15327 do { \ 15328 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_MCS, value); \ 15329 (word) |= (value) << HTT_FW_TX_DATA_HDR_MCS_S; \ 15330 } while (0) 15331 #define HTT_FW_TX_DATA_HDR_MCS_GET(word) \ 15332 (((word) & HTT_FW_TX_DATA_HDR_MCS_M) >> HTT_FW_TX_DATA_HDR_MCS_S) 15333 15334 #define HTT_FW_TX_DATA_HDR_RATE_SET(word, value) \ 15335 do { \ 15336 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RATE, value); \ 15337 (word) |= (value) << HTT_FW_TX_DATA_HDR_RATE_S; \ 15338 } while (0) 15339 #define HTT_FW_TX_DATA_HDR_RATE_GET(word) \ 15340 (((word) & HTT_FW_TX_DATA_HDR_RATE_M) >> HTT_FW_TX_DATA_HDR_RATE_S) 15341 15342 #define HTT_FW_TX_DATA_HDR_RSSI_SET(word, value) \ 15343 do { \ 15344 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RSSI, value); \ 15345 (word) |= (value) << HTT_FW_TX_DATA_HDR_RSSI_S; \ 15346 } while (0) 15347 #define HTT_FW_TX_DATA_HDR_RSSI_GET(word) \ 15348 (((word) & HTT_FW_TX_DATA_HDR_RSSI_M) >> HTT_FW_TX_DATA_HDR_RSSI_S) 15349 15350 15351 #define HTT_FW_TX_DATA_HDR_NSS_SET(word, value) \ 15352 do { \ 15353 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_NSS, value); \ 15354 (word) |= (value) << HTT_FW_TX_DATA_HDR_NSS_S; \ 15355 } while (0) 15356 #define HTT_FW_TX_DATA_HDR_NSS_GET(word) \ 15357 (((word) & HTT_FW_TX_DATA_HDR_NSS_M) >> HTT_FW_TX_DATA_HDR_NSS_S) 15358 15359 #define HTT_FW_TX_DATA_HDR_BW_SET(word, value) \ 15360 do { \ 15361 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BW, value); \ 15362 (word) |= (value) << HTT_FW_TX_DATA_HDR_BW_S; \ 15363 } while (0) 15364 #define HTT_FW_TX_DATA_HDR_BW_GET(word) \ 15365 (((word) & HTT_FW_TX_DATA_HDR_BW_M) >> HTT_FW_TX_DATA_HDR_BW_S) 15366 15367 15368 #define HTT_FW_TX_DATA_HDR_STBC_SET(word, value) \ 15369 do { \ 15370 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_STBC, value); \ 15371 (word) |= (value) << HTT_FW_TX_DATA_HDR_STBC_S; \ 15372 } while (0) 15373 #define HTT_FW_TX_DATA_HDR_STBC_GET(word) \ 15374 (((word) & HTT_FW_TX_DATA_HDR_STBC_M) >> HTT_FW_TX_DATA_HDR_STBC_S) 15375 15376 15377 #define HTT_FW_TX_DATA_HDR_SGI_SET(word, value) \ 15378 do { \ 15379 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SGI, value); \ 15380 (word) |= (value) << HTT_FW_TX_DATA_HDR_SGI_S; \ 15381 } while (0) 15382 #define HTT_FW_TX_DATA_HDR_SGI_GET(word) \ 15383 (((word) & HTT_FW_TX_DATA_HDR_SGI_M) >> HTT_FW_TX_DATA_HDR_SGI_S) 15384 15385 #define HTT_FW_TX_DATA_HDR_LDPC_SET(word, value) \ 15386 do { \ 15387 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_LDPC, value); \ 15388 (word) |= (value) << HTT_FW_TX_DATA_HDR_LDPC_S; \ 15389 } while (0) 15390 #define HTT_FW_TX_DATA_HDR_LDPC_GET(word) \ 15391 (((word) & HTT_FW_TX_DATA_HDR_LDPC_M) >> HTT_FW_TX_DATA_HDR_LDPC_S) 15392 15393 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_SET(word, value) \ 15394 do { \ 15395 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BEAMFORMED, value); \ 15396 (word) |= (value) << HTT_FW_TX_DATA_HDR_BEAMFORMED_S; \ 15397 } while (0) 15398 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_GET(word) \ 15399 (((word) & HTT_FW_TX_DATA_HDR_BEAMFORMED_M) >> HTT_FW_TX_DATA_HDR_BEAMFORMED_S) 15400 15401 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_SET(word, value) \ 15402 do { \ 15403 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_TX_RETRY_CNT, value); \ 15404 (word) |= (value) << HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S; \ 15405 } while (0) 15406 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_GET(word) \ 15407 (((word) & HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M) >> HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S) 15408 15409 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_SET(word, value) \ 15410 do { \ 15411 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_FRAMECTRL, value); \ 15412 (word) |= (value) << HTT_FW_TX_DATA_HDR_FRAMECTRL_S; \ 15413 } while (0) 15414 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_GET(word) \ 15415 (((word) & HTT_FW_TX_DATA_HDR_FRAMECTRL_M) >> HTT_FW_TX_DATA_HDR_FRAMECTRL_S) 15416 15417 15418 #define HTT_FW_TX_DATA_HDR_SEQNO_SET(word, value) \ 15419 do { \ 15420 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SEQNO, value); \ 15421 (word) |= (value) << HTT_FW_TX_DATA_HDR_SEQNO_S; \ 15422 } while (0) 15423 #define HTT_FW_TX_DATA_HDR_SEQNO_GET(word) \ 15424 (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S) 15425 15426 15427 /** 15428 * @brief target -> host software UMAC TX completion indication message 15429 * 15430 * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND 15431 * 15432 * @details 15433 * The following diagram shows the format of the soft UMAC TX completion 15434 * indication sent from the target to the host 15435 * 15436 * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| 15437 * |-------------------------------------+----------------+------------| 15438 * hdr: | rsvd | msdu_cnt | msg_type | 15439 * pyld: |===================================================================| 15440 * MSDU 0| buf addr low (bits 31:0) | 15441 * |-----------------------------------------------+------+------------| 15442 * | SW buffer cookie | RS | buf addr hi| 15443 * |--------+--+--+-------------+--------+---------+------+------------| 15444 * | rsvd0 | M| V| tx count | TID | SW peer ID | 15445 * |--------+--+--+-------------+--------+----------------------+------| 15446 * | frametype | TQM status number | RELR | 15447 * |-----+-----+-----------------------------------+--+-+-+-----+------| 15448 * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | 15449 * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| 15450 * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| 15451 * |--------+-------------------------+--+------+-----+--+-+-----+---+-| 15452 * | PPDU transmission TSF | 15453 * |-------------------------------------------------------------------| 15454 * | rsvd3 | 15455 * |===================================================================| 15456 * MSDU 1| buf addr low (bits 31:0) | 15457 * : ... : 15458 * | rsvd3 | 15459 * |===================================================================| 15460 * etc. 15461 * 15462 * Where: 15463 * RS = release source 15464 * V = valid 15465 * M = multicast 15466 * RELR = release reason 15467 * F = first MSDU 15468 * L = last MSDU 15469 * A = MSDU is part of A-MSDU 15470 * I = rate info valid 15471 * PKTYP = packet type 15472 * S = STBC 15473 * LC = LDPC 15474 * OF = OFDMA transmission 15475 */ 15476 typedef enum { 15477 /* 0 (REASON_FRAME_ACKED): 15478 * Corresponds to tqm_release_reason = <enum 0 tqm_rr_frame_acked>; 15479 * frame is removed because an ACK of BA for it was received. 15480 */ 15481 HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, 15482 15483 /* 1 (REASON_REMOVE_CMD_FW): 15484 * Corresponds to tqm_release_reason = <enum 1 tqm_rr_rem_cmd_rem>; 15485 * frame is removed because a remove command of type "Remove_mpdus" 15486 * initiated by SW. 15487 */ 15488 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, 15489 15490 /* 2 (REASON_REMOVE_CMD_TX): 15491 * Corresponds to tqm_release_reason = <enum 2 tqm_rr_rem_cmd_tx>; 15492 * frame is removed because a remove command of type 15493 * "Remove_transmitted_mpdus" initiated by SW. 15494 */ 15495 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, 15496 15497 /* 3 (REASON_REMOVE_CMD_NOTX): 15498 * Corresponds to tqm_release_reason = <enum 3 tqm_rr_rem_cmd_notx>; 15499 * frame is removed because a remove command of type 15500 * "Remove_untransmitted_mpdus" initiated by SW. 15501 */ 15502 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, 15503 15504 /* 4 (REASON_REMOVE_CMD_AGED): 15505 * Corresponds to tqm_release_reason = <enum 4 tqm_rr_rem_cmd_aged>; 15506 * frame is removed because a remove command of type "Remove_aged_mpdus" 15507 * or "Remove_aged_msdus" initiated by SW. 15508 */ 15509 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, 15510 15511 /* 5 (RELEASE_FW_REASON1): 15512 * Corresponds to tqm_release_reason = <enum 5 tqm_fw_reason1>; 15513 * frame is removed because a remove command where fw indicated that 15514 * remove reason is fw_reason1. 15515 */ 15516 HTT_TX_MSDU_RELEASE_FW_REASON1, 15517 15518 /* 6 (RELEASE_FW_REASON2): 15519 * Corresponds to tqm_release_reason = <enum 6 tqm_fw_reason2>; 15520 * frame is removed because a remove command where fw indicated that 15521 * remove reason is fw_reason1. 15522 */ 15523 HTT_TX_MSDU_RELEASE_FW_REASON2, 15524 15525 /* 7 (RELEASE_FW_REASON3): 15526 * Corresponds to tqm_release_reason = <enum 7 tqm_fw_reason3>; 15527 * frame is removed because a remove command where fw indicated that 15528 * remove reason is fw_reason1. 15529 */ 15530 HTT_TX_MSDU_RELEASE_FW_REASON3, 15531 15532 /* 8 (REASON_REMOVE_CMD_DISABLEQ): 15533 * Corresponds to tqm_release_reason = <enum 8 tqm_rr_rem_cmd_disable_queue> 15534 * frame is removed because a remove command of type 15535 * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" 15536 * initiated by SW. 15537 */ 15538 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, 15539 15540 /* 9 (REASON_DROP_MISC): 15541 * Corresponds to sw_release_reason = Packet dropped by FW due to 15542 * any discard reason that is not categorized as MSDU TTL expired. 15543 * Examples: TXDE ENQ layer dropped the packet due to peer delete, 15544 * tid delete, no resource credit available. 15545 */ 15546 HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, 15547 15548 /* 10 (REASON_DROP_TTL): 15549 * Corresponds to sw_release_reason = Packet dropped by FW due to 15550 * discard reason that frame is not transmitted due to MSDU TTL expired. 15551 */ 15552 HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, 15553 15554 /* 11 - available for use */ 15555 /* 12 - available for use */ 15556 /* 13 - available for use */ 15557 /* 14 - available for use */ 15558 /* 15 - available for use */ 15559 15560 HTT_TX_MSDU_RELEASE_REASON_MAX = 16 15561 } htt_t2h_tx_msdu_release_reason_e; 15562 15563 typedef enum { 15564 /* 0 (RELEASE_SOURCE_FW): 15565 * MSDU released by FW even before the frame was queued to TQM-L HW. 15566 */ 15567 HTT_TX_MSDU_RELEASE_SOURCE_FW, 15568 15569 /* 1 (RELEASE_SOURCE_TQM_LITE): 15570 * MSDU released by TQM-L HW. 15571 */ 15572 HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, 15573 15574 HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 15575 } htt_t2h_tx_msdu_release_source_e; 15576 15577 struct htt_t2h_tx_buffer_addr_info { /* 2 words */ 15578 A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ 15579 A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ 15580 /* release_source: 15581 * holds a htt_t2h_tx_msdu_release_source_e enum value 15582 */ 15583 release_source : 3, /* [10:8] */ 15584 sw_buffer_cookie : 21; /* [31:11] */ 15585 /* NOTE: 15586 * To preserve backwards compatibility, 15587 * no new fields can be added in this struct. 15588 */ 15589 }; 15590 15591 /* member definitions of htt_t2h_tx_buffer_addr_info */ 15592 15593 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF 15594 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 15595 15596 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ 15597 do { \ 15598 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ 15599 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ 15600 } while (0) 15601 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ 15602 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) 15603 15604 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF 15605 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 15606 15607 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ 15608 do { \ 15609 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ 15610 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ 15611 } while (0) 15612 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ 15613 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) 15614 15615 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 15616 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 15617 15618 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ 15619 do { \ 15620 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ 15621 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ 15622 } while (0) 15623 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ 15624 (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) 15625 15626 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 15627 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 15628 15629 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 15630 do { \ 15631 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ 15632 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ 15633 } while (0) 15634 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ 15635 (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) 15636 15637 struct htt_t2h_tx_rate_stats_info { /* 2 words */ 15638 /* word 0 */ 15639 A_UINT32 15640 /* tx_rate_stats_info_valid: 15641 * Indicates if the tx rate stats below are valid. 15642 */ 15643 tx_rate_stats_info_valid : 1, /* [0] */ 15644 /* transmit_bw: 15645 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15646 * Indicates the BW of the upcoming transmission that shall likely 15647 * start in about 3 -4 us on the medium: 15648 * <enum 0 transmit_bw_20_MHz> 15649 * <enum 1 transmit_bw_40_MHz> 15650 * <enum 2 transmit_bw_80_MHz> 15651 * <enum 3 transmit_bw_160_MHz> 15652 * <enum 4 transmit_bw_320_MHz> 15653 */ 15654 transmit_bw : 3, /* [3:1] */ 15655 /* transmit_pkt_type: 15656 * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15657 * Field filled in by PDG. 15658 * Not valid when in SW transmit mode 15659 * The packet type 15660 * <enum_type PKT_TYPE_ENUM> 15661 * Type: enum Definition Name: PKT_TYPE_ENUM 15662 * enum number enum name Description 15663 * ------------------------------------ 15664 * 0 dot11a 802.11a PPDU type 15665 * 1 dot11b 802.11b PPDU type 15666 * 2 dot11n_mm 802.11n Mixed Mode PPDU type 15667 * 3 dot11ac 802.11ac PPDU type 15668 * 4 dot11ax 802.11ax PPDU type 15669 * 5 dot11ba 802.11ba (WUR) PPDU type 15670 * 6 dot11be 802.11be PPDU type 15671 * 7 dot11az 802.11az (ranging) PPDU type 15672 */ 15673 transmit_pkt_type : 4, /* [7:4] */ 15674 /* transmit_stbc: 15675 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15676 * Field filled in by PDG. 15677 * Not valid when in SW transmit mode 15678 * When set, STBC transmission rate was used. 15679 */ 15680 transmit_stbc : 1, /* [8] */ 15681 /* transmit_ldpc: 15682 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15683 * Field filled in by PDG. 15684 * Not valid when in SW transmit mode 15685 * When set, use LDPC transmission rates 15686 */ 15687 transmit_ldpc : 1, /* [9] */ 15688 /* transmit_sgi: 15689 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15690 * Field filled in by PDG. 15691 * Not valid when in SW transmit mode 15692 * <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used for HE 15693 * <enum 1 0_4_us_sgi > Legacy short GI. Can also be used for HE 15694 * <enum 2 1_6_us_sgi > HE related GI 15695 * <enum 3 3_2_us_sgi > HE related GI 15696 * <legal 0 - 3> 15697 */ 15698 transmit_sgi : 2, /* [11:10] */ 15699 /* transmit_mcs: 15700 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15701 * Field filled in by PDG. 15702 * Not valid when in SW transmit mode 15703 * 15704 * For details, refer to MCS_TYPE description 15705 * <legal all> 15706 * Pkt_type Related definition of MCS_TYPE 15707 * dot11b This field is the rate: 15708 * 0: CCK 11 Mbps Long 15709 * 1: CCK 5.5 Mbps Long 15710 * 2: CCK 2 Mbps Long 15711 * 3: CCK 1 Mbps Long 15712 * 4: CCK 11 Mbps Short 15713 * 5: CCK 5.5 Mbps Short 15714 * 6: CCK 2 Mbps Short 15715 * NOTE: The numbering here is NOT the same as the as MAC gives 15716 * in the "rate" field in the SIG given to the PHY. 15717 * The MAC will do an internal translation. 15718 * 15719 * Dot11a This field is the rate: 15720 * 0: OFDM 48 Mbps 15721 * 1: OFDM 24 Mbps 15722 * 2: OFDM 12 Mbps 15723 * 3: OFDM 6 Mbps 15724 * 4: OFDM 54 Mbps 15725 * 5: OFDM 36 Mbps 15726 * 6: OFDM 18 Mbps 15727 * 7: OFDM 9 Mbps 15728 * NOTE: The numbering here is NOT the same as the as MAC gives 15729 * in the "rate" field in the SIG given to the PHY. 15730 * The MAC will do an internal translation. 15731 * 15732 * Dot11n_mm (mixed mode) This field represends the MCS. 15733 * 0: HT MCS 0 (BPSK 1/2) 15734 * 1: HT MCS 1 (QPSK 1/2) 15735 * 2: HT MCS 2 (QPSK 3/4) 15736 * 3: HT MCS 3 (16-QAM 1/2) 15737 * 4: HT MCS 4 (16-QAM 3/4) 15738 * 5: HT MCS 5 (64-QAM 2/3) 15739 * 6: HT MCS 6 (64-QAM 3/4) 15740 * 7: HT MCS 7 (64-QAM 5/6) 15741 * NOTE: To get higher MCS's use the nss field to indicate the 15742 * number of spatial streams. 15743 * 15744 * Dot11ac This field represends the MCS. 15745 * 0: VHT MCS 0 (BPSK 1/2) 15746 * 1: VHT MCS 1 (QPSK 1/2) 15747 * 2: VHT MCS 2 (QPSK 3/4) 15748 * 3: VHT MCS 3 (16-QAM 1/2) 15749 * 4: VHT MCS 4 (16-QAM 3/4) 15750 * 5: VHT MCS 5 (64-QAM 2/3) 15751 * 6: VHT MCS 6 (64-QAM 3/4) 15752 * 7: VHT MCS 7 (64-QAM 5/6) 15753 * 8: VHT MCS 8 (256-QAM 3/4) 15754 * 9: VHT MCS 9 (256-QAM 5/6) 15755 * 10: VHT MCS 10 (1024-QAM 3/4) 15756 * 11: VHT MCS 11 (1024-QAM 5/6) 15757 * NOTE: There are several illegal VHT rates due to fractional 15758 * number of bits per symbol. 15759 * Below are the illegal rates for 4 streams and lower: 15760 * 20 MHz, 1 stream, MCS 9 15761 * 20 MHz, 2 stream, MCS 9 15762 * 20 MHz, 4 stream, MCS 9 15763 * 80 MHz, 3 stream, MCS 6 15764 * 160 MHz, 3 stream, MCS 9 (Unsupported) 15765 * 160 MHz, 4 stream, MCS 7 (Unsupported) 15766 * 15767 * dot11ax This field represends the MCS. 15768 * 0: HE MCS 0 (BPSK 1/2) 15769 * 1: HE MCS 1 (QPSK 1/2) 15770 * 2: HE MCS 2 (QPSK 3/4) 15771 * 3: HE MCS 3 (16-QAM 1/2) 15772 * 4: HE MCS 4 (16-QAM 3/4) 15773 * 5: HE MCS 5 (64-QAM 2/3) 15774 * 6: HE MCS 6 (64-QAM 3/4) 15775 * 7: HE MCS 7 (64-QAM 5/6) 15776 * 8: HE MCS 8 (256-QAM 3/4) 15777 * 9: HE MCS 9 (256-QAM 5/6) 15778 * 10: HE MCS 10 (1024-QAM 3/4) 15779 * 11: HE MCS 11 (1024-QAM 5/6) 15780 * 12: HE MCS 12 (4096-QAM 3/4) 15781 * 13: HE MCS 13 (4096-QAM 5/6) 15782 * 15783 * dot11ba This field is the rate: 15784 * 0: LDR 15785 * 1: HDR 15786 * 2: Exclusive rate 15787 */ 15788 transmit_mcs : 4, /* [15:12] */ 15789 /* ofdma_transmission: 15790 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15791 * Field filled in by PDG. 15792 * Set when the transmission was an OFDMA transmission (DL or UL). 15793 * <legal all> 15794 */ 15795 ofdma_transmission : 1, /* [16] */ 15796 /* tones_in_ru: 15797 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15798 * Field filled in by PDG. 15799 * Not valid when in SW transmit mode 15800 * The number of tones in the RU used. 15801 * <legal all> 15802 */ 15803 tones_in_ru : 12, /* [28:17] */ 15804 rsvd2 : 3; /* [31:29] */ 15805 15806 /* word 1 */ 15807 /* ppdu_transmission_tsf: 15808 * Based on a HWSCH configuration register setting, 15809 * this field either contains: 15810 * Lower 32 bits of the TSF, snapshot of this value when transmission 15811 * of the PPDU containing the frame finished. 15812 * OR 15813 * Lower 32 bits of the TSF, snapshot of this value when transmission 15814 * of the PPDU containing the frame started. 15815 * <legal all> 15816 */ 15817 A_UINT32 ppdu_transmission_tsf; 15818 15819 /* NOTE: 15820 * To preserve backwards compatibility, 15821 * no new fields can be added in this struct. 15822 */ 15823 }; 15824 15825 /* member definitions of htt_t2h_tx_rate_stats_info */ 15826 15827 #define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 15828 #define HTT_TX_RATE_STATS_INFO_VALID_S 0 15829 15830 #define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ 15831 do { \ 15832 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ 15833 (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ 15834 } while (0) 15835 #define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ 15836 (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) 15837 15838 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E 15839 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 15840 15841 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ 15842 do { \ 15843 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ 15844 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ 15845 } while (0) 15846 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ 15847 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) 15848 15849 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 15850 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 15851 15852 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ 15853 do { \ 15854 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ 15855 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ 15856 } while (0) 15857 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ 15858 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) 15859 15860 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 15861 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 15862 15863 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ 15864 do { \ 15865 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ 15866 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ 15867 } while (0) 15868 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ 15869 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) 15870 15871 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 15872 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 15873 15874 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ 15875 do { \ 15876 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ 15877 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ 15878 } while (0) 15879 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ 15880 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) 15881 15882 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 15883 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 15884 15885 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ 15886 do { \ 15887 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ 15888 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ 15889 } while (0) 15890 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ 15891 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) 15892 15893 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 15894 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 15895 15896 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ 15897 do { \ 15898 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ 15899 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ 15900 } while (0) 15901 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ 15902 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) 15903 15904 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 15905 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 15906 15907 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ 15908 do { \ 15909 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ 15910 (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ 15911 } while (0) 15912 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ 15913 (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) 15914 15915 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 15916 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 15917 15918 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ 15919 do { \ 15920 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ 15921 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ 15922 } while (0) 15923 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ 15924 (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) 15925 15926 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF 15927 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 15928 15929 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ 15930 do { \ 15931 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ 15932 (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ 15933 } while (0) 15934 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ 15935 (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) 15936 15937 struct htt_t2h_tx_msdu_info { /* 8 words */ 15938 /* words 0 + 1 */ 15939 struct htt_t2h_tx_buffer_addr_info addr_info; 15940 15941 /* word 2 */ 15942 A_UINT32 15943 sw_peer_id : 16, 15944 tid : 4, 15945 transmit_cnt : 7, 15946 valid : 1, 15947 mcast : 1, 15948 rsvd0 : 3; 15949 15950 /* word 3 */ 15951 A_UINT32 15952 release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ 15953 tqm_status_number : 24, 15954 frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ 15955 15956 /* word 4 */ 15957 A_UINT32 15958 /* ack_frame_rssi: 15959 * If this frame is removed as the result of the 15960 * reception of an ACK or BA, this field indicates 15961 * the RSSI of the received ACK or BA frame. 15962 * When the frame is removed as result of a direct 15963 * remove command from the SW, this field is set 15964 * to 0x0 (which is never a valid value when real 15965 * RSSI is available). 15966 * Units: dB w.r.t noise floor 15967 */ 15968 ack_frame_rssi : 8, 15969 first_msdu : 1, 15970 last_msdu : 1, 15971 msdu_part_of_amsdu : 1, 15972 buffer_timestamp : 19, /* units = TU = 1024 microseconds */ 15973 rsvd1 : 2; 15974 15975 /* words 5 + 6 */ 15976 struct htt_t2h_tx_rate_stats_info tx_rate_stats; 15977 15978 /* word 7 */ 15979 /* rsvd3: 15980 * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] 15981 * is not sufficient 15982 */ 15983 A_UINT32 rsvd3; 15984 15985 /* NOTE: 15986 * To preserve backwards compatibility, 15987 * no new fields can be added in this struct. 15988 */ 15989 }; 15990 15991 /* member definitions of htt_t2h_tx_msdu_info */ 15992 15993 #define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF 15994 #define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 15995 15996 #define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ 15997 do { \ 15998 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ 15999 (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ 16000 } while (0) 16001 #define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ 16002 (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) 16003 16004 #define HTT_TX_MSDU_INFO_TID_M 0x000F0000 16005 #define HTT_TX_MSDU_INFO_TID_S 16 16006 16007 #define HTT_TX_MSDU_INFO_TID_SET(word, value) \ 16008 do { \ 16009 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ 16010 (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ 16011 } while (0) 16012 #define HTT_TX_MSDU_INFO_TID_GET(word) \ 16013 (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) 16014 16015 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 16016 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 16017 16018 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ 16019 do { \ 16020 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ 16021 (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ 16022 } while (0) 16023 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ 16024 (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) 16025 16026 #define HTT_TX_MSDU_INFO_VALID_M 0x08000000 16027 #define HTT_TX_MSDU_INFO_VALID_S 27 16028 16029 #define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ 16030 do { \ 16031 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ 16032 (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ 16033 } while (0) 16034 #define HTT_TX_MSDU_INFO_VALID_GET(word) \ 16035 (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) 16036 16037 #define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 16038 #define HTT_TX_MSDU_INFO_MCAST_S 28 16039 16040 #define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ 16041 do { \ 16042 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ 16043 (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ 16044 } while (0) 16045 #define HTT_TX_MSDU_INFO_MCAST_GET(word) \ 16046 (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) 16047 16048 #define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F 16049 #define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 16050 16051 #define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ 16052 do { \ 16053 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ 16054 (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ 16055 } while (0) 16056 #define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ 16057 (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) 16058 16059 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 16060 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 16061 16062 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ 16063 do { \ 16064 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ 16065 (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ 16066 } while (0) 16067 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ 16068 (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) 16069 16070 #define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 16071 #define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 16072 16073 #define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ 16074 do { \ 16075 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ 16076 (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ 16077 } while (0) 16078 #define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ 16079 (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) 16080 16081 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF 16082 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 16083 16084 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ 16085 do { \ 16086 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ 16087 (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ 16088 } while (0) 16089 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ 16090 (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) 16091 16092 #define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 16093 #define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 16094 16095 #define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ 16096 do { \ 16097 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ 16098 (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ 16099 } while (0) 16100 #define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ 16101 (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) 16102 16103 #define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 16104 #define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 16105 16106 #define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ 16107 do { \ 16108 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ 16109 (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ 16110 } while (0) 16111 #define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ 16112 (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) 16113 16114 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 16115 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 16116 16117 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ 16118 do { \ 16119 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ 16120 (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ 16121 } while (0) 16122 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ 16123 (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) 16124 16125 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 16126 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 16127 16128 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ 16129 do { \ 16130 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ 16131 (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ 16132 } while (0) 16133 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ 16134 (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) 16135 16136 struct htt_t2h_soft_umac_tx_compl_ind { 16137 A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ 16138 msdu_cnt : 8, /* min: 0, max: 255 */ 16139 rsvd0 : 16; 16140 /* NOTE: 16141 * To preserve backwards compatibility, 16142 * no new fields can be added in this struct. 16143 */ 16144 /* 16145 * append here: 16146 * struct htt_t2h_tx_msdu_info payload[1(or more)] 16147 * for all the msdu's that are part of this completion. 16148 */ 16149 }; 16150 16151 /* member definitions of htt_t2h_soft_umac_tx_compl_ind */ 16152 16153 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 16154 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 16155 16156 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ 16157 do { \ 16158 HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ 16159 (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ 16160 } while (0) 16161 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ 16162 (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) 16163 16164 16165 /** 16166 * @brief target -> host rate-control update indication message 16167 * 16168 * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND) 16169 * 16170 * @details 16171 * The following diagram shows the format of the RC Update message 16172 * sent from the target to the host, while processing the tx-completion 16173 * of a transmitted PPDU. 16174 * 16175 * |31 24|23 16|15 8|7 0| 16176 * |-------------------------------------------------------------| 16177 * | peer ID | vdev ID | msg_type | 16178 * |-------------------------------------------------------------| 16179 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 16180 * |-------------------------------------------------------------| 16181 * | reserved | num elems | MAC addr 5 | MAC addr 4 | 16182 * |-------------------------------------------------------------| 16183 * | : | 16184 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16185 * | : | 16186 * |-------------------------------------------------------------| 16187 * | : | 16188 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16189 * | : | 16190 * |-------------------------------------------------------------| 16191 * : : 16192 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16193 * 16194 */ 16195 16196 typedef struct { 16197 A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ 16198 A_UINT32 rate_code_flags; 16199 A_UINT32 flags; /* Encodes information such as excessive 16200 retransmission, aggregate, some info 16201 from .11 frame control, 16202 STBC, LDPC, (SGI and Tx Chain Mask 16203 are encoded in ptx_rc->flags field), 16204 AMPDU truncation (BT/time based etc.), 16205 RTS/CTS attempt */ 16206 16207 A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ 16208 A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ 16209 A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ 16210 A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ 16211 A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ 16212 A_UINT32 is_probe; /* Valid if probing. Else, 0 */ 16213 } HTT_RC_TX_DONE_PARAMS; 16214 16215 #define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS)) /* bytes */ 16216 #define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ 16217 16218 #define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ 16219 #define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ 16220 16221 #define HTT_RC_UPDATE_VDEVID_S 8 16222 #define HTT_RC_UPDATE_VDEVID_M 0xff00 16223 #define HTT_RC_UPDATE_PEERID_S 16 16224 #define HTT_RC_UPDATE_PEERID_M 0xffff0000 16225 16226 #define HTT_RC_UPDATE_NUM_ELEMS_S 16 16227 #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000 16228 16229 #define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ 16230 do { \ 16231 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ 16232 ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ 16233 } while (0) 16234 16235 #define HTT_RC_UPDATE_VDEVID_GET(_info) \ 16236 (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) 16237 16238 #define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ 16239 do { \ 16240 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ 16241 ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ 16242 } while (0) 16243 16244 #define HTT_RC_UPDATE_PEERID_GET(_info) \ 16245 (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) 16246 16247 #define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ 16248 do { \ 16249 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ 16250 ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ 16251 } while (0) 16252 16253 #define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ 16254 (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) 16255 16256 /** 16257 * @brief target -> host rx fragment indication message definition 16258 * 16259 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FRAG_IND 16260 * 16261 * @details 16262 * The following field definitions describe the format of the rx fragment 16263 * indication message sent from the target to the host. 16264 * The rx fragment indication message shares the format of the 16265 * rx indication message, but not all fields from the rx indication message 16266 * are relevant to the rx fragment indication message. 16267 * 16268 * 16269 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 16270 * |-----------+-------------------+---------------------+-------------| 16271 * | peer ID | |FV| ext TID | msg type | 16272 * |-------------------------------------------------------------------| 16273 * | | flush | flush | 16274 * | | end | start | 16275 * | | seq num | seq num | 16276 * |-------------------------------------------------------------------| 16277 * | reserved | FW rx desc bytes | 16278 * |-------------------------------------------------------------------| 16279 * | | FW MSDU Rx | 16280 * | | desc B0 | 16281 * |-------------------------------------------------------------------| 16282 * Header fields: 16283 * - MSG_TYPE 16284 * Bits 7:0 16285 * Purpose: identifies this as an rx fragment indication message 16286 * Value: 0xa (HTT_T2H_MSG_TYPE_RX_FRAG_IND) 16287 * - EXT_TID 16288 * Bits 12:8 16289 * Purpose: identify the traffic ID of the rx data, including 16290 * special "extended" TID values for multicast, broadcast, and 16291 * non-QoS data frames 16292 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 16293 * - FLUSH_VALID (FV) 16294 * Bit 13 16295 * Purpose: indicate whether the flush IE (start/end sequence numbers) 16296 * is valid 16297 * Value: 16298 * 1 -> flush IE is valid and needs to be processed 16299 * 0 -> flush IE is not valid and should be ignored 16300 * - PEER_ID 16301 * Bits 31:16 16302 * Purpose: Identify, by ID, which peer sent the rx data 16303 * Value: ID of the peer who sent the rx data 16304 * - FLUSH_SEQ_NUM_START 16305 * Bits 5:0 16306 * Purpose: Indicate the start of a series of MPDUs to flush 16307 * Not all MPDUs within this series are necessarily valid - the host 16308 * must check each sequence number within this range to see if the 16309 * corresponding MPDU is actually present. 16310 * This field is only valid if the FV bit is set. 16311 * Value: 16312 * The sequence number for the first MPDUs to check to flush. 16313 * The sequence number is masked by 0x3f. 16314 * - FLUSH_SEQ_NUM_END 16315 * Bits 11:6 16316 * Purpose: Indicate the end of a series of MPDUs to flush 16317 * Value: 16318 * The sequence number one larger than the sequence number of the 16319 * last MPDU to check to flush. 16320 * The sequence number is masked by 0x3f. 16321 * Not all MPDUs within this series are necessarily valid - the host 16322 * must check each sequence number within this range to see if the 16323 * corresponding MPDU is actually present. 16324 * This field is only valid if the FV bit is set. 16325 * Rx descriptor fields: 16326 * - FW_RX_DESC_BYTES 16327 * Bits 15:0 16328 * Purpose: Indicate how many bytes in the Rx indication are used for 16329 * FW Rx descriptors 16330 * Value: 1 16331 */ 16332 #define HTT_RX_FRAG_IND_HDR_PREFIX_SIZE32 2 16333 16334 #define HTT_RX_FRAG_IND_FW_DESC_BYTE_OFFSET 12 16335 16336 #define HTT_RX_FRAG_IND_EXT_TID_SET HTT_RX_IND_EXT_TID_SET 16337 #define HTT_RX_FRAG_IND_EXT_TID_GET HTT_RX_IND_EXT_TID_GET 16338 16339 #define HTT_RX_FRAG_IND_PEER_ID_SET HTT_RX_IND_PEER_ID_SET 16340 #define HTT_RX_FRAG_IND_PEER_ID_GET HTT_RX_IND_PEER_ID_GET 16341 16342 #define HTT_RX_FRAG_IND_FLUSH_VALID_SET HTT_RX_IND_FLUSH_VALID_SET 16343 #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET 16344 16345 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \ 16346 HTT_RX_IND_FLUSH_SEQ_NUM_START_SET 16347 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \ 16348 HTT_RX_IND_FLUSH_SEQ_NUM_START_GET 16349 16350 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ 16351 HTT_RX_IND_FLUSH_SEQ_NUM_END_SET 16352 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ 16353 HTT_RX_IND_FLUSH_SEQ_NUM_END_GET 16354 16355 #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET 16356 16357 #define HTT_RX_FRAG_IND_BYTES \ 16358 (4 /* msg hdr */ + \ 16359 4 /* flush spec */ + \ 16360 4 /* (unused) FW rx desc bytes spec */ + \ 16361 4 /* FW rx desc */) 16362 16363 /** 16364 * @brief target -> host test message definition 16365 * 16366 * MSG_TYPE => HTT_T2H_MSG_TYPE_TEST 16367 * 16368 * @details 16369 * The following field definitions describe the format of the test 16370 * message sent from the target to the host. 16371 * The message consists of a 4-octet header, followed by a variable 16372 * number of 32-bit integer values, followed by a variable number 16373 * of 8-bit character values. 16374 * 16375 * |31 16|15 8|7 0| 16376 * |-----------------------------------------------------------| 16377 * | num chars | num ints | msg type | 16378 * |-----------------------------------------------------------| 16379 * | int 0 | 16380 * |-----------------------------------------------------------| 16381 * | int 1 | 16382 * |-----------------------------------------------------------| 16383 * | ... | 16384 * |-----------------------------------------------------------| 16385 * | char 3 | char 2 | char 1 | char 0 | 16386 * |-----------------------------------------------------------| 16387 * | | | ... | char 4 | 16388 * |-----------------------------------------------------------| 16389 * - MSG_TYPE 16390 * Bits 7:0 16391 * Purpose: identifies this as a test message 16392 * Value: HTT_MSG_TYPE_TEST 16393 * - NUM_INTS 16394 * Bits 15:8 16395 * Purpose: indicate how many 32-bit integers follow the message header 16396 * - NUM_CHARS 16397 * Bits 31:16 16398 * Purpose: indicate how many 8-bit characters follow the series of integers 16399 */ 16400 #define HTT_RX_TEST_NUM_INTS_M 0xff00 16401 #define HTT_RX_TEST_NUM_INTS_S 8 16402 #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000 16403 #define HTT_RX_TEST_NUM_CHARS_S 16 16404 16405 #define HTT_RX_TEST_NUM_INTS_SET(word, value) \ 16406 do { \ 16407 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ 16408 (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ 16409 } while (0) 16410 #define HTT_RX_TEST_NUM_INTS_GET(word) \ 16411 (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) 16412 16413 #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \ 16414 do { \ 16415 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ 16416 (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ 16417 } while (0) 16418 #define HTT_RX_TEST_NUM_CHARS_GET(word) \ 16419 (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) 16420 16421 /** 16422 * @brief target -> host packet log message 16423 * 16424 * MSG_TYPE => HTT_T2H_MSG_TYPE_PKTLOG 16425 * 16426 * @details 16427 * The following field definitions describe the format of the packet log 16428 * message sent from the target to the host. 16429 * The message consists of a 4-octet header,followed by a variable number 16430 * of 32-bit character values. 16431 * 16432 * |31 16|15 12|11 10|9 8|7 0| 16433 * |------------------------------------------------------------------| 16434 * | payload_size | rsvd |pdev_id|mac_id| msg type | 16435 * |------------------------------------------------------------------| 16436 * | payload | 16437 * |------------------------------------------------------------------| 16438 * - MSG_TYPE 16439 * Bits 7:0 16440 * Purpose: identifies this as a pktlog message 16441 * Value: 0x8 (HTT_T2H_MSG_TYPE_PKTLOG) 16442 * - mac_id 16443 * Bits 9:8 16444 * Purpose: identifies which MAC/PHY instance generated this pktlog info 16445 * Value: 0-3 16446 * - pdev_id 16447 * Bits 11:10 16448 * Purpose: pdev_id 16449 * Value: 0-3 16450 * 0 (for rings at SOC level), 16451 * 1/2/3 PDEV -> 0/1/2 16452 * - payload_size 16453 * Bits 31:16 16454 * Purpose: explicitly specify the payload size 16455 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 16456 */ 16457 PREPACK struct htt_pktlog_msg { 16458 A_UINT32 header; 16459 A_UINT32 payload[1/* or more */]; 16460 } POSTPACK; 16461 16462 #define HTT_T2H_PKTLOG_MAC_ID_M 0x00000300 16463 #define HTT_T2H_PKTLOG_MAC_ID_S 8 16464 16465 #define HTT_T2H_PKTLOG_PDEV_ID_M 0x00000C00 16466 #define HTT_T2H_PKTLOG_PDEV_ID_S 10 16467 16468 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_M 0xFFFF0000 16469 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_S 16 16470 16471 #define HTT_T2H_PKTLOG_MAC_ID_SET(word, value) \ 16472 do { \ 16473 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_MAC_ID, value); \ 16474 (word) |= (value) << HTT_T2H_PKTLOG_MAC_ID_S; \ 16475 } while (0) 16476 #define HTT_T2H_PKTLOG_MAC_ID_GET(word) \ 16477 (((word) & HTT_T2H_PKTLOG_MAC_ID_M) >> \ 16478 HTT_T2H_PKTLOG_MAC_ID_S) 16479 16480 #define HTT_T2H_PKTLOG_PDEV_ID_SET(word, value) \ 16481 do { \ 16482 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PDEV_ID, value); \ 16483 (word) |= (value) << HTT_T2H_PKTLOG_PDEV_ID_S; \ 16484 } while (0) 16485 #define HTT_T2H_PKTLOG_PDEV_ID_GET(word) \ 16486 (((word) & HTT_T2H_PKTLOG_PDEV_ID_M) >> \ 16487 HTT_T2H_PKTLOG_PDEV_ID_S) 16488 16489 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_SET(word, value) \ 16490 do { \ 16491 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PAYLOAD_SIZE, value); \ 16492 (word) |= (value) << HTT_T2H_PKTLOG_PAYLOAD_SIZE_S; \ 16493 } while (0) 16494 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_GET(word) \ 16495 (((word) & HTT_T2H_PKTLOG_PAYLOAD_SIZE_M) >> \ 16496 HTT_T2H_PKTLOG_PAYLOAD_SIZE_S) 16497 16498 /* 16499 * Rx reorder statistics 16500 * NB: all the fields must be defined in 4 octets size. 16501 */ 16502 struct rx_reorder_stats { 16503 /* Non QoS MPDUs received */ 16504 A_UINT32 deliver_non_qos; 16505 /* MPDUs received in-order */ 16506 A_UINT32 deliver_in_order; 16507 /* Flush due to reorder timer expired */ 16508 A_UINT32 deliver_flush_timeout; 16509 /* Flush due to move out of window */ 16510 A_UINT32 deliver_flush_oow; 16511 /* Flush due to DELBA */ 16512 A_UINT32 deliver_flush_delba; 16513 /* MPDUs dropped due to FCS error */ 16514 A_UINT32 fcs_error; 16515 /* MPDUs dropped due to monitor mode non-data packet */ 16516 A_UINT32 mgmt_ctrl; 16517 /* Unicast-data MPDUs dropped due to invalid peer */ 16518 A_UINT32 invalid_peer; 16519 /* MPDUs dropped due to duplication (non aggregation) */ 16520 A_UINT32 dup_non_aggr; 16521 /* MPDUs dropped due to processed before */ 16522 A_UINT32 dup_past; 16523 /* MPDUs dropped due to duplicate in reorder queue */ 16524 A_UINT32 dup_in_reorder; 16525 /* Reorder timeout happened */ 16526 A_UINT32 reorder_timeout; 16527 /* invalid bar ssn */ 16528 A_UINT32 invalid_bar_ssn; 16529 /* reorder reset due to bar ssn */ 16530 A_UINT32 ssn_reset; 16531 /* Flush due to delete peer */ 16532 A_UINT32 deliver_flush_delpeer; 16533 /* Flush due to offload*/ 16534 A_UINT32 deliver_flush_offload; 16535 /* Flush due to out of buffer*/ 16536 A_UINT32 deliver_flush_oob; 16537 /* MPDUs dropped due to PN check fail */ 16538 A_UINT32 pn_fail; 16539 /* MPDUs dropped due to unable to allocate memory */ 16540 A_UINT32 store_fail; 16541 /* Number of times the tid pool alloc succeeded */ 16542 A_UINT32 tid_pool_alloc_succ; 16543 /* Number of times the MPDU pool alloc succeeded */ 16544 A_UINT32 mpdu_pool_alloc_succ; 16545 /* Number of times the MSDU pool alloc succeeded */ 16546 A_UINT32 msdu_pool_alloc_succ; 16547 /* Number of times the tid pool alloc failed */ 16548 A_UINT32 tid_pool_alloc_fail; 16549 /* Number of times the MPDU pool alloc failed */ 16550 A_UINT32 mpdu_pool_alloc_fail; 16551 /* Number of times the MSDU pool alloc failed */ 16552 A_UINT32 msdu_pool_alloc_fail; 16553 /* Number of times the tid pool freed */ 16554 A_UINT32 tid_pool_free; 16555 /* Number of times the MPDU pool freed */ 16556 A_UINT32 mpdu_pool_free; 16557 /* Number of times the MSDU pool freed */ 16558 A_UINT32 msdu_pool_free; 16559 /* number of MSDUs undelivered to HTT and queued to Data Rx MSDU free list*/ 16560 A_UINT32 msdu_queued; 16561 /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ 16562 A_UINT32 msdu_recycled; 16563 /* Number of MPDUs with invalid peer but A2 found in AST */ 16564 A_UINT32 invalid_peer_a2_in_ast; 16565 /* Number of MPDUs with invalid peer but A3 found in AST */ 16566 A_UINT32 invalid_peer_a3_in_ast; 16567 /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ 16568 A_UINT32 invalid_peer_bmc_mpdus; 16569 /* Number of MSDUs with err attention word */ 16570 A_UINT32 rxdesc_err_att; 16571 /* Number of MSDUs with flag of peer_idx_invalid */ 16572 A_UINT32 rxdesc_err_peer_idx_inv; 16573 /* Number of MSDUs with flag of peer_idx_timeout */ 16574 A_UINT32 rxdesc_err_peer_idx_to; 16575 /* Number of MSDUs with flag of overflow */ 16576 A_UINT32 rxdesc_err_ov; 16577 /* Number of MSDUs with flag of msdu_length_err */ 16578 A_UINT32 rxdesc_err_msdu_len; 16579 /* Number of MSDUs with flag of mpdu_length_err */ 16580 A_UINT32 rxdesc_err_mpdu_len; 16581 /* Number of MSDUs with flag of tkip_mic_err */ 16582 A_UINT32 rxdesc_err_tkip_mic; 16583 /* Number of MSDUs with flag of decrypt_err */ 16584 A_UINT32 rxdesc_err_decrypt; 16585 /* Number of MSDUs with flag of fcs_err */ 16586 A_UINT32 rxdesc_err_fcs; 16587 /* Number of Unicast (bc_mc bit is not set in attention word) 16588 * frames with invalid peer handler 16589 */ 16590 A_UINT32 rxdesc_uc_msdus_inv_peer; 16591 /* Number of unicast frame directly (direct bit is set in attention word) 16592 * to DUT with invalid peer handler 16593 */ 16594 A_UINT32 rxdesc_direct_msdus_inv_peer; 16595 /* Number of Broadcast/Multicast (bc_mc bit set in attention word) 16596 * frames with invalid peer handler 16597 */ 16598 A_UINT32 rxdesc_bmc_msdus_inv_peer; 16599 /* Number of MSDUs dropped due to no first MSDU flag */ 16600 A_UINT32 rxdesc_no_1st_msdu; 16601 /* Number of MSDUs dropped due to ring overflow */ 16602 A_UINT32 msdu_drop_ring_ov; 16603 /* Number of MSDUs dropped due to FC mismatch */ 16604 A_UINT32 msdu_drop_fc_mismatch; 16605 /* Number of MSDUs dropped due to mgt frame in Remote ring */ 16606 A_UINT32 msdu_drop_mgmt_remote_ring; 16607 /* Number of MSDUs dropped due to errors not reported in attention word */ 16608 A_UINT32 msdu_drop_misc; 16609 /* Number of MSDUs go to offload before reorder */ 16610 A_UINT32 offload_msdu_wal; 16611 /* Number of data frame dropped by offload after reorder */ 16612 A_UINT32 offload_msdu_reorder; 16613 /* Number of MPDUs with sequence number in the past and within the BA window */ 16614 A_UINT32 dup_past_within_window; 16615 /* Number of MPDUs with sequence number in the past and outside the BA window */ 16616 A_UINT32 dup_past_outside_window; 16617 /* Number of MSDUs with decrypt/MIC error */ 16618 A_UINT32 rxdesc_err_decrypt_mic; 16619 /* Number of data MSDUs received on both local and remote rings */ 16620 A_UINT32 data_msdus_on_both_rings; 16621 /* MPDUs never filled */ 16622 A_UINT32 holes_not_filled; 16623 }; 16624 16625 16626 /* 16627 * Rx Remote buffer statistics 16628 * NB: all the fields must be defined in 4 octets size. 16629 */ 16630 struct rx_remote_buffer_mgmt_stats { 16631 /* Total number of MSDUs reaped for Rx processing */ 16632 A_UINT32 remote_reaped; 16633 /* MSDUs recycled within firmware */ 16634 A_UINT32 remote_recycled; 16635 /* MSDUs stored by Data Rx */ 16636 A_UINT32 data_rx_msdus_stored; 16637 /* Number of HTT indications from WAL Rx MSDU */ 16638 A_UINT32 wal_rx_ind; 16639 /* Number of unconsumed HTT indications from WAL Rx MSDU */ 16640 A_UINT32 wal_rx_ind_unconsumed; 16641 /* Number of HTT indications from Data Rx MSDU */ 16642 A_UINT32 data_rx_ind; 16643 /* Number of unconsumed HTT indications from Data Rx MSDU */ 16644 A_UINT32 data_rx_ind_unconsumed; 16645 /* Number of HTT indications from ATHBUF */ 16646 A_UINT32 athbuf_rx_ind; 16647 /* Number of remote buffers requested for refill */ 16648 A_UINT32 refill_buf_req; 16649 /* Number of remote buffers filled by the host */ 16650 A_UINT32 refill_buf_rsp; 16651 /* Number of times MAC hw_index = f/w write_index */ 16652 A_INT32 mac_no_bufs; 16653 /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ 16654 A_INT32 fw_indices_equal; 16655 /* Number of times f/w finds no buffers to post */ 16656 A_INT32 host_no_bufs; 16657 }; 16658 16659 /* 16660 * TXBF MU/SU packets and NDPA statistics 16661 * NB: all the fields must be defined in 4 octets size. 16662 */ 16663 struct rx_txbf_musu_ndpa_pkts_stats { 16664 A_UINT32 number_mu_pkts; /* number of TXBF MU packets received */ 16665 A_UINT32 number_su_pkts; /* number of TXBF SU packets received */ 16666 A_UINT32 txbf_directed_ndpa_count; /* number of TXBF directed NDPA */ 16667 A_UINT32 txbf_ndpa_retry_count; /* number of TXBF retried NDPA */ 16668 A_UINT32 txbf_total_ndpa_count; /* total number of TXBF NDPA */ 16669 16670 A_UINT32 reserved[3]; /* must be set to 0x0 */ 16671 }; 16672 16673 16674 /* 16675 * htt_dbg_stats_status - 16676 * present - The requested stats have been delivered in full. 16677 * This indicates that either the stats information was contained 16678 * in its entirety within this message, or else this message 16679 * completes the delivery of the requested stats info that was 16680 * partially delivered through earlier STATS_CONF messages. 16681 * partial - The requested stats have been delivered in part. 16682 * One or more subsequent STATS_CONF messages with the same 16683 * cookie value will be sent to deliver the remainder of the 16684 * information. 16685 * error - The requested stats could not be delivered, for example due 16686 * to a shortage of memory to construct a message holding the 16687 * requested stats. 16688 * invalid - The requested stat type is either not recognized, or the 16689 * target is configured to not gather the stats type in question. 16690 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16691 * series_done - This special value indicates that no further stats info 16692 * elements are present within a series of stats info elems 16693 * (within a stats upload confirmation message). 16694 */ 16695 enum htt_dbg_stats_status { 16696 HTT_DBG_STATS_STATUS_PRESENT = 0, 16697 HTT_DBG_STATS_STATUS_PARTIAL = 1, 16698 HTT_DBG_STATS_STATUS_ERROR = 2, 16699 HTT_DBG_STATS_STATUS_INVALID = 3, 16700 16701 16702 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 16703 }; 16704 16705 /** 16706 * @brief target -> host statistics upload 16707 * 16708 * MSG_TYPE => HTT_T2H_MSG_TYPE_STATS_CONF 16709 * 16710 * @details 16711 * The following field definitions describe the format of the HTT target 16712 * to host stats upload confirmation message. 16713 * The message contains a cookie echoed from the HTT host->target stats 16714 * upload request, which identifies which request the confirmation is 16715 * for, and a series of tag-length-value stats information elements. 16716 * The tag-length header for each stats info element also includes a 16717 * status field, to indicate whether the request for the stat type in 16718 * question was fully met, partially met, unable to be met, or invalid 16719 * (if the stat type in question is disabled in the target). 16720 * A special value of all 1's in this status field is used to indicate 16721 * the end of the series of stats info elements. 16722 * 16723 * 16724 * |31 16|15 8|7 5|4 0| 16725 * |------------------------------------------------------------| 16726 * | reserved | msg type | 16727 * |------------------------------------------------------------| 16728 * | cookie LSBs | 16729 * |------------------------------------------------------------| 16730 * | cookie MSBs | 16731 * |------------------------------------------------------------| 16732 * | stats entry length | reserved | S |stat type| 16733 * |------------------------------------------------------------| 16734 * | | 16735 * | type-specific stats info | 16736 * | | 16737 * |------------------------------------------------------------| 16738 * | stats entry length | reserved | S |stat type| 16739 * |------------------------------------------------------------| 16740 * | | 16741 * | type-specific stats info | 16742 * | | 16743 * |------------------------------------------------------------| 16744 * | n/a | reserved | 111 | n/a | 16745 * |------------------------------------------------------------| 16746 * Header fields: 16747 * - MSG_TYPE 16748 * Bits 7:0 16749 * Purpose: identifies this is a statistics upload confirmation message 16750 * Value: 0x9 (HTT_T2H_MSG_TYPE_STATS_CONF) 16751 * - COOKIE_LSBS 16752 * Bits 31:0 16753 * Purpose: Provide a mechanism to match a target->host stats confirmation 16754 * message with its preceding host->target stats request message. 16755 * Value: LSBs of the opaque cookie specified by the host-side requestor 16756 * - COOKIE_MSBS 16757 * Bits 31:0 16758 * Purpose: Provide a mechanism to match a target->host stats confirmation 16759 * message with its preceding host->target stats request message. 16760 * Value: MSBs of the opaque cookie specified by the host-side requestor 16761 * 16762 * Stats Information Element tag-length header fields: 16763 * - STAT_TYPE 16764 * Bits 4:0 16765 * Purpose: identifies the type of statistics info held in the 16766 * following information element 16767 * Value: htt_dbg_stats_type 16768 * - STATUS 16769 * Bits 7:5 16770 * Purpose: indicate whether the requested stats are present 16771 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 16772 * the completion of the stats entry series 16773 * - LENGTH 16774 * Bits 31:16 16775 * Purpose: indicate the stats information size 16776 * Value: This field specifies the number of bytes of stats information 16777 * that follows the element tag-length header. 16778 * It is expected but not required that this length is a multiple of 16779 * 4 bytes. Even if the length is not an integer multiple of 4, the 16780 * subsequent stats entry header will begin on a 4-byte aligned 16781 * boundary. 16782 */ 16783 #define HTT_T2H_STATS_COOKIE_SIZE 8 16784 16785 #define HTT_T2H_STATS_CONF_TAIL_SIZE 4 16786 16787 #define HTT_T2H_STATS_CONF_HDR_SIZE 4 16788 16789 #define HTT_T2H_STATS_CONF_TLV_HDR_SIZE 4 16790 16791 #define HTT_T2H_STATS_CONF_TLV_TYPE_M 0x0000001f 16792 #define HTT_T2H_STATS_CONF_TLV_TYPE_S 0 16793 #define HTT_T2H_STATS_CONF_TLV_STATUS_M 0x000000e0 16794 #define HTT_T2H_STATS_CONF_TLV_STATUS_S 5 16795 #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000 16796 #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16 16797 16798 #define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ 16799 do { \ 16800 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ 16801 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ 16802 } while (0) 16803 #define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ 16804 (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ 16805 HTT_T2H_STATS_CONF_TLV_TYPE_S) 16806 16807 #define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ 16808 do { \ 16809 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ 16810 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ 16811 } while (0) 16812 #define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ 16813 (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ 16814 HTT_T2H_STATS_CONF_TLV_STATUS_S) 16815 16816 #define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ 16817 do { \ 16818 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ 16819 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ 16820 } while (0) 16821 #define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ 16822 (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ 16823 HTT_T2H_STATS_CONF_TLV_LENGTH_S) 16824 16825 #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18 16826 #define HTT_MAX_AGGR 64 16827 #define HTT_HL_MAX_AGGR 18 16828 16829 /** 16830 * @brief host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 16831 * 16832 * MSG_TYPE => HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG 16833 * 16834 * @details 16835 * The following field definitions describe the format of the HTT host 16836 * to target frag_desc/msdu_ext bank configuration message. 16837 * The message contains the based address and the min and max id of the 16838 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 16839 * MSDU_EXT/FRAG_DESC. 16840 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 16841 * In peregrine the firmware will use fragment_desc_ptr but in WIFI2.0 16842 * the hardware does the mapping/translation. 16843 * 16844 * Total banks that can be configured is configured to 16. 16845 * 16846 * This should be called before any TX has be initiated by the HTT 16847 * 16848 * |31 16|15 8|7 5|4 0| 16849 * |------------------------------------------------------------| 16850 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 16851 * |------------------------------------------------------------| 16852 * | BANK0_BASE_ADDRESS (bits 31:0) | 16853 #if HTT_PADDR64 16854 * | BANK0_BASE_ADDRESS (bits 63:32) | 16855 #endif 16856 * |------------------------------------------------------------| 16857 * | ... | 16858 * |------------------------------------------------------------| 16859 * | BANK15_BASE_ADDRESS (bits 31:0) | 16860 #if HTT_PADDR64 16861 * | BANK15_BASE_ADDRESS (bits 63:32) | 16862 #endif 16863 * |------------------------------------------------------------| 16864 * | BANK0_MAX_ID | BANK0_MIN_ID | 16865 * |------------------------------------------------------------| 16866 * | ... | 16867 * |------------------------------------------------------------| 16868 * | BANK15_MAX_ID | BANK15_MIN_ID | 16869 * |------------------------------------------------------------| 16870 * Header fields: 16871 * - MSG_TYPE 16872 * Bits 7:0 16873 * Value: 0x6 (HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG) 16874 * for systems with 64-bit format for bus addresses: 16875 * - BANKx_BASE_ADDRESS_LO 16876 * Bits 31:0 16877 * Purpose: Provide a mechanism to specify the base address of the 16878 * MSDU_EXT bank physical/bus address. 16879 * Value: lower 4 bytes of MSDU_EXT bank physical / bus address 16880 * - BANKx_BASE_ADDRESS_HI 16881 * Bits 31:0 16882 * Purpose: Provide a mechanism to specify the base address of the 16883 * MSDU_EXT bank physical/bus address. 16884 * Value: higher 4 bytes of MSDU_EXT bank physical / bus address 16885 * for systems with 32-bit format for bus addresses: 16886 * - BANKx_BASE_ADDRESS 16887 * Bits 31:0 16888 * Purpose: Provide a mechanism to specify the base address of the 16889 * MSDU_EXT bank physical/bus address. 16890 * Value: MSDU_EXT bank physical / bus address 16891 * - BANKx_MIN_ID 16892 * Bits 15:0 16893 * Purpose: Provide a mechanism to specify the min index that needs to 16894 * mapped. 16895 * - BANKx_MAX_ID 16896 * Bits 31:16 16897 * Purpose: Provide a mechanism to specify the max index that needs to 16898 * mapped. 16899 * 16900 */ 16901 16902 /** @todo Compress the fields to fit MAX HTT Message size, until then configure to a 16903 * safe value. 16904 * @note MAX supported banks is 16. 16905 */ 16906 #define HTT_TX_MSDU_EXT_BANK_MAX 4 16907 16908 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_M 0x300 16909 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_S 8 16910 16911 #define HTT_H2T_FRAG_DESC_BANK_SWAP_M 0x400 16912 #define HTT_H2T_FRAG_DESC_BANK_SWAP_S 10 16913 16914 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M 0xff0000 16915 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S 16 16916 16917 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M 0xff000000 16918 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S 24 16919 16920 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M 0xffff 16921 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S 0 16922 16923 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000 16924 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16 16925 16926 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ 16927 do { \ 16928 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ 16929 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ 16930 } while (0) 16931 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ 16932 (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> HTT_H2T_FRAG_DESC_BANK_PDEVID_S) 16933 16934 #define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ 16935 do { \ 16936 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value); \ 16937 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S); \ 16938 } while (0) 16939 #define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ 16940 (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> HTT_H2T_FRAG_DESC_BANK_SWAP_S) 16941 16942 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ 16943 do { \ 16944 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ 16945 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ 16946 } while (0) 16947 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ 16948 (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) 16949 16950 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ 16951 do { \ 16952 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ 16953 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ 16954 } while (0) 16955 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ 16956 (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) 16957 16958 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ 16959 do { \ 16960 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ 16961 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ 16962 } while (0) 16963 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ 16964 (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) 16965 16966 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ 16967 do { \ 16968 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ 16969 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ 16970 } while (0) 16971 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ 16972 (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) 16973 16974 16975 /* 16976 * TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T: 16977 * This macro defines a htt_tx_frag_descXXX_bank_cfg_t in which any physical 16978 * addresses are stored in a XXX-bit field. 16979 * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and 16980 * htt_tx_frag_desc64_bank_cfg_t structs. 16981 */ 16982 #define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ 16983 _paddr_bits_, \ 16984 _paddr__bank_base_address_) \ 16985 PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ 16986 /** word 0 \ 16987 * msg_type: 8, \ 16988 * pdev_id: 2, \ 16989 * swap: 1, \ 16990 * reserved0: 5, \ 16991 * num_banks: 8, \ 16992 * desc_size: 8; \ 16993 */ \ 16994 A_UINT32 word0; \ 16995 /* \ 16996 * If bank_base_address is 64 bits, the upper / lower halves are stored \ 16997 * in little-endian order (bytes 0-3 in the first A_UINT32, bytes 4-7 in \ 16998 * the second A_UINT32). \ 16999 */ \ 17000 _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ 17001 A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ 17002 } POSTPACK 17003 /* define htt_tx_frag_desc32_bank_cfg_t */ 17004 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address)); 17005 /* define htt_tx_frag_desc64_bank_cfg_t */ 17006 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); 17007 /* 17008 * Make htt_tx_frag_desc_bank_cfg_t be an alias for either 17009 * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t 17010 */ 17011 #if HTT_PADDR64 17012 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t 17013 #else 17014 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t 17015 #endif 17016 17017 /** 17018 * @brief target -> host HTT TX Credit total count update message definition 17019 * 17020 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND 17021 * 17022 *|31 16|15|14 9| 8 |7 0 | 17023 *|---------------------+--+----------+-------+----------| 17024 *|cur htt credit delta | Q| reserved | sign | msg type | 17025 *|------------------------------------------------------| 17026 * 17027 * Header fields: 17028 * - MSG_TYPE 17029 * Bits 7:0 17030 * Purpose: identifies this as a htt tx credit delta update message 17031 * Value: 0xf (HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND) 17032 * - SIGN 17033 * Bits 8 17034 * identifies whether credit delta is positive or negative 17035 * Value: 17036 * - 0x0: credit delta is positive, rebalance in some buffers 17037 * - 0x1: credit delta is negative, rebalance out some buffers 17038 * - reserved 17039 * Bits 14:9 17040 * Value: 0x0 17041 * - TXQ_GRP 17042 * Bit 15 17043 * Purpose: indicates whether any tx queue group information elements 17044 * are appended to the tx credit update message 17045 * Value: 0 -> no tx queue group information element is present 17046 * 1 -> a tx queue group information element immediately follows 17047 * - DELTA_COUNT 17048 * Bits 31:16 17049 * Purpose: Specify current htt credit delta absolute count 17050 */ 17051 17052 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 17053 #define HTT_TX_CREDIT_SIGN_BIT_S 8 17054 #define HTT_TX_CREDIT_TXQ_GRP_M 0x00008000 17055 #define HTT_TX_CREDIT_TXQ_GRP_S 15 17056 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 17057 #define HTT_TX_CREDIT_DELTA_ABS_S 16 17058 17059 17060 #define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ 17061 do { \ 17062 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ 17063 (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ 17064 } while (0) 17065 17066 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ 17067 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) 17068 17069 #define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ 17070 do { \ 17071 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ 17072 (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ 17073 } while (0) 17074 17075 #define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ 17076 (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) 17077 17078 #define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ 17079 do { \ 17080 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ 17081 (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ 17082 } while (0) 17083 17084 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ 17085 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) 17086 17087 17088 #define HTT_TX_CREDIT_MSG_BYTES 4 17089 17090 #define HTT_TX_CREDIT_SIGN_BIT_POSITIVE 0x0 17091 #define HTT_TX_CREDIT_SIGN_BIT_NEGATIVE 0x1 17092 17093 17094 /** 17095 * @brief HTT WDI_IPA Operation Response Message 17096 * 17097 * MSG_TYPE => HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE 17098 * 17099 * @details 17100 * HTT WDI_IPA Operation Response message is sent by target 17101 * to host confirming suspend or resume operation. 17102 * |31 24|23 16|15 8|7 0| 17103 * |----------------+----------------+----------------+----------------| 17104 * | op_code | Rsvd | msg_type | 17105 * |-------------------------------------------------------------------| 17106 * | Rsvd | Response len | 17107 * |-------------------------------------------------------------------| 17108 * | | 17109 * | Response-type specific info | 17110 * | | 17111 * | | 17112 * |-------------------------------------------------------------------| 17113 * Header fields: 17114 * - MSG_TYPE 17115 * Bits 7:0 17116 * Purpose: Identifies this as WDI_IPA Operation Response message 17117 * value: = 0x14 (HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE) 17118 * - OP_CODE 17119 * Bits 31:16 17120 * Purpose: Identifies the operation target is responding to (e.g. TX suspend) 17121 * value: = enum htt_wdi_ipa_op_code 17122 * - RSP_LEN 17123 * Bits 16:0 17124 * Purpose: length for the response-type specific info 17125 * value: = length in bytes for response-type specific info 17126 * For example, if OP_CODE == HTT_WDI_IPA_OPCODE_DBG_STATS, the 17127 * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t). 17128 */ 17129 17130 PREPACK struct htt_wdi_ipa_op_response_t 17131 { 17132 /* DWORD 0: flags and meta-data */ 17133 A_UINT32 17134 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17135 reserved1: 8, 17136 op_code: 16; 17137 A_UINT32 17138 rsp_len: 16, 17139 reserved2: 16; 17140 } POSTPACK; 17141 17142 #define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ 17143 17144 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000 17145 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16 17146 17147 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff 17148 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0 17149 17150 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ 17151 (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) 17152 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ 17153 do { \ 17154 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ 17155 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ 17156 } while (0) 17157 17158 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ 17159 (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) 17160 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ 17161 do { \ 17162 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ 17163 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ 17164 } while (0) 17165 17166 17167 enum htt_phy_mode { 17168 htt_phy_mode_11a = 0, 17169 htt_phy_mode_11g = 1, 17170 htt_phy_mode_11b = 2, 17171 htt_phy_mode_11g_only = 3, 17172 htt_phy_mode_11na_ht20 = 4, 17173 htt_phy_mode_11ng_ht20 = 5, 17174 htt_phy_mode_11na_ht40 = 6, 17175 htt_phy_mode_11ng_ht40 = 7, 17176 htt_phy_mode_11ac_vht20 = 8, 17177 htt_phy_mode_11ac_vht40 = 9, 17178 htt_phy_mode_11ac_vht80 = 10, 17179 htt_phy_mode_11ac_vht20_2g = 11, 17180 htt_phy_mode_11ac_vht40_2g = 12, 17181 htt_phy_mode_11ac_vht80_2g = 13, 17182 htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ 17183 htt_phy_mode_11ac_vht160 = 15, 17184 17185 htt_phy_mode_max, 17186 }; 17187 17188 /** 17189 * @brief target -> host HTT channel change indication 17190 * 17191 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CHANGE 17192 * 17193 * @details 17194 * Specify when a channel change occurs. 17195 * This allows the host to precisely determine which rx frames arrived 17196 * on the old channel and which rx frames arrived on the new channel. 17197 * 17198 *|31 |7 0 | 17199 *|-------------------------------------------+----------| 17200 *| reserved | msg type | 17201 *|------------------------------------------------------| 17202 *| primary_chan_center_freq_mhz | 17203 *|------------------------------------------------------| 17204 *| contiguous_chan1_center_freq_mhz | 17205 *|------------------------------------------------------| 17206 *| contiguous_chan2_center_freq_mhz | 17207 *|------------------------------------------------------| 17208 *| phy_mode | 17209 *|------------------------------------------------------| 17210 * 17211 * Header fields: 17212 * - MSG_TYPE 17213 * Bits 7:0 17214 * Purpose: identifies this as a htt channel change indication message 17215 * Value: 0x15 (HTT_T2H_MSG_TYPE_CHAN_CHANGE) 17216 * - PRIMARY_CHAN_CENTER_FREQ_MHZ 17217 * Bits 31:0 17218 * Purpose: identify the (center of the) new 20 MHz primary channel 17219 * Value: center frequency of the 20 MHz primary channel, in MHz units 17220 * - CONTIG_CHAN1_CENTER_FREQ_MHZ 17221 * Bits 31:0 17222 * Purpose: identify the (center of the) contiguous frequency range 17223 * comprising the new channel. 17224 * For example, if the new channel is a 80 MHz channel extending 17225 * 60 MHz beyond the primary channel, this field would be 30 larger 17226 * than the primary channel center frequency field. 17227 * Value: center frequency of the contiguous frequency range comprising 17228 * the full channel in MHz units 17229 * (80+80 channels also use the CONTIG_CHAN2 field) 17230 * - CONTIG_CHAN2_CENTER_FREQ_MHZ 17231 * Bits 31:0 17232 * Purpose: Identify the (center of the) 80 MHz extension frequency range 17233 * within a VHT 80+80 channel. 17234 * This field is only relevant for VHT 80+80 channels. 17235 * Value: center frequency of the 80 MHz extension channel in a VHT 80+80 17236 * channel (arbitrary value for cases besides VHT 80+80) 17237 * - PHY_MODE 17238 * Bits 31:0 17239 * Purpose: specify the PHY channel's type (legacy vs. HT vs. VHT), width, 17240 * and band 17241 * Value: htt_phy_mode enum value 17242 */ 17243 17244 PREPACK struct htt_chan_change_t 17245 { 17246 /* DWORD 0: flags and meta-data */ 17247 A_UINT32 17248 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17249 reserved1: 24; 17250 A_UINT32 primary_chan_center_freq_mhz; 17251 A_UINT32 contig_chan1_center_freq_mhz; 17252 A_UINT32 contig_chan2_center_freq_mhz; 17253 A_UINT32 phy_mode; 17254 } POSTPACK; 17255 /* 17256 * Due to historical / backwards-compatibility reasons, maintain the 17257 * below htt_chan_change_msg struct definition, which needs to be 17258 * consistent with the above htt_chan_change_t struct definition 17259 * (aside from the htt_chan_change_t definition including the msg_type 17260 * dword within the message, and the htt_chan_change_msg only containing 17261 * the payload of the message that follows the msg_type dword). 17262 */ 17263 PREPACK struct htt_chan_change_msg { 17264 A_UINT32 chan_mhz; /* frequency in mhz */ 17265 A_UINT32 band_center_freq1; /* Center frequency 1 in MHz */ 17266 A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ 17267 A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */ 17268 } POSTPACK; 17269 17270 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff 17271 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S 0 17272 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M 0xffffffff 17273 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S 0 17274 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M 0xffffffff 17275 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S 0 17276 #define HTT_CHAN_CHANGE_PHY_MODE_M 0xffffffff 17277 #define HTT_CHAN_CHANGE_PHY_MODE_S 0 17278 17279 17280 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ 17281 do { \ 17282 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value);\ 17283 (word) |= (value) << HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ 17284 } while (0) 17285 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ 17286 (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ 17287 >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) 17288 17289 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ 17290 do { \ 17291 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value);\ 17292 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ 17293 } while (0) 17294 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ 17295 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ 17296 >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) 17297 17298 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ 17299 do { \ 17300 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value);\ 17301 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ 17302 } while (0) 17303 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ 17304 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ 17305 >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) 17306 17307 #define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ 17308 do { \ 17309 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value);\ 17310 (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ 17311 } while (0) 17312 #define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ 17313 (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ 17314 >> HTT_CHAN_CHANGE_PHY_MODE_S) 17315 17316 #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t) 17317 17318 17319 /** 17320 * @brief rx offload packet error message 17321 * 17322 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR 17323 * 17324 * @details 17325 * HTT_RX_OFLD_PKT_ERR message is sent by target to host to indicate err 17326 * of target payload like mic err. 17327 * 17328 * |31 24|23 16|15 8|7 0| 17329 * |----------------+----------------+----------------+----------------| 17330 * | tid | vdev_id | msg_sub_type | msg_type | 17331 * |-------------------------------------------------------------------| 17332 * : (sub-type dependent content) : 17333 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 17334 * Header fields: 17335 * - msg_type 17336 * Bits 7:0 17337 * Purpose: Identifies this as HTT_RX_OFLD_PKT_ERR message 17338 * value: 0x16 (HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR) 17339 * - msg_sub_type 17340 * Bits 15:8 17341 * Purpose: Identifies which type of rx error is reported by this message 17342 * value: htt_rx_ofld_pkt_err_type 17343 * - vdev_id 17344 * Bits 23:16 17345 * Purpose: Identifies which vdev received the erroneous rx frame 17346 * value: 17347 * - tid 17348 * Bits 31:24 17349 * Purpose: Identifies the traffic type of the rx frame 17350 * value: 17351 * 17352 * - The payload fields used if the sub-type == MIC error are shown below. 17353 * Note - MIC err is per MSDU, while PN is per MPDU. 17354 * The FW will discard the whole MPDU if any MSDU within the MPDU is marked 17355 * with MIC err in A-MSDU case, so FW will send only one HTT message 17356 * with the PN of this MPDU attached to indicate MIC err for one MPDU 17357 * instead of sending separate HTT messages for each wrong MSDU within 17358 * the MPDU. 17359 * 17360 * |31 24|23 16|15 8|7 0| 17361 * |----------------+----------------+----------------+----------------| 17362 * | Rsvd | key_id | peer_id | 17363 * |-------------------------------------------------------------------| 17364 * | receiver MAC addr 31:0 | 17365 * |-------------------------------------------------------------------| 17366 * | Rsvd | receiver MAC addr 47:32 | 17367 * |-------------------------------------------------------------------| 17368 * | transmitter MAC addr 31:0 | 17369 * |-------------------------------------------------------------------| 17370 * | Rsvd | transmitter MAC addr 47:32 | 17371 * |-------------------------------------------------------------------| 17372 * | PN 31:0 | 17373 * |-------------------------------------------------------------------| 17374 * | Rsvd | PN 47:32 | 17375 * |-------------------------------------------------------------------| 17376 * - peer_id 17377 * Bits 15:0 17378 * Purpose: identifies which peer is frame is from 17379 * value: 17380 * - key_id 17381 * Bits 23:16 17382 * Purpose: identifies key_id of rx frame 17383 * value: 17384 * - RA_31_0 (receiver MAC addr 31:0) 17385 * Bits 31:0 17386 * Purpose: identifies by MAC address which vdev received the frame 17387 * value: MAC address lower 4 bytes 17388 * - RA_47_32 (receiver MAC addr 47:32) 17389 * Bits 15:0 17390 * Purpose: identifies by MAC address which vdev received the frame 17391 * value: MAC address upper 2 bytes 17392 * - TA_31_0 (transmitter MAC addr 31:0) 17393 * Bits 31:0 17394 * Purpose: identifies by MAC address which peer transmitted the frame 17395 * value: MAC address lower 4 bytes 17396 * - TA_47_32 (transmitter MAC addr 47:32) 17397 * Bits 15:0 17398 * Purpose: identifies by MAC address which peer transmitted the frame 17399 * value: MAC address upper 2 bytes 17400 * - PN_31_0 17401 * Bits 31:0 17402 * Purpose: Identifies pn of rx frame 17403 * value: PN lower 4 bytes 17404 * - PN_47_32 17405 * Bits 15:0 17406 * Purpose: Identifies pn of rx frame 17407 * value: 17408 * TKIP or CCMP: PN upper 2 bytes 17409 * WAPI: PN bytes 6:5 (bytes 15:7 not included in this message) 17410 */ 17411 17412 enum htt_rx_ofld_pkt_err_type { 17413 HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, 17414 HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, 17415 }; 17416 17417 /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */ 17418 #define HTT_RX_OFLD_PKT_ERR_HDR_BYTES 4 17419 17420 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M 0x0000ff00 17421 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S 8 17422 17423 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_M 0x00ff0000 17424 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_S 16 17425 17426 #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000 17427 #define HTT_RX_OFLD_PKT_ERR_TID_S 24 17428 17429 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ 17430 (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ 17431 >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) 17432 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ 17433 do { \ 17434 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ 17435 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ 17436 } while (0) 17437 17438 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ 17439 (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) 17440 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ 17441 do { \ 17442 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ 17443 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ 17444 } while (0) 17445 17446 #define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ 17447 (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) 17448 #define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ 17449 do { \ 17450 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ 17451 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ 17452 } while (0) 17453 17454 /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */ 17455 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28 17456 17457 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M 0x0000ffff 17458 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S 0 17459 17460 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M 0x00ff0000 17461 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S 16 17462 17463 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M 0xffffffff 17464 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S 0 17465 17466 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M 0x0000ffff 17467 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S 0 17468 17469 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M 0xffffffff 17470 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S 0 17471 17472 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M 0x0000ffff 17473 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S 0 17474 17475 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M 0xffffffff 17476 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S 0 17477 17478 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff 17479 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0 17480 17481 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ 17482 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ 17483 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) 17484 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ 17485 do { \ 17486 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ 17487 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ 17488 } while (0) 17489 17490 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ 17491 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ 17492 HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) 17493 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ 17494 do { \ 17495 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ 17496 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ 17497 } while (0) 17498 17499 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ 17500 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ 17501 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) 17502 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ 17503 do { \ 17504 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ 17505 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ 17506 } while (0) 17507 17508 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ 17509 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ 17510 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) 17511 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ 17512 do { \ 17513 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ 17514 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ 17515 } while (0) 17516 17517 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ 17518 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ 17519 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) 17520 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ 17521 do { \ 17522 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ 17523 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ 17524 } while (0) 17525 17526 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ 17527 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ 17528 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) 17529 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ 17530 do { \ 17531 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ 17532 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ 17533 } while (0) 17534 17535 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ 17536 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ 17537 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) 17538 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ 17539 do { \ 17540 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ 17541 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ 17542 } while (0) 17543 17544 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ 17545 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ 17546 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) 17547 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ 17548 do { \ 17549 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ 17550 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ 17551 } while (0) 17552 17553 /** 17554 * @brief target -> host peer rate report message 17555 * 17556 * MSG_TYPE => HTT_T2H_MSG_TYPE_RATE_REPORT 17557 * 17558 * @details 17559 * HTT_T2H_MSG_TYPE_RATE_REPORT message is sent by target to host to indicate the 17560 * justified rate of all the peers. 17561 * 17562 * |31 24|23 16|15 8|7 0| 17563 * |----------------+----------------+----------------+----------------| 17564 * | peer_count | | msg_type | 17565 * |-------------------------------------------------------------------| 17566 * : Payload (variant number of peer rate report) : 17567 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 17568 * Header fields: 17569 * - msg_type 17570 * Bits 7:0 17571 * Purpose: Identifies this as HTT_T2H_MSG_TYPE_RATE_REPORT message. 17572 * value: 0x17 (HTT_T2H_MSG_TYPE_RATE_REPORT) 17573 * - reserved 17574 * Bits 15:8 17575 * Purpose: 17576 * value: 17577 * - peer_count 17578 * Bits 31:16 17579 * Purpose: Specify how many peer rate report elements are present in the payload. 17580 * value: 17581 * 17582 * Payload: 17583 * There are variant number of peer rate report follow the first 32 bits. 17584 * The peer rate report is defined as follows. 17585 * 17586 * |31 20|19 16|15 0| 17587 * |-----------------------+---------+---------------------------------|- 17588 * | reserved | phy | peer_id | \ 17589 * |-------------------------------------------------------------------| -> report #0 17590 * | rate | / 17591 * |-----------------------+---------+---------------------------------|- 17592 * | reserved | phy | peer_id | \ 17593 * |-------------------------------------------------------------------| -> report #1 17594 * | rate | / 17595 * |-----------------------+---------+---------------------------------|- 17596 * | reserved | phy | peer_id | \ 17597 * |-------------------------------------------------------------------| -> report #2 17598 * | rate | / 17599 * |-------------------------------------------------------------------|- 17600 * : : 17601 * : : 17602 * : : 17603 * :-------------------------------------------------------------------: 17604 * 17605 * - peer_id 17606 * Bits 15:0 17607 * Purpose: identify the peer 17608 * value: 17609 * - phy 17610 * Bits 19:16 17611 * Purpose: identify which phy is in use 17612 * value: 0=11b, 1=11a/g, 2=11n, 3=11ac. 17613 * Please see enum htt_peer_report_phy_type for detail. 17614 * - reserved 17615 * Bits 31:20 17616 * Purpose: 17617 * value: 17618 * - rate 17619 * Bits 31:0 17620 * Purpose: represent the justified rate of the peer specified by peer_id 17621 * value: 17622 */ 17623 17624 enum htt_peer_rate_report_phy_type { 17625 HTT_PEER_RATE_REPORT_11B = 0, 17626 HTT_PEER_RATE_REPORT_11A_G, 17627 HTT_PEER_RATE_REPORT_11N, 17628 HTT_PEER_RATE_REPORT_11AC, 17629 }; 17630 17631 #define HTT_PEER_RATE_REPORT_SIZE 8 17632 17633 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M 0xffff0000 17634 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S 16 17635 17636 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_M 0x0000ffff 17637 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_S 0 17638 17639 #define HTT_PEER_RATE_REPORT_MSG_PHY_M 0x000f0000 17640 #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16 17641 17642 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \ 17643 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ 17644 >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) 17645 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \ 17646 do { \ 17647 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ 17648 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ 17649 } while (0) 17650 17651 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \ 17652 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ 17653 >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) 17654 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \ 17655 do { \ 17656 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ 17657 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ 17658 } while (0) 17659 17660 #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \ 17661 (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ 17662 >> HTT_PEER_RATE_REPORT_MSG_PHY_S) 17663 #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \ 17664 do { \ 17665 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ 17666 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ 17667 } while (0) 17668 17669 /** 17670 * @brief target -> host flow pool map message 17671 * 17672 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_MAP 17673 * 17674 * @details 17675 * HTT_T2H_MSG_TYPE_FLOW_POOL_MAP message is sent by the target when setting up 17676 * a flow of descriptors. 17677 * 17678 * This message is in TLV format and indicates the parameters to be setup a 17679 * flow in the host. Each entry indicates that a particular flow ID is ready to 17680 * receive descriptors from a specified pool. 17681 * 17682 * The message would appear as follows: 17683 * 17684 * |31 24|23 16|15 8|7 0| 17685 * |----------------+----------------+----------------+----------------| 17686 * header | reserved | num_flows | msg_type | 17687 * |-------------------------------------------------------------------| 17688 * | | 17689 * : payload : 17690 * | | 17691 * |-------------------------------------------------------------------| 17692 * 17693 * The header field is one DWORD long and is interpreted as follows: 17694 * b'0:7 - msg_type: Set to 0x18 (HTT_T2H_MSG_TYPE_FLOW_POOL_MAP) 17695 * b'8-15 - num_flows: This will indicate the number of flows being setup in 17696 * this message 17697 * b'16-31 - reserved: These bits are reserved for future use 17698 * 17699 * Payload: 17700 * The payload would contain multiple objects of the following structure. Each 17701 * object represents a flow. 17702 * 17703 * |31 24|23 16|15 8|7 0| 17704 * |----------------+----------------+----------------+----------------| 17705 * header | reserved | num_flows | msg_type | 17706 * |-------------------------------------------------------------------| 17707 * payload0| flow_type | 17708 * |-------------------------------------------------------------------| 17709 * | flow_id | 17710 * |-------------------------------------------------------------------| 17711 * | reserved0 | flow_pool_id | 17712 * |-------------------------------------------------------------------| 17713 * | reserved1 | flow_pool_size | 17714 * |-------------------------------------------------------------------| 17715 * | reserved2 | 17716 * |-------------------------------------------------------------------| 17717 * payload1| flow_type | 17718 * |-------------------------------------------------------------------| 17719 * | flow_id | 17720 * |-------------------------------------------------------------------| 17721 * | reserved0 | flow_pool_id | 17722 * |-------------------------------------------------------------------| 17723 * | reserved1 | flow_pool_size | 17724 * |-------------------------------------------------------------------| 17725 * | reserved2 | 17726 * |-------------------------------------------------------------------| 17727 * | . | 17728 * | . | 17729 * | . | 17730 * |-------------------------------------------------------------------| 17731 * 17732 * Each payload is 5 DWORDS long and is interpreted as follows: 17733 * dword0 - b'0:31 - flow_type: This indicates the type of the entity to which 17734 * this flow is associated. It can be VDEV, peer, 17735 * or tid (AC). Based on enum htt_flow_type. 17736 * 17737 * dword1 - b'0:31 - flow_id: Identifier for the flow corresponding to this 17738 * object. For flow_type vdev it is set to the 17739 * vdevid, for peer it is peerid and for tid, it is 17740 * tid_num. 17741 * 17742 * dword2 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being used 17743 * in the host for this flow 17744 * b'16:31 - reserved0: This field in reserved for the future. In case 17745 * we have a hierarchical implementation (HCM) of 17746 * pools, it can be used to indicate the ID of the 17747 * parent-pool. 17748 * 17749 * dword3 - b'0:15 - flow_pool_size: Size of the pool in number of descriptors. 17750 * Descriptors for this flow will be 17751 * allocated from this pool in the host. 17752 * b'16:31 - reserved1: This field in reserved for the future. In case 17753 * we have a hierarchical implementation of pools, 17754 * it can be used to indicate the max number of 17755 * descriptors in the pool. The b'0:15 can be used 17756 * to indicate min number of descriptors in the 17757 * HCM scheme. 17758 * 17759 * dword4 - b'0:31 - reserved2: This field in reserved for the future. In case 17760 * we have a hierarchical implementation of pools, 17761 * b'0:15 can be used to indicate the 17762 * priority-based borrowing (PBB) threshold of 17763 * the flow's pool. The b'16:31 are still left 17764 * reserved. 17765 */ 17766 17767 enum htt_flow_type { 17768 FLOW_TYPE_VDEV = 0, 17769 /* Insert new flow types above this line */ 17770 }; 17771 17772 PREPACK struct htt_flow_pool_map_payload_t { 17773 A_UINT32 flow_type; 17774 A_UINT32 flow_id; 17775 A_UINT32 flow_pool_id:16, 17776 reserved0:16; 17777 A_UINT32 flow_pool_size:16, 17778 reserved1:16; 17779 A_UINT32 reserved2; 17780 } POSTPACK; 17781 17782 #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32)) 17783 17784 #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \ 17785 (sizeof(struct htt_flow_pool_map_payload_t)) 17786 17787 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00 17788 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8 17789 17790 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_M 0xffffffff 17791 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_S 0 17792 17793 #define HTT_FLOW_POOL_MAP_FLOW_ID_M 0xffffffff 17794 #define HTT_FLOW_POOL_MAP_FLOW_ID_S 0 17795 17796 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M 0x0000ffff 17797 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S 0 17798 17799 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff 17800 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0 17801 17802 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ 17803 (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) 17804 17805 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ 17806 (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) 17807 17808 #define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ 17809 (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) 17810 17811 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ 17812 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ 17813 HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) 17814 17815 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ 17816 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ 17817 HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) 17818 17819 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ 17820 do { \ 17821 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ 17822 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ 17823 } while (0) 17824 17825 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ 17826 do { \ 17827 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ 17828 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ 17829 } while (0) 17830 17831 #define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ 17832 do { \ 17833 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ 17834 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ 17835 } while (0) 17836 17837 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ 17838 do { \ 17839 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ 17840 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ 17841 } while (0) 17842 17843 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ 17844 do { \ 17845 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ 17846 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ 17847 } while (0) 17848 17849 /** 17850 * @brief target -> host flow pool unmap message 17851 * 17852 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 17853 * 17854 * @details 17855 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP message is sent by the target when tearing 17856 * down a flow of descriptors. 17857 * This message indicates that for the flow (whose ID is provided) is wanting 17858 * to stop receiving descriptors. This flow ID corresponds to the ID of the 17859 * pool of descriptors from where descriptors are being allocated for this 17860 * flow. When a flow (and its pool) are unmapped, all the child-pools will also 17861 * be unmapped by the host. 17862 * 17863 * The message would appear as follows: 17864 * 17865 * |31 24|23 16|15 8|7 0| 17866 * |----------------+----------------+----------------+----------------| 17867 * | reserved0 | msg_type | 17868 * |-------------------------------------------------------------------| 17869 * | flow_type | 17870 * |-------------------------------------------------------------------| 17871 * | flow_id | 17872 * |-------------------------------------------------------------------| 17873 * | reserved1 | flow_pool_id | 17874 * |-------------------------------------------------------------------| 17875 * 17876 * The message is interpreted as follows: 17877 * dword0 - b'0:7 - msg_type: This will be set to 0x19 17878 * (HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP) 17879 * b'8:31 - reserved0: Reserved for future use 17880 * 17881 * dword1 - b'0:31 - flow_type: This indicates the type of the entity to which 17882 * this flow is associated. It can be VDEV, peer, 17883 * or tid (AC). Based on enum htt_flow_type. 17884 * 17885 * dword2 - b'0:31 - flow_id: Identifier for the flow corresponding to this 17886 * object. For flow_type vdev it is set to the 17887 * vdevid, for peer it is peerid and for tid, it is 17888 * tid_num. 17889 * 17890 * dword3 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being 17891 * used in the host for this flow 17892 * b'16:31 - reserved0: This field in reserved for the future. 17893 * 17894 */ 17895 17896 PREPACK struct htt_flow_pool_unmap_t { 17897 A_UINT32 msg_type:8, 17898 reserved0:24; 17899 A_UINT32 flow_type; 17900 A_UINT32 flow_id; 17901 A_UINT32 flow_pool_id:16, 17902 reserved1:16; 17903 } POSTPACK; 17904 17905 #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t)) 17906 17907 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M 0xffffffff 17908 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S 0 17909 17910 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_M 0xffffffff 17911 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_S 0 17912 17913 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff 17914 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0 17915 17916 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ 17917 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ 17918 HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) 17919 17920 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ 17921 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) 17922 17923 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ 17924 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ 17925 HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) 17926 17927 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ 17928 do { \ 17929 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ 17930 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ 17931 } while (0) 17932 17933 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ 17934 do { \ 17935 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ 17936 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ 17937 } while (0) 17938 17939 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ 17940 do { \ 17941 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ 17942 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ 17943 } while (0) 17944 17945 17946 /** 17947 * @brief target -> host SRING setup done message 17948 * 17949 * MSG_TYPE => HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 17950 * 17951 * @details 17952 * HTT_T2H_MSG_TYPE_SRING_SETUP_DONE message is sent by the target when 17953 * SRNG ring setup is done 17954 * 17955 * This message indicates whether the last setup operation is successful. 17956 * It will be sent to host when host set respose_required bit in 17957 * HTT_H2T_MSG_TYPE_SRING_SETUP. 17958 * The message would appear as follows: 17959 * 17960 * |31 24|23 16|15 8|7 0| 17961 * |--------------- +----------------+----------------+----------------| 17962 * | setup_status | ring_id | pdev_id | msg_type | 17963 * |-------------------------------------------------------------------| 17964 * 17965 * The message is interpreted as follows: 17966 * dword0 - b'0:7 - msg_type: This will be set to 0x1a 17967 * (HTT_T2H_MSG_TYPE_SRING_SETUP_DONE) 17968 * b'8:15 - pdev_id: 17969 * 0 (for rings at SOC/UMAC level), 17970 * 1/2/3 mac id (for rings at LMAC level) 17971 * b'16:23 - ring_id: Identify the ring which is set up 17972 * More details can be got from enum htt_srng_ring_id 17973 * b'24:31 - setup_status: Indicate status of setup operation 17974 * Refer to htt_ring_setup_status 17975 */ 17976 17977 PREPACK struct htt_sring_setup_done_t { 17978 A_UINT32 msg_type: 8, 17979 pdev_id: 8, 17980 ring_id: 8, 17981 setup_status: 8; 17982 } POSTPACK; 17983 17984 enum htt_ring_setup_status { 17985 htt_ring_setup_status_ok = 0, 17986 htt_ring_setup_status_error, 17987 }; 17988 17989 #define HTT_SRING_SETUP_DONE_SZ (sizeof(struct htt_sring_setup_done_t)) 17990 17991 #define HTT_SRING_SETUP_DONE_PDEV_ID_M 0x0000ff00 17992 #define HTT_SRING_SETUP_DONE_PDEV_ID_S 8 17993 #define HTT_SRING_SETUP_DONE_PDEV_ID_GET(_var) \ 17994 (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \ 17995 HTT_SRING_SETUP_DONE_PDEV_ID_S) 17996 #define HTT_SRING_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 17997 do { \ 17998 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \ 17999 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 18000 } while (0) 18001 18002 #define HTT_SRING_SETUP_DONE_RING_ID_M 0x00ff0000 18003 #define HTT_SRING_SETUP_DONE_RING_ID_S 16 18004 #define HTT_SRING_SETUP_DONE_RING_ID_GET(_var) \ 18005 (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \ 18006 HTT_SRING_SETUP_DONE_RING_ID_S) 18007 #define HTT_SRING_SETUP_DONE_RING_ID_SET(_var, _val) \ 18008 do { \ 18009 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \ 18010 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \ 18011 } while (0) 18012 18013 #define HTT_SRING_SETUP_DONE_STATUS_M 0xff000000 18014 #define HTT_SRING_SETUP_DONE_STATUS_S 24 18015 #define HTT_SRING_SETUP_DONE_STATUS_GET(_var) \ 18016 (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \ 18017 HTT_SRING_SETUP_DONE_STATUS_S) 18018 #define HTT_SRING_SETUP_DONE_STATUS_SET(_var, _val) \ 18019 do { \ 18020 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \ 18021 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \ 18022 } while (0) 18023 18024 18025 /** 18026 * @brief target -> flow map flow info 18027 * 18028 * MSG_TYPE => HTT_T2H_MSG_TYPE_MAP_FLOW_INFO 18029 * 18030 * @details 18031 * HTT TX map flow entry with tqm flow pointer 18032 * Sent from firmware to host to add tqm flow pointer in corresponding 18033 * flow search entry. Flow metadata is replayed back to host as part of this 18034 * struct to enable host to find the specific flow search entry 18035 * 18036 * The message would appear as follows: 18037 * 18038 * |31 28|27 18|17 14|13 8|7 0| 18039 * |-------+------------------------------------------+----------------| 18040 * | rsvd0 | fse_hsh_idx | msg_type | 18041 * |-------------------------------------------------------------------| 18042 * | rsvd1 | tid | peer_id | 18043 * |-------------------------------------------------------------------| 18044 * | tqm_flow_pntr_lo | 18045 * |-------------------------------------------------------------------| 18046 * | tqm_flow_pntr_hi | 18047 * |-------------------------------------------------------------------| 18048 * | fse_meta_data | 18049 * |-------------------------------------------------------------------| 18050 * 18051 * The message is interpreted as follows: 18052 * 18053 * dword0 - b'0:7 - msg_type: This will be set to 0x1b 18054 * (HTT_T2H_MSG_TYPE_MAP_FLOW_INFO) 18055 * 18056 * dword0 - b'8:27 - fse_hsh_idx: Flow search table index provided by host 18057 * for this flow entry 18058 * 18059 * dword0 - b'28:31 - rsvd0: Reserved for future use 18060 * 18061 * dword1 - b'0:13 - peer_id: Software peer id given by host during association 18062 * 18063 * dword1 - b'14:17 - tid 18064 * 18065 * dword1 - b'18:31 - rsvd1: Reserved for future use 18066 * 18067 * dword2 - b'0:31 - tqm_flow_pntr_lo: Lower 32 bits of TQM flow pointer 18068 * 18069 * dword3 - b'0:31 - tqm_flow_pntr_hi: Higher 32 bits of TQM flow pointer 18070 * 18071 * dword4 - b'0:31 - fse_meta_data: Replay back TX flow search metadata 18072 * given by host 18073 */ 18074 PREPACK struct htt_tx_map_flow_info { 18075 A_UINT32 18076 msg_type: 8, 18077 fse_hsh_idx: 20, 18078 rsvd0: 4; 18079 A_UINT32 18080 peer_id: 14, 18081 tid: 4, 18082 rsvd1: 14; 18083 A_UINT32 tqm_flow_pntr_lo; 18084 A_UINT32 tqm_flow_pntr_hi; 18085 struct htt_tx_flow_metadata fse_meta_data; 18086 } POSTPACK; 18087 18088 /* DWORD 0 */ 18089 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M 0x0fffff00 18090 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S 8 18091 18092 /* DWORD 1 */ 18093 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_M 0x00003fff 18094 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_S 0 18095 #define HTT_TX_MAP_FLOW_INFO_TID_M 0x0003c000 18096 #define HTT_TX_MAP_FLOW_INFO_TID_S 14 18097 18098 /* DWORD 0 */ 18099 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_GET(_var) \ 18100 (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \ 18101 HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S) 18102 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_SET(_var, _val) \ 18103 do { \ 18104 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \ 18105 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \ 18106 } while (0) 18107 18108 /* DWORD 1 */ 18109 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_GET(_var) \ 18110 (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \ 18111 HTT_TX_MAP_FLOW_INFO_PEER_ID_S) 18112 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_SET(_var, _val) \ 18113 do { \ 18114 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \ 18115 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \ 18116 } while (0) 18117 18118 #define HTT_TX_MAP_FLOW_INFO_TID_GET(_var) \ 18119 (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \ 18120 HTT_TX_MAP_FLOW_INFO_TID_S) 18121 #define HTT_TX_MAP_FLOW_INFO_TID_SET(_var, _val) \ 18122 do { \ 18123 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \ 18124 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \ 18125 } while (0) 18126 18127 18128 /* 18129 * htt_dbg_ext_stats_status - 18130 * present - The requested stats have been delivered in full. 18131 * This indicates that either the stats information was contained 18132 * in its entirety within this message, or else this message 18133 * completes the delivery of the requested stats info that was 18134 * partially delivered through earlier STATS_CONF messages. 18135 * partial - The requested stats have been delivered in part. 18136 * One or more subsequent STATS_CONF messages with the same 18137 * cookie value will be sent to deliver the remainder of the 18138 * information. 18139 * error - The requested stats could not be delivered, for example due 18140 * to a shortage of memory to construct a message holding the 18141 * requested stats. 18142 * invalid - The requested stat type is either not recognized, or the 18143 * target is configured to not gather the stats type in question. 18144 */ 18145 enum htt_dbg_ext_stats_status { 18146 HTT_DBG_EXT_STATS_STATUS_PRESENT = 0, 18147 HTT_DBG_EXT_STATS_STATUS_PARTIAL = 1, 18148 HTT_DBG_EXT_STATS_STATUS_ERROR = 2, 18149 HTT_DBG_EXT_STATS_STATUS_INVALID = 3, 18150 }; 18151 18152 /** 18153 * @brief target -> host ppdu stats upload 18154 * 18155 * MSG_TYPE => HTT_T2H_MSG_TYPE_PPDU_STATS_IND 18156 * 18157 * @details 18158 * The following field definitions describe the format of the HTT target 18159 * to host ppdu stats indication message. 18160 * 18161 * 18162 * |31 24|23 16|15 12|11 10|9 8|7 0 | 18163 * |-----------------------------+-------+-------+--------+---------------| 18164 * | payload_size | rsvd |pdev_id|mac_id | msg type | 18165 * |-------------+---------------+-------+-------+--------+---------------| 18166 * | tgt_private | ppdu_id | 18167 * |-------------+--------------------------------------------------------| 18168 * | Timestamp in us | 18169 * |----------------------------------------------------------------------| 18170 * | reserved | 18171 * |----------------------------------------------------------------------| 18172 * | type-specific stats info | 18173 * | (see htt_ppdu_stats.h) | 18174 * |----------------------------------------------------------------------| 18175 * Header fields: 18176 * - MSG_TYPE 18177 * Bits 7:0 18178 * Purpose: Identifies this is a PPDU STATS indication 18179 * message. 18180 * Value: 0x1d (HTT_T2H_MSG_TYPE_PPDU_STATS_IND) 18181 * - mac_id 18182 * Bits 9:8 18183 * Purpose: mac_id of this ppdu_id 18184 * Value: 0-3 18185 * - pdev_id 18186 * Bits 11:10 18187 * Purpose: pdev_id of this ppdu_id 18188 * Value: 0-3 18189 * 0 (for rings at SOC level), 18190 * 1/2/3 PDEV -> 0/1/2 18191 * - payload_size 18192 * Bits 31:16 18193 * Purpose: total tlv size 18194 * Value: payload_size in bytes 18195 */ 18196 #define HTT_T2H_PPDU_STATS_IND_HDR_SIZE 16 18197 18198 #define HTT_T2H_PPDU_STATS_MAC_ID_M 0x00000300 18199 #define HTT_T2H_PPDU_STATS_MAC_ID_S 8 18200 18201 #define HTT_T2H_PPDU_STATS_PDEV_ID_M 0x00000C00 18202 #define HTT_T2H_PPDU_STATS_PDEV_ID_S 10 18203 18204 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 18205 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 18206 18207 #define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF 18208 #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 18209 /* bits 31:24 are used by the target for internal purposes */ 18210 18211 #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ 18212 do { \ 18213 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_MAC_ID, value); \ 18214 (word) |= (value) << HTT_T2H_PPDU_STATS_MAC_ID_S; \ 18215 } while (0) 18216 #define HTT_T2H_PPDU_STATS_MAC_ID_GET(word) \ 18217 (((word) & HTT_T2H_PPDU_STATS_MAC_ID_M) >> \ 18218 HTT_T2H_PPDU_STATS_MAC_ID_S) 18219 18220 #define HTT_T2H_PPDU_STATS_PDEV_ID_SET(word, value) \ 18221 do { \ 18222 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PDEV_ID, value); \ 18223 (word) |= (value) << HTT_T2H_PPDU_STATS_PDEV_ID_S; \ 18224 } while (0) 18225 #define HTT_T2H_PPDU_STATS_PDEV_ID_GET(word) \ 18226 (((word) & HTT_T2H_PPDU_STATS_PDEV_ID_M) >> \ 18227 HTT_T2H_PPDU_STATS_PDEV_ID_S) 18228 18229 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_SET(word, value) \ 18230 do { \ 18231 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PAYLOAD_SIZE, value); \ 18232 (word) |= (value) << HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S; \ 18233 } while (0) 18234 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_GET(word) \ 18235 (((word) & HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M) >> \ 18236 HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S) 18237 18238 #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ 18239 do { \ 18240 /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ 18241 (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ 18242 } while (0) 18243 #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ 18244 (((word) & HTT_T2H_PPDU_STATS_PPDU_ID_M) >> \ 18245 HTT_T2H_PPDU_STATS_PPDU_ID_S) 18246 18247 /* htt_t2h_ppdu_stats_ind_hdr_t 18248 * This struct contains the fields within the header of the 18249 * HTT_T2H_PPDU_STATS_IND message, preceding the type-specific 18250 * stats info. 18251 * This struct assumes little-endian layout, and thus is only 18252 * suitable for use within processors known to be little-endian 18253 * (such as the target). 18254 * In contrast, the above macros provide endian-portable methods 18255 * to get and set the bitfields within this PPDU_STATS_IND header. 18256 */ 18257 typedef struct { 18258 A_UINT32 msg_type: 8, /* bits 7:0 */ 18259 mac_id: 2, /* bits 9:8 */ 18260 pdev_id: 2, /* bits 11:10 */ 18261 reserved1: 4, /* bits 15:12 */ 18262 payload_size: 16; /* bits 31:16 */ 18263 A_UINT32 ppdu_id; 18264 A_UINT32 timestamp_us; 18265 A_UINT32 reserved2; 18266 } htt_t2h_ppdu_stats_ind_hdr_t; 18267 18268 /** 18269 * @brief target -> host extended statistics upload 18270 * 18271 * MSG_TYPE => HTT_T2H_MSG_TYPE_EXT_STATS_CONF 18272 * 18273 * @details 18274 * The following field definitions describe the format of the HTT target 18275 * to host stats upload confirmation message. 18276 * The message contains a cookie echoed from the HTT host->target stats 18277 * upload request, which identifies which request the confirmation is 18278 * for, and a single stats can span over multiple HTT stats indication 18279 * due to the HTT message size limitation so every HTT ext stats indication 18280 * will have tag-length-value stats information elements. 18281 * The tag-length header for each HTT stats IND message also includes a 18282 * status field, to indicate whether the request for the stat type in 18283 * question was fully met, partially met, unable to be met, or invalid 18284 * (if the stat type in question is disabled in the target). 18285 * A Done bit 1's indicate the end of the of stats info elements. 18286 * 18287 * 18288 * |31 16|15 12|11|10 8|7 5|4 0| 18289 * |--------------------------------------------------------------| 18290 * | reserved | msg type | 18291 * |--------------------------------------------------------------| 18292 * | cookie LSBs | 18293 * |--------------------------------------------------------------| 18294 * | cookie MSBs | 18295 * |--------------------------------------------------------------| 18296 * | stats entry length | rsvd | D| S | stat type | 18297 * |--------------------------------------------------------------| 18298 * | type-specific stats info | 18299 * | (see htt_stats.h) | 18300 * |--------------------------------------------------------------| 18301 * Header fields: 18302 * - MSG_TYPE 18303 * Bits 7:0 18304 * Purpose: Identifies this is a extended statistics upload confirmation 18305 * message. 18306 * Value: 0x1c (HTT_T2H_MSG_TYPE_EXT_STATS_CONF) 18307 * - COOKIE_LSBS 18308 * Bits 31:0 18309 * Purpose: Provide a mechanism to match a target->host stats confirmation 18310 * message with its preceding host->target stats request message. 18311 * Value: LSBs of the opaque cookie specified by the host-side requestor 18312 * - COOKIE_MSBS 18313 * Bits 31:0 18314 * Purpose: Provide a mechanism to match a target->host stats confirmation 18315 * message with its preceding host->target stats request message. 18316 * Value: MSBs of the opaque cookie specified by the host-side requestor 18317 * 18318 * Stats Information Element tag-length header fields: 18319 * - STAT_TYPE 18320 * Bits 7:0 18321 * Purpose: identifies the type of statistics info held in the 18322 * following information element 18323 * Value: htt_dbg_ext_stats_type 18324 * - STATUS 18325 * Bits 10:8 18326 * Purpose: indicate whether the requested stats are present 18327 * Value: htt_dbg_ext_stats_status 18328 * - DONE 18329 * Bits 11 18330 * Purpose: 18331 * Indicates the completion of the stats entry, this will be the last 18332 * stats conf HTT segment for the requested stats type. 18333 * Value: 18334 * 0 -> the stats retrieval is ongoing 18335 * 1 -> the stats retrieval is complete 18336 * - LENGTH 18337 * Bits 31:16 18338 * Purpose: indicate the stats information size 18339 * Value: This field specifies the number of bytes of stats information 18340 * that follows the element tag-length header. 18341 * It is expected but not required that this length is a multiple of 18342 * 4 bytes. 18343 */ 18344 #define HTT_T2H_EXT_STATS_COOKIE_SIZE 8 18345 18346 #define HTT_T2H_EXT_STATS_CONF_HDR_SIZE 4 18347 18348 #define HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 4 18349 18350 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M 0x000000ff 18351 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S 0 18352 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M 0x00000700 18353 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S 8 18354 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_M 0x00000800 18355 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_S 11 18356 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M 0xffff0000 18357 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S 16 18358 18359 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_SET(word, value) \ 18360 do { \ 18361 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_TYPE, value); \ 18362 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S; \ 18363 } while (0) 18364 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_GET(word) \ 18365 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M) >> \ 18366 HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S) 18367 18368 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_SET(word, value) \ 18369 do { \ 18370 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_STATUS, value); \ 18371 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S; \ 18372 } while (0) 18373 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_GET(word) \ 18374 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M) >> \ 18375 HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S) 18376 18377 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_SET(word, value) \ 18378 do { \ 18379 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_DONE, value); \ 18380 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_DONE_S; \ 18381 } while (0) 18382 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_GET(word) \ 18383 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_DONE_M) >> \ 18384 HTT_T2H_EXT_STATS_CONF_TLV_DONE_S) 18385 18386 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_SET(word, value) \ 18387 do { \ 18388 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_LENGTH, value); \ 18389 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S; \ 18390 } while (0) 18391 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_GET(word) \ 18392 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M) >> \ 18393 HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S) 18394 18395 18396 /** 18397 * @brief target -> host streaming statistics upload 18398 * 18399 * MSG_TYPE => HTT_T2H_MSG_TYPE_STREAMING_STATS_IND 18400 * 18401 * @details 18402 * The following field definitions describe the format of the HTT target 18403 * to host streaming stats upload indication message. 18404 * The host can use a STREAMING_STATS_REQ message to enable the target to 18405 * produce an ongoing series of STREAMING_STATS_IND messages, and can also 18406 * use the STREAMING_STATS_REQ message to halt the target's production of 18407 * STREAMING_STATS_IND messages. 18408 * The STREAMING_STATS_IND message contains a payload of TLVs containing 18409 * the stats enabled by the host's STREAMING_STATS_REQ message. 18410 * 18411 * |31 8|7 0| 18412 * |--------------------------------------------------------------| 18413 * | reserved | msg type | 18414 * |--------------------------------------------------------------| 18415 * | type-specific stats info | 18416 * | (see htt_stats.h) | 18417 * |--------------------------------------------------------------| 18418 * Header fields: 18419 * - MSG_TYPE 18420 * Bits 7:0 18421 * Purpose: Identifies this as a streaming statistics upload indication 18422 * message. 18423 * Value: 0x2f (HTT_T2H_MSG_TYPE_STREAMING_STATS_IND) 18424 */ 18425 18426 #define HTT_T2H_STREAMING_STATS_IND_HDR_SIZE 4 18427 18428 18429 typedef enum { 18430 HTT_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */ 18431 HTT_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */ 18432 HTT_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */ 18433 HTT_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ 18434 HTT_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ 18435 HTT_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ 18436 /* Reserved from 128 - 255 for target internal use.*/ 18437 HTT_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ 18438 } HTT_PEER_TYPE; 18439 18440 /** macro to convert MAC address from char array to HTT word format */ 18441 #define HTT_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr, phtt_mac_addr) do { \ 18442 (phtt_mac_addr)->mac_addr31to0 = \ 18443 (((c_macaddr)[0] << 0) | \ 18444 ((c_macaddr)[1] << 8) | \ 18445 ((c_macaddr)[2] << 16) | \ 18446 ((c_macaddr)[3] << 24)); \ 18447 (phtt_mac_addr)->mac_addr47to32 = ((c_macaddr)[4] | ((c_macaddr)[5] << 8));\ 18448 } while (0) 18449 18450 /** 18451 * @brief target -> host monitor mac header indication message 18452 * 18453 * MSG_TYPE => HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND 18454 * 18455 * @details 18456 * The following diagram shows the format of the monitor mac header message 18457 * sent from the target to the host. 18458 * This message is primarily sent when promiscuous rx mode is enabled. 18459 * One message is sent per rx PPDU. 18460 * 18461 * |31 24|23 16|15 8|7 0| 18462 * |-------------------------------------------------------------| 18463 * | peer_id | reserved0 | msg_type | 18464 * |-------------------------------------------------------------| 18465 * | reserved1 | num_mpdu | 18466 * |-------------------------------------------------------------| 18467 * | struct hw_rx_desc | 18468 * | (see wal_rx_desc.h) | 18469 * |-------------------------------------------------------------| 18470 * | struct ieee80211_frame_addr4 | 18471 * | (see ieee80211_defs.h) | 18472 * |-------------------------------------------------------------| 18473 * | struct ieee80211_frame_addr4 | 18474 * | (see ieee80211_defs.h) | 18475 * |-------------------------------------------------------------| 18476 * | ...... | 18477 * |-------------------------------------------------------------| 18478 * 18479 * Header fields: 18480 * - msg_type 18481 * Bits 7:0 18482 * Purpose: Identifies this is a monitor mac header indication message. 18483 * Value: 0x20 (HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND) 18484 * - peer_id 18485 * Bits 31:16 18486 * Purpose: Software peer id given by host during association, 18487 * During promiscuous mode, the peer ID will be invalid (0xFF) 18488 * for rx PPDUs received from unassociated peers. 18489 * Value: peer ID (for associated peers) or 0xFF (for unassociated peers) 18490 * - num_mpdu 18491 * Bits 15:0 18492 * Purpose: The number of MPDU frame headers (struct ieee80211_frame_addr4) 18493 * delivered within the message. 18494 * Value: 1 to 32 18495 * num_mpdu is limited to a maximum value of 32, due to buffer 18496 * size limits. For PPDUs with more than 32 MPDUs, only the 18497 * ieee80211_frame_addr4 headers from the first 32 MPDUs within 18498 * the PPDU will be provided. 18499 */ 18500 #define HTT_T2H_MONITOR_MAC_HEADER_IND_HDR_SIZE 8 18501 18502 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M 0xFFFF0000 18503 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S 16 18504 18505 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M 0x0000FFFF 18506 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S 0 18507 18508 18509 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_SET(word, value) \ 18510 do { \ 18511 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_PEER_ID, value); \ 18512 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S; \ 18513 } while (0) 18514 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_GET(word) \ 18515 (((word) & HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M) >> \ 18516 HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S) 18517 18518 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_SET(word, value) \ 18519 do { \ 18520 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU, value); \ 18521 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S; \ 18522 } while (0) 18523 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_GET(word) \ 18524 (((word) & HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M) >> \ 18525 HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S) 18526 18527 /** 18528 * @brief target -> host flow pool resize Message 18529 * 18530 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE 18531 * 18532 * @details 18533 * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE message is sent by the target when 18534 * the flow pool associated with the specified ID is resized 18535 * 18536 * The message would appear as follows: 18537 * 18538 * |31 16|15 8|7 0| 18539 * |---------------------------------+----------------+----------------| 18540 * | reserved0 | Msg type | 18541 * |-------------------------------------------------------------------| 18542 * | flow pool new size | flow pool ID | 18543 * |-------------------------------------------------------------------| 18544 * 18545 * The message is interpreted as follows: 18546 * b'0:7 - msg_type: This will be set to 0x21 18547 * (HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE) 18548 * 18549 * b'0:15 - flow pool ID: Existing flow pool ID 18550 * 18551 * b'16:31 - flow pool new size: new pool size for existing flow pool ID 18552 * 18553 */ 18554 18555 PREPACK struct htt_flow_pool_resize_t { 18556 A_UINT32 msg_type:8, 18557 reserved0:24; 18558 A_UINT32 flow_pool_id:16, 18559 flow_pool_new_size:16; 18560 } POSTPACK; 18561 18562 #define HTT_FLOW_POOL_RESIZE_SZ (sizeof(struct htt_flow_pool_resize_t)) 18563 18564 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M 0x0000ffff 18565 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S 0 18566 18567 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M 0xffff0000 18568 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S 16 18569 18570 18571 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_GET(_var) \ 18572 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M) >> \ 18573 HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S) 18574 18575 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_SET(_var, _val) \ 18576 do { \ 18577 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID, _val); \ 18578 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)); \ 18579 } while (0) 18580 18581 18582 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_GET(_var) \ 18583 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M) >> \ 18584 HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S) 18585 18586 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_SET(_var, _val) \ 18587 do { \ 18588 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE, _val); \ 18589 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \ 18590 } while (0) 18591 18592 18593 18594 #define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC 18595 #define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */ 18596 #define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4 18597 #define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \ 18598 (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES) 18599 #define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4 18600 #define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4 18601 /* 18602 * The read and write indices point to the data within the host buffer. 18603 * Because the first 4 bytes of the host buffer is used for the read index and 18604 * the next 4 bytes for the write index, the data itself starts at offset 8. 18605 * The read index and write index are the byte offsets from the base of the 18606 * meta-data buffer, and thus have a minimum value of 8 rather than 0. 18607 * Refer the ASCII text picture below. 18608 */ 18609 #define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \ 18610 (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \ 18611 HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES) 18612 18613 /* 18614 *************************************************************************** 18615 * 18616 * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 18617 * 18618 *************************************************************************** 18619 * 18620 * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used 18621 * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by 18622 * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is 18623 * written into the Host memory region mentioned below. 18624 * 18625 * Read index is updated by the Host. At any point of time, the read index will 18626 * indicate the index that will next be read by the Host. The read index is 18627 * in units of bytes offset from the base of the meta-data buffer. 18628 * 18629 * Write index is updated by the FW. At any point of time, the write index will 18630 * indicate from where the FW can start writing any new data. The write index is 18631 * in units of bytes offset from the base of the meta-data buffer. 18632 * 18633 * If the Host is not fast enough in reading the CFR data, any new capture data 18634 * would be dropped if there is no space left to write the new captures. 18635 * 18636 * The last 4 bytes of the memory region will have the magic pattern 18637 * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does 18638 * not overrun the host buffer. 18639 * 18640 * ,--------------------. read and write indices store the 18641 * | | byte offset from the base of the 18642 * | ,--------+--------. meta-data buffer to the next 18643 * | | | | location within the data buffer 18644 * | | v v that will be read / written 18645 * ************************************************************************ 18646 * * Read * Write * * Magic * 18647 * * index * index * CFR data1 ...... CFR data N * pattern * 18648 * * (4 bytes) * (4 bytes) * * (4 bytes)* 18649 * ************************************************************************ 18650 * |<---------- data buffer ---------->| 18651 * 18652 * |<----------------- meta-data buffer allocated in Host ----------------| 18653 * 18654 * Note: 18655 * - Considering the 4 bytes needed to store the Read index (R) and the 18656 * Write index (W), the initial value is as follows: 18657 * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX 18658 * - Buffer empty condition: 18659 * R = W 18660 * 18661 * Regarding CFR data format: 18662 * -------------------------- 18663 * 18664 * Each CFR tone is stored in HW as 16-bits with the following format: 18665 * {bits[15:12], bits[11:6], bits[5:0]} = 18666 * {unsigned exponent (4 bits), 18667 * signed mantissa_real (6 bits), 18668 * signed mantissa_imag (6 bits)} 18669 * 18670 * CFR_real = mantissa_real * 2^(exponent-5) 18671 * CFR_imag = mantissa_imag * 2^(exponent-5) 18672 * 18673 * 18674 * The CFR data is written to the 16-bit unsigned output array (buff) in 18675 * ascending tone order. For example, the Legacy20 CFR is output as follows: 18676 * 18677 * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]] 18678 * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]] 18679 * . 18680 * . 18681 * . 18682 * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]] 18683 * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]] 18684 */ 18685 18686 /* Bandwidth of peer CFR captures */ 18687 typedef enum { 18688 HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0, 18689 HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1, 18690 HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, 18691 HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, 18692 HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, 18693 HTT_PEER_CFR_CAPTURE_BW_MAX, 18694 } HTT_PEER_CFR_CAPTURE_BW; 18695 18696 /* Mode of the peer CFR captures. The type of RX frame for which the CFR 18697 * was captured 18698 */ 18699 typedef enum { 18700 HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0, 18701 HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1, 18702 HTT_PEER_CFR_CAPTURE_MODE_HT = 2, 18703 HTT_PEER_CFR_CAPTURE_MODE_VHT = 3, 18704 HTT_PEER_CFR_CAPTURE_MODE_MAX, 18705 } HTT_PEER_CFR_CAPTURE_MODE; 18706 18707 typedef enum { 18708 /* This message type is currently used for the below purpose: 18709 * 18710 * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the 18711 * wmi_peer_cfr_capture_cmd. 18712 * If payload_present bit is set to 0 then the associated memory region 18713 * gets allocated through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID. 18714 * If payload_present bit is set to 1 then CFR dump is part of the HTT 18715 * message; the CFR dump will be present at the end of the message, 18716 * after the chan_phy_mode. 18717 */ 18718 HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1, 18719 18720 /* Always keep this last */ 18721 HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX, 18722 } HTT_PEER_CFR_CAPTURE_MSG_TYPE; 18723 18724 /** 18725 * @brief target -> host CFR dump completion indication message definition 18726 * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1. 18727 * 18728 * MSG_TYPE => HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 18729 * 18730 * @details 18731 * The following diagram shows the format of the Channel Frequency Response 18732 * (CFR) dump completion indication. This inidcation is sent to the Host when 18733 * the channel capture of a peer is copied by Firmware into the Host memory 18734 * 18735 * ************************************************************************** 18736 * 18737 * Message format when the CFR capture message type is 18738 * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 18739 * 18740 * ************************************************************************** 18741 * 18742 * |31 16|15 |8|7 0| 18743 * |----------------------------------------------------------------| 18744 * header: | reserved |P| msg_type | 18745 * word 0 | | | | 18746 * |----------------------------------------------------------------| 18747 * payload: | cfr_capture_msg_type | 18748 * word 1 | | 18749 * |----------------------------------------------------------------| 18750 * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id | 18751 * word 2 | | | | | | | | | 18752 * |----------------------------------------------------------------| 18753 * | mac_addr31to0 | 18754 * word 3 | | 18755 * |----------------------------------------------------------------| 18756 * | unused / reserved | mac_addr47to32 | 18757 * word 4 | | | 18758 * |----------------------------------------------------------------| 18759 * | index | 18760 * word 5 | | 18761 * |----------------------------------------------------------------| 18762 * | length | 18763 * word 6 | | 18764 * |----------------------------------------------------------------| 18765 * | timestamp | 18766 * word 7 | | 18767 * |----------------------------------------------------------------| 18768 * | counter | 18769 * word 8 | | 18770 * |----------------------------------------------------------------| 18771 * | chan_mhz | 18772 * word 9 | | 18773 * |----------------------------------------------------------------| 18774 * | band_center_freq1 | 18775 * word 10 | | 18776 * |----------------------------------------------------------------| 18777 * | band_center_freq2 | 18778 * word 11 | | 18779 * |----------------------------------------------------------------| 18780 * | chan_phy_mode | 18781 * word 12 | | 18782 * |----------------------------------------------------------------| 18783 * where, 18784 * P - payload present bit (payload_present explained below) 18785 * req_id - memory request id (mem_req_id explained below) 18786 * S - status field (status explained below) 18787 * capbw - capture bandwidth (capture_bw explained below) 18788 * mode - mode of capture (mode explained below) 18789 * sts - space time streams (sts_count explained below) 18790 * chbw - channel bandwidth (channel_bw explained below) 18791 * captype - capture type (cap_type explained below) 18792 * 18793 * The following field definitions describe the format of the CFR dump 18794 * completion indication sent from the target to the host 18795 * 18796 * Header fields: 18797 * 18798 * Word 0 18799 * - msg_type 18800 * Bits 7:0 18801 * Purpose: Identifies this as CFR TX completion indication 18802 * Value: 0x22 (HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND) 18803 * - payload_present 18804 * Bit 8 18805 * Purpose: Identifies how CFR data is sent to host 18806 * Value: 0 - If CFR Payload is written to host memory 18807 * 1 - If CFR Payload is sent as part of HTT message 18808 * (This is the requirement for SDIO/USB where it is 18809 * not possible to write CFR data to host memory) 18810 * - reserved 18811 * Bits 31:9 18812 * Purpose: Reserved 18813 * Value: 0 18814 * 18815 * Payload fields: 18816 * 18817 * Word 1 18818 * - cfr_capture_msg_type 18819 * Bits 31:0 18820 * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE 18821 * to specify the format used for the remainder of the message 18822 * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18823 * (currently only MSG_TYPE_1 is defined) 18824 * 18825 * Word 2 18826 * - mem_req_id 18827 * Bits 6:0 18828 * Purpose: Contain the mem request id of the region where the CFR capture 18829 * has been stored - of type WMI_HOST_MEM_REQ_ID 18830 * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID (if payload_present is 1, 18831 this value is invalid) 18832 * - status 18833 * Bit 7 18834 * Purpose: Boolean value carrying the status of the CFR capture of the peer 18835 * Value: 1 (True) - Successful; 0 (False) - Not successful 18836 * - capture_bw 18837 * Bits 10:8 18838 * Purpose: Carry the bandwidth of the CFR capture 18839 * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW 18840 * - mode 18841 * Bits 13:11 18842 * Purpose: Carry the mode of the rx frame for which the CFR was captured 18843 * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE 18844 * - sts_count 18845 * Bits 16:14 18846 * Purpose: Carry the number of space time streams 18847 * Value: Number of space time streams 18848 * - channel_bw 18849 * Bits 19:17 18850 * Purpose: Carry the bandwidth of the channel of the vdev performing the 18851 * measurement 18852 * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW) 18853 * - cap_type 18854 * Bits 23:20 18855 * Purpose: Carry the type of the capture 18856 * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD) 18857 * - vdev_id 18858 * Bits 31:24 18859 * Purpose: Carry the virtual device id 18860 * Value: vdev ID 18861 * 18862 * Word 3 18863 * - mac_addr31to0 18864 * Bits 31:0 18865 * Purpose: Contain the bits 31:0 of the peer MAC address 18866 * Value: Bits 31:0 of the peer MAC address 18867 * 18868 * Word 4 18869 * - mac_addr47to32 18870 * Bits 15:0 18871 * Purpose: Contain the bits 47:32 of the peer MAC address 18872 * Value: Bits 47:32 of the peer MAC address 18873 * 18874 * Word 5 18875 * - index 18876 * Bits 31:0 18877 * Purpose: Contain the index at which this CFR dump was written in the Host 18878 * allocated memory. This index is the number of bytes from the base address. 18879 * Value: Index position 18880 * 18881 * Word 6 18882 * - length 18883 * Bits 31:0 18884 * Purpose: Carry the length of the CFR capture of the peer, in bytes 18885 * Value: Length of the CFR capture of the peer 18886 * 18887 * Word 7 18888 * - timestamp 18889 * Bits 31:0 18890 * Purpose: Carry the time at which the CFR was captured in the hardware. The 18891 * clock used for this timestamp is private to the target and not visible to 18892 * the host i.e., Host can interpret only the relative timestamp deltas from 18893 * one message to the next, but can't interpret the absolute timestamp from a 18894 * single message. 18895 * Value: Timestamp in microseconds 18896 * 18897 * Word 8 18898 * - counter 18899 * Bits 31:0 18900 * Purpose: Carry the count of the current CFR capture from FW. This is 18901 * helpful to identify any drops in FW in any scenario (e.g., lack of space 18902 * in host memory) 18903 * Value: Count of the current CFR capture 18904 * 18905 * Word 9 18906 * - chan_mhz 18907 * Bits 31:0 18908 * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV 18909 * Value: Primary 20 channel frequency 18910 * 18911 * Word 10 18912 * - band_center_freq1 18913 * Bits 31:0 18914 * Purpose: Carry the center frequency 1 in MHz of the VDEV 18915 * Value: Center frequency 1 in MHz 18916 * 18917 * Word 11 18918 * - band_center_freq2 18919 * Bits 31:0 18920 * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of 18921 * the VDEV 18922 * 80plus80 mode 18923 * Value: Center frequency 2 in MHz 18924 * 18925 * Word 12 18926 * - chan_phy_mode 18927 * Bits 31:0 18928 * Purpose: Carry the phy mode of the channel, of the VDEV 18929 * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h 18930 */ 18931 PREPACK struct htt_cfr_dump_ind_type_1 { 18932 A_UINT32 mem_req_id:7, 18933 status:1, 18934 capture_bw:3, 18935 mode:3, 18936 sts_count:3, 18937 channel_bw:3, 18938 cap_type:4, 18939 vdev_id:8; 18940 htt_mac_addr addr; 18941 A_UINT32 index; 18942 A_UINT32 length; 18943 A_UINT32 timestamp; 18944 A_UINT32 counter; 18945 struct htt_chan_change_msg chan; 18946 } POSTPACK; 18947 18948 PREPACK struct htt_cfr_dump_compl_ind { 18949 A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */ 18950 union { 18951 /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */ 18952 struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1; 18953 /* If there is a need to change the memory layout and its associated 18954 * HTT indication format, a new CFR capture message type can be 18955 * introduced and added into this union. 18956 */ 18957 }; 18958 } POSTPACK; 18959 18960 /* 18961 * Get / set macros for the bit fields within WORD-1 of htt_cfr_dump_compl_ind, 18962 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18963 */ 18964 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M 0x00000100 18965 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S 8 18966 18967 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_SET(word, value) \ 18968 do { \ 18969 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID, value); \ 18970 (word) |= (value) << HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S; \ 18971 } while(0) 18972 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_GET(word) \ 18973 (((word) & HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M) >> \ 18974 HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S) 18975 18976 /* 18977 * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind, 18978 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18979 */ 18980 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F 18981 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0 18982 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080 18983 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7 18984 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700 18985 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8 18986 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800 18987 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11 18988 #define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000 18989 #define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14 18990 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000 18991 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17 18992 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000 18993 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20 18994 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000 18995 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24 18996 18997 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \ 18998 do { \ 18999 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \ 19000 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \ 19001 } while (0) 19002 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \ 19003 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \ 19004 HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S) 19005 19006 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \ 19007 do { \ 19008 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \ 19009 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \ 19010 } while (0) 19011 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \ 19012 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \ 19013 HTT_T2H_CFR_DUMP_TYPE1_STATUS_S) 19014 19015 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \ 19016 do { \ 19017 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \ 19018 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \ 19019 } while (0) 19020 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \ 19021 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \ 19022 HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S) 19023 19024 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \ 19025 do { \ 19026 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \ 19027 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \ 19028 } while (0) 19029 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \ 19030 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \ 19031 HTT_T2H_CFR_DUMP_TYPE1_MODE_S) 19032 19033 #define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \ 19034 do { \ 19035 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \ 19036 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \ 19037 } while (0) 19038 #define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \ 19039 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \ 19040 HTT_T2H_CFR_DUMP_TYPE1_STS_S) 19041 19042 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \ 19043 do { \ 19044 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \ 19045 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \ 19046 } while (0) 19047 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \ 19048 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \ 19049 HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S) 19050 19051 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \ 19052 do { \ 19053 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \ 19054 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \ 19055 } while (0) 19056 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \ 19057 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \ 19058 HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S) 19059 19060 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \ 19061 do { \ 19062 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \ 19063 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \ 19064 } while (0) 19065 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \ 19066 (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \ 19067 HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S) 19068 19069 19070 /** 19071 * @brief target -> host peer (PPDU) stats message 19072 * 19073 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_STATS_IND 19074 * 19075 * @details 19076 * This message is generated by FW when FW is sending stats to host 19077 * about one or more PPDUs that the FW has transmitted to one or more peers. 19078 * This message is sent autonomously by the target rather than upon request 19079 * by the host. 19080 * The following field definitions describe the format of the HTT target 19081 * to host peer stats indication message. 19082 * 19083 * The HTT_T2H PPDU_STATS_IND message has a header followed by one 19084 * or more PPDU stats records. 19085 * Each PPDU stats record uses a htt_tx_ppdu_stats_info TLV. 19086 * If the details of N PPDUS are sent in one PEER_STATS_IND message, 19087 * then the message would start with the 19088 * header, followed by N htt_tx_ppdu_stats_info structures, as depicted 19089 * below. 19090 * 19091 * |31 16|15|14|13 11|10 9|8|7 0| 19092 * |-------------------------------------------------------------| 19093 * | reserved |MSG_TYPE | 19094 * |-------------------------------------------------------------| 19095 * rec 0 | TLV header | 19096 * rec 0 |-------------------------------------------------------------| 19097 * rec 0 | ppdu successful bytes | 19098 * rec 0 |-------------------------------------------------------------| 19099 * rec 0 | ppdu retry bytes | 19100 * rec 0 |-------------------------------------------------------------| 19101 * rec 0 | ppdu failed bytes | 19102 * rec 0 |-------------------------------------------------------------| 19103 * rec 0 | peer id | S|SG| BW | BA |A|rate code| 19104 * rec 0 |-------------------------------------------------------------| 19105 * rec 0 | retried MSDUs | successful MSDUs | 19106 * rec 0 |-------------------------------------------------------------| 19107 * rec 0 | TX duration | failed MSDUs | 19108 * rec 0 |-------------------------------------------------------------| 19109 * ... 19110 * |-------------------------------------------------------------| 19111 * rec N | TLV header | 19112 * rec N |-------------------------------------------------------------| 19113 * rec N | ppdu successful bytes | 19114 * rec N |-------------------------------------------------------------| 19115 * rec N | ppdu retry bytes | 19116 * rec N |-------------------------------------------------------------| 19117 * rec N | ppdu failed bytes | 19118 * rec N |-------------------------------------------------------------| 19119 * rec N | peer id | S|SG| BW | BA |A|rate code| 19120 * rec N |-------------------------------------------------------------| 19121 * rec N | retried MSDUs | successful MSDUs | 19122 * rec N |-------------------------------------------------------------| 19123 * rec N | TX duration | failed MSDUs | 19124 * rec N |-------------------------------------------------------------| 19125 * 19126 * where: 19127 * A = is A-MPDU flag 19128 * BA = block-ack failure flags 19129 * BW = bandwidth spec 19130 * SG = SGI enabled spec 19131 * S = skipped rate ctrl 19132 * One htt_tx_ppdu_stats_info instance will have stats for one PPDU 19133 * 19134 * Header 19135 * ------ 19136 * dword0 - b'0:7 - msg_type : 0x23 (HTT_T2H_MSG_TYPE_PEER_STATS_IND) 19137 * dword0 - b'8:31 - reserved : Reserved for future use 19138 * 19139 * payload include below peer_stats information 19140 * -------------------------------------------- 19141 * @TLV : HTT_PPDU_STATS_INFO_TLV 19142 * @tx_success_bytes : total successful bytes in the PPDU. 19143 * @tx_retry_bytes : total retried bytes in the PPDU. 19144 * @tx_failed_bytes : total failed bytes in the PPDU. 19145 * @tx_ratecode : rate code used for the PPDU. 19146 * @is_ampdu : Indicates PPDU is AMPDU or not. 19147 * @ba_ack_failed : BA/ACK failed for this PPDU 19148 * b00 -> BA received 19149 * b01 -> BA failed once 19150 * b10 -> BA failed twice, when HW retry is enabled. 19151 * @bw : BW 19152 * b00 -> 20 MHz 19153 * b01 -> 40 MHz 19154 * b10 -> 80 MHz 19155 * b11 -> 160 MHz (or 80+80) 19156 * @sg : SGI enabled 19157 * @s : skipped ratectrl 19158 * @peer_id : peer id 19159 * @tx_success_msdus : successful MSDUs 19160 * @tx_retry_msdus : retried MSDUs 19161 * @tx_failed_msdus : MSDUs dropped in FW after max retry 19162 * @tx_duration : Tx duration for the PPDU (microsecond units) 19163 */ 19164 19165 19166 /** 19167 * @brief target -> host backpressure event 19168 * 19169 * MSG_TYPE => HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND 19170 * 19171 * @details 19172 * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID message is sent by the target when 19173 * continuous backpressure is seen in the LMAC/ UMAC rings software rings. 19174 * This message will only be sent if the backpressure condition has existed 19175 * continuously for an initial period (100 ms). 19176 * Repeat messages with updated information will be sent after each 19177 * subsequent period (100 ms) as long as the backpressure remains unabated. 19178 * This message indicates the ring id along with current head and tail index 19179 * locations (i.e. write and read indices). 19180 * The backpressure time indicates the time in ms for which continuous 19181 * backpressure has been observed in the ring. 19182 * 19183 * The message format is as follows: 19184 * 19185 * |31 24|23 16|15 8|7 0| 19186 * |----------------+----------------+----------------+----------------| 19187 * | ring_id | ring_type | pdev_id | msg_type | 19188 * |-------------------------------------------------------------------| 19189 * | tail_idx | head_idx | 19190 * |-------------------------------------------------------------------| 19191 * | backpressure_time_ms | 19192 * |-------------------------------------------------------------------| 19193 * 19194 * The message is interpreted as follows: 19195 * dword0 - b'0:7 - msg_type: This will be set to 0x24 19196 * (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND) 19197 * b'8:15 - pdev_id: 0 indicates msg is for UMAC ring. 19198 * 1, 2, 3 indicates pdev_id 0,1,2 and 19199 * the msg is for LMAC ring. 19200 * b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type. 19201 * b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/ 19202 * htt_backpressure_lmac_ring_id. This represents 19203 * the ring id for which continuous backpressure 19204 * is seen 19205 * 19206 * dword1 - b'0:15 - head_idx: This indicates the current head index of 19207 * the ring indicated by the ring_id 19208 * 19209 * dword1 - b'16:31 - tail_idx: This indicates the current tail index of 19210 * the ring indicated by the ring id 19211 * 19212 * dword2 - b'0:31 - backpressure_time_ms: Indicates how long continuous 19213 * backpressure has been seen in the ring 19214 * indicated by the ring_id. 19215 * Units = milliseconds 19216 */ 19217 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_M 0x0000ff00 19218 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_S 8 19219 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_M 0x00ff0000 19220 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_S 16 19221 #define HTT_T2H_RX_BKPRESSURE_RINGID_M 0xff000000 19222 #define HTT_T2H_RX_BKPRESSURE_RINGID_S 24 19223 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M 0x0000ffff 19224 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S 0 19225 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M 0xffff0000 19226 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S 16 19227 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_M 0xffffffff 19228 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_S 0 19229 19230 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_SET(word, value) \ 19231 do { \ 19232 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_PDEV_ID, value); \ 19233 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_PDEV_ID_S; \ 19234 } while (0) 19235 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_GET(word) \ 19236 (((word) & HTT_T2H_RX_BKPRESSURE_PDEV_ID_M) >> \ 19237 HTT_T2H_RX_BKPRESSURE_PDEV_ID_S) 19238 19239 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_SET(word, value) \ 19240 do { \ 19241 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RING_TYPE, value); \ 19242 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RING_TYPE_S; \ 19243 } while (0) 19244 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_GET(word) \ 19245 (((word) & HTT_T2H_RX_BKPRESSURE_RING_TYPE_M) >> \ 19246 HTT_T2H_RX_BKPRESSURE_RING_TYPE_S) 19247 19248 #define HTT_T2H_RX_BKPRESSURE_RINGID_SET(word, value) \ 19249 do { \ 19250 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RINGID, value); \ 19251 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RINGID_S; \ 19252 } while (0) 19253 #define HTT_T2H_RX_BKPRESSURE_RINGID_GET(word) \ 19254 (((word) & HTT_T2H_RX_BKPRESSURE_RINGID_M) >> \ 19255 HTT_T2H_RX_BKPRESSURE_RINGID_S) 19256 19257 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_SET(word, value) \ 19258 do { \ 19259 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_HEAD_IDX, value); \ 19260 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S; \ 19261 } while (0) 19262 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_GET(word) \ 19263 (((word) & HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M) >> \ 19264 HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S) 19265 19266 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_SET(word, value) \ 19267 do { \ 19268 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TAIL_IDX, value); \ 19269 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S; \ 19270 } while (0) 19271 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_GET(word) \ 19272 (((word) & HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M) >> \ 19273 HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S) 19274 19275 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_SET(word, value) \ 19276 do { \ 19277 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TIME_MS, value); \ 19278 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TIME_MS_S; \ 19279 } while (0) 19280 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_GET(word) \ 19281 (((word) & HTT_T2H_RX_BKPRESSURE_TIME_MS_M) >> \ 19282 HTT_T2H_RX_BKPRESSURE_TIME_MS_S) 19283 19284 enum htt_backpressure_ring_type { 19285 HTT_SW_RING_TYPE_UMAC, 19286 HTT_SW_RING_TYPE_LMAC, 19287 HTT_SW_RING_TYPE_MAX, 19288 }; 19289 19290 /* Ring id for which the message is sent to host */ 19291 enum htt_backpressure_umac_ringid { 19292 HTT_SW_RING_IDX_REO_REO2SW1_RING, 19293 HTT_SW_RING_IDX_REO_REO2SW2_RING, 19294 HTT_SW_RING_IDX_REO_REO2SW3_RING, 19295 HTT_SW_RING_IDX_REO_REO2SW4_RING, 19296 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 19297 HTT_SW_RING_IDX_REO_REO2TCL_RING, 19298 HTT_SW_RING_IDX_REO_REO2FW_RING, 19299 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 19300 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 19301 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 19302 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 19303 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 19304 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 19305 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 19306 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 19307 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 19308 HTT_SW_RING_IDX_REO_REO_CMD_RING, 19309 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 19310 HTT_SW_UMAC_RING_IDX_MAX, 19311 }; 19312 19313 enum htt_backpressure_lmac_ringid { 19314 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 19315 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 19316 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 19317 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 19318 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 19319 HTT_SW_RING_IDX_RXDMA2FW_RING, 19320 HTT_SW_RING_IDX_RXDMA2SW_RING, 19321 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 19322 HTT_SW_RING_IDX_RXDMA2REO_RING, 19323 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 19324 HTT_SW_RING_IDX_MONITOR_BUF_RING, 19325 HTT_SW_RING_IDX_MONITOR_DESC_RING, 19326 HTT_SW_RING_IDX_MONITOR_DEST_RING, 19327 HTT_SW_LMAC_RING_IDX_MAX, 19328 }; 19329 19330 PREPACK struct htt_t2h_msg_bkpressure_event_ind_t { 19331 A_UINT32 msg_type: 8, /* HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND */ 19332 pdev_id: 8, 19333 ring_type: 8, /* htt_backpressure_ring_type */ 19334 /* 19335 * ring_id holds an enum value from either 19336 * htt_backpressure_umac_ringid or 19337 * htt_backpressure_lmac_ringid, based on 19338 * the ring_type setting. 19339 */ 19340 ring_id: 8; 19341 A_UINT16 head_idx; 19342 A_UINT16 tail_idx; 19343 A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */ 19344 } POSTPACK; 19345 19346 19347 /* 19348 * Defines two 32 bit words that can be used by the target to indicate a per 19349 * user RU allocation and rate information. 19350 * 19351 * This information is currently provided in the "sw_response_reference_ptr" 19352 * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the 19353 * "rx_ppdu_end_user_stats" TLV. 19354 * 19355 * VALID: 19356 * The consumer of these words must explicitly check the valid bit, 19357 * and only attempt interpretation of any of the remaining fields if 19358 * the valid bit is set to 1. 19359 * 19360 * VERSION: 19361 * The consumer of these words must also explicitly check the version bit, 19362 * and only use the V0 definition if the VERSION field is set to 0. 19363 * 19364 * Version 1 is currently undefined, with the exception of the VALID and 19365 * VERSION fields. 19366 * 19367 * Version 0: 19368 * 19369 * The fields below are duplicated per BW. 19370 * 19371 * The consumer must determine which BW field to use, based on the UL OFDMA 19372 * PPDU BW indicated by HW. 19373 * 19374 * RU_START: RU26 start index for the user. 19375 * Note that this is always using the RU26 index, regardless 19376 * of the actual RU assigned to the user 19377 * (i.e. the second RU52 is RU_START 2, RU_SIZE 19378 * HTT_UL_OFDMA_V0_RU_SIZE_RU_52) 19379 * 19380 * For example, 20MHz (the value in the top row is RU_START) 19381 * 19382 * RU Size 0 (26): |0|1|2|3|4|5|6|7|8| 19383 * RU Size 1 (52): | | | | | | 19384 * RU Size 2 (106): | | | | 19385 * RU Size 3 (242): | | 19386 * 19387 * RU_SIZE: Indicates the RU size, as defined by enum 19388 * htt_ul_ofdma_user_info_ru_size. 19389 * 19390 * LDPC: LDPC enabled (if 0, BCC is used) 19391 * 19392 * DCM: DCM enabled 19393 * 19394 * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0| 19395 * |---------------------------------+--------------------------------| 19396 * |Ver|Valid| FW internal | 19397 * |---------------------------------+--------------------------------| 19398 * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS| 19399 * |---------------------------------+--------------------------------| 19400 */ 19401 19402 enum htt_ul_ofdma_user_info_ru_size { 19403 HTT_UL_OFDMA_V0_RU_SIZE_RU_26, 19404 HTT_UL_OFDMA_V0_RU_SIZE_RU_52, 19405 HTT_UL_OFDMA_V0_RU_SIZE_RU_106, 19406 HTT_UL_OFDMA_V0_RU_SIZE_RU_242, 19407 HTT_UL_OFDMA_V0_RU_SIZE_RU_484, 19408 HTT_UL_OFDMA_V0_RU_SIZE_RU_996, 19409 HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 19410 }; 19411 19412 /* htt_up_ofdma_user_info_v0 provides an abstract view of the info */ 19413 struct htt_ul_ofdma_user_info_v0 { 19414 A_UINT32 word0; 19415 A_UINT32 word1; 19416 }; 19417 19418 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ 19419 A_UINT32 w0_fw_rsvd:29; \ 19420 A_UINT32 w0_manual_ulofdma_trig:1; \ 19421 A_UINT32 w0_valid:1; \ 19422 A_UINT32 w0_version:1; 19423 19424 struct htt_ul_ofdma_user_info_v0_bitmap_w0 { 19425 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 19426 }; 19427 19428 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 \ 19429 A_UINT32 w1_nss:3; \ 19430 A_UINT32 w1_mcs:4; \ 19431 A_UINT32 w1_ldpc:1; \ 19432 A_UINT32 w1_dcm:1; \ 19433 A_UINT32 w1_ru_start:7; \ 19434 A_UINT32 w1_ru_size:3; \ 19435 A_UINT32 w1_trig_type:4; \ 19436 A_UINT32 w1_unused:9; 19437 struct htt_ul_ofdma_user_info_v0_bitmap_w1 { 19438 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 19439 }; 19440 19441 19442 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ 19443 A_UINT32 w0_fw_rsvd:27; \ 19444 A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ 19445 A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ 19446 A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ 19447 19448 struct htt_ul_ofdma_user_info_v1_bitmap_w0 { 19449 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 19450 }; 19451 19452 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 \ 19453 A_UINT32 w1_unused_0_to_18:19; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ \ 19454 A_UINT32 w1_trig_type:4; \ 19455 A_UINT32 w1_unused_23_to_31:9; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ 19456 19457 struct htt_ul_ofdma_user_info_v1_bitmap_w1 { 19458 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 19459 }; 19460 19461 19462 /* htt_ul_ofdma_user_info_v0_bitmap shows what bitfields are within the info */ 19463 PREPACK struct htt_ul_ofdma_user_info_v0_bitmap { 19464 union { 19465 A_UINT32 word0; 19466 struct { 19467 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 19468 }; 19469 }; 19470 union { 19471 A_UINT32 word1; 19472 struct { 19473 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 19474 }; 19475 }; 19476 } POSTPACK; 19477 19478 /* 19479 * htt_ul_ofdma_user_info_v1_bitmap bits are aligned to 19480 * htt_ul_ofdma_user_info_v0_bitmap, based on the w0_version 19481 * this should be picked. 19482 */ 19483 PREPACK struct htt_ul_ofdma_user_info_v1_bitmap { 19484 union { 19485 A_UINT32 word0; 19486 struct { 19487 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 19488 }; 19489 }; 19490 union { 19491 A_UINT32 word1; 19492 struct { 19493 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 19494 }; 19495 }; 19496 } POSTPACK; 19497 19498 19499 enum HTT_UL_OFDMA_TRIG_TYPE { 19500 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0, 19501 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP, 19502 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR, 19503 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS, 19504 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR, 19505 }; 19506 19507 19508 #define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0)) 19509 19510 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff 19511 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 19512 19513 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 19514 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 19515 19516 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 19517 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 19518 19519 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000 19520 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31 19521 19522 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007 19523 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0 19524 19525 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078 19526 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3 19527 19528 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080 19529 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7 19530 19531 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100 19532 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8 19533 19534 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00 19535 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9 19536 19537 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000 19538 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16 19539 19540 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000 19541 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19 19542 19543 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000 19544 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23 19545 19546 /*--- word 0 ---*/ 19547 19548 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \ 19549 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S) 19550 19551 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \ 19552 do { \ 19553 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \ 19554 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \ 19555 } while (0) 19556 19557 19558 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \ 19559 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S) 19560 19561 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \ 19562 do { \ 19563 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \ 19564 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \ 19565 } while (0) 19566 19567 19568 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \ 19569 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S) 19570 19571 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \ 19572 do { \ 19573 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \ 19574 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \ 19575 } while (0) 19576 19577 19578 /*--- word 1 ---*/ 19579 19580 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \ 19581 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S) 19582 19583 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \ 19584 do { \ 19585 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \ 19586 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \ 19587 } while (0) 19588 19589 19590 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \ 19591 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S) 19592 19593 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \ 19594 do { \ 19595 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \ 19596 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \ 19597 } while (0) 19598 19599 19600 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \ 19601 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S) 19602 19603 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \ 19604 do { \ 19605 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \ 19606 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \ 19607 } while (0) 19608 19609 19610 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \ 19611 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S) 19612 19613 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \ 19614 do { \ 19615 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \ 19616 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \ 19617 } while (0) 19618 19619 19620 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \ 19621 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S) 19622 19623 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \ 19624 do { \ 19625 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \ 19626 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \ 19627 } while (0) 19628 19629 19630 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \ 19631 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S) 19632 19633 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \ 19634 do { \ 19635 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \ 19636 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \ 19637 } while (0) 19638 19639 19640 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \ 19641 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S) 19642 19643 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \ 19644 do { \ 19645 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \ 19646 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \ 19647 } while (0) 19648 19649 /** 19650 * @brief target -> host channel calibration data message 19651 * 19652 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CALDATA 19653 * 19654 * @brief host -> target channel calibration data message 19655 * 19656 * MSG_TYPE => HTT_H2T_MSG_TYPE_CHAN_CALDATA 19657 * 19658 * @details 19659 * The following field definitions describe the format of the channel 19660 * calibration data message sent from the target to the host when 19661 * MSG_TYPE is HTT_T2H_MSG_TYPE_CHAN_CALDATA, and sent from the host 19662 * to the target when MSG_TYPE is HTT_H2T_MSG_TYPE_CHAN_CALDATA. 19663 * The message is defined as htt_chan_caldata_msg followed by a variable 19664 * number of 32-bit character values. 19665 * 19666 * |31 21|20|19 16|15 13| 12|11 8|7 0| 19667 * |------------------------------------------------------------------| 19668 * | rsv | A| frag | rsv |ck_v| sub_type| msg type | 19669 * |------------------------------------------------------------------| 19670 * | payload size | mhz | 19671 * |------------------------------------------------------------------| 19672 * | center frequency 2 | center frequency 1 | 19673 * |------------------------------------------------------------------| 19674 * | check sum | 19675 * |------------------------------------------------------------------| 19676 * | payload | 19677 * |------------------------------------------------------------------| 19678 * message info field: 19679 * - MSG_TYPE 19680 * Bits 7:0 19681 * Purpose: identifies this as a channel calibration data message 19682 * Value: 0x25 (HTT_T2H_MSG_TYPE_CHAN_CALDATA) 19683 * 0x14 (HTT_H2T_MSG_TYPE_CHAN_CALDATA) 19684 * - SUB_TYPE 19685 * Bits 11:8 19686 * Purpose: T2H: indicates whether target is providing chan cal data 19687 * to the host to store, or requesting that the host 19688 * download previously-stored data. 19689 * H2T: indicates whether the host is providing the requested 19690 * channel cal data, or if it is rejecting the data 19691 * request because it does not have the requested data. 19692 * Value: see HTT_T2H_MSG_CHAN_CALDATA_xxx defs 19693 * - CHKSUM_VALID 19694 * Bit 12 19695 * Purpose: indicates if the checksum field is valid 19696 * value: 19697 * - FRAG 19698 * Bit 19:16 19699 * Purpose: indicates the fragment index for message 19700 * value: 0 for first fragment, 1 for second fragment, ... 19701 * - APPEND 19702 * Bit 20 19703 * Purpose: indicates if this is the last fragment 19704 * value: 0 = final fragment, 1 = more fragments will be appended 19705 * 19706 * channel and payload size field 19707 * - MHZ 19708 * Bits 15:0 19709 * Purpose: indicates the channel primary frequency 19710 * Value: 19711 * - PAYLOAD_SIZE 19712 * Bits 31:16 19713 * Purpose: indicates the bytes of calibration data in payload 19714 * Value: 19715 * 19716 * center frequency field 19717 * - CENTER FREQUENCY 1 19718 * Bits 15:0 19719 * Purpose: indicates the channel center frequency 19720 * Value: channel center frequency, in MHz units 19721 * - CENTER FREQUENCY 2 19722 * Bits 31:16 19723 * Purpose: indicates the secondary channel center frequency, 19724 * only for 11acvht 80plus80 mode 19725 * Value: secondary channel center frequency, in MHz units, if applicable 19726 * 19727 * checksum field 19728 * - CHECK_SUM 19729 * Bits 31:0 19730 * Purpose: check the payload data, it is just for this fragment. 19731 * This is intended for the target to check that the channel 19732 * calibration data returned by the host is the unmodified data 19733 * that was previously provided to the host by the target. 19734 * value: checksum of fragment payload 19735 */ 19736 PREPACK struct htt_chan_caldata_msg { 19737 /* DWORD 0: message info */ 19738 A_UINT32 19739 msg_type: 8, 19740 sub_type: 4 , 19741 chksum_valid: 1, /** 1:valid, 0:invalid */ 19742 reserved1: 3, 19743 frag_idx: 4, /** fragment index for calibration data */ 19744 appending: 1, /** 0: no fragment appending, 19745 * 1: extra fragment appending */ 19746 reserved2: 11; 19747 19748 /* DWORD 1: channel and payload size */ 19749 A_UINT32 19750 mhz: 16, /** primary 20 MHz channel frequency in mhz */ 19751 payload_size: 16; /** unit: bytes */ 19752 19753 /* DWORD 2: center frequency */ 19754 A_UINT32 19755 band_center_freq1: 16, /** Center frequency 1 in MHz */ 19756 band_center_freq2: 16; /** Center frequency 2 in MHz, 19757 * valid only for 11acvht 80plus80 mode */ 19758 19759 /* DWORD 3: check sum */ 19760 A_UINT32 chksum; 19761 19762 /* variable length for calibration data */ 19763 A_UINT32 payload[1/* or more */]; 19764 } POSTPACK; 19765 19766 /* T2H SUBTYPE */ 19767 #define HTT_T2H_MSG_CHAN_CALDATA_REQ 0 19768 #define HTT_T2H_MSG_CHAN_CALDATA_UPLOAD 1 19769 19770 /* H2T SUBTYPE */ 19771 #define HTT_H2T_MSG_CHAN_CALDATA_REJ 0 19772 #define HTT_H2T_MSG_CHAN_CALDATA_DOWNLOAD 1 19773 19774 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_S 8 19775 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_M 0x00000f00 19776 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_GET(_var) \ 19777 (((_var) & HTT_CHAN_CALDATA_MSG_SUB_TYPE_M) >> HTT_CHAN_CALDATA_MSG_SUB_TYPE_S) 19778 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_SET(_var, _val) \ 19779 do { \ 19780 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_SUB_TYPE, _val); \ 19781 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_SUB_TYPE_S)); \ 19782 } while (0) 19783 19784 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_S 12 19785 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_M 0x00001000 19786 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_GET(_var) \ 19787 (((_var) & HTT_CHAN_CALDATA_MSG_CHKSUM_V_M) >> HTT_CHAN_CALDATA_MSG_CHKSUM_V_S) 19788 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_SET(_var, _val) \ 19789 do { \ 19790 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_CHKSUM_V, _val); \ 19791 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_CHKSUM_V_S)); \ 19792 } while (0) 19793 19794 19795 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_S 16 19796 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_M 0x000f0000 19797 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_GET(_var) \ 19798 (((_var) & HTT_CHAN_CALDATA_MSG_FRAG_IDX_M) >> HTT_CHAN_CALDATA_MSG_FRAG_IDX_S) 19799 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_SET(_var, _val) \ 19800 do { \ 19801 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FRAG_IDX, _val); \ 19802 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FRAG_IDX_S)); \ 19803 } while (0) 19804 19805 #define HTT_CHAN_CALDATA_MSG_APPENDING_S 20 19806 #define HTT_CHAN_CALDATA_MSG_APPENDING_M 0x00100000 19807 #define HTT_CHAN_CALDATA_MSG_APPENDING_GET(_var) \ 19808 (((_var) & HTT_CHAN_CALDATA_MSG_APPENDING_M) >> HTT_CHAN_CALDATA_MSG_APPENDING_S) 19809 #define HTT_CHAN_CALDATA_MSG_APPENDING_SET(_var, _val) \ 19810 do { \ 19811 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_APPENDING, _val); \ 19812 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_APPENDING_S)); \ 19813 } while (0) 19814 19815 #define HTT_CHAN_CALDATA_MSG_MHZ_S 0 19816 #define HTT_CHAN_CALDATA_MSG_MHZ_M 0x0000ffff 19817 #define HTT_CHAN_CALDATA_MSG_MHZ_GET(_var) \ 19818 (((_var) & HTT_CHAN_CALDATA_MSG_MHZ_M) >> HTT_CHAN_CALDATA_MSG_MHZ_S) 19819 #define HTT_CHAN_CALDATA_MSG_MHZ_SET(_var, _val) \ 19820 do { \ 19821 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_MHZ, _val); \ 19822 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_MHZ_S)); \ 19823 } while (0) 19824 19825 19826 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_S 16 19827 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_M 0xffff0000 19828 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_GET(_var) \ 19829 (((_var) & HTT_CHAN_CALDATA_MSG_PLD_SIZE_M) >> HTT_CHAN_CALDATA_MSG_PLD_SIZE_S) 19830 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_SET(_var, _val) \ 19831 do { \ 19832 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_PLD_SIZE, _val); \ 19833 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_PLD_SIZE_S)); \ 19834 } while (0) 19835 19836 19837 #define HTT_CHAN_CALDATA_MSG_FREQ1_S 0 19838 #define HTT_CHAN_CALDATA_MSG_FREQ1_M 0x0000ffff 19839 #define HTT_CHAN_CALDATA_MSG_FREQ1_GET(_var) \ 19840 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ1_M) >> HTT_CHAN_CALDATA_MSG_FREQ1_S) 19841 #define HTT_CHAN_CALDATA_MSG_FREQ1_SET(_var, _val) \ 19842 do { \ 19843 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ1, _val); \ 19844 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ1_S)); \ 19845 } while (0) 19846 19847 #define HTT_CHAN_CALDATA_MSG_FREQ2_S 16 19848 #define HTT_CHAN_CALDATA_MSG_FREQ2_M 0xffff0000 19849 #define HTT_CHAN_CALDATA_MSG_FREQ2_GET(_var) \ 19850 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ2_M) >> HTT_CHAN_CALDATA_MSG_FREQ2_S) 19851 #define HTT_CHAN_CALDATA_MSG_FREQ2_SET(_var, _val) \ 19852 do { \ 19853 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ2, _val); \ 19854 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \ 19855 } while (0) 19856 19857 19858 /** 19859 * @brief target -> host FSE CMEM based send 19860 * 19861 * MSG_TYPE => HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND 19862 * 19863 * @details 19864 * HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND message is sent by the target when 19865 * FSE placement in CMEM is enabled. 19866 * 19867 * This message sends the non-secure CMEM base address. 19868 * It will be sent to host in response to message 19869 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG. 19870 * The message would appear as follows: 19871 * 19872 * |31 24|23 16|15 8|7 0| 19873 * |----------------+----------------+----------------+----------------| 19874 * | reserved | num_entries | msg_type | 19875 * |----------------+----------------+----------------+----------------| 19876 * | base_address_lo | 19877 * |----------------+----------------+----------------+----------------| 19878 * | base_address_hi | 19879 * |-------------------------------------------------------------------| 19880 * 19881 * The message is interpreted as follows: 19882 * dword0 - b'0:7 - msg_type: This will be set to 0x27 19883 * (HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND) 19884 * b'8:15 - number_entries: Indicated the number of entries 19885 * programmed. 19886 * b'16:31 - reserved. 19887 * dword1 - b'0:31 - base_address_lo: Indicate lower 32 bits of 19888 * CMEM base address 19889 * dword2 - b'0:31 - base_address_hi: Indicate upper 32 bits of 19890 * CMEM base address 19891 */ 19892 19893 PREPACK struct htt_cmem_base_send_t { 19894 A_UINT32 msg_type: 8, 19895 num_entries: 8, 19896 reserved: 16; 19897 A_UINT32 base_address_lo; 19898 A_UINT32 base_address_hi; 19899 } POSTPACK; 19900 19901 #define HTT_CMEM_BASE_SEND_SIZE (sizeof(struct htt_cmem_base_send_t)) 19902 19903 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_M 0x0000FF00 19904 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_S 8 19905 19906 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_GET(_var) \ 19907 (((_var) & HTT_CMEM_BASE_SEND_NUM_ENTRIES_M) >> \ 19908 HTT_CMEM_BASE_SEND_NUM_ENTRIES_S) 19909 19910 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_SET(_var, _val) \ 19911 do { \ 19912 HTT_CHECK_SET_VAL(HTT_CMEM_BASE_SEND_NUM_ENTRIES, _val); \ 19913 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 19914 } while (0) 19915 19916 /** 19917 * @brief - HTT PPDU ID format 19918 * 19919 * @details 19920 * The following field definitions describe the format of the PPDU ID. 19921 * The PPDU ID is truncated to 24 bits for TLVs from TQM. 19922 * 19923 * |31 30|29 24| 23|22 21|20 19|18 17|16 12|11 0| 19924 * +-------------------------------------------------------------------------- 19925 * |rsvd |seq_cmd_type|tqm_cmd|rsvd |seq_idx|mac_id| hwq_ id | sch id | 19926 * +-------------------------------------------------------------------------- 19927 * 19928 * sch id :Schedule command id 19929 * Bits [11 : 0] : monotonically increasing counter to track the 19930 * PPDU posted to a specific transmit queue. 19931 * 19932 * hwq_id: Hardware Queue ID. 19933 * Bits [16 : 12] : Indicates the queue id in the hardware transmit queue. 19934 * 19935 * mac_id: MAC ID 19936 * Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct 19937 * 19938 * seq_idx: Sequence index. 19939 * Bits [21 : 19] : Sequence index indicates all the PPDU belonging to 19940 * a particular TXOP. 19941 * 19942 * tqm_cmd: HWSCH/TQM flag. 19943 * Bit [23] : Always set to 0. 19944 * 19945 * seq_cmd_type: Sequence command type. 19946 * Bit [29 : 24] : Indicates the frame type for the current sequence. 19947 * Refer to enum HTT_STATS_FTYPE for values. 19948 */ 19949 PREPACK struct htt_ppdu_id { 19950 A_UINT32 19951 sch_id: 12, 19952 hwq_id: 5, 19953 mac_id: 2, 19954 seq_idx: 2, 19955 reserved1: 2, 19956 tqm_cmd: 1, 19957 seq_cmd_type: 6, 19958 reserved2: 2; 19959 } POSTPACK; 19960 19961 #define HTT_PPDU_ID_SCH_ID_S 0 19962 #define HTT_PPDU_ID_SCH_ID_M 0x00000fff 19963 #define HTT_PPDU_ID_SCH_ID_GET(_var) \ 19964 (((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S) 19965 19966 #define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \ 19967 do { \ 19968 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \ 19969 ((_var) |= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \ 19970 } while (0) 19971 19972 #define HTT_PPDU_ID_HWQ_ID_S 12 19973 #define HTT_PPDU_ID_HWQ_ID_M 0x0001f000 19974 #define HTT_PPDU_ID_HWQ_ID_GET(_var) \ 19975 (((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S) 19976 19977 #define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \ 19978 do { \ 19979 HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \ 19980 ((_var) |= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \ 19981 } while (0) 19982 19983 #define HTT_PPDU_ID_MAC_ID_S 17 19984 #define HTT_PPDU_ID_MAC_ID_M 0x00060000 19985 #define HTT_PPDU_ID_MAC_ID_GET(_var) \ 19986 (((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S) 19987 19988 #define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \ 19989 do { \ 19990 HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \ 19991 ((_var) |= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \ 19992 } while (0) 19993 19994 #define HTT_PPDU_ID_SEQ_IDX_S 19 19995 #define HTT_PPDU_ID_SEQ_IDX_M 0x00180000 19996 #define HTT_PPDU_ID_SEQ_IDX_GET(_var) \ 19997 (((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S) 19998 19999 #define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \ 20000 do { \ 20001 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \ 20002 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \ 20003 } while (0) 20004 20005 #define HTT_PPDU_ID_TQM_CMD_S 23 20006 #define HTT_PPDU_ID_TQM_CMD_M 0x00800000 20007 #define HTT_PPDU_ID_TQM_CMD_GET(_var) \ 20008 (((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S) 20009 20010 #define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \ 20011 do { \ 20012 HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \ 20013 ((_var) |= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \ 20014 } while (0) 20015 20016 #define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24 20017 #define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000 20018 #define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \ 20019 (((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S) 20020 20021 #define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \ 20022 do { \ 20023 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \ 20024 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \ 20025 } while (0) 20026 20027 /** 20028 * @brief target -> RX PEER METADATA V0 format 20029 * Host will know the peer metadata version from the wmi_service_ready_ext2 20030 * message from target, and will confirm to the target which peer metadata 20031 * version to use in the wmi_init message. 20032 * 20033 * The following diagram shows the format of the RX PEER METADATA. 20034 * 20035 * |31 24|23 16|15 8|7 0| 20036 * |-----------------------------------------------------------------------| 20037 * | Reserved | VDEV ID | PEER ID | 20038 * |-----------------------------------------------------------------------| 20039 */ 20040 PREPACK struct htt_rx_peer_metadata_v0 { 20041 A_UINT32 20042 peer_id: 16, 20043 vdev_id: 8, 20044 reserved1: 8; 20045 } POSTPACK; 20046 20047 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_S 0 20048 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_M 0x0000ffff 20049 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_GET(_var) \ 20050 (((_var) & HTT_RX_PEER_META_DATA_V0_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V0_PEER_ID_S) 20051 20052 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_SET(_var, _val) \ 20053 do { \ 20054 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_PEER_ID, _val); \ 20055 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_PEER_ID_S)); \ 20056 } while (0) 20057 20058 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_S 16 20059 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_M 0x00ff0000 20060 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_GET(_var) \ 20061 (((_var) & HTT_RX_PEER_META_DATA_V0_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V0_VDEV_ID_S) 20062 20063 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_SET(_var, _val) \ 20064 do { \ 20065 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_VDEV_ID, _val); \ 20066 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_VDEV_ID_S)); \ 20067 } while (0) 20068 20069 /** 20070 * @brief target -> RX PEER METADATA V1 format 20071 * Host will know the peer metadata version from the wmi_service_ready_ext2 20072 * message from target, and will confirm to the target which peer metadata 20073 * version to use in the wmi_init message. 20074 * 20075 * The following diagram shows the format of the RX PEER METADATA V1 format. 20076 * 20077 * |31 29|28 26|25 24|23 16|15 14| 13 |12 0| 20078 * |---------------------------------------------------------------------------| 20079 * |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID| 20080 * |---------------------------------------------------------------------------| 20081 */ 20082 PREPACK struct htt_rx_peer_metadata_v1 { 20083 A_UINT32 20084 peer_id: 13, 20085 ml_peer_valid: 1, 20086 logical_link_id: 2, 20087 vdev_id: 8, 20088 lmac_id: 2, 20089 chip_id: 3, 20090 reserved2: 3; 20091 } POSTPACK; 20092 20093 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_S 0 20094 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_M 0x00001fff 20095 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_GET(_var) \ 20096 (((_var) & HTT_RX_PEER_META_DATA_V1_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1_PEER_ID_S) 20097 20098 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_SET(_var, _val) \ 20099 do { \ 20100 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_PEER_ID, _val); \ 20101 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_PEER_ID_S)); \ 20102 } while (0) 20103 20104 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S 13 20105 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M 0x00002000 20106 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_GET(_var) \ 20107 (((_var) & HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S) 20108 20109 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_SET(_var, _val) \ 20110 do { \ 20111 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID, _val); \ 20112 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S)); \ 20113 } while (0) 20114 20115 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_S 16 20116 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_M 0x00ff0000 20117 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \ 20118 (((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S) 20119 20120 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S 14 20121 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M 0x0000c000 20122 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \ 20123 (((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S) 20124 20125 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \ 20126 do { \ 20127 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val); \ 20128 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \ 20129 } while (0) 20130 20131 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \ 20132 do { \ 20133 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val); \ 20134 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)); \ 20135 } while (0) 20136 20137 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_S 24 20138 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_M 0x03000000 20139 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_GET(_var) \ 20140 (((_var) & HTT_RX_PEER_META_DATA_V1_LMAC_ID_M) >> HTT_RX_PEER_META_DATA_V1_LMAC_ID_S) 20141 20142 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_SET(_var, _val) \ 20143 do { \ 20144 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LMAC_ID, _val); \ 20145 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LMAC_ID_S)); \ 20146 } while (0) 20147 20148 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_S 26 20149 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_M 0x1c000000 20150 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_GET(_var) \ 20151 (((_var) & HTT_RX_PEER_META_DATA_V1_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1_CHIP_ID_S) 20152 20153 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_SET(_var, _val) \ 20154 do { \ 20155 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_CHIP_ID, _val); \ 20156 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ 20157 } while (0) 20158 20159 /** 20160 * @brief target -> RX PEER METADATA V1A format 20161 * Host will know the peer metadata version from the wmi_service_ready_ext2 20162 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20163 * and will confirm to the target which peer metadata version to use in the 20164 * wmi_init message. 20165 * 20166 * The following diagram shows the format of the RX PEER METADATA V1A format. 20167 * 20168 * |31 29|28 26|25 22|21 14| 13 |12 0| 20169 * |-------------------------------------------------------------------| 20170 * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20171 * |-------------------------------------------------------------------| 20172 */ 20173 PREPACK struct htt_rx_peer_metadata_v1a { 20174 A_UINT32 20175 peer_id: 13, 20176 ml_peer_valid: 1, 20177 vdev_id: 8, 20178 logical_link_id: 4, 20179 chip_id: 3, 20180 reserved2: 3; 20181 } POSTPACK; 20182 20183 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 20184 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff 20185 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ 20186 (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) 20187 20188 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ 20189 do { \ 20190 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ 20191 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ 20192 } while (0) 20193 20194 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 20195 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 20196 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ 20197 (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) 20198 20199 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ 20200 do { \ 20201 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ 20202 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ 20203 } while (0) 20204 20205 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 20206 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 20207 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ 20208 (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) 20209 20210 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ 20211 do { \ 20212 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ 20213 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ 20214 } while (0) 20215 20216 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 20217 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 20218 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ 20219 (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) 20220 20221 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ 20222 do { \ 20223 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ 20224 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ 20225 } while (0) 20226 20227 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 20228 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 20229 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ 20230 (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) 20231 20232 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ 20233 do { \ 20234 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ 20235 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ 20236 } while (0) 20237 20238 20239 /** 20240 * @brief target -> RX PEER METADATA V1B format 20241 * Host will know the peer metadata version from the wmi_service_ready_ext2 20242 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20243 * and will confirm to the target which peer metadata version to use in the 20244 * wmi_init message. 20245 * 20246 * The following diagram shows the format of the RX PEER METADATA V1B format. 20247 * 20248 * |31 29|28 26|25 22|21 14| 13 |12 0| 20249 * |--------------------------------------------------------------| 20250 * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20251 * |--------------------------------------------------------------| 20252 */ 20253 PREPACK struct htt_rx_peer_metadata_v1b { 20254 A_UINT32 20255 peer_id: 13, 20256 ml_peer_valid: 1, 20257 vdev_id: 8, 20258 hw_link_id: 4, 20259 chip_id: 3, 20260 reserved2: 3; 20261 } POSTPACK; 20262 20263 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 20264 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff 20265 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ 20266 (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) 20267 20268 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ 20269 do { \ 20270 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ 20271 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ 20272 } while (0) 20273 20274 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 20275 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 20276 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ 20277 (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) 20278 20279 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ 20280 do { \ 20281 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ 20282 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ 20283 } while (0) 20284 20285 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 20286 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 20287 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ 20288 (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) 20289 20290 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ 20291 do { \ 20292 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ 20293 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ 20294 } while (0) 20295 20296 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 20297 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 20298 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ 20299 (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) 20300 20301 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ 20302 do { \ 20303 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ 20304 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ 20305 } while (0) 20306 20307 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 20308 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 20309 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ 20310 (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) 20311 20312 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ 20313 do { \ 20314 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ 20315 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ 20316 } while (0) 20317 20318 /* generic variables for masks and shifts for various fields */ 20319 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; 20320 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; 20321 20322 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; 20323 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; 20324 20325 /* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ 20326 extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); 20327 extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); 20328 20329 extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); 20330 extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); 20331 20332 extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); 20333 extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); 20334 20335 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); 20336 extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20337 20338 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); 20339 extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); 20340 20341 extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); 20342 extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); 20343 20344 extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); 20345 extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20346 20347 20348 /* 20349 * In some systems, the host SW wants to specify priorities between 20350 * different MSDU / flow queues within the same peer-TID. 20351 * The below enums are used for the host to identify to the target 20352 * which MSDU queue's priority it wants to adjust. 20353 */ 20354 20355 /* 20356 * The MSDUQ index describe index of TCL HW, where each index is 20357 * used for queuing particular types of MSDUs. 20358 * The different MSDU queue types are defined in HTT_MSDU_QTYPE. 20359 */ 20360 enum HTT_MSDUQ_INDEX { 20361 HTT_MSDUQ_INDEX_NON_UDP, /* NON UDP MSDUQ index */ 20362 HTT_MSDUQ_INDEX_UDP, /* UDP MSDUQ index */ 20363 20364 HTT_MSDUQ_INDEX_CUSTOM_PRIO_0, /* Latency priority 0 index */ 20365 HTT_MSDUQ_INDEX_CUSTOM_PRIO_1, /* Latency priority 1 index */ 20366 20367 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_0, /* High num TID cases/ MLO dedicate link cases */ 20368 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_1, /* High num TID cases/ MLO dedicate link cases */ 20369 20370 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_2, /* High num TID cases/ MLO dedicate link cases */ 20371 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_3, /* High num TID cases/ MLO dedicate link cases */ 20372 20373 HTT_MSDUQ_MAX_INDEX, 20374 }; 20375 20376 /* MSDU qtype definition */ 20377 enum HTT_MSDU_QTYPE { 20378 /* 20379 * The LATENCY_CRIT_0 and LATENCY_CRIT_1 queue types don't have a fixed 20380 * relative priority. Instead, the relative priority of CRIT_0 versus 20381 * CRIT_1 is controlled by the FW, through the configuration parameters 20382 * it applies to the queues. 20383 */ 20384 HTT_MSDU_QTYPE_LATENCY_CRIT_0, /* Specified MSDUQ index used for latency critical 0 */ 20385 HTT_MSDU_QTYPE_LATENCY_CRIT_1, /* Specified MSDUQ index used for latency critical 1 */ 20386 HTT_MSDU_QTYPE_UDP, /* Specifies MSDUQ index used for UDP flow */ 20387 HTT_MSDU_QTYPE_NON_UDP, /* Specifies MSDUQ index used for non-udp flow */ 20388 HTT_MSDU_QTYPE_HOL, /* Specified MSDUQ index used for Head of Line */ 20389 HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */ 20390 HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */ 20391 HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */ 20392 20393 20394 /* New MSDU_QTYPE should be added above this line */ 20395 /* 20396 * Below QTYPE_MAX will increase if additional QTYPEs are defined 20397 * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in 20398 * any host/target message definitions. The QTYPE_MAX value can 20399 * only be used internally within the host or within the target. 20400 * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX 20401 * it must regard the unexpected value as a default qtype value, 20402 * or ignore it. 20403 */ 20404 HTT_MSDU_QTYPE_MAX, 20405 HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */ 20406 }; 20407 20408 enum HTT_MSDUQ_LEGACY_FLOW_INDEX { 20409 HTT_MSDUQ_LEGACY_HI_PRI_FLOW_INDEX = 0, 20410 HTT_MSDUQ_LEGACY_LO_PRI_FLOW_INDEX = 1, 20411 HTT_MSDUQ_LEGACY_UDP_FLOW_INDEX = 2, 20412 HTT_MSDUQ_LEGACY_NON_UDP_FLOW_INDEX = 3, 20413 }; 20414 20415 /** 20416 * @brief target -> host mlo timestamp offset indication 20417 * 20418 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 20419 * 20420 * @details 20421 * The following field definitions describe the format of the HTT target 20422 * to host mlo timestamp offset indication message. 20423 * 20424 * 20425 * |31 16|15 12|11 10|9 8|7 0 | 20426 * |----------------------------------------------------------------------| 20427 * | mac_clk_freq_mhz | rsvd |chip_id|pdev_id| msg type | 20428 * |----------------------------------------------------------------------| 20429 * | Sync time stamp lo in us | 20430 * |----------------------------------------------------------------------| 20431 * | Sync time stamp hi in us | 20432 * |----------------------------------------------------------------------| 20433 * | mlo time stamp offset lo in us | 20434 * |----------------------------------------------------------------------| 20435 * | mlo time stamp offset hi in us | 20436 * |----------------------------------------------------------------------| 20437 * | mlo time stamp offset clocks in clock ticks | 20438 * |----------------------------------------------------------------------| 20439 * |31 26|25 16|15 0 | 20440 * |rsvd2 | mlo time stamp | mlo time stamp compensation in us | 20441 * | | compensation in clks | | 20442 * |----------------------------------------------------------------------| 20443 * |31 22|21 0 | 20444 * | rsvd 3 | mlo time stamp comp timer period | 20445 * |----------------------------------------------------------------------| 20446 * The message is interpreted as follows: 20447 * 20448 * dword0 - b'0:7 - msg_type: This will be set to 20449 * HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 20450 * value: 0x28 20451 * 20452 * dword0 - b'9:8 - pdev_id 20453 * 20454 * dword0 - b'11:10 - chip_id 20455 * 20456 * dword0 - b'15:12 - rsvd1: Reserved for future use 20457 * 20458 * dword0 - b'31:16 - mac clock frequency of the mac HW block in MHz 20459 * 20460 * dword1 - b'31:0 - lower 32 bits of the WLAN global time stamp (in us) at 20461 * which last sync interrupt was received 20462 * 20463 * dword2 - b'31:0 - upper 32 bits of the WLAN global time stamp (in us) at 20464 * which last sync interrupt was received 20465 * 20466 * dword3 - b'31:0 - lower 32 bits of the MLO time stamp offset in us 20467 * 20468 * dword4 - b'31:0 - upper 32 bits of the MLO time stamp offset in us 20469 * 20470 * dword5 - b'31:0 - MLO time stamp offset in clock ticks for sub us 20471 * 20472 * dword6 - b'15:0 - MLO time stamp compensation applied in us 20473 * 20474 * dword6 - b'25:16 - MLO time stamp compensation applied in clock ticks 20475 * for sub us resolution 20476 * 20477 * dword6 - b'31:26 - rsvd2: Reserved for future use 20478 * 20479 * dword7 - b'21:0 - period of MLO compensation timer at which compensation 20480 * is applied, in us 20481 * 20482 * dword7 - b'31:22 - rsvd3: Reserved for future use 20483 */ 20484 20485 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M 0x000000FF 20486 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S 0 20487 20488 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M 0x00000300 20489 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S 8 20490 20491 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M 0x00000C00 20492 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S 10 20493 20494 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M 0xFFFF0000 20495 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S 16 20496 20497 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M 0x0000FFFF 20498 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S 0 20499 20500 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M 0x03FF0000 20501 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S 16 20502 20503 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M 0x003FFFFF 20504 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S 0 20505 20506 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_GET(_var) \ 20507 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S) 20508 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_SET(_var, _val) \ 20509 do { \ 20510 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE, _val); \ 20511 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)); \ 20512 } while (0) 20513 20514 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_GET(_var) \ 20515 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S) 20516 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_SET(_var, _val) \ 20517 do { \ 20518 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID, _val); \ 20519 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)); \ 20520 } while (0) 20521 20522 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_GET(_var) \ 20523 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S) 20524 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_SET(_var, _val) \ 20525 do { \ 20526 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID, _val); \ 20527 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)); \ 20528 } while (0) 20529 20530 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_GET(_var) \ 20531 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M) >> \ 20532 HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S) 20533 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_SET(_var, _val) \ 20534 do { \ 20535 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ, _val); \ 20536 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)); \ 20537 } while (0) 20538 20539 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_GET(_var) \ 20540 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M) >> \ 20541 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S) 20542 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_SET(_var, _val) \ 20543 do { \ 20544 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US, _val); \ 20545 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)); \ 20546 } while (0) 20547 20548 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_GET(_var) \ 20549 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M) >> \ 20550 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S) 20551 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_SET(_var, _val) \ 20552 do { \ 20553 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS, _val); \ 20554 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)); \ 20555 } while (0) 20556 20557 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_GET(_var) \ 20558 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M) >> \ 20559 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S) 20560 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_SET(_var, _val) \ 20561 do { \ 20562 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US, _val); \ 20563 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)); \ 20564 } while (0) 20565 20566 typedef struct { 20567 A_UINT32 msg_type: 8, /* bits 7:0 */ 20568 pdev_id: 2, /* bits 9:8 */ 20569 chip_id: 2, /* bits 11:10 */ 20570 reserved1: 4, /* bits 15:12 */ 20571 mac_clk_freq_mhz: 16; /* bits 31:16 */ 20572 A_UINT32 sync_timestamp_lo_us; 20573 A_UINT32 sync_timestamp_hi_us; 20574 A_UINT32 mlo_timestamp_offset_lo_us; 20575 A_UINT32 mlo_timestamp_offset_hi_us; 20576 A_UINT32 mlo_timestamp_offset_clks; 20577 A_UINT32 mlo_timestamp_comp_us: 16, /* bits 15:0 */ 20578 mlo_timestamp_comp_clks: 10, /* bits 25:16 */ 20579 reserved2: 6; /* bits 31:26 */ 20580 A_UINT32 mlo_timestamp_comp_timer_period_us: 22, /* bits 21:0 */ 20581 reserved3: 10; /* bits 31:22 */ 20582 } htt_t2h_mlo_offset_ind_t; 20583 20584 /* 20585 * @brief target -> host VDEV TX RX STATS 20586 * 20587 * MSG_TYPE => HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND 20588 * 20589 * @details 20590 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message is sent by the target 20591 * every periodic interval programmed in HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG. 20592 * After the host sends an initial HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 20593 * this HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message will be sent 20594 * periodically by target even in the absence of any further HTT request 20595 * messages from host. 20596 * 20597 * The message is formatted as follows: 20598 * 20599 * |31 16|15 8|7 0| 20600 * |---------------------------------+----------------+----------------| 20601 * | payload_size | pdev_id | msg_type | 20602 * |---------------------------------+----------------+----------------| 20603 * | reserved0 | 20604 * |-------------------------------------------------------------------| 20605 * | reserved1 | 20606 * |-------------------------------------------------------------------| 20607 * | reserved2 | 20608 * |-------------------------------------------------------------------| 20609 * | | 20610 * | VDEV specific Tx Rx stats info | 20611 * | | 20612 * |-------------------------------------------------------------------| 20613 * 20614 * The message is interpreted as follows: 20615 * dword0 - b'0:7 - msg_type: This will be set to 0x2c 20616 * (HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND) 20617 * b'8:15 - pdev_id 20618 * b'16:31 - size in bytes of the payload that follows the 16-byte 20619 * message header fields (msg_type through reserved2) 20620 * dword1 - b'0:31 - reserved0. 20621 * dword2 - b'0:31 - reserved1. 20622 * dword3 - b'0:31 - reserved2. 20623 */ 20624 typedef struct { 20625 A_UINT32 msg_type: 8, 20626 pdev_id: 8, 20627 payload_size: 16; 20628 A_UINT32 reserved0; 20629 A_UINT32 reserved1; 20630 A_UINT32 reserved2; 20631 } htt_t2h_vdevs_txrx_stats_periodic_hdr_t; 20632 20633 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_HDR_SIZE 16 20634 20635 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M 0x0000FF00 20636 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S 8 20637 20638 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 20639 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S) 20640 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 20641 do { \ 20642 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID, _val); \ 20643 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S)); \ 20644 } while (0) 20645 20646 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M 0xFFFF0000 20647 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S 16 20648 20649 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_GET(_var) \ 20650 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S) 20651 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_SET(_var, _val) \ 20652 do { \ 20653 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE, _val); \ 20654 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S)); \ 20655 } while (0) 20656 20657 /* SOC related stats */ 20658 typedef struct { 20659 htt_tlv_hdr_t tlv_hdr; 20660 20661 /* When TQM is not able to find the peers during Tx, then it drops the packets 20662 * This can be due to either the peer is deleted or deletion is ongoing 20663 * */ 20664 A_UINT32 inv_peers_msdu_drop_count_lo; 20665 A_UINT32 inv_peers_msdu_drop_count_hi; 20666 } htt_stats_soc_txrx_stats_common_tlv; 20667 /* preserve old name alias for new name consistent with the tag name */ 20668 typedef htt_stats_soc_txrx_stats_common_tlv htt_t2h_soc_txrx_stats_common_tlv; 20669 20670 /* VDEV HW Tx/Rx stats */ 20671 typedef struct { 20672 htt_tlv_hdr_t tlv_hdr; 20673 A_UINT32 vdev_id; 20674 20675 /* Rx msdu byte cnt */ 20676 A_UINT32 rx_msdu_byte_cnt_lo; 20677 A_UINT32 rx_msdu_byte_cnt_hi; 20678 20679 /* Rx msdu cnt */ 20680 A_UINT32 rx_msdu_cnt_lo; 20681 A_UINT32 rx_msdu_cnt_hi; 20682 20683 /* tx msdu byte cnt */ 20684 A_UINT32 tx_msdu_byte_cnt_lo; 20685 A_UINT32 tx_msdu_byte_cnt_hi; 20686 20687 /* tx msdu cnt */ 20688 A_UINT32 tx_msdu_cnt_lo; 20689 A_UINT32 tx_msdu_cnt_hi; 20690 20691 /* tx excessive retry discarded msdu cnt */ 20692 A_UINT32 tx_msdu_excessive_retry_discard_cnt_lo; 20693 A_UINT32 tx_msdu_excessive_retry_discard_cnt_hi; 20694 20695 /* TX congestion ctrl msdu drop cnt */ 20696 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_lo; 20697 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_hi; 20698 20699 /* discarded tx msdus cnt coz of time to live expiry */ 20700 A_UINT32 tx_msdu_ttl_expire_drop_cnt_lo; 20701 A_UINT32 tx_msdu_ttl_expire_drop_cnt_hi; 20702 20703 /* tx excessive retry discarded msdu byte cnt */ 20704 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_lo; 20705 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_hi; 20706 20707 /* TX congestion ctrl msdu drop byte cnt */ 20708 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_lo; 20709 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_hi; 20710 20711 /* discarded tx msdus byte cnt coz of time to live expiry */ 20712 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_lo; 20713 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_hi; 20714 20715 /* TQM bypass frame cnt */ 20716 A_UINT32 tqm_bypass_frame_cnt_lo; 20717 A_UINT32 tqm_bypass_frame_cnt_hi; 20718 20719 /* TQM bypass byte cnt */ 20720 A_UINT32 tqm_bypass_byte_cnt_lo; 20721 A_UINT32 tqm_bypass_byte_cnt_hi; 20722 } htt_stats_vdev_txrx_stats_hw_stats_tlv; 20723 /* preserve old name alias for new name consistent with the tag name */ 20724 typedef htt_stats_vdev_txrx_stats_hw_stats_tlv 20725 htt_t2h_vdev_txrx_stats_hw_stats_tlv; 20726 20727 /* 20728 * MSG_TYPE => HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF 20729 * 20730 * @details 20731 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF message is sent by the target in 20732 * response to a SAWF_DEF_QUEUES_MAP_REPORT_REQ from the host. 20733 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF will show which service class 20734 * the default MSDU queues of each of the specified TIDs for the peer 20735 * specified in the SAWF_DEF_QUEUES_MAP_REPORT_REQ message are linked to. 20736 * If the default MSDU queues of a given TID within the peer are not linked 20737 * to a service class, the svc_class_id field for that TID will have a 20738 * 0xff HTT_SAWF_SVC_CLASS_INVALID_ID value to indicate the default MSDU 20739 * queues for that TID are not mapped to any service class. 20740 * 20741 * |31 16|15 8|7 0| 20742 * |------------------------------+--------------+--------------| 20743 * | peer ID | reserved | msg type | 20744 * |------------------------------+--------------+------+-------| 20745 * | reserved | svc class ID | TID | 20746 * |------------------------------------------------------------| 20747 * ... 20748 * |------------------------------------------------------------| 20749 * | reserved | svc class ID | TID | 20750 * |------------------------------------------------------------| 20751 * Header fields: 20752 * dword0 - b'7:0 - msg_type: This will be set to 20753 * 0x2d (HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF) 20754 * b'31:16 - peer ID 20755 * dword1 - b'7:0 - TID 20756 * b'15:8 - svc class ID 20757 * (dword2, etc. same format as dword1) 20758 */ 20759 20760 #define HTT_SAWF_SVC_CLASS_INVALID_ID 0xff 20761 20762 PREPACK struct htt_t2h_sawf_def_queues_map_report_conf { 20763 A_UINT32 msg_type :8, 20764 reserved0 :8, 20765 peer_id :16; 20766 struct { 20767 A_UINT32 tid :8, 20768 svc_class_id :8, 20769 reserved1 :16; 20770 } tid_reports[1/*or more*/]; 20771 } POSTPACK; 20772 20773 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_HDR_BYTES 4 /* msg_type, peer_id */ 20774 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_ELEM_BYTES 4 /* TID, svc_class_id */ 20775 20776 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M 0xFFFF0000 20777 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S 16 20778 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_GET(_var) \ 20779 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M) >> \ 20780 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S) 20781 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_SET(_var, _val) \ 20782 do { \ 20783 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID, _val); \ 20784 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S)); \ 20785 } while (0) 20786 20787 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M 0x000000FF 20788 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S 0 20789 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_GET(_var) \ 20790 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M) >> \ 20791 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S) 20792 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_SET(_var, _val) \ 20793 do { \ 20794 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID, _val); \ 20795 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S)); \ 20796 } while (0) 20797 20798 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M 0x0000FF00 20799 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S 8 20800 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_GET(_var) \ 20801 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M) >> \ 20802 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S) 20803 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_SET(_var, _val) \ 20804 do { \ 20805 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID, _val); \ 20806 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S)); \ 20807 } while (0) 20808 20809 20810 /* 20811 * MSG_TYPE => HTT_T2H_SAWF_MSDUQ_INFO_IND 20812 * 20813 * @details 20814 * When SAWF is enabled and a flow is mapped to a policy during the traffic 20815 * flow if the flow is seen the associated service class is conveyed to the 20816 * target via TCL Data Command. Target on the other hand internally creates the 20817 * MSDUQ. Once the target creates the MSDUQ the target sends the information 20818 * of the newly created MSDUQ and some other identifiers to uniquely identity 20819 * the newly created MSDUQ 20820 * 20821 * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0| 20822 * |------------------------------+------------------------+--------------| 20823 * | peer ID | HTT qtype | msg type | 20824 * |---------------------------------+--------------+--+---+-------+------| 20825 * | reserved |AST list index|FO|WC | HLOS | remap| 20826 * | | | | | TID | TID | 20827 * |---------------------+------------------------------------------------| 20828 * | reserved1 | tgt_opaque_id | 20829 * |---------------------+------------------------------------------------| 20830 * 20831 * Header fields: 20832 * 20833 * dword0 - b'7:0 - msg_type: This will be set to 20834 * 0x2e (HTT_T2H_SAWF_MSDUQ_INFO_IND) 20835 * b'15:8 - HTT qtype 20836 * b'31:16 - peer ID 20837 * 20838 * dword1 - b'3:0 - remap TID, as assigned in firmware 20839 * b'7:4 - HLOS TID, as sent by host in TCL Data Command 20840 * hlos_tid : Common to Lithium and Beryllium 20841 * b'9:8 - who_classify_info_sel (WC), as sent by host in 20842 * TCL Data Command : Beryllium 20843 * b10 - flow_override (FO), as sent by host in 20844 * TCL Data Command: Beryllium 20845 * b11:14 - ast_list_idx 20846 * Array index into the list of extension AST entries 20847 * (not the actual AST 16-bit index). 20848 * The ast_list_idx is one-based, with the following 20849 * range of values: 20850 * - legacy targets supporting 16 user-defined 20851 * MSDU queues: 1-2 20852 * - legacy targets supporting 48 user-defined 20853 * MSDU queues: 1-6 20854 * - new targets: 0 (peer_id is used instead) 20855 * Note that since ast_list_idx is one-based, 20856 * the host will need to subtract 1 to use it as an 20857 * index into a list of extension AST entries. 20858 * b15:31 - reserved 20859 * 20860 * dword2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a 20861 * unique MSDUQ id in firmware 20862 * b'24:31 - reserved1 20863 */ 20864 PREPACK struct htt_t2h_sawf_msduq_event { 20865 A_UINT32 msg_type : 8, 20866 htt_qtype : 8, 20867 peer_id :16; 20868 20869 A_UINT32 remap_tid : 4, 20870 hlos_tid : 4, 20871 who_classify_info_sel : 2, 20872 flow_override : 1, 20873 ast_list_idx : 4, 20874 reserved :17; 20875 20876 A_UINT32 tgt_opaque_id :24, 20877 reserved1 : 8; 20878 } POSTPACK; 20879 20880 #define HTT_SAWF_MSDUQ_INFO_SIZE (sizeof(struct htt_t2h_sawf_msduq_event)) 20881 20882 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M 0x0000FF00 20883 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S 8 20884 20885 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_GET(_var) \ 20886 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M) >> \ 20887 HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S) 20888 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_SET(_var, _val) \ 20889 do { \ 20890 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE, _val); \ 20891 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S));\ 20892 } while (0) 20893 20894 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M 0xFFFF0000 20895 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S 16 20896 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_GET(_var) \ 20897 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M) >> \ 20898 HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S) 20899 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_SET(_var, _val) \ 20900 do { \ 20901 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID, _val); \ 20902 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S)); \ 20903 } while (0) 20904 20905 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M 0x0000000F 20906 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S 0 20907 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_GET(_var) \ 20908 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M) >> \ 20909 HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S) 20910 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_SET(_var, _val) \ 20911 do { \ 20912 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID, _val); \ 20913 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S)); \ 20914 } while (0) 20915 20916 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M 0x000000F0 20917 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S 4 20918 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_GET(_var) \ 20919 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M) >> \ 20920 HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S) 20921 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_SET(_var, _val) \ 20922 do { \ 20923 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID, _val); \ 20924 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S)); \ 20925 } while (0) 20926 20927 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M 0x00000300 20928 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S 8 20929 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_GET(_var) \ 20930 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M) >> \ 20931 HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S) 20932 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_SET(_var, _val) \ 20933 do { \ 20934 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL, _val); \ 20935 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S)); \ 20936 } while (0) 20937 20938 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M 0x00000400 20939 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S 10 20940 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_GET(_var) \ 20941 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M) >> \ 20942 HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S) 20943 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_SET(_var, _val) \ 20944 do { \ 20945 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE, _val); \ 20946 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)); \ 20947 } while (0) 20948 20949 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M 0x00007800 20950 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S 11 20951 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_GET(_var) \ 20952 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M) >> \ 20953 HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S) 20954 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_SET(_var, _val) \ 20955 do { \ 20956 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX, _val); \ 20957 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)); \ 20958 } while (0) 20959 20960 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M 0x00FFFFFF 20961 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S 0 20962 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_GET(_var) \ 20963 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID) >> \ 20964 HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S) 20965 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_SET(_var, _val) \ 20966 do { \ 20967 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID, _val); \ 20968 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S)); \ 20969 } while (0) 20970 20971 20972 /** 20973 * @brief target -> PPDU id format indication 20974 * 20975 * MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND 20976 * 20977 * @details 20978 * The following field definitions describe the format of the HTT target 20979 * to host PPDU ID format indication message. 20980 * hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command. 20981 * ring_id :- HWSCH ring id in which this PPDU was enqueued. 20982 * seq_idx :- Sequence control index of this PPDU. 20983 * link_id :- HW link ID of the link in which the PPDU was enqueued. 20984 * seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.) 20985 * tqm_cmd:- 20986 * 20987 * |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 | 20988 * |--------------------------------------------------+------------------------| 20989 * | rsvd0 | msg type | 20990 * |-----+----------+----------+---------+-----+----------+----------+---------| 20991 * |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V | 20992 * |-----+----------+----------+---------+-----+----------+----------+---------| 20993 * |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V| 20994 * |-----+----------+----------+---------+-----+----------+----------+---------| 20995 * |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V| 20996 * |-----+----------+----------+---------+-----+----------+----------+---------| 20997 * |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V | 20998 * |-----+----------+----------+---------+-----+----------+----------+---------| 20999 * Where: OF = bit offset, NB = number of bits, V = valid 21000 * The message is interpreted as follows: 21001 * 21002 * dword0 - b'7:0 - msg_type: This will be set to 21003 * HTT_T2H_PPDU_ID_FMT_IND 21004 * value: 0x30 21005 * 21006 * dword0 - b'31:8 - reserved 21007 * 21008 * dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not 21009 * 21010 * dword1 - b'5:1 - number of bits in hwsch_cmd_id 21011 * 21012 * dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits) 21013 * 21014 * dword1 - b'15:11 - reserved for future use 21015 * 21016 * dword1 - b'16:16 - field to indicate whether ring_id is valid or not 21017 * 21018 * dword1 - b'21:17 - number of bits in ring_id 21019 * 21020 * dword1 - b'26:22 - offset of ring_id (in number of bits) 21021 * 21022 * dword1 - b'31:27 - reserved for future use 21023 * 21024 * dword2 - b'0:0 - field to indicate whether sequence index is valid or not 21025 * 21026 * dword2 - b'5:1 - number of bits in sequence index 21027 * 21028 * dword2 - b'10:6 - offset of sequence index (in number of bits) 21029 * 21030 * dword2 - b'15:11 - reserved for future use 21031 * 21032 * dword2 - b'16:16 - field to indicate whether link_id is valid or not 21033 * 21034 * dword2 - b'21:17 - number of bits in link_id 21035 * 21036 * dword2 - b'26:22 - offset of link_id (in number of bits) 21037 * 21038 * dword2 - b'31:27 - reserved for future use 21039 * 21040 * dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not 21041 * 21042 * dword3 - b'5:1 - number of bits in seq_cmd_type 21043 * 21044 * dword3 - b'10:6 - offset of seq_cmd_type (in number of bits) 21045 * 21046 * dword3 - b'15:11 - reserved for future use 21047 * 21048 * dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not 21049 * 21050 * dword3 - b'21:17 - number of bits in tqm_cmd 21051 * 21052 * dword3 - b'26:22 - offset of tqm_cmd (in number of bits) 21053 * 21054 * dword3 - b'31:27 - reserved for future use 21055 * 21056 * dword4 - b'0:0 - field to indicate whether mac_id is valid or not 21057 * 21058 * dword4 - b'5:1 - number of bits in mac_id 21059 * 21060 * dword4 - b'10:6 - offset of mac_id (in number of bits) 21061 * 21062 * dword4 - b'15:11 - reserved for future use 21063 * 21064 * dword4 - b'16:16 - field to indicate whether crc is valid or not 21065 * 21066 * dword4 - b'21:17 - number of bits in crc 21067 * 21068 * dword4 - b'26:22 - offset of crc (in number of bits) 21069 * 21070 * dword4 - b'31:27 - reserved for future use 21071 * 21072 */ 21073 21074 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001 21075 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0 21076 21077 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E 21078 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1 21079 21080 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0 21081 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6 21082 21083 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000 21084 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16 21085 21086 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000 21087 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17 21088 21089 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000 21090 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22 21091 21092 21093 /* macros for accessing lower 16 bits in dword */ 21094 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \ 21095 do { \ 21096 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \ 21097 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \ 21098 } while (0) 21099 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \ 21100 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S) 21101 21102 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \ 21103 do { \ 21104 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \ 21105 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \ 21106 } while (0) 21107 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \ 21108 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S) 21109 21110 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \ 21111 do { \ 21112 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \ 21113 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \ 21114 } while (0) 21115 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \ 21116 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S) 21117 21118 /* macros for accessing upper 16 bits in dword */ 21119 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \ 21120 do { \ 21121 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \ 21122 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \ 21123 } while (0) 21124 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \ 21125 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S) 21126 21127 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \ 21128 do { \ 21129 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \ 21130 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \ 21131 } while (0) 21132 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \ 21133 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S) 21134 21135 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \ 21136 do { \ 21137 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \ 21138 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \ 21139 } while (0) 21140 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \ 21141 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S) 21142 21143 21144 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \ 21145 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21146 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \ 21147 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21148 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \ 21149 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21150 21151 #define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \ 21152 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21153 #define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \ 21154 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21155 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \ 21156 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21157 21158 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \ 21159 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21160 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \ 21161 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21162 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \ 21163 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21164 21165 #define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \ 21166 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21167 #define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \ 21168 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21169 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \ 21170 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21171 21172 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \ 21173 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21174 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \ 21175 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21176 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \ 21177 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21178 21179 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \ 21180 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21181 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \ 21182 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21183 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \ 21184 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21185 21186 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \ 21187 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21188 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \ 21189 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21190 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \ 21191 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21192 21193 #define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \ 21194 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21195 #define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \ 21196 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21197 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \ 21198 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21199 21200 21201 /* offsets in number dwords */ 21202 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1 21203 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1 21204 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2 21205 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2 21206 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3 21207 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3 21208 #define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4 21209 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4 21210 21211 21212 typedef struct { 21213 A_UINT32 msg_type: 8, /* bits 7:0 */ 21214 rsvd0: 24;/* bits 31:8 */ 21215 A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */ 21216 hwsch_cmd_id_bits: 5, /* bits 5:1 */ 21217 hwsch_cmd_id_offset: 5, /* bits 10:6 */ 21218 rsvd1: 5, /* bits 15:11 */ 21219 ring_id_valid: 1, /* bits 16:16 */ 21220 ring_id_bits: 5, /* bits 21:17 */ 21221 ring_id_offset: 5, /* bits 26:22 */ 21222 rsvd2: 5; /* bits 31:27 */ 21223 A_UINT32 seq_idx_valid: 1, /* bits 0:0 */ 21224 seq_idx_bits: 5, /* bits 5:1 */ 21225 seq_idx_offset: 5, /* bits 10:6 */ 21226 rsvd3: 5, /* bits 15:11 */ 21227 link_id_valid: 1, /* bits 16:16 */ 21228 link_id_bits: 5, /* bits 21:17 */ 21229 link_id_offset: 5, /* bits 26:22 */ 21230 rsvd4: 5; /* bits 31:27 */ 21231 A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */ 21232 seq_cmd_type_bits: 5, /* bits 5:1 */ 21233 seq_cmd_type_offset: 5, /* bits 10:6 */ 21234 rsvd5: 5, /* bits 15:11 */ 21235 tqm_cmd_valid: 1, /* bits 16:16 */ 21236 tqm_cmd_bits: 5, /* bits 21:17 */ 21237 tqm_cmd_offset: 5, /* bits 26:12 */ 21238 rsvd6: 5; /* bits 31:27 */ 21239 A_UINT32 mac_id_valid: 1, /* bits 0:0 */ 21240 mac_id_bits: 5, /* bits 5:1 */ 21241 mac_id_offset: 5, /* bits 10:6 */ 21242 rsvd8: 5, /* bits 15:11 */ 21243 crc_valid: 1, /* bits 16:16 */ 21244 crc_bits: 5, /* bits 21:17 */ 21245 crc_offset: 5, /* bits 26:12 */ 21246 rsvd9: 5; /* bits 31:27 */ 21247 } htt_t2h_ppdu_id_fmt_ind_t; 21248 21249 21250 /** 21251 * @brief target -> host RX_CCE_SUPER_RULE setup done message 21252 * 21253 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE 21254 * 21255 * @details 21256 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target 21257 * when RX_CCE_SUPER_RULE setup is done 21258 * 21259 * This message shows the configuration results after the setup operation. 21260 * It will always be sent to host. 21261 * The message would appear as follows: 21262 * 21263 * |31 24|23 16|15 8|7 0| 21264 * |-----------------+-----------------+----------------+----------------| 21265 * | result | response_type | pdev_id | msg_type | 21266 * |---------------------------------------------------------------------| 21267 * 21268 * The message is interpreted as follows: 21269 * dword0 - b'0:7 - msg_type: This will be set to 0x33 21270 * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) 21271 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on 21272 * b'16:23 - response_type: Indicate the response type of this setup 21273 * done msg 21274 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, 21275 * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 21276 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21277 * response to HTT_RX_CCE_SUPER_RULE_INSTALL 21278 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21279 * response to HTT_RX_CCE_SUPER_RULE_RELEASE 21280 * b'24:31 - result: Indicate result of setup operation 21281 * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE: 21282 * b'24 - is_rule_enough: indicate if there are 21283 * enough free cce rule slots 21284 * 0: not enough 21285 * 1: enough 21286 * b'25:31 - avail_rule_num: indicate the number of 21287 * remaining free cce rule slots, only makes sense 21288 * when is_rule_enough = 0 21289 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE: 21290 * b'24 - cfg_result_0: indicate the config result 21291 * of RX_CCE_SUPER_RULE_0 21292 * 0: Install/Uninstall fails 21293 * 1: Install/Uninstall succeeds 21294 * b'25 - cfg_result_1: indicate the config result 21295 * of RX_CCE_SUPER_RULE_1 21296 * 0: Install/Uninstall fails 21297 * 1: Install/Uninstall succeeds 21298 * b'26:31 - reserved 21299 * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE: 21300 * b'24 - cfg_result_0: indicate the config result 21301 * of RX_CCE_SUPER_RULE_0 21302 * 0: Release fails 21303 * 1: Release succeeds 21304 * b'25 - cfg_result_1: indicate the config result 21305 * of RX_CCE_SUPER_RULE_1 21306 * 0: Release fails 21307 * 1: Release succeeds 21308 * b'26:31 - reserved 21309 */ 21310 21311 enum htt_rx_cce_super_rule_setup_done_response_type { 21312 HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0, 21313 HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21314 HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21315 21316 /*All reply type should be before this*/ 21317 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE, 21318 }; 21319 21320 PREPACK struct htt_rx_cce_super_rule_setup_done_t { 21321 A_UINT8 msg_type; 21322 A_UINT8 pdev_id; 21323 A_UINT8 response_type; 21324 union { 21325 struct { 21326 /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */ 21327 A_UINT8 is_rule_enough: 1, 21328 avail_rule_num: 7; 21329 }; 21330 struct { 21331 /* 21332 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and 21333 * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE 21334 */ 21335 A_UINT8 cfg_result_0: 1, 21336 cfg_result_1: 1, 21337 rsvd: 6; 21338 }; 21339 } result; 21340 } POSTPACK; 21341 21342 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) 21343 21344 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 21345 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 21346 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ 21347 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ 21348 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) 21349 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 21350 do { \ 21351 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ 21352 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ 21353 } while (0) 21354 21355 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 21356 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 21357 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ 21358 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ 21359 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) 21360 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ 21361 do { \ 21362 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ 21363 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ 21364 } while (0) 21365 21366 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000 21367 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24 21368 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ 21369 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ 21370 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S) 21371 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ 21372 do { \ 21373 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ 21374 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ 21375 } while (0) 21376 21377 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000 21378 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24 21379 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \ 21380 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \ 21381 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S) 21382 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \ 21383 do { \ 21384 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \ 21385 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \ 21386 } while (0) 21387 21388 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000 21389 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25 21390 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \ 21391 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \ 21392 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S) 21393 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \ 21394 do { \ 21395 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \ 21396 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \ 21397 } while (0) 21398 21399 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000 21400 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24 21401 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \ 21402 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \ 21403 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S) 21404 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \ 21405 do { \ 21406 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \ 21407 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \ 21408 } while (0) 21409 21410 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000 21411 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25 21412 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \ 21413 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \ 21414 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S) 21415 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \ 21416 do { \ 21417 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \ 21418 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ 21419 } while (0) 21420 21421 /** 21422 * THE BELOW MESSAGE HAS BEEN DEPRECATED 21423 *====================================== 21424 * @brief target -> host CoDel MSDU queue latencies array configuration 21425 * 21426 * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND 21427 * 21428 * @details 21429 * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used 21430 * by the target to inform the host of the location and size of the DDR array of 21431 * per MSDU queue latency metrics. This array is updated by the host and 21432 * read by the target. The target uses these metric values to determine 21433 * which MSDU queues have latencies exceeding their CoDel latency target. 21434 * 21435 * |31 16|15 8|7 0| 21436 * |-------------------------------------------+----------| 21437 * | number of array elements | reserved | MSG_TYPE | 21438 * |-------------------------------------------+----------| 21439 * | array physical address, low bits | 21440 * |------------------------------------------------------| 21441 * | array physical address, high bits | 21442 * |------------------------------------------------------| 21443 * Header fields: 21444 * - MSG_TYPE 21445 * Bits 7:0 21446 * Purpose: Identifies this as a CoDel MSDU queue latencies 21447 * array configuration message. 21448 * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND) 21449 * - NUM_ELEM 21450 * Bits 31:16 21451 * Purpose: Inform the host of the length of the MSDU queue latencies array. 21452 * Value: Specifies the number of elements in the MSDU queue latency 21453 * metrics array. This value is the same as the maximum number of 21454 * MSDU queues supported by the target. 21455 * Since each array element is 16 bits, the size in bytes of the 21456 * MSDU queue latency metrics array is twice the number of elements. 21457 * - PADDR_LOW 21458 * Bits 31:0 21459 * Purpose: Inform the host of the MSDU queue latencies array's location. 21460 * Value: Lower 32 bits of the physical address of the MSDU queue latency 21461 * metrics array. 21462 * - PADDR_HIGH 21463 * Bits 31:0 21464 * Purpose: Inform the host of the MSDU queue latencies array's location. 21465 * Value: Upper 32 bits of the physical address of the MSDU queue latency 21466 * metrics array. 21467 */ 21468 typedef struct { 21469 A_UINT32 msg_type: 8, /* bits 7:0 */ 21470 reserved: 8, /* bits 15:8 */ 21471 num_elem: 16; /* bits 31:16 */ 21472 A_UINT32 paddr_low; 21473 A_UINT32 paddr_high; 21474 } htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */ 21475 21476 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ 21477 21478 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000 21479 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16 21480 21481 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \ 21482 (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \ 21483 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S) 21484 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \ 21485 do { \ 21486 HTT_CHECK_SET_VAL( \ 21487 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \ 21488 ((_var) |= ((_val) << \ 21489 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \ 21490 } while (0) 21491 21492 /* 21493 * This CoDel MSDU queue latencies array whose location and number of 21494 * elements are specified by this HTT_T2H message consists of 16-bit elements 21495 * that each specify a statistical summary (min) of a MSDU queue's latency, 21496 * using milliseconds units. 21497 */ 21498 #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 21499 21500 21501 /** 21502 * @brief target -> host rx completion indication message definition 21503 * 21504 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND 21505 * 21506 * @details 21507 * The following diagram shows the format of the Rx completion indication sent 21508 * from the target to the host 21509 * 21510 * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| 21511 * |---------------+----------------------------+----------------| 21512 * | vdev_id | peer_id | msg_type | 21513 * hdr: |---------------+--------------------------+-+----------------| 21514 * | rsvd0 |F| msdu_cnt | 21515 * pyld: |==========================================+=+================| 21516 * MSDU 0 | buf addr lo (bits 31:0) | 21517 * |-----+--------------------------------------+----------------| 21518 * |rsvd1| SW buffer cookie | buf addr hi | 21519 * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| 21520 * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| 21521 * |-------------------------------------------------+---------+-| 21522 * | rsvd3 | err info|E| 21523 * |=================================================+=========+=| 21524 * MSDU 1 | buf addr lo (bits 31:0) | 21525 * : ... : 21526 * | rsvd3 | err info|E| 21527 * |-------------------------------------------------------------| 21528 * Where: 21529 * F = fragment 21530 * M = MPDU retry bit 21531 * R = raw MPDU frame 21532 * F = first MSDU in MPDU 21533 * L = last MSDU in MPDU 21534 * C = MSDU continuation 21535 * S = Souce Addr is valid 21536 * D = Dest Addr is valid 21537 * MC = Dest Addr is multicast / broadcast 21538 * W = is first MSDU after WoW wakeup 21539 * R2 = rsvd2 21540 * E = error valid 21541 */ 21542 21543 /* htt_t2h_rx_data_msdu_err: 21544 * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field 21545 * when FW forwards MSDU to host. 21546 */ 21547 typedef enum htt_t2h_rx_data_msdu_err { 21548 /* ERR_DECRYPT: 21549 * FW sets this when rxdma_error_code = <enum 3 rxdma_decrypt_err>. 21550 * host maintains error stats, recycles buffer. 21551 */ 21552 HTT_RXDATA_ERR_DECRYPT = 0, 21553 21554 /* ERR_TKIP_MIC: 21555 * FW sets this when rxdma_error_code = <enum 4 rxdma_tkip_mic_err>. 21556 * Host maintains error stats, recycles buffer, sends notification to 21557 * middleware. 21558 */ 21559 HTT_RXDATA_ERR_TKIP_MIC = 1, 21560 21561 /* ERR_UNENCRYPTED: 21562 * FW sets this when rxdma_error_code = <enum 5 rxdma_unecrypted_err>. 21563 * Host maintains error stats, recycles buffer. 21564 */ 21565 HTT_RXDATA_ERR_UNENCRYPTED = 2, 21566 21567 /* ERR_MSDU_LIMIT: 21568 * FW sets this when rxdma_error_code = <enum 7 rxdma_msdu_limit_err>. 21569 * Host maintains error stats, recycles buffer. 21570 */ 21571 HTT_RXDATA_ERR_MSDU_LIMIT = 3, 21572 21573 /* ERR_FLUSH_REQUEST: 21574 * FW sets this when rxdma_error_code = <enum 13 rxdma_flush_request>. 21575 * Host maintains error stats, recycles buffer. 21576 */ 21577 HTT_RXDATA_ERR_FLUSH_REQUEST = 4, 21578 21579 /* ERR_OOR: 21580 * FW full reorder layer maps this error to <enum 7 regular_frame_OOR>. 21581 * Host maintains error stats, recycles buffer mainly for low 21582 * TCP KPI debugging. 21583 */ 21584 HTT_RXDATA_ERR_OOR = 5, 21585 21586 /* ERR_2K_JUMP: 21587 * FW full reorder layer maps this error to <enum 5 regular_frame_2k_jump>. 21588 * Host maintains error stats, recycles buffer mainly for low 21589 * TCP KPI debugging. 21590 */ 21591 HTT_RXDATA_ERR_2K_JUMP = 6, 21592 21593 /* ERR_ZERO_LEN_MSDU: 21594 * FW sets this error flag for a 0 length MSDU. 21595 * Host maintains error stats, recycles buffer. 21596 */ 21597 HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, 21598 21599 /* ERR_INVALID_PEER: 21600 * FW sets this error flag when MSDU is recived from invalid PEER 21601 * HOST decides to send DEAUTH or not, recyles buffer. 21602 */ 21603 HTT_RXDATA_ERR_INVALID_PEER = 8, 21604 21605 /* add new error codes here */ 21606 21607 HTT_RXDATA_ERR_MAX = 32 21608 } htt_t2h_rx_data_msdu_err_e; 21609 21610 struct htt_t2h_rx_data_ind_t 21611 { 21612 A_UINT32 /* word 0 */ 21613 /* msg_type: 21614 * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. 21615 */ 21616 msg_type: 8, 21617 peer_id: 16, /* This will provide peer data */ 21618 vdev_id: 8; /* This will provide vdev id info */ 21619 A_UINT32 /* word 1 */ 21620 /* msdu_cnt: 21621 * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. 21622 */ 21623 msdu_cnt: 8, 21624 frag: 1, /* this bit will be set for 802.11 frag MPDU */ 21625 rsvd0: 23; 21626 /* NOTE: 21627 * To preserve backwards compatibility, 21628 * no new fields can be added in this struct. 21629 */ 21630 }; 21631 21632 struct htt_t2h_rx_data_msdu_info 21633 { 21634 A_UINT32 /* word 0 */ 21635 buffer_addr_low : 32; 21636 A_UINT32 /* word 1 */ 21637 buffer_addr_high : 8, 21638 sw_buffer_cookie : 21, 21639 /* fw_offloads_inspected: 21640 * When reo_destination_indication is 6 in reo_entrance_ring 21641 * of the RXDMA2REO MPDU upload, all the MSDUs that are part 21642 * of the MPDU are inspected by FW offloads layer, subsequently 21643 * the MSDUs are qualified to be host interested. 21644 * In such case the fw_offloads_inspected is set to 1, else 0. 21645 * This will assist host to not consider such MSDUs for FISA 21646 * flow addition. 21647 */ 21648 fw_offloads_inspected : 1, 21649 rsvd1 : 2; 21650 A_UINT32 /* word 2 */ 21651 mpdu_retry_bit : 1, /* used for stats maintenance */ 21652 raw_mpdu_frame : 1, /* used for pkt drop and processing */ 21653 first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 21654 last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 21655 msdu_continuation : 1, /* used for MSDU scatter/gather support */ 21656 sa_is_valid : 1, /* used for HW issue check in 21657 * is_sa_da_idx_valid() */ 21658 da_is_valid : 1, /* used for HW issue check and 21659 * intra-BSS forwarding */ 21660 da_is_mcbc : 1, 21661 tid_info : 8, /* used for stats maintenance */ 21662 msdu_length : 14, 21663 is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU 21664 * provided by fw after WoW exit */ 21665 rsvd2 : 1; 21666 A_UINT32 /* word 3 */ 21667 error_valid : 1, /* Set if the MSDU has any error */ 21668 error_info : 5, /* If error_valid is TRUE, then refer to 21669 * "htt_t2h_rx_data_msdu_err_e" for 21670 * checking error reason. */ 21671 rsvd3 : 26; 21672 /* NOTE: 21673 * To preserve backwards compatibility, 21674 * no new fields can be added in this struct. 21675 */ 21676 }; 21677 21678 /* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words 21679 * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead 21680 * for every Rx DATA IND sent by FW to host. 21681 */ 21682 #define HTT_RX_DATA_IND_HDR_SIZE (2*4) 21683 /* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words 21684 * This is the size of each MSDU detail that will be piggybacked with the 21685 * RX IND header. 21686 */ 21687 #define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) 21688 21689 /* member definitions of htt_t2h_rx_data_ind_t */ 21690 21691 #define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 21692 #define HTT_RX_DATA_IND_PEER_ID_S 8 21693 21694 #define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ 21695 do { \ 21696 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ 21697 (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ 21698 } while (0) 21699 #define HTT_RX_DATA_IND_PEER_ID_GET(word) \ 21700 (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) 21701 21702 #define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 21703 #define HTT_RX_DATA_IND_VDEV_ID_S 24 21704 21705 #define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ 21706 do { \ 21707 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ 21708 (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ 21709 } while (0) 21710 #define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ 21711 (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) 21712 21713 #define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff 21714 #define HTT_RX_DATA_IND_MSDU_CNT_S 0 21715 21716 #define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ 21717 do { \ 21718 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ 21719 (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ 21720 } while (0) 21721 #define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ 21722 (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) 21723 21724 #define HTT_RX_DATA_IND_FRAG_M 0x00000100 21725 #define HTT_RX_DATA_IND_FRAG_S 8 21726 21727 #define HTT_RX_DATA_IND_FRAG_SET(word, value) \ 21728 do { \ 21729 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ 21730 (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ 21731 } while (0) 21732 #define HTT_RX_DATA_IND_FRAG_GET(word) \ 21733 (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) 21734 21735 /* member definitions of htt_t2h_rx_data_msdu_info */ 21736 21737 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF 21738 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 21739 21740 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF 21741 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 21742 21743 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ 21744 do { \ 21745 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ 21746 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ 21747 } while (0) 21748 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ 21749 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) 21750 21751 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ 21752 do { \ 21753 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ 21754 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ 21755 } while (0) 21756 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ 21757 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) 21758 21759 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 21760 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 21761 21762 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 21763 do { \ 21764 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ 21765 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ 21766 } while (0) 21767 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ 21768 (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) 21769 21770 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000 21771 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29 21772 21773 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \ 21774 do { \ 21775 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \ 21776 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \ 21777 } while (0) 21778 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \ 21779 (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S) 21780 21781 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 21782 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 21783 21784 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ 21785 do { \ 21786 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ 21787 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ 21788 } while (0) 21789 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ 21790 (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) 21791 21792 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 21793 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 21794 21795 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ 21796 do { \ 21797 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ 21798 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ 21799 } while (0) 21800 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ 21801 (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) 21802 21803 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 21804 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 21805 21806 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ 21807 do { \ 21808 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ 21809 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ 21810 } while (0) 21811 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ 21812 (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) 21813 21814 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 21815 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 21816 21817 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ 21818 do { \ 21819 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ 21820 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ 21821 } while (0) 21822 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ 21823 (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) 21824 21825 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 21826 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 21827 21828 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ 21829 do { \ 21830 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ 21831 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ 21832 } while (0) 21833 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ 21834 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) 21835 21836 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 21837 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 21838 21839 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ 21840 do { \ 21841 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ 21842 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ 21843 } while (0) 21844 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ 21845 (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) 21846 21847 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 21848 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 21849 21850 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ 21851 do { \ 21852 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ 21853 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ 21854 } while (0) 21855 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ 21856 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) 21857 21858 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 21859 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 21860 21861 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ 21862 do { \ 21863 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ 21864 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ 21865 } while (0) 21866 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ 21867 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) 21868 21869 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 21870 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 21871 21872 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ 21873 do { \ 21874 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ 21875 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ 21876 } while (0) 21877 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ 21878 (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) 21879 21880 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 21881 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 21882 21883 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ 21884 do { \ 21885 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ 21886 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ 21887 } while (0) 21888 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ 21889 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) 21890 21891 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 21892 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 21893 21894 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ 21895 do { \ 21896 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ 21897 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ 21898 } while (0) 21899 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ 21900 (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) 21901 21902 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 21903 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 21904 21905 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ 21906 do { \ 21907 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ 21908 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ 21909 } while (0) 21910 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ 21911 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) 21912 21913 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E 21914 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 21915 21916 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ 21917 do { \ 21918 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ 21919 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ 21920 } while (0) 21921 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ 21922 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) 21923 21924 21925 /** 21926 * @brief target -> Primary peer migration message to host 21927 * 21928 * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 21929 * 21930 * @details 21931 * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target 21932 * to host to flush & set-up the RX rings to new primary peer 21933 * 21934 * The message would appear as follows: 21935 * 21936 * |31 16|15 12|11 8|7 0| 21937 * |-------------------------------+---------+---------+--------------| 21938 * | vdev ID | pdev ID | chip ID | msg type | 21939 * |-------------------------------+---------+---------+--------------| 21940 * | ML peer ID | SW peer ID | 21941 * |-------------------------------+----------------------------------| 21942 * 21943 * The message is interpreted as follows: 21944 * dword0 - b'0:7 - msg_type: This will be set to 0x37 21945 * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) 21946 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 21947 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 21948 * as primary 21949 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 21950 * as primary 21951 * 21952 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 21953 * chosen as primary 21954 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 21955 * primary peer belongs. 21956 */ 21957 typedef struct { 21958 A_UINT32 msg_type: 8, /* bits 7:0 */ 21959 chip_id: 4, /* bits 11:8 */ 21960 pdev_id: 4, /* bits 15:12 */ 21961 vdev_id: 16; /* bits 31:16 */ 21962 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 21963 ml_peer_id: 16; /* bits 31:16 */ 21964 } htt_t2h_primary_link_peer_migrate_ind_t; 21965 21966 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 21967 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 21968 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 21969 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 21970 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 21971 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 21972 do { \ 21973 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 21974 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 21975 } while (0) 21976 21977 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 21978 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 21979 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 21980 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 21981 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 21982 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 21983 do { \ 21984 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 21985 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 21986 } while (0) 21987 21988 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 21989 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 21990 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 21991 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 21992 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 21993 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 21994 do { \ 21995 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 21996 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 21997 } while (0) 21998 21999 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 22000 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 22001 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 22002 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 22003 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 22004 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 22005 do { \ 22006 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 22007 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 22008 } while (0) 22009 22010 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 22011 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 22012 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 22013 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 22014 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 22015 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 22016 do { \ 22017 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 22018 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 22019 } while (0) 22020 22021 /** 22022 * @brief target -> host rx peer AST override message defenition 22023 * 22024 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND 22025 * 22026 * @details 22027 * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above 22028 * where in the dummy ast index is provided to the host. 22029 * This new message below is sent to the host at run time from the TX_DE 22030 * exception path when a SAWF flow is detected for a peer. 22031 * This is sent up once per SAWF peer. 22032 * This layout assumes the target operates as little-endian. 22033 * 22034 * |31 24|23 16|15 8|7 0| 22035 * |--------------------------------------+-----------------+-----------------| 22036 * | SW peer ID | vdev ID | msg type | 22037 * |-----------------+--------------------+-----------------+-----------------| 22038 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 22039 * |-----------------+--------------------+-----------------+-----------------| 22040 * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | 22041 * |--------------------------------------+-----------------+-----------------| 22042 * | reserved | dummy AST Index #2 | 22043 * |--------------------------------------+-----------------------------------| 22044 * 22045 * The following field definitions describe the format of the peer ast override 22046 * index messages sent from the target to the host. 22047 * - MSG_TYPE 22048 * Bits 7:0 22049 * Purpose: identifies this as a peer map v3 message 22050 * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) 22051 * - VDEV_ID 22052 * Bits 15:8 22053 * Purpose: Indicates which virtual device the peer is associated with. 22054 * - SW_PEER_ID 22055 * Bits 31:16 22056 * Purpose: The peer ID (index) that WAL has allocated for this peer. 22057 * - MAC_ADDR_L32 22058 * Bits 31:0 22059 * Purpose: Identifies which peer node the peer ID is for. 22060 * Value: lower 4 bytes of peer node's MAC address 22061 * - MAC_ADDR_U16 22062 * Bits 15:0 22063 * Purpose: Identifies which peer node the peer ID is for. 22064 * Value: upper 2 bytes of peer node's MAC address 22065 * - AST_INDEX1 22066 * Bits 31:16 22067 * Purpose: The 1st extra AST index used to identify user defined MSDUQ 22068 * - AST_INDEX2 22069 * Bits 15:0 22070 * Purpose: The 2nd extra AST index used to identify user defined MSDUQ 22071 */ 22072 22073 /* dword 0 */ 22074 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 22075 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 22076 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 22077 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 22078 /* dword 1 */ 22079 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff 22080 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 22081 /* dword 2 */ 22082 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff 22083 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 22084 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 22085 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 22086 /* dword 3 */ 22087 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff 22088 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 22089 22090 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ 22091 do { \ 22092 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ 22093 (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ 22094 } while (0) 22095 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ 22096 (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) 22097 22098 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ 22099 do { \ 22100 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ 22101 (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ 22102 } while (0) 22103 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ 22104 (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) 22105 22106 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ 22107 do { \ 22108 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ 22109 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ 22110 } while (0) 22111 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ 22112 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) 22113 22114 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ 22115 do { \ 22116 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ 22117 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ 22118 } while (0) 22119 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ 22120 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) 22121 22122 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ 22123 do { \ 22124 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ 22125 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ 22126 } while (0) 22127 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ 22128 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) 22129 22130 22131 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ 22132 do { \ 22133 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ 22134 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ 22135 } while (0) 22136 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ 22137 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) 22138 22139 22140 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ 22141 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ 22142 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ 22143 22144 #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 22145 22146 22147 /** 22148 * @brief target -> periodic report of tx latency to host 22149 * 22150 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND 22151 * 22152 * @details 22153 * The message starts with a message header followed by one or more 22154 * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev. 22155 * After each upload, these tx latency stats will be reset. 22156 * 22157 * |31 24|23 16|15 14|13 10|9 8|7 0| 22158 * +-------------------------+-----+-----+---+----------| 22159 * hdr | |pyld elem sz| | GR | P | msg type | 22160 *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22161 * pyld | peer ID | 22162 * |----------------------------------------------------| 22163 * | peer_tx_latency[0] | 22164 * |----------------------------------------------------| 22165 * 1st | peer_tx_latency[1] | 22166 * peer |----------------------------------------------------| 22167 * | peer_tx_latency[2] | 22168 * |----------------------------------------------------| 22169 * | peer_tx_latency[3] | 22170 * |----------------------------------------------------| 22171 * | avg latency | 22172 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22173 * | peer ID | 22174 * |----------------------------------------------------| 22175 * | peer_tx_latency[0] | 22176 * |----------------------------------------------------| 22177 * 2nd | peer_tx_latency[1] | 22178 * peer |----------------------------------------------------| 22179 * | peer_tx_latency[2] | 22180 * |----------------------------------------------------| 22181 * | peer_tx_latency[3] | 22182 * |----------------------------------------------------| 22183 * | avg latency | 22184 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22185 * Where: 22186 * P = pdev ID 22187 * GR = granularity 22188 * 22189 * @details 22190 * htt_t2h_tx_latency_stats_periodic_hdr_t: 22191 * - msg_type 22192 * Bits 7:0 22193 * Purpose: identifies this as a tx latency report message 22194 * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND) 22195 * - pdev_id 22196 * Bits 9:8 22197 * Purpose: Indicates which pdev this message is associated with. 22198 * - granularity 22199 * Bits 13:10 22200 * Purpose: specifies the granulairty of each tx latency bucket in MS. 22201 * There are 4 buckets in total. E.g. if granularity is set to 5 ms, 22202 * then the ranges for the 4 latency histogram buckets will be 22203 * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively. 22204 * - payload_elem_size 22205 * Bits 23:16 22206 * Purpose: specifies the size of each element within the msg's payload 22207 * In other words, this field specified the value of 22208 * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's 22209 * revision of the htt_t2h_peer_tx_latency_stats definition. 22210 * If the payload_elem_size reported in the message exceeds the 22211 * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22212 * revision of the htt_t2h_peer_tx_latency_stats definition, 22213 * the host shall ignore the excess data. 22214 * Conversely, if the payload_elem_size reported in the message is 22215 * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22216 * revision of the htt_t2h_peer_tx_latency_stats definition, 22217 * the host shall use 0x0 values for the portion of the data not 22218 * provided by the target. 22219 * The host can compare the payload_elem_size to the total size of 22220 * the message minus the size of the message header to determine 22221 * how many peer payload elements are present in the message. 22222 * - sw_peer_id 22223 * Purpose: The peer to which the following stats belong 22224 * - peer_tx_latency 22225 * Purpose: tx latency histogram for this peer, with 4 buckets whose 22226 * size (in milliseconds) is specified by the granularity field 22227 * - avg_latency 22228 * Purpose: average tx latency (in ms) for this peer in this report interval 22229 */ 22230 typedef struct { 22231 A_UINT32 msg_type: 8, 22232 pdev_id: 2, 22233 granularity: 4, 22234 reserved1: 2, 22235 payload_elem_size: 8, 22236 reserved2: 8; 22237 } htt_t2h_tx_latency_stats_periodic_hdr_t; 22238 22239 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \ 22240 (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t)) 22241 #define HTT_PEER_TX_LATENCY_REPORT_BINS 4 22242 22243 typedef struct _htt_tx_latency_stats { 22244 A_UINT32 peer_id; 22245 A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS]; 22246 A_UINT32 avg_latency; 22247 } htt_t2h_peer_tx_latency_stats; 22248 22249 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300 22250 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8 22251 22252 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 22253 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S) 22254 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 22255 do { \ 22256 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \ 22257 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \ 22258 } while (0) 22259 22260 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00 22261 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10 22262 22263 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \ 22264 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S) 22265 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \ 22266 do { \ 22267 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \ 22268 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ 22269 } while (0) 22270 22271 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000 22272 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16 22273 22274 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ 22275 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) 22276 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \ 22277 do { \ 22278 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \ 22279 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \ 22280 } while (0) 22281 22282 22283 22284 #endif 22285