1 /* 2 * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 6 * 7 * 8 * Permission to use, copy, modify, and/or distribute this software for 9 * any purpose with or without fee is hereby granted, provided that the 10 * above copyright notice and this permission notice appear in all 11 * copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 14 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 15 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 16 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 17 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 18 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * This file was originally distributed by Qualcomm Atheros, Inc. 25 * under proprietary terms before Copyright ownership was assigned 26 * to the Linux Foundation. 27 */ 28 29 /** 30 * @file htt.h 31 * 32 * @details the public header file of HTT layer 33 */ 34 35 #ifndef _HTT_H_ 36 #define _HTT_H_ 37 38 #include <htt_deps.h> 39 #include <htt_common.h> 40 41 /* 42 * Unless explicitly specified to use 64 bits to represent physical addresses 43 * (or more precisely, bus addresses), default to 32 bits. 44 */ 45 #ifndef HTT_PADDR64 46 #define HTT_PADDR64 0 47 #endif 48 49 #ifndef offsetof 50 #define offsetof(type, field) ((unsigned int)(&((type *)0)->field)) 51 #endif 52 53 /* 54 * HTT version history: 55 * 1.0 initial numbered version 56 * 1.1 modifications to STATS messages. 57 * These modifications are not backwards compatible, but since the 58 * STATS messages themselves are non-essential (they are for debugging), 59 * the 1.1 version of the HTT message library as a whole is compatible 60 * with the 1.0 version. 61 * 1.2 reset mask IE added to STATS_REQ message 62 * 1.3 stat config IE added to STATS_REQ message 63 *---- 64 * 2.0 FW rx PPDU desc added to RX_IND message 65 * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0 66 *---- 67 * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message 68 * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message 69 * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG, 70 * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages 71 * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message 72 * 3.4 Added tx_compl_req flag in HTT tx descriptor 73 * 3.5 Added flush and fail stats in rx_reorder stats structure 74 * 3.6 Added frag flag in HTT RX INORDER PADDR IND header 75 * 3.7 Made changes to support EOS Mac_core 3.0 76 * 3.8 Added txq_group information element definition; 77 * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message 78 * 3.9 Added HTT_T2H CHAN_CHANGE message; 79 * Allow buffer addresses in bus-address format to be stored as 80 * either 32 bits or 64 bits. 81 * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF 82 * messages to specify which HTT options to use. 83 * Initial TLV options cover: 84 * - whether to use 32 or 64 bits to represent LL bus addresses 85 * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems 86 * - how many tx queue groups to use 87 * 3.11 Expand rx debug stats: 88 * - Expand the rx_reorder_stats struct with stats about successful and 89 * failed rx buffer allcoations. 90 * - Add a new rx_remote_buffer_mgmt_stats struct with stats about 91 * the supply, allocation, use, and recycling of rx buffers for the 92 * "remote ring" of rx buffers in host member in LL systems. 93 * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats. 94 * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype 95 * 3.13 Add constants + macros to support 64-bit address format for the 96 * tx fragments descriptor, the rx ring buffer, and the rx ring 97 * index shadow register. 98 * 3.14 Add a method for the host to provide detailed per-frame tx specs: 99 * - Add htt_tx_msdu_desc_ext_t struct def. 100 * - Add TLV to specify whether the target supports the HTT tx MSDU 101 * extension descriptor. 102 * - Change a reserved bit in the HTT tx MSDU descriptor to an 103 * "extension" bit, to specify whether a HTT tx MSDU extension 104 * descriptor is present. 105 * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg. 106 * (This allows the host to obtain key information about the MSDU 107 * from a memory location already in the cache, rather than taking a 108 * cache miss for each MSDU by reading the HW rx descs.) 109 * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate 110 * whether a copy-engine classification result is appended to TX_FRM. 111 * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG 112 * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of 113 * tx frames in the target after the peer has already been deleted. 114 * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2 115 * 3.20 Expand rx_reorder_stats. 116 * 3.21 Add optional rx channel spec to HL RX_IND. 117 * 3.22 Expand rx_reorder_stats 118 * (distinguish duplicates within vs. outside block ack window) 119 * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate. 120 * The justified rate is calculated by two steps. The first is to multiply 121 * user-rate by (1 - PER) and the other is to smooth the step 1's result 122 * by a low pass filter. 123 * This change allows HL download scheduling to consider the WLAN rate 124 * that will be used for transmitting the downloaded frames. 125 * 3.24 Expand rx_reorder_stats 126 * (add counter for decrypt / MIC errors) 127 * 3.25 Expand rx_reorder_stats 128 * (add counter of frames received into both local + remote rings) 129 * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames 130 * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats) 131 * 3.27 Add a new interface for flow-control. The following t2h messages have 132 * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and 133 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 134 * 3.28 Add a new interface for ring interface change. The following two h2t 135 * and one t2h messages have been included: 136 * HTT_H2T_MSG_TYPE_SRING_SETUP, HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 137 * and HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 138 * 3.29 Add definitions of htt_tx_msdu_desc_ext2_t descriptor and other 139 * information elements passed from the host to a Lithium target, 140 * Add definitions of the HTT_H2T ADD_WDS_ENTRY and DELETE_WDS_ENTRY 141 * messages and the HTT_T2H MAP_FLOW_INFO message (for use with Lithium 142 * targets). 143 * 3.30 Add pktlog flag inside HTT_T2H RX_IN_ORD_PADDR_IND message 144 * 3.31 Add HTT_H2T_MSG_TYPE_RFS_CONFIG 145 * 3.32 Add HTT_WDI_IPA_OPCODE_SHARING_STATS, HTT_WDI_IPA_OPCODE_SET_QUOTA and 146 * HTT_WDI_IPA_OPCODE_IND_QUOTA for getting quota and reporting WiFi 147 * sharing stats 148 * 3.33 Add HTT_TX_COMPL_IND_STAT_DROP and HTT_TX_COMPL_IND_STAT_HOST_INSPECT 149 * 3.34 Add HW_PEER_ID field to PEER_MAP 150 * 3.35 Revise bitfield defs of HTT_SRING_SETUP message 151 * (changes are not backwards compatible, but HTT_SRING_SETUP message is 152 * not yet in use) 153 * 3.36 Add HTT_H2T_MSG_TYPE_EXT_STATS_REQ and HTT_T2H_MSG_TYPE_EXT_STATS_CONF 154 * 3.37 Add HTT_PEER_TYPE and htt_mac_addr defs 155 * 3.38 Add holes_no_filled field to rx_reorder_stats 156 * 3.39 Add host_inspected flag to htt_tx_tcl_vdev_metadata 157 * 3.40 Add optional timestamps in the HTT tx completion 158 * 3.41 Add optional tx power spec in the HTT tx completion (for DSRC use) 159 * 3.42 Add PPDU_STATS_CFG + PPDU_STATS_IND 160 * 3.43 Add HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR defs 161 * 3.44 Add htt_tx_wbm_completion_v2 162 * 3.45 Add host_tx_desc_pool flag in htt_tx_msdu_desc_ext2_t 163 * 3.46 Add MAC ID and payload size fields to HTT_T2H_MSG_TYPE_PKTLOG header 164 * 3.47 Add HTT_T2H PEER_MAP_V2 and PEER_UNMAP_V2 165 * 3.48 Add pdev ID field to HTT_T2H_MSG_TYPE_PPDU_STATS_IND and 166 * HTT_T2H_MSG_TYPE_PKTLOG 167 * 3.49 Add HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND def 168 * 3.50 Add learning_frame flag to htt_tx_msdu_desc_ext2_t 169 * 3.51 Add SW peer ID and TID num to HTT TX WBM COMPLETION 170 * 3.52 Add HTT_T2H FLOW_POOL_RESIZE msg def 171 * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def 172 * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status 173 * 3.55 Add initiator / responder flags to RX_DELBA indication 174 * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs 175 * 3.57 Add support for in-band data within HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 176 * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg 177 * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def 178 * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def 179 * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg 180 * 3.62 Add antenna mask to reserved space in htt_rx_ppdu_desc_t 181 * 3.63 Add HTT_HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND def 182 * 3.64 Add struct htt_tx_compl_ind_append_tx_tsf64 and add tx_tsf64 183 * array to the end of HTT_T2H TX_COMPL_IND msg 184 * 3.65 Add fields in htt_tx_msdu_desc_ext2_t to allow the host to provide 185 * a "cookie" to identify a MSDU, and to specify to not apply aggregation 186 * for a MSDU. 187 * 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg. 188 * Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg. 189 * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg. 190 * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP 191 * 3.69 Add htt_ul_ofdma_user_info_v0 defs 192 * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg 193 * 3.71 Add rx offload engine / flow search engine htt setup message defs for 194 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 195 * 3.72 Add tx_retry_cnt fields to htt_tx_offload_deliver_ind_hdr_t and 196 * htt_tx_data_hdr_information 197 * 3.73 Add channel pre-calibration data upload and download messages defs for 198 * HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA 199 * 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg. 200 * 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG. 201 * 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg. 202 * 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg. 203 * 3.78 Add htt_ppdu_id def. 204 * 3.79 Add HTT_NUM_AC_WMM def. 205 * 3.80 Add add WDS_FREE_COUNT bitfield in T2H PEER_UNMAP_V2 msg. 206 * 3.81 Add ppdu_start_tsf field in HTT_TX_WBM_COMPLETION_V2. 207 * 3.82 Add WIN_SIZE field to HTT_T2H_MSG_TYPE_RX_DELBA msg. 208 * 3.83 Shrink seq_idx field in HTT PPDU ID from 3 bits to 2. 209 * 3.84 Add fisa_control_bits_v2 def. 210 * 3.85 Add HTT_RX_PEER_META_DATA defs. 211 * 3.86 Add HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND def. 212 * 3.87 Add on-chip AST index field to PEER_MAP_V2 msg. 213 * 3.88 Add HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE def. 214 * 3.89 Add MSDU queue enumerations. 215 * 3.90 Add HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND def. 216 * 3.91 Add HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP, _UNMAP defs. 217 * 3.92 Add HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG def. 218 * 3.93 Add HTT_T2H_MSG_TYPE_PEER_MAP_V3 def. 219 * 3.94 Add HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 220 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND defs. 221 * 3.95 Add HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 222 * 3.96 Modify HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def. 223 * 3.97 Add tx MSDU drop byte count fields in vdev_txrx_stats_hw_stats TLV. 224 * 3.98 Add htt_tx_tcl_metadata_v2 def. 225 * 3.99 Add HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ, _UNMAP_REQ, _MAP_REPORT_REQ and 226 * HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF defs. 227 * 3.100 Add htt_tx_wbm_completion_v3 def. 228 * 3.101 Add HTT_UL_OFDMA_USER_INFO_V1_BITMAP defs. 229 * 3.102 Add HTT_H2T_MSG_TYPE_MSI_SETUP def. 230 * 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs. 231 * 3.104 Add mgmt/ctrl/data specs in rx ring cfg. 232 * 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs. 233 * 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def. 234 * 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t. 235 * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def. 236 * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs. 237 * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t. 238 * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg. 239 * 3.112 Add logical_link_id field in rx_peer_metadata_v1. 240 * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t 241 * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. 242 * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and 243 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. 244 * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. 245 * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. 246 * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. 247 * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. 248 * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. 249 * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. 250 * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg 251 * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. 252 * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. 253 * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. 254 * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. 255 * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. 256 * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND 257 * msg defs 258 */ 259 #define HTT_CURRENT_VERSION_MAJOR 3 260 #define HTT_CURRENT_VERSION_MINOR 128 261 262 #define HTT_NUM_TX_FRAG_DESC 1024 263 264 #define HTT_WIFI_IP_VERSION(x,y) ((x) == (y)) 265 266 #define HTT_CHECK_SET_VAL(field, val) \ 267 A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) 268 269 /* macros to assist in sign-extending fields from HTT messages */ 270 #define HTT_SIGN_BIT_MASK(field) \ 271 ((field ## _M + (1 << field ## _S)) >> 1) 272 #define HTT_SIGN_BIT(_val, field) \ 273 (_val & HTT_SIGN_BIT_MASK(field)) 274 #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ 275 (HTT_SIGN_BIT(_val, field) >> field ## _S) 276 #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ 277 (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) 278 #define HTT_SIGN_BIT_EXTENSION(_val, field) \ 279 (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ 280 HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) 281 #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ 282 (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) 283 284 285 /* 286 * TEMPORARY: 287 * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for 288 * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code 289 * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been 290 * updated. 291 */ 292 #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX 293 294 /* 295 * TEMPORARY: 296 * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for 297 * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code 298 * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been 299 * updated. 300 */ 301 #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND 302 303 /** 304 * htt_dbg_stats_type - 305 * bit positions for each stats type within a stats type bitmask 306 * The bitmask contains 24 bits. 307 */ 308 enum htt_dbg_stats_type { 309 HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ 310 HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ 311 HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ 312 HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ 313 HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ 314 HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ 315 HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ 316 HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ 317 HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ 318 HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ 319 HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ 320 HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ 321 HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ 322 HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ 323 HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ 324 HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ 325 /* bits 16-23 currently reserved */ 326 327 /* keep this last */ 328 HTT_DBG_NUM_STATS 329 }; 330 331 /*=== HTT option selection TLVs === 332 * Certain HTT messages have alternatives or options. 333 * For such cases, the host and target need to agree on which option to use. 334 * Option specification TLVs can be appended to the VERSION_REQ and 335 * VERSION_CONF messages to select options other than the default. 336 * These TLVs are entirely optional - if they are not provided, there is a 337 * well-defined default for each option. If they are provided, they can be 338 * provided in any order. Each TLV can be present or absent independent of 339 * the presence / absence of other TLVs. 340 * 341 * The HTT option selection TLVs use the following format: 342 * |31 16|15 8|7 0| 343 * |---------------------------------+----------------+----------------| 344 * | value (payload) | length | tag | 345 * |-------------------------------------------------------------------| 346 * The value portion need not be only 2 bytes; it can be extended by any 347 * integer number of 4-byte units. The total length of the TLV, including 348 * the tag and length fields, must be a multiple of 4 bytes. The length 349 * field specifies the total TLV size in 4-byte units. Thus, the typical 350 * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value 351 * field, would store 0x1 in its length field, to show that the TLV occupies 352 * a single 4-byte unit. 353 */ 354 355 /*--- TLV header format - applies to all HTT option TLVs ---*/ 356 357 enum HTT_OPTION_TLV_TAGS { 358 HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, 359 HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, 360 HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, 361 HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, 362 HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, 363 /* TCL_METADATA_VER: added to support V2 and higher of the TCL Data Cmd */ 364 HTT_OPTION_TLV_TAG_TCL_METADATA_VER = 0x5, 365 }; 366 367 #define HTT_TCL_METADATA_VER_SZ 4 368 369 PREPACK struct htt_option_tlv_header_t { 370 A_UINT8 tag; 371 A_UINT8 length; 372 } POSTPACK; 373 374 #define HTT_OPTION_TLV_TAG_M 0x000000ff 375 #define HTT_OPTION_TLV_TAG_S 0 376 #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00 377 #define HTT_OPTION_TLV_LENGTH_S 8 378 /* 379 * value0 - 16 bit value field stored in word0 380 * The TLV's value field may be longer than 2 bytes, in which case 381 * the remainder of the value is stored in word1, word2, etc. 382 */ 383 #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 384 #define HTT_OPTION_TLV_VALUE0_S 16 385 386 #define HTT_OPTION_TLV_TAG_SET(word, tag) \ 387 do { \ 388 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ 389 (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ 390 } while (0) 391 #define HTT_OPTION_TLV_TAG_GET(word) \ 392 (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) 393 394 #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ 395 do { \ 396 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ 397 (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ 398 } while (0) 399 #define HTT_OPTION_TLV_LENGTH_GET(word) \ 400 (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) 401 402 #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ 403 do { \ 404 HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ 405 (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ 406 } while (0) 407 #define HTT_OPTION_TLV_VALUE0_GET(word) \ 408 (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) 409 410 /*--- format of specific HTT option TLVs ---*/ 411 412 /* 413 * HTT option TLV for specifying LL bus address size 414 * Some chips require bus addresses used by the target to access buffers 415 * within the host's memory to be 32 bits; others require bus addresses 416 * used by the target to access buffers within the host's memory to be 417 * 64 bits. 418 * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as 419 * a suffix to the VERSION_CONF message to specify which bus address format 420 * the target requires. 421 * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should 422 * default to providing bus addresses to the target in 32-bit format. 423 */ 424 enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { 425 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, 426 HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, 427 }; 428 PREPACK struct htt_option_tlv_ll_bus_addr_size_t { 429 struct htt_option_tlv_header_t hdr; 430 A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ 431 } POSTPACK; 432 433 /* 434 * HTT option TLV for specifying whether HL systems should indicate 435 * over-the-air tx completion for individual frames, or should instead 436 * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly 437 * requests an OTA tx completion for a particular tx frame. 438 * This option does not apply to LL systems, where the TX_COMPL_IND 439 * is mandatory. 440 * This option is primarily intended for HL systems in which the tx frame 441 * downloads over the host --> target bus are as slow as or slower than 442 * the transmissions over the WLAN PHY. For cases where the bus is faster 443 * than the WLAN PHY, the target will transmit relatively large A-MPDUs, 444 * and consequently will send one TX_COMPL_IND message that covers several 445 * tx frames. For cases where the WLAN PHY is faster than the bus, 446 * the target will end up transmitting very short A-MPDUs, and consequently 447 * sending many TX_COMPL_IND messages, which each cover a very small number 448 * of tx frames. 449 * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as 450 * a suffix to the VERSION_REQ message to request whether the host desires to 451 * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then 452 * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the 453 * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used 454 * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the 455 * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of 456 * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV 457 * back to the host confirming use of TX_CREDIT_UPDATE_IND. 458 * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or 459 * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that 460 * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the 461 * TLV. 462 */ 463 enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { 464 HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, 465 HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, 466 }; 467 PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { 468 struct htt_option_tlv_header_t hdr; 469 A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */ 470 } POSTPACK; 471 472 /* 473 * HTT option TLV for specifying how many tx queue groups the target 474 * may establish. 475 * This TLV specifies the maximum value the target may send in the 476 * txq_group_id field of any TXQ_GROUP information elements sent by 477 * the target to the host. This allows the host to pre-allocate an 478 * appropriate number of tx queue group structs. 479 * 480 * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as 481 * a suffix to the VERSION_REQ message to specify whether the host supports 482 * tx queue groups at all, and if so if there is any limit on the number of 483 * tx queue groups that the host supports. 484 * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as 485 * a suffix to the VERSION_CONF message. If the host has specified in the 486 * VER_REQ message a limit on the number of tx queue groups the host can 487 * support, the target shall limit its specification of the maximum tx groups 488 * to be no larger than this host-specified limit. 489 * 490 * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host 491 * shall preallocate 4 tx queue group structs, and the target shall not 492 * specify a txq_group_id larger than 3. 493 */ 494 enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { 495 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, 496 /* 497 * values 1 through N specify the max number of tx queue groups 498 * the sender supports 499 */ 500 HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, 501 }; 502 /* TEMPORARY backwards-compatibility alias for a typo fix - 503 * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected 504 * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided 505 * to support the old name (with the typo) until all references to the 506 * old name are replaced with the new name. 507 */ 508 #define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t 509 PREPACK struct htt_option_tlv_max_tx_queue_groups_t { 510 struct htt_option_tlv_header_t hdr; 511 A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ 512 } POSTPACK; 513 514 /* 515 * HTT option TLV for specifying whether the target supports an extended 516 * version of the HTT tx descriptor. If the target provides this TLV 517 * and specifies in the TLV that the target supports an extended version 518 * of the HTT tx descriptor, the target must check the "extension" bit in 519 * the HTT tx descriptor, and if the extension bit is set, to expect a 520 * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU 521 * descriptor. Furthermore, the target must provide room for the HTT 522 * tx MSDU extension descriptor in the target's TX_FRM buffer. 523 * This option is intended for systems where the host needs to explicitly 524 * control the transmission parameters such as tx power for individual 525 * tx frames. 526 * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host 527 * as a suffix to the VERSION_CONF message to explicitly specify whether 528 * the target supports the HTT tx MSDU extension descriptor. 529 * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted 530 * by the host as lack of target support for the HTT tx MSDU extension 531 * descriptor; the host shall provide HTT tx MSDU extension descriptors in 532 * the HTT_H2T TX_FRM messages only if the target indicates it supports 533 * the HTT tx MSDU extension descriptor. 534 * The host is not required to provide the HTT tx MSDU extension descriptor 535 * just because the target supports it; the target must check the 536 * "extension" bit in the HTT tx MSDU descriptor to determine whether an 537 * extension descriptor is present. 538 */ 539 enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { 540 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, 541 HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, 542 }; 543 PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { 544 struct htt_option_tlv_header_t hdr; 545 A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */ 546 } POSTPACK; 547 548 /* 549 * For the tcl data command V2 and higher support added a new 550 * version tag HTT_OPTION_TLV_TAG_TCL_METADATA_VER. 551 * This will be used as a TLV in HTT_H2T_MSG_TYPE_VERSION_REQ and 552 * HTT_T2H_MSG_TYPE_VERSION_CONF. 553 * HTT option TLV for specifying which version of the TCL metadata struct 554 * should be used: 555 * V1 -> use htt_tx_tcl_metadata struct 556 * V2 -> use htt_tx_tcl_metadata_v2 struct 557 * Old FW will only support V1. 558 * New FW will support V2. New FW will still support V1, at least during 559 * a transition period. 560 * Similarly, old host will only support V1, and new host will support V1 + V2. 561 * 562 * The host can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 563 * HTT_H2T_MSG_TYPE_VERSION_REQ to indicate to the target which version(s) 564 * of TCL metadata the host supports. If the host doesn't provide a 565 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_REQ message, it 566 * is implicitly understood that the host only supports V1. 567 * The target can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the 568 * HTT_T2H_MSG_TYPE_VERSION_CONF to indicate which version of TCL metadata 569 * the host shall use. The target shall only select one of the versions 570 * supported by the host. If the target doesn't provide a 571 * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it 572 * is implicitly understood that the V1 TCL metadata shall be used. 573 * 574 * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 575 * read as version 2.1. We added support for Dynamic AST Index Allocation 576 * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 577 * we will retain older behavior of making sure the AST Index for SAWF 578 * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 579 * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and 580 * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index 581 * in TCLV2 command and do the dynamic AST allocations. 582 */ 583 enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { 584 HTT_OPTION_TLV_TCL_METADATA_V1 = 1, 585 HTT_OPTION_TLV_TCL_METADATA_V2 = 2, 586 /* values 3-20 reserved */ 587 HTT_OPTION_TLV_TCL_METADATA_V21 = 21, 588 }; 589 590 PREPACK struct htt_option_tlv_tcl_metadata_ver_t { 591 struct htt_option_tlv_header_t hdr; 592 A_UINT16 tcl_metadata_ver; /* TCL_METADATA_VER_VALUES enum */ 593 } POSTPACK; 594 595 #define HTT_OPTION_TLV_TCL_METADATA_VER_SET(word, value) \ 596 HTT_OPTION_TLV_VALUE0_SET(word, value) 597 #define HTT_OPTION_TLV_TCL_METADATA_VER_GET(word) \ 598 HTT_OPTION_TLV_VALUE0_GET(word) 599 600 typedef struct { 601 union { 602 /* BIT [11 : 0] :- tag 603 * BIT [23 : 12] :- length 604 * BIT [31 : 24] :- reserved 605 */ 606 A_UINT32 tag__length; 607 /* 608 * The following struct is not endian-portable. 609 * It is suitable for use within the target, which is known to be 610 * little-endian. 611 * The host should use the above endian-portable macros to access 612 * the tag and length bitfields in an endian-neutral manner. 613 */ 614 struct { 615 A_UINT32 tag : 12, /* BIT [11 : 0] */ 616 length : 12, /* BIT [23 : 12] */ 617 reserved : 8; /* BIT [31 : 24] */ 618 }; 619 }; 620 } htt_tlv_hdr_t; 621 622 /** HTT stats TLV tag values */ 623 typedef enum { 624 HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */ 625 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */ 626 HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */ 627 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */ 628 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */ 629 HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv */ 630 HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv */ 631 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */ 632 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v */ 633 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v */ 634 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v */ 635 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */ 636 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */ 637 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */ 638 HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */ 639 HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */ 640 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */ 641 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */ 642 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */ 643 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */ 644 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */ 645 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */ 646 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */ 647 HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */ 648 HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */ 649 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */ 650 HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */ 651 HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv */ 652 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */ 653 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */ 654 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */ 655 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */ 656 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */ 657 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */ 658 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */ 659 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */ 660 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv */ 661 HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv */ 662 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */ 663 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v */ 664 HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */ 665 HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v */ 666 HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv */ 667 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */ 668 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v */ 669 HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */ 670 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */ 671 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */ 672 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */ 673 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */ 674 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */ 675 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */ 676 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */ 677 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */ 678 HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv */ 679 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */ 680 HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */ 681 HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */ 682 HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */ 683 HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */ 684 HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */ 685 HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */ 686 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */ 687 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv */ 688 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */ 689 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */ 690 HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */ 691 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */ 692 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */ 693 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */ 694 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats) */ 695 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats) */ 696 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv */ 697 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv */ 698 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv */ 699 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */ 700 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */ 701 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */ 702 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */ 703 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */ 704 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, /* htt_tx_sounding_stats_tlv */ 705 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, /* htt_tx_pdev_stats_tx_ppdu_stats_tlv_v */ 706 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, /* htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v */ 707 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, /* htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v */ 708 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, /* htt_tx_hwq_txop_used_cnt_hist_tlv_v */ 709 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, /* htt_tx_de_fw2wbm_ring_full_hist_tlv */ 710 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, /* htt_sched_txq_sched_order_su_tlv */ 711 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, /* htt_sched_txq_sched_eligibility_tlv */ 712 HTT_STATS_PDEV_OBSS_PD_TAG = 88, /* htt_pdev_obss_pd_stats_tlv */ 713 HTT_STATS_HW_WAR_TAG = 89, /* htt_hw_war_stats_tlv */ 714 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, /* htt_ring_backpressure_stats_tlv */ 715 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, /* htt_latency_prof_stats_tlv */ 716 HTT_STATS_LATENCY_CTX_TAG = 92, /* htt_latency_prof_ctx_tlv */ 717 HTT_STATS_LATENCY_CNT_TAG = 93, /* htt_latency_prof_cnt_tlv */ 718 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, /* htt_rx_pdev_ul_trigger_stats_tlv */ 719 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, /* htt_rx_pdev_ul_ofdma_user_stats_tlv */ 720 HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG = 96, /* htt_rx_pdev_ul_mimo_user_stats_tlv */ 721 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, /* htt_rx_pdev_ul_mumimo_trig_stats_tlv */ 722 HTT_STATS_RX_FSE_STATS_TAG = 98, /* htt_rx_fse_stats_tlv */ 723 HTT_STATS_PEER_SCHED_STATS_TAG = 99, /* htt_peer_sched_stats_tlv */ 724 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, /* htt_sched_txq_supercycle_triggers_tlv_v */ 725 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, /* htt_peer_ctrl_path_txrx_stats_tlv */ 726 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, /* htt_pdev_ctrl_path_tx_stats_tlv */ 727 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, /* htt_rx_pdev_rate_ext_stats_tlv */ 728 HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, /* htt_tx_pdev_dl_mu_mimo_sch_stats_tlv */ 729 HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, /* htt_tx_pdev_ul_mu_mimo_sch_stats_tlv */ 730 HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, /* htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv */ 731 HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, /* htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv */ 732 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, /* htt_tx_peer_rate_txbf_stats_tlv */ 733 HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, /* htt_stats_error_tlv_v */ 734 HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, /* htt_stats_error_tlv_v */ 735 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, /* htt_tx_selfgen_ac_sched_status_stats_tlv */ 736 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, /* htt_tx_selfgen_ax_sched_status_stats_tlv */ 737 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, /* htt_txbf_ofdma_ndpa_stats_tlv - DEPRECATED */ 738 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, /* htt_txbf_ofdma_ndp_stats_tlv - DEPRECATED */ 739 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, /* htt_txbf_ofdma_brp_stats_tlv - DEPRECATED */ 740 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, /* htt_txbf_ofdma_steer_stats_tlv - DEPRECATED */ 741 HTT_STATS_STA_UL_OFDMA_STATS_TAG = 117, /* htt_sta_ul_ofdma_stats_tlv */ 742 HTT_STATS_VDEV_RTT_RESP_STATS_TAG = 118, /* htt_vdev_rtt_resp_stats_tlv */ 743 HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG = 119, /* htt_pktlog_and_htt_ring_stats_tlv */ 744 HTT_STATS_DLPAGER_STATS_TAG = 120, /* htt_dlpager_stats_tlv */ 745 HTT_STATS_PHY_COUNTERS_TAG = 121, /* htt_phy_counters_tlv */ 746 HTT_STATS_PHY_STATS_TAG = 122, /* htt_phy_stats_tlv */ 747 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, /* htt_phy_reset_counters_tlv */ 748 HTT_STATS_PHY_RESET_STATS_TAG = 124, /* htt_phy_reset_stats_tlv */ 749 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, /* htt_t2h_soc_txrx_stats_common_tlv */ 750 HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, /* htt_t2h_vdev_txrx_stats_hw_stats_tlv */ 751 HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, /* htt_vdev_rtt_init_stats_tlv */ 752 HTT_STATS_PER_RATE_STATS_TAG = 128, /* htt_tx_rate_stats_per_tlv */ 753 HTT_STATS_MU_PPDU_DIST_TAG = 129, /* htt_pdev_mu_ppdu_dist_tlv */ 754 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, /* htt_tx_pdev_mumimo_grp_stats_tlv */ 755 HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG = 131, /* htt_tx_pdev_rate_stats_be_tlv */ 756 HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */ 757 HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv */ 758 HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv */ 759 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */ 760 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv */ 761 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv */ 762 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv */ 763 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv */ 764 HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ 765 HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ 766 HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ 767 HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv */ 768 HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv */ 769 HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */ 770 HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */ 771 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, /* htt_txbf_ofdma_ax_ndpa_stats_tlv */ 772 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, /* htt_txbf_ofdma_ax_ndp_stats_tlv */ 773 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, /* htt_txbf_ofdma_ax_brp_stats_tlv */ 774 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, /* htt_txbf_ofdma_ax_steer_stats_tlv */ 775 HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG = 151, /* htt_txbf_ofdma_be_ndpa_stats_tlv */ 776 HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG = 152, /* htt_txbf_ofdma_be_ndp_stats_tlv */ 777 HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, /* htt_txbf_ofdma_be_brp_stats_tlv */ 778 HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, /* htt_txbf_ofdma_be_steer_stats_tlv */ 779 HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */ 780 HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv */ 781 HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */ 782 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */ 783 HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */ 784 HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */ 785 HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */ 786 HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv */ 787 HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv */ 788 HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */ 789 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv */ 790 HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */ 791 HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */ 792 HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */ 793 HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */ 794 HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */ 795 HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v */ 796 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv */ 797 HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv */ 798 HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ 799 HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v */ 800 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ 801 HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ 802 HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ 803 HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ 804 HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ 805 HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ 806 HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ 807 HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ 808 HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ 809 HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ 810 HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ 811 HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ 812 HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ 813 HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ 814 HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ 815 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ 816 817 818 HTT_STATS_MAX_TAG, 819 } htt_stats_tlv_tag_t; 820 /* retain deprecated enum name as an alias for the current enum name */ 821 typedef htt_stats_tlv_tag_t htt_tlv_tag_t; 822 823 #define HTT_STATS_TLV_TAG_M 0x00000fff 824 #define HTT_STATS_TLV_TAG_S 0 825 #define HTT_STATS_TLV_LENGTH_M 0x00fff000 826 #define HTT_STATS_TLV_LENGTH_S 12 827 828 #define HTT_STATS_TLV_TAG_GET(_var) \ 829 (((_var) & HTT_STATS_TLV_TAG_M) >> \ 830 HTT_STATS_TLV_TAG_S) 831 832 #define HTT_STATS_TLV_TAG_SET(_var, _val) \ 833 do { \ 834 HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \ 835 ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \ 836 } while (0) 837 838 #define HTT_STATS_TLV_LENGTH_GET(_var) \ 839 (((_var) & HTT_STATS_TLV_LENGTH_M) >> \ 840 HTT_STATS_TLV_LENGTH_S) 841 #define HTT_STATS_TLV_LENGTH_SET(_var, _val) \ 842 do { \ 843 HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \ 844 ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \ 845 } while (0) 846 847 848 /*=== host -> target messages ===============================================*/ 849 850 enum htt_h2t_msg_type { 851 HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, 852 HTT_H2T_MSG_TYPE_TX_FRM = 0x1, 853 HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, 854 HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, 855 HTT_H2T_MSG_TYPE_SYNC = 0x4, 856 HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, 857 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, 858 DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ 859 HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, 860 HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, 861 HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ 862 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 863 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 864 HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, 865 HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, 866 HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, 867 HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, 868 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 869 HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, 870 HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, 871 HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, 872 HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, 873 HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, 874 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 875 HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, 876 HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, 877 HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, 878 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 879 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, 880 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, 881 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, 882 HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, 883 HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, 884 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, 885 HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, 886 HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, 887 HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, 888 HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, 889 890 /* keep this last */ 891 HTT_H2T_NUM_MSGS 892 }; 893 894 /* 895 * HTT host to target message type - 896 * stored in bits 7:0 of the first word of the message 897 */ 898 #define HTT_H2T_MSG_TYPE_M 0xff 899 #define HTT_H2T_MSG_TYPE_S 0 900 901 #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ 902 do { \ 903 HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ 904 (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ 905 } while (0) 906 #define HTT_H2T_MSG_TYPE_GET(word) \ 907 (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) 908 909 /** 910 * @brief host -> target version number request message definition 911 * 912 * MSG_TYPE => HTT_H2T_MSG_TYPE_VERSION_REQ 913 * 914 * 915 * |31 24|23 16|15 8|7 0| 916 * |----------------+----------------+----------------+----------------| 917 * | reserved | msg type | 918 * |-------------------------------------------------------------------| 919 * : option request TLV (optional) | 920 * :...................................................................: 921 * 922 * The VER_REQ message may consist of a single 4-byte word, or may be 923 * extended with TLVs that specify which HTT options the host is requesting 924 * from the target. 925 * The following option TLVs may be appended to the VER_REQ message: 926 * - HL_SUPPRESS_TX_COMPL_IND 927 * - HL_MAX_TX_QUEUE_GROUPS 928 * These TLVs may appear in an arbitrary order. Any number of these TLVs 929 * may be appended to the VER_REQ message (but only one TLV of each type). 930 * 931 * Header fields: 932 * - MSG_TYPE 933 * Bits 7:0 934 * Purpose: identifies this as a version number request message 935 * Value: 0x0 (HTT_H2T_MSG_TYPE_VERSION_REQ) 936 */ 937 938 #define HTT_VER_REQ_BYTES 4 939 940 /* TBDXXX: figure out a reasonable number */ 941 #define HTT_HL_DATA_SVC_PIPE_DEPTH 24 942 #define HTT_LL_DATA_SVC_PIPE_DEPTH 64 943 944 /** 945 * @brief HTT tx MSDU descriptor 946 * 947 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_FRM 948 * 949 * @details 950 * The HTT tx MSDU descriptor is created by the host HTT SW for each 951 * tx MSDU. The HTT tx MSDU descriptor contains the information that 952 * the target firmware needs for the FW's tx processing, particularly 953 * for creating the HW msdu descriptor. 954 * The same HTT tx descriptor is used for HL and LL systems, though 955 * a few fields within the tx descriptor are used only by LL or 956 * only by HL. 957 * The HTT tx descriptor is defined in two manners: by a struct with 958 * bitfields, and by a series of [dword offset, bit mask, bit shift] 959 * definitions. 960 * The target should use the struct def, for simplicitly and clarity, 961 * but the host shall use the bit-mast + bit-shift defs, to be endian- 962 * neutral. Specifically, the host shall use the get/set macros built 963 * around the mask + shift defs. 964 */ 965 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0 966 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1 967 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1 968 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2 969 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2 970 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4 971 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3 972 #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8 973 974 #define HTT_TX_VDEV_ID_WORD 0 975 #define HTT_TX_VDEV_ID_MASK 0x3f 976 #define HTT_TX_VDEV_ID_SHIFT 16 977 978 #define HTT_TX_L3_CKSUM_OFFLOAD 1 979 #define HTT_TX_L4_CKSUM_OFFLOAD 2 980 981 #define HTT_TX_MSDU_LEN_DWORD 1 982 #define HTT_TX_MSDU_LEN_MASK 0xffff; 983 984 /* 985 * HTT_VAR_PADDR macros 986 * Allow physical / bus addresses to be either a single 32-bit value, 987 * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts 988 */ 989 #define HTT_VAR_PADDR32(var_name) \ 990 A_UINT32 var_name 991 #define HTT_VAR_PADDR64_LE(var_name) \ 992 struct { \ 993 /* little-endian: lo precedes hi */ \ 994 A_UINT32 lo; \ 995 A_UINT32 hi; \ 996 } var_name 997 998 /* 999 * TEMPLATE_HTT_TX_MSDU_DESC_T: 1000 * This macro defines a htt_tx_msdu_descXXX_t in which any physical 1001 * addresses are stored in a XXX-bit field. 1002 * This macro is used to define both htt_tx_msdu_desc32_t and 1003 * htt_tx_msdu_desc64_t structs. 1004 */ 1005 #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ 1006 PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ 1007 { \ 1008 /* DWORD 0: flags and meta-data */ \ 1009 A_UINT32 \ 1010 msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ 1011 \ 1012 /* pkt_subtype - \ 1013 * Detailed specification of the tx frame contents, extending the \ 1014 * general specification provided by pkt_type. \ 1015 * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ 1016 * pkt_type | pkt_subtype \ 1017 * ============================================================== \ 1018 * 802.3 | bit 0:3 - Reserved \ 1019 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1020 * | not appended to the HTT message \ 1021 * | 0x1 - Copy-Engine Classification Results \ 1022 * | appended to the HTT message in the \ 1023 * | format: \ 1024 * | [HTT tx desc, frame header, \ 1025 * | CE classification results] \ 1026 * | The CE classification results begin \ 1027 * | at the next 4-byte boundary after \ 1028 * | the frame header. \ 1029 * ------------+------------------------------------------------- \ 1030 * Eth2 | bit 0:3 - Reserved \ 1031 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1032 * | not appended to the HTT message \ 1033 * | 0x1 - Copy-Engine Classification Results \ 1034 * | appended to the HTT message. \ 1035 * | See the above specification of the \ 1036 * | CE classification results location. \ 1037 * ------------+------------------------------------------------- \ 1038 * native WiFi | bit 0:3 - Reserved \ 1039 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1040 * | not appended to the HTT message \ 1041 * | 0x1 - Copy-Engine Classification Results \ 1042 * | appended to the HTT message. \ 1043 * | See the above specification of the \ 1044 * | CE classification results location. \ 1045 * ------------+------------------------------------------------- \ 1046 * mgmt | 0x0 - 802.11 MAC header absent \ 1047 * | 0x1 - 802.11 MAC header present \ 1048 * ------------+------------------------------------------------- \ 1049 * raw | bit 0: 0x0 - 802.11 MAC header absent \ 1050 * | 0x1 - 802.11 MAC header present \ 1051 * | bit 1: 0x0 - allow aggregation \ 1052 * | 0x1 - don't allow aggregation \ 1053 * | bit 2: 0x0 - perform encryption \ 1054 * | 0x1 - don't perform encryption \ 1055 * | bit 3: 0x0 - perform tx classification / queuing \ 1056 * | 0x1 - don't perform tx classification; \ 1057 * | insert the frame into the "misc" \ 1058 * | tx queue \ 1059 * | bit 4: 0x0 - Copy-Engine Classification Results \ 1060 * | not appended to the HTT message \ 1061 * | 0x1 - Copy-Engine Classification Results \ 1062 * | appended to the HTT message. \ 1063 * | See the above specification of the \ 1064 * | CE classification results location. \ 1065 */ \ 1066 pkt_subtype: 5, \ 1067 \ 1068 /* pkt_type - \ 1069 * General specification of the tx frame contents. \ 1070 * The htt_pkt_type enum should be used to specify and check the \ 1071 * value of this field. \ 1072 */ \ 1073 pkt_type: 3, \ 1074 \ 1075 /* vdev_id - \ 1076 * ID for the vdev that is sending this tx frame. \ 1077 * For certain non-standard packet types, e.g. pkt_type == raw \ 1078 * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ 1079 * This field is used primarily for determining where to queue \ 1080 * broadcast and multicast frames. \ 1081 */ \ 1082 vdev_id: 6, \ 1083 /* ext_tid - \ 1084 * The extended traffic ID. \ 1085 * If the TID is unknown, the extended TID is set to \ 1086 * HTT_TX_EXT_TID_INVALID. \ 1087 * If the tx frame is QoS data, then the extended TID has the 0-15 \ 1088 * value of the QoS TID. \ 1089 * If the tx frame is non-QoS data, then the extended TID is set to \ 1090 * HTT_TX_EXT_TID_NON_QOS. \ 1091 * If the tx frame is multicast or broadcast, then the extended TID \ 1092 * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ 1093 */ \ 1094 ext_tid: 5, \ 1095 \ 1096 /* postponed - \ 1097 * This flag indicates whether the tx frame has been downloaded to \ 1098 * the target before but discarded by the target, and now is being \ 1099 * downloaded again; or if this is a new frame that is being \ 1100 * downloaded for the first time. \ 1101 * This flag allows the target to determine the correct order for \ 1102 * transmitting new vs. old frames. \ 1103 * value: 0 -> new frame, 1 -> re-send of a previously sent frame \ 1104 * This flag only applies to HL systems, since in LL systems, \ 1105 * the tx flow control is handled entirely within the target. \ 1106 */ \ 1107 postponed: 1, \ 1108 \ 1109 /* extension - \ 1110 * This flag indicates whether a HTT tx MSDU extension descriptor \ 1111 * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \ 1112 * \ 1113 * 0x0 - no extension MSDU descriptor is present \ 1114 * 0x1 - an extension MSDU descriptor immediately follows the \ 1115 * regular MSDU descriptor \ 1116 */ \ 1117 extension: 1, \ 1118 \ 1119 /* cksum_offload - \ 1120 * This flag indicates whether checksum offload is enabled or not \ 1121 * for this frame. Target FW use this flag to turn on HW checksumming \ 1122 * 0x0 - No checksum offload \ 1123 * 0x1 - L3 header checksum only \ 1124 * 0x2 - L4 checksum only \ 1125 * 0x3 - L3 header checksum + L4 checksum \ 1126 */ \ 1127 cksum_offload: 2, \ 1128 \ 1129 /* tx_comp_req - \ 1130 * This flag indicates whether Tx Completion \ 1131 * from fw is required or not. \ 1132 * This flag is only relevant if tx completion is not \ 1133 * universally enabled. \ 1134 * For all LL systems, tx completion is mandatory, \ 1135 * so this flag will be irrelevant. \ 1136 * For HL systems tx completion is optional, but HL systems in which \ 1137 * the bus throughput exceeds the WLAN throughput will \ 1138 * probably want to always use tx completion, and thus \ 1139 * would not check this flag. \ 1140 * This flag is required when tx completions are not used universally, \ 1141 * but are still required for certain tx frames for which \ 1142 * an OTA delivery acknowledgment is needed by the host. \ 1143 * In practice, this would be for HL systems in which the \ 1144 * bus throughput is less than the WLAN throughput. \ 1145 * \ 1146 * 0x0 - Tx Completion Indication from Fw not required \ 1147 * 0x1 - Tx Completion Indication from Fw is required \ 1148 */ \ 1149 tx_compl_req: 1; \ 1150 \ 1151 \ 1152 /* DWORD 1: MSDU length and ID */ \ 1153 A_UINT32 \ 1154 len: 16, /* MSDU length, in bytes */ \ 1155 id: 16; /* MSDU ID used to identify the MSDU to the host, \ 1156 * and this id is used to calculate fragmentation \ 1157 * descriptor pointer inside the target based on \ 1158 * the base address, configured inside the target. \ 1159 */ \ 1160 \ 1161 /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ 1162 /* frags_desc_ptr - \ 1163 * The fragmentation descriptor pointer tells the HW's MAC DMA \ 1164 * where the tx frame's fragments reside in memory. \ 1165 * This field only applies to LL systems, since in HL systems the \ 1166 * (degenerate single-fragment) fragmentation descriptor is created \ 1167 * within the target. \ 1168 */ \ 1169 _paddr__frags_desc_ptr_; \ 1170 \ 1171 /* DWORD 3 (or 4): peerid, chanfreq */ \ 1172 /* \ 1173 * Peer ID : Target can use this value to know which peer-id packet \ 1174 * destined to. \ 1175 * It's intended to be specified by host in case of NAWDS. \ 1176 */ \ 1177 A_UINT16 peerid; \ 1178 \ 1179 /* \ 1180 * Channel frequency: This identifies the desired channel \ 1181 * frequency (in mhz) for tx frames. This is used by FW to help \ 1182 * determine when it is safe to transmit or drop frames for \ 1183 * off-channel operation. \ 1184 * The default value of zero indicates to FW that the corresponding \ 1185 * VDEV's home channel (if there is one) is the desired channel \ 1186 * frequency. \ 1187 */ \ 1188 A_UINT16 chanfreq; \ 1189 \ 1190 /* Reason reserved is commented is increasing the htt structure size \ 1191 * leads to some weird issues. \ 1192 * A_UINT32 reserved_dword3_bits0_31; \ 1193 */ \ 1194 } POSTPACK 1195 /* define a htt_tx_msdu_desc32_t type */ 1196 TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); 1197 /* define a htt_tx_msdu_desc64_t type */ 1198 TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); 1199 /* 1200 * Make htt_tx_msdu_desc_t be an alias for either 1201 * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t 1202 */ 1203 #if HTT_PADDR64 1204 #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t 1205 #else 1206 #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t 1207 #endif 1208 1209 /* decriptor information for Management frame*/ 1210 /* 1211 * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT. 1212 * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t. 1213 */ 1214 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 1215 extern A_UINT32 mgmt_hdr_len; 1216 PREPACK struct htt_mgmt_tx_desc_t { 1217 A_UINT32 msg_type; 1218 #if HTT_PADDR64 1219 A_UINT64 frag_paddr; /* DMAble address of the data */ 1220 #else 1221 A_UINT32 frag_paddr; /* DMAble address of the data */ 1222 #endif 1223 A_UINT32 desc_id; /* returned to host during completion 1224 * to free the meory*/ 1225 A_UINT32 len; /* Fragment length */ 1226 A_UINT32 vdev_id; /* virtual device ID*/ 1227 A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ 1228 } POSTPACK; 1229 1230 PREPACK struct htt_mgmt_tx_compl_ind { 1231 A_UINT32 desc_id; 1232 A_UINT32 status; 1233 } POSTPACK; 1234 1235 /* 1236 * This SDU header size comes from the summation of the following: 1237 * 1. Max of: 1238 * a. Native WiFi header, for native WiFi frames: 24 bytes 1239 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4) 1240 * b. 802.11 header, for raw frames: 36 bytes 1241 * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4, 1242 * QoS header, HT header) 1243 * c. 802.3 header, for ethernet frames: 14 bytes 1244 * (destination address, source address, ethertype / length) 1245 * 2. Max of: 1246 * a. IPv4 header, up through the DiffServ Code Point: 2 bytes 1247 * b. IPv6 header, up through the Traffic Class: 2 bytes 1248 * 3. 802.1Q VLAN header: 4 bytes 1249 * 4. LLC/SNAP header: 8 bytes 1250 */ 1251 #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30 1252 #define HTT_TX_HDR_SIZE_802_11_RAW 36 1253 #define HTT_TX_HDR_SIZE_ETHERNET 14 1254 1255 #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW 1256 A_COMPILE_TIME_ASSERT( 1257 htt_encap_hdr_size_max_check_nwifi, 1258 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI); 1259 A_COMPILE_TIME_ASSERT( 1260 htt_encap_hdr_size_max_check_enet, 1261 HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET); 1262 1263 #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ 1264 #define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ 1265 1266 #define HTT_TX_HDR_SIZE_802_1Q 4 1267 #define HTT_TX_HDR_SIZE_LLC_SNAP 8 1268 1269 1270 #define HTT_COMMON_TX_FRM_HDR_LEN \ 1271 (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ 1272 HTT_TX_HDR_SIZE_802_1Q + \ 1273 HTT_TX_HDR_SIZE_LLC_SNAP) 1274 1275 #define HTT_HL_TX_FRM_HDR_LEN \ 1276 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) 1277 1278 #define HTT_LL_TX_FRM_HDR_LEN \ 1279 (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) 1280 1281 #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) 1282 1283 /* dword 0 */ 1284 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0 1285 #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0 1286 #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00 1287 #define HTT_TX_DESC_PKT_SUBTYPE_S 8 1288 1289 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0 1290 #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0 1291 #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400 1292 #define HTT_TX_DESC_NO_ENCRYPT_S 10 1293 1294 #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0 1295 #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0 1296 #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000 1297 #define HTT_TX_DESC_PKT_TYPE_S 13 1298 1299 #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0 1300 #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0 1301 #define HTT_TX_DESC_VDEV_ID_M 0x003f0000 1302 #define HTT_TX_DESC_VDEV_ID_S 16 1303 1304 #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0 1305 #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0 1306 #define HTT_TX_DESC_EXT_TID_M 0x07c00000 1307 #define HTT_TX_DESC_EXT_TID_S 22 1308 1309 #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0 1310 #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0 1311 #define HTT_TX_DESC_POSTPONED_M 0x08000000 1312 #define HTT_TX_DESC_POSTPONED_S 27 1313 1314 #define HTT_TX_DESC_EXTENSION_OFFSET_BYTE 0 1315 #define HTT_TX_DESC_EXTENSION_OFFSET_DWORD 0 1316 #define HTT_TX_DESC_EXTENSION_M 0x10000000 1317 #define HTT_TX_DESC_EXTENSION_S 28 1318 1319 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0 1320 #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0 1321 #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000 1322 #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29 1323 1324 #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0 1325 #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0 1326 #define HTT_TX_DESC_TX_COMP_M 0x80000000 1327 #define HTT_TX_DESC_TX_COMP_S 31 1328 1329 /* dword 1 */ 1330 #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4 1331 #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1 1332 #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff 1333 #define HTT_TX_DESC_FRM_LEN_S 0 1334 1335 #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4 1336 #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1 1337 #define HTT_TX_DESC_FRM_ID_M 0xffff0000 1338 #define HTT_TX_DESC_FRM_ID_S 16 1339 1340 /* dword 2 */ 1341 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8 1342 #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2 1343 /* for systems using 64-bit format for bus addresses */ 1344 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff 1345 #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0 1346 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff 1347 #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0 1348 /* for systems using 32-bit format for bus addresses */ 1349 #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff 1350 #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0 1351 1352 /* dword 3 */ 1353 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 1354 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 1355 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ 1356 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) 1357 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ 1358 (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) 1359 1360 #if HTT_PADDR64 1361 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 1362 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 1363 #else 1364 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 1365 #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 1366 #endif 1367 1368 #define HTT_TX_DESC_PEER_ID_M 0x0000ffff 1369 #define HTT_TX_DESC_PEER_ID_S 0 1370 /* 1371 * TEMPORARY: 1372 * The original definitions for the PEER_ID fields contained typos 1373 * (with _DESC_PADDR appended to this PEER_ID field name). 1374 * Retain deprecated original names for PEER_ID fields until all code that 1375 * refers to them has been updated. 1376 */ 1377 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ 1378 HTT_TX_DESC_PEER_ID_OFFSET_BYTES 1379 #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ 1380 HTT_TX_DESC_PEER_ID_OFFSET_DWORD 1381 #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ 1382 HTT_TX_DESC_PEER_ID_M 1383 #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ 1384 HTT_TX_DESC_PEER_ID_S 1385 1386 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */ 1387 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */ 1388 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ 1389 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) 1390 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ 1391 (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) 1392 1393 #if HTT_PADDR64 1394 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 1395 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 1396 #else 1397 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 1398 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 1399 #endif 1400 1401 #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 1402 #define HTT_TX_DESC_CHAN_FREQ_S 16 1403 1404 #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ 1405 (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) 1406 #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ 1407 do { \ 1408 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ 1409 ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ 1410 } while (0) 1411 1412 #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ 1413 (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) 1414 #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ 1415 do { \ 1416 HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ 1417 ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ 1418 } while (0) 1419 1420 #define HTT_TX_DESC_PKT_TYPE_GET(_var) \ 1421 (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) 1422 #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ 1423 do { \ 1424 HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ 1425 ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ 1426 } while (0) 1427 1428 #define HTT_TX_DESC_VDEV_ID_GET(_var) \ 1429 (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) 1430 #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ 1431 do { \ 1432 HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ 1433 ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ 1434 } while (0) 1435 1436 #define HTT_TX_DESC_EXT_TID_GET(_var) \ 1437 (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) 1438 #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ 1439 do { \ 1440 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ 1441 ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ 1442 } while (0) 1443 1444 #define HTT_TX_DESC_POSTPONED_GET(_var) \ 1445 (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) 1446 #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ 1447 do { \ 1448 HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ 1449 ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ 1450 } while (0) 1451 1452 #define HTT_TX_DESC_EXTENSION_GET(_var) \ 1453 (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S) 1454 #define HTT_TX_DESC_EXTENSION_SET(_var, _val) \ 1455 do { \ 1456 HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \ 1457 ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \ 1458 } while (0) 1459 1460 #define HTT_TX_DESC_FRM_LEN_GET(_var) \ 1461 (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) 1462 #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ 1463 do { \ 1464 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ 1465 ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ 1466 } while (0) 1467 1468 #define HTT_TX_DESC_FRM_ID_GET(_var) \ 1469 (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) 1470 #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ 1471 do { \ 1472 HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ 1473 ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ 1474 } while (0) 1475 1476 #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ 1477 (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) 1478 #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ 1479 do { \ 1480 HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ 1481 ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ 1482 } while (0) 1483 1484 #define HTT_TX_DESC_TX_COMP_GET(_var) \ 1485 (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) 1486 #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ 1487 do { \ 1488 HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ 1489 ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ 1490 } while (0) 1491 1492 #define HTT_TX_DESC_PEER_ID_GET(_var) \ 1493 (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) 1494 #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ 1495 do { \ 1496 HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ 1497 ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ 1498 } while (0) 1499 1500 #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ 1501 (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) 1502 #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ 1503 do { \ 1504 HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ 1505 ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ 1506 } while (0) 1507 1508 1509 /* enums used in the HTT tx MSDU extension descriptor */ 1510 enum { 1511 htt_tx_guard_interval_regular = 0, 1512 htt_tx_guard_interval_short = 1, 1513 }; 1514 1515 enum { 1516 htt_tx_preamble_type_ofdm = 0, 1517 htt_tx_preamble_type_cck = 1, 1518 htt_tx_preamble_type_ht = 2, 1519 htt_tx_preamble_type_vht = 3, 1520 }; 1521 1522 enum { 1523 htt_tx_bandwidth_5MHz = 0, 1524 htt_tx_bandwidth_10MHz = 1, 1525 htt_tx_bandwidth_20MHz = 2, 1526 htt_tx_bandwidth_40MHz = 3, 1527 htt_tx_bandwidth_80MHz = 4, 1528 htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ 1529 }; 1530 1531 /** 1532 * @brief HTT tx MSDU extension descriptor 1533 * @details 1534 * If the target supports HTT tx MSDU extension descriptors, the host has 1535 * the option of appending the following struct following the regular 1536 * HTT tx MSDU descriptor (and setting the "extension" flag in the regular 1537 * HTT tx MSDU descriptor, to show that the extension descriptor is present). 1538 * The HTT tx MSDU extension descriptors allows the host to provide detailed 1539 * tx specs for each frame. 1540 */ 1541 PREPACK struct htt_tx_msdu_desc_ext_t { 1542 /* DWORD 0: flags */ 1543 A_UINT32 1544 valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */ 1545 valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */ 1546 valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */ 1547 valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/ 1548 valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */ 1549 valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */ 1550 valid_retries: 1, /* bit 6: if set, tx retries spec is valid */ 1551 valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */ 1552 valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/ 1553 is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */ 1554 reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */ 1555 1556 /* DWORD 1: tx power, tx rate, tx BW */ 1557 A_UINT32 1558 /* pwr - 1559 * Specify what power the tx frame needs to be transmitted at. 1560 * The power a signed (two's complement) value is in units of 0.5 dBm. 1561 * The value needs to be appropriately sign-extended when extracting 1562 * the value from the message and storing it in a variable that is 1563 * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro 1564 * automatically handles this sign-extension.) 1565 * If the transmission uses multiple tx chains, this power spec is 1566 * the total transmit power, assuming incoherent combination of 1567 * per-chain power to produce the total power. 1568 */ 1569 pwr: 8, 1570 1571 /* mcs_mask - 1572 * Specify the allowable values for MCS index (modulation and coding) 1573 * to use for transmitting the frame. 1574 * 1575 * For HT / VHT preamble types, this mask directly corresponds to 1576 * the HT or VHT MCS indices that are allowed. For each bit N set 1577 * within the mask, MCS index N is allowed for transmitting the frame. 1578 * For legacy CCK and OFDM rates, separate bits are provided for CCK 1579 * rates versus OFDM rates, so the host has the option of specifying 1580 * that the target must transmit the frame with CCK or OFDM rates 1581 * (not HT or VHT), but leaving the decision to the target whether 1582 * to use CCK or OFDM. 1583 * 1584 * For CCK and OFDM, the bits within this mask are interpreted as 1585 * follows: 1586 * bit 0 -> CCK 1 Mbps rate is allowed 1587 * bit 1 -> CCK 2 Mbps rate is allowed 1588 * bit 2 -> CCK 5.5 Mbps rate is allowed 1589 * bit 3 -> CCK 11 Mbps rate is allowed 1590 * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed 1591 * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed 1592 * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed 1593 * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed 1594 * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed 1595 * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed 1596 * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed 1597 * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed 1598 * 1599 * The MCS index specification needs to be compatible with the 1600 * bandwidth mask specification. For example, a MCS index == 9 1601 * specification is inconsistent with a preamble type == VHT, 1602 * Nss == 1, and channel bandwidth == 20 MHz. 1603 * 1604 * Furthermore, the host has only a limited ability to specify to 1605 * the target to select from HT + legacy rates, or VHT + legacy rates, 1606 * since this mcs_mask can specify either HT/VHT rates or legacy rates. 1607 */ 1608 mcs_mask: 12, 1609 1610 /* nss_mask - 1611 * Specify which numbers of spatial streams (MIMO factor) are permitted. 1612 * Each bit in this mask corresponds to a Nss value: 1613 * bit 0: if set, Nss = 1 (non-MIMO) is permitted 1614 * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted 1615 * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted 1616 * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted 1617 * The values in the Nss mask must be suitable for the recipient, e.g. 1618 * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a 1619 * recipient which only supports 2x2 MIMO. 1620 */ 1621 nss_mask: 4, 1622 1623 /* guard_interval - 1624 * Specify a htt_tx_guard_interval enum value to indicate whether 1625 * the transmission should use a regular guard interval or a 1626 * short guard interval. 1627 */ 1628 guard_interval: 1, 1629 1630 /* preamble_type_mask - 1631 * Specify which preamble types (CCK, OFDM, HT, VHT) the target 1632 * may choose from for transmitting this frame. 1633 * The bits in this mask correspond to the values in the 1634 * htt_tx_preamble_type enum. For example, to allow the target 1635 * to transmit the frame as either CCK or OFDM, this field would 1636 * be set to 1637 * (1 << htt_tx_preamble_type_ofdm) | 1638 * (1 << htt_tx_preamble_type_cck) 1639 */ 1640 preamble_type_mask: 4, 1641 1642 reserved1_31_29: 3; /* unused, set to 0x0 */ 1643 1644 /* DWORD 2: tx chain mask, tx retries */ 1645 A_UINT32 1646 /* chain_mask - specify which chains to transmit from */ 1647 chain_mask: 4, 1648 1649 /* retry_limit - 1650 * Specify the maximum number of transmissions, including the 1651 * initial transmission, to attempt before giving up if no ack 1652 * is received. 1653 * If the tx rate is specified, then all retries shall use the 1654 * same rate as the initial transmission. 1655 * If no tx rate is specified, the target can choose whether to 1656 * retain the original rate during the retransmissions, or to 1657 * fall back to a more robust rate. 1658 */ 1659 retry_limit: 4, 1660 1661 /* bandwidth_mask - 1662 * Specify what channel widths may be used for the transmission. 1663 * A value of zero indicates "don't care" - the target may choose 1664 * the transmission bandwidth. 1665 * The bits within this mask correspond to the htt_tx_bandwidth 1666 * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. 1667 * The bandwidth_mask must be consistent with the preamble_type_mask 1668 * and mcs_mask specs, if they are provided. For example, 80 MHz and 1669 * 160 MHz can only be enabled in the mask if preamble_type == VHT. 1670 */ 1671 bandwidth_mask: 6, 1672 1673 reserved2_31_14: 18; /* unused, set to 0x0 */ 1674 1675 /* DWORD 3: tx expiry time (TSF) LSBs */ 1676 A_UINT32 expire_tsf_lo; 1677 1678 /* DWORD 4: tx expiry time (TSF) MSBs */ 1679 A_UINT32 expire_tsf_hi; 1680 1681 A_UINT32 reserved_for_future_expansion_set_to_zero[3]; 1682 } POSTPACK; 1683 1684 /* DWORD 0 */ 1685 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001 1686 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0 1687 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 1688 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1 1689 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 1690 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2 1691 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008 1692 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3 1693 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010 1694 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4 1695 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020 1696 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5 1697 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040 1698 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6 1699 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080 1700 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7 1701 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100 1702 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8 1703 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200 1704 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9 1705 1706 /* DWORD 1 */ 1707 #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff 1708 #define HTT_TX_MSDU_EXT_DESC_PWR_S 0 1709 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00 1710 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8 1711 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000 1712 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20 1713 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000 1714 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24 1715 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000 1716 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25 1717 1718 /* DWORD 2 */ 1719 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f 1720 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0 1721 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0 1722 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4 1723 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00 1724 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8 1725 1726 1727 /* DWORD 0 */ 1728 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ 1729 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 1730 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) 1731 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 1732 do { \ 1733 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ 1734 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ 1735 } while (0) 1736 1737 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 1738 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ 1739 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) 1740 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 1741 do { \ 1742 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ 1743 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ 1744 } while (0) 1745 1746 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 1747 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 1748 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) 1749 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 1750 do { \ 1751 HTT_CHECK_SET_VAL( \ 1752 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 1753 ((_var) |= ((_val) \ 1754 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 1755 } while (0) 1756 1757 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ 1758 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \ 1759 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) 1760 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1761 do { \ 1762 HTT_CHECK_SET_VAL( \ 1763 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ 1764 ((_var) |= ((_val) \ 1765 << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ 1766 } while (0) 1767 1768 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 1769 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 1770 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) 1771 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 1772 do { \ 1773 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 1774 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 1775 } while (0) 1776 1777 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ 1778 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ 1779 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) 1780 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 1781 do { \ 1782 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ 1783 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ 1784 } while (0) 1785 1786 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ 1787 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ 1788 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) 1789 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ 1790 do { \ 1791 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ 1792 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ 1793 } while (0) 1794 1795 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 1796 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 1797 HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) 1798 #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 1799 do { \ 1800 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 1801 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 1802 } while (0) 1803 1804 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ 1805 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ 1806 HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) 1807 #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 1808 do { \ 1809 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ 1810 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ 1811 } while (0) 1812 1813 1814 /* DWORD 1 */ 1815 #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ 1816 (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ 1817 HTT_TX_MSDU_EXT_DESC_PWR_S) 1818 #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ 1819 (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ 1820 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) 1821 #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ 1822 ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ 1823 HTT_TX_MSDU_EXT_DESC_PWR_M) 1824 1825 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ 1826 (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ 1827 HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) 1828 #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ 1829 do { \ 1830 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ 1831 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ 1832 } while (0) 1833 1834 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ 1835 (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ 1836 HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) 1837 #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ 1838 do { \ 1839 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ 1840 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ 1841 } while (0) 1842 1843 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ 1844 (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ 1845 HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) 1846 #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ 1847 do { \ 1848 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ 1849 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ 1850 } while (0) 1851 1852 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ 1853 (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ 1854 HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) 1855 #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ 1856 do { \ 1857 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \ 1858 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ 1859 } while (0) 1860 1861 1862 /* DWORD 2 */ 1863 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ 1864 (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ 1865 HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) 1866 #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ 1867 do { \ 1868 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ 1869 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ 1870 } while (0) 1871 1872 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ 1873 (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ 1874 HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) 1875 #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ 1876 do { \ 1877 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ 1878 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ 1879 } while (0) 1880 1881 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ 1882 (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ 1883 HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) 1884 #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ 1885 do { \ 1886 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ 1887 ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ 1888 } while (0) 1889 1890 1891 typedef enum { 1892 HTT_11AX_HE_LTF_SUBTYPE_1X, 1893 HTT_11AX_HE_LTF_SUBTYPE_2X, 1894 HTT_11AX_HE_LTF_SUBTYPE_4X, 1895 } htt_11ax_ltf_subtype_t; 1896 1897 typedef enum { 1898 HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM, 1899 HTT_TX_MSDU_EXT2_DESC_PREAM_CCK, 1900 HTT_TX_MSDU_EXT2_DESC_PREAM_HT , 1901 HTT_TX_MSDU_EXT2_DESC_PREAM_VHT, 1902 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU, 1903 HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU, 1904 } htt_tx_ext2_preamble_type_t; 1905 1906 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_M 0x00000001 1907 #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_S 0 1908 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_M 0x00000002 1909 #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_S 1 1910 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_M 0x00000004 1911 #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_S 2 1912 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_M 0x00000008 1913 #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_S 3 1914 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_M 0x00000010 1915 #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_S 4 1916 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_M 0x00000020 1917 #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_S 5 1918 1919 /** 1920 * @brief HTT tx MSDU extension descriptor v2 1921 * @details 1922 * In Lithium, if htt_tx_tcl_metadata->valid_htt_ext is set, this structure 1923 * is received as tcl_exit_base->host_meta_info in firmware. 1924 * Also there is no htt_tx_msdu_desc_t in Lithium since most of those fields 1925 * are already part of tcl_exit_base. 1926 */ 1927 PREPACK struct htt_tx_msdu_desc_ext2_t { 1928 /* DWORD 0: flags */ 1929 A_UINT32 1930 valid_pwr : 1, /* if set, tx pwr spec is valid */ 1931 valid_mcs_mask : 1, /* if set, tx MCS mask is valid */ 1932 valid_nss_mask : 1, /* if set, tx Nss mask is valid */ 1933 valid_preamble_type : 1, /* if set, tx preamble spec is valid */ 1934 valid_retries : 1, /* if set, tx retries spec is valid */ 1935 valid_bw_info : 1, /* if set, tx dyn_bw and bw_mask are valid */ 1936 valid_guard_interval : 1, /* if set, tx guard intv spec is valid */ 1937 valid_chainmask : 1, /* if set, tx chainmask is valid */ 1938 valid_encrypt_type : 1, /* if set, encrypt type is valid */ 1939 valid_key_flags : 1, /* if set, key flags is valid */ 1940 valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */ 1941 valid_chanfreq : 1, /* if set, chanfreq is valid */ 1942 is_dsrc : 1, /* if set, MSDU is a DSRC frame */ 1943 guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */ 1944 encrypt_type : 2, /* 0 = NO_ENCRYPT, 1945 1 = ENCRYPT, 1946 2 ~ 3 - Reserved */ 1947 /* retry_limit - 1948 * Specify the maximum number of transmissions, including the 1949 * initial transmission, to attempt before giving up if no ack 1950 * is received. 1951 * If the tx rate is specified, then all retries shall use the 1952 * same rate as the initial transmission. 1953 * If no tx rate is specified, the target can choose whether to 1954 * retain the original rate during the retransmissions, or to 1955 * fall back to a more robust rate. 1956 */ 1957 retry_limit : 4, 1958 use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation. 1959 * Valid only for 11ax preamble types HE_SU 1960 * and HE_EXT_SU 1961 */ 1962 ltf_subtype_11ax : 2, /* Takes enum values of htt_11ax_ltf_subtype_t 1963 * Valid only for 11ax preamble types HE_SU 1964 * and HE_EXT_SU 1965 */ 1966 dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */ 1967 bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw). 1968 * (Bit mask of 5, 10, 20, 40, 80, 160Mhz. 1969 * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.) 1970 */ 1971 host_tx_desc_pool : 1; /* If set, Firmware allocates tx_descriptors 1972 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead 1973 * of WAL_BUFFERID_TX_TCL_DATA_EXP. 1974 * Use cases: 1975 * Any time firmware uses TQM-BYPASS for Data 1976 * TID, firmware expect host to set this bit. 1977 */ 1978 1979 /* DWORD 1: tx power, tx rate */ 1980 A_UINT32 1981 power : 8, /* unit of the power field is 0.5 dbm 1982 * similar to pwr field in htt_tx_msdu_desc_ext_t 1983 * signed value ranging from -64dbm to 63.5 dbm 1984 */ 1985 mcs_mask : 12, /* mcs bit mask of 0 ~ 11 1986 * Setting more than one MCS isn't currently 1987 * supported by the target (but is supported 1988 * in the interface in case in the future 1989 * the target supports specifications of 1990 * a limited set of MCS values. 1991 */ 1992 nss_mask : 8, /* Nss bit mask 0 ~ 7 1993 * Setting more than one Nss isn't currently 1994 * supported by the target (but is supported 1995 * in the interface in case in the future 1996 * the target supports specifications of 1997 * a limited set of Nss values. 1998 */ 1999 pream_type : 3, /* Takes enum values of htt_tx_ext2_preamble_type_t */ 2000 update_peer_cache : 1; /* When set these custom values will be 2001 * used for all packets, until the next 2002 * update via this ext header. 2003 * This is to make sure not all packets 2004 * need to include this header. 2005 */ 2006 2007 /* DWORD 2: tx chain mask, tx retries */ 2008 A_UINT32 2009 /* chain_mask - specify which chains to transmit from */ 2010 chain_mask : 8, 2011 2012 key_flags : 8, /* Key Index and related flags - used in mesh mode 2013 * TODO: Update Enum values for key_flags 2014 */ 2015 2016 /* 2017 * Channel frequency: This identifies the desired channel 2018 * frequency (in MHz) for tx frames. This is used by FW to help 2019 * determine when it is safe to transmit or drop frames for 2020 * off-channel operation. 2021 * The default value of zero indicates to FW that the corresponding 2022 * VDEV's home channel (if there is one) is the desired channel 2023 * frequency. 2024 */ 2025 chanfreq : 16; 2026 2027 /* DWORD 3: tx expiry time (TSF) LSBs */ 2028 A_UINT32 expire_tsf_lo; 2029 2030 /* DWORD 4: tx expiry time (TSF) MSBs */ 2031 A_UINT32 expire_tsf_hi; 2032 2033 /* DWORD 5: flags to control routing / processing of the MSDU */ 2034 A_UINT32 2035 /* learning_frame 2036 * When this flag is set, this frame will be dropped by FW 2037 * rather than being enqueued to the Transmit Queue Manager (TQM) HW. 2038 */ 2039 learning_frame : 1, 2040 /* send_as_standalone 2041 * This will indicate if the msdu needs to be sent as a singleton PPDU, 2042 * i.e. with no A-MSDU or A-MPDU aggregation. 2043 * The scope is extended to other use-cases. 2044 */ 2045 send_as_standalone : 1, 2046 /* is_host_opaque_valid 2047 * Host should set this bit to 1 if the host_opaque_cookie is populated 2048 * with valid information. 2049 */ 2050 is_host_opaque_valid : 1, 2051 traffic_end_indication: 1, 2052 rsvd0 : 28; 2053 2054 /* DWORD 6 : Host opaque cookie for special frames */ 2055 A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */ 2056 rsvd1 : 16; 2057 2058 /* 2059 * This structure can be expanded further up to 40 bytes 2060 * by adding further DWORDs as needed. 2061 */ 2062 } POSTPACK; 2063 2064 /* DWORD 0 */ 2065 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_M 0x00000001 2066 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S 0 2067 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 2068 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S 1 2069 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 2070 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S 2 2071 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M 0x00000008 2072 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S 3 2073 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M 0x00000010 2074 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S 4 2075 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M 0x00000020 2076 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S 5 2077 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000040 2078 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S 6 2079 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000080 2080 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S 7 2081 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M 0x00000100 2082 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S 8 2083 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M 0x00000200 2084 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S 9 2085 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000400 2086 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S 10 2087 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M 0x00000800 2088 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S 11 2089 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M 0x00001000 2090 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S 12 2091 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M 0x00006000 2092 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S 13 2093 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M 0x00018000 2094 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S 15 2095 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M 0x001e0000 2096 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S 17 2097 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M 0x00200000 2098 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S 21 2099 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M 0x00c00000 2100 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S 22 2101 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_M 0x01000000 2102 #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_S 24 2103 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_M 0x7e000000 2104 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_S 25 2105 2106 /* DWORD 1 */ 2107 #define HTT_TX_MSDU_EXT2_DESC_PWR_M 0x000000ff 2108 #define HTT_TX_MSDU_EXT2_DESC_PWR_S 0 2109 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M 0x000fff00 2110 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S 8 2111 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M 0x0ff00000 2112 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S 20 2113 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_M 0x70000000 2114 #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_S 28 2115 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_M 0x80000000 2116 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_S 31 2117 2118 /* DWORD 2 */ 2119 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M 0x000000ff 2120 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S 0 2121 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_M 0x0000ff00 2122 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S 8 2123 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_M 0xffff0000 2124 #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_S 16 2125 2126 /* DWORD 5 */ 2127 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M 0x00000001 2128 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S 0 2129 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M 0x00000002 2130 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S 1 2131 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M 0x00000004 2132 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S 2 2133 2134 /* DWORD 6 */ 2135 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M 0x0000FFFF 2136 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S 0 2137 2138 2139 /* DWORD 0 */ 2140 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \ 2141 (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ 2142 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S) 2143 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \ 2144 do { \ 2145 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \ 2146 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)); \ 2147 } while (0) 2148 2149 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ 2150 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \ 2151 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S) 2152 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ 2153 do { \ 2154 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK, _val); \ 2155 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \ 2156 } while (0) 2157 2158 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_GET(_var) \ 2159 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \ 2160 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S) 2161 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_SET(_var, _val) \ 2162 do { \ 2163 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK, _val); \ 2164 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \ 2165 } while (0) 2166 2167 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_GET(_var) \ 2168 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \ 2169 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S) 2170 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_SET(_var, _val) \ 2171 do { \ 2172 HTT_CHECK_SET_VAL( \ 2173 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \ 2174 ((_var) |= ((_val) \ 2175 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \ 2176 } while (0) 2177 2178 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_GET(_var) \ 2179 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \ 2180 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S) 2181 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ 2182 do { \ 2183 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES, _val); \ 2184 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \ 2185 } while (0) 2186 2187 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \ 2188 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \ 2189 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S) 2190 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \ 2191 do { \ 2192 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO, _val); \ 2193 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \ 2194 } while (0) 2195 2196 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ 2197 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ 2198 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S) 2199 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ 2200 do { \ 2201 HTT_CHECK_SET_VAL( \ 2202 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ 2203 ((_var) |= ((_val) \ 2204 << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ 2205 } while (0) 2206 2207 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ 2208 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ 2209 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S) 2210 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ 2211 do { \ 2212 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK, _val); \ 2213 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \ 2214 } while (0) 2215 2216 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \ 2217 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \ 2218 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S) 2219 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_SET(_var, _val) \ 2220 do { \ 2221 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \ 2222 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\ 2223 } while (0) 2224 2225 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \ 2226 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \ 2227 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S) 2228 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \ 2229 do { \ 2230 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \ 2231 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\ 2232 } while (0) 2233 2234 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ 2235 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ 2236 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S) 2237 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ 2238 do { \ 2239 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ 2240 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\ 2241 } while (0) 2242 2243 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \ 2244 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \ 2245 HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S) 2246 #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \ 2247 do { \ 2248 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ, _val); \ 2249 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)); \ 2250 } while (0) 2251 2252 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \ 2253 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \ 2254 HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S) 2255 #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \ 2256 do { \ 2257 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val); \ 2258 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)); \ 2259 } while (0) 2260 2261 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \ 2262 (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \ 2263 HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S) 2264 #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \ 2265 do { \ 2266 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val); \ 2267 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)); \ 2268 } while (0) 2269 2270 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \ 2271 (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \ 2272 HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S) 2273 #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \ 2274 do { \ 2275 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val); \ 2276 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)); \ 2277 } while (0) 2278 2279 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \ 2280 (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \ 2281 HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S) 2282 #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \ 2283 do { \ 2284 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val); \ 2285 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)); \ 2286 } while (0) 2287 2288 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \ 2289 (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \ 2290 HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S) 2291 #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \ 2292 do { \ 2293 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val); \ 2294 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)); \ 2295 } while (0) 2296 2297 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \ 2298 (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \ 2299 HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S) 2300 #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \ 2301 do { \ 2302 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX, _val); \ 2303 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \ 2304 } while (0) 2305 2306 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \ 2307 (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \ 2308 HTT_TX_MSDU_EXT2_DESC_BW_MASK_S) 2309 #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \ 2310 do { \ 2311 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \ 2312 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)); \ 2313 } while (0) 2314 2315 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \ 2316 (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \ 2317 HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S) 2318 #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \ 2319 do { \ 2320 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val); \ 2321 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \ 2322 } while (0) 2323 2324 /* DWORD 1 */ 2325 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \ 2326 (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \ 2327 HTT_TX_MSDU_EXT2_DESC_PWR_S) 2328 #define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \ 2329 (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \ 2330 HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR)) 2331 #define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \ 2332 ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \ 2333 HTT_TX_MSDU_EXT2_DESC_PWR_M) 2334 2335 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \ 2336 (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \ 2337 HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S) 2338 #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \ 2339 do { \ 2340 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val); \ 2341 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)); \ 2342 } while (0) 2343 2344 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \ 2345 (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \ 2346 HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S) 2347 #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \ 2348 do { \ 2349 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val); \ 2350 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)); \ 2351 } while (0) 2352 2353 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \ 2354 (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \ 2355 HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S) 2356 #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \ 2357 do { \ 2358 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val); \ 2359 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)); \ 2360 } while (0) 2361 2362 #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_GET(_var) \ 2363 (((_var) & HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_M) >> \ 2364 HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S) 2365 #define HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_SET(_var, _val) \ 2366 do { \ 2367 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE, _val); \ 2368 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S)); \ 2369 } while (0) 2370 2371 /* DWORD 2 */ 2372 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \ 2373 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \ 2374 HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S) 2375 #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \ 2376 do { \ 2377 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val); \ 2378 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)); \ 2379 } while (0) 2380 2381 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \ 2382 (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \ 2383 HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S) 2384 #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \ 2385 do { \ 2386 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val); \ 2387 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)); \ 2388 } while (0) 2389 2390 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \ 2391 (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \ 2392 HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S) 2393 #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \ 2394 do { \ 2395 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val); \ 2396 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)); \ 2397 } while (0) 2398 2399 /* DWORD 5 */ 2400 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_GET(_var) \ 2401 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M) >> \ 2402 HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S) 2403 #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_SET(_var, _val) \ 2404 do { \ 2405 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME, _val); \ 2406 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)); \ 2407 } while (0) 2408 2409 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_GET(_var) \ 2410 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M) >> \ 2411 HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S) 2412 2413 #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET(_var, _val) \ 2414 do { \ 2415 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE, _val); \ 2416 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)); \ 2417 } while (0) 2418 2419 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_GET(_var) \ 2420 (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M) >> \ 2421 HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S) 2422 #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET(_var, _val) \ 2423 do { \ 2424 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID, _val); \ 2425 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)); \ 2426 } while (0) 2427 2428 /* DWORD 6 */ 2429 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_GET(_var) \ 2430 (((_var) & HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M) >> \ 2431 HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S) 2432 #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET(_var, _val) \ 2433 do { \ 2434 HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE, _val); \ 2435 ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)); \ 2436 } while (0) 2437 2438 2439 typedef enum { 2440 HTT_TCL_METADATA_TYPE_PEER_BASED = 0, 2441 HTT_TCL_METADATA_TYPE_VDEV_BASED = 1, 2442 } htt_tcl_metadata_type; 2443 2444 /** 2445 * @brief HTT TCL command number format 2446 * @details 2447 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2448 * available to firmware as tcl_exit_base->tcl_status_number. 2449 * For regular / multicast packets host will send vdev and mac id and for 2450 * NAWDS packets, host will send peer id. 2451 * A_UINT32 is used to avoid endianness conversion problems. 2452 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2453 */ 2454 2455 typedef struct { 2456 A_UINT32 2457 type: 1, /* vdev_id based or peer_id based */ 2458 rsvd: 31; 2459 } htt_tx_tcl_vdev_or_peer_t; 2460 2461 typedef struct { 2462 A_UINT32 2463 type: 1, /* vdev_id based or peer_id based */ 2464 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2465 vdev_id: 8, 2466 pdev_id: 2, 2467 host_inspected:1, 2468 rsvd: 19; 2469 } htt_tx_tcl_vdev_metadata; 2470 2471 typedef struct { 2472 A_UINT32 2473 type: 1, /* vdev_id based or peer_id based */ 2474 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2475 peer_id: 14, 2476 rsvd: 16; 2477 } htt_tx_tcl_peer_metadata; 2478 2479 PREPACK struct htt_tx_tcl_metadata { 2480 union { 2481 htt_tx_tcl_vdev_or_peer_t vdev_or_peer; 2482 htt_tx_tcl_vdev_metadata vdev_meta; 2483 htt_tx_tcl_peer_metadata peer_meta; 2484 }; 2485 } POSTPACK; 2486 2487 /* DWORD 0 */ 2488 #define HTT_TX_TCL_METADATA_TYPE_M 0x00000001 2489 #define HTT_TX_TCL_METADATA_TYPE_S 0 2490 #define HTT_TX_TCL_METADATA_VALID_HTT_M 0x00000002 2491 #define HTT_TX_TCL_METADATA_VALID_HTT_S 1 2492 2493 /* VDEV metadata */ 2494 #define HTT_TX_TCL_METADATA_VDEV_ID_M 0x000003fc 2495 #define HTT_TX_TCL_METADATA_VDEV_ID_S 2 2496 #define HTT_TX_TCL_METADATA_PDEV_ID_M 0x00000c00 2497 #define HTT_TX_TCL_METADATA_PDEV_ID_S 10 2498 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_M 0x00001000 2499 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_S 12 2500 2501 /* PEER metadata */ 2502 #define HTT_TX_TCL_METADATA_PEER_ID_M 0x0000fffc 2503 #define HTT_TX_TCL_METADATA_PEER_ID_S 2 2504 2505 #define HTT_TX_TCL_METADATA_TYPE_GET(_var) \ 2506 (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \ 2507 HTT_TX_TCL_METADATA_TYPE_S) 2508 #define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \ 2509 do { \ 2510 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val); \ 2511 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S)); \ 2512 } while (0) 2513 2514 #define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \ 2515 (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \ 2516 HTT_TX_TCL_METADATA_VALID_HTT_S) 2517 #define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \ 2518 do { \ 2519 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val); \ 2520 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S)); \ 2521 } while (0) 2522 2523 #define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \ 2524 (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \ 2525 HTT_TX_TCL_METADATA_VDEV_ID_S) 2526 #define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \ 2527 do { \ 2528 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val); \ 2529 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S)); \ 2530 } while (0) 2531 2532 #define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \ 2533 (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \ 2534 HTT_TX_TCL_METADATA_PDEV_ID_S) 2535 #define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \ 2536 do { \ 2537 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val); \ 2538 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S)); \ 2539 } while (0) 2540 2541 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_GET(_var) \ 2542 (((_var) & HTT_TX_TCL_METADATA_HOST_INSPECTED_M) >> \ 2543 HTT_TX_TCL_METADATA_HOST_INSPECTED_S) 2544 #define HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \ 2545 do { \ 2546 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_HOST_INSPECTED, _val); \ 2547 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_HOST_INSPECTED_S)); \ 2548 } while (0) 2549 2550 #define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \ 2551 (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \ 2552 HTT_TX_TCL_METADATA_PEER_ID_S) 2553 #define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \ 2554 do { \ 2555 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val); \ 2556 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S)); \ 2557 } while (0) 2558 2559 /*------------------------------------------------------------------ 2560 * V2 Version of TCL Data Command 2561 * V2 Version to support peer_id, vdev_id, svc_class_id and 2562 * MLO global_seq all flavours of TCL Data Cmd. 2563 *-----------------------------------------------------------------*/ 2564 2565 typedef enum { 2566 HTT_TCL_METADATA_V2_TYPE_PEER_BASED = 0, 2567 HTT_TCL_METADATA_V2_TYPE_VDEV_BASED = 1, 2568 HTT_TCL_METADATA_V2_TYPE_SVC_ID_BASED = 2, 2569 HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED = 3, 2570 } htt_tcl_metadata_type_v2; 2571 2572 /** 2573 * @brief HTT TCL command number format 2574 * @details 2575 * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and 2576 * available to firmware as tcl_exit_base->tcl_status_number. 2577 * A_UINT32 is used to avoid endianness conversion problems. 2578 * tcl_status_number size is 16 bits, hence only 16 bits can be used. 2579 */ 2580 typedef struct { 2581 A_UINT32 2582 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2583 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2584 vdev_id: 8, 2585 pdev_id: 2, 2586 host_inspected:1, 2587 rsvd: 2, 2588 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2589 } htt_tx_tcl_vdev_metadata_v2; 2590 2591 typedef struct { 2592 A_UINT32 2593 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2594 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2595 peer_id: 13, 2596 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2597 } htt_tx_tcl_peer_metadata_v2; 2598 2599 typedef struct { 2600 A_UINT32 2601 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2602 valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ 2603 svc_class_id: 8, 2604 ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ 2605 rsvd: 2, 2606 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2607 } htt_tx_tcl_svc_class_id_metadata; 2608 2609 typedef struct { 2610 A_UINT32 2611 type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ 2612 host_inspected: 1, 2613 global_seq_no: 12, 2614 rsvd: 1, 2615 padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ 2616 } htt_tx_tcl_global_seq_metadata; 2617 2618 PREPACK struct htt_tx_tcl_metadata_v2 { 2619 union { 2620 htt_tx_tcl_vdev_metadata_v2 vdev_meta_v2; 2621 htt_tx_tcl_peer_metadata_v2 peer_meta_v2; 2622 htt_tx_tcl_svc_class_id_metadata svc_class_id_meta; 2623 htt_tx_tcl_global_seq_metadata global_seq_meta; 2624 }; 2625 } POSTPACK; 2626 2627 /* DWORD 0 */ 2628 #define HTT_TX_TCL_METADATA_TYPE_V2_M 0x00000003 2629 #define HTT_TX_TCL_METADATA_TYPE_V2_S 0 2630 2631 /* Valid htt ext for V2 tcl data cmd used by VDEV, PEER and SVC_ID meta */ 2632 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M 0x00000004 2633 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S 2 2634 2635 /* VDEV V2 metadata */ 2636 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_M 0x000007f8 2637 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_S 3 2638 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_M 0x00001800 2639 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_S 11 2640 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M 0x00002000 2641 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S 13 2642 2643 /* PEER V2 metadata */ 2644 #define HTT_TX_TCL_METADATA_V2_PEER_ID_M 0x0000fff8 2645 #define HTT_TX_TCL_METADATA_V2_PEER_ID_S 3 2646 2647 /* SVC_CLASS_ID metadata */ 2648 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_M 0x000007f8 2649 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_S 3 2650 2651 /* Global Seq no metadata */ 2652 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M 0x00000004 2653 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S 2 2654 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M 0x00007ff8 2655 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S 3 2656 2657 2658 /*----- Get and Set V2 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */ 2659 #define HTT_TX_TCL_METADATA_TYPE_V2_GET(_var) \ 2660 (((_var) & HTT_TX_TCL_METADATA_TYPE_V2_M) >> \ 2661 HTT_TX_TCL_METADATA_TYPE_V2_S) 2662 #define HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val) \ 2663 do { \ 2664 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V2, _val); \ 2665 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V2_S)); \ 2666 } while (0) 2667 2668 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_GET(_var) \ 2669 (((_var) & HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M) >> \ 2670 HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S) 2671 #define HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val) \ 2672 do { \ 2673 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID, _val); \ 2674 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S)); \ 2675 } while (0) 2676 2677 /*----- Get and Set V2 type field in Vdev meta fields ----*/ 2678 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_GET(_var) \ 2679 (((_var) & HTT_TX_TCL_METADATA_V2_VDEV_ID_M) >> \ 2680 HTT_TX_TCL_METADATA_V2_VDEV_ID_S) 2681 #define HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val) \ 2682 do { \ 2683 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VDEV_ID, _val); \ 2684 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VDEV_ID_S)); \ 2685 } while (0) 2686 2687 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_GET(_var) \ 2688 (((_var) & HTT_TX_TCL_METADATA_V2_PDEV_ID_M) >> \ 2689 HTT_TX_TCL_METADATA_V2_PDEV_ID_S) 2690 #define HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val) \ 2691 do { \ 2692 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PDEV_ID, _val); \ 2693 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PDEV_ID_S)); \ 2694 } while (0) 2695 2696 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_GET(_var) \ 2697 (((_var) & HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M) >> \ 2698 HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S) 2699 #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val) \ 2700 do { \ 2701 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_HOST_INSPECTED, _val); \ 2702 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S)); \ 2703 } while (0) 2704 2705 /*----- Get and Set V2 type field in Peer meta fields ----*/ 2706 #define HTT_TX_TCL_METADATA_V2_PEER_ID_GET(_var) \ 2707 (((_var) & HTT_TX_TCL_METADATA_V2_PEER_ID_M) >> \ 2708 HTT_TX_TCL_METADATA_V2_PEER_ID_S) 2709 #define HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val) \ 2710 do { \ 2711 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PEER_ID, _val); \ 2712 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PEER_ID_S)); \ 2713 } while (0) 2714 2715 /*----- Get and Set V2 type field in Service Class fields ----*/ 2716 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_GET(_var) \ 2717 (((_var) & HTT_TX_TCL_METADATA_SVC_CLASS_ID_M) >> \ 2718 HTT_TX_TCL_METADATA_SVC_CLASS_ID_S) 2719 #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_SET(_var, _val) \ 2720 do { \ 2721 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_SVC_CLASS_ID, _val); \ 2722 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_SVC_CLASS_ID_S)); \ 2723 } while (0) 2724 2725 /*----- Get and Set V2 type field in Global sequence fields ----*/ 2726 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_GET(_var) \ 2727 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M) >> \ 2728 HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S) 2729 #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \ 2730 do { \ 2731 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED, _val); \ 2732 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S)); \ 2733 } while (0) 2734 2735 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_GET(_var) \ 2736 (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M) >> \ 2737 HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S) 2738 #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(_var, _val) \ 2739 do { \ 2740 HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_NO, _val); \ 2741 ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S)); \ 2742 } while (0) 2743 2744 /*------------------------------------------------------------------ 2745 * End V2 Version of TCL Data Command 2746 *-----------------------------------------------------------------*/ 2747 2748 typedef enum { 2749 HTT_TX_FW2WBM_TX_STATUS_OK, 2750 HTT_TX_FW2WBM_TX_STATUS_DROP, 2751 HTT_TX_FW2WBM_TX_STATUS_TTL, 2752 HTT_TX_FW2WBM_TX_STATUS_REINJECT, 2753 HTT_TX_FW2WBM_TX_STATUS_INSPECT, 2754 HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, 2755 HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH, 2756 2757 HTT_TX_FW2WBM_TX_STATUS_MAX 2758 } htt_tx_fw2wbm_tx_status_t; 2759 2760 typedef enum { 2761 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, /* deprecated */ 2762 HTT_TX_FW2WBM_REINJECT_REASON_RAW_ENCAP_EXP /* current */ = 2763 HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, 2764 HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP, 2765 HTT_TX_FW2WBM_REINJECT_REASON_MCAST, 2766 HTT_TX_FW2WBM_REINJECT_REASON_ARP, 2767 HTT_TX_FW2WBM_REINJECT_REASON_DHCP, 2768 HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL, 2769 HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST, 2770 2771 HTT_TX_FW2WBM_REINJECT_REASON_MAX, 2772 } htt_tx_fw2wbm_reinject_reason_t; 2773 2774 /** 2775 * @brief HTT TX WBM Completion from firmware to host 2776 * @details 2777 * This structure is passed from firmware to host overlaid on wbm_release_ring 2778 * DWORD 3 and 4 for software based completions (Exception frames and 2779 * TQM bypass frames) 2780 * For software based completions, wbm_release_ring->release_source_module will 2781 * be set to release_source_fw 2782 */ 2783 PREPACK struct htt_tx_wbm_completion { 2784 A_UINT32 2785 sch_cmd_id: 24, 2786 exception_frame: 1, /* If set, this packet was queued via exception path */ 2787 rsvd0_31_25: 7; 2788 2789 A_UINT32 2790 ack_frame_rssi: 8, /* If this frame is removed as the result of the 2791 * reception of an ACK or BA, this field indicates 2792 * the RSSI of the received ACK or BA frame. 2793 * When the frame is removed as result of a direct 2794 * remove command from the SW, this field is set 2795 * to 0x0 (which is never a valid value when real 2796 * RSSI is available). 2797 * Units: dB w.r.t noise floor 2798 */ 2799 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2800 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2801 rsvd1_31_16: 16; 2802 } POSTPACK; 2803 2804 /* DWORD 0 */ 2805 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M 0x00ffffff 2806 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S 0 2807 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_M 0x01000000 2808 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_S 24 2809 2810 /* DWORD 1 */ 2811 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_M 0x000000ff 2812 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_S 0 2813 #define HTT_TX_WBM_COMPLETION_TX_STATUS_M 0x00000f00 2814 #define HTT_TX_WBM_COMPLETION_TX_STATUS_S 8 2815 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_M 0x0000f000 2816 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_S 12 2817 2818 /* DWORD 0 */ 2819 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \ 2820 (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \ 2821 HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S) 2822 #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \ 2823 do { \ 2824 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val); \ 2825 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)); \ 2826 } while (0) 2827 2828 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \ 2829 (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \ 2830 HTT_TX_WBM_COMPLETION_EXP_FRAME_S) 2831 #define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \ 2832 do { \ 2833 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val); \ 2834 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S)); \ 2835 } while (0) 2836 2837 /* DWORD 1 */ 2838 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \ 2839 (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \ 2840 HTT_TX_WBM_COMPLETION_ACK_RSSI_S) 2841 #define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \ 2842 do { \ 2843 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val); \ 2844 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S)); \ 2845 } while (0) 2846 2847 #define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \ 2848 (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \ 2849 HTT_TX_WBM_COMPLETION_TX_STATUS_S) 2850 #define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \ 2851 do { \ 2852 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val); \ 2853 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S)); \ 2854 } while (0) 2855 2856 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \ 2857 (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \ 2858 HTT_TX_WBM_COMPLETION_REINJECT_REASON_S) 2859 #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \ 2860 do { \ 2861 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val); \ 2862 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \ 2863 } while (0) 2864 2865 /** 2866 * @brief HTT TX WBM Completion from firmware to host 2867 * @details 2868 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 2869 * (WBM) offload HW. 2870 * This structure is passed from firmware to host overlaid on wbm_release_ring 2871 * For software based completions, release_source_module will 2872 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 2873 * struct wbm_release_ring and then switch to this after looking at 2874 * release_source_module. 2875 */ 2876 PREPACK struct htt_tx_wbm_completion_v2 { 2877 A_UINT32 2878 used_by_hw0; /* Refer to struct wbm_release_ring */ 2879 A_UINT32 2880 used_by_hw1; /* Refer to struct wbm_release_ring */ 2881 A_UINT32 2882 used_by_hw2: 9, /* Refer to struct wbm_release_ring */ 2883 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2884 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2885 exception_frame: 1, 2886 transmit_count: 7, /* Refer to struct wbm_release_ring */ 2887 rsvd0: 5, /* For future use */ 2888 used_by_hw4: 1, /* wbm_internal_error bit being used by HW */ 2889 rsvd1: 1; /* For future use */ 2890 A_UINT32 2891 data0: 32; /* data0,1 and 2 changes based on tx_status type 2892 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 2893 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 2894 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 2895 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 2896 */ 2897 A_UINT32 2898 data1: 32; 2899 A_UINT32 2900 data2: 32; 2901 A_UINT32 2902 used_by_hw3; /* Refer to struct wbm_release_ring */ 2903 } POSTPACK; 2904 2905 /* DWORD 1, 2 and part of 3 are accessed via HW header files */ 2906 /* DWORD 3 */ 2907 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M 0x00001e00 2908 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S 9 2909 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M 0x0001e000 2910 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13 2911 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000 2912 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17 2913 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000 2914 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18 2915 2916 /* DWORD 3 */ 2917 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \ 2918 (((_var) & HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M) >> \ 2919 HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S) 2920 2921 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_SET(_var, _val) \ 2922 do { \ 2923 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TX_STATUS, _val); \ 2924 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S)); \ 2925 } while (0) 2926 2927 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(_var) \ 2928 (((_var) & HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M) >> \ 2929 HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S) 2930 2931 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_SET(_var, _val) \ 2932 do { \ 2933 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON, _val); \ 2934 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S)); \ 2935 } while (0) 2936 2937 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_GET(_var) \ 2938 (((_var) & HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M) >> \ 2939 HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S) 2940 2941 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_SET(_var, _val) \ 2942 do { \ 2943 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_EXP_FRAME, _val); \ 2944 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \ 2945 } while (0) 2946 2947 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \ 2948 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \ 2949 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S) 2950 2951 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \ 2952 do { \ 2953 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \ 2954 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \ 2955 } while (0) 2956 2957 /** 2958 * @brief HTT TX WBM Completion from firmware to host (V3) 2959 * @details 2960 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 2961 * (WBM) offload HW. 2962 * This structure is passed from firmware to host overlaid on wbm_release_ring 2963 * For software based completions, release_source_module will 2964 * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using 2965 * struct wbm_release_ring and then switch to this after looking at 2966 * release_source_module. 2967 * Due to overlap with WBM block, htt_tx_wbm_completion_v3 will be used 2968 * by new generations of targets. 2969 */ 2970 PREPACK struct htt_tx_wbm_completion_v3 { 2971 A_UINT32 2972 used_by_hw0; /* Refer to struct wbm_release_ring */ 2973 A_UINT32 2974 used_by_hw1; /* Refer to struct wbm_release_ring */ 2975 A_UINT32 2976 used_by_hw2: 13, /* Refer to struct wbm_release_ring */ 2977 tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ 2978 used_by_hw3: 15; 2979 A_UINT32 2980 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ 2981 exception_frame: 1, 2982 transmit_count: 7, /* Refer to struct wbm_release_ring */ 2983 rsvd0: 20; /* For future use */ 2984 A_UINT32 2985 data0: 32; /* data0,1 and 2 changes based on tx_status type 2986 * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 2987 * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used. 2988 * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used. 2989 * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used. 2990 */ 2991 A_UINT32 2992 data1: 32; 2993 A_UINT32 2994 data2: 32; 2995 A_UINT32 2996 rsvd1: 20, 2997 used_by_hw4: 12; /* Refer to struct wbm_release_ring */ 2998 } POSTPACK; 2999 3000 /* DWORD 3 */ 3001 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000 3002 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13 3003 3004 /* DWORD 4 */ 3005 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F 3006 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0 3007 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010 3008 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4 3009 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0 3010 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5 3011 3012 3013 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \ 3014 (((_var) & HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M) >> \ 3015 HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S) 3016 3017 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_SET(_var, _val) \ 3018 do { \ 3019 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TX_STATUS, _val); \ 3020 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)); \ 3021 } while (0) 3022 3023 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(_var) \ 3024 (((_var) & HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M) >> \ 3025 HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S) 3026 3027 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_SET(_var, _val) \ 3028 do { \ 3029 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON, _val); \ 3030 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)); \ 3031 } while (0) 3032 3033 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_GET(_var) \ 3034 (((_var) & HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M) >> \ 3035 HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S) 3036 3037 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_SET(_var, _val) \ 3038 do { \ 3039 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_EXP_FRAME, _val); \ 3040 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \ 3041 } while (0) 3042 3043 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \ 3044 (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \ 3045 HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S) 3046 3047 #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \ 3048 do { \ 3049 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \ 3050 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \ 3051 } while (0) 3052 3053 3054 typedef enum { 3055 TX_FRAME_TYPE_UNDEFINED = 0, 3056 TX_FRAME_TYPE_EAPOL = 1, 3057 } htt_tx_wbm_status_frame_type; 3058 3059 /** 3060 * @brief HTT TX WBM transmit status from firmware to host 3061 * @details 3062 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3063 * (WBM) offload HW. 3064 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3065 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP 3066 * or HTT_TX_FW2WBM_TX_STATUS_TTL 3067 */ 3068 PREPACK struct htt_tx_wbm_transmit_status { 3069 A_UINT32 3070 sch_cmd_id: 24, 3071 ack_frame_rssi: 8; /* If this frame is removed as the result of the 3072 * reception of an ACK or BA, this field indicates 3073 * the RSSI of the received ACK or BA frame. 3074 * When the frame is removed as result of a direct 3075 * remove command from the SW, this field is set 3076 * to 0x0 (which is never a valid value when real 3077 * RSSI is available). 3078 * Units: dB w.r.t noise floor 3079 */ 3080 A_UINT32 3081 sw_peer_id: 16, 3082 tid_num: 5, 3083 valid: 1, /* If this "valid" flag is set, the sw_peer_id 3084 * and tid_num fields contain valid data. 3085 * If this "valid" flag is not set, the 3086 * sw_peer_id and tid_num fields must be ignored. 3087 */ 3088 mcast: 1, 3089 mcast_valid: 1, /* If this "mcast_valid" is set, the mcast field 3090 * contains valid data. 3091 */ 3092 frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */ 3093 transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the 3094 * transmit_count field in struct 3095 * htt_tx_wbm_completion_vx has valid data. 3096 */ 3097 reserved: 3; 3098 A_UINT32 3099 ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast 3100 * packets in the wbm completion path 3101 */ 3102 } POSTPACK; 3103 3104 /* DWORD 4 */ 3105 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M 0x00ffffff 3106 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S 0 3107 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M 0xff000000 3108 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S 24 3109 3110 /* DWORD 5 */ 3111 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M 0x0000ffff 3112 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S 0 3113 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_M 0x001f0000 3114 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_S 16 3115 #define HTT_TX_WBM_COMPLETION_V2_VALID_M 0x00200000 3116 #define HTT_TX_WBM_COMPLETION_V2_VALID_S 21 3117 #define HTT_TX_WBM_COMPLETION_V2_MCAST_M 0x00400000 3118 #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22 3119 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000 3120 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23 3121 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000 3122 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24 3123 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000 3124 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28 3125 3126 /* DWORD 4 */ 3127 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \ 3128 (((_var) & HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M) >> \ 3129 HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S) 3130 3131 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_SET(_var, _val) \ 3132 do { \ 3133 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID, _val); \ 3134 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S)); \ 3135 } while (0) 3136 3137 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var) \ 3138 (((_var) & HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M) >> \ 3139 HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S) 3140 3141 #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_SET(_var, _val) \ 3142 do { \ 3143 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI, _val); \ 3144 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)); \ 3145 } while (0) 3146 3147 /* DWORD 5 */ 3148 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var) \ 3149 (((_var) & HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M) >> \ 3150 HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S) 3151 3152 #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_SET(_var, _val) \ 3153 do { \ 3154 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID, _val); \ 3155 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)); \ 3156 } while (0) 3157 3158 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var) \ 3159 (((_var) & HTT_TX_WBM_COMPLETION_V2_TID_NUM_M) >> \ 3160 HTT_TX_WBM_COMPLETION_V2_TID_NUM_S) 3161 3162 #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_SET(_var, _val) \ 3163 do { \ 3164 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TID_NUM, _val); \ 3165 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)); \ 3166 } while (0) 3167 3168 #define HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var) \ 3169 (((_var) & HTT_TX_WBM_COMPLETION_V2_VALID_M) >> \ 3170 HTT_TX_WBM_COMPLETION_V2_VALID_S) 3171 3172 #define HTT_TX_WBM_COMPLETION_V2_VALID_SET(_var, _val) \ 3173 do { \ 3174 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VALID, _val); \ 3175 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VALID_S)); \ 3176 } while (0) 3177 3178 #define HTT_TX_WBM_COMPLETION_V2_MCAST_GET(_var) \ 3179 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_M) >> \ 3180 HTT_TX_WBM_COMPLETION_V2_MCAST_S) 3181 3182 #define HTT_TX_WBM_COMPLETION_V2_MCAST_SET(_var, _val) \ 3183 do { \ 3184 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST, _val); \ 3185 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_S)); \ 3186 } while (0) 3187 3188 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_GET(_var) \ 3189 (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M) >> \ 3190 HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S) 3191 3192 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_SET(_var, _val) \ 3193 do { \ 3194 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3195 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \ 3196 } while (0) 3197 3198 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \ 3199 (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \ 3200 HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S) 3201 3202 #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \ 3203 do { \ 3204 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \ 3205 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \ 3206 3207 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \ 3208 (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \ 3209 HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S) 3210 3211 #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \ 3212 do { \ 3213 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ 3214 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \ 3215 } while (0) 3216 3217 3218 /** 3219 * @brief HTT TX WBM reinject status from firmware to host 3220 * @details 3221 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3222 * (WBM) offload HW. 3223 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3224 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT. 3225 */ 3226 PREPACK struct htt_tx_wbm_reinject_status { 3227 A_UINT32 3228 reserved0: 32; 3229 A_UINT32 3230 reserved1: 32; 3231 A_UINT32 3232 reserved2: 32; 3233 } POSTPACK; 3234 3235 /** 3236 * @brief HTT TX WBM multicast echo check notification from firmware to host 3237 * @details 3238 * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt 3239 * (WBM) offload HW. 3240 * This structure is passed from firmware to host overlaid on wbm_release_ring. 3241 * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY. 3242 * FW sends SA addresses to host for all multicast/broadcast packets received on 3243 * STA side. 3244 */ 3245 PREPACK struct htt_tx_wbm_mec_addr_notify { 3246 A_UINT32 3247 mec_sa_addr_31_0; 3248 A_UINT32 3249 mec_sa_addr_47_32: 16, 3250 sa_ast_index: 16; 3251 A_UINT32 3252 vdev_id: 8, 3253 reserved0: 24; 3254 3255 } POSTPACK; 3256 3257 /* DWORD 4 - mec_sa_addr_31_0 */ 3258 /* DWORD 5 */ 3259 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M 0x0000ffff 3260 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S 0 3261 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M 0xffff0000 3262 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S 16 3263 3264 /* DWORD 6 */ 3265 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M 0x000000ff 3266 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S 0 3267 3268 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_GET(_var) \ 3269 (((_var) & HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M) >> \ 3270 HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S) 3271 3272 #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_SET(_var, _val) \ 3273 do { \ 3274 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32, _val); \ 3275 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S)); \ 3276 } while (0) 3277 3278 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_GET(_var) \ 3279 (((_var) & HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M) >> \ 3280 HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S) 3281 3282 #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_SET(_var, _val) \ 3283 do { \ 3284 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX, _val); \ 3285 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S)); \ 3286 } while (0) 3287 3288 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var) \ 3289 (((_var) & HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M) >> \ 3290 HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S) 3291 3292 #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_SET(_var, _val) \ 3293 do { \ 3294 HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VDEV_ID, _val); \ 3295 ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S)); \ 3296 } while (0) 3297 3298 typedef enum { 3299 TX_FLOW_PRIORITY_BE, 3300 TX_FLOW_PRIORITY_HIGH, 3301 TX_FLOW_PRIORITY_LOW, 3302 } htt_tx_flow_priority_t; 3303 3304 typedef enum { 3305 TX_FLOW_LATENCY_SENSITIVE, 3306 TX_FLOW_LATENCY_INSENSITIVE, 3307 } htt_tx_flow_latency_t; 3308 3309 typedef enum { 3310 TX_FLOW_BEST_EFFORT_TRAFFIC, 3311 TX_FLOW_INTERACTIVE_TRAFFIC, 3312 TX_FLOW_PERIODIC_TRAFFIC, 3313 TX_FLOW_BURSTY_TRAFFIC, 3314 TX_FLOW_OVER_SUBSCRIBED_TRAFFIC, 3315 } htt_tx_flow_traffic_pattern_t; 3316 3317 /** 3318 * @brief HTT TX Flow search metadata format 3319 * @details 3320 * Host will set this metadata in flow table's flow search entry along with 3321 * to_tqm_if_m0_fw. It indicates to forward the first MSDU to both the 3322 * firmware and TQM ring if the flow search entry wins. 3323 * This metadata is available to firmware in that first MSDU's 3324 * tcl_exit_base->meta_data_fse. Firmware uses this metadata to map a new flow 3325 * to one of the available flows for specific tid and returns the tqm flow 3326 * pointer as part of htt_tx_map_flow_info message. 3327 */ 3328 PREPACK struct htt_tx_flow_metadata { 3329 A_UINT32 3330 rsvd0_1_0: 2, 3331 tid: 4, 3332 priority: 3, /* Takes enum values of htt_tx_flow_priority_t */ 3333 traffic_pattern: 3, /* Takes enum values of htt_tx_flow_traffic_pattern_t */ 3334 tid_override: 1, /* If set, tid field in this struct is the final tid. 3335 * Else choose final tid based on latency, priority. 3336 */ 3337 dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */ 3338 latency_sensitive: 2, /* Takes enum values of htt_tx_flow_latency_t */ 3339 host_flow_identifier: 16; /* Used by host to map flow metadata with flow entry */ 3340 } POSTPACK; 3341 3342 /* DWORD 0 */ 3343 #define HTT_TX_FLOW_METADATA_TID_M 0x0000003c 3344 #define HTT_TX_FLOW_METADATA_TID_S 2 3345 #define HTT_TX_FLOW_METADATA_PRIORITY_M 0x000001c0 3346 #define HTT_TX_FLOW_METADATA_PRIORITY_S 6 3347 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M 0x00000e00 3348 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S 9 3349 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_M 0x00001000 3350 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_S 12 3351 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M 0x00002000 3352 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S 13 3353 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M 0x0000c000 3354 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S 14 3355 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M 0xffff0000 3356 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S 16 3357 3358 /* DWORD 0 */ 3359 #define HTT_TX_FLOW_METADATA_TID_GET(_var) \ 3360 (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \ 3361 HTT_TX_FLOW_METADATA_TID_S) 3362 #define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \ 3363 do { \ 3364 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \ 3365 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \ 3366 } while (0) 3367 3368 #define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \ 3369 (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \ 3370 HTT_TX_FLOW_METADATA_PRIORITY_S) 3371 #define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \ 3372 do { \ 3373 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \ 3374 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S)); \ 3375 } while (0) 3376 3377 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \ 3378 (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \ 3379 HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S) 3380 #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \ 3381 do { \ 3382 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val); \ 3383 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)); \ 3384 } while (0) 3385 3386 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \ 3387 (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \ 3388 HTT_TX_FLOW_METADATA_TID_OVERRIDE_S) 3389 #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \ 3390 do { \ 3391 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val); \ 3392 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)); \ 3393 } while (0) 3394 3395 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \ 3396 (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \ 3397 HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S) 3398 #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \ 3399 do { \ 3400 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val); \ 3401 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)); \ 3402 } while (0) 3403 3404 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \ 3405 (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \ 3406 HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S) 3407 #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \ 3408 do { \ 3409 HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \ 3410 ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S)); \ 3411 } while (0) 3412 3413 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \ 3414 (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \ 3415 HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S) 3416 #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \ 3417 do { \ 3418 HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val); \ 3419 ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)); \ 3420 } while (0) 3421 3422 3423 /** 3424 * @brief host -> target ADD WDS Entry 3425 * 3426 * MSG_TYPE => HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY 3427 * 3428 * @brief host -> target DELETE WDS Entry 3429 * 3430 * MSG_TYPE => HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY 3431 * 3432 * @details 3433 * HTT wds entry from source port learning 3434 * Host will learn wds entries from rx and send this message to firmware 3435 * to enable firmware to configure/delete AST entries for wds clients. 3436 * Firmware creates Source address's AST entry with Transmit MAC's peer_id 3437 * and when SA's entry is deleted, firmware removes this AST entry 3438 * 3439 * The message would appear as follows: 3440 * 3441 * |31 30|29 |17 16|15 8|7 0| 3442 * |----------------+----------------+----------------+----------------| 3443 * | rsvd0 |PDVID| vdev_id | msg_type | 3444 * |-------------------------------------------------------------------| 3445 * | sa_addr_31_0 | 3446 * |-------------------------------------------------------------------| 3447 * | | ta_peer_id | sa_addr_47_32 | 3448 * |-------------------------------------------------------------------| 3449 * Where PDVID = pdev_id 3450 * 3451 * The message is interpreted as follows: 3452 * 3453 * dword0 - b'0:7 - msg_type: This will be set to 3454 * 0xd (HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY) or 3455 * 0xe (HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY) 3456 * 3457 * dword0 - b'8:15 - vdev_id 3458 * 3459 * dword0 - b'16:17 - pdev_id 3460 * 3461 * dword0 - b'18:31 - rsvd10: Reserved for future use 3462 * 3463 * dword1 - b'0:31 - sa_addr_31_0: Lower 32 bits of source mac address 3464 * 3465 * dword2 - b'0:15 - sa_addr_47_32: Upper 16 bits of source mac address 3466 * 3467 * dword2 - b'16:19 - ta_peer_id: peer id of Transmit MAC 3468 */ 3469 3470 PREPACK struct htt_wds_entry { 3471 A_UINT32 3472 msg_type: 8, 3473 vdev_id: 8, 3474 pdev_id: 2, 3475 rsvd0: 14; 3476 A_UINT32 sa_addr_31_0; 3477 A_UINT32 3478 sa_addr_47_32: 16, 3479 ta_peer_id: 14, 3480 rsvd2: 2; 3481 } POSTPACK; 3482 3483 /* DWORD 0 */ 3484 #define HTT_WDS_ENTRY_VDEV_ID_M 0x0000ff00 3485 #define HTT_WDS_ENTRY_VDEV_ID_S 8 3486 #define HTT_WDS_ENTRY_PDEV_ID_M 0x00030000 3487 #define HTT_WDS_ENTRY_PDEV_ID_S 16 3488 3489 /* DWORD 2 */ 3490 #define HTT_WDS_ENTRY_SA_ADDR_47_32_M 0x0000ffff 3491 #define HTT_WDS_ENTRY_SA_ADDR_47_32_S 0 3492 #define HTT_WDS_ENTRY_TA_PEER_ID_M 0x3fff0000 3493 #define HTT_WDS_ENTRY_TA_PEER_ID_S 16 3494 3495 /* DWORD 0 */ 3496 #define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \ 3497 (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \ 3498 HTT_WDS_ENTRY_VDEV_ID_S) 3499 #define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \ 3500 do { \ 3501 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \ 3502 ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \ 3503 } while (0) 3504 3505 #define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \ 3506 (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \ 3507 HTT_WDS_ENTRY_PDEV_ID_S) 3508 #define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \ 3509 do { \ 3510 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \ 3511 ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \ 3512 } while (0) 3513 3514 /* DWORD 2 */ 3515 #define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \ 3516 (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \ 3517 HTT_WDS_ENTRY_SA_ADDR_47_32_S) 3518 #define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \ 3519 do { \ 3520 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \ 3521 ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \ 3522 } while (0) 3523 3524 #define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \ 3525 (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \ 3526 HTT_WDS_ENTRY_TA_PEER_ID_S) 3527 #define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \ 3528 do { \ 3529 HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \ 3530 ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \ 3531 } while (0) 3532 3533 3534 /** 3535 * @brief MAC DMA rx ring setup specification 3536 * 3537 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_CFG 3538 * 3539 * @details 3540 * To allow for dynamic rx ring reconfiguration and to avoid race 3541 * conditions, the host SW never directly programs the MAC DMA rx ring(s) 3542 * it uses. Instead, it sends this message to the target, indicating how 3543 * the rx ring used by the host should be set up and maintained. 3544 * The message consists of a 4-octet header followed by 1 or 2 rx ring setup 3545 * specifications. 3546 * 3547 * |31 16|15 8|7 0| 3548 * |---------------------------------------------------------------| 3549 * header: | reserved | num rings | msg type | 3550 * |---------------------------------------------------------------| 3551 * payload 1: | FW_IDX shadow register physical address (bits 31:0) | 3552 #if HTT_PADDR64 3553 * | FW_IDX shadow register physical address (bits 63:32) | 3554 #endif 3555 * |---------------------------------------------------------------| 3556 * | rx ring base physical address (bits 31:0) | 3557 #if HTT_PADDR64 3558 * | rx ring base physical address (bits 63:32) | 3559 #endif 3560 * |---------------------------------------------------------------| 3561 * | rx ring buffer size | rx ring length | 3562 * |---------------------------------------------------------------| 3563 * | FW_IDX initial value | enabled flags | 3564 * |---------------------------------------------------------------| 3565 * | MSDU payload offset | 802.11 header offset | 3566 * |---------------------------------------------------------------| 3567 * | PPDU end offset | PPDU start offset | 3568 * |---------------------------------------------------------------| 3569 * | MPDU end offset | MPDU start offset | 3570 * |---------------------------------------------------------------| 3571 * | MSDU end offset | MSDU start offset | 3572 * |---------------------------------------------------------------| 3573 * | frag info offset | rx attention offset | 3574 * |---------------------------------------------------------------| 3575 * payload 2, if present, has the same format as payload 1 3576 * Header fields: 3577 * - MSG_TYPE 3578 * Bits 7:0 3579 * Purpose: identifies this as an rx ring configuration message 3580 * Value: 0x2 (HTT_H2T_MSG_TYPE_RX_RING_CFG) 3581 * - NUM_RINGS 3582 * Bits 15:8 3583 * Purpose: indicates whether the host is setting up one rx ring or two 3584 * Value: 1 or 2 3585 * Payload: 3586 * for systems using 64-bit format for bus addresses: 3587 * - IDX_SHADOW_REG_PADDR_LO 3588 * Bits 31:0 3589 * Value: lower 4 bytes of physical address of the host's 3590 * FW_IDX shadow register 3591 * - IDX_SHADOW_REG_PADDR_HI 3592 * Bits 31:0 3593 * Value: upper 4 bytes of physical address of the host's 3594 * FW_IDX shadow register 3595 * - RING_BASE_PADDR_LO 3596 * Bits 31:0 3597 * Value: lower 4 bytes of physical address of the host's rx ring 3598 * - RING_BASE_PADDR_HI 3599 * Bits 31:0 3600 * Value: uppper 4 bytes of physical address of the host's rx ring 3601 * for systems using 32-bit format for bus addresses: 3602 * - IDX_SHADOW_REG_PADDR 3603 * Bits 31:0 3604 * Value: physical address of the host's FW_IDX shadow register 3605 * - RING_BASE_PADDR 3606 * Bits 31:0 3607 * Value: physical address of the host's rx ring 3608 * - RING_LEN 3609 * Bits 15:0 3610 * Value: number of elements in the rx ring 3611 * - RING_BUF_SZ 3612 * Bits 31:16 3613 * Value: size of the buffers referenced by the rx ring, in byte units 3614 * - ENABLED_FLAGS 3615 * Bits 15:0 3616 * Value: 1-bit flags to show whether different rx fields are enabled 3617 * bit 0: 802.11 header enabled (1) or disabled (0) 3618 * bit 1: MSDU payload enabled (1) or disabled (0) 3619 * bit 2: PPDU start enabled (1) or disabled (0) 3620 * bit 3: PPDU end enabled (1) or disabled (0) 3621 * bit 4: MPDU start enabled (1) or disabled (0) 3622 * bit 5: MPDU end enabled (1) or disabled (0) 3623 * bit 6: MSDU start enabled (1) or disabled (0) 3624 * bit 7: MSDU end enabled (1) or disabled (0) 3625 * bit 8: rx attention enabled (1) or disabled (0) 3626 * bit 9: frag info enabled (1) or disabled (0) 3627 * bit 10: unicast rx enabled (1) or disabled (0) 3628 * bit 11: multicast rx enabled (1) or disabled (0) 3629 * bit 12: ctrl rx enabled (1) or disabled (0) 3630 * bit 13: mgmt rx enabled (1) or disabled (0) 3631 * bit 14: null rx enabled (1) or disabled (0) 3632 * bit 15: phy data rx enabled (1) or disabled (0) 3633 * - IDX_INIT_VAL 3634 * Bits 31:16 3635 * Purpose: Specify the initial value for the FW_IDX. 3636 * Value: the number of buffers initially present in the host's rx ring 3637 * - OFFSET_802_11_HDR 3638 * Bits 15:0 3639 * Value: offset in QUAD-bytes of 802.11 header from the buffer start 3640 * - OFFSET_MSDU_PAYLOAD 3641 * Bits 31:16 3642 * Value: offset in QUAD-bytes of MSDU payload from the buffer start 3643 * - OFFSET_PPDU_START 3644 * Bits 15:0 3645 * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start 3646 * - OFFSET_PPDU_END 3647 * Bits 31:16 3648 * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start 3649 * - OFFSET_MPDU_START 3650 * Bits 15:0 3651 * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start 3652 * - OFFSET_MPDU_END 3653 * Bits 31:16 3654 * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start 3655 * - OFFSET_MSDU_START 3656 * Bits 15:0 3657 * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start 3658 * - OFFSET_MSDU_END 3659 * Bits 31:16 3660 * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start 3661 * - OFFSET_RX_ATTN 3662 * Bits 15:0 3663 * Value: offset in QUAD-bytes of rx attention word from the buffer start 3664 * - OFFSET_FRAG_INFO 3665 * Bits 31:16 3666 * Value: offset in QUAD-bytes of frag info table 3667 */ 3668 /* header fields */ 3669 #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00 3670 #define HTT_RX_RING_CFG_NUM_RINGS_S 8 3671 3672 /* payload fields */ 3673 /* for systems using a 64-bit format for bus addresses */ 3674 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff 3675 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0 3676 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff 3677 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0 3678 #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff 3679 #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0 3680 #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff 3681 #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0 3682 3683 /* for systems using a 32-bit format for bus addresses */ 3684 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff 3685 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0 3686 #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff 3687 #define HTT_RX_RING_CFG_BASE_PADDR_S 0 3688 3689 #define HTT_RX_RING_CFG_LEN_M 0xffff 3690 #define HTT_RX_RING_CFG_LEN_S 0 3691 #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000 3692 #define HTT_RX_RING_CFG_BUF_SZ_S 16 3693 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1 3694 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0 3695 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2 3696 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1 3697 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4 3698 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2 3699 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8 3700 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3 3701 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10 3702 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4 3703 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20 3704 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5 3705 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40 3706 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6 3707 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80 3708 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7 3709 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100 3710 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8 3711 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200 3712 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9 3713 #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400 3714 #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10 3715 #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800 3716 #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11 3717 #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000 3718 #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12 3719 #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000 3720 #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13 3721 #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000 3722 #define HTT_RX_RING_CFG_ENABLED_NULL_S 14 3723 #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000 3724 #define HTT_RX_RING_CFG_ENABLED_PHY_S 15 3725 #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000 3726 #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16 3727 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff 3728 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0 3729 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000 3730 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16 3731 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff 3732 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0 3733 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000 3734 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16 3735 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff 3736 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0 3737 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000 3738 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16 3739 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff 3740 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0 3741 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000 3742 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16 3743 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff 3744 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0 3745 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000 3746 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16 3747 3748 #define HTT_RX_RING_CFG_HDR_BYTES 4 3749 #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 3750 #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 3751 #if HTT_PADDR64 3752 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 3753 #else 3754 #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 3755 #endif 3756 #define HTT_RX_RING_CFG_BYTES(num_rings) \ 3757 (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) 3758 3759 3760 #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ 3761 (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) 3762 #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ 3763 do { \ 3764 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ 3765 ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ 3766 } while (0) 3767 3768 /* degenerate case for 32-bit fields */ 3769 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) 3770 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ 3771 ((_var) = (_val)) 3772 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) 3773 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ 3774 ((_var) = (_val)) 3775 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) 3776 #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ 3777 ((_var) = (_val)) 3778 3779 /* degenerate case for 32-bit fields */ 3780 #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) 3781 #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) \ 3782 ((_var) = (_val)) 3783 #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) 3784 #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) \ 3785 ((_var) = (_val)) 3786 #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) 3787 #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) \ 3788 ((_var) = (_val)) 3789 3790 #define HTT_RX_RING_CFG_LEN_GET(_var) \ 3791 (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) 3792 #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ 3793 do { \ 3794 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ 3795 ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ 3796 } while (0) 3797 3798 #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ 3799 (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) 3800 #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ 3801 do { \ 3802 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ 3803 ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ 3804 } while (0) 3805 3806 #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ 3807 (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ 3808 HTT_RX_RING_CFG_IDX_INIT_VAL_S) 3809 #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ 3810 do { \ 3811 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ 3812 ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ 3813 } while (0) 3814 3815 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ 3816 (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ 3817 HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) 3818 #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ 3819 do { \ 3820 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ 3821 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ 3822 } while (0) 3823 3824 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ 3825 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ 3826 HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) 3827 #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ 3828 do { \ 3829 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ 3830 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ 3831 } while (0) 3832 3833 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ 3834 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ 3835 HTT_RX_RING_CFG_ENABLED_PPDU_START_S) 3836 #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ 3837 do { \ 3838 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ 3839 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ 3840 } while (0) 3841 3842 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ 3843 (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ 3844 HTT_RX_RING_CFG_ENABLED_PPDU_END_S) 3845 #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ 3846 do { \ 3847 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ 3848 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ 3849 } while (0) 3850 3851 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ 3852 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ 3853 HTT_RX_RING_CFG_ENABLED_MPDU_START_S) 3854 #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ 3855 do { \ 3856 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ 3857 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ 3858 } while (0) 3859 3860 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ 3861 (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ 3862 HTT_RX_RING_CFG_ENABLED_MPDU_END_S) 3863 #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ 3864 do { \ 3865 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ 3866 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ 3867 } while (0) 3868 3869 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ 3870 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ 3871 HTT_RX_RING_CFG_ENABLED_MSDU_START_S) 3872 #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ 3873 do { \ 3874 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ 3875 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ 3876 } while (0) 3877 3878 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ 3879 (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ 3880 HTT_RX_RING_CFG_ENABLED_MSDU_END_S) 3881 #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ 3882 do { \ 3883 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ 3884 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ 3885 } while (0) 3886 3887 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ 3888 (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ 3889 HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) 3890 #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ 3891 do { \ 3892 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ 3893 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ 3894 } while (0) 3895 3896 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ 3897 (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ 3898 HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) 3899 #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ 3900 do { \ 3901 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ 3902 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ 3903 } while (0) 3904 3905 #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ 3906 (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ 3907 HTT_RX_RING_CFG_ENABLED_UCAST_S) 3908 #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ 3909 do { \ 3910 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ 3911 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ 3912 } while (0) 3913 3914 #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ 3915 (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ 3916 HTT_RX_RING_CFG_ENABLED_MCAST_S) 3917 #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ 3918 do { \ 3919 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ 3920 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ 3921 } while (0) 3922 #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ 3923 (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ 3924 HTT_RX_RING_CFG_ENABLED_CTRL_S) 3925 #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ 3926 do { \ 3927 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ 3928 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ 3929 } while (0) 3930 #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ 3931 (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ 3932 HTT_RX_RING_CFG_ENABLED_MGMT_S) 3933 #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ 3934 do { \ 3935 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ 3936 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ 3937 } while (0) 3938 #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ 3939 (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ 3940 HTT_RX_RING_CFG_ENABLED_NULL_S) 3941 #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ 3942 do { \ 3943 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ 3944 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ 3945 } while (0) 3946 #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ 3947 (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ 3948 HTT_RX_RING_CFG_ENABLED_PHY_S) 3949 #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ 3950 do { \ 3951 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ 3952 ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ 3953 } while (0) 3954 3955 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ 3956 (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ 3957 HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) 3958 #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ 3959 do { \ 3960 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ 3961 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ 3962 } while (0) 3963 3964 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ 3965 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ 3966 HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) 3967 #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ 3968 do { \ 3969 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ 3970 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ 3971 } while (0) 3972 3973 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ 3974 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ 3975 HTT_RX_RING_CFG_OFFSET_PPDU_START_S) 3976 #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ 3977 do { \ 3978 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ 3979 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ 3980 } while (0) 3981 3982 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ 3983 (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ 3984 HTT_RX_RING_CFG_OFFSET_PPDU_END_S) 3985 #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ 3986 do { \ 3987 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ 3988 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ 3989 } while (0) 3990 3991 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ 3992 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ 3993 HTT_RX_RING_CFG_OFFSET_MPDU_START_S) 3994 #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ 3995 do { \ 3996 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ 3997 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ 3998 } while (0) 3999 4000 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ 4001 (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ 4002 HTT_RX_RING_CFG_OFFSET_MPDU_END_S) 4003 #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ 4004 do { \ 4005 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ 4006 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ 4007 } while (0) 4008 4009 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ 4010 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ 4011 HTT_RX_RING_CFG_OFFSET_MSDU_START_S) 4012 #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ 4013 do { \ 4014 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ 4015 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ 4016 } while (0) 4017 4018 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ 4019 (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ 4020 HTT_RX_RING_CFG_OFFSET_MSDU_END_S) 4021 #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ 4022 do { \ 4023 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ 4024 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ 4025 } while (0) 4026 4027 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ 4028 (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ 4029 HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) 4030 #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ 4031 do { \ 4032 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ 4033 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ 4034 } while (0) 4035 4036 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ 4037 (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ 4038 HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) 4039 #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ 4040 do { \ 4041 HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ 4042 ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ 4043 } while (0) 4044 4045 /** 4046 * @brief host -> target FW statistics retrieve 4047 * 4048 * MSG_TYPE => HTT_H2T_MSG_TYPE_STATS_REQ 4049 * 4050 * @details 4051 * The following field definitions describe the format of the HTT host 4052 * to target FW stats retrieve message. The message specifies the type of 4053 * stats host wants to retrieve. 4054 * 4055 * |31 24|23 16|15 8|7 0| 4056 * |-----------------------------------------------------------| 4057 * | stats types request bitmask | msg type | 4058 * |-----------------------------------------------------------| 4059 * | stats types reset bitmask | reserved | 4060 * |-----------------------------------------------------------| 4061 * | stats type | config value | 4062 * |-----------------------------------------------------------| 4063 * | cookie LSBs | 4064 * |-----------------------------------------------------------| 4065 * | cookie MSBs | 4066 * |-----------------------------------------------------------| 4067 * Header fields: 4068 * - MSG_TYPE 4069 * Bits 7:0 4070 * Purpose: identifies this is a stats upload request message 4071 * Value: 0x3 (HTT_H2T_MSG_TYPE_STATS_REQ) 4072 * - UPLOAD_TYPES 4073 * Bits 31:8 4074 * Purpose: identifies which types of FW statistics to upload 4075 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4076 * - RESET_TYPES 4077 * Bits 31:8 4078 * Purpose: identifies which types of FW statistics to reset 4079 * Value: mask with bits set in positions defined by htt_dbg_stats_type 4080 * - CFG_VAL 4081 * Bits 23:0 4082 * Purpose: give an opaque configuration value to the specified stats type 4083 * Value: stats-type specific configuration value 4084 * if stats type == tx PPDU log, then CONFIG_VAL has the format: 4085 * bits 7:0 - how many per-MPDU byte counts to include in a record 4086 * bits 15:8 - how many per-MPDU MSDU counts to include in a record 4087 * bits 23:16 - how many per-MSDU byte counts to include in a record 4088 * - CFG_STAT_TYPE 4089 * Bits 31:24 4090 * Purpose: specify which stats type (if any) the config value applies to 4091 * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have 4092 * a valid configuration specification 4093 * - COOKIE_LSBS 4094 * Bits 31:0 4095 * Purpose: Provide a mechanism to match a target->host stats confirmation 4096 * message with its preceding host->target stats request message. 4097 * Value: LSBs of the opaque cookie specified by the host-side requestor 4098 * - COOKIE_MSBS 4099 * Bits 31:0 4100 * Purpose: Provide a mechanism to match a target->host stats confirmation 4101 * message with its preceding host->target stats request message. 4102 * Value: MSBs of the opaque cookie specified by the host-side requestor 4103 */ 4104 4105 #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ 4106 4107 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 4108 4109 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00 4110 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8 4111 4112 #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00 4113 #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8 4114 4115 #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff 4116 #define HTT_H2T_STATS_REQ_CFG_VAL_S 0 4117 4118 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 4119 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 4120 4121 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ 4122 (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ 4123 HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) 4124 #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ 4125 do { \ 4126 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ 4127 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ 4128 } while (0) 4129 4130 #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ 4131 (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ 4132 HTT_H2T_STATS_REQ_RESET_TYPES_S) 4133 #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ 4134 do { \ 4135 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ 4136 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ 4137 } while (0) 4138 4139 #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ 4140 (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ 4141 HTT_H2T_STATS_REQ_CFG_VAL_S) 4142 #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ 4143 do { \ 4144 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ 4145 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ 4146 } while (0) 4147 4148 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ 4149 (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ 4150 HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) 4151 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ 4152 do { \ 4153 HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ 4154 ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ 4155 } while (0) 4156 4157 /** 4158 * @brief host -> target HTT out-of-band sync request 4159 * 4160 * MSG_TYPE => HTT_H2T_MSG_TYPE_SYNC 4161 * 4162 * @details 4163 * The HTT SYNC tells the target to suspend processing of subsequent 4164 * HTT host-to-target messages until some other target agent locally 4165 * informs the target HTT FW that the current sync counter is equal to 4166 * or greater than (in a modulo sense) the sync counter specified in 4167 * the SYNC message. 4168 * This allows other host-target components to synchronize their operation 4169 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 4170 * security key has been downloaded to and activated by the target. 4171 * In the absence of any explicit synchronization counter value 4172 * specification, the target HTT FW will use zero as the default current 4173 * sync value. 4174 * 4175 * |31 24|23 16|15 8|7 0| 4176 * |-----------------------------------------------------------| 4177 * | reserved | sync count | msg type | 4178 * |-----------------------------------------------------------| 4179 * Header fields: 4180 * - MSG_TYPE 4181 * Bits 7:0 4182 * Purpose: identifies this as a sync message 4183 * Value: 0x4 (HTT_H2T_MSG_TYPE_SYNC) 4184 * - SYNC_COUNT 4185 * Bits 15:8 4186 * Purpose: specifies what sync value the HTT FW will wait for from 4187 * an out-of-band specification to resume its operation 4188 * Value: in-band sync counter value to compare against the out-of-band 4189 * counter spec. 4190 * The HTT target FW will suspend its host->target message processing 4191 * as long as 4192 * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128 4193 */ 4194 4195 #define HTT_H2T_SYNC_MSG_SZ 4 4196 4197 #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 4198 #define HTT_H2T_SYNC_COUNT_S 8 4199 4200 #define HTT_H2T_SYNC_COUNT_GET(_var) \ 4201 (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ 4202 HTT_H2T_SYNC_COUNT_S) 4203 #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ 4204 do { \ 4205 HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ 4206 ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ 4207 } while (0) 4208 4209 4210 /** 4211 * @brief host -> target HTT aggregation configuration 4212 * 4213 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG 4214 */ 4215 #define HTT_AGGR_CFG_MSG_SZ 4 4216 4217 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00 4218 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8 4219 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 4220 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 4221 4222 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ 4223 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ 4224 HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) 4225 #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ 4226 do { \ 4227 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ 4228 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ 4229 } while (0) 4230 4231 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4232 (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4233 HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) 4234 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4235 do { \ 4236 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ 4237 ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ 4238 } while (0) 4239 4240 4241 /** 4242 * @brief host -> target HTT configure max amsdu info per vdev 4243 * 4244 * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG_EX 4245 * 4246 * @details 4247 * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev 4248 * 4249 * |31 21|20 16|15 8|7 0| 4250 * |-----------------------------------------------------------| 4251 * | reserved | vdev id | max amsdu | msg type | 4252 * |-----------------------------------------------------------| 4253 * Header fields: 4254 * - MSG_TYPE 4255 * Bits 7:0 4256 * Purpose: identifies this as a aggr cfg ex message 4257 * Value: 0xa (HTT_H2T_MSG_TYPE_AGGR_CFG_EX) 4258 * - MAX_NUM_AMSDU_SUBFRM 4259 * Bits 15:8 4260 * Purpose: max MSDUs per A-MSDU 4261 * - VDEV_ID 4262 * Bits 20:16 4263 * Purpose: ID of the vdev to which this limit is applied 4264 */ 4265 #define HTT_AGGR_CFG_EX_MSG_SZ 4 4266 4267 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00 4268 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8 4269 #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 4270 #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 4271 4272 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ 4273 (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ 4274 HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) 4275 #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ 4276 do { \ 4277 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ 4278 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ 4279 } while (0) 4280 4281 #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ 4282 (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ 4283 HTT_AGGR_CFG_EX_VDEV_ID_S) 4284 #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ 4285 do { \ 4286 HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ 4287 ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ 4288 } while (0) 4289 4290 /** 4291 * @brief HTT WDI_IPA Config Message 4292 * 4293 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_CFG 4294 * 4295 * @details 4296 * The HTT WDI_IPA config message is created/sent by host at driver 4297 * init time. It contains information about data structures used on 4298 * WDI_IPA TX and RX path. 4299 * TX CE ring is used for pushing packet metadata from IPA uC 4300 * to WLAN FW 4301 * TX Completion ring is used for generating TX completions from 4302 * WLAN FW to IPA uC 4303 * RX Indication ring is used for indicating RX packets from FW 4304 * to IPA uC 4305 * RX Ring2 is used as either completion ring or as second 4306 * indication ring. when Ring2 is used as completion ring, IPA uC 4307 * puts completed RX packet meta data to Ring2. when Ring2 is used 4308 * as second indication ring, RX packets for LTE-WLAN aggregation are 4309 * indicated in Ring2, other RX packets (e.g. hotspot related) are 4310 * indicated in RX Indication ring. Please see WDI_IPA specification 4311 * for more details. 4312 * |31 24|23 16|15 8|7 0| 4313 * |----------------+----------------+----------------+----------------| 4314 * | tx pkt pool size | Rsvd | msg_type | 4315 * |-------------------------------------------------------------------| 4316 * | tx comp ring base (bits 31:0) | 4317 #if HTT_PADDR64 4318 * | tx comp ring base (bits 63:32) | 4319 #endif 4320 * |-------------------------------------------------------------------| 4321 * | tx comp ring size | 4322 * |-------------------------------------------------------------------| 4323 * | tx comp WR_IDX physical address (bits 31:0) | 4324 #if HTT_PADDR64 4325 * | tx comp WR_IDX physical address (bits 63:32) | 4326 #endif 4327 * |-------------------------------------------------------------------| 4328 * | tx CE WR_IDX physical address (bits 31:0) | 4329 #if HTT_PADDR64 4330 * | tx CE WR_IDX physical address (bits 63:32) | 4331 #endif 4332 * |-------------------------------------------------------------------| 4333 * | rx indication ring base (bits 31:0) | 4334 #if HTT_PADDR64 4335 * | rx indication ring base (bits 63:32) | 4336 #endif 4337 * |-------------------------------------------------------------------| 4338 * | rx indication ring size | 4339 * |-------------------------------------------------------------------| 4340 * | rx ind RD_IDX physical address (bits 31:0) | 4341 #if HTT_PADDR64 4342 * | rx ind RD_IDX physical address (bits 63:32) | 4343 #endif 4344 * |-------------------------------------------------------------------| 4345 * | rx ind WR_IDX physical address (bits 31:0) | 4346 #if HTT_PADDR64 4347 * | rx ind WR_IDX physical address (bits 63:32) | 4348 #endif 4349 * |-------------------------------------------------------------------| 4350 * |-------------------------------------------------------------------| 4351 * | rx ring2 base (bits 31:0) | 4352 #if HTT_PADDR64 4353 * | rx ring2 base (bits 63:32) | 4354 #endif 4355 * |-------------------------------------------------------------------| 4356 * | rx ring2 size | 4357 * |-------------------------------------------------------------------| 4358 * | rx ring2 RD_IDX physical address (bits 31:0) | 4359 #if HTT_PADDR64 4360 * | rx ring2 RD_IDX physical address (bits 63:32) | 4361 #endif 4362 * |-------------------------------------------------------------------| 4363 * | rx ring2 WR_IDX physical address (bits 31:0) | 4364 #if HTT_PADDR64 4365 * | rx ring2 WR_IDX physical address (bits 63:32) | 4366 #endif 4367 * |-------------------------------------------------------------------| 4368 * 4369 * Header fields: 4370 * Header fields: 4371 * - MSG_TYPE 4372 * Bits 7:0 4373 * Purpose: Identifies this as WDI_IPA config message 4374 * value: = 0x8 (HTT_H2T_MSG_TYPE_WDI_IPA_CFG) 4375 * - TX_PKT_POOL_SIZE 4376 * Bits 15:0 4377 * Purpose: Total number of TX packet buffer pool allocated by Host for 4378 * WDI_IPA TX path 4379 * For systems using 32-bit format for bus addresses: 4380 * - TX_COMP_RING_BASE_ADDR 4381 * Bits 31:0 4382 * Purpose: TX Completion Ring base address in DDR 4383 * - TX_COMP_RING_SIZE 4384 * Bits 31:0 4385 * Purpose: TX Completion Ring size (must be power of 2) 4386 * - TX_COMP_WR_IDX_ADDR 4387 * Bits 31:0 4388 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4389 * updates the Write Index for WDI_IPA TX completion ring 4390 * - TX_CE_WR_IDX_ADDR 4391 * Bits 31:0 4392 * Purpose: DDR address where IPA uC 4393 * updates the WR Index for TX CE ring 4394 * (needed for fusion platforms) 4395 * - RX_IND_RING_BASE_ADDR 4396 * Bits 31:0 4397 * Purpose: RX Indication Ring base address in DDR 4398 * - RX_IND_RING_SIZE 4399 * Bits 31:0 4400 * Purpose: RX Indication Ring size 4401 * - RX_IND_RD_IDX_ADDR 4402 * Bits 31:0 4403 * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA 4404 * RX indication ring 4405 * - RX_IND_WR_IDX_ADDR 4406 * Bits 31:0 4407 * Purpose: IPA doorbell register address OR DDR address where WIFI FW 4408 * updates the Write Index for WDI_IPA RX indication ring 4409 * - RX_RING2_BASE_ADDR 4410 * Bits 31:0 4411 * Purpose: Second RX Ring(Indication or completion)base address in DDR 4412 * - RX_RING2_SIZE 4413 * Bits 31:0 4414 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4415 * - RX_RING2_RD_IDX_ADDR 4416 * Bits 31:0 4417 * Purpose: If Second RX ring is Indication ring, DDR address where 4418 * IPA uC updates the Read Index for Ring2. 4419 * If Second RX ring is completion ring, this is NOT used 4420 * - RX_RING2_WR_IDX_ADDR 4421 * Bits 31:0 4422 * Purpose: If Second RX ring is Indication ring, DDR address where 4423 * WIFI FW updates the Write Index for WDI_IPA RX ring2 4424 * If second RX ring is completion ring, DDR address where 4425 * IPA uC updates the Write Index for Ring 2. 4426 * For systems using 64-bit format for bus addresses: 4427 * - TX_COMP_RING_BASE_ADDR_LO 4428 * Bits 31:0 4429 * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR 4430 * - TX_COMP_RING_BASE_ADDR_HI 4431 * Bits 31:0 4432 * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR 4433 * - TX_COMP_RING_SIZE 4434 * Bits 31:0 4435 * Purpose: TX Completion Ring size (must be power of 2) 4436 * - TX_COMP_WR_IDX_ADDR_LO 4437 * Bits 31:0 4438 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4439 * Lower 4 bytes of DDR address where WIFI FW 4440 * updates the Write Index for WDI_IPA TX completion ring 4441 * - TX_COMP_WR_IDX_ADDR_HI 4442 * Bits 31:0 4443 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4444 * Higher 4 bytes of DDR address where WIFI FW 4445 * updates the Write Index for WDI_IPA TX completion ring 4446 * - TX_CE_WR_IDX_ADDR_LO 4447 * Bits 31:0 4448 * Purpose: Lower 4 bytes of DDR address where IPA uC 4449 * updates the WR Index for TX CE ring 4450 * (needed for fusion platforms) 4451 * - TX_CE_WR_IDX_ADDR_HI 4452 * Bits 31:0 4453 * Purpose: Higher 4 bytes of DDR address where IPA uC 4454 * updates the WR Index for TX CE ring 4455 * (needed for fusion platforms) 4456 * - RX_IND_RING_BASE_ADDR_LO 4457 * Bits 31:0 4458 * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR 4459 * - RX_IND_RING_BASE_ADDR_HI 4460 * Bits 31:0 4461 * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR 4462 * - RX_IND_RING_SIZE 4463 * Bits 31:0 4464 * Purpose: RX Indication Ring size 4465 * - RX_IND_RD_IDX_ADDR_LO 4466 * Bits 31:0 4467 * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index 4468 * for WDI_IPA RX indication ring 4469 * - RX_IND_RD_IDX_ADDR_HI 4470 * Bits 31:0 4471 * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index 4472 * for WDI_IPA RX indication ring 4473 * - RX_IND_WR_IDX_ADDR_LO 4474 * Bits 31:0 4475 * Purpose: Lower 4 bytes of IPA doorbell register address OR 4476 * Lower 4 bytes of DDR address where WIFI FW 4477 * updates the Write Index for WDI_IPA RX indication ring 4478 * - RX_IND_WR_IDX_ADDR_HI 4479 * Bits 31:0 4480 * Purpose: Higher 4 bytes of IPA doorbell register address OR 4481 * Higher 4 bytes of DDR address where WIFI FW 4482 * updates the Write Index for WDI_IPA RX indication ring 4483 * - RX_RING2_BASE_ADDR_LO 4484 * Bits 31:0 4485 * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4486 * - RX_RING2_BASE_ADDR_HI 4487 * Bits 31:0 4488 * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR 4489 * - RX_RING2_SIZE 4490 * Bits 31:0 4491 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) 4492 * - RX_RING2_RD_IDX_ADDR_LO 4493 * Bits 31:0 4494 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4495 * DDR address where IPA uC updates the Read Index for Ring2. 4496 * If Second RX ring is completion ring, this is NOT used 4497 * - RX_RING2_RD_IDX_ADDR_HI 4498 * Bits 31:0 4499 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4500 * DDR address where IPA uC updates the Read Index for Ring2. 4501 * If Second RX ring is completion ring, this is NOT used 4502 * - RX_RING2_WR_IDX_ADDR_LO 4503 * Bits 31:0 4504 * Purpose: If Second RX ring is Indication ring, lower 4 bytes of 4505 * DDR address where WIFI FW updates the Write Index 4506 * for WDI_IPA RX ring2 4507 * If second RX ring is completion ring, lower 4 bytes of 4508 * DDR address where IPA uC updates the Write Index for Ring 2. 4509 * - RX_RING2_WR_IDX_ADDR_HI 4510 * Bits 31:0 4511 * Purpose: If Second RX ring is Indication ring, higher 4 bytes of 4512 * DDR address where WIFI FW updates the Write Index 4513 * for WDI_IPA RX ring2 4514 * If second RX ring is completion ring, higher 4 bytes of 4515 * DDR address where IPA uC updates the Write Index for Ring 2. 4516 */ 4517 4518 #if HTT_PADDR64 4519 #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ 4520 #else 4521 #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ 4522 #endif 4523 4524 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 4525 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16 4526 4527 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff 4528 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0 4529 4530 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff 4531 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0 4532 4533 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff 4534 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0 4535 4536 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff 4537 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0 4538 4539 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff 4540 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0 4541 4542 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff 4543 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0 4544 4545 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff 4546 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0 4547 4548 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff 4549 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0 4550 4551 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff 4552 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0 4553 4554 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff 4555 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0 4556 4557 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff 4558 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0 4559 4560 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff 4561 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0 4562 4563 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff 4564 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0 4565 4566 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff 4567 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0 4568 4569 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff 4570 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0 4571 4572 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff 4573 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0 4574 4575 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff 4576 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0 4577 4578 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff 4579 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0 4580 4581 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff 4582 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0 4583 4584 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff 4585 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0 4586 4587 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff 4588 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0 4589 4590 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff 4591 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0 4592 4593 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff 4594 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0 4595 4596 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff 4597 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0 4598 4599 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff 4600 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0 4601 4602 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff 4603 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0 4604 4605 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff 4606 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0 4607 4608 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff 4609 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0 4610 4611 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff 4612 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0 4613 4614 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff 4615 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 4616 4617 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ 4618 (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) 4619 #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ 4620 do { \ 4621 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ 4622 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ 4623 } while (0) 4624 4625 /* for systems using 32-bit format for bus addr */ 4626 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ 4627 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) 4628 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ 4629 do { \ 4630 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \ 4631 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ 4632 } while (0) 4633 4634 /* for systems using 64-bit format for bus addr */ 4635 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ 4636 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) 4637 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ 4638 do { \ 4639 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \ 4640 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ 4641 } while (0) 4642 4643 /* for systems using 64-bit format for bus addr */ 4644 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ 4645 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) 4646 #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ 4647 do { \ 4648 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ 4649 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ 4650 } while (0) 4651 4652 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ 4653 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) 4654 #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ 4655 do { \ 4656 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ 4657 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ 4658 } while (0) 4659 4660 /* for systems using 32-bit format for bus addr */ 4661 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ 4662 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) 4663 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ 4664 do { \ 4665 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ 4666 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ 4667 } while (0) 4668 4669 /* for systems using 64-bit format for bus addr */ 4670 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ 4671 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) 4672 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ 4673 do { \ 4674 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ 4675 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ 4676 } while (0) 4677 4678 /* for systems using 64-bit format for bus addr */ 4679 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ 4680 (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) 4681 #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ 4682 do { \ 4683 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ 4684 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ 4685 } while (0) 4686 4687 4688 /* for systems using 32-bit format for bus addr */ 4689 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ 4690 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) 4691 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ 4692 do { \ 4693 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ 4694 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ 4695 } while (0) 4696 4697 /* for systems using 64-bit format for bus addr */ 4698 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ 4699 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) 4700 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ 4701 do { \ 4702 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ 4703 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ 4704 } while (0) 4705 4706 /* for systems using 64-bit format for bus addr */ 4707 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ 4708 (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) 4709 #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ 4710 do { \ 4711 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ 4712 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ 4713 } while (0) 4714 4715 /* for systems using 32-bit format for bus addr */ 4716 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ 4717 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) 4718 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ 4719 do { \ 4720 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ 4721 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ 4722 } while (0) 4723 4724 /* for systems using 64-bit format for bus addr */ 4725 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ 4726 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) 4727 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ 4728 do { \ 4729 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ 4730 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ 4731 } while (0) 4732 4733 /* for systems using 64-bit format for bus addr */ 4734 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ 4735 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) 4736 #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ 4737 do { \ 4738 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ 4739 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ 4740 } while (0) 4741 4742 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ 4743 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) 4744 #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ 4745 do { \ 4746 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ 4747 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ 4748 } while (0) 4749 4750 /* for systems using 32-bit format for bus addr */ 4751 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ 4752 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) 4753 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ 4754 do { \ 4755 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ 4756 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ 4757 } while (0) 4758 4759 /* for systems using 64-bit format for bus addr */ 4760 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ 4761 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) 4762 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ 4763 do { \ 4764 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ 4765 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ 4766 } while (0) 4767 4768 /* for systems using 64-bit format for bus addr */ 4769 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ 4770 (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) 4771 #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ 4772 do { \ 4773 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ 4774 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ 4775 } while (0) 4776 4777 /* for systems using 32-bit format for bus addr */ 4778 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ 4779 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) 4780 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ 4781 do { \ 4782 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ 4783 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ 4784 } while (0) 4785 4786 /* for systems using 64-bit format for bus addr */ 4787 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ 4788 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) 4789 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ 4790 do { \ 4791 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ 4792 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ 4793 } while (0) 4794 4795 /* for systems using 64-bit format for bus addr */ 4796 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ 4797 (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) 4798 #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ 4799 do { \ 4800 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ 4801 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ 4802 } while (0) 4803 4804 /* for systems using 32-bit format for bus addr */ 4805 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ 4806 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) 4807 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ 4808 do { \ 4809 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ 4810 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ 4811 } while (0) 4812 4813 /* for systems using 64-bit format for bus addr */ 4814 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ 4815 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) 4816 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ 4817 do { \ 4818 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ 4819 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ 4820 } while (0) 4821 4822 /* for systems using 64-bit format for bus addr */ 4823 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ 4824 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) 4825 #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ 4826 do { \ 4827 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ 4828 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ 4829 } while (0) 4830 4831 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ 4832 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) 4833 #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ 4834 do { \ 4835 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ 4836 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ 4837 } while (0) 4838 4839 /* for systems using 32-bit format for bus addr */ 4840 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ 4841 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) 4842 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ 4843 do { \ 4844 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ 4845 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ 4846 } while (0) 4847 4848 /* for systems using 64-bit format for bus addr */ 4849 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ 4850 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) 4851 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ 4852 do { \ 4853 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ 4854 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ 4855 } while (0) 4856 4857 /* for systems using 64-bit format for bus addr */ 4858 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ 4859 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) 4860 #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ 4861 do { \ 4862 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ 4863 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ 4864 } while (0) 4865 4866 /* for systems using 32-bit format for bus addr */ 4867 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ 4868 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) 4869 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ 4870 do { \ 4871 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ 4872 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ 4873 } while (0) 4874 4875 /* for systems using 64-bit format for bus addr */ 4876 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ 4877 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) 4878 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ 4879 do { \ 4880 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ 4881 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ 4882 } while (0) 4883 4884 /* for systems using 64-bit format for bus addr */ 4885 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ 4886 (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) 4887 #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ 4888 do { \ 4889 HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ 4890 ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ 4891 } while (0) 4892 4893 /* 4894 * TEMPLATE_HTT_WDI_IPA_CONFIG_T: 4895 * This macro defines a htt_wdi_ipa_configXXX_t in which any physical 4896 * addresses are stored in a XXX-bit field. 4897 * This macro is used to define both htt_wdi_ipa_config32_t and 4898 * htt_wdi_ipa_config64_t structs. 4899 */ 4900 #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ 4901 _paddr__tx_comp_ring_base_addr_, \ 4902 _paddr__tx_comp_wr_idx_addr_, \ 4903 _paddr__tx_ce_wr_idx_addr_, \ 4904 _paddr__rx_ind_ring_base_addr_, \ 4905 _paddr__rx_ind_rd_idx_addr_, \ 4906 _paddr__rx_ind_wr_idx_addr_, \ 4907 _paddr__rx_ring2_base_addr_,\ 4908 _paddr__rx_ring2_rd_idx_addr_,\ 4909 _paddr__rx_ring2_wr_idx_addr_) \ 4910 PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ 4911 { \ 4912 /* DWORD 0: flags and meta-data */ \ 4913 A_UINT32 \ 4914 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ 4915 reserved: 8, \ 4916 tx_pkt_pool_size: 16;\ 4917 /* DWORD 1 */\ 4918 _paddr__tx_comp_ring_base_addr_;\ 4919 /* DWORD 2 (or 3)*/\ 4920 A_UINT32 tx_comp_ring_size;\ 4921 /* DWORD 3 (or 4)*/\ 4922 _paddr__tx_comp_wr_idx_addr_;\ 4923 /* DWORD 4 (or 6)*/\ 4924 _paddr__tx_ce_wr_idx_addr_;\ 4925 /* DWORD 5 (or 8)*/\ 4926 _paddr__rx_ind_ring_base_addr_;\ 4927 /* DWORD 6 (or 10)*/\ 4928 A_UINT32 rx_ind_ring_size;\ 4929 /* DWORD 7 (or 11)*/\ 4930 _paddr__rx_ind_rd_idx_addr_;\ 4931 /* DWORD 8 (or 13)*/\ 4932 _paddr__rx_ind_wr_idx_addr_;\ 4933 /* DWORD 9 (or 15)*/\ 4934 _paddr__rx_ring2_base_addr_;\ 4935 /* DWORD 10 (or 17) */\ 4936 A_UINT32 rx_ring2_size;\ 4937 /* DWORD 11 (or 18) */\ 4938 _paddr__rx_ring2_rd_idx_addr_;\ 4939 /* DWORD 12 (or 20) */\ 4940 _paddr__rx_ring2_wr_idx_addr_;\ 4941 } POSTPACK 4942 4943 /* define a htt_wdi_ipa_config32_t type */ 4944 TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); 4945 4946 /* define a htt_wdi_ipa_config64_t type */ 4947 TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); 4948 4949 #if HTT_PADDR64 4950 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t 4951 #else 4952 #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t 4953 #endif 4954 4955 enum htt_wdi_ipa_op_code { 4956 HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, 4957 HTT_WDI_IPA_OPCODE_TX_RESUME = 1, 4958 HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, 4959 HTT_WDI_IPA_OPCODE_RX_RESUME = 3, 4960 HTT_WDI_IPA_OPCODE_DBG_STATS = 4, 4961 HTT_WDI_IPA_OPCODE_GET_SHARING_STATS = 5, 4962 HTT_WDI_IPA_OPCODE_SET_QUOTA = 6, 4963 HTT_WDI_IPA_OPCODE_IND_QUOTA = 7, 4964 /* keep this last */ 4965 HTT_WDI_IPA_OPCODE_MAX 4966 }; 4967 4968 /** 4969 * @brief HTT WDI_IPA Operation Request Message 4970 * 4971 * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ 4972 * 4973 * @details 4974 * HTT WDI_IPA Operation Request message is sent by host 4975 * to either suspend or resume WDI_IPA TX or RX path. 4976 * |31 24|23 16|15 8|7 0| 4977 * |----------------+----------------+----------------+----------------| 4978 * | op_code | Rsvd | msg_type | 4979 * |-------------------------------------------------------------------| 4980 * 4981 * Header fields: 4982 * - MSG_TYPE 4983 * Bits 7:0 4984 * Purpose: Identifies this as WDI_IPA Operation Request message 4985 * value: = 0x9 (HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ) 4986 * - OP_CODE 4987 * Bits 31:16 4988 * Purpose: Identifies operation host is requesting (e.g. TX suspend) 4989 * value: = enum htt_wdi_ipa_op_code 4990 */ 4991 4992 PREPACK struct htt_wdi_ipa_op_request_t 4993 { 4994 /* DWORD 0: flags and meta-data */ 4995 A_UINT32 4996 msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ 4997 reserved: 8, 4998 op_code: 16; 4999 } POSTPACK; 5000 5001 #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ 5002 5003 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 5004 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 5005 5006 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ 5007 (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) 5008 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ 5009 do { \ 5010 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ 5011 ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ 5012 } while (0) 5013 5014 /* 5015 * @brief host -> target HTT_MSI_SETUP message 5016 * 5017 * MSG_TYPE => HTT_H2T_MSG_TYPE_MSI_SETUP 5018 * 5019 * @details 5020 * After target is booted up, host can send MSI setup message so that 5021 * target sets up HW registers based on setup message. 5022 * 5023 * The message would appear as follows: 5024 * |31 24|23 16|15|14 8|7 0| 5025 * |---------------+-----------------+-----------------+-----------------| 5026 * | reserved | msi_type | pdev_id | msg_type | 5027 * |---------------------------------------------------------------------| 5028 * | msi_addr_lo | 5029 * |---------------------------------------------------------------------| 5030 * | msi_addr_hi | 5031 * |---------------------------------------------------------------------| 5032 * | msi_data | 5033 * |---------------------------------------------------------------------| 5034 * 5035 * The message is interpreted as follows: 5036 * dword0 - b'0:7 - msg_type: This will be set to 5037 * 0x1f (HTT_H2T_MSG_TYPE_MSI_SETUP) 5038 * b'8:15 - pdev_id: 5039 * 0 (for rings at SOC/UMAC level), 5040 * 1/2/3 mac id (for rings at LMAC level) 5041 * b'16:23 - msi_type: identify which msi registers need to be setup 5042 * more details can be got from enum htt_msi_setup_type 5043 * b'24:31 - reserved 5044 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5045 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5046 * dword10 - b'0:31 - ring_msi_data: MSI data configured by host 5047 */ 5048 PREPACK struct htt_msi_setup_t { 5049 A_UINT32 msg_type: 8, 5050 pdev_id: 8, 5051 msi_type: 8, 5052 reserved: 8; 5053 A_UINT32 msi_addr_lo; 5054 A_UINT32 msi_addr_hi; 5055 A_UINT32 msi_data; 5056 } POSTPACK; 5057 5058 enum htt_msi_setup_type { 5059 HTT_PPDU_END_MSI_SETUP_TYPE, 5060 5061 /* Insert new types here*/ 5062 }; 5063 5064 #define HTT_MSI_SETUP_SZ (sizeof(struct htt_msi_setup_t)) 5065 #define HTT_MSI_SETUP_PDEV_ID_M 0x0000ff00 5066 #define HTT_MSI_SETUP_PDEV_ID_S 8 5067 #define HTT_MSI_SETUP_PDEV_ID_GET(_var) \ 5068 (((_var) & HTT_MSI_SETUP_PDEV_ID_M) >> \ 5069 HTT_MSI_SETUP_PDEV_ID_S) 5070 #define HTT_MSI_SETUP_PDEV_ID_SET(_var, _val) \ 5071 do { \ 5072 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_PDEV_ID, _val); \ 5073 ((_var) |= ((_val) << HTT_MSI_SETUP_PDEV_ID_S)); \ 5074 } while (0) 5075 5076 #define HTT_MSI_SETUP_MSI_TYPE_M 0x00ff0000 5077 #define HTT_MSI_SETUP_MSI_TYPE_S 16 5078 #define HTT_MSI_SETUP_MSI_TYPE_GET(_var) \ 5079 (((_var) & HTT_MSI_SETUP_MSI_TYPE_M) >> \ 5080 HTT_MSI_SETUP_MSI_TYPE_S) 5081 #define HTT_MSI_SETUP_MSI_TYPE_SET(_var, _val) \ 5082 do { \ 5083 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_TYPE, _val); \ 5084 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_TYPE_S)); \ 5085 } while (0) 5086 5087 #define HTT_MSI_SETUP_MSI_ADDR_LO_M 0xffffffff 5088 #define HTT_MSI_SETUP_MSI_ADDR_LO_S 0 5089 #define HTT_MSI_SETUP_MSI_ADDR_LO_GET(_var) \ 5090 (((_var) & HTT_MSI_SETUP_MSI_ADDR_LO_M) >> \ 5091 HTT_MSI_SETUP_MSI_ADDR_LO_S) 5092 #define HTT_MSI_SETUP_MSI_ADDR_LO_SET(_var, _val) \ 5093 do { \ 5094 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_LO, _val); \ 5095 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_LO_S)); \ 5096 } while (0) 5097 5098 #define HTT_MSI_SETUP_MSI_ADDR_HI_M 0xffffffff 5099 #define HTT_MSI_SETUP_MSI_ADDR_HI_S 0 5100 #define HTT_MSI_SETUP_MSI_ADDR_HI_GET(_var) \ 5101 (((_var) & HTT_MSI_SETUP_MSI_ADDR_HI_M) >> \ 5102 HTT_MSI_SETUP_MSI_ADDR_HI_S) 5103 #define HTT_MSI_SETUP_MSI_ADDR_HI_SET(_var, _val) \ 5104 do { \ 5105 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_HI, _val); \ 5106 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_HI_S)); \ 5107 } while (0) 5108 5109 #define HTT_MSI_SETUP_MSI_DATA_M 0xffffffff 5110 #define HTT_MSI_SETUP_MSI_DATA_S 0 5111 #define HTT_MSI_SETUP_MSI_DATA_GET(_var) \ 5112 (((_var) & HTT_MSI_SETUP_MSI_DATA_M) >> \ 5113 HTT_MSI_SETUP_MSI_DATA_S) 5114 #define HTT_MSI_SETUP_MSI_DATA_SET(_var, _val) \ 5115 do { \ 5116 HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_DATA, _val); \ 5117 ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_DATA_S)); \ 5118 } while (0) 5119 5120 /* 5121 * @brief host -> target HTT_SRING_SETUP message 5122 * 5123 * MSG_TYPE => HTT_H2T_MSG_TYPE_SRING_SETUP 5124 * 5125 * @details 5126 * After target is booted up, Host can send SRING setup message for 5127 * each host facing LMAC SRING. Target setups up HW registers based 5128 * on setup message and confirms back to Host if response_required is set. 5129 * Host should wait for confirmation message before sending new SRING 5130 * setup message 5131 * 5132 * The message would appear as follows: 5133 * |31 24|23 21|20|19|18 16|15|14 8|7 0| 5134 * |--------------- +-----------------+-----------------+-----------------| 5135 * | ring_type | ring_id | pdev_id | msg_type | 5136 * |----------------------------------------------------------------------| 5137 * | ring_base_addr_lo | 5138 * |----------------------------------------------------------------------| 5139 * | ring_base_addr_hi | 5140 * |----------------------------------------------------------------------| 5141 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 5142 * |----------------------------------------------------------------------| 5143 * | ring_head_offset32_remote_addr_lo | 5144 * |----------------------------------------------------------------------| 5145 * | ring_head_offset32_remote_addr_hi | 5146 * |----------------------------------------------------------------------| 5147 * | ring_tail_offset32_remote_addr_lo | 5148 * |----------------------------------------------------------------------| 5149 * | ring_tail_offset32_remote_addr_hi | 5150 * |----------------------------------------------------------------------| 5151 * | ring_msi_addr_lo | 5152 * |----------------------------------------------------------------------| 5153 * | ring_msi_addr_hi | 5154 * |----------------------------------------------------------------------| 5155 * | ring_msi_data | 5156 * |----------------------------------------------------------------------| 5157 * | intr_timer_th |IM| intr_batch_counter_th | 5158 * |----------------------------------------------------------------------| 5159 * | reserved |ID|RR| PTCF| intr_low_threshold | 5160 * |----------------------------------------------------------------------| 5161 * | reserved |IPA drop thres hi|IPA drop thres lo| 5162 * |----------------------------------------------------------------------| 5163 * Where 5164 * IM = sw_intr_mode 5165 * RR = response_required 5166 * PTCF = prefetch_timer_cfg 5167 * IP = IPA drop flag 5168 * 5169 * The message is interpreted as follows: 5170 * dword0 - b'0:7 - msg_type: This will be set to 5171 * 0xb (HTT_H2T_MSG_TYPE_SRING_SETUP) 5172 * b'8:15 - pdev_id: 5173 * 0 (for rings at SOC/UMAC level), 5174 * 1/2/3 mac id (for rings at LMAC level) 5175 * b'16:23 - ring_id: identify which ring is to setup, 5176 * more details can be got from enum htt_srng_ring_id 5177 * b'24:31 - ring_type: identify type of host rings, 5178 * more details can be got from enum htt_srng_ring_type 5179 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 5180 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 5181 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 5182 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 5183 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 5184 * SW_TO_HW_RING. 5185 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 5186 * dword4 - b'0:31 - ring_head_offset32_remote_addr_lo: 5187 * Lower 32 bits of memory address of the remote variable 5188 * storing the 4-byte word offset that identifies the head 5189 * element within the ring. 5190 * (The head offset variable has type A_UINT32.) 5191 * Valid for HW_TO_SW and SW_TO_SW rings. 5192 * dword5 - b'0:31 - ring_head_offset32_remote_addr_hi: 5193 * Upper 32 bits of memory address of the remote variable 5194 * storing the 4-byte word offset that identifies the head 5195 * element within the ring. 5196 * (The head offset variable has type A_UINT32.) 5197 * Valid for HW_TO_SW and SW_TO_SW rings. 5198 * dword6 - b'0:31 - ring_tail_offset32_remote_addr_lo: 5199 * Lower 32 bits of memory address of the remote variable 5200 * storing the 4-byte word offset that identifies the tail 5201 * element within the ring. 5202 * (The tail offset variable has type A_UINT32.) 5203 * Valid for HW_TO_SW and SW_TO_SW rings. 5204 * dword7 - b'0:31 - ring_tail_offset32_remote_addr_hi: 5205 * Upper 32 bits of memory address of the remote variable 5206 * storing the 4-byte word offset that identifies the tail 5207 * element within the ring. 5208 * (The tail offset variable has type A_UINT32.) 5209 * Valid for HW_TO_SW and SW_TO_SW rings. 5210 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 5211 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5212 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 5213 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5214 * dword10 - b'0:31 - ring_msi_data: MSI data 5215 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 5216 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 5217 * dword11 - b'0:14 - intr_batch_counter_th: 5218 * batch counter threshold is in units of 4-byte words. 5219 * HW internally maintains and increments batch count. 5220 * (see SRING spec for detail description). 5221 * When batch count reaches threshold value, an interrupt 5222 * is generated by HW. 5223 * b'15 - sw_intr_mode: 5224 * This configuration shall be static. 5225 * Only programmed at power up. 5226 * 0: generate pulse style sw interrupts 5227 * 1: generate level style sw interrupts 5228 * b'16:31 - intr_timer_th: 5229 * The timer init value when timer is idle or is 5230 * initialized to start downcounting. 5231 * In 8us units (to cover a range of 0 to 524 ms) 5232 * dword12 - b'0:15 - intr_low_threshold: 5233 * Used only by Consumer ring to generate ring_sw_int_p. 5234 * Ring entries low threshold water mark, that is used 5235 * in combination with the interrupt timer as well as 5236 * the the clearing of the level interrupt. 5237 * b'16:18 - prefetch_timer_cfg: 5238 * Used only by Consumer ring to set timer mode to 5239 * support Application prefetch handling. 5240 * The external tail offset/pointer will be updated 5241 * at following intervals: 5242 * 3'b000: (Prefetch feature disabled; used only for debug) 5243 * 3'b001: 1 usec 5244 * 3'b010: 4 usec 5245 * 3'b011: 8 usec (default) 5246 * 3'b100: 16 usec 5247 * Others: Reserved 5248 * b'19 - response_required: 5249 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 5250 * b'20 - ipa_drop_flag: 5251 Indicates that host will config ipa drop threshold percentage 5252 * b'21:31 - reserved: reserved for future use 5253 * dword13 - b'0:7 - ipa drop low threshold percentage: 5254 * b'8:15 - ipa drop high threshold percentage: 5255 * b'16:31 - Reserved 5256 */ 5257 PREPACK struct htt_sring_setup_t { 5258 A_UINT32 msg_type: 8, 5259 pdev_id: 8, 5260 ring_id: 8, 5261 ring_type: 8; 5262 A_UINT32 ring_base_addr_lo; 5263 A_UINT32 ring_base_addr_hi; 5264 A_UINT32 ring_size: 16, 5265 ring_entry_size: 8, 5266 ring_misc_cfg_flag: 8; 5267 A_UINT32 ring_head_offset32_remote_addr_lo; 5268 A_UINT32 ring_head_offset32_remote_addr_hi; 5269 A_UINT32 ring_tail_offset32_remote_addr_lo; 5270 A_UINT32 ring_tail_offset32_remote_addr_hi; 5271 A_UINT32 ring_msi_addr_lo; 5272 A_UINT32 ring_msi_addr_hi; 5273 A_UINT32 ring_msi_data; 5274 A_UINT32 intr_batch_counter_th: 15, 5275 sw_intr_mode: 1, 5276 intr_timer_th: 16; 5277 A_UINT32 intr_low_threshold: 16, 5278 prefetch_timer_cfg: 3, 5279 response_required: 1, 5280 ipa_drop_flag: 1, 5281 reserved1: 11; 5282 A_UINT32 ipa_drop_low_threshold: 8, 5283 ipa_drop_high_threshold: 8, 5284 reserved: 16; 5285 } POSTPACK; 5286 5287 enum htt_srng_ring_type { 5288 HTT_HW_TO_SW_RING = 0, 5289 HTT_SW_TO_HW_RING, 5290 HTT_SW_TO_SW_RING, 5291 /* Insert new ring types above this line */ 5292 }; 5293 5294 enum htt_srng_ring_id { 5295 HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */ 5296 HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */ 5297 HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */ 5298 HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ 5299 HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */ 5300 HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */ 5301 HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */ 5302 HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */ 5303 HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */ 5304 HTT_TX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5305 HTT_TX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5306 HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */ 5307 HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ 5308 HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ 5309 HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ 5310 /* Add Other SRING which can't be directly configured by host software above this line */ 5311 }; 5312 5313 #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t)) 5314 5315 #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00 5316 #define HTT_SRING_SETUP_PDEV_ID_S 8 5317 #define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ 5318 (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ 5319 HTT_SRING_SETUP_PDEV_ID_S) 5320 #define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ 5321 do { \ 5322 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ 5323 ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ 5324 } while (0) 5325 5326 #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000 5327 #define HTT_SRING_SETUP_RING_ID_S 16 5328 #define HTT_SRING_SETUP_RING_ID_GET(_var) \ 5329 (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ 5330 HTT_SRING_SETUP_RING_ID_S) 5331 #define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ 5332 do { \ 5333 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ 5334 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ 5335 } while (0) 5336 5337 #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000 5338 #define HTT_SRING_SETUP_RING_TYPE_S 24 5339 #define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ 5340 (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ 5341 HTT_SRING_SETUP_RING_TYPE_S) 5342 #define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ 5343 do { \ 5344 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ 5345 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ 5346 } while (0) 5347 5348 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff 5349 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0 5350 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ 5351 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ 5352 HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) 5353 #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ 5354 do { \ 5355 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \ 5356 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \ 5357 } while (0) 5358 5359 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff 5360 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0 5361 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ 5362 (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ 5363 HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) 5364 #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ 5365 do { \ 5366 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \ 5367 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \ 5368 } while (0) 5369 5370 #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff 5371 #define HTT_SRING_SETUP_RING_SIZE_S 0 5372 #define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ 5373 (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ 5374 HTT_SRING_SETUP_RING_SIZE_S) 5375 #define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ 5376 do { \ 5377 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ 5378 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ 5379 } while (0) 5380 5381 #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff0000 5382 #define HTT_SRING_SETUP_ENTRY_SIZE_S 16 5383 #define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ 5384 (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ 5385 HTT_SRING_SETUP_ENTRY_SIZE_S) 5386 #define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ 5387 do { \ 5388 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ 5389 ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ 5390 } while (0) 5391 5392 #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff000000 5393 #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24 5394 #define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \ 5395 (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ 5396 HTT_SRING_SETUP_MISC_CFG_FLAG_S) 5397 #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \ 5398 do { \ 5399 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ 5400 ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ 5401 } while (0) 5402 5403 /* This control bit is applicable to only Producer, which updates Ring ID field 5404 * of each descriptor before pushing into the ring. 5405 * 0: updates ring_id(default) 5406 * 1: ring_id updating disabled */ 5407 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M 0x01000000 5408 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S 24 5409 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \ 5410 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \ 5411 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S) 5412 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_SET(_var, _val) \ 5413 do { \ 5414 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val); \ 5415 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \ 5416 } while (0) 5417 5418 /* This control bit is applicable to only Producer, which updates Loopcnt field 5419 * of each descriptor before pushing into the ring. 5420 * 0: updates Loopcnt(default) 5421 * 1: Loopcnt updating disabled */ 5422 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M 0x02000000 5423 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S 25 5424 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_GET(_var) \ 5425 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \ 5426 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S) 5427 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_SET(_var, _val) \ 5428 do { \ 5429 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \ 5430 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \ 5431 } while (0) 5432 5433 /* Secured access enable/disable bit. SRNG drives value of this register bit 5434 * into security_id port of GXI/AXI. */ 5435 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M 0x04000000 5436 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S 26 5437 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_GET(_var) \ 5438 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \ 5439 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S) 5440 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_SET(_var, _val) \ 5441 do { \ 5442 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY, _val); \ 5443 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)); \ 5444 } while (0) 5445 5446 /* During MSI write operation, SRNG drives value of this register bit into 5447 * swap bit of GXI/AXI. */ 5448 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M 0x08000000 5449 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S 27 5450 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_GET(_var) \ 5451 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ 5452 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) 5453 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ 5454 do { \ 5455 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ 5456 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ 5457 } while (0) 5458 5459 /* During Pointer write operation, SRNG drives value of this register bit into 5460 * swap bit of GXI/AXI. */ 5461 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M 0x10000000 5462 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S 28 5463 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_GET(_var) \ 5464 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \ 5465 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S) 5466 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_SET(_var, _val) \ 5467 do { \ 5468 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \ 5469 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \ 5470 } while (0) 5471 5472 /* During any data or TLV write operation, SRNG drives value of this register 5473 * bit into swap bit of GXI/AXI. */ 5474 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M 0x20000000 5475 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S 29 5476 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_GET(_var) \ 5477 (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \ 5478 HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S) 5479 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_SET(_var, _val) \ 5480 do { \ 5481 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP, _val); \ 5482 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)); \ 5483 } while (0) 5484 5485 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED1 0x40000000 5486 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED2 0x80000000 5487 5488 5489 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5490 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5491 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5492 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5493 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5494 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5495 do { \ 5496 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5497 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5498 } while (0) 5499 5500 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5501 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5502 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5503 (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5504 HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5505 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5506 do { \ 5507 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5508 ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5509 } while (0) 5510 5511 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff 5512 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 5513 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ 5514 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ 5515 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) 5516 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ 5517 do { \ 5518 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ 5519 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ 5520 } while (0) 5521 5522 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff 5523 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 5524 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ 5525 (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ 5526 HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) 5527 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ 5528 do { \ 5529 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ 5530 ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ 5531 } while (0) 5532 5533 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_M 0xffffffff 5534 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_S 0 5535 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_GET(_var) \ 5536 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \ 5537 HTT_SRING_SETUP_RING_MSI_ADDR_LO_S) 5538 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_SET(_var, _val) \ 5539 do { \ 5540 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \ 5541 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \ 5542 } while (0) 5543 5544 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_M 0xffffffff 5545 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_S 0 5546 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_GET(_var) \ 5547 (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \ 5548 HTT_SRING_SETUP_RING_MSI_ADDR_HI_S) 5549 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_SET(_var, _val) \ 5550 do { \ 5551 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \ 5552 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \ 5553 } while (0) 5554 5555 #define HTT_SRING_SETUP_RING_MSI_DATA_M 0xffffffff 5556 #define HTT_SRING_SETUP_RING_MSI_DATA_S 0 5557 #define HTT_SRING_SETUP_RING_MSI_DATA_GET(_var) \ 5558 (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \ 5559 HTT_SRING_SETUP_RING_MSI_DATA_S) 5560 #define HTT_SRING_SETUP_RING_MSI_DATA_SET(_var, _val) \ 5561 do { \ 5562 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \ 5563 ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \ 5564 } while (0) 5565 5566 5567 5568 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M 0x00007fff 5569 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S 0 5570 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_GET(_var) \ 5571 (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \ 5572 HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S) 5573 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_SET(_var, _val) \ 5574 do { \ 5575 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \ 5576 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \ 5577 } while (0) 5578 5579 #define HTT_SRING_SETUP_SW_INTR_MODE_M 0x00008000 5580 #define HTT_SRING_SETUP_SW_INTR_MODE_S 15 5581 #define HTT_SRING_SETUP_SW_INTR_MODE_GET(_var) \ 5582 (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \ 5583 HTT_SRING_SETUP_SW_INTR_MODE_S) 5584 #define HTT_SRING_SETUP_SW_INTR_MODE_SET(_var, _val) \ 5585 do { \ 5586 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \ 5587 ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \ 5588 } while (0) 5589 5590 #define HTT_SRING_SETUP_INTR_TIMER_TH_M 0xffff0000 5591 #define HTT_SRING_SETUP_INTR_TIMER_TH_S 16 5592 #define HTT_SRING_SETUP_INTR_TIMER_TH_GET(_var) \ 5593 (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \ 5594 HTT_SRING_SETUP_INTR_TIMER_TH_S) 5595 #define HTT_SRING_SETUP_INTR_TIMER_TH_SET(_var, _val) \ 5596 do { \ 5597 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \ 5598 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \ 5599 } while (0) 5600 5601 #define HTT_SRING_SETUP_INTR_LOW_TH_M 0x0000ffff 5602 #define HTT_SRING_SETUP_INTR_LOW_TH_S 0 5603 #define HTT_SRING_SETUP_INTR_LOW_TH_GET(_var) \ 5604 (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \ 5605 HTT_SRING_SETUP_INTR_LOW_TH_S) 5606 #define HTT_SRING_SETUP_INTR_LOW_TH_SET(_var, _val) \ 5607 do { \ 5608 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \ 5609 ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \ 5610 } while (0) 5611 5612 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M 0x00070000 5613 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S 16 5614 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_GET(_var) \ 5615 (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \ 5616 HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S) 5617 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_SET(_var, _val) \ 5618 do { \ 5619 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \ 5620 ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \ 5621 } while (0) 5622 5623 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_M 0x00080000 5624 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_S 19 5625 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_GET(_var) \ 5626 (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \ 5627 HTT_SRING_SETUP_RESPONSE_REQUIRED_S) 5628 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_SET(_var, _val) \ 5629 do { \ 5630 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \ 5631 ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ 5632 } while (0) 5633 5634 5635 /** 5636 * @brief host -> target RX ring selection config message 5637 * 5638 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 5639 * 5640 * @details 5641 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 5642 * configure RXDMA rings. 5643 * The configuration is per ring based and includes both packet subtypes 5644 * and PPDU/MPDU TLVs. 5645 * 5646 * The message would appear as follows: 5647 * 5648 * |31 28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0| 5649 * |-----+--+--+--+--+-----------------+----+---+---+---+---------------| 5650 * |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 5651 * |-----------------------+-----+-----+--------------------------------| 5652 * |rsvd2|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | 5653 * |--------------------------------------------------------------------| 5654 * | packet_type_enable_flags_0 | 5655 * |--------------------------------------------------------------------| 5656 * | packet_type_enable_flags_1 | 5657 * |--------------------------------------------------------------------| 5658 * | packet_type_enable_flags_2 | 5659 * |--------------------------------------------------------------------| 5660 * | packet_type_enable_flags_3 | 5661 * |--------------------------------------------------------------------| 5662 * | tlv_filter_in_flags | 5663 * |-----------------------------------+--------------------------------| 5664 * | rx_header_offset | rx_packet_offset | 5665 * |-----------------------------------+--------------------------------| 5666 * | rx_mpdu_start_offset | rx_mpdu_end_offset | 5667 * |-----------------------------------+--------------------------------| 5668 * | rx_msdu_start_offset | rx_msdu_end_offset | 5669 * |-----------------------------------+--------------------------------| 5670 * | rsvd3 | rx_attention_offset | 5671 * |--------------------------------------------------------------------| 5672 * | rsvd4 | mo| fp| rx_drop_threshold | 5673 * | |ndp|ndp| | 5674 * |--------------------------------------------------------------------| 5675 * Where: 5676 * PS = pkt_swap 5677 * SS = status_swap 5678 * OV = rx_offsets_valid 5679 * DT = drop_thresh_valid 5680 * CLM = config_length_mgmt 5681 * CLC = config_length_ctrl 5682 * CLD = config_length_data 5683 * RXHDL = rx_hdr_len 5684 * RX = rxpcu_filter_enable_flag 5685 * The message is interpreted as follows: 5686 * dword0 - b'0:7 - msg_type: This will be set to 5687 * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG) 5688 * b'8:15 - pdev_id: 5689 * 0 (for rings at SOC/UMAC level), 5690 * 1/2/3 mac id (for rings at LMAC level) 5691 * b'16:23 - ring_id : Identify the ring to configure. 5692 * More details can be got from enum htt_srng_ring_id 5693 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 5694 * BUF_RING_CFG_0 defs within HW .h files, 5695 * e.g. wmac_top_reg_seq_hwioreg.h 5696 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 5697 * BUF_RING_CFG_0 defs within HW .h files, 5698 * e.g. wmac_top_reg_seq_hwioreg.h 5699 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 5700 * configuration fields are valid 5701 * b'27 - drop_thresh_valid (DT): flag to indicate if the 5702 * rx_drop_threshold field is valid 5703 * b'28 - rx_mon_global_en: Enable/Disable global register 5704 8 configuration in Rx monitor module. 5705 * b'29:31 - rsvd1: reserved for future use 5706 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 5707 * in byte units. 5708 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5709 * b'16:18 - config_length_mgmt (MGMT): 5710 * Represents the length of mpdu bytes for mgmt pkt. 5711 * valid values: 5712 * 001 - 64bytes 5713 * 010 - 128bytes 5714 * 100 - 256bytes 5715 * 111 - Full mpdu bytes 5716 * b'19:21 - config_length_ctrl (CTRL): 5717 * Represents the length of mpdu bytes for ctrl pkt. 5718 * valid values: 5719 * 001 - 64bytes 5720 * 010 - 128bytes 5721 * 100 - 256bytes 5722 * 111 - Full mpdu bytes 5723 * b'22:24 - config_length_data (DATA): 5724 * Represents the length of mpdu bytes for data pkt. 5725 * valid values: 5726 * 001 - 64bytes 5727 * 010 - 128bytes 5728 * 100 - 256bytes 5729 * 111 - Full mpdu bytes 5730 * b'25:26 - rx_hdr_len: 5731 * Specifies the number of bytes of recvd packet to copy 5732 * into the rx_hdr tlv. 5733 * supported values for now by host: 5734 * 01 - 64bytes 5735 * 10 - 128bytes 5736 * 11 - 256bytes 5737 * default - 128 bytes 5738 * b'27 - rxpcu_filter_enable_flag 5739 * For Scan Radio Host CPU utilization is very high. 5740 * In order to reduce CPU utilization we need to filter out 5741 * certain configured MAC frames. 5742 * To filter out configured MAC address frames, RxPCU should 5743 * be zero which means allow all frames for MD at RxOLE 5744 * host wil fiter out frames. 5745 * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out) 5746 * b'28:31 - rsvd2: Reserved for future use 5747 * dword2 - b'0:31 - packet_type_enable_flags_0: 5748 * Enable MGMT packet from 0b0000 to 0b1001 5749 * bits from low to high: FP, MD, MO - 3 bits 5750 * FP: Filter_Pass 5751 * MD: Monitor_Direct 5752 * MO: Monitor_Other 5753 * 10 mgmt subtypes * 3 bits -> 30 bits 5754 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 5755 * dword3 - b'0:31 - packet_type_enable_flags_1: 5756 * Enable MGMT packet from 0b1010 to 0b1111 5757 * bits from low to high: FP, MD, MO - 3 bits 5758 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 5759 * dword4 - b'0:31 - packet_type_enable_flags_2: 5760 * Enable CTRL packet from 0b0000 to 0b1001 5761 * bits from low to high: FP, MD, MO - 3 bits 5762 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 5763 * dword5 - b'0:31 - packet_type_enable_flags_3: 5764 * Enable CTRL packet from 0b1010 to 0b1111, 5765 * MCAST_DATA, UCAST_DATA, NULL_DATA 5766 * bits from low to high: FP, MD, MO - 3 bits 5767 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 5768 * dword6 - b'0:31 - tlv_filter_in_flags: 5769 * Filter in Attention/MPDU/PPDU/Header/User tlvs 5770 * Refer to CFG_TLV_FILTER_IN_FLAG defs 5771 * dword7 - b'0:15 - rx_packet_offset: rx_packet_offset in byte units 5772 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5773 * A value of 0 will be considered as ignore this config. 5774 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5775 * e.g. wmac_top_reg_seq_hwioreg.h 5776 * - b'16:31 - rx_header_offset: rx_header_offset in byte units 5777 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5778 * A value of 0 will be considered as ignore this config. 5779 * Refer to BUF_RING_CFG_1 defs within HW .h files, 5780 * e.g. wmac_top_reg_seq_hwioreg.h 5781 * dword8 - b'0:15 - rx_mpdu_end_offset: rx_mpdu_end_offset in byte units 5782 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5783 * A value of 0 will be considered as ignore this config. 5784 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5785 * e.g. wmac_top_reg_seq_hwioreg.h 5786 * - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units 5787 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5788 * A value of 0 will be considered as ignore this config. 5789 * Refer to BUF_RING_CFG_2 defs within HW .h files, 5790 * e.g. wmac_top_reg_seq_hwioreg.h 5791 * dword9 - b'0:15 - rx_msdu_end_offset: rx_msdu_end_offset in byte units 5792 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5793 * A value of 0 will be considered as ignore this config. 5794 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5795 * e.g. wmac_top_reg_seq_hwioreg.h 5796 * - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units 5797 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5798 * A value of 0 will be considered as ignore this config. 5799 * Refer to BUF_RING_CFG_3 defs within HW .h files, 5800 * e.g. wmac_top_reg_seq_hwioreg.h 5801 * dword10- b'0:15 - rx_attention_offset: rx_attention_offset in byte units 5802 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 5803 * A value of 0 will be considered as ignore this config. 5804 * Refer to BUF_RING_CFG_4 defs within HW .h files, 5805 * e.g. wmac_top_reg_seq_hwioreg.h 5806 * - b'16:31 - rsvd3 for future use 5807 * dword11- b'9:0 - rx_drop_threshold: Threshold configured in monitor mode 5808 * to source rings. Consumer drops packets if the available 5809 * words in the ring falls below the configured threshold 5810 * value. 5811 * - b'10 - fp_ndp: Flag to indicate FP NDP status tlv is subscribed 5812 * by host. 1 -> subscribed 5813 * - b'11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed 5814 * by host. 1 -> subscribed 5815 * - b'12 - fp_phy_err: Flag to indicate FP PHY status tlv is 5816 * subscribed by host. 1 -> subscribed 5817 * - b'13:14 - fp_phy_err_buf_src: This indicates the source ring 5818 * selection for the FP PHY ERR status tlv. 5819 * 0 - wbm2rxdma_buf_source_ring 5820 * 1 - fw2rxdma_buf_source_ring 5821 * 2 - sw2rxdma_buf_source_ring 5822 * 3 - no_buffer_ring 5823 * - b'15:16 - fp_phy_err_buf_dest: This indicates the destination ring 5824 * selection for the FP PHY ERR status tlv. 5825 * 0 - rxdma_release_ring 5826 * 1 - rxdma2fw_ring 5827 * 2 - rxdma2sw_ring 5828 * 3 - rxdma2reo_ring 5829 * - b'17:19 - pkt_type_en_msdu_or_mpdu_logging 5830 * b'17 - Enables MSDU/MPDU logging for frames of MGMT type 5831 * b'18 - Enables MSDU/MPDU logging for frames of CTRL type 5832 * b'19 - Enables MSDU/MPDU logging for frames of DATA type 5833 * - b'20 - dma_mpdu_mgmt: 1: MPDU level logging 5834 * 0: MSDU level logging 5835 * - b'21 - dma_mpdu_ctrl: 1: MPDU level logging 5836 * 0: MSDU level logging 5837 * - b'22 - dma_mpdu_data: 1: MPDU level logging 5838 * 0: MSDU level logging 5839 * - b'23 - word_mask_compaction: enable/disable word mask for 5840 * mpdu/msdu start/end tlvs 5841 * - b'24 - rbm_override_enable: enabling/disabling return buffer 5842 * manager override 5843 * - b'25:28 - rbm_override_val: return buffer manager override value 5844 * dword12- b'0:31 - phy_err_mask: This field is to select the fp phy errors 5845 * which have to be posted to host from phy. 5846 * Corresponding to errors defined in 5847 * phyrx_abort_request_reason enums 0 to 31. 5848 * Refer to RXPCU register definition header files for the 5849 * phyrx_abort_request_reason enum definition. 5850 * dword13- b'0:31 - phy_err_mask_cont: This field is to select the fp phy 5851 * errors which have to be posted to host from phy. 5852 * Corresponding to errors defined in 5853 * phyrx_abort_request_reason enums 32 to 63. 5854 * Refer to RXPCU register definition header files for the 5855 * phyrx_abort_request_reason enum definition. 5856 * dword14- b'0:15 - rx_mpdu_start_word_mask: word mask for rx mpdu start, 5857 * applicable if word mask enabled 5858 * - b'16:18 - rx_mpdu_end_word_mask: word mask value for rx mpdu end, 5859 * applicable if word mask enabled 5860 * - b'19:31 - rsvd7 5861 * dword15- b'0:16 - rx_msdu_end_word_mask 5862 * - b'17:31 - rsvd5 5863 * dword17- b'0 - en_rx_tlv_pkt_offset: 5864 * 0: RX_PKT TLV logging at offset 0 for the subsequent 5865 * buffer 5866 * 1: RX_PKT TLV logging at specified offset for the 5867 * subsequent buffer 5868 * b`15:1 - rx_pkt_tlv_offset: Qword offset for rx_packet TLVs. 5869 */ 5870 PREPACK struct htt_rx_ring_selection_cfg_t { 5871 A_UINT32 msg_type: 8, 5872 pdev_id: 8, 5873 ring_id: 8, 5874 status_swap: 1, 5875 pkt_swap: 1, 5876 rx_offsets_valid: 1, 5877 drop_thresh_valid: 1, 5878 rx_mon_global_en: 1, 5879 rsvd1: 3; 5880 A_UINT32 ring_buffer_size: 16, 5881 config_length_mgmt:3, 5882 config_length_ctrl:3, 5883 config_length_data:3, 5884 rx_hdr_len: 2, 5885 rxpcu_filter_enable_flag:1, 5886 rsvd2: 4; 5887 A_UINT32 packet_type_enable_flags_0; 5888 A_UINT32 packet_type_enable_flags_1; 5889 A_UINT32 packet_type_enable_flags_2; 5890 A_UINT32 packet_type_enable_flags_3; 5891 A_UINT32 tlv_filter_in_flags; 5892 A_UINT32 rx_packet_offset: 16, 5893 rx_header_offset: 16; 5894 A_UINT32 rx_mpdu_end_offset: 16, 5895 rx_mpdu_start_offset: 16; 5896 A_UINT32 rx_msdu_end_offset: 16, 5897 rx_msdu_start_offset: 16; 5898 A_UINT32 rx_attn_offset: 16, 5899 rsvd3: 16; 5900 A_UINT32 rx_drop_threshold: 10, 5901 fp_ndp: 1, 5902 mo_ndp: 1, 5903 fp_phy_err: 1, 5904 fp_phy_err_buf_src: 2, 5905 fp_phy_err_buf_dest: 2, 5906 pkt_type_enable_msdu_or_mpdu_logging:3, 5907 dma_mpdu_mgmt: 1, 5908 dma_mpdu_ctrl: 1, 5909 dma_mpdu_data: 1, 5910 word_mask_compaction_enable:1, 5911 rbm_override_enable: 1, 5912 rbm_override_val: 4, 5913 rsvd4: 3; 5914 A_UINT32 phy_err_mask; 5915 A_UINT32 phy_err_mask_cont; 5916 A_UINT32 rx_mpdu_start_word_mask:16, 5917 rx_mpdu_end_word_mask: 3, 5918 rsvd7: 13; 5919 A_UINT32 rx_msdu_end_word_mask: 17, 5920 rsvd5: 15; 5921 A_UINT32 en_rx_tlv_pkt_offset: 1, 5922 rx_pkt_tlv_offset: 15, 5923 rsvd6: 16; 5924 A_UINT32 rx_mpdu_start_word_mask_v2: 20, 5925 rx_mpdu_end_word_mask_v2: 8, 5926 rsvd8: 4; 5927 A_UINT32 rx_msdu_end_word_mask_v2: 20, 5928 rsvd9: 12; 5929 A_UINT32 rx_ppdu_end_usr_stats_word_mask_v2: 20, 5930 rsvd10: 12; 5931 A_UINT32 packet_type_enable_fpmo_flags0; 5932 A_UINT32 packet_type_enable_fpmo_flags1; 5933 } POSTPACK; 5934 5935 #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) 5936 5937 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 5938 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_S 8 5939 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_GET(_var) \ 5940 (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \ 5941 HTT_RX_RING_SELECTION_CFG_PDEV_ID_S) 5942 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_SET(_var, _val) \ 5943 do { \ 5944 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \ 5945 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \ 5946 } while (0) 5947 5948 #define HTT_RX_RING_SELECTION_CFG_RING_ID_M 0x00ff0000 5949 #define HTT_RX_RING_SELECTION_CFG_RING_ID_S 16 5950 #define HTT_RX_RING_SELECTION_CFG_RING_ID_GET(_var) \ 5951 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \ 5952 HTT_RX_RING_SELECTION_CFG_RING_ID_S) 5953 #define HTT_RX_RING_SELECTION_CFG_RING_ID_SET(_var, _val) \ 5954 do { \ 5955 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \ 5956 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \ 5957 } while (0) 5958 5959 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M 0x01000000 5960 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S 24 5961 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_GET(_var) \ 5962 (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \ 5963 HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S) 5964 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(_var, _val) \ 5965 do { \ 5966 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP, _val); \ 5967 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \ 5968 } while (0) 5969 5970 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M 0x02000000 5971 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S 25 5972 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_GET(_var) \ 5973 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \ 5974 HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S) 5975 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(_var, _val) \ 5976 do { \ 5977 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP, _val); \ 5978 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \ 5979 } while (0) 5980 5981 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M 0x04000000 5982 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S 26 5983 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \ 5984 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \ 5985 HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S) 5986 #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \ 5987 do { \ 5988 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \ 5989 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \ 5990 } while (0) 5991 5992 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M 0x08000000 5993 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S 27 5994 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_GET(_var) \ 5995 (((_var) & HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M) >> \ 5996 HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S) 5997 #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_SET(_var, _val) \ 5998 do { \ 5999 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID, _val); \ 6000 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \ 6001 } while (0) 6002 6003 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M 0x10000000 6004 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S 28 6005 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_GET(_var) \ 6006 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M) >> \ 6007 HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S) 6008 #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_SET(_var, _val) \ 6009 do { \ 6010 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN, _val); \ 6011 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \ 6012 } while (0) 6013 6014 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff 6015 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 6016 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ 6017 (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \ 6018 HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S) 6019 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 6020 do { \ 6021 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE, _val); \ 6022 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \ 6023 } while (0) 6024 6025 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 6026 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S 16 6027 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 6028 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M) >> \ 6029 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S) 6030 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 6031 do { \ 6032 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT, _val); \ 6033 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)); \ 6034 } while (0) 6035 6036 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 6037 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S 19 6038 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 6039 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M) >> \ 6040 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S) 6041 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 6042 do { \ 6043 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL, _val); \ 6044 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S)); \ 6045 } while (0) 6046 6047 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 6048 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S 22 6049 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 6050 (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M) >> \ 6051 HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S) 6052 #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 6053 do { \ 6054 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA, _val); \ 6055 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S)); \ 6056 } while (0) 6057 6058 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000 6059 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25 6060 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \ 6061 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ 6062 HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) 6063 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \ 6064 do { \ 6065 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \ 6066 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\ 6067 } while(0) 6068 6069 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000 6070 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27 6071 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \ 6072 (((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \ 6073 HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S) 6074 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \ 6075 do { \ 6076 HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \ 6077 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S));\ 6078 } while(0) 6079 6080 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff 6081 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0 6082 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \ 6083 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \ 6084 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S) 6085 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_SET(_var, _val) \ 6086 do { \ 6087 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, _val); \ 6088 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \ 6089 } while (0) 6090 6091 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M 0xffffffff 6092 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S 0 6093 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_GET(_var) \ 6094 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \ 6095 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S) 6096 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_SET(_var, _val) \ 6097 do { \ 6098 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val); \ 6099 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \ 6100 } while (0) 6101 6102 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M 0xffffffff 6103 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S 0 6104 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_GET(_var) \ 6105 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \ 6106 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S) 6107 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_SET(_var, _val) \ 6108 do { \ 6109 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val); \ 6110 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \ 6111 } while (0) 6112 6113 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M 0xffffffff 6114 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S 0 6115 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_GET(_var) \ 6116 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \ 6117 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S) 6118 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_SET(_var, _val) \ 6119 do { \ 6120 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val); \ 6121 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \ 6122 } while (0) 6123 6124 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M 0xffffffff 6125 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S 0 6126 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \ 6127 (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \ 6128 HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S) 6129 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_SET(_var, _val) \ 6130 do { \ 6131 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \ 6132 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \ 6133 } while (0) 6134 6135 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M 0x0000ffff 6136 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S 0 6137 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \ 6138 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \ 6139 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S) 6140 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \ 6141 do { \ 6142 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \ 6143 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \ 6144 } while (0) 6145 6146 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M 0xffff0000 6147 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S 16 6148 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \ 6149 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \ 6150 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S) 6151 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \ 6152 do { \ 6153 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \ 6154 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \ 6155 } while (0) 6156 6157 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M 0x0000ffff 6158 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S 0 6159 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \ 6160 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \ 6161 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S) 6162 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \ 6163 do { \ 6164 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \ 6165 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \ 6166 } while (0) 6167 6168 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M 0xffff0000 6169 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S 16 6170 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \ 6171 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \ 6172 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S) 6173 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \ 6174 do { \ 6175 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \ 6176 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \ 6177 } while (0) 6178 6179 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M 0x0000ffff 6180 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S 0 6181 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \ 6182 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \ 6183 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S) 6184 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \ 6185 do { \ 6186 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \ 6187 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \ 6188 } while (0) 6189 6190 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M 0xffff0000 6191 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S 16 6192 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \ 6193 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \ 6194 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S) 6195 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \ 6196 do { \ 6197 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \ 6198 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \ 6199 } while (0) 6200 6201 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M 0x0000ffff 6202 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S 0 6203 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \ 6204 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \ 6205 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S) 6206 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \ 6207 do { \ 6208 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \ 6209 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \ 6210 } while (0) 6211 6212 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M 0x000003ff 6213 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S 0 6214 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_GET(_var) \ 6215 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M) >> \ 6216 HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S) 6217 #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(_var, _val) \ 6218 do { \ 6219 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD, _val); \ 6220 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \ 6221 } while (0) 6222 6223 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_M 0x00000400 6224 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_S 10 6225 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_GET(_var) \ 6226 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_NDP_M) >> \ 6227 HTT_RX_RING_SELECTION_CFG_FP_NDP_S) 6228 #define HTT_RX_RING_SELECTION_CFG_FP_NDP_SET(_var, _val) \ 6229 do { \ 6230 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_NDP, _val); \ 6231 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_NDP_S)); \ 6232 } while (0) 6233 6234 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_M 0x00000800 6235 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_S 11 6236 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_GET(_var) \ 6237 (((_var) & HTT_RX_RING_SELECTION_CFG_MO_NDP_M) >> \ 6238 HTT_RX_RING_SELECTION_CFG_MO_NDP_S) 6239 #define HTT_RX_RING_SELECTION_CFG_MO_NDP_SET(_var, _val) \ 6240 do { \ 6241 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_MO_NDP, _val); \ 6242 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \ 6243 } while (0) 6244 6245 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M 0x00001000 6246 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S 12 6247 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_GET(_var) \ 6248 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M) >> \ 6249 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S) 6250 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_SET(_var, _val) \ 6251 do { \ 6252 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR, _val); \ 6253 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)); \ 6254 } while (0) 6255 6256 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M 0x00006000 6257 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S 13 6258 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_GET(_var) \ 6259 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M) >> \ 6260 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S) 6261 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_SET(_var, _val) \ 6262 do { \ 6263 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC, _val); \ 6264 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)); \ 6265 } while (0) 6266 6267 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M 0x00018000 6268 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S 15 6269 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_GET(_var) \ 6270 (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M) >> \ 6271 HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S) 6272 #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_SET(_var, _val) \ 6273 do { \ 6274 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST, _val); \ 6275 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)); \ 6276 } while (0) 6277 6278 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M 0x000E0000 6279 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S 17 6280 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_GET(_var) \ 6281 (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M) >> \ 6282 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S) 6283 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_SET(_var, _val) \ 6284 do { \ 6285 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING, _val); \ 6286 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S)); \ 6287 } while (0) 6288 6289 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M 0x00100000 6290 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S 20 6291 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_GET(_var) \ 6292 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M) >> \ 6293 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S) 6294 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 6295 do { \ 6296 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT, _val); \ 6297 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S)); \ 6298 } while (0) 6299 6300 6301 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M 0x00200000 6302 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S 21 6303 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_GET(_var) \ 6304 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M) >> \ 6305 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S) 6306 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 6307 do { \ 6308 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL, _val); \ 6309 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S)); \ 6310 } while (0) 6311 6312 6313 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M 0x00400000 6314 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S 22 6315 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_GET(_var) \ 6316 (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M) >> \ 6317 HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S) 6318 #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 6319 do { \ 6320 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA, _val); \ 6321 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S)); \ 6322 } while (0) 6323 6324 6325 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00800000 6326 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S 23 6327 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 6328 (((_var) & HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 6329 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S) 6330 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 6331 do { \ 6332 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 6333 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 6334 } while (0) 6335 6336 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M 0x01000000 6337 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S 24 6338 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_GET(_var) \ 6339 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M) >> \ 6340 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S) 6341 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_SET(_var, _val) \ 6342 do { \ 6343 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE, _val);\ 6344 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S)); \ 6345 } while (0) 6346 6347 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M 0x1E000000 6348 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S 25 6349 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_GET(_var) \ 6350 (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M) >> \ 6351 HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S) 6352 #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_SET(_var, _val) \ 6353 do { \ 6354 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE, _val);\ 6355 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S));\ 6356 } while (0) 6357 6358 6359 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M 0xffffffff 6360 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S 0 6361 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_GET(_var) \ 6362 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M) >> \ 6363 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S) 6364 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_SET(_var, _val) \ 6365 do { \ 6366 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK, _val); \ 6367 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)); \ 6368 } while (0) 6369 6370 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M 0xffffffff 6371 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S 0 6372 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_GET(_var) \ 6373 (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M) >> \ 6374 HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S) 6375 #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_SET(_var, _val) \ 6376 do { \ 6377 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT, _val); \ 6378 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)); \ 6379 } while (0) 6380 6381 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M 0x0000FFFF 6382 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S 0 6383 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_GET(_var) \ 6384 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M)>> \ 6385 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S) 6386 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(_var, _val) \ 6387 do { \ 6388 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK, _val);\ 6389 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \ 6390 } while (0) 6391 6392 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0x00070000 6393 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S 16 6394 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_GET(_var) \ 6395 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M)>> \ 6396 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S) 6397 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(_var, _val) \ 6398 do { \ 6399 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK, _val);\ 6400 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)); \ 6401 } while (0) 6402 6403 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M 0x0001FFFF 6404 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S 0 6405 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_GET(_var) \ 6406 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M)>> \ 6407 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S) 6408 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(_var, _val) \ 6409 do { \ 6410 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK, _val);\ 6411 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S)); \ 6412 } while (0) 6413 6414 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M 0x00000001 6415 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S 0 6416 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_GET(_var) \ 6417 (((_var) & HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M)>> \ 6418 HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S) 6419 #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6420 do { \ 6421 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET, _val); \ 6422 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S)); \ 6423 } while (0) 6424 6425 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M 0x0000FFFE 6426 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S 1 6427 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_GET(_var) \ 6428 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M)>> \ 6429 HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S) 6430 #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_SET(_var, _val) \ 6431 do { \ 6432 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET, _val); \ 6433 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)); \ 6434 } while (0) 6435 6436 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M 0x000FFFFF 6437 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S 0 6438 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_GET(_var) \ 6439 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M)>> \ 6440 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S) 6441 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_SET(_var, _val) \ 6442 do { \ 6443 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2, _val);\ 6444 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)); \ 6445 } while (0) 6446 6447 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M 0x0FF00000 6448 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S 20 6449 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_GET(_var) \ 6450 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M)>> \ 6451 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S) 6452 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_SET(_var, _val) \ 6453 do { \ 6454 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2, _val);\ 6455 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)); \ 6456 } while (0) 6457 6458 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M 0x000FFFFF 6459 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S 0 6460 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_GET(_var) \ 6461 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M)>> \ 6462 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S) 6463 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_SET(_var, _val) \ 6464 do { \ 6465 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2, _val);\ 6466 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)); \ 6467 } while (0) 6468 6469 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M 0x000FFFFF 6470 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S 0 6471 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_GET(_var) \ 6472 (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M)>> \ 6473 HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S) 6474 #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_SET(_var, _val) \ 6475 do { \ 6476 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2, _val);\ 6477 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)); \ 6478 } while (0) 6479 6480 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M 0xFFFFFFFF 6481 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S 0 6482 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_GET(_var) \ 6483 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M)>> \ 6484 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S) 6485 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_SET(_var, _val) \ 6486 do { \ 6487 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0, _val); \ 6488 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)); \ 6489 } while (0) 6490 6491 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M 0xFFFFFFFF 6492 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S 0 6493 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_GET(_var) \ 6494 (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M)>> \ 6495 HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S) 6496 #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_SET(_var, _val) \ 6497 do { \ 6498 HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1, _val); \ 6499 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \ 6500 } while (0) 6501 6502 /* 6503 * Subtype based MGMT frames enable bits. 6504 * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other 6505 */ 6506 /* association request */ 6507 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M 0x00000001 6508 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_S 0 6509 6510 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M 0x00000002 6511 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_S 1 6512 6513 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M 0x00000004 6514 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_S 2 6515 6516 /* association response */ 6517 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M 0x00000008 6518 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_S 3 6519 6520 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M 0x00000010 6521 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_S 4 6522 6523 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M 0x00000020 6524 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_S 5 6525 6526 /* Reassociation request */ 6527 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M 0x00000040 6528 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_S 6 6529 6530 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M 0x00000080 6531 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_S 7 6532 6533 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M 0x00000100 6534 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_S 8 6535 6536 /* Reassociation response */ 6537 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M 0x00000200 6538 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_S 9 6539 6540 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M 0x00000400 6541 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_S 10 6542 6543 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M 0x00000800 6544 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_S 11 6545 6546 /* Probe request */ 6547 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M 0x00001000 6548 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_S 12 6549 6550 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M 0x00002000 6551 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_S 13 6552 6553 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M 0x00004000 6554 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_S 14 6555 6556 /* Probe response */ 6557 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M 0x00008000 6558 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_S 15 6559 6560 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M 0x00010000 6561 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_S 16 6562 6563 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M 0x00020000 6564 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_S 17 6565 6566 /* Timing Advertisement */ 6567 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M 0x00040000 6568 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_S 18 6569 6570 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M 0x00080000 6571 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_S 19 6572 6573 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M 0x00100000 6574 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_S 20 6575 6576 /* Reserved */ 6577 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M 0x00200000 6578 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_S 21 6579 6580 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M 0x00400000 6581 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_S 22 6582 6583 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M 0x00800000 6584 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23 6585 6586 /* Beacon */ 6587 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000 6588 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24 6589 6590 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000 6591 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25 6592 6593 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000 6594 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26 6595 6596 /* ATIM */ 6597 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000 6598 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27 6599 6600 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000 6601 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28 6602 6603 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000 6604 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29 6605 6606 /* Disassociation */ 6607 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M 0x00000001 6608 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_S 0 6609 6610 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M 0x00000002 6611 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_S 1 6612 6613 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M 0x00000004 6614 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_S 2 6615 6616 /* Authentication */ 6617 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M 0x00000008 6618 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_S 3 6619 6620 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M 0x00000010 6621 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_S 4 6622 6623 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M 0x00000020 6624 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_S 5 6625 6626 /* Deauthentication */ 6627 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M 0x00000040 6628 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_S 6 6629 6630 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M 0x00000080 6631 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_S 7 6632 6633 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M 0x00000100 6634 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_S 8 6635 6636 /* Action */ 6637 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M 0x00000200 6638 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_S 9 6639 6640 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M 0x00000400 6641 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_S 10 6642 6643 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M 0x00000800 6644 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_S 11 6645 6646 /* Action No Ack */ 6647 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M 0x00001000 6648 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_S 12 6649 6650 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M 0x00002000 6651 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_S 13 6652 6653 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M 0x00004000 6654 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_S 14 6655 6656 /* Reserved */ 6657 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M 0x00008000 6658 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_S 15 6659 6660 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M 0x00010000 6661 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_S 16 6662 6663 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M 0x00020000 6664 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_S 17 6665 6666 /* 6667 * Subtype based CTRL frames enable bits. 6668 * FP: Filter_Pass, MD: Monitor_Direct, MO: Monitor_Other 6669 */ 6670 /* Reserved */ 6671 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M 0x00000001 6672 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_S 0 6673 6674 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M 0x00000002 6675 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_S 1 6676 6677 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M 0x00000004 6678 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_S 2 6679 6680 /* Reserved */ 6681 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M 0x00000008 6682 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_S 3 6683 6684 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M 0x00000010 6685 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_S 4 6686 6687 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M 0x00000020 6688 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_S 5 6689 6690 /* Reserved */ 6691 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M 0x00000040 6692 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_S 6 6693 6694 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M 0x00000080 6695 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_S 7 6696 6697 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M 0x00000100 6698 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_S 8 6699 6700 /* Reserved */ 6701 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M 0x00000200 6702 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_S 9 6703 6704 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M 0x00000400 6705 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_S 10 6706 6707 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M 0x00000800 6708 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_S 11 6709 6710 /* Reserved */ 6711 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M 0x00001000 6712 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_S 12 6713 6714 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M 0x00002000 6715 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_S 13 6716 6717 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M 0x00004000 6718 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_S 14 6719 6720 /* Reserved */ 6721 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M 0x00008000 6722 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_S 15 6723 6724 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M 0x00010000 6725 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_S 16 6726 6727 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M 0x00020000 6728 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_S 17 6729 6730 /* Reserved */ 6731 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M 0x00040000 6732 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_S 18 6733 6734 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M 0x00080000 6735 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_S 19 6736 6737 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M 0x00100000 6738 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_S 20 6739 6740 /* Control Wrapper */ 6741 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M 0x00200000 6742 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_S 21 6743 6744 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M 0x00400000 6745 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_S 22 6746 6747 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M 0x00800000 6748 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_S 23 6749 6750 /* Block Ack Request */ 6751 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M 0x01000000 6752 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_S 24 6753 6754 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M 0x02000000 6755 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_S 25 6756 6757 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M 0x04000000 6758 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_S 26 6759 6760 /* Block Ack*/ 6761 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M 0x08000000 6762 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_S 27 6763 6764 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M 0x10000000 6765 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_S 28 6766 6767 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M 0x20000000 6768 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_S 29 6769 6770 /* PS-POLL */ 6771 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M 0x00000001 6772 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_S 0 6773 6774 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M 0x00000002 6775 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_S 1 6776 6777 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M 0x00000004 6778 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_S 2 6779 6780 /* RTS */ 6781 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M 0x00000008 6782 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_S 3 6783 6784 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M 0x00000010 6785 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_S 4 6786 6787 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M 0x00000020 6788 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_S 5 6789 6790 /* CTS */ 6791 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M 0x00000040 6792 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_S 6 6793 6794 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M 0x00000080 6795 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_S 7 6796 6797 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M 0x00000100 6798 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_S 8 6799 6800 /* ACK */ 6801 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M 0x00000200 6802 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_S 9 6803 6804 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M 0x00000400 6805 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_S 10 6806 6807 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M 0x00000800 6808 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_S 11 6809 6810 /* CF-END */ 6811 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M 0x00001000 6812 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_S 12 6813 6814 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M 0x00002000 6815 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_S 13 6816 6817 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M 0x00004000 6818 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_S 14 6819 6820 /* CF-END + CF-ACK */ 6821 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M 0x00008000 6822 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_S 15 6823 6824 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M 0x00010000 6825 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_S 16 6826 6827 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M 0x00020000 6828 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_S 17 6829 6830 /* Multicast data */ 6831 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M 0x00040000 6832 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_S 18 6833 6834 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M 0x00080000 6835 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_S 19 6836 6837 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M 0x00100000 6838 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_S 20 6839 6840 /* Unicast data */ 6841 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M 0x00200000 6842 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_S 21 6843 6844 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M 0x00400000 6845 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_S 22 6846 6847 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M 0x00800000 6848 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_S 23 6849 6850 /* NULL data */ 6851 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M 0x01000000 6852 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_S 24 6853 6854 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M 0x02000000 6855 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_S 25 6856 6857 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000 6858 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26 6859 6860 /* FPMO mode flags */ 6861 /* MGMT */ 6862 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_M 0x00000001 6863 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_S 0 6864 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_M 0x00000002 6865 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_S 1 6866 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_M 0x00000004 6867 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_S 2 6868 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_M 0x00000008 6869 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_S 3 6870 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_M 0x00000010 6871 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_S 4 6872 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_M 0x00000020 6873 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_S 5 6874 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_M 0x00000040 6875 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_S 6 6876 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_M 0x00000080 6877 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_S 7 6878 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_M 0x00000100 6879 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_S 8 6880 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_M 0x00000200 6881 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_S 9 6882 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_M 0x00000400 6883 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_S 10 6884 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_M 0x00000800 6885 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_S 11 6886 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_M 0x00001000 6887 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_S 12 6888 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_M 0x00002000 6889 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_S 13 6890 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_M 0x00004000 6891 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_S 14 6892 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_M 0x00008000 6893 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_S 15 6894 6895 /* CTRL */ 6896 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_M 0x00010000 6897 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_S 16 6898 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_M 0x00020000 6899 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_S 17 6900 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_M 0x00040000 6901 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_S 18 6902 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_M 0x00080000 6903 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_S 19 6904 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_M 0x00100000 6905 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_S 20 6906 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_M 0x00200000 6907 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_S 21 6908 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_M 0x00400000 6909 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_S 22 6910 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_M 0x00800000 6911 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_S 23 6912 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_M 0x01000000 6913 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_S 24 6914 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_M 0x02000000 6915 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_S 25 6916 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_M 0x04000000 6917 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_S 26 6918 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_M 0x08000000 6919 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_S 27 6920 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_M 0x10000000 6921 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_S 28 6922 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_M 0x20000000 6923 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_S 29 6924 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_M 0x40000000 6925 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_S 30 6926 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_M 0x80000000 6927 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_S 31 6928 6929 /* DATA */ 6930 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_M 0x00000001 6931 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_S 0 6932 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_M 0x00000002 6933 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_S 1 6934 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_M 0x00000004 6935 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_S 2 6936 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_M 0x00000008 6937 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_S 3 6938 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_M 0x00000010 6939 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_S 4 6940 6941 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \ 6942 do { \ 6943 HTT_CHECK_SET_VAL(httsym, value); \ 6944 (word) |= (value) << httsym##_S; \ 6945 } while (0) 6946 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word, httsym) \ 6947 (((word) & httsym##_M) >> httsym##_S) 6948 6949 #define htt_rx_ring_pkt_enable_subtype_set( \ 6950 word, flag, mode, type, subtype, val) \ 6951 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET( \ 6952 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype, val) 6953 6954 #define htt_rx_ring_pkt_enable_subtype_get( \ 6955 word, flag, mode, type, subtype) \ 6956 HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET( \ 6957 word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype) 6958 6959 /* Definition to filter in TLVs */ 6960 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001 6961 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0 6962 6963 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002 6964 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1 6965 6966 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004 6967 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2 6968 6969 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008 6970 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3 6971 6972 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010 6973 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4 6974 6975 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M 0x00000020 6976 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5 6977 6978 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040 6979 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6 6980 6981 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080 6982 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7 6983 6984 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100 6985 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8 6986 6987 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200 6988 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9 6989 6990 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M 0x00000400 6991 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10 6992 6993 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800 6994 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_S 11 6995 6996 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M 0x00001000 6997 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S 12 6998 6999 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_M 0x00002000 7000 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_S 13 7001 7002 #define HTT_RX_RING_TLV_ENABLE_SET(word, httsym, enable) \ 7003 do { \ 7004 HTT_CHECK_SET_VAL(httsym, enable); \ 7005 (word) |= (enable) << httsym##_S; \ 7006 } while (0) 7007 #define HTT_RX_RING_TLV_ENABLE_GET(word, httsym) \ 7008 (((word) & httsym##_M) >> httsym##_S) 7009 7010 #define htt_rx_ring_tlv_filter_in_enable_set(word, tlv, enable) \ 7011 HTT_RX_RING_TLV_ENABLE_SET( \ 7012 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable) 7013 7014 #define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \ 7015 HTT_RX_RING_TLV_ENABLE_GET( \ 7016 word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv) 7017 7018 /** 7019 * @brief host -> target TX monitor config message 7020 * 7021 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_MONITOR_CFG 7022 * 7023 * @details 7024 * HTT_H2T_MSG_TYPE_TX_MONITOR_CFG message is sent by host to 7025 * configure RXDMA rings. 7026 * The configuration is per ring based and includes both packet types 7027 * and PPDU/MPDU TLVs. 7028 * 7029 * The message would appear as follows: 7030 * 7031 * |31 26|25|24|23 22|21|20|19|18 16|15|14|13|12|11|10|9|8|7|6|5|4|3|2 0| 7032 * |--------+--+--+-----+--+--+--+-----+--+--+--+--+--+--+-+-+-+-+-+-+-+----| 7033 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 7034 * |-----------+--------+--------+-----+------------------------------------| 7035 * | rsvd2 | DATA | CTRL | MGMT| ring_buffer_size | 7036 * |--------------------------------------+--+--+--+--+--+-+-+-+-+-+-+-+----| 7037 * | | M| M| M| M| M|M|M|M|M|M|M|M| | 7038 * | | S| S| S| P| P|P|S|S|S|P|P|P| | 7039 * | | E| E| E| E| E|E|S|S|S|S|S|S| | 7040 * | rsvd3 | D| C| M| D| C|M|D|C|M|D|C|M| E | 7041 * |------------------------------------------------------------------------| 7042 * | tlv_filter_mask_in0 | 7043 * |------------------------------------------------------------------------| 7044 * | tlv_filter_mask_in1 | 7045 * |------------------------------------------------------------------------| 7046 * | tlv_filter_mask_in2 | 7047 * |------------------------------------------------------------------------| 7048 * | tlv_filter_mask_in3 | 7049 * |-----------------+-----------------+---------------------+--------------| 7050 * | tx_msdu_start_wm| tx_queue_ext_wm | tx_peer_entry_wm |tx_fes_stup_wm| 7051 * |------------------------------------------------------------------------| 7052 * | pcu_ppdu_setup_word_mask | 7053 * |--------------------+--+--+--+-----+---------------------+--------------| 7054 * | rsvd4 | D| C| M| PT | rxpcu_usrsetp_wm |tx_mpdu_srt_wm| 7055 * |------------------------------------------------------------------------| 7056 * 7057 * Where: 7058 * PS = pkt_swap 7059 * SS = status_swap 7060 * The message is interpreted as follows: 7061 * dword0 - b'0:7 - msg_type: This will be set to 7062 * 0x1b (HTT_H2T_MSG_TYPE_TX_MONITOR_CFG) 7063 * b'8:15 - pdev_id: 7064 * 0 (for rings at SOC level), 7065 * 1/2/3 mac id (for rings at LMAC level) 7066 * b'16:23 - ring_id : Identify the ring to configure. 7067 * More details can be got from enum htt_srng_ring_id 7068 * b'24 - status_swap (SS): 1 is to swap status TLV - refer to 7069 * BUF_RING_CFG_0 defs within HW .h files, 7070 * e.g. wmac_top_reg_seq_hwioreg.h 7071 * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to 7072 * BUF_RING_CFG_0 defs within HW .h files, 7073 * e.g. wmac_top_reg_seq_hwioreg.h 7074 * b'26 - tx_mon_global_en: Enable/Disable global register 7075 * configuration in Tx monitor module. 7076 * b'27:31 - rsvd1: reserved for future use 7077 * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, 7078 * in byte units. 7079 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 7080 * b'16:18 - config_length_mgmt(MGMT) for MGMT: Each bit set represent 7081 * 64, 128, 256. 7082 * If all 3 bits are set config length is > 256. 7083 * if val is '0', then ignore this field. 7084 * b'19:21 - config_length_ctrl(CTRL) for CTRL: Each bit set represent 7085 * 64, 128, 256. 7086 * If all 3 bits are set config length is > 256. 7087 * if val is '0', then ignore this field. 7088 * b'22:24 - config_length_data(DATA) for DATA: Each bit set represent 7089 * 64, 128, 256. 7090 * If all 3 bits are set config length is > 256. 7091 * If val is '0', then ignore this field. 7092 * - b'25:31 - rsvd2: Reserved for future use 7093 * dword2 - b'0:2 - packet_type_enable_flags(E): MGMT, CTRL, DATA 7094 * b'3 - filter_in_tx_mpdu_start_mgmt(MPSM): 7095 * If packet_type_enable_flags is '1' for MGMT type, 7096 * monitor will ignore this bit and allow this TLV. 7097 * If packet_type_enable_flags is '0' for MGMT type, 7098 * monitor will use this bit to enable/disable logging 7099 * of this TLV. 7100 * b'4 - filter_in_tx_mpdu_start_ctrl(MPSC) 7101 * If packet_type_enable_flags is '1' for CTRL type, 7102 * monitor will ignore this bit and allow this TLV. 7103 * If packet_type_enable_flags is '0' for CTRL type, 7104 * monitor will use this bit to enable/disable logging 7105 * of this TLV. 7106 * b'5 - filter_in_tx_mpdu_start_data(MPSD) 7107 * If packet_type_enable_flags is '1' for DATA type, 7108 * monitor will ignore this bit and allow this TLV. 7109 * If packet_type_enable_flags is '0' for DATA type, 7110 * monitor will use this bit to enable/disable logging 7111 * of this TLV. 7112 * b'6 - filter_in_tx_msdu_start_mgmt(MSSM) 7113 * If packet_type_enable_flags is '1' for MGMT type, 7114 * monitor will ignore this bit and allow this TLV. 7115 * If packet_type_enable_flags is '0' for MGMT type, 7116 * monitor will use this bit to enable/disable logging 7117 * of this TLV. 7118 * b'7 - filter_in_tx_msdu_start_ctrl(MSSC) 7119 * If packet_type_enable_flags is '1' for CTRL type, 7120 * monitor will ignore this bit and allow this TLV. 7121 * If packet_type_enable_flags is '0' for CTRL type, 7122 * monitor will use this bit to enable/disable logging 7123 * of this TLV. 7124 * b'8 - filter_in_tx_msdu_start_data(MSSD) 7125 * If packet_type_enable_flags is '1' for DATA type, 7126 * monitor will ignore this bit and allow this TLV. 7127 * If packet_type_enable_flags is '0' for DATA type, 7128 * monitor will use this bit to enable/disable logging 7129 * of this TLV. 7130 * b'9 - filter_in_tx_mpdu_end_mgmt(MPEM) 7131 * If packet_type_enable_flags is '1' for MGMT type, 7132 * monitor will ignore this bit and allow this TLV. 7133 * If packet_type_enable_flags is '0' for MGMT type, 7134 * monitor will use this bit to enable/disable logging 7135 * of this TLV. 7136 * If filter_in_TX_MPDU_START = 1 it is recommended 7137 * to set this bit. 7138 * b'10 - filter_in_tx_mpdu_end_ctrl(MPEC) 7139 * If packet_type_enable_flags is '1' for CTRL type, 7140 * monitor will ignore this bit and allow this TLV. 7141 * If packet_type_enable_flags is '0' for CTRL type, 7142 * monitor will use this bit to enable/disable logging 7143 * of this TLV. 7144 * If filter_in_TX_MPDU_START = 1 it is recommended 7145 * to set this bit. 7146 * b'11 - filter_in_tx_mpdu_end_data(MPED) 7147 * If packet_type_enable_flags is '1' for DATA type, 7148 * monitor will ignore this bit and allow this TLV. 7149 * If packet_type_enable_flags is '0' for DATA type, 7150 * monitor will use this bit to enable/disable logging 7151 * of this TLV. 7152 * If filter_in_TX_MPDU_START = 1 it is recommended 7153 * to set this bit. 7154 * b'12 - filter_in_tx_msdu_end_mgmt(MSEM) 7155 * If packet_type_enable_flags is '1' for MGMT type, 7156 * monitor will ignore this bit and allow this TLV. 7157 * If packet_type_enable_flags is '0' for MGMT type, 7158 * monitor will use this bit to enable/disable logging 7159 * of this TLV. 7160 * If filter_in_TX_MSDU_START = 1 it is recommended 7161 * to set this bit. 7162 * b'13 - filter_in_tx_msdu_end_ctrl(MSEC) 7163 * If packet_type_enable_flags is '1' for CTRL type, 7164 * monitor will ignore this bit and allow this TLV. 7165 * If packet_type_enable_flags is '0' for CTRL type, 7166 * monitor will use this bit to enable/disable logging 7167 * of this TLV. 7168 * If filter_in_TX_MSDU_START = 1 it is recommended 7169 * to set this bit. 7170 * b'14 - filter_in_tx_msdu_end_data(MSED) 7171 * If packet_type_enable_flags is '1' for DATA type, 7172 * monitor will ignore this bit and allow this TLV. 7173 * If packet_type_enable_flags is '0' for DATA type, 7174 * monitor will use this bit to enable/disable logging 7175 * of this TLV. 7176 * If filter_in_TX_MSDU_START = 1 it is recommended 7177 * to set this bit. 7178 * b'15:31 - rsvd3: Reserved for future use 7179 * dword3 - b'0:31 - tlv_filter_mask_in0: 7180 * dword4 - b'0:31 - tlv_filter_mask_in1: 7181 * dword5 - b'0:31 - tlv_filter_mask_in2: 7182 * dword6 - b'0:31 - tlv_filter_mask_in3: 7183 * dword7 - b'0:7 - tx_fes_setup_word_mask: 7184 * - b'8:15 - tx_peer_entry_word_mask: 7185 * - b'16:23 - tx_queue_ext_word_mask: 7186 * - b'24:31 - tx_msdu_start_word_mask: 7187 * dword8 - b'0:31 - pcu_ppdu_setup_word_mask: 7188 * dword9 - b'0:7 - tx_mpdu_start_word_mask: 7189 * - b'8:15 - rxpcu_user_setup_word_mask: 7190 * - b'16:18 - pkt_type_enable_msdu_or_mpdu_logging (PT): 7191 * MGMT, CTRL, DATA 7192 * - b'19 - dma_mpdu_mgmt(M): For MGMT 7193 * 0 -> MSDU level logging is enabled 7194 * (valid only if bit is set in 7195 * pkt_type_enable_msdu_or_mpdu_logging) 7196 * 1 -> MPDU level logging is enabled 7197 * (valid only if bit is set in 7198 * pkt_type_enable_msdu_or_mpdu_logging) 7199 * - b'20 - dma_mpdu_ctrl(C) : For CTRL 7200 * 0 -> MSDU level logging is enabled 7201 * (valid only if bit is set in 7202 * pkt_type_enable_msdu_or_mpdu_logging) 7203 * 1 -> MPDU level logging is enabled 7204 * (valid only if bit is set in 7205 * pkt_type_enable_msdu_or_mpdu_logging) 7206 * - b'21 - dma_mpdu_data(D) : For DATA 7207 * 0 -> MSDU level logging is enabled 7208 * (valid only if bit is set in 7209 * pkt_type_enable_msdu_or_mpdu_logging) 7210 * 1 -> MPDU level logging is enabled 7211 * (valid only if bit is set in 7212 * pkt_type_enable_msdu_or_mpdu_logging) 7213 * - b'22:31 - rsvd4 for future use 7214 */ 7215 PREPACK struct htt_tx_monitor_cfg_t { 7216 A_UINT32 msg_type: 8, 7217 pdev_id: 8, 7218 ring_id: 8, 7219 status_swap: 1, 7220 pkt_swap: 1, 7221 tx_mon_global_en: 1, 7222 rsvd1: 5; 7223 A_UINT32 ring_buffer_size: 16, 7224 config_length_mgmt: 3, 7225 config_length_ctrl: 3, 7226 config_length_data: 3, 7227 rsvd2: 7; 7228 A_UINT32 pkt_type_enable_flags: 3, 7229 filter_in_tx_mpdu_start_mgmt: 1, 7230 filter_in_tx_mpdu_start_ctrl: 1, 7231 filter_in_tx_mpdu_start_data: 1, 7232 filter_in_tx_msdu_start_mgmt: 1, 7233 filter_in_tx_msdu_start_ctrl: 1, 7234 filter_in_tx_msdu_start_data: 1, 7235 filter_in_tx_mpdu_end_mgmt: 1, 7236 filter_in_tx_mpdu_end_ctrl: 1, 7237 filter_in_tx_mpdu_end_data: 1, 7238 filter_in_tx_msdu_end_mgmt: 1, 7239 filter_in_tx_msdu_end_ctrl: 1, 7240 filter_in_tx_msdu_end_data: 1, 7241 word_mask_compaction_enable: 1, 7242 rsvd3: 16; 7243 A_UINT32 tlv_filter_mask_in0; 7244 A_UINT32 tlv_filter_mask_in1; 7245 A_UINT32 tlv_filter_mask_in2; 7246 A_UINT32 tlv_filter_mask_in3; 7247 A_UINT32 tx_fes_setup_word_mask: 8, 7248 tx_peer_entry_word_mask: 8, 7249 tx_queue_ext_word_mask: 8, 7250 tx_msdu_start_word_mask: 8; 7251 A_UINT32 pcu_ppdu_setup_word_mask; 7252 A_UINT32 tx_mpdu_start_word_mask: 8, 7253 rxpcu_user_setup_word_mask: 8, 7254 pkt_type_enable_msdu_or_mpdu_logging: 3, 7255 dma_mpdu_mgmt: 1, 7256 dma_mpdu_ctrl: 1, 7257 dma_mpdu_data: 1, 7258 rsvd4: 10; 7259 A_UINT32 tx_queue_ext_v2_word_mask: 12, 7260 tx_peer_entry_v2_word_mask: 12, 7261 rsvd5: 8; 7262 A_UINT32 fes_status_end_word_mask: 16, 7263 response_end_status_word_mask: 16; 7264 A_UINT32 fes_status_prot_word_mask: 11, 7265 rsvd6: 21; 7266 } POSTPACK; 7267 7268 #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t)) 7269 7270 #define HTT_TX_MONITOR_CFG_PDEV_ID_M 0x0000ff00 7271 #define HTT_TX_MONITOR_CFG_PDEV_ID_S 8 7272 #define HTT_TX_MONITOR_CFG_PDEV_ID_GET(_var) \ 7273 (((_var) & HTT_TX_MONITOR_CFG_PDEV_ID_M) >> \ 7274 HTT_TX_MONITOR_CFG_PDEV_ID_S) 7275 #define HTT_TX_MONITOR_CFG_PDEV_ID_SET(_var, _val) \ 7276 do { \ 7277 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDEV_ID, _val); \ 7278 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDEV_ID_S)); \ 7279 } while (0) 7280 7281 #define HTT_TX_MONITOR_CFG_RING_ID_M 0x00ff0000 7282 #define HTT_TX_MONITOR_CFG_RING_ID_S 16 7283 #define HTT_TX_MONITOR_CFG_RING_ID_GET(_var) \ 7284 (((_var) & HTT_TX_MONITOR_CFG_RING_ID_M) >> \ 7285 HTT_TX_MONITOR_CFG_RING_ID_S) 7286 #define HTT_TX_MONITOR_CFG_RING_ID_SET(_var, _val) \ 7287 do { \ 7288 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_ID, _val); \ 7289 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_ID_S)); \ 7290 } while (0) 7291 7292 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_M 0x01000000 7293 #define HTT_TX_MONITOR_CFG_STATUS_SWAP_S 24 7294 #define HTT_TX_MONITOR_CFG_STATUS_TLV_GET(_var) \ 7295 (((_var) & HTT_TX_MONITOR_CFG_STATUS_SWAP_M) >> \ 7296 HTT_TX_MONITOR_CFG_STATUS_SWAP_S) 7297 #define HTT_TX_MONITOR_CFG_STATUS_TLV_SET(_var, _val) \ 7298 do { \ 7299 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_STATUS_SWAP, _val); \ 7300 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_STATUS_SWAP_S)); \ 7301 } while (0) 7302 7303 #define HTT_TX_MONITOR_CFG_PKT_SWAP_M 0x02000000 7304 #define HTT_TX_MONITOR_CFG_PKT_SWAP_S 25 7305 #define HTT_TX_MONITOR_CFG_PKT_TLV_GET(_var) \ 7306 (((_var) & HTT_TX_MONITOR_CFG_PKT_SWAP_M) >> \ 7307 HTT_TX_MONITOR_CFG_PKT_SWAP_S) 7308 #define HTT_TX_MONITOR_CFG_PKT_TLV_SET(_var, _val) \ 7309 do { \ 7310 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_SWAP, _val); \ 7311 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \ 7312 } while (0) 7313 7314 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M 0x04000000 7315 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S 26 7316 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_GET(_var) \ 7317 (((_var) & HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M) >> \ 7318 HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S) 7319 #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_SET(_var, _val) \ 7320 do { \ 7321 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN, _val); \ 7322 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)); \ 7323 } while (0) 7324 7325 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff 7326 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 7327 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ 7328 (((_var) & HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M) >> \ 7329 HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S) 7330 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ 7331 do { \ 7332 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE, _val); \ 7333 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)); \ 7334 } while (0) 7335 7336 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M 0x00070000 7337 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S 16 7338 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_GET(_var) \ 7339 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M) >> \ 7340 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S) 7341 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \ 7342 do { \ 7343 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT, _val); \ 7344 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \ 7345 } while (0) 7346 7347 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M 0x00380000 7348 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S 19 7349 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_GET(_var) \ 7350 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M) >> \ 7351 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S) 7352 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \ 7353 do { \ 7354 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL, _val); \ 7355 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)); \ 7356 } while (0) 7357 7358 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M 0x01C00000 7359 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S 22 7360 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_GET(_var) \ 7361 (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M) >> \ 7362 HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S) 7363 #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \ 7364 do { \ 7365 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA, _val); \ 7366 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)); \ 7367 } while (0) 7368 7369 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M 0x00000007 7370 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S 0 7371 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_GET(_var) \ 7372 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M) >> \ 7373 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S) 7374 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_SET(_var, _val) \ 7375 do { \ 7376 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS, _val); \ 7377 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)); \ 7378 } while (0) 7379 7380 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M 0x00000008 7381 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S 3 7382 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_GET(_var) \ 7383 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M) >> \ 7384 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S) 7385 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_SET(_var, _val) \ 7386 do { \ 7387 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT, _val); \ 7388 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S)); \ 7389 } while (0) 7390 7391 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M 0x00000010 7392 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S 4 7393 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_GET(_var) \ 7394 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M) >> \ 7395 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S) 7396 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_SET(_var, _val) \ 7397 do { \ 7398 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL, _val); \ 7399 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)); \ 7400 } while (0) 7401 7402 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M 0x00000020 7403 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S 5 7404 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_GET(_var) \ 7405 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M) >> \ 7406 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S) 7407 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_SET(_var, _val) \ 7408 do { \ 7409 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA, _val); \ 7410 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S)); \ 7411 } while (0) 7412 7413 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M 0x00000040 7414 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S 6 7415 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_GET(_var) \ 7416 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M) >> \ 7417 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S) 7418 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_SET(_var, _val) \ 7419 do { \ 7420 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT, _val); \ 7421 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S)); \ 7422 } while (0) 7423 7424 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M 0x00000080 7425 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S 7 7426 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_GET(_var) \ 7427 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M) >> \ 7428 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S) 7429 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_SET(_var, _val) \ 7430 do { \ 7431 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL, _val); \ 7432 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)); \ 7433 } while (0) 7434 7435 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M 0x00000100 7436 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S 8 7437 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_GET(_var) \ 7438 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M) >> \ 7439 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S) 7440 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_SET(_var, _val) \ 7441 do { \ 7442 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA, _val); \ 7443 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S)); \ 7444 } while (0) 7445 7446 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M 0x00000200 7447 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S 9 7448 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_GET(_var) \ 7449 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M) >> \ 7450 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S) 7451 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_SET(_var, _val) \ 7452 do { \ 7453 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT, _val); \ 7454 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S)); \ 7455 } while (0) 7456 7457 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M 0x00000400 7458 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S 10 7459 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_GET(_var) \ 7460 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M) >> \ 7461 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S) 7462 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_SET(_var, _val) \ 7463 do { \ 7464 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL, _val); \ 7465 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)); \ 7466 } while (0) 7467 7468 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M 0x00000800 7469 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S 11 7470 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_GET(_var) \ 7471 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M) >> \ 7472 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S) 7473 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_SET(_var, _val) \ 7474 do { \ 7475 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA, _val); \ 7476 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S)); \ 7477 } while (0) 7478 7479 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M 0x00001000 7480 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S 12 7481 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_GET(_var) \ 7482 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M) >> \ 7483 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S) 7484 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_SET(_var, _val) \ 7485 do { \ 7486 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT, _val); \ 7487 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S)); \ 7488 } while (0) 7489 7490 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M 0x00002000 7491 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S 13 7492 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_GET(_var) \ 7493 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M) >> \ 7494 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S) 7495 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_SET(_var, _val) \ 7496 do { \ 7497 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL, _val); \ 7498 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)); \ 7499 } while (0) 7500 7501 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M 0x00004000 7502 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S 14 7503 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_GET(_var) \ 7504 (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M) >> \ 7505 HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S) 7506 #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_SET(_var, _val) \ 7507 do { \ 7508 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA, _val); \ 7509 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \ 7510 } while (0) 7511 7512 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000 7513 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15 7514 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ 7515 (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ 7516 HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S) 7517 #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ 7518 do { \ 7519 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ 7520 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ 7521 } while (0) 7522 7523 7524 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff 7525 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0 7526 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \ 7527 (((_var) & HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M) >> \ 7528 HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S) 7529 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_SET(_var, _val) \ 7530 do { \ 7531 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TLV_FILTER_MASK, _val); \ 7532 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)); \ 7533 } while (0) 7534 7535 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M 0x000000ff 7536 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S 0 7537 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_GET(_var) \ 7538 (((_var) & HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M) >> \ 7539 HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S) 7540 #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_SET(_var, _val) \ 7541 do { \ 7542 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK, _val); \ 7543 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)); \ 7544 } while (0) 7545 7546 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M 0x0000ff00 7547 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S 8 7548 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_GET(_var) \ 7549 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M) >> \ 7550 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S) 7551 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_SET(_var, _val) \ 7552 do { \ 7553 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK, _val); \ 7554 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)); \ 7555 } while (0) 7556 7557 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M 0x00ff0000 7558 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S 16 7559 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_GET(_var) \ 7560 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M) >> \ 7561 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S) 7562 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_SET(_var, _val) \ 7563 do { \ 7564 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK, _val); \ 7565 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)); \ 7566 } while (0) 7567 7568 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M 0xff000000 7569 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S 24 7570 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_GET(_var) \ 7571 (((_var) & HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M) >> \ 7572 HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S) 7573 #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_SET(_var, _val) \ 7574 do { \ 7575 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK, _val); \ 7576 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)); \ 7577 } while (0) 7578 7579 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M 0xffffffff 7580 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S 0 7581 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_GET(_var) \ 7582 (((_var) & HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M) >> \ 7583 HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S) 7584 #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_SET(_var, _val) \ 7585 do { \ 7586 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK, _val); \ 7587 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)); \ 7588 } while (0) 7589 7590 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M 0x000000ff 7591 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S 0 7592 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_GET(_var) \ 7593 (((_var) & HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M) >> \ 7594 HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S) 7595 #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_SET(_var, _val) \ 7596 do { \ 7597 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK, _val); \ 7598 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)); \ 7599 } while (0) 7600 7601 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M 0x0000ff00 7602 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S 8 7603 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_GET(_var) \ 7604 (((_var) & HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M) >> \ 7605 HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S) 7606 #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_SET(_var, _val) \ 7607 do { \ 7608 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK, _val); \ 7609 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)); \ 7610 } while (0) 7611 7612 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00070000 7613 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S 16 7614 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \ 7615 (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \ 7616 HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S) 7617 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \ 7618 do { \ 7619 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK, _val); \ 7620 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)); \ 7621 } while (0) 7622 7623 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M 0x00080000 7624 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S 19 7625 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_GET(_var) \ 7626 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M) >> \ 7627 HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S) 7628 #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_SET(_var, _val) \ 7629 do { \ 7630 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT, _val); \ 7631 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S)); \ 7632 } while (0) 7633 7634 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M 0x00100000 7635 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S 20 7636 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_GET(_var) \ 7637 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M) >> \ 7638 HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S) 7639 #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_SET(_var, _val) \ 7640 do { \ 7641 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL, _val); \ 7642 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S)); \ 7643 } while (0) 7644 7645 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M 0x00200000 7646 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S 21 7647 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_GET(_var) \ 7648 (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M) >> \ 7649 HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S) 7650 #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_SET(_var, _val) \ 7651 do { \ 7652 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_DATA, _val); \ 7653 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \ 7654 } while (0) 7655 7656 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M 0x00000fff 7657 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S 0 7658 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \ 7659 (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \ 7660 HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S) 7661 #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \ 7662 do { \ 7663 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \ 7664 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \ 7665 } while (0) 7666 7667 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M 0x00fff000 7668 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S 12 7669 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \ 7670 (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \ 7671 HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S) 7672 #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \ 7673 do { \ 7674 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \ 7675 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \ 7676 } while (0) 7677 7678 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M 0x0000ffff 7679 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S 0 7680 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \ 7681 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \ 7682 HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S) 7683 #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \ 7684 do { \ 7685 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \ 7686 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \ 7687 } while (0) 7688 7689 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M 0xffff0000 7690 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S 16 7691 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \ 7692 (((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \ 7693 HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S) 7694 #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \ 7695 do { \ 7696 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \ 7697 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \ 7698 } while (0) 7699 7700 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M 0x000007ff 7701 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S 0 7702 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \ 7703 (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \ 7704 HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S) 7705 #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \ 7706 do { \ 7707 HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \ 7708 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \ 7709 } while (0) 7710 7711 /* 7712 * pkt_type_enable_flags 7713 */ 7714 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_M 0x00000001 7715 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_S 0 7716 7717 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_M 0x00000002 7718 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_S 1 7719 7720 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_M 0x00000004 7721 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_S 2 7722 7723 /* 7724 * PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING 7725 */ 7726 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_M 0x00010000 7727 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_S 16 7728 7729 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_M 0x00020000 7730 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_S 17 7731 7732 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_M 0x00040000 7733 #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_S 18 7734 7735 #define HTT_TX_MONITOR_CFG_PKT_TYPE_SET(word, httsym, value) \ 7736 do { \ 7737 HTT_CHECK_SET_VAL(httsym, value); \ 7738 (word) |= (value) << httsym##_S; \ 7739 } while (0) 7740 #define HTT_TX_MONITOR_CFG_PKT_TYPE_GET(word, httsym) \ 7741 (((word) & httsym##_M) >> httsym##_S) 7742 7743 /* mode -> ENABLE_FLAGS, ENABLE_MSDU_OR_MPDU_LOGGING 7744 * type -> MGMT, CTRL, DATA*/ 7745 7746 #define htt_tx_ring_pkt_type_set( \ 7747 word, mode, type, val) \ 7748 HTT_TX_MONITOR_CFG_PKT_TYPE_SET( \ 7749 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type, val) 7750 7751 #define htt_tx_ring_pkt_type_get( \ 7752 word, mode, type) \ 7753 HTT_TX_MONITOR_CFG_PKT_TYPE_GET( \ 7754 word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type) 7755 7756 /* Definition to filter in TLVs */ 7757 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_M 0x00000001 7758 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_S 0 7759 7760 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_M 0x00000002 7761 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_S 1 7762 7763 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_M 0x00000004 7764 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_S 2 7765 7766 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_M 0x00000008 7767 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_S 3 7768 7769 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_M 0x00000010 7770 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_S 4 7771 7772 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_M 0x00000020 7773 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_S 5 7774 7775 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_M 0x00000040 7776 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_S 6 7777 7778 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_M 0x00000080 7779 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_S 7 7780 7781 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_M 0x00000100 7782 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_S 8 7783 7784 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_M 0x00000200 7785 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_S 9 7786 7787 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_M 0x00000400 7788 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_S 10 7789 7790 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_M 0x00000800 7791 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_S 11 7792 7793 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_M 0x00001000 7794 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_S 12 7795 7796 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_M 0x00002000 7797 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_S 13 7798 7799 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_M 0x00004000 7800 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_S 14 7801 7802 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_M 0x00008000 7803 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_S 15 7804 7805 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_M 0x00010000 7806 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_S 16 7807 7808 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_M 0x00020000 7809 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_S 17 7810 7811 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_M 0x00040000 7812 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_S 18 7813 7814 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_M 0x00080000 7815 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_S 19 7816 7817 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_M 0x00100000 7818 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_S 20 7819 7820 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_M 0x00200000 7821 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_S 21 7822 7823 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_M 0x00400000 7824 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_S 22 7825 7826 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_M 0x00800000 7827 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_S 23 7828 7829 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_M 0x01000000 7830 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_S 24 7831 7832 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_M 0x02000000 7833 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_S 25 7834 7835 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_M 0x04000000 7836 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_S 26 7837 7838 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_M 0x08000000 7839 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_S 27 7840 7841 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_M 0x10000000 7842 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_S 28 7843 7844 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_M 0x20000000 7845 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_S 29 7846 7847 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_M 0x40000000 7848 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_S 30 7849 7850 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_M 0x80000000 7851 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_S 31 7852 7853 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET(word, httsym, enable) \ 7854 do { \ 7855 HTT_CHECK_SET_VAL(httsym, enable); \ 7856 (word) |= (enable) << httsym##_S; \ 7857 } while (0) 7858 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET(word, httsym) \ 7859 (((word) & httsym##_M) >> httsym##_S) 7860 7861 #define htt_tx_monitor_tlv_filter_in0_enable_set(word, tlv, enable) \ 7862 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET( \ 7863 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv, enable) 7864 7865 #define htt_tx_monitor_tlv_filter_in0_enable_get(word, tlv) \ 7866 HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET( \ 7867 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv) 7868 7869 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_M 0x00000001 7870 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_S 0 7871 7872 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_M 0x00000002 7873 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_S 1 7874 7875 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_M 0x00000004 7876 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_S 2 7877 7878 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_M 0x00000008 7879 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_S 3 7880 7881 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_M 0x00000010 7882 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_S 4 7883 7884 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_M 0x00000020 7885 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_S 5 7886 7887 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_M 0x00000040 7888 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_S 6 7889 7890 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_M 0x00000080 7891 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_S 7 7892 7893 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_M 0x00000100 7894 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_S 8 7895 7896 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_M 0x00000200 7897 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_S 9 7898 7899 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_M 0x00000400 7900 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_S 10 7901 7902 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_M 0x00000800 7903 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_S 11 7904 7905 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_M 0x00001000 7906 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_S 12 7907 7908 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_M 0x00002000 7909 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_S 13 7910 7911 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_M 0x00004000 7912 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_S 14 7913 7914 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_M 0x00008000 7915 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_S 15 7916 7917 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_M 0x00010000 7918 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_S 16 7919 7920 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_M 0x00020000 7921 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_S 17 7922 7923 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_M 0x00040000 7924 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_S 18 7925 7926 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_M 0x00080000 7927 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_S 19 7928 7929 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_M 0x00100000 7930 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_S 20 7931 7932 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_M 0x00200000 7933 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_S 21 7934 7935 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_M 0x00400000 7936 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_S 22 7937 7938 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_M 0x00800000 7939 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_S 23 7940 7941 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_M 0x01000000 7942 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_S 24 7943 7944 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_M 0x02000000 7945 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_S 25 7946 7947 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_M 0x04000000 7948 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_S 26 7949 7950 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_M 0x08000000 7951 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_S 27 7952 7953 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_M 0x10000000 7954 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_S 28 7955 7956 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_M 0x20000000 7957 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_S 29 7958 7959 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_M 0x40000000 7960 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_S 30 7961 7962 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_M 0x80000000 7963 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_S 31 7964 7965 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET(word, httsym, enable) \ 7966 do { \ 7967 HTT_CHECK_SET_VAL(httsym, enable); \ 7968 (word) |= (enable) << httsym##_S; \ 7969 } while (0) 7970 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET(word, httsym) \ 7971 (((word) & httsym##_M) >> httsym##_S) 7972 7973 #define htt_tx_monitor_tlv_filter_in1_enable_set(word, tlv, enable) \ 7974 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET( \ 7975 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv, enable) 7976 7977 #define htt_tx_monitor_tlv_filter_in1_enable_get(word, tlv) \ 7978 HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET( \ 7979 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv) 7980 7981 7982 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_M 0x00000001 7983 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_S 0 7984 7985 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_M 0x00000002 7986 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_S 1 7987 7988 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_M 0x00000004 7989 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_S 2 7990 7991 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_M 0x00000008 7992 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_S 3 7993 7994 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_M 0x00000010 7995 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_S 4 7996 7997 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_M 0x00000020 7998 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_S 5 7999 8000 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_M 0x00000040 8001 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_S 6 8002 8003 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_M 0x00000080 8004 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_S 7 8005 8006 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_M 0x00000100 8007 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_S 8 8008 8009 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_M 0x00000200 8010 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_S 9 8011 8012 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_M 0x00000400 8013 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_S 10 8014 8015 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_M 0x00000800 8016 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_S 11 8017 8018 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_M 0x00001000 8019 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_S 12 8020 8021 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_M 0x00002000 8022 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_S 13 8023 8024 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_M 0x00004000 8025 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_S 14 8026 8027 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_M 0x00008000 8028 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_S 15 8029 8030 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_M 0x00010000 8031 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_S 16 8032 8033 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_M 0x00020000 8034 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_S 17 8035 8036 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_M 0x00040000 8037 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_S 18 8038 8039 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_M 0x00080000 8040 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_S 19 8041 8042 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_M 0x00100000 8043 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_S 20 8044 8045 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_M 0x00200000 8046 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_S 21 8047 8048 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_M 0x00400000 8049 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_S 22 8050 8051 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_M 0x00800000 8052 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_S 23 8053 8054 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_M 0x01000000 8055 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_S 24 8056 8057 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_M 0x02000000 8058 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_S 25 8059 8060 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_M 0x04000000 8061 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_S 26 8062 8063 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_M 0x08000000 8064 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_S 27 8065 8066 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_M 0x10000000 8067 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_S 28 8068 8069 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_M 0x20000000 8070 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_S 29 8071 8072 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_M 0x40000000 8073 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_S 30 8074 8075 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_M 0x80000000 8076 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_S 31 8077 8078 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET(word, httsym, enable) \ 8079 do { \ 8080 HTT_CHECK_SET_VAL(httsym, enable); \ 8081 (word) |= (enable) << httsym##_S; \ 8082 } while (0) 8083 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET(word, httsym) \ 8084 (((word) & httsym##_M) >> httsym##_S) 8085 8086 #define htt_tx_monitor_tlv_filter_in2_enable_set(word, tlv, enable) \ 8087 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET( \ 8088 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv, enable) 8089 8090 #define htt_tx_monitor_tlv_filter_in2_enable_get(word, tlv) \ 8091 HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET( \ 8092 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv) 8093 8094 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_M 0x00000001 8095 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_S 0 8096 8097 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_M 0x00000002 8098 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_S 1 8099 8100 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_M 0x00000004 8101 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_S 2 8102 8103 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_M 0x00000008 8104 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_S 3 8105 8106 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_M 0x00000010 8107 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_S 4 8108 8109 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_M 0x00000020 8110 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_S 5 8111 8112 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_M 0x00000040 8113 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_S 6 8114 8115 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_M 0x00000080 8116 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_S 7 8117 8118 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_M 0x00000100 8119 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_S 8 8120 8121 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_M 0x00000200 8122 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_S 9 8123 8124 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_M 0x00000400 8125 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_S 10 8126 8127 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_M 0x00000800 8128 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_S 11 8129 8130 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_M 0x00001000 8131 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_S 12 8132 8133 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_M 0x00002000 8134 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_S 13 8135 8136 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_M 0x00004000 8137 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_S 14 8138 8139 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_M 0x00008000 8140 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_S 15 8141 8142 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_M 0x00010000 8143 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_S 16 8144 8145 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_M 0x00020000 8146 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_S 17 8147 8148 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_M 0x00040000 8149 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_S 18 8150 8151 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_M 0x00080000 8152 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_S 19 8153 8154 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_M 0x00100000 8155 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_S 20 8156 8157 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_M 0x00200000 8158 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_S 21 8159 8160 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET(word, httsym, enable) \ 8161 do { \ 8162 HTT_CHECK_SET_VAL(httsym, enable); \ 8163 (word) |= (enable) << httsym##_S; \ 8164 } while (0) 8165 #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET(word, httsym) \ 8166 (((word) & httsym##_M) >> httsym##_S) 8167 8168 #define htt_tx_monitor_tlv_filter_in3_enable_set(word, tlv, enable) \ 8169 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET( \ 8170 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv, enable) 8171 8172 #define htt_tx_monitor_tlv_filter_in3_enable_get(word, tlv) \ 8173 HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET( \ 8174 word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv) 8175 8176 /** 8177 * @brief host --> target Receive Flow Steering configuration message definition 8178 * 8179 * MSG_TYPE => HTT_H2T_MSG_TYPE_RFS_CONFIG 8180 * 8181 * host --> target Receive Flow Steering configuration message definition. 8182 * Host must send this message before sending HTT_H2T_MSG_TYPE_RX_RING_CFG. 8183 * The reason for this is we want RFS to be configured and ready before MAC 8184 * remote ring is enabled via HTT_H2T_MSG_TYPE_RX_RING_CFG. 8185 * 8186 * |31 24|23 16|15 9|8|7 0| 8187 * |----------------+----------------+----------------+----------------| 8188 * | reserved |E| msg type | 8189 * |-------------------------------------------------------------------| 8190 * Where E = RFS enable flag 8191 * 8192 * The RFS_CONFIG message consists of a single 4-byte word. 8193 * 8194 * Header fields: 8195 * - MSG_TYPE 8196 * Bits 7:0 8197 * Purpose: identifies this as a RFS config msg 8198 * Value: 0xf (HTT_H2T_MSG_TYPE_RFS_CONFIG) 8199 * - RFS_CONFIG 8200 * Bit 8 8201 * Purpose: Tells target whether to enable (1) or disable (0) 8202 * flow steering feature when sending rx indication messages to host 8203 */ 8204 #define HTT_H2T_RFS_CONFIG_M 0x100 8205 #define HTT_H2T_RFS_CONFIG_S 8 8206 #define HTT_RX_RFS_CONFIG_GET(_var) \ 8207 (((_var) & HTT_H2T_RFS_CONFIG_M) >> \ 8208 HTT_H2T_RFS_CONFIG_S) 8209 #define HTT_RX_RFS_CONFIG_SET(_var, _val) \ 8210 do { \ 8211 HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \ 8212 ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \ 8213 } while (0) 8214 8215 #define HTT_RFS_CFG_REQ_BYTES 4 8216 8217 8218 /** 8219 * @brief host -> target FW extended statistics request 8220 * 8221 * MSG_TYPE => HTT_H2T_MSG_TYPE_EXT_STATS_REQ 8222 * 8223 * @details 8224 * The following field definitions describe the format of the HTT host 8225 * to target FW extended stats retrieve message. 8226 * The message specifies the type of stats the host wants to retrieve. 8227 * 8228 * |31 24|23 16|15 8|7 0| 8229 * |-----------------------------------------------------------| 8230 * | reserved | stats type | pdev_mask | msg type | 8231 * |-----------------------------------------------------------| 8232 * | config param [0] | 8233 * |-----------------------------------------------------------| 8234 * | config param [1] | 8235 * |-----------------------------------------------------------| 8236 * | config param [2] | 8237 * |-----------------------------------------------------------| 8238 * | config param [3] | 8239 * |-----------------------------------------------------------| 8240 * | reserved | 8241 * |-----------------------------------------------------------| 8242 * | cookie LSBs | 8243 * |-----------------------------------------------------------| 8244 * | cookie MSBs | 8245 * |-----------------------------------------------------------| 8246 * Header fields: 8247 * - MSG_TYPE 8248 * Bits 7:0 8249 * Purpose: identifies this is a extended stats upload request message 8250 * Value: 0x10 (HTT_H2T_MSG_TYPE_EXT_STATS_REQ) 8251 * - PDEV_MASK 8252 * Bits 8:15 8253 * Purpose: identifies the mask of PDEVs to retrieve stats from 8254 * Value: This is a overloaded field, refer to usage and interpretation of 8255 * PDEV in interface document. 8256 * Bit 8 : Reserved for SOC stats 8257 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8258 * Indicates MACID_MASK in DBS 8259 * - STATS_TYPE 8260 * Bits 23:16 8261 * Purpose: identifies which FW statistics to upload 8262 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8263 * - Reserved 8264 * Bits 31:24 8265 * - CONFIG_PARAM [0] 8266 * Bits 31:0 8267 * Purpose: give an opaque configuration value to the specified stats type 8268 * Value: stats-type specific configuration value 8269 * Refer to htt_stats.h for interpretation for each stats sub_type 8270 * - CONFIG_PARAM [1] 8271 * Bits 31:0 8272 * Purpose: give an opaque configuration value to the specified stats type 8273 * Value: stats-type specific configuration value 8274 * Refer to htt_stats.h for interpretation for each stats sub_type 8275 * - CONFIG_PARAM [2] 8276 * Bits 31:0 8277 * Purpose: give an opaque configuration value to the specified stats type 8278 * Value: stats-type specific configuration value 8279 * Refer to htt_stats.h for interpretation for each stats sub_type 8280 * - CONFIG_PARAM [3] 8281 * Bits 31:0 8282 * Purpose: give an opaque configuration value to the specified stats type 8283 * Value: stats-type specific configuration value 8284 * Refer to htt_stats.h for interpretation for each stats sub_type 8285 * - Reserved [31:0] for future use. 8286 * - COOKIE_LSBS 8287 * Bits 31:0 8288 * Purpose: Provide a mechanism to match a target->host stats confirmation 8289 * message with its preceding host->target stats request message. 8290 * Value: LSBs of the opaque cookie specified by the host-side requestor 8291 * - COOKIE_MSBS 8292 * Bits 31:0 8293 * Purpose: Provide a mechanism to match a target->host stats confirmation 8294 * message with its preceding host->target stats request message. 8295 * Value: MSBs of the opaque cookie specified by the host-side requestor 8296 */ 8297 8298 #define HTT_H2T_EXT_STATS_REQ_MSG_SZ 32 /* bytes */ 8299 8300 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M 0x0000ff00 8301 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S 8 8302 8303 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M 0x00ff0000 8304 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S 16 8305 8306 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M 0xffffffff 8307 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S 0 8308 8309 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_GET(_var) \ 8310 (((_var) & HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M) >> \ 8311 HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S) 8312 #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_SET(_var, _val) \ 8313 do { \ 8314 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_PDEV_MASK, _val); \ 8315 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S)); \ 8316 } while (0) 8317 8318 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_GET(_var) \ 8319 (((_var) & HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M) >> \ 8320 HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S) 8321 #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8322 do { \ 8323 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_STATS_TYPE, _val); \ 8324 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S)); \ 8325 } while (0) 8326 8327 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_GET(_var) \ 8328 (((_var) & HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M) >> \ 8329 HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S) 8330 #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_SET(_var, _val) \ 8331 do { \ 8332 HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM, _val); \ 8333 ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S)); \ 8334 } while (0) 8335 8336 /** 8337 * @brief host -> target FW streaming statistics request 8338 * 8339 * MSG_TYPE => HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ 8340 * 8341 * @details 8342 * The following field definitions describe the format of the HTT host 8343 * to target message that requests the target to start or stop producing 8344 * ongoing stats of the specified type. 8345 * 8346 * |31|30 |23 16|15 8|7 0| 8347 * |-----------------------------------------------------------| 8348 * |EN| reserved | stats type | reserved | msg type | 8349 * |-----------------------------------------------------------| 8350 * | config param [0] | 8351 * |-----------------------------------------------------------| 8352 * | config param [1] | 8353 * |-----------------------------------------------------------| 8354 * | config param [2] | 8355 * |-----------------------------------------------------------| 8356 * | config param [3] | 8357 * |-----------------------------------------------------------| 8358 * Where: 8359 * - EN is an enable/disable flag 8360 * Header fields: 8361 * - MSG_TYPE 8362 * Bits 7:0 8363 * Purpose: identifies this is a streaming stats upload request message 8364 * Value: 0x20 (HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ) 8365 * - STATS_TYPE 8366 * Bits 23:16 8367 * Purpose: identifies which FW statistics to upload 8368 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 8369 * Only the htt_dbg_ext_stats_type values identified as streaming 8370 * stats are valid to specify in this STEAMING_STATS_REQ message. 8371 * - ENABLE 8372 * Bit 31 8373 * Purpose: enable/disable the target's ongoing stats of the specified type 8374 * Value: 8375 * 0 - disable ongoing production of the specified stats type 8376 * 1 - enable ongoing production of the specified stats type 8377 * - CONFIG_PARAM [0] 8378 * Bits 31:0 8379 * Purpose: give an opaque configuration value to the specified stats type 8380 * Value: stats-type specific configuration value 8381 * Refer to htt_stats.h for interpretation for each stats sub_type 8382 * - CONFIG_PARAM [1] 8383 * Bits 31:0 8384 * Purpose: give an opaque configuration value to the specified stats type 8385 * Value: stats-type specific configuration value 8386 * Refer to htt_stats.h for interpretation for each stats sub_type 8387 * - CONFIG_PARAM [2] 8388 * Bits 31:0 8389 * Purpose: give an opaque configuration value to the specified stats type 8390 * Value: stats-type specific configuration value 8391 * Refer to htt_stats.h for interpretation for each stats sub_type 8392 * - CONFIG_PARAM [3] 8393 * Bits 31:0 8394 * Purpose: give an opaque configuration value to the specified stats type 8395 * Value: stats-type specific configuration value 8396 * Refer to htt_stats.h for interpretation for each stats sub_type 8397 */ 8398 8399 #define HTT_H2T_STREAMING_STATS_REQ_MSG_SZ 20 /* bytes */ 8400 8401 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M 0x00ff0000 8402 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S 16 8403 8404 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_M 0x80000000 8405 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_S 31 8406 8407 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_GET(_var) \ 8408 (((_var) & HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M) >> \ 8409 HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S) 8410 #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_SET(_var, _val) \ 8411 do { \ 8412 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE, _val); \ 8413 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S)); \ 8414 } while (0) 8415 8416 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_GET(_var) \ 8417 (((_var) & HTT_H2T_STREAMING_STATS_REQ_ENABLE_M) >> \ 8418 HTT_H2T_STREAMING_STATS_REQ_ENABLE_S) 8419 #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_SET(_var, _val) \ 8420 do { \ 8421 HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_ENABLE, _val); \ 8422 ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_ENABLE_S)); \ 8423 } while (0) 8424 8425 /** 8426 * @brief host -> target FW PPDU_STATS request message 8427 * 8428 * MSG_TYPE => HTT_H2T_MSG_TYPE_PPDU_STATS_CFG 8429 * 8430 * @details 8431 * The following field definitions describe the format of the HTT host 8432 * to target FW for PPDU_STATS_CFG msg. 8433 * The message allows the host to configure the PPDU_STATS_IND messages 8434 * produced by the target. 8435 * 8436 * |31 24|23 16|15 8|7 0| 8437 * |-----------------------------------------------------------| 8438 * | REQ bit mask | pdev_mask | msg type | 8439 * |-----------------------------------------------------------| 8440 * Header fields: 8441 * - MSG_TYPE 8442 * Bits 7:0 8443 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 8444 * Value: 0x11 (HTT_H2T_MSG_TYPE_PPDU_STATS_CFG) 8445 * - PDEV_MASK 8446 * Bits 8:15 8447 * Purpose: identifies which pdevs this PPDU stats configuration applies to 8448 * Value: This is a overloaded field, refer to usage and interpretation of 8449 * PDEV in interface document. 8450 * Bit 8 : Reserved for SOC stats 8451 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 8452 * Indicates MACID_MASK in DBS 8453 * - REQ_TLV_BIT_MASK 8454 * Bits 16:31 8455 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 8456 * needs to be included in the target's PPDU_STATS_IND messages. 8457 * Value: refer htt_ppdu_stats_tlv_tag_t 8458 * 8459 */ 8460 #define HTT_H2T_PPDU_STATS_CFG_MSG_SZ 4 /* bytes */ 8461 8462 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M 0x0000ff00 8463 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S 8 8464 8465 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M 0xffff0000 8466 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S 16 8467 8468 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_GET(_var) \ 8469 (((_var) & HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M) >> \ 8470 HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S) 8471 8472 #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_SET(_var, _val) \ 8473 do { \ 8474 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_PDEV_MASK, _val); \ 8475 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S)); \ 8476 } while (0) 8477 8478 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_GET(_var) \ 8479 (((_var) & HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M) >> \ 8480 HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S) 8481 8482 #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_SET(_var, _val) \ 8483 do { \ 8484 HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK, _val); \ 8485 ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \ 8486 } while (0) 8487 8488 /** 8489 * @brief Host-->target HTT RX FSE setup message 8490 * 8491 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG 8492 * 8493 * @details 8494 * Through this message, the host will provide details of the flow tables 8495 * in host DDR along with hash keys. 8496 * This message can be sent per SOC or per PDEV, which is differentiated 8497 * by pdev id values. 8498 * The host will allocate flow search table and sends table size, 8499 * physical DMA address of flow table, and hash keys to firmware to 8500 * program into the RXOLE FSE HW block. 8501 * 8502 * The following field definitions describe the format of the RX FSE setup 8503 * message sent from the host to target 8504 * 8505 * Header fields: 8506 * dword0 - b'7:0 - msg_type: This will be set to 8507 * 0x12 (HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG) 8508 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8509 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8510 * pdev's LMAC ring. 8511 * b'31:16 - reserved : Reserved for future use 8512 * dword1 - b'19:0 - number of records: This field indicates the number of 8513 * entries in the flow table. For example: 8k number of 8514 * records is equivalent to 8515 * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT) 8516 * b'27:20 - max search: This field specifies the skid length to FSE 8517 * parser HW module whenever match is not found at the 8518 * exact index pointed by hash. 8519 * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used. 8520 * Refer htt_ip_da_sa_prefix below for more details. 8521 * b'31:30 - reserved: Reserved for future use 8522 * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow 8523 * table allocated by host in DDR 8524 * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow 8525 * table allocated by host in DDR 8526 * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table 8527 * entry hashing 8528 * 8529 * 8530 * |31 30|29 28|27|26|25 20|19 16|15 8|7 0| 8531 * |---------------------------------------------------------------| 8532 * | reserved | pdev_id | MSG_TYPE | 8533 * |---------------------------------------------------------------| 8534 * |resvd|IPDSA| max_search | Number of records | 8535 * |---------------------------------------------------------------| 8536 * | base address lo | 8537 * |---------------------------------------------------------------| 8538 * | base address high | 8539 * |---------------------------------------------------------------| 8540 * | toeplitz key 31_0 | 8541 * |---------------------------------------------------------------| 8542 * | toeplitz key 63_32 | 8543 * |---------------------------------------------------------------| 8544 * | toeplitz key 95_64 | 8545 * |---------------------------------------------------------------| 8546 * | toeplitz key 127_96 | 8547 * |---------------------------------------------------------------| 8548 * | toeplitz key 159_128 | 8549 * |---------------------------------------------------------------| 8550 * | toeplitz key 191_160 | 8551 * |---------------------------------------------------------------| 8552 * | toeplitz key 223_192 | 8553 * |---------------------------------------------------------------| 8554 * | toeplitz key 255_224 | 8555 * |---------------------------------------------------------------| 8556 * | toeplitz key 287_256 | 8557 * |---------------------------------------------------------------| 8558 * | reserved | toeplitz key 314_288(26:0 bits) | 8559 * |---------------------------------------------------------------| 8560 * where: 8561 * IPDSA = ip_da_sa 8562 */ 8563 8564 /** 8565 * @brief: htt_ip_da_sa_prefix 8566 * 0x0 -> Prefix is 0x20010db8_00000000_00000000 8567 * IPv6 addresses beginning with 0x20010db8 are reserved for 8568 * documentation per RFC3849 8569 * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6 8570 * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6 8571 * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix 8572 */ 8573 8574 enum htt_ip_da_sa_prefix { 8575 HTT_RX_IPV6_20010db8, 8576 HTT_RX_IPV4_MAPPED_IPV6, 8577 HTT_RX_IPV4_COMPATIBLE_IPV6, 8578 HTT_RX_IPV6_64FF9B, 8579 }; 8580 8581 8582 /** 8583 * @brief Host-->target HTT RX FISA configure and enable 8584 * 8585 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FISA_CFG 8586 * 8587 * @details 8588 * The host will send this command down to configure and enable the FISA 8589 * operational params. 8590 * Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH 8591 * register. 8592 * Should configure both the MACs. 8593 * 8594 * dword0 - b'7:0 - msg_type: 8595 * This will be set to 0x15 (HTT_H2T_MSG_TYPE_RX_FISA_CFG) 8596 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 8597 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that 8598 * pdev's LMAC ring. 8599 * b'31:16 - reserved : Reserved for future use 8600 * 8601 * dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable 8602 * b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC 8603 * packets. 1 flow search will be skipped 8604 * b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non 8605 * tcp,udp packets 8606 * b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length 8607 * calculation 8608 * b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length 8609 * calculation 8610 * b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length 8611 * calculation 8612 * b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation 8613 * b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP 8614 * length 8615 * 0 L4 checksum will be provided in the RX_MSDU_END tlv 8616 * 1 IPV4 hdr checksum after adjusting for cumulative IP 8617 * length 8618 * b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence 8619 * num jump 8620 * b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence 8621 * num jump 8622 * b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos 8623 * data type switch has happened for MPDU Sequence num jump 8624 * b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type 8625 * for MPDU Sequence num jump 8626 * b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands 8627 * for decrypt errors 8628 * b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop 8629 * while aggregating a msdu 8630 * b'17:14 - LIMIT, Aggregtion limit for number of MSDUs. 8631 * The aggregation is done until (number of MSDUs aggregated 8632 * < LIMIT + 1) 8633 * b'31:18 - Reserved 8634 * 8635 * fisa_control_value - 32bit value FW can write to register 8636 * 8637 * dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation 8638 * Threshold value for FISA timeout (units are microseconds). 8639 * When the global timestamp exceeds this threshold, FISA 8640 * aggregation will be restarted. 8641 * A value of 0 means timeout is disabled. 8642 * Compare the threshold register with timestamp field in 8643 * flow entry to generate timeout for the flow. 8644 * 8645 * |31 18 |17 16|15 8|7 0| 8646 * |-------------------------------------------------------------| 8647 * | reserved | pdev_mask | msg type | 8648 * |-------------------------------------------------------------| 8649 * | reserved | FISA_CTRL | 8650 * |-------------------------------------------------------------| 8651 * | FISA_TIMEOUT_THRESH | 8652 * |-------------------------------------------------------------| 8653 */ 8654 PREPACK struct htt_h2t_msg_type_fisa_config_t { 8655 A_UINT32 msg_type:8, 8656 pdev_id:8, 8657 reserved0:16; 8658 8659 /** 8660 * @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register 8661 * [17:0] 8662 */ 8663 union { 8664 /* 8665 * fisa_control_bits structure is deprecated. 8666 * Please use fisa_control_bits_v2 going forward. 8667 */ 8668 struct { 8669 A_UINT32 fisa_enable: 1, 8670 ipsec_skip_search: 1, 8671 nontcp_skip_search: 1, 8672 add_ipv4_fixed_hdr_len: 1, 8673 add_ipv6_fixed_hdr_len: 1, 8674 add_tcp_fixed_hdr_len: 1, 8675 add_udp_hdr_len: 1, 8676 chksum_cum_ip_len_en: 1, 8677 disable_tid_check: 1, 8678 disable_ta_check: 1, 8679 disable_qos_check: 1, 8680 disable_raw_check: 1, 8681 disable_decrypt_err_check: 1, 8682 disable_msdu_drop_check: 1, 8683 fisa_aggr_limit: 4, 8684 reserved: 14; 8685 } fisa_control_bits; 8686 struct { 8687 A_UINT32 fisa_enable: 1, 8688 fisa_aggr_limit: 6, 8689 reserved: 25; 8690 } fisa_control_bits_v2; 8691 8692 A_UINT32 fisa_control_value; 8693 } u_fisa_control; 8694 8695 /** 8696 * @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA 8697 * timeout threshold for aggregation. Unit in usec. 8698 * [31:0] 8699 */ 8700 A_UINT32 fisa_timeout_threshold; 8701 } POSTPACK; 8702 8703 8704 /* DWord 0: pdev-ID */ 8705 #define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00 8706 #define HTT_RX_FISA_CONFIG_PDEV_ID_S 8 8707 #define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \ 8708 (((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \ 8709 HTT_RX_FISA_CONFIG_PDEV_ID_S) 8710 #define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \ 8711 do { \ 8712 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \ 8713 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \ 8714 } while (0) 8715 8716 /* Dword 1: fisa_control_value fisa config */ 8717 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001 8718 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0 8719 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \ 8720 (((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \ 8721 HTT_RX_FISA_CONFIG_FISA_ENABLE_S) 8722 #define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \ 8723 do { \ 8724 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \ 8725 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \ 8726 } while (0) 8727 8728 /* Dword 1: fisa_control_value ipsec_skip_search */ 8729 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002 8730 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1 8731 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \ 8732 (((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \ 8733 HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S) 8734 #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \ 8735 do { \ 8736 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \ 8737 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \ 8738 } while (0) 8739 8740 /* Dword 1: fisa_control_value non_tcp_skip_search */ 8741 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004 8742 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2 8743 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \ 8744 (((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \ 8745 HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S) 8746 #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \ 8747 do { \ 8748 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \ 8749 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \ 8750 } while (0) 8751 8752 /* Dword 1: fisa_control_value add_ipv4_fixed_hdr */ 8753 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008 8754 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3 8755 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \ 8756 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \ 8757 HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S) 8758 #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \ 8759 do { \ 8760 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \ 8761 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \ 8762 } while (0) 8763 8764 /* Dword 1: fisa_control_value add_ipv6_fixed_hdr */ 8765 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010 8766 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4 8767 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \ 8768 (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \ 8769 HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S) 8770 #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \ 8771 do { \ 8772 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \ 8773 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \ 8774 } while (0) 8775 8776 /* Dword 1: fisa_control_value tcp_fixed_hdr_len */ 8777 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020 8778 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5 8779 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \ 8780 (((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \ 8781 HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S) 8782 #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \ 8783 do { \ 8784 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \ 8785 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \ 8786 } while (0) 8787 8788 /* Dword 1: fisa_control_value add_udp_hdr_len */ 8789 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040 8790 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6 8791 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \ 8792 (((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \ 8793 HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S) 8794 #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \ 8795 do { \ 8796 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \ 8797 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \ 8798 } while (0) 8799 8800 /* Dword 1: fisa_control_value chksum_cum_ip_len_en */ 8801 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080 8802 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7 8803 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \ 8804 (((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \ 8805 HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S) 8806 #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \ 8807 do { \ 8808 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \ 8809 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \ 8810 } while (0) 8811 8812 /* Dword 1: fisa_control_value disable_tid_check */ 8813 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100 8814 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8 8815 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \ 8816 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \ 8817 HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S) 8818 #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \ 8819 do { \ 8820 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \ 8821 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \ 8822 } while (0) 8823 8824 /* Dword 1: fisa_control_value disable_ta_check */ 8825 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200 8826 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9 8827 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \ 8828 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \ 8829 HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S) 8830 #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \ 8831 do { \ 8832 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \ 8833 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \ 8834 } while (0) 8835 8836 /* Dword 1: fisa_control_value disable_qos_check */ 8837 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400 8838 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10 8839 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \ 8840 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \ 8841 HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S) 8842 #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \ 8843 do { \ 8844 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \ 8845 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \ 8846 } while (0) 8847 8848 /* Dword 1: fisa_control_value disable_raw_check */ 8849 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800 8850 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11 8851 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \ 8852 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \ 8853 HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S) 8854 #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \ 8855 do { \ 8856 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \ 8857 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \ 8858 } while (0) 8859 8860 /* Dword 1: fisa_control_value disable_decrypt_err_check */ 8861 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000 8862 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12 8863 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \ 8864 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \ 8865 HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S) 8866 #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \ 8867 do { \ 8868 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \ 8869 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \ 8870 } while (0) 8871 8872 /* Dword 1: fisa_control_value disable_msdu_drop_check */ 8873 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000 8874 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13 8875 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \ 8876 (((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \ 8877 HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S) 8878 #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \ 8879 do { \ 8880 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \ 8881 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \ 8882 } while (0) 8883 8884 /* Dword 1: fisa_control_value fisa_aggr_limit */ 8885 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000 8886 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14 8887 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \ 8888 (((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \ 8889 HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S) 8890 #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \ 8891 do { \ 8892 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \ 8893 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \ 8894 } while (0) 8895 8896 /* Dword 1: fisa_control_value fisa config */ 8897 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M 0x00000001 8898 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S 0 8899 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_GET(_var) \ 8900 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M) >> \ 8901 HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S) 8902 #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_SET(_var, _val) \ 8903 do { \ 8904 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_ENABLE, _val); \ 8905 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S)); \ 8906 } while (0) 8907 8908 /* Dword 1: fisa_control_value fisa_aggr_limit */ 8909 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e 8910 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1 8911 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \ 8912 (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \ 8913 HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S) 8914 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_SET(_var, _val) \ 8915 do { \ 8916 HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT, _val); \ 8917 ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S)); \ 8918 } while (0) 8919 8920 PREPACK struct htt_h2t_msg_rx_fse_setup_t { 8921 A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */ 8922 pdev_id:8, 8923 reserved0:16; 8924 A_UINT32 num_records:20, 8925 max_search:8, 8926 ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */ 8927 reserved1:2; 8928 A_UINT32 base_addr_lo; 8929 A_UINT32 base_addr_hi; 8930 A_UINT32 toeplitz31_0; 8931 A_UINT32 toeplitz63_32; 8932 A_UINT32 toeplitz95_64; 8933 A_UINT32 toeplitz127_96; 8934 A_UINT32 toeplitz159_128; 8935 A_UINT32 toeplitz191_160; 8936 A_UINT32 toeplitz223_192; 8937 A_UINT32 toeplitz255_224; 8938 A_UINT32 toeplitz287_256; 8939 A_UINT32 toeplitz314_288:27, 8940 reserved2:5; 8941 } POSTPACK; 8942 8943 #define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t)) 8944 #define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t)) 8945 #define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t)) 8946 8947 #define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff 8948 #define HTT_RX_FSE_SETUP_HASH_314_288_S 0 8949 8950 /* DWORD 0: Pdev ID */ 8951 #define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00 8952 #define HTT_RX_FSE_SETUP_PDEV_ID_S 8 8953 #define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \ 8954 (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \ 8955 HTT_RX_FSE_SETUP_PDEV_ID_S) 8956 #define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \ 8957 do { \ 8958 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \ 8959 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \ 8960 } while (0) 8961 8962 /* DWORD 1:num of records */ 8963 #define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff 8964 #define HTT_RX_FSE_SETUP_NUM_REC_S 0 8965 #define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \ 8966 (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \ 8967 HTT_RX_FSE_SETUP_NUM_REC_S) 8968 #define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \ 8969 do { \ 8970 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \ 8971 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \ 8972 } while (0) 8973 8974 /* DWORD 1:max_search */ 8975 #define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000 8976 #define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20 8977 #define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \ 8978 (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \ 8979 HTT_RX_FSE_SETUP_MAX_SEARCH_S) 8980 #define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \ 8981 do { \ 8982 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \ 8983 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \ 8984 } while (0) 8985 8986 /* DWORD 1:ip_da_sa prefix */ 8987 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000 8988 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28 8989 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \ 8990 (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \ 8991 HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S) 8992 #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \ 8993 do { \ 8994 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \ 8995 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \ 8996 } while (0) 8997 8998 /* DWORD 2: Base Address LO */ 8999 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff 9000 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0 9001 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \ 9002 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \ 9003 HTT_RX_FSE_SETUP_BASE_ADDR_LO_S) 9004 #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \ 9005 do { \ 9006 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \ 9007 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \ 9008 } while (0) 9009 9010 /* DWORD 3: Base Address High */ 9011 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff 9012 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0 9013 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \ 9014 (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \ 9015 HTT_RX_FSE_SETUP_BASE_ADDR_HI_S) 9016 #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \ 9017 do { \ 9018 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \ 9019 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \ 9020 } while (0) 9021 9022 /* DWORD 4-12: Hash Value */ 9023 #define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff 9024 #define HTT_RX_FSE_SETUP_HASH_VALUE_S 0 9025 #define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \ 9026 (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \ 9027 HTT_RX_FSE_SETUP_HASH_VALUE_S) 9028 #define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \ 9029 do { \ 9030 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \ 9031 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \ 9032 } while (0) 9033 9034 /* DWORD 13: Hash Value 314:288 bits */ 9035 #define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \ 9036 (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \ 9037 HTT_RX_FSE_SETUP_HASH_314_288_S) 9038 #define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \ 9039 do { \ 9040 HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \ 9041 ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \ 9042 } while (0) 9043 9044 /** 9045 * @brief Host-->target HTT RX FSE operation message 9046 * 9047 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG 9048 * 9049 * @details 9050 * The host will send this Flow Search Engine (FSE) operation message for 9051 * every flow add/delete operation. 9052 * The FSE operation includes FSE full cache invalidation or individual entry 9053 * invalidation. 9054 * This message can be sent per SOC or per PDEV which is differentiated 9055 * by pdev id values. 9056 * 9057 * |31 16|15 8|7 1|0| 9058 * |-------------------------------------------------------------| 9059 * | reserved | pdev_id | MSG_TYPE | 9060 * |-------------------------------------------------------------| 9061 * | reserved | operation |I| 9062 * |-------------------------------------------------------------| 9063 * | ip_src_addr_31_0 | 9064 * |-------------------------------------------------------------| 9065 * | ip_src_addr_63_32 | 9066 * |-------------------------------------------------------------| 9067 * | ip_src_addr_95_64 | 9068 * |-------------------------------------------------------------| 9069 * | ip_src_addr_127_96 | 9070 * |-------------------------------------------------------------| 9071 * | ip_dst_addr_31_0 | 9072 * |-------------------------------------------------------------| 9073 * | ip_dst_addr_63_32 | 9074 * |-------------------------------------------------------------| 9075 * | ip_dst_addr_95_64 | 9076 * |-------------------------------------------------------------| 9077 * | ip_dst_addr_127_96 | 9078 * |-------------------------------------------------------------| 9079 * | l4_dst_port | l4_src_port | 9080 * | (32-bit SPI incase of IPsec) | 9081 * |-------------------------------------------------------------| 9082 * | reserved | l4_proto | 9083 * |-------------------------------------------------------------| 9084 * 9085 * where I is 1-bit ipsec_valid. 9086 * 9087 * The following field definitions describe the format of the RX FSE operation 9088 * message sent from the host to target for every add/delete flow entry to flow 9089 * table. 9090 * 9091 * Header fields: 9092 * dword0 - b'7:0 - msg_type: This will be set to 9093 * 0x13 (HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG) 9094 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9095 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9096 * specified pdev's LMAC ring. 9097 * b'31:16 - reserved : Reserved for future use 9098 * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec 9099 * (Internet Protocol Security). 9100 * IPsec describes the framework for providing security at 9101 * IP layer. IPsec is defined for both versions of IP: 9102 * IPV4 and IPV6. 9103 * Please refer to htt_rx_flow_proto enumeration below for 9104 * more info. 9105 * ipsec_valid = 1 for IPSEC packets 9106 * ipsec_valid = 0 for IP Packets 9107 * b'7:1 - operation: This indicates types of FSE operation. 9108 * Refer to htt_rx_fse_operation enumeration: 9109 * 0 - No Cache Invalidation required 9110 * 1 - Cache invalidate only one entry given by IP 9111 * src/dest address at DWORD[2:9] 9112 * 2 - Complete FSE Cache Invalidation 9113 * 3 - FSE Disable 9114 * 4 - FSE Enable 9115 * b'31:8 - reserved: Reserved for future use 9116 * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address 9117 * for per flow addition/deletion 9118 * For IPV4 src/dest addresses, the first A_UINT32 is used 9119 * and the subsequent 3 A_UINT32 will be padding bytes. 9120 * For IPV6 src/dest Addresses, all A_UINT32 are used. 9121 * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range 9122 * from 0 to 65535 but only 0 to 1023 are designated as 9123 * well-known ports. Refer to [RFC1700] for more details. 9124 * This field is valid only if 9125 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9126 * - L4 dest port (31:16): 16-bit Destination Port numbers 9127 * range from 0 to 65535 but only 0 to 1023 are designated 9128 * as well-known ports. Refer to [RFC1700] for more details. 9129 * This field is valid only if 9130 * (valid_ip_proto(l4_proto) && (ipsec_valid == 0)) 9131 * - SPI (31:0): Security Parameters Index is an 9132 * identification tag added to the header while using IPsec 9133 * for tunneling the IP traffici. 9134 * Valid only if IPSec_valid bit (in DWORD1) is set to 1. 9135 * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are 9136 * Assigned Internet Protocol Numbers. 9137 * l4_proto numbers for standard protocol like UDP/TCP 9138 * protocol at l4 layer, e.g. l4_proto = 6 for TCP, 9139 * l4_proto = 17 for UDP etc. 9140 * b'31:8 - reserved: Reserved for future use. 9141 * 9142 */ 9143 9144 PREPACK struct htt_h2t_msg_rx_fse_operation_t { 9145 A_UINT32 msg_type:8, 9146 pdev_id:8, 9147 reserved0:16; 9148 A_UINT32 ipsec_valid:1, 9149 operation:7, 9150 reserved1:24; 9151 A_UINT32 ip_src_addr_31_0; 9152 A_UINT32 ip_src_addr_63_32; 9153 A_UINT32 ip_src_addr_95_64; 9154 A_UINT32 ip_src_addr_127_96; 9155 A_UINT32 ip_dest_addr_31_0; 9156 A_UINT32 ip_dest_addr_63_32; 9157 A_UINT32 ip_dest_addr_95_64; 9158 A_UINT32 ip_dest_addr_127_96; 9159 union { 9160 A_UINT32 spi; 9161 struct { 9162 A_UINT32 l4_src_port:16, 9163 l4_dest_port:16; 9164 } ip; 9165 } u; 9166 A_UINT32 l4_proto:8, 9167 reserved:24; 9168 } POSTPACK; 9169 9170 /** 9171 * @brief Host-->target HTT RX Full monitor mode register configuration message 9172 * 9173 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE 9174 * 9175 * @details 9176 * The host will send this Full monitor mode register configuration message. 9177 * This message can be sent per SOC or per PDEV which is differentiated 9178 * by pdev id values. 9179 * 9180 * |31 16|15 11|10 8|7 3|2|1|0| 9181 * |-------------------------------------------------------------| 9182 * | reserved | pdev_id | MSG_TYPE | 9183 * |-------------------------------------------------------------| 9184 * | reserved |Release Ring |N|Z|E| 9185 * |-------------------------------------------------------------| 9186 * 9187 * where E is 1-bit full monitor mode enable/disable. 9188 * Z is 1-bit additional descriptor for zero mpdu enable/disable 9189 * N is 1-bit additional descriptor for non zero mdpu enable/disable 9190 * 9191 * The following field definitions describe the format of the full monitor 9192 * mode configuration message sent from the host to target for each pdev. 9193 * 9194 * Header fields: 9195 * dword0 - b'7:0 - msg_type: This will be set to 9196 * 0x17 (HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE) 9197 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9198 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9199 * specified pdev's LMAC ring. 9200 * b'31:16 - reserved : Reserved for future use. 9201 * dword1 - b'0 - full_monitor_mode enable: This indicates that the full 9202 * monitor mode rxdma register is to be enabled or disabled. 9203 * b'1 - addnl_descs_zero_mpdus_end: This indicates that the 9204 * additional descriptors at ppdu end for zero mpdus 9205 * enabled or disabled. 9206 * b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the 9207 * additional descriptors at ppdu end for non zero mpdus 9208 * enabled or disabled. 9209 * b'10:3 - release_ring: This indicates the destination ring 9210 * selection for the descriptor at the end of PPDU 9211 * 0 - REO ring select 9212 * 1 - FW ring select 9213 * 2 - SW ring select 9214 * 3 - Release ring select 9215 * Refer to htt_rx_full_mon_release_ring. 9216 * b'31:11 - reserved for future use 9217 */ 9218 PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t { 9219 A_UINT32 msg_type:8, 9220 pdev_id:8, 9221 reserved0:16; 9222 A_UINT32 full_monitor_mode_enable:1, 9223 addnl_descs_zero_mpdus_end:1, 9224 addnl_descs_non_zero_mpdus_end:1, 9225 release_ring:8, 9226 reserved1:21; 9227 } POSTPACK; 9228 9229 /** 9230 * Enumeration for full monitor mode destination ring select 9231 * 0 - REO destination ring select 9232 * 1 - FW destination ring select 9233 * 2 - SW destination ring select 9234 * 3 - Release destination ring select 9235 */ 9236 enum htt_rx_full_mon_release_ring { 9237 HTT_RX_MON_RING_REO, 9238 HTT_RX_MON_RING_FW, 9239 HTT_RX_MON_RING_SW, 9240 HTT_RX_MON_RING_RELEASE, 9241 }; 9242 9243 #define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t)) 9244 /* DWORD 0: Pdev ID */ 9245 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00 9246 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8 9247 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \ 9248 (((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \ 9249 HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S) 9250 #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \ 9251 do { \ 9252 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \ 9253 ((_var) |= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \ 9254 } while (0) 9255 9256 /* DWORD 1:ENABLE */ 9257 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001 9258 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0 9259 9260 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \ 9261 do { \ 9262 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \ 9263 (word) |= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \ 9264 } while (0) 9265 #define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \ 9266 (((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S) 9267 9268 /* DWORD 1:ZERO_MPDU */ 9269 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002 9270 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1 9271 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \ 9272 do { \ 9273 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \ 9274 (word) |= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \ 9275 } while (0) 9276 #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \ 9277 (((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S) 9278 9279 9280 /* DWORD 1:NON_ZERO_MPDU */ 9281 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004 9282 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2 9283 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \ 9284 do { \ 9285 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \ 9286 (word) |= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \ 9287 } while (0) 9288 #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \ 9289 (((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S) 9290 9291 /* DWORD 1:RELEASE_RINGS */ 9292 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8 9293 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3 9294 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \ 9295 do { \ 9296 HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \ 9297 (word) |= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \ 9298 } while (0) 9299 #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \ 9300 (((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S) 9301 9302 /** 9303 * Enumeration for IP Protocol or IPSEC Protocol 9304 * IPsec describes the framework for providing security at IP layer. 9305 * IPsec is defined for both versions of IP: IPV4 and IPV6. 9306 */ 9307 enum htt_rx_flow_proto { 9308 HTT_RX_FLOW_IP_PROTO, 9309 HTT_RX_FLOW_IPSEC_PROTO, 9310 }; 9311 9312 /** 9313 * Enumeration for FSE Cache Invalidation 9314 * 0 - No Cache Invalidation required 9315 * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9 9316 * 2 - Complete FSE Cache Invalidation 9317 * 3 - FSE Disable 9318 * 4 - FSE Enable 9319 */ 9320 enum htt_rx_fse_operation { 9321 HTT_RX_FSE_CACHE_INVALIDATE_NONE, 9322 HTT_RX_FSE_CACHE_INVALIDATE_ENTRY, 9323 HTT_RX_FSE_CACHE_INVALIDATE_FULL, 9324 HTT_RX_FSE_DISABLE, 9325 HTT_RX_FSE_ENABLE, 9326 }; 9327 9328 /* DWORD 0: Pdev ID */ 9329 #define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00 9330 #define HTT_RX_FSE_OPERATION_PDEV_ID_S 8 9331 #define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \ 9332 (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \ 9333 HTT_RX_FSE_OPERATION_PDEV_ID_S) 9334 #define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \ 9335 do { \ 9336 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \ 9337 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \ 9338 } while (0) 9339 9340 /* DWORD 1:IP PROTO or IPSEC */ 9341 #define HTT_RX_FSE_IPSEC_VALID_M 0x00000001 9342 #define HTT_RX_FSE_IPSEC_VALID_S 0 9343 9344 #define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \ 9345 do { \ 9346 HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \ 9347 (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \ 9348 } while (0) 9349 #define HTT_RX_FSE_IPSEC_VALID_GET(word) \ 9350 (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S) 9351 9352 /* DWORD 1:FSE Operation */ 9353 #define HTT_RX_FSE_OPERATION_M 0x000000fe 9354 #define HTT_RX_FSE_OPERATION_S 1 9355 9356 #define HTT_RX_FSE_OPERATION_SET(word, op_val) \ 9357 do { \ 9358 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \ 9359 (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \ 9360 } while (0) 9361 #define HTT_RX_FSE_OPERATION_GET(word) \ 9362 (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S) 9363 9364 /* DWORD 2-9:IP Address */ 9365 #define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff 9366 #define HTT_RX_FSE_OPERATION_IP_ADDR_S 0 9367 #define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \ 9368 (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \ 9369 HTT_RX_FSE_OPERATION_IP_ADDR_S) 9370 #define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \ 9371 do { \ 9372 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \ 9373 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \ 9374 } while (0) 9375 9376 /* DWORD 10:Source Port Number */ 9377 #define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff 9378 #define HTT_RX_FSE_SOURCEPORT_S 0 9379 9380 #define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \ 9381 do { \ 9382 HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \ 9383 (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \ 9384 } while (0) 9385 #define HTT_RX_FSE_SOURCEPORT_GET(word) \ 9386 (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S) 9387 9388 9389 /* DWORD 11:Destination Port Number */ 9390 #define HTT_RX_FSE_DESTPORT_M 0xffff0000 9391 #define HTT_RX_FSE_DESTPORT_S 16 9392 9393 #define HTT_RX_FSE_DESTPORT_SET(word, dport) \ 9394 do { \ 9395 HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \ 9396 (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \ 9397 } while (0) 9398 #define HTT_RX_FSE_DESTPORT_GET(word) \ 9399 (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S) 9400 9401 /* DWORD 10-11:SPI (In case of IPSEC) */ 9402 #define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff 9403 #define HTT_RX_FSE_OPERATION_SPI_S 0 9404 #define HTT_RX_FSE_OPERATION_SPI_GET(_var) \ 9405 (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \ 9406 HTT_RX_FSE_OPERATION_SPI_ADDR_S) 9407 #define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \ 9408 do { \ 9409 HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \ 9410 ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \ 9411 } while (0) 9412 9413 /* DWORD 12:L4 PROTO */ 9414 #define HTT_RX_FSE_L4_PROTO_M 0x000000ff 9415 #define HTT_RX_FSE_L4_PROTO_S 0 9416 9417 #define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \ 9418 do { \ 9419 HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \ 9420 (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \ 9421 } while (0) 9422 #define HTT_RX_FSE_L4_PROTO_GET(word) \ 9423 (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S) 9424 9425 9426 /** 9427 * @brief host --> target Receive to configure the RxOLE 3-tuple Hash 9428 * 9429 * MSG_TYPE => HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG 9430 * 9431 * |31 24|23 |15 8|7 2|1|0| 9432 * |----------------+----------------+----------------+----------------| 9433 * | reserved | pdev_id | msg_type | 9434 * |---------------------------------+----------------+----------------| 9435 * | reserved |E|F| 9436 * |---------------------------------+----------------+----------------| 9437 * Where E = Configure the target to provide the 3-tuple hash value in 9438 * toeplitz_hash_2_or_4 field of rx_msdu_start tlv 9439 * F = Configure the target to provide the 3-tuple hash value in 9440 * flow_id_toeplitz field of rx_msdu_start tlv 9441 * 9442 * The following field definitions describe the format of the 3 tuple hash value 9443 * message sent from the host to target as part of initialization sequence. 9444 * 9445 * Header fields: 9446 * dword0 - b'7:0 - msg_type: This will be set to 9447 * 0x16 (HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG) 9448 * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc 9449 * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the 9450 * specified pdev's LMAC ring. 9451 * b'31:16 - reserved : Reserved for future use 9452 * dword1 - b'0 - flow_id_toeplitz_field_enable 9453 * b'1 - toeplitz_hash_2_or_4_field_enable 9454 * b'31:2 - reserved : Reserved for future use 9455 * ---------+------+---------------------------------------------------------- 9456 * bit1 | bit0 | Functionality 9457 * ---------+------+---------------------------------------------------------- 9458 * 0 | 1 | Configure the target to provide the 3 tuple hash value 9459 * | | in flow_id_toeplitz field 9460 * ---------+------+---------------------------------------------------------- 9461 * 1 | 0 | Configure the target to provide the 3 tuple hash value 9462 * | | in toeplitz_hash_2_or_4 field 9463 * ---------+------+---------------------------------------------------------- 9464 * 1 | 1 | Configure the target to provide the 3 tuple hash value 9465 * | | in both flow_id_toeplitz & toeplitz_hash_2_or_4 field 9466 * ---------+------+---------------------------------------------------------- 9467 * 0 | 0 | Configure the target to provide the 5 tuple hash value 9468 * | | in flow_id_toeplitz field 2 or 4 tuple has value in 9469 * | | toeplitz_hash_2_or_4 field 9470 *---------------------------------------------------------------------------- 9471 */ 9472 PREPACK struct htt_h2t_msg_rx_3_tuple_hash_cfg_t { 9473 A_UINT32 msg_type :8, 9474 pdev_id :8, 9475 reserved0 :16; 9476 A_UINT32 flow_id_toeplitz_field_enable :1, 9477 toeplitz_hash_2_or_4_field_enable :1, 9478 reserved1 :30; 9479 } POSTPACK; 9480 9481 /* DWORD0 : pdev_id configuration Macros */ 9482 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_M 0xff00 9483 #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_S 8 9484 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_GET(_var) \ 9485 (((_var) & HTT_H2T_3_TUPLE_HASH_PDEV_ID_M) >> \ 9486 HTT_H2T_3_TUPLE_HASH_PDEV_ID_S) 9487 #define HTT_RX_3_TUPLE_HASH_PDEV_ID_SET(_var, _val) \ 9488 do { \ 9489 HTT_CHECK_SET_VAL(HTT_H2T_3_TUPLE_HASH_PDEV_ID, _val); \ 9490 ((_var) |= ((_val) << HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)); \ 9491 } while (0) 9492 9493 /* DWORD1: rx 3 tuple hash value reception field configuration Macros */ 9494 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M 0x1 9495 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S 0 9496 #define HTT_FLOW_ID_TOEPLITZ_FIELD_CONFIG_GET(_var) \ 9497 (((_var) & HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M) >> \ 9498 HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S) 9499 #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_SET(_var, _val) \ 9500 do { \ 9501 HTT_CHECK_SET_VAL(HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG, _val); \ 9502 ((_var) |= ((_val) << HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)); \ 9503 } while (0) 9504 9505 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M 0x2 9506 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S 1 9507 #define HTT_TOEPLITZ_2_OR_4_FIELD_CONFIG_GET(_var) \ 9508 (((_var) & HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M) >> \ 9509 HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S) 9510 #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_SET(_var, _val) \ 9511 do { \ 9512 HTT_CHECK_SET_VAL(HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG, _val); \ 9513 ((_var) |= ((_val) << HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)); \ 9514 } while (0) 9515 9516 #define HTT_3_TUPLE_HASH_CFG_REQ_BYTES 8 9517 9518 /** 9519 * @brief host --> target Host PA Address Size 9520 * 9521 * MSG_TYPE => HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE 9522 * 9523 * @details 9524 * The HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE message is sent by the host to 9525 * provide the physical start address and size of each of the memory 9526 * areas within host DDR that the target FW may need to access. 9527 * 9528 * For example, the host can use this message to allow the target FW 9529 * to set up access to the host's pools of TQM link descriptors. 9530 * The message would appear as follows: 9531 * 9532 * |31 24|23 16|15 8|7 0| 9533 * |----------------+----------------+----------------+----------------| 9534 * | reserved | num_entries | msg_type | 9535 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9536 * | mem area 0 size | 9537 * |----------------+----------------+----------------+----------------| 9538 * | mem area 0 physical_address_lo | 9539 * |----------------+----------------+----------------+----------------| 9540 * | mem area 0 physical_address_hi | 9541 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9542 * | mem area 1 size | 9543 * |----------------+----------------+----------------+----------------| 9544 * | mem area 1 physical_address_lo | 9545 * |----------------+----------------+----------------+----------------| 9546 * | mem area 1 physical_address_hi | 9547 * |----------------+----------------+----------------+----------------| 9548 * ... 9549 * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-| 9550 * | mem area N size | 9551 * |----------------+----------------+----------------+----------------| 9552 * | mem area N physical_address_lo | 9553 * |----------------+----------------+----------------+----------------| 9554 * | mem area N physical_address_hi | 9555 * |----------------+----------------+----------------+----------------| 9556 * 9557 * The message is interpreted as follows: 9558 * dword0 - b'0:7 - msg_type: This will be set to 9559 * 0x18 (HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE) 9560 * b'8:15 - number_entries: Indicated the number of host memory 9561 * areas specified within the remainder of the message 9562 * b'16:31 - reserved. 9563 * dword1 - b'0:31 - memory area 0 size in bytes 9564 * dword2 - b'0:31 - memory area 0 physical address, lower 32 bits 9565 * dword3 - b'0:31 - memory area 0 physical address, upper 32 bits 9566 * and similar for memory area 1 through memory area N. 9567 */ 9568 9569 PREPACK struct htt_h2t_host_paddr_size { 9570 A_UINT32 msg_type: 8, 9571 num_entries: 8, 9572 reserved: 16; 9573 } POSTPACK; 9574 9575 PREPACK struct htt_h2t_host_paddr_size_entry_t { 9576 A_UINT32 size; 9577 A_UINT32 physical_address_lo; 9578 A_UINT32 physical_address_hi; 9579 } POSTPACK; 9580 9581 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE \ 9582 (sizeof(struct htt_h2t_host_paddr_size_entry_t)) 9583 #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_DWORDS \ 9584 (HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE >> 2) 9585 9586 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M 0x0000FF00 9587 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S 8 9588 9589 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_GET(_var) \ 9590 (((_var) & HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M) >> \ 9591 HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S) 9592 9593 #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_SET(_var, _val) \ 9594 do { \ 9595 HTT_CHECK_SET_VAL(HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES, _val); \ 9596 ((_var) |= ((_val) << HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S)); \ 9597 } while (0) 9598 9599 /** 9600 * @brief host --> target Host RXDMA RXOLE PPE register configuration 9601 * 9602 * MSG_TYPE => HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG 9603 * 9604 * @details 9605 * The HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG message is sent by the host to 9606 * provide the PPE DS register confiuration for RXOLE and RXDMA. 9607 * 9608 * The message would appear as follows: 9609 * 9610 * |31 19|18 |17 |16 |15 |14 |13 9|8|7 0| 9611 * |---------------------------------+---+---+----------+-+-----------| 9612 * | reserved |IFO|DNO|DRO|IBO|MIO| RDI |O| msg_type | 9613 * |---------------------+---+---+---+---+---+----------+-+-----------| 9614 * 9615 * 9616 * The message is interpreted as follows: 9617 * dword0 - b'0:7 - msg_type: This will be set to 9618 * 0x19 (HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG) 9619 * b'8 - override bit to drive MSDUs to PPE ring 9620 * b'9:13 - REO destination ring indication 9621 * b'14 - Multi buffer msdu override enable bit 9622 * b'15 - Intra BSS override 9623 * b'16 - Decap raw override 9624 * b'17 - Decap Native wifi override 9625 * b'18 - IP frag override 9626 * b'19:31 - reserved 9627 */ 9628 PREPACK struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg_t { 9629 A_UINT32 msg_type: 8, /* HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG */ 9630 override: 1, 9631 reo_destination_indication: 5, 9632 multi_buffer_msdu_override_en: 1, 9633 intra_bss_override: 1, 9634 decap_raw_override: 1, 9635 decap_nwifi_override: 1, 9636 ip_frag_override: 1, 9637 reserved: 13; 9638 } POSTPACK; 9639 9640 /* DWORD 0: Override */ 9641 #define HTT_PPE_CFG_OVERRIDE_M 0x00000100 9642 #define HTT_PPE_CFG_OVERRIDE_S 8 9643 #define HTT_PPE_CFG_OVERRIDE_GET(_var) \ 9644 (((_var) & HTT_PPE_CFG_OVERRIDE_M) >> \ 9645 HTT_PPE_CFG_OVERRIDE_S) 9646 #define HTT_PPE_CFG_OVERRIDE_SET(_var, _val) \ 9647 do { \ 9648 HTT_CHECK_SET_VAL(HTT_PPE_CFG_OVERRIDE, _val); \ 9649 ((_var) |= ((_val) << HTT_PPE_CFG_OVERRIDE_S)); \ 9650 } while (0) 9651 9652 /* DWORD 0: REO Destination Indication*/ 9653 #define HTT_PPE_CFG_REO_DEST_IND_M 0x00003E00 9654 #define HTT_PPE_CFG_REO_DEST_IND_S 9 9655 #define HTT_PPE_CFG_REO_DEST_IND_GET(_var) \ 9656 (((_var) & HTT_PPE_CFG_REO_DEST_IND_M) >> \ 9657 HTT_PPE_CFG_REO_DEST_IND_S) 9658 #define HTT_PPE_CFG_REO_DEST_IND_SET(_var, _val) \ 9659 do { \ 9660 HTT_CHECK_SET_VAL(HTT_PPE_CFG_REO_DEST_IND, _val); \ 9661 ((_var) |= ((_val) << HTT_PPE_CFG_REO_DEST_IND_S)); \ 9662 } while (0) 9663 9664 /* DWORD 0: Multi buffer MSDU override */ 9665 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M 0x00004000 9666 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S 14 9667 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_GET(_var) \ 9668 (((_var) & HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M) >> \ 9669 HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S) 9670 #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_SET(_var, _val) \ 9671 do { \ 9672 HTT_CHECK_SET_VAL(HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN, _val); \ 9673 ((_var) |= ((_val) << HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S)); \ 9674 } while (0) 9675 9676 /* DWORD 0: Intra BSS override */ 9677 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M 0x00008000 9678 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S 15 9679 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_GET(_var) \ 9680 (((_var) & HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M) >> \ 9681 HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S) 9682 #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_SET(_var, _val) \ 9683 do { \ 9684 HTT_CHECK_SET_VAL(HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN, _val); \ 9685 ((_var) |= ((_val) << HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S)); \ 9686 } while (0) 9687 9688 /* DWORD 0: Decap RAW override */ 9689 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M 0x00010000 9690 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S 16 9691 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_GET(_var) \ 9692 (((_var) & HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M) >> \ 9693 HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S) 9694 #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_SET(_var, _val) \ 9695 do { \ 9696 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN, _val); \ 9697 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S)); \ 9698 } while (0) 9699 9700 /* DWORD 0: Decap NWIFI override */ 9701 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M 0x00020000 9702 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S 17 9703 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_GET(_var) \ 9704 (((_var) & HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M) >> \ 9705 HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S) 9706 #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_SET(_var, _val) \ 9707 do { \ 9708 HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN, _val); \ 9709 ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S)); \ 9710 } while (0) 9711 9712 /* DWORD 0: IP frag override */ 9713 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M 0x00040000 9714 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S 18 9715 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_GET(_var) \ 9716 (((_var) & HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M) >> \ 9717 HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S) 9718 #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_SET(_var, _val) \ 9719 do { \ 9720 HTT_CHECK_SET_VAL(HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN, _val); \ 9721 ((_var) |= ((_val) << HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S)); \ 9722 } while (0) 9723 9724 /* 9725 * MSG_TYPE => HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG 9726 * 9727 * @details 9728 * The following field definitions describe the format of the HTT host 9729 * to target FW VDEV TX RX stats retrieve message. 9730 * The message specifies the type of stats the host wants to retrieve. 9731 * 9732 * |31 27|26 25|24 17|16|15 8|7 0| 9733 * |-----------------------------------------------------------| 9734 * | rsvd | R | Periodic Int| E| pdev_id | msg type | 9735 * |-----------------------------------------------------------| 9736 * | vdev_id lower bitmask | 9737 * |-----------------------------------------------------------| 9738 * | vdev_id upper bitmask | 9739 * |-----------------------------------------------------------| 9740 * Header fields: 9741 * Where: 9742 * dword0 - b'7:0 - msg_type: This will be set to 9743 * 0x1a (HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG) 9744 * b'15:8 - pdev id 9745 * b'16(E) - Enable/Disable the vdev HW stats 9746 * b'17:24(PI) - Periodic Interval, units = 8 ms, e.g. 125 -> 1000 ms 9747 * b'25:26(R) - Reset stats bits 9748 * 0: don't reset stats 9749 * 1: reset stats once 9750 * 2: reset stats at the start of each periodic interval 9751 * b'27:31 - reserved for future use 9752 * dword1 - b'0:31 - vdev_id lower bitmask 9753 * dword2 - b'0:31 - vdev_id upper bitmask 9754 */ 9755 9756 PREPACK struct htt_h2t_vdevs_txrx_stats_cfg { 9757 A_UINT32 msg_type :8, 9758 pdev_id :8, 9759 enable :1, 9760 periodic_interval :8, 9761 reset_stats_bits :2, 9762 reserved0 :5; 9763 A_UINT32 vdev_id_lower_bitmask; 9764 A_UINT32 vdev_id_upper_bitmask; 9765 } POSTPACK; 9766 9767 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M 0xFF00 9768 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S 8 9769 #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_GET(_var) \ 9770 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M) >> \ 9771 HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S) 9772 #define HTT_RX_VDEVS_TXRX_STATS_PDEV_ID_SET(_var, _val) \ 9773 do { \ 9774 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID, _val); \ 9775 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S)); \ 9776 } while (0) 9777 9778 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M 0x10000 9779 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S 16 9780 #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_GET(_var) \ 9781 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M) >> \ 9782 HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S) 9783 #define HTT_RX_VDEVS_TXRX_STATS_ENABLE_SET(_var, _val) \ 9784 do { \ 9785 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_ENABLE, _val); \ 9786 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S)); \ 9787 } while (0) 9788 9789 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M 0x1FE0000 9790 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S 17 9791 #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_GET(_var) \ 9792 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M) >> \ 9793 HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S) 9794 #define HTT_RX_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_SET(_var, _val) \ 9795 do { \ 9796 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL, _val); \ 9797 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S)); \ 9798 } while (0) 9799 9800 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M 0x6000000 9801 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S 25 9802 #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_GET(_var) \ 9803 (((_var) & HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M) >> \ 9804 HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S) 9805 #define HTT_RX_VDEVS_TXRX_STATS_RESET_STATS_BITS_SET(_var, _val) \ 9806 do { \ 9807 HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS, _val); \ 9808 ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S)); \ 9809 } while (0) 9810 9811 9812 /* 9813 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ 9814 * 9815 * @details 9816 * The SAWF_DEF_QUEUES_MAP_REQ message is sent by the host to link 9817 * the default MSDU queues for one of the TIDs within the specified peer 9818 * to the specified service class. 9819 * The TID is indirectly specified - each service class is associated 9820 * with a TID. All default MSDU queues for this peer-TID will be 9821 * linked to the service class in question. 9822 * 9823 * |31 16|15 8|7 0| 9824 * |------------------------------+--------------+--------------| 9825 * | peer ID | svc class ID | msg type | 9826 * |------------------------------------------------------------| 9827 * Header fields: 9828 * dword0 - b'7:0 - msg_type: This will be set to 9829 * 0x1c (HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ) 9830 * b'15:8 - service class ID 9831 * b'31:16 - peer ID 9832 */ 9833 9834 PREPACK struct htt_h2t_sawf_def_queues_map_req { 9835 A_UINT32 msg_type :8, 9836 svc_class_id :8, 9837 peer_id :16; 9838 } POSTPACK; 9839 9840 #define HTT_SAWF_DEF_QUEUES_MAP_REQ_BYTES 4 9841 9842 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M 0x0000FF00 9843 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S 8 9844 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_GET(_var) \ 9845 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M) >> \ 9846 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S) 9847 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_SET(_var, _val) \ 9848 do { \ 9849 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID, _val); \ 9850 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S));\ 9851 } while (0) 9852 9853 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M 0xFFFF0000 9854 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S 16 9855 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_GET(_var) \ 9856 (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M) >> \ 9857 HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S) 9858 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_SET(_var, _val) \ 9859 do { \ 9860 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID, _val); \ 9861 ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S)); \ 9862 } while (0) 9863 9864 9865 /* 9866 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ 9867 * 9868 * @details 9869 * The SAWF_DEF_QUEUES_UNMAP_REQ message is sent by the host to 9870 * remove the linkage of the specified peer-TID's MSDU queues to 9871 * service classes. 9872 * 9873 * |31 16|15 8|7 0| 9874 * |------------------------------+--------------+--------------| 9875 * | peer ID | svc class ID | msg type | 9876 * |------------------------------------------------------------| 9877 * Header fields: 9878 * dword0 - b'7:0 - msg_type: This will be set to 9879 * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ) 9880 * b'15:8 - service class ID 9881 * b'31:16 - peer ID 9882 * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 9883 * value for peer ID indicates that the target should 9884 * apply the UNMAP_REQ to all peers. 9885 */ 9886 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 0xff 9887 PREPACK struct htt_h2t_sawf_def_queues_unmap_req { 9888 A_UINT32 msg_type :8, 9889 svc_class_id :8, 9890 peer_id :16; 9891 } POSTPACK; 9892 9893 #define HTT_SAWF_DEF_QUEUES_UNMAP_REQ_BYTES 4 9894 9895 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M 0x0000FF00 9896 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S 8 9897 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(word0) \ 9898 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \ 9899 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S) 9900 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(word0, _val) \ 9901 do { \ 9902 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID, _val); \ 9903 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \ 9904 } while (0) 9905 9906 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M 0xFFFF0000 9907 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S 16 9908 #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(word0) \ 9909 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \ 9910 HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S) 9911 #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(word0, _val) \ 9912 do { \ 9913 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID, _val); \ 9914 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \ 9915 } while (0) 9916 9917 /* 9918 * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ 9919 * 9920 * @details 9921 * The SAWF_DEF_QUEUES_MAP_REPORT_REQ message is sent by the host to 9922 * request the target to report what service class the default MSDU queues 9923 * of the specified TIDs within the peer are linked to. 9924 * The target will respond with a SAWF_DEF_QUEUES_MAP_REPORT_CONF message 9925 * to report what service class (if any) the default MSDU queues for 9926 * each of the specified TIDs are linked to. 9927 * 9928 * |31 16|15 8|7 1| 0| 9929 * |------------------------------+--------------+--------------| 9930 * | peer ID | TID mask | msg type | 9931 * |------------------------------------------------------------| 9932 * | reserved |ETO| 9933 * |------------------------------------------------------------| 9934 * Header fields: 9935 * dword0 - b'7:0 - msg_type: This will be set to 9936 * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ) 9937 * b'15:8 - TID mask 9938 * b'31:16 - peer ID 9939 * dword1 - b'0 - "Existing Tids Only" flag 9940 * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF 9941 * message generated by this REQ will only show the 9942 * mapping for TIDs that actually exist in the target's 9943 * peer object. 9944 * Any TIDs that are covered by a MAP_REQ but which 9945 * do not actually exist will be shown as being 9946 * unmapped (i.e. svc class ID 0xff). 9947 * If this flag is cleared, the MAP_REPORT_CONF message 9948 * will consider not only the mapping of TIDs currently 9949 * existing in the peer, but also the mapping that will 9950 * be applied for any TID objects created within this 9951 * peer in the future. 9952 * b'31:1 - reserved for future use 9953 */ 9954 9955 PREPACK struct htt_h2t_sawf_def_queues_map_report_req { 9956 A_UINT32 msg_type :8, 9957 tid_mask :8, 9958 peer_id :16; 9959 A_UINT32 existing_tids_only:1, 9960 reserved :31; 9961 } POSTPACK; 9962 9963 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 8 9964 9965 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M 0x0000FF00 9966 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S 8 9967 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(word0) \ 9968 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \ 9969 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S) 9970 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(word0, _val) \ 9971 do { \ 9972 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK, _val); \ 9973 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\ 9974 } while (0) 9975 9976 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M 0xFFFF0000 9977 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S 16 9978 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(word0) \ 9979 (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \ 9980 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S) 9981 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(word0, _val) \ 9982 do { \ 9983 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID, _val); \ 9984 ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \ 9985 } while (0) 9986 9987 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M 0x00000001 9988 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S 0 9989 #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_GET(word1) \ 9990 (((word1) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M) >> \ 9991 HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S) 9992 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_SET(word1, _val) \ 9993 do { \ 9994 HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY, _val); \ 9995 ((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \ 9996 } while (0) 9997 9998 /** 9999 * @brief Format of shared memory between Host and Target 10000 * for UMAC recovery feature messaging. 10001 * @details 10002 * This is shared memory between Host and Target allocated 10003 * and used in chips where UMAC recovery feature is supported. 10004 * This shared memory is allocated per SOC level by Host since each 10005 * SOC's target Q6FW needs to communicate independently to the Host 10006 * through its own shared memory. 10007 * If target sets a bit in t2h_msg (provided it's valid bit offset) 10008 * then host interprets it as a new message from target. 10009 * Host clears that particular read bit in t2h_msg after each read 10010 * operation. It is vice versa for h2t_msg. At any given point 10011 * of time there is expected to be only one bit set 10012 * either in t2h_msg or h2t_msg (referring to valid bit offset). 10013 * 10014 * The message is interpreted as follows: 10015 * dword0 - b'0:31 - magic_num: Magic number for the shared memory region 10016 * added for debuggability purpose. 10017 * dword1 - b'0 - do_pre_reset 10018 * b'1 - do_post_reset_start 10019 * b'2 - do_post_reset_complete 10020 * b'3 - initiate_umac_recovery 10021 * b'4 - initiate_target_recovery_sync_using_umac 10022 * b'5:31 - rsvd_t2h 10023 * dword2 - b'0 - pre_reset_done 10024 * b'1 - post_reset_start_done 10025 * b'2 - post_reset_complete_done 10026 * b'3 - start_pre_reset (deprecated) 10027 * b'4:31 - rsvd_h2t 10028 */ 10029 PREPACK typedef struct { 10030 /** Magic number added for debuggability. */ 10031 A_UINT32 magic_num; 10032 union { 10033 /* 10034 * BIT [0] :- T2H msg to do pre-reset 10035 * BIT [1] :- T2H msg to do post-reset start 10036 * BIT [2] :- T2H msg to do post-reset complete 10037 * BIT [3] :- T2H msg to indicate to Host that 10038 * a trigger request for MLO UMAC Recovery 10039 * is received for UMAC hang. 10040 * BIT [4] :- T2H msg to indicate to Host that 10041 * a trigger request for MLO UMAC Recovery 10042 * is received for Mode-1 Target Recovery. 10043 * BIT [31 : 5] :- reserved 10044 */ 10045 A_UINT32 t2h_msg; 10046 struct { 10047 A_UINT32 10048 do_pre_reset: 1, /* BIT [0] */ 10049 do_post_reset_start: 1, /* BIT [1] */ 10050 do_post_reset_complete: 1, /* BIT [2] */ 10051 initiate_umac_recovery: 1, /* BIT [3] */ 10052 initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ 10053 rsvd_t2h: 27; /* BIT [31:5] */ 10054 }; 10055 }; 10056 10057 union { 10058 /* 10059 * BIT [0] :- H2T msg to send pre-reset done 10060 * BIT [1] :- H2T msg to send post-reset start done 10061 * BIT [2] :- H2T msg to send post-reset complete done 10062 * BIT [3] :- H2T msg to start pre-reset. This is deprecated. 10063 * BIT [31 : 4] :- reserved 10064 */ 10065 A_UINT32 h2t_msg; 10066 struct { 10067 A_UINT32 pre_reset_done : 1, /* BIT [0] */ 10068 post_reset_start_done : 1, /* BIT [1] */ 10069 post_reset_complete_done : 1, /* BIT [2] */ 10070 start_pre_reset : 1, /* BIT [3] */ 10071 rsvd_h2t : 28; /* BIT [31 : 4] */ 10072 }; 10073 }; 10074 } POSTPACK htt_umac_hang_recovery_msg_shmem_t; 10075 10076 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES \ 10077 (sizeof(htt_umac_hang_recovery_msg_shmem_t)) 10078 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DWORDS \ 10079 (HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES >> 2) 10080 10081 /* dword1 - b'0 - do_pre_reset */ 10082 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M 0x00000001 10083 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S 0 10084 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_GET(word1) \ 10085 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M) >> \ 10086 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S) 10087 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_SET(word1, _val) \ 10088 do { \ 10089 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET, _val); \ 10090 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S));\ 10091 } while (0) 10092 10093 /* dword1 - b'1 - do_post_reset_start */ 10094 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M 0x00000002 10095 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S 1 10096 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_GET(word1) \ 10097 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M) >> \ 10098 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S) 10099 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_SET(word1, _val) \ 10100 do { \ 10101 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START, _val); \ 10102 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S));\ 10103 } while (0) 10104 10105 /* dword1 - b'2 - do_post_reset_complete */ 10106 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M 0x00000004 10107 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S 2 10108 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_GET(word1) \ 10109 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M) >> \ 10110 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S) 10111 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_SET(word1, _val) \ 10112 do { \ 10113 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE, _val); \ 10114 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\ 10115 } while (0) 10116 10117 /* dword1 - b'3 - initiate_umac_recovery */ 10118 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 10119 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 10120 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ 10121 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ 10122 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) 10123 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ 10124 do { \ 10125 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY, _val); \ 10126 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ 10127 } while (0) 10128 10129 /* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ 10130 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 10131 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 10132 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ 10133 (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ 10134 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) 10135 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ 10136 do { \ 10137 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ 10138 ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ 10139 } while (0) 10140 10141 /* dword2 - b'0 - pre_reset_done */ 10142 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 10143 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 10144 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_GET(word2) \ 10145 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M) >> \ 10146 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S) 10147 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_SET(word2, _val) \ 10148 do { \ 10149 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE, _val); \ 10150 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S));\ 10151 } while (0) 10152 10153 /* dword2 - b'1 - post_reset_start_done */ 10154 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M 0x00000002 10155 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S 1 10156 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_GET(word2) \ 10157 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M) >> \ 10158 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S) 10159 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_SET(word2, _val) \ 10160 do { \ 10161 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE, _val); \ 10162 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S));\ 10163 } while (0) 10164 10165 /* dword2 - b'2 - post_reset_complete_done */ 10166 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M 0x00000004 10167 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S 2 10168 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_GET(word2) \ 10169 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M) >> \ 10170 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S) 10171 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_SET(word2, _val) \ 10172 do { \ 10173 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE, _val); \ 10174 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\ 10175 } while (0) 10176 10177 /* dword2 - b'3 - start_pre_reset */ 10178 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M 0x00000008 10179 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S 3 10180 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_GET(word2) \ 10181 (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M) >> \ 10182 HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S) 10183 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_SET(word2, _val) \ 10184 do { \ 10185 HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET, _val); \ 10186 ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S));\ 10187 } while (0) 10188 10189 /** 10190 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message 10191 * 10192 * @details 10193 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent 10194 * by the host to provide prerequisite info to target for the UMAC hang 10195 * recovery feature. 10196 * The info sent in this H2T message are T2H message method, H2T message 10197 * method, T2H MSI interrupt number and physical start address, size of 10198 * the shared memory (refers to the shared memory dedicated for messaging 10199 * between host and target when the DUT is in UMAC hang recovery mode). 10200 * This H2T message is expected to be only sent if the WMI service bit 10201 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target. 10202 * 10203 * |31 16|15 12|11 8|7 0| 10204 * |-------------------------------+--------------+--------------+------------| 10205 * | reserved |h2t msg method|t2h msg method| msg_type | 10206 * |--------------------------------------------------------------------------| 10207 * | t2h msi interrupt number | 10208 * |--------------------------------------------------------------------------| 10209 * | shared memory area size | 10210 * |--------------------------------------------------------------------------| 10211 * | shared memory area physical address low | 10212 * |--------------------------------------------------------------------------| 10213 * | shared memory area physical address high | 10214 * |--------------------------------------------------------------------------| 10215 * 10216 * The message is interpreted as follows: 10217 * dword0 - b'0:7 - msg_type 10218 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP) 10219 * b'8:11 - t2h_msg_method: indicates method to be used for 10220 * T2H communication in UMAC hang recovery mode. 10221 * Value zero indicates MSI interrupt (default method). 10222 * Refer to htt_umac_hang_recovery_msg_method enum. 10223 * b'12:15 - h2t_msg_method: indicates method to be used for 10224 * H2T communication in UMAC hang recovery mode. 10225 * Value zero indicates polling by target for this h2t msg 10226 * during UMAC hang recovery mode. 10227 * Refer to htt_umac_hang_recovery_msg_method enum. 10228 * b'16:31 - reserved. 10229 * dword1 - b'0:31 - t2h_msi_data: MSI data to be used for 10230 * T2H communication in UMAC hang recovery mode. 10231 * dword2 - b'0:31 - size: size of shared memory dedicated for messaging 10232 * only when in UMAC hang recovery mode. 10233 * This refers to size in bytes. 10234 * dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address 10235 * of the shared memory dedicated for messaging only when 10236 * in UMAC hang recovery mode. 10237 * dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address 10238 * of the shared memory dedicated for messaging only when 10239 * in UMAC hang recovery mode. 10240 */ 10241 10242 /* t2h_msg_method and h2t_msg_method */ 10243 enum htt_umac_hang_recovery_msg_method { 10244 htt_umac_hang_recovery_msg_t2h_msi_and_h2t_polling = 0, 10245 }; 10246 10247 PREPACK typedef struct { 10248 A_UINT32 msg_type : 8, 10249 t2h_msg_method : 4, 10250 h2t_msg_method : 4, 10251 reserved : 16; 10252 A_UINT32 t2h_msi_data; 10253 /* size bytes and physical address of shared memory. */ 10254 struct htt_h2t_host_paddr_size_entry_t msg_shared_mem; 10255 } POSTPACK htt_h2t_umac_hang_recovery_prerequisite_setup_t; 10256 10257 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES \ 10258 (sizeof(htt_h2t_umac_hang_recovery_prerequisite_setup_t)) 10259 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_DWORDS \ 10260 (HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES >> 2) 10261 10262 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M 0x00000F00 10263 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S 8 10264 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_GET(word0) \ 10265 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M) >> \ 10266 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S) 10267 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_SET(word0, _val) \ 10268 do { \ 10269 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD, _val); \ 10270 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S));\ 10271 } while (0) 10272 10273 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M 0x0000F000 10274 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S 12 10275 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_GET(word0) \ 10276 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M) >> \ 10277 HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S) 10278 #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_SET(word0, _val) \ 10279 do { \ 10280 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD, _val); \ 10281 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\ 10282 } while (0) 10283 10284 /** 10285 * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET message 10286 * 10287 * @details 10288 * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level 10289 * HTT message sent by the host to indicate that the target needs to start the 10290 * UMAC hang recovery feature from the point of pre-reset routine. 10291 * The purpose of this H2T message is to have host synchronize and trigger 10292 * UMAC recovery across all targets. 10293 * The info sent in this H2T message is the flag to indicate whether the 10294 * target needs to execute UMAC-recovery in context of the Initiator or 10295 * Non-Initiator. 10296 * This H2T message is expected to be sent as response to the 10297 * initiate_umac_recovery indication from the Initiator target attached to 10298 * this same host. 10299 * This H2T message is expected to be only sent if the WMI service bit 10300 * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target 10301 * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent 10302 * beforehand. 10303 * 10304 * |31 10|9|8|7 0| 10305 * |-----------------------------------------------------------| 10306 * | reserved |U|I| msg_type | 10307 * |-----------------------------------------------------------| 10308 * Where: 10309 * I = is_initiator 10310 * U = is_umac_hang 10311 * 10312 * The message is interpreted as follows: 10313 * dword0 - b'0:7 - msg_type 10314 * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET) 10315 * b'8 - is_initiator: indicates whether the target needs to 10316 * execute the UMAC-recovery in context of the Initiator or 10317 * Non-Initiator. 10318 * The value zero indicates this target is Non-Initiator. 10319 * b'9 - is_umac_hang: indicates whether MLO UMAC recovery 10320 * executed in context of UMAC hang or Target recovery. 10321 * b'10:31 - reserved. 10322 */ 10323 10324 PREPACK typedef struct { 10325 A_UINT32 msg_type : 8, 10326 is_initiator : 1, 10327 is_umac_hang : 1, 10328 reserved : 22; 10329 } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; 10330 10331 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ 10332 (sizeof(htt_h2t_umac_hang_recovery_start_pre_reset_t)) 10333 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_DWORDS \ 10334 (HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES >> 2) 10335 10336 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M 0x00000100 10337 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S 8 10338 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_GET(word0) \ 10339 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M) >> \ 10340 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S) 10341 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_SET(word0, _val) \ 10342 do { \ 10343 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR, _val); \ 10344 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ 10345 } while (0) 10346 10347 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 10348 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 10349 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ 10350 (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ 10351 HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) 10352 #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ 10353 do { \ 10354 HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ 10355 ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ 10356 } while (0) 10357 10358 10359 /* 10360 * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message 10361 * 10362 * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP 10363 * 10364 * @details 10365 * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request, 10366 * install or uninstall rx cce super rules to match certain kind of packets 10367 * with specific parameters. Target sets up HW registers based on setup message 10368 * and always confirms back to Host. 10369 * 10370 * The message would appear as follows: 10371 * |31 24|23 16|15 8|7 0| 10372 * |-----------------+-----------------+-----------------+-----------------| 10373 * | reserved | operation | pdev_id | msg_type | 10374 * |-----------------------------------------------------------------------| 10375 * | cce_super_rule_param[0] | 10376 * |-----------------------------------------------------------------------| 10377 * | cce_super_rule_param[1] | 10378 * |-----------------------------------------------------------------------| 10379 * 10380 * The message is interpreted as follows: 10381 * dword0 - b'0:7 - msg_type: This will be set to 10382 * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) 10383 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for 10384 * b'16:23 - operation: Identify operation to be taken, 10385 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 10386 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL 10387 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE 10388 * b'24:31 - reserved 10389 * dword1~10 - cce_super_rule_param[0]: 10390 * contains parameters used to setup RX_CCE_SUPER_RULE_0 10391 * dword11~20 - cce_super_rule_param[1]: 10392 * contains parameters used to setup RX_CCE_SUPER_RULE_1 10393 * 10394 * Each cce_super_rule_param structure would appear as follows: 10395 * |31 24|23 16|15 8|7 0| 10396 * |-----------------+-----------------+-----------------+-----------------| 10397 * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | 10398 * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| 10399 * |-----------------------------------------------------------------------| 10400 * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | 10401 * |-----------------------------------------------------------------------| 10402 * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | 10403 * |-----------------------------------------------------------------------| 10404 * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| 10405 * |-----------------------------------------------------------------------| 10406 * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | 10407 * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| 10408 * |-----------------------------------------------------------------------| 10409 * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | 10410 * |-----------------------------------------------------------------------| 10411 * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | 10412 * |-----------------------------------------------------------------------| 10413 * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| 10414 * |-----------------------------------------------------------------------| 10415 * | is_valid | l4_type | l3_type | 10416 * |-----------------------------------------------------------------------| 10417 * | l4_dst_port | l4_src_port | 10418 * |-----------------------------------------------------------------------| 10419 * 10420 * The cce_super_rule_param[0] structure is interpreted as follows: 10421 * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address 10422 * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address, 10423 * in case of ipv4) 10424 * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address 10425 * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address, 10426 * in case of ipv4) 10427 * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address 10428 * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address, 10429 * in case of ipv4) 10430 * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address 10431 * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address, 10432 * in case of ipv4) 10433 * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address 10434 * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address 10435 * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address 10436 * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address 10437 * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address 10438 * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address 10439 * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address 10440 * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address 10441 * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address 10442 * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address 10443 * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address 10444 * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address 10445 * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address 10446 * (or dst_ipv4_addr[0]: b'24:31 of destination 10447 * ipv4 address, in case of ipv4) 10448 * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address 10449 * (or dst_ipv4_addr[1]: b'16:23 of destination 10450 * ipv4 address, in case of ipv4) 10451 * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address 10452 * (or dst_ipv4_addr[2]: b'8:15 of destination 10453 * ipv4 address, in case of ipv4) 10454 * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address 10455 * (or dst_ipv4_addr[3]: b'0:7 of destination 10456 * ipv4 address, in case of ipv4) 10457 * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address 10458 * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address 10459 * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address 10460 * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address 10461 * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address 10462 * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address 10463 * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address 10464 * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address 10465 * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address 10466 * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address 10467 * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address 10468 * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address 10469 * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used 10470 * 0x0008: ipv4 10471 * 0xdd86: ipv6 10472 * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used 10473 * 6: TCP 10474 * 17: UDP 10475 * b'24:31 - is_valid: indicate whether this parameter is valid 10476 * 0: invalid 10477 * 1: valid 10478 * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field 10479 * b'16:31 - l4_dst_port: TCP/UDP destination port field 10480 * 10481 * The cce_super_rule_param[1] structure is similar. 10482 */ 10483 #define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2 10484 10485 enum htt_rx_cce_super_rule_setup_operation { 10486 HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0, 10487 HTT_RX_CCE_SUPER_RULE_INSTALL, 10488 HTT_RX_CCE_SUPER_RULE_RELEASE, 10489 10490 /* All operation should be before this */ 10491 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION, 10492 }; 10493 10494 typedef struct { 10495 union { 10496 A_UINT8 src_ipv4_addr[4]; 10497 A_UINT8 src_ipv6_addr[16]; 10498 }; 10499 union { 10500 A_UINT8 dst_ipv4_addr[4]; 10501 A_UINT8 dst_ipv6_addr[16]; 10502 }; 10503 A_UINT32 l3_type: 16, 10504 l4_type: 8, 10505 is_valid: 8; 10506 A_UINT32 l4_src_port: 16, 10507 l4_dst_port: 16; 10508 } htt_rx_cce_super_rule_param_t; 10509 10510 PREPACK struct htt_rx_cce_super_rule_setup_t { 10511 A_UINT32 msg_type: 8, 10512 pdev_id: 8, 10513 operation: 8, 10514 reserved: 8; 10515 htt_rx_cce_super_rule_param_t 10516 cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM]; 10517 } POSTPACK; 10518 10519 #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ 10520 (sizeof(struct htt_rx_cce_super_rule_setup_t)) 10521 10522 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 10523 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 10524 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ 10525 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ 10526 HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) 10527 #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ 10528 do { \ 10529 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ 10530 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ 10531 } while (0) 10532 10533 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 10534 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16 10535 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ 10536 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \ 10537 HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S) 10538 #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ 10539 do { \ 10540 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \ 10541 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \ 10542 } while (0) 10543 10544 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff 10545 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0 10546 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ 10547 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ 10548 HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S) 10549 #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ 10550 do { \ 10551 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ 10552 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ 10553 } while (0) 10554 10555 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 10556 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16 10557 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ 10558 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ 10559 HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S) 10560 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ 10561 do { \ 10562 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ 10563 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ 10564 } while (0) 10565 10566 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 10567 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24 10568 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ 10569 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ 10570 HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S) 10571 #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ 10572 do { \ 10573 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \ 10574 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \ 10575 } while (0) 10576 10577 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff 10578 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 10579 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ 10580 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ 10581 HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) 10582 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ 10583 do { \ 10584 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ 10585 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ 10586 } while (0) 10587 10588 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 10589 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 10590 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ 10591 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ 10592 HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S) 10593 #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ 10594 do { \ 10595 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ 10596 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ 10597 } while (0) 10598 10599 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ 10600 do { \ 10601 A_MEMCPY(_array, _ptr, 4); \ 10602 } while (0) 10603 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ 10604 do { \ 10605 A_MEMCPY(_ptr, _array, 4); \ 10606 } while (0) 10607 10608 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ 10609 do { \ 10610 A_MEMCPY(_array, _ptr, 16); \ 10611 } while (0) 10612 #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ 10613 do { \ 10614 A_MEMCPY(_ptr, _array, 16); \ 10615 } while (0) 10616 10617 10618 /** 10619 * htt_h2t_primary_link_peer_status_type - 10620 * Unique number for each status or reasons 10621 * The status reasons can go up to 255 max 10622 */ 10623 enum htt_h2t_primary_link_peer_status_type { 10624 /* Host Primary Link Peer migration Success */ 10625 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, 10626 10627 10628 /* keep this last */ 10629 /* Host Primary Link Peer migration Fail */ 10630 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, 10631 HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 10632 }; 10633 10634 10635 /** 10636 * @brief host -> Primary peer migration completion message from host 10637 * 10638 * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP 10639 * 10640 * @details 10641 * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to 10642 * target Confirming that primary link peer migration has completed, 10643 * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 10644 * message from the target. 10645 * 10646 * The message would appear as follows: 10647 * 10648 * |31 25|24|23 16|15 12|11 8|7 0| 10649 * |----------------------------+----------+---------+--------------| 10650 * | vdev ID | pdev ID | chip ID | msg type | 10651 * |----------------------------+----------+---------+--------------| 10652 * | ML peer ID | SW peer ID | 10653 * |------------+--+------------+--------------------+--------------| 10654 * | reserved |SV| src_info | status | 10655 * |------------+--+---------------------------------+--------------| 10656 * Where: 10657 * SV = src_info_valid flag 10658 * 10659 * The message is interpreted as follows: 10660 * dword0 - b'0:7 - msg_type: This will be set to 0x24 10661 * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) 10662 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 10663 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 10664 * as primary 10665 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 10666 * as primary 10667 * 10668 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 10669 * chosen as primary 10670 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 10671 * primary peer belongs. 10672 * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration 10673 * b'8:23 - src_info: Indicates New Virtual port number through 10674 * which Rx Pipe connects to the correct PPE. 10675 * b'24 - src_info_valid: Indicates src_info is valid. 10676 */ 10677 10678 typedef struct { 10679 A_UINT32 msg_type: 8, /* bits 7:0 */ 10680 chip_id: 4, /* bits 11:8 */ 10681 pdev_id: 4, /* bits 15:12 */ 10682 vdev_id: 16; /* bits 31:16 */ 10683 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 10684 ml_peer_id: 16; /* bits 31:16 */ 10685 A_UINT32 status: 8, /* bits 7:0 */ 10686 src_info: 16, /* bits 23:8 */ 10687 src_info_valid: 1, /* bit 24 */ 10688 reserved: 7; /* bits 31:25 */ 10689 } htt_h2t_primary_link_peer_migrate_resp_t; 10690 10691 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 10692 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 10693 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 10694 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 10695 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 10696 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 10697 do { \ 10698 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 10699 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 10700 } while (0) 10701 10702 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 10703 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 10704 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 10705 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 10706 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 10707 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 10708 do { \ 10709 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 10710 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 10711 } while (0) 10712 10713 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 10714 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 10715 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 10716 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 10717 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 10718 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 10719 do { \ 10720 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 10721 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 10722 } while (0) 10723 10724 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 10725 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 10726 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 10727 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 10728 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 10729 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 10730 do { \ 10731 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 10732 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 10733 } while (0) 10734 10735 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 10736 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 10737 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 10738 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 10739 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 10740 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 10741 do { \ 10742 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 10743 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 10744 } while (0) 10745 10746 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF 10747 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 10748 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ 10749 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ 10750 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) 10751 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ 10752 do { \ 10753 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ 10754 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ 10755 } while (0) 10756 10757 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 10758 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 10759 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ 10760 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ 10761 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) 10762 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ 10763 do { \ 10764 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ 10765 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ 10766 } while (0) 10767 10768 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 10769 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 10770 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ 10771 (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ 10772 HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) 10773 #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ 10774 do { \ 10775 HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ 10776 ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ 10777 } while (0) 10778 10779 10780 /** 10781 * @brief host -> tgt msg to configure params for PPDU tx latency stats report 10782 * 10783 * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG 10784 * 10785 * @details 10786 * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to 10787 * configure the parameters needed for FW to report PPDU tx latency stats 10788 * for latency prediction in user space. 10789 * 10790 * The message would appear as follows: 10791 * |31 28|27 12|11|10 8|7 0| 10792 * |-----------+-------------------+--+-------+--------------| 10793 * |granularity| periodic interval | E|vdev ID| msg type | 10794 * |-----------+-------------------+--+-------+--------------| 10795 * Where: E = enable 10796 * 10797 * The message is interpreted as follows: 10798 * dword0 - b'0:7 - msg_type: This will be set to 0x25 10799 * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG) 10800 * b'8:10 - vdev_id: Indicate which vdev is configuration is for 10801 * b'11 - enable: Indicate this message is to enable/disable 10802 * PPDU latency report from FW 10803 * b'12:27 - periodic_interval: Indicate the report interval in MS 10804 * b'28:31 - granularity: Indicate the granularity of the latency 10805 * stats report, in ms 10806 */ 10807 10808 /* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */ 10809 PREPACK struct htt_h2t_tx_latency_stats_cfg { 10810 A_UINT32 msg_type :8, 10811 vdev_id :3, 10812 enable :1, 10813 periodic_interval :16, 10814 granularity :4; 10815 } POSTPACK; 10816 10817 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700 10818 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8 10819 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \ 10820 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \ 10821 HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S) 10822 #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \ 10823 do { \ 10824 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \ 10825 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \ 10826 } while (0) 10827 10828 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800 10829 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11 10830 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \ 10831 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \ 10832 HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S) 10833 #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \ 10834 do { \ 10835 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \ 10836 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \ 10837 } while (0) 10838 10839 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000 10840 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12 10841 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \ 10842 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \ 10843 HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S) 10844 #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \ 10845 do { \ 10846 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \ 10847 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \ 10848 } while (0) 10849 10850 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000 10851 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28 10852 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \ 10853 (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \ 10854 HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S) 10855 #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \ 10856 do { \ 10857 HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \ 10858 ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \ 10859 } while (0) 10860 10861 10862 10863 /*=== target -> host messages ===============================================*/ 10864 10865 10866 enum htt_t2h_msg_type { 10867 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 10868 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 10869 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 10870 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 10871 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 10872 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 10873 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 10874 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 10875 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 10876 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 10877 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 10878 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 10879 DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* no longer used */ 10880 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 10881 HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 10882 /* only used for HL, add HTT MSG for HTT CREDIT update */ 10883 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 10884 HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, 10885 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 10886 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 10887 /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ 10888 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 10889 HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 10890 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 10891 HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, 10892 HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, 10893 HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, 10894 HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a, 10895 HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b, 10896 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 10897 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 10898 HTT_T2H_MSG_TYPE_PEER_MAP_V2 = 0x1e, 10899 HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f, 10900 HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20, 10901 HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21, 10902 HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22, 10903 HTT_T2H_MSG_TYPE_PEER_STATS_IND = 0x23, 10904 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 10905 /* TX_OFFLOAD_DELIVER_IND: 10906 * Forward the target's locally-generated packets to the host, 10907 * to provide to the monitor mode interface. 10908 */ 10909 HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25, 10910 HTT_T2H_MSG_TYPE_CHAN_CALDATA = 0x26, 10911 HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND = 0x27, 10912 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 10913 HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29, 10914 HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP = 0x2a, 10915 HTT_T2H_MSG_TYPE_PEER_MAP_V3 = 0x2b, 10916 HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND = 0x2c, 10917 HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, 10918 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, /* alias */ 10919 HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e, 10920 HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */ 10921 HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f, 10922 HTT_T2H_PPDU_ID_FMT_IND = 0x30, 10923 HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, 10924 HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, 10925 HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, 10926 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */ 10927 HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, 10928 HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, 10929 HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, 10930 HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, 10931 HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, 10932 HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a, 10933 10934 10935 HTT_T2H_MSG_TYPE_TEST, 10936 /* keep this last */ 10937 HTT_T2H_NUM_MSGS 10938 }; 10939 10940 /* 10941 * HTT target to host message type - 10942 * stored in bits 7:0 of the first word of the message 10943 */ 10944 #define HTT_T2H_MSG_TYPE_M 0xff 10945 #define HTT_T2H_MSG_TYPE_S 0 10946 10947 #define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ 10948 do { \ 10949 HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ 10950 (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ 10951 } while (0) 10952 #define HTT_T2H_MSG_TYPE_GET(word) \ 10953 (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) 10954 10955 /** 10956 * @brief target -> host version number confirmation message definition 10957 * 10958 * MSG_TYPE => HTT_T2H_MSG_TYPE_VERSION_CONF 10959 * 10960 * |31 24|23 16|15 8|7 0| 10961 * |----------------+----------------+----------------+----------------| 10962 * | reserved | major number | minor number | msg type | 10963 * |-------------------------------------------------------------------| 10964 * : option request TLV (optional) | 10965 * :...................................................................: 10966 * 10967 * The VER_CONF message may consist of a single 4-byte word, or may be 10968 * extended with TLVs that specify HTT options selected by the target. 10969 * The following option TLVs may be appended to the VER_CONF message: 10970 * - LL_BUS_ADDR_SIZE 10971 * - HL_SUPPRESS_TX_COMPL_IND 10972 * - MAX_TX_QUEUE_GROUPS 10973 * These TLVs may appear in an arbitrary order. Any number of these TLVs 10974 * may be appended to the VER_CONF message (but only one TLV of each type). 10975 * 10976 * Header fields: 10977 * - MSG_TYPE 10978 * Bits 7:0 10979 * Purpose: identifies this as a version number confirmation message 10980 * Value: 0x0 (HTT_T2H_MSG_TYPE_VERSION_CONF) 10981 * - VER_MINOR 10982 * Bits 15:8 10983 * Purpose: Specify the minor number of the HTT message library version 10984 * in use by the target firmware. 10985 * The minor number specifies the specific revision within a range 10986 * of fundamentally compatible HTT message definition revisions. 10987 * Compatible revisions involve adding new messages or perhaps 10988 * adding new fields to existing messages, in a backwards-compatible 10989 * manner. 10990 * Incompatible revisions involve changing the message type values, 10991 * or redefining existing messages. 10992 * Value: minor number 10993 * - VER_MAJOR 10994 * Bits 15:8 10995 * Purpose: Specify the major number of the HTT message library version 10996 * in use by the target firmware. 10997 * The major number specifies the family of minor revisions that are 10998 * fundamentally compatible with each other, but not with prior or 10999 * later families. 11000 * Value: major number 11001 */ 11002 11003 #define HTT_VER_CONF_MINOR_M 0x0000ff00 11004 #define HTT_VER_CONF_MINOR_S 8 11005 #define HTT_VER_CONF_MAJOR_M 0x00ff0000 11006 #define HTT_VER_CONF_MAJOR_S 16 11007 11008 11009 #define HTT_VER_CONF_MINOR_SET(word, value) \ 11010 do { \ 11011 HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ 11012 (word) |= (value) << HTT_VER_CONF_MINOR_S; \ 11013 } while (0) 11014 #define HTT_VER_CONF_MINOR_GET(word) \ 11015 (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) 11016 11017 #define HTT_VER_CONF_MAJOR_SET(word, value) \ 11018 do { \ 11019 HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ 11020 (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ 11021 } while (0) 11022 #define HTT_VER_CONF_MAJOR_GET(word) \ 11023 (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) 11024 11025 11026 #define HTT_VER_CONF_BYTES 4 11027 11028 11029 /** 11030 * @brief - target -> host HTT Rx In order indication message 11031 * 11032 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND 11033 * 11034 * @details 11035 * 11036 * |31 24|23 |15|14|13|12|11|10|9|8|7|6|5|4 0| 11037 * |----------------+-------------------+---------------------+---------------| 11038 * | peer ID | P| F| O| ext TID | msg type | 11039 * |--------------------------------------------------------------------------| 11040 * | MSDU count | Reserved | vdev id | 11041 * |--------------------------------------------------------------------------| 11042 * | MSDU 0 bus address (bits 31:0) | 11043 #if HTT_PADDR64 11044 * | MSDU 0 bus address (bits 63:32) | 11045 #endif 11046 * |--------------------------------------------------------------------------| 11047 * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length | 11048 * |--------------------------------------------------------------------------| 11049 * | MSDU 1 bus address (bits 31:0) | 11050 #if HTT_PADDR64 11051 * | MSDU 1 bus address (bits 63:32) | 11052 #endif 11053 * |--------------------------------------------------------------------------| 11054 * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length | 11055 * |--------------------------------------------------------------------------| 11056 */ 11057 11058 11059 /** @brief - MSDU info byte for TCP_CHECKSUM_OFFLOAD use 11060 * 11061 * @details 11062 * bits 11063 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 11064 * |-----+----+-------+--------+--------+---------+---------+-----------| 11065 * | reserved | is IP | is UDP | is TCP | is IPv6 |IP chksum| TCP/UDP | 11066 * | | frag | | | | fail |chksum fail| 11067 * |-----+----+-------+--------+--------+---------+---------+-----------| 11068 * (see fw_rx_msdu_info def in wal_rx_desc.h) 11069 */ 11070 11071 struct htt_rx_in_ord_paddr_ind_hdr_t 11072 { 11073 A_UINT32 /* word 0 */ 11074 msg_type: 8, 11075 ext_tid: 5, 11076 offload: 1, 11077 frag: 1, 11078 pktlog: 1, /* tell host whether to store MSDUs referenced in this message in pktlog */ 11079 peer_id: 16; 11080 11081 A_UINT32 /* word 1 */ 11082 vap_id: 8, 11083 /* NOTE: 11084 * This reserved_1 field is not truly reserved - certain targets use 11085 * this field internally to store debug information, and do not zero 11086 * out the contents of the field before uploading the message to the 11087 * host. Thus, any host-target communication supported by this field 11088 * is limited to using values that are never used by the debug 11089 * information stored by certain targets in the reserved_1 field. 11090 * In particular, the targets in question don't use the value 0x3 11091 * within bits 7:6 of this field (i.e. bits 15:14 of the A_UINT32), 11092 * so this previously-unused value within these bits is available to 11093 * use as the host / target PKT_CAPTURE_MODE flag. 11094 */ 11095 reserved_1: 8, /* reserved_1a: 6, pkt_capture_mode: 2, */ 11096 /* if pkt_capture_mode == 0x3, host should 11097 * send rx frames to monitor mode interface 11098 */ 11099 msdu_cnt: 16; 11100 }; 11101 11102 struct htt_rx_in_ord_paddr_ind_msdu32_t 11103 { 11104 A_UINT32 dma_addr; 11105 A_UINT32 11106 length: 16, 11107 fw_desc: 8, 11108 msdu_info:8; 11109 }; 11110 struct htt_rx_in_ord_paddr_ind_msdu64_t 11111 { 11112 A_UINT32 dma_addr_lo; 11113 A_UINT32 dma_addr_hi; 11114 A_UINT32 11115 length: 16, 11116 fw_desc: 8, 11117 msdu_info:8; 11118 }; 11119 #if HTT_PADDR64 11120 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t 11121 #else 11122 #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t 11123 #endif 11124 11125 11126 #define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) 11127 #define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) 11128 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES 11129 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS 11130 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) 11131 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) 11132 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) 11133 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) 11134 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) 11135 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) 11136 11137 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00 11138 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8 11139 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M 0x00002000 11140 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S 13 11141 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_M 0x00004000 11142 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_S 14 11143 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M 0x00008000 11144 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S 15 11145 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M 0xffff0000 11146 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16 11147 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff 11148 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0 11149 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M 0x0000c000 11150 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S 14 11151 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000 11152 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16 11153 /* for systems using 64-bit format for bus addresses */ 11154 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M 0xffffffff 11155 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S 0 11156 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M 0xffffffff 11157 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S 0 11158 /* for systems using 32-bit format for bus addresses */ 11159 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_M 0xffffffff 11160 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_S 0 11161 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M 0x0000ffff 11162 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S 0 11163 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M 0x00ff0000 11164 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S 16 11165 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M 0xff000000 11166 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24 11167 11168 11169 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ 11170 do { \ 11171 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ 11172 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ 11173 } while (0) 11174 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ 11175 (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) 11176 11177 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ 11178 do { \ 11179 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ 11180 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ 11181 } while (0) 11182 #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ 11183 (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) 11184 11185 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ 11186 do { \ 11187 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ 11188 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ 11189 } while (0) 11190 #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ 11191 (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) 11192 11193 /* 11194 * If the PKT_CAPTURE_MODE flags value is MONITOR (0x3), the host should 11195 * deliver the rx frames to the monitor mode interface. 11196 * The HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET macro 11197 * sets the PKT_CAPTURE_MODE flags value to MONITOR, and the 11198 * HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET macro 11199 * checks whether the PKT_CAPTURE_MODE flags value is MONITOR. 11200 */ 11201 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR 0x3 11202 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET(word) \ 11203 do { \ 11204 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE, HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR); \ 11205 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S; \ 11206 } while (0) 11207 #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET(word) \ 11208 ((((word) & HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M) >> HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S) == \ 11209 HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR) 11210 11211 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ 11212 do { \ 11213 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ 11214 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ 11215 } while (0) 11216 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ 11217 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) 11218 11219 /* for systems using 64-bit format for bus addresses */ 11220 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ 11221 do { \ 11222 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ 11223 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ 11224 } while (0) 11225 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ 11226 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) 11227 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ 11228 do { \ 11229 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ 11230 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ 11231 } while (0) 11232 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ 11233 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) 11234 11235 /* for systems using 32-bit format for bus addresses */ 11236 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ 11237 do { \ 11238 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ 11239 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ 11240 } while (0) 11241 #define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ 11242 (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_S) 11243 11244 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ 11245 do { \ 11246 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value); \ 11247 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ 11248 } while (0) 11249 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \ 11250 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) 11251 11252 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ 11253 do { \ 11254 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ 11255 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ 11256 } while (0) 11257 #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ 11258 (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) 11259 11260 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ 11261 do { \ 11262 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value); \ 11263 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S; \ 11264 } while (0) 11265 #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \ 11266 (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) 11267 11268 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ 11269 do { \ 11270 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value); \ 11271 (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ 11272 } while (0) 11273 #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ 11274 (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) 11275 11276 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ 11277 do { \ 11278 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ 11279 (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ 11280 } while (0) 11281 #define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ 11282 (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> HTT_RX_IN_ORD_PADDR_IND_FRAG_S) 11283 11284 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_SET(word, value) \ 11285 do { \ 11286 HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \ 11287 (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \ 11288 } while (0) 11289 #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \ 11290 (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S) 11291 11292 11293 /* definitions used within target -> host rx indication message */ 11294 11295 PREPACK struct htt_rx_ind_hdr_prefix_t 11296 { 11297 A_UINT32 /* word 0 */ 11298 msg_type: 8, 11299 ext_tid: 5, 11300 release_valid: 1, 11301 flush_valid: 1, 11302 reserved0: 1, 11303 peer_id: 16; 11304 11305 A_UINT32 /* word 1 */ 11306 flush_start_seq_num: 6, 11307 flush_end_seq_num: 6, 11308 release_start_seq_num: 6, 11309 release_end_seq_num: 6, 11310 num_mpdu_ranges: 8; 11311 } POSTPACK; 11312 11313 #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t)) 11314 #define HTT_RX_IND_HDR_PREFIX_SIZE32 (HTT_RX_IND_HDR_PREFIX_BYTES >> 2) 11315 11316 #define HTT_TGT_RSSI_INVALID 0x80 11317 11318 PREPACK struct htt_rx_ppdu_desc_t 11319 { 11320 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 11321 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 11322 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 11323 #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 11324 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 11325 #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 11326 #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 11327 #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 11328 A_UINT32 /* word 0 */ 11329 rssi_cmb: 8, 11330 timestamp_submicrosec: 8, 11331 phy_err_code: 8, 11332 phy_err: 1, 11333 legacy_rate: 4, 11334 legacy_rate_sel: 1, 11335 end_valid: 1, 11336 start_valid: 1; 11337 11338 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 11339 union { 11340 A_UINT32 /* word 1 */ 11341 rssi0_pri20: 8, 11342 rssi0_ext20: 8, 11343 rssi0_ext40: 8, 11344 rssi0_ext80: 8; 11345 A_UINT32 rssi0; /* access all 20/40/80 per-bandwidth RSSIs together */ 11346 } u0; 11347 11348 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 11349 union { 11350 A_UINT32 /* word 2 */ 11351 rssi1_pri20: 8, 11352 rssi1_ext20: 8, 11353 rssi1_ext40: 8, 11354 rssi1_ext80: 8; 11355 A_UINT32 rssi1; /* access all 20/40/80 per-bandwidth RSSIs together */ 11356 } u1; 11357 11358 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 11359 union { 11360 A_UINT32 /* word 3 */ 11361 rssi2_pri20: 8, 11362 rssi2_ext20: 8, 11363 rssi2_ext40: 8, 11364 rssi2_ext80: 8; 11365 A_UINT32 rssi2; /* access all 20/40/80 per-bandwidth RSSIs together */ 11366 } u2; 11367 11368 #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 11369 union { 11370 A_UINT32 /* word 4 */ 11371 rssi3_pri20: 8, 11372 rssi3_ext20: 8, 11373 rssi3_ext40: 8, 11374 rssi3_ext80: 8; 11375 A_UINT32 rssi3; /* access all 20/40/80 per-bandwidth RSSIs together */ 11376 } u3; 11377 11378 #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 11379 A_UINT32 tsf32; /* word 5 */ 11380 11381 #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 11382 A_UINT32 timestamp_microsec; /* word 6 */ 11383 11384 #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 11385 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 11386 A_UINT32 /* word 7 */ 11387 vht_sig_a1: 24, 11388 preamble_type: 8; 11389 11390 #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 11391 #define HTT_RX_IND_PPDU_OFFSET_WORD_SA_ANT_MATRIX 8 11392 A_UINT32 /* word 8 */ 11393 vht_sig_a2: 24, 11394 /* sa_ant_matrix 11395 * For cases where a single rx chain has options to be connected to 11396 * different rx antennas, show which rx antennas were in use during 11397 * receipt of a given PPDU. 11398 * This sa_ant_matrix provides a bitmask of the antennas used while 11399 * receiving this frame. 11400 */ 11401 sa_ant_matrix: 8; 11402 } POSTPACK; 11403 11404 #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t)) 11405 #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2) 11406 11407 PREPACK struct htt_rx_ind_hdr_suffix_t 11408 { 11409 A_UINT32 /* word 0 */ 11410 fw_rx_desc_bytes: 16, 11411 reserved0: 16; 11412 } POSTPACK; 11413 11414 #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t)) 11415 #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2) 11416 11417 PREPACK struct htt_rx_ind_hdr_t 11418 { 11419 struct htt_rx_ind_hdr_prefix_t prefix; 11420 struct htt_rx_ppdu_desc_t rx_ppdu_desc; 11421 struct htt_rx_ind_hdr_suffix_t suffix; 11422 } POSTPACK; 11423 11424 #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t)) 11425 #define HTT_RX_IND_HDR_SIZE32 (HTT_RX_IND_HDR_BYTES >> 2) 11426 11427 /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */ 11428 A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, 11429 (HTT_RX_IND_HDR_BYTES & 0x3) == 0); 11430 11431 /* 11432 * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET: 11433 * the offset into the HTT rx indication message at which the 11434 * FW rx PPDU descriptor resides 11435 */ 11436 #define HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET HTT_RX_IND_HDR_PREFIX_BYTES 11437 11438 /* 11439 * HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET: 11440 * the offset into the HTT rx indication message at which the 11441 * header suffix (FW rx MSDU byte count) resides 11442 */ 11443 #define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ 11444 (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) 11445 11446 /* 11447 * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET: 11448 * the offset into the HTT rx indication message at which the per-MSDU 11449 * information starts 11450 * Bytes 0-7 are the message header; bytes 8-11 contain the length of the 11451 * per-MSDU information portion of the message. The per-MSDU info itself 11452 * starts at byte 12. 11453 */ 11454 #define HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET HTT_RX_IND_HDR_BYTES 11455 11456 11457 /** 11458 * @brief target -> host rx indication message definition 11459 * 11460 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IND 11461 * 11462 * @details 11463 * The following field definitions describe the format of the rx indication 11464 * message sent from the target to the host. 11465 * The message consists of three major sections: 11466 * 1. a fixed-length header 11467 * 2. a variable-length list of firmware rx MSDU descriptors 11468 * 3. one or more 4-octet MPDU range information elements 11469 * The fixed length header itself has two sub-sections 11470 * 1. the message meta-information, including identification of the 11471 * sender and type of the received data, and a 4-octet flush/release IE 11472 * 2. the firmware rx PPDU descriptor 11473 * 11474 * The format of the message is depicted below. 11475 * in this depiction, the following abbreviations are used for information 11476 * elements within the message: 11477 * - SV - start valid: this flag is set if the FW rx PPDU descriptor 11478 * elements associated with the PPDU start are valid. 11479 * Specifically, the following fields are valid only if SV is set: 11480 * RSSI (all variants), L, legacy rate, preamble type, service, 11481 * VHT-SIG-A 11482 * - EV - end valid: this flag is set if the FW rx PPDU descriptor 11483 * elements associated with the PPDU end are valid. 11484 * Specifically, the following fields are valid only if EV is set: 11485 * P, PHY err code, TSF, microsec / sub-microsec timestamp 11486 * - L - Legacy rate selector - if legacy rates are used, this flag 11487 * indicates whether the rate is from a CCK (L == 1) or OFDM 11488 * (L == 0) PHY. 11489 * - P - PHY error flag - boolean indication of whether the rx frame had 11490 * a PHY error 11491 * 11492 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 11493 * |----------------+-------------------+---------------------+---------------| 11494 * | peer ID | |RV|FV| ext TID | msg type | 11495 * |--------------------------------------------------------------------------| 11496 * | num | release | release | flush | flush | 11497 * | MPDU | end | start | end | start | 11498 * | ranges | seq num | seq num | seq num | seq num | 11499 * |==========================================================================| 11500 * |S|E|L| legacy |P| PHY err code | sub-microsec | combined | 11501 * |V|V| | rate | | | timestamp | RSSI | 11502 * |--------------------------------------------------------------------------| 11503 * | RSSI rx0 ext80 | RSSI rx0 ext40 | RSSI rx0 ext20 | RSSI rx0 pri20| 11504 * |--------------------------------------------------------------------------| 11505 * | RSSI rx1 ext80 | RSSI rx1 ext40 | RSSI rx1 ext20 | RSSI rx1 pri20| 11506 * |--------------------------------------------------------------------------| 11507 * | RSSI rx2 ext80 | RSSI rx2 ext40 | RSSI rx2 ext20 | RSSI rx2 pri20| 11508 * |--------------------------------------------------------------------------| 11509 * | RSSI rx3 ext80 | RSSI rx3 ext40 | RSSI rx3 ext20 | RSSI rx3 pri20| 11510 * |--------------------------------------------------------------------------| 11511 * | TSF LSBs | 11512 * |--------------------------------------------------------------------------| 11513 * | microsec timestamp | 11514 * |--------------------------------------------------------------------------| 11515 * | preamble type | HT-SIG / VHT-SIG-A1 | 11516 * |--------------------------------------------------------------------------| 11517 * | service | HT-SIG / VHT-SIG-A2 | 11518 * |==========================================================================| 11519 * | reserved | FW rx desc bytes | 11520 * |--------------------------------------------------------------------------| 11521 * | MSDU Rx | MSDU Rx | MSDU Rx | MSDU Rx | 11522 * | desc B3 | desc B2 | desc B1 | desc B0 | 11523 * |--------------------------------------------------------------------------| 11524 * : : : 11525 * |--------------------------------------------------------------------------| 11526 * | alignment | MSDU Rx | 11527 * | padding | desc Bn | 11528 * |--------------------------------------------------------------------------| 11529 * | reserved | MPDU range status | MPDU count | 11530 * |--------------------------------------------------------------------------| 11531 * : reserved : MPDU range status : MPDU count : 11532 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : 11533 * 11534 * Header fields: 11535 * - MSG_TYPE 11536 * Bits 7:0 11537 * Purpose: identifies this as an rx indication message 11538 * Value: 0x1 (HTT_T2H_MSG_TYPE_RX_IND) 11539 * - EXT_TID 11540 * Bits 12:8 11541 * Purpose: identify the traffic ID of the rx data, including 11542 * special "extended" TID values for multicast, broadcast, and 11543 * non-QoS data frames 11544 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 11545 * - FLUSH_VALID (FV) 11546 * Bit 13 11547 * Purpose: indicate whether the flush IE (start/end sequence numbers) 11548 * is valid 11549 * Value: 11550 * 1 -> flush IE is valid and needs to be processed 11551 * 0 -> flush IE is not valid and should be ignored 11552 * - REL_VALID (RV) 11553 * Bit 13 11554 * Purpose: indicate whether the release IE (start/end sequence numbers) 11555 * is valid 11556 * Value: 11557 * 1 -> release IE is valid and needs to be processed 11558 * 0 -> release IE is not valid and should be ignored 11559 * - PEER_ID 11560 * Bits 31:16 11561 * Purpose: Identify, by ID, which peer sent the rx data 11562 * Value: ID of the peer who sent the rx data 11563 * - FLUSH_SEQ_NUM_START 11564 * Bits 5:0 11565 * Purpose: Indicate the start of a series of MPDUs to flush 11566 * Not all MPDUs within this series are necessarily valid - the host 11567 * must check each sequence number within this range to see if the 11568 * corresponding MPDU is actually present. 11569 * This field is only valid if the FV bit is set. 11570 * Value: 11571 * The sequence number for the first MPDUs to check to flush. 11572 * The sequence number is masked by 0x3f. 11573 * - FLUSH_SEQ_NUM_END 11574 * Bits 11:6 11575 * Purpose: Indicate the end of a series of MPDUs to flush 11576 * Value: 11577 * The sequence number one larger than the sequence number of the 11578 * last MPDU to check to flush. 11579 * The sequence number is masked by 0x3f. 11580 * Not all MPDUs within this series are necessarily valid - the host 11581 * must check each sequence number within this range to see if the 11582 * corresponding MPDU is actually present. 11583 * This field is only valid if the FV bit is set. 11584 * - REL_SEQ_NUM_START 11585 * Bits 17:12 11586 * Purpose: Indicate the start of a series of MPDUs to release. 11587 * All MPDUs within this series are present and valid - the host 11588 * need not check each sequence number within this range to see if 11589 * the corresponding MPDU is actually present. 11590 * This field is only valid if the RV bit is set. 11591 * Value: 11592 * The sequence number for the first MPDUs to check to release. 11593 * The sequence number is masked by 0x3f. 11594 * - REL_SEQ_NUM_END 11595 * Bits 23:18 11596 * Purpose: Indicate the end of a series of MPDUs to release. 11597 * Value: 11598 * The sequence number one larger than the sequence number of the 11599 * last MPDU to check to release. 11600 * The sequence number is masked by 0x3f. 11601 * All MPDUs within this series are present and valid - the host 11602 * need not check each sequence number within this range to see if 11603 * the corresponding MPDU is actually present. 11604 * This field is only valid if the RV bit is set. 11605 * - NUM_MPDU_RANGES 11606 * Bits 31:24 11607 * Purpose: Indicate how many ranges of MPDUs are present. 11608 * Each MPDU range consists of a series of contiguous MPDUs within the 11609 * rx frame sequence which all have the same MPDU status. 11610 * Value: 1-63 (typically a small number, like 1-3) 11611 * 11612 * Rx PPDU descriptor fields: 11613 * - RSSI_CMB 11614 * Bits 7:0 11615 * Purpose: Combined RSSI from all active rx chains, across the active 11616 * bandwidth. 11617 * Value: RSSI dB units w.r.t. noise floor 11618 * - TIMESTAMP_SUBMICROSEC 11619 * Bits 15:8 11620 * Purpose: high-resolution timestamp 11621 * Value: 11622 * Sub-microsecond time of PPDU reception. 11623 * This timestamp ranges from [0,MAC clock MHz). 11624 * This timestamp can be used in conjunction with TIMESTAMP_MICROSEC 11625 * to form a high-resolution, large range rx timestamp. 11626 * - PHY_ERR_CODE 11627 * Bits 23:16 11628 * Purpose: 11629 * If the rx frame processing resulted in a PHY error, indicate what 11630 * type of rx PHY error occurred. 11631 * Value: 11632 * This field is valid if the "P" (PHY_ERR) flag is set. 11633 * TBD: document/specify the values for this field 11634 * - PHY_ERR 11635 * Bit 24 11636 * Purpose: indicate whether the rx PPDU had a PHY error 11637 * Value: 0 -> no rx PHY error, 1 -> rx PHY error encountered 11638 * - LEGACY_RATE 11639 * Bits 28:25 11640 * Purpose: 11641 * If the rx frame used a legacy rate rather than a HT or VHT rate, 11642 * specify which rate was used. 11643 * Value: 11644 * The LEGACY_RATE field's value depends on the "L" (LEGACY_RATE_SEL) 11645 * flag. 11646 * If LEGACY_RATE_SEL is 0: 11647 * 0x8: OFDM 48 Mbps 11648 * 0x9: OFDM 24 Mbps 11649 * 0xA: OFDM 12 Mbps 11650 * 0xB: OFDM 6 Mbps 11651 * 0xC: OFDM 54 Mbps 11652 * 0xD: OFDM 36 Mbps 11653 * 0xE: OFDM 18 Mbps 11654 * 0xF: OFDM 9 Mbps 11655 * If LEGACY_RATE_SEL is 1: 11656 * 0x8: CCK 11 Mbps long preamble 11657 * 0x9: CCK 5.5 Mbps long preamble 11658 * 0xA: CCK 2 Mbps long preamble 11659 * 0xB: CCK 1 Mbps long preamble 11660 * 0xC: CCK 11 Mbps short preamble 11661 * 0xD: CCK 5.5 Mbps short preamble 11662 * 0xE: CCK 2 Mbps short preamble 11663 * - LEGACY_RATE_SEL 11664 * Bit 29 11665 * Purpose: if rx used a legacy rate, specify whether it was OFDM or CCK 11666 * Value: 11667 * This field is valid if the PREAMBLE_TYPE field indicates the rx 11668 * used a legacy rate. 11669 * 0 -> OFDM, 1 -> CCK 11670 * - END_VALID 11671 * Bit 30 11672 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 11673 * the start of the PPDU are valid. Specifically, the following 11674 * fields are only valid if END_VALID is set: 11675 * PHY_ERR, PHY_ERR_CODE, TSF32, TIMESTAMP_MICROSEC, 11676 * TIMESTAMP_SUBMICROSEC 11677 * Value: 11678 * 0 -> rx PPDU desc end fields are not valid 11679 * 1 -> rx PPDU desc end fields are valid 11680 * - START_VALID 11681 * Bit 31 11682 * Purpose: Indicate whether the FW rx PPDU desc fields associated with 11683 * the end of the PPDU are valid. Specifically, the following 11684 * fields are only valid if START_VALID is set: 11685 * RSSI, LEGACY_RATE_SEL, LEGACY_RATE, PREAMBLE_TYPE, SERVICE, 11686 * VHT-SIG-A 11687 * Value: 11688 * 0 -> rx PPDU desc start fields are not valid 11689 * 1 -> rx PPDU desc start fields are valid 11690 * - RSSI0_PRI20 11691 * Bits 7:0 11692 * Purpose: RSSI from chain 0 on the primary 20 MHz channel 11693 * Value: RSSI dB units w.r.t. noise floor 11694 * 11695 * - RSSI0_EXT20 11696 * Bits 7:0 11697 * Purpose: RSSI from chain 0 on the bonded extension 20 MHz channel 11698 * (if the rx bandwidth was >= 40 MHz) 11699 * Value: RSSI dB units w.r.t. noise floor 11700 * - RSSI0_EXT40 11701 * Bits 7:0 11702 * Purpose: RSSI from chain 0 on the bonded extension 40 MHz channel 11703 * (if the rx bandwidth was >= 80 MHz) 11704 * Value: RSSI dB units w.r.t. noise floor 11705 * - RSSI0_EXT80 11706 * Bits 7:0 11707 * Purpose: RSSI from chain 0 on the bonded extension 80 MHz channel 11708 * (if the rx bandwidth was >= 160 MHz) 11709 * Value: RSSI dB units w.r.t. noise floor 11710 * 11711 * - RSSI1_PRI20 11712 * Bits 7:0 11713 * Purpose: RSSI from chain 1 on the primary 20 MHz channel 11714 * Value: RSSI dB units w.r.t. noise floor 11715 * - RSSI1_EXT20 11716 * Bits 7:0 11717 * Purpose: RSSI from chain 1 on the bonded extension 20 MHz channel 11718 * (if the rx bandwidth was >= 40 MHz) 11719 * Value: RSSI dB units w.r.t. noise floor 11720 * - RSSI1_EXT40 11721 * Bits 7:0 11722 * Purpose: RSSI from chain 1 on the bonded extension 40 MHz channel 11723 * (if the rx bandwidth was >= 80 MHz) 11724 * Value: RSSI dB units w.r.t. noise floor 11725 * - RSSI1_EXT80 11726 * Bits 7:0 11727 * Purpose: RSSI from chain 1 on the bonded extension 80 MHz channel 11728 * (if the rx bandwidth was >= 160 MHz) 11729 * Value: RSSI dB units w.r.t. noise floor 11730 * 11731 * - RSSI2_PRI20 11732 * Bits 7:0 11733 * Purpose: RSSI from chain 2 on the primary 20 MHz channel 11734 * Value: RSSI dB units w.r.t. noise floor 11735 * - RSSI2_EXT20 11736 * Bits 7:0 11737 * Purpose: RSSI from chain 2 on the bonded extension 20 MHz channel 11738 * (if the rx bandwidth was >= 40 MHz) 11739 * Value: RSSI dB units w.r.t. noise floor 11740 * - RSSI2_EXT40 11741 * Bits 7:0 11742 * Purpose: RSSI from chain 2 on the bonded extension 40 MHz channel 11743 * (if the rx bandwidth was >= 80 MHz) 11744 * Value: RSSI dB units w.r.t. noise floor 11745 * - RSSI2_EXT80 11746 * Bits 7:0 11747 * Purpose: RSSI from chain 2 on the bonded extension 80 MHz channel 11748 * (if the rx bandwidth was >= 160 MHz) 11749 * Value: RSSI dB units w.r.t. noise floor 11750 * 11751 * - RSSI3_PRI20 11752 * Bits 7:0 11753 * Purpose: RSSI from chain 3 on the primary 20 MHz channel 11754 * Value: RSSI dB units w.r.t. noise floor 11755 * - RSSI3_EXT20 11756 * Bits 7:0 11757 * Purpose: RSSI from chain 3 on the bonded extension 20 MHz channel 11758 * (if the rx bandwidth was >= 40 MHz) 11759 * Value: RSSI dB units w.r.t. noise floor 11760 * - RSSI3_EXT40 11761 * Bits 7:0 11762 * Purpose: RSSI from chain 3 on the bonded extension 40 MHz channel 11763 * (if the rx bandwidth was >= 80 MHz) 11764 * Value: RSSI dB units w.r.t. noise floor 11765 * - RSSI3_EXT80 11766 * Bits 7:0 11767 * Purpose: RSSI from chain 3 on the bonded extension 80 MHz channel 11768 * (if the rx bandwidth was >= 160 MHz) 11769 * Value: RSSI dB units w.r.t. noise floor 11770 * 11771 * - TSF32 11772 * Bits 31:0 11773 * Purpose: specify the time the rx PPDU was received, in TSF units 11774 * Value: 32 LSBs of the TSF 11775 * - TIMESTAMP_MICROSEC 11776 * Bits 31:0 11777 * Purpose: specify the time the rx PPDU was received, in microsecond units 11778 * Value: PPDU rx time, in microseconds 11779 * - VHT_SIG_A1 11780 * Bits 23:0 11781 * Purpose: Provide the HT-SIG (initial 24 bits) or VHT-SIG-A1 field 11782 * from the rx PPDU 11783 * Value: 11784 * If PREAMBLE_TYPE specifies VHT, then this field contains the 11785 * VHT-SIG-A1 data. 11786 * If PREAMBLE_TYPE specifies HT, then this field contains the 11787 * first 24 bits of the HT-SIG data. 11788 * Otherwise, this field is invalid. 11789 * Refer to the the 802.11 protocol for the definition of the 11790 * HT-SIG and VHT-SIG-A1 fields 11791 * - VHT_SIG_A2 11792 * Bits 23:0 11793 * Purpose: Provide the HT-SIG (final 24 bits) or VHT-SIG-A2 field 11794 * from the rx PPDU 11795 * Value: 11796 * If PREAMBLE_TYPE specifies VHT, then this field contains the 11797 * VHT-SIG-A2 data. 11798 * If PREAMBLE_TYPE specifies HT, then this field contains the 11799 * last 24 bits of the HT-SIG data. 11800 * Otherwise, this field is invalid. 11801 * Refer to the the 802.11 protocol for the definition of the 11802 * HT-SIG and VHT-SIG-A2 fields 11803 * - PREAMBLE_TYPE 11804 * Bits 31:24 11805 * Purpose: indicate the PHY format of the received burst 11806 * Value: 11807 * 0x4: Legacy (OFDM/CCK) 11808 * 0x8: HT 11809 * 0x9: HT with TxBF 11810 * 0xC: VHT 11811 * 0xD: VHT with TxBF 11812 * - SERVICE 11813 * Bits 31:24 11814 * Purpose: TBD 11815 * Value: TBD 11816 * 11817 * Rx MSDU descriptor fields: 11818 * - FW_RX_DESC_BYTES 11819 * Bits 15:0 11820 * Purpose: Indicate how many bytes in the Rx indication are used for 11821 * FW Rx descriptors 11822 * 11823 * Payload fields: 11824 * - MPDU_COUNT 11825 * Bits 7:0 11826 * Purpose: Indicate how many sequential MPDUs share the same status. 11827 * All MPDUs within the indicated list are from the same RA-TA-TID. 11828 * - MPDU_STATUS 11829 * Bits 15:8 11830 * Purpose: Indicate whether the (group of sequential) MPDU(s) were 11831 * received successfully. 11832 * Value: 11833 * 0x1: success 11834 * 0x2: FCS error 11835 * 0x3: duplicate error 11836 * 0x4: replay error 11837 * 0x5: invalid peer 11838 */ 11839 /* header fields */ 11840 #define HTT_RX_IND_EXT_TID_M 0x1f00 11841 #define HTT_RX_IND_EXT_TID_S 8 11842 #define HTT_RX_IND_FLUSH_VALID_M 0x2000 11843 #define HTT_RX_IND_FLUSH_VALID_S 13 11844 #define HTT_RX_IND_REL_VALID_M 0x4000 11845 #define HTT_RX_IND_REL_VALID_S 14 11846 #define HTT_RX_IND_PEER_ID_M 0xffff0000 11847 #define HTT_RX_IND_PEER_ID_S 16 11848 11849 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_M 0x3f 11850 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_S 0 11851 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_M 0xfc0 11852 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_S 6 11853 #define HTT_RX_IND_REL_SEQ_NUM_START_M 0x3f000 11854 #define HTT_RX_IND_REL_SEQ_NUM_START_S 12 11855 #define HTT_RX_IND_REL_SEQ_NUM_END_M 0xfc0000 11856 #define HTT_RX_IND_REL_SEQ_NUM_END_S 18 11857 #define HTT_RX_IND_NUM_MPDU_RANGES_M 0xff000000 11858 #define HTT_RX_IND_NUM_MPDU_RANGES_S 24 11859 11860 /* rx PPDU descriptor fields */ 11861 #define HTT_RX_IND_RSSI_CMB_M 0x000000ff 11862 #define HTT_RX_IND_RSSI_CMB_S 0 11863 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M 0x0000ff00 11864 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S 8 11865 #define HTT_RX_IND_PHY_ERR_CODE_M 0x00ff0000 11866 #define HTT_RX_IND_PHY_ERR_CODE_S 16 11867 #define HTT_RX_IND_PHY_ERR_M 0x01000000 11868 #define HTT_RX_IND_PHY_ERR_S 24 11869 #define HTT_RX_IND_LEGACY_RATE_M 0x1e000000 11870 #define HTT_RX_IND_LEGACY_RATE_S 25 11871 #define HTT_RX_IND_LEGACY_RATE_SEL_M 0x20000000 11872 #define HTT_RX_IND_LEGACY_RATE_SEL_S 29 11873 #define HTT_RX_IND_END_VALID_M 0x40000000 11874 #define HTT_RX_IND_END_VALID_S 30 11875 #define HTT_RX_IND_START_VALID_M 0x80000000 11876 #define HTT_RX_IND_START_VALID_S 31 11877 11878 #define HTT_RX_IND_RSSI_PRI20_M 0x000000ff 11879 #define HTT_RX_IND_RSSI_PRI20_S 0 11880 #define HTT_RX_IND_RSSI_EXT20_M 0x0000ff00 11881 #define HTT_RX_IND_RSSI_EXT20_S 8 11882 #define HTT_RX_IND_RSSI_EXT40_M 0x00ff0000 11883 #define HTT_RX_IND_RSSI_EXT40_S 16 11884 #define HTT_RX_IND_RSSI_EXT80_M 0xff000000 11885 #define HTT_RX_IND_RSSI_EXT80_S 24 11886 11887 #define HTT_RX_IND_VHT_SIG_A1_M 0x00ffffff 11888 #define HTT_RX_IND_VHT_SIG_A1_S 0 11889 #define HTT_RX_IND_VHT_SIG_A2_M 0x00ffffff 11890 #define HTT_RX_IND_VHT_SIG_A2_S 0 11891 #define HTT_RX_IND_PREAMBLE_TYPE_M 0xff000000 11892 #define HTT_RX_IND_PREAMBLE_TYPE_S 24 11893 #define HTT_RX_IND_SERVICE_M 0xff000000 11894 #define HTT_RX_IND_SERVICE_S 24 11895 #define HTT_RX_IND_SA_ANT_MATRIX_M 0xff000000 11896 #define HTT_RX_IND_SA_ANT_MATRIX_S 24 11897 11898 /* rx MSDU descriptor fields */ 11899 #define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff 11900 #define HTT_RX_IND_FW_RX_DESC_BYTES_S 0 11901 11902 /* payload fields */ 11903 #define HTT_RX_IND_MPDU_COUNT_M 0xff 11904 #define HTT_RX_IND_MPDU_COUNT_S 0 11905 #define HTT_RX_IND_MPDU_STATUS_M 0xff00 11906 #define HTT_RX_IND_MPDU_STATUS_S 8 11907 11908 11909 #define HTT_RX_IND_EXT_TID_SET(word, value) \ 11910 do { \ 11911 HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ 11912 (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ 11913 } while (0) 11914 #define HTT_RX_IND_EXT_TID_GET(word) \ 11915 (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) 11916 11917 #define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ 11918 do { \ 11919 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ 11920 (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ 11921 } while (0) 11922 #define HTT_RX_IND_FLUSH_VALID_GET(word) \ 11923 (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) 11924 11925 #define HTT_RX_IND_REL_VALID_SET(word, value) \ 11926 do { \ 11927 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ 11928 (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ 11929 } while (0) 11930 #define HTT_RX_IND_REL_VALID_GET(word) \ 11931 (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) 11932 11933 #define HTT_RX_IND_PEER_ID_SET(word, value) \ 11934 do { \ 11935 HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ 11936 (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ 11937 } while (0) 11938 #define HTT_RX_IND_PEER_ID_GET(word) \ 11939 (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) 11940 11941 11942 #define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ 11943 do { \ 11944 HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ 11945 (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ 11946 } while (0) 11947 #define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ 11948 (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> HTT_RX_IND_FW_RX_DESC_BYTES_S) 11949 11950 11951 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ 11952 do { \ 11953 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ 11954 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ 11955 } while (0) 11956 #define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ 11957 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ 11958 HTT_RX_IND_FLUSH_SEQ_NUM_START_S) 11959 11960 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ 11961 do { \ 11962 HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ 11963 (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ 11964 } while (0) 11965 #define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ 11966 (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ 11967 HTT_RX_IND_FLUSH_SEQ_NUM_END_S) 11968 11969 #define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ 11970 do { \ 11971 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ 11972 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ 11973 } while (0) 11974 #define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ 11975 (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ 11976 HTT_RX_IND_REL_SEQ_NUM_START_S) 11977 11978 #define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ 11979 do { \ 11980 HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ 11981 (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ 11982 } while (0) 11983 #define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ 11984 (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ 11985 HTT_RX_IND_REL_SEQ_NUM_END_S) 11986 11987 #define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ 11988 do { \ 11989 HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ 11990 (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ 11991 } while (0) 11992 #define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ 11993 (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ 11994 HTT_RX_IND_NUM_MPDU_RANGES_S) 11995 11996 /* FW rx PPDU descriptor fields */ 11997 #define HTT_RX_IND_RSSI_CMB_SET(word, value) \ 11998 do { \ 11999 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ 12000 (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ 12001 } while (0) 12002 #define HTT_RX_IND_RSSI_CMB_GET(word) \ 12003 (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ 12004 HTT_RX_IND_RSSI_CMB_S) 12005 12006 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ 12007 do { \ 12008 HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ 12009 (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ 12010 } while (0) 12011 #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ 12012 (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ 12013 HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) 12014 12015 #define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ 12016 do { \ 12017 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ 12018 (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ 12019 } while (0) 12020 #define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ 12021 (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ 12022 HTT_RX_IND_PHY_ERR_CODE_S) 12023 12024 #define HTT_RX_IND_PHY_ERR_SET(word, value) \ 12025 do { \ 12026 HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ 12027 (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ 12028 } while (0) 12029 #define HTT_RX_IND_PHY_ERR_GET(word) \ 12030 (((word) & HTT_RX_IND_PHY_ERR_M) >> \ 12031 HTT_RX_IND_PHY_ERR_S) 12032 12033 #define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ 12034 do { \ 12035 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ 12036 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ 12037 } while (0) 12038 #define HTT_RX_IND_LEGACY_RATE_GET(word) \ 12039 (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ 12040 HTT_RX_IND_LEGACY_RATE_S) 12041 12042 #define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ 12043 do { \ 12044 HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ 12045 (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ 12046 } while (0) 12047 #define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ 12048 (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ 12049 HTT_RX_IND_LEGACY_RATE_SEL_S) 12050 12051 #define HTT_RX_IND_END_VALID_SET(word, value) \ 12052 do { \ 12053 HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ 12054 (word) |= (value) << HTT_RX_IND_END_VALID_S; \ 12055 } while (0) 12056 #define HTT_RX_IND_END_VALID_GET(word) \ 12057 (((word) & HTT_RX_IND_END_VALID_M) >> \ 12058 HTT_RX_IND_END_VALID_S) 12059 12060 #define HTT_RX_IND_START_VALID_SET(word, value) \ 12061 do { \ 12062 HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ 12063 (word) |= (value) << HTT_RX_IND_START_VALID_S; \ 12064 } while (0) 12065 #define HTT_RX_IND_START_VALID_GET(word) \ 12066 (((word) & HTT_RX_IND_START_VALID_M) >> \ 12067 HTT_RX_IND_START_VALID_S) 12068 12069 #define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ 12070 do { \ 12071 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ 12072 (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ 12073 } while (0) 12074 #define HTT_RX_IND_RSSI_PRI20_GET(word) \ 12075 (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ 12076 HTT_RX_IND_RSSI_PRI20_S) 12077 12078 #define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ 12079 do { \ 12080 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ 12081 (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ 12082 } while (0) 12083 #define HTT_RX_IND_RSSI_EXT20_GET(word) \ 12084 (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ 12085 HTT_RX_IND_RSSI_EXT20_S) 12086 12087 #define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ 12088 do { \ 12089 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ 12090 (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ 12091 } while (0) 12092 #define HTT_RX_IND_RSSI_EXT40_GET(word) \ 12093 (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ 12094 HTT_RX_IND_RSSI_EXT40_S) 12095 12096 #define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ 12097 do { \ 12098 HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ 12099 (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ 12100 } while (0) 12101 #define HTT_RX_IND_RSSI_EXT80_GET(word) \ 12102 (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ 12103 HTT_RX_IND_RSSI_EXT80_S) 12104 12105 #define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ 12106 do { \ 12107 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ 12108 (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ 12109 } while (0) 12110 #define HTT_RX_IND_VHT_SIG_A1_GET(word) \ 12111 (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ 12112 HTT_RX_IND_VHT_SIG_A1_S) 12113 12114 #define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ 12115 do { \ 12116 HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ 12117 (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ 12118 } while (0) 12119 #define HTT_RX_IND_VHT_SIG_A2_GET(word) \ 12120 (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ 12121 HTT_RX_IND_VHT_SIG_A2_S) 12122 12123 #define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ 12124 do { \ 12125 HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ 12126 (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ 12127 } while (0) 12128 #define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ 12129 (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ 12130 HTT_RX_IND_PREAMBLE_TYPE_S) 12131 12132 #define HTT_RX_IND_SERVICE_SET(word, value) \ 12133 do { \ 12134 HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ 12135 (word) |= (value) << HTT_RX_IND_SERVICE_S; \ 12136 } while (0) 12137 #define HTT_RX_IND_SERVICE_GET(word) \ 12138 (((word) & HTT_RX_IND_SERVICE_M) >> \ 12139 HTT_RX_IND_SERVICE_S) 12140 12141 #define HTT_RX_IND_SA_ANT_MATRIX_SET(word, value) \ 12142 do { \ 12143 HTT_CHECK_SET_VAL(HTT_RX_IND_SA_ANT_MATRIX, value); \ 12144 (word) |= (value) << HTT_RX_IND_SA_ANT_MATRIX_S; \ 12145 } while (0) 12146 #define HTT_RX_IND_SA_ANT_MATRIX_GET(word) \ 12147 (((word) & HTT_RX_IND_SA_ANT_MATRIX_M) >> \ 12148 HTT_RX_IND_SA_ANT_MATRIX_S) 12149 12150 #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \ 12151 do { \ 12152 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ 12153 (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ 12154 } while (0) 12155 #define HTT_RX_IND_MPDU_COUNT_GET(word) \ 12156 (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) 12157 12158 #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \ 12159 do { \ 12160 HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ 12161 (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ 12162 } while (0) 12163 #define HTT_RX_IND_MPDU_STATUS_GET(word) \ 12164 (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) 12165 12166 12167 #define HTT_RX_IND_HL_BYTES \ 12168 (HTT_RX_IND_HDR_BYTES + \ 12169 4 /* single FW rx MSDU descriptor */ + \ 12170 4 /* single MPDU range information element */) 12171 #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2) 12172 12173 /* Could we use one macro entry? */ 12174 #define HTT_WORD_SET(word, field, value) \ 12175 do { \ 12176 HTT_CHECK_SET_VAL(field, value); \ 12177 (word) |= ((value) << field ## _S); \ 12178 } while (0) 12179 #define HTT_WORD_GET(word, field) \ 12180 (((word) & field ## _M) >> field ## _S) 12181 12182 PREPACK struct hl_htt_rx_ind_base { 12183 A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; /* align with LL case rx indication message, but reduced to 5 words */ 12184 } POSTPACK; 12185 12186 /* 12187 * HTT_RX_IND_HL_RX_DESC_BASE_OFFSET 12188 * Currently, we use a resv field in hl_htt_rx_ind_base to store some 12189 * HL host needed info; refer to fw_rx_desc_base in wal_rx_desc.h. 12190 * The field is just after the MSDU FW rx desc, and 1 byte ahead of 12191 * htt_rx_ind_hl_rx_desc_t. 12192 */ 12193 #define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) 12194 struct htt_rx_ind_hl_rx_desc_t { 12195 A_UINT8 ver; 12196 A_UINT8 len; 12197 struct { 12198 A_UINT8 12199 first_msdu: 1, 12200 last_msdu: 1, 12201 c3_failed: 1, 12202 c4_failed: 1, 12203 ipv6: 1, 12204 tcp: 1, 12205 udp: 1, 12206 reserved: 1; 12207 } flags; 12208 /* NOTE: no reserved space - don't append any new fields here */ 12209 }; 12210 12211 #define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ 12212 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12213 + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) 12214 #define HTT_RX_IND_HL_RX_DESC_VER 0 12215 12216 #define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ 12217 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12218 + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) 12219 12220 #define HTT_RX_IND_HL_FLAG_OFFSET \ 12221 (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ 12222 + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) 12223 12224 #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0) 12225 #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1) 12226 #define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ 12227 #define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ 12228 #define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or else ipv4 */ 12229 #define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ 12230 #define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ 12231 /* This structure is used in HL, the basic descriptor information 12232 * used by host. the structure is translated by FW from HW desc 12233 * or generated by FW. But in HL monitor mode, the host would use 12234 * the same structure with LL. 12235 */ 12236 PREPACK struct hl_htt_rx_desc_base { 12237 A_UINT32 12238 seq_num:12, 12239 encrypted:1, 12240 chan_info_present:1, 12241 resv0:2, 12242 mcast_bcast:1, 12243 fragment:1, 12244 key_id_oct:8, 12245 resv1:6; 12246 A_UINT32 12247 pn_31_0; 12248 union { 12249 struct { 12250 A_UINT16 pn_47_32; 12251 A_UINT16 pn_63_48; 12252 } pn16; 12253 A_UINT32 pn_63_32; 12254 } u0; 12255 A_UINT32 12256 pn_95_64; 12257 A_UINT32 12258 pn_127_96; 12259 } POSTPACK; 12260 12261 12262 /* 12263 * Channel information can optionally be appended after hl_htt_rx_desc_base. 12264 * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly, 12265 * and the chan_info_present flag in hl_htt_rx_desc_base will be set. 12266 * Please see htt_chan_change_t for description of the fields. 12267 */ 12268 PREPACK struct htt_chan_info_t 12269 { 12270 A_UINT32 primary_chan_center_freq_mhz: 16, 12271 contig_chan1_center_freq_mhz: 16; 12272 A_UINT32 contig_chan2_center_freq_mhz: 16, 12273 phy_mode: 8, 12274 reserved: 8; 12275 } POSTPACK; 12276 12277 #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t) 12278 12279 #define HL_RX_DESC_SIZE (sizeof(struct hl_htt_rx_desc_base)) 12280 #define HL_RX_DESC_SIZE_DWORD (HL_RX_STD_DESC_SIZE >> 2) 12281 12282 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_M 0xfff 12283 #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_S 0 12284 #define HTT_HL_RX_DESC_MPDU_ENC_M 0x1000 12285 #define HTT_HL_RX_DESC_MPDU_ENC_S 12 12286 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_M 0x2000 12287 #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_S 13 12288 #define HTT_HL_RX_DESC_MCAST_BCAST_M 0x10000 12289 #define HTT_HL_RX_DESC_MCAST_BCAST_S 16 12290 #define HTT_HL_RX_DESC_FRAGMENT_M 0x20000 12291 #define HTT_HL_RX_DESC_FRAGMENT_S 17 12292 #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000 12293 #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18 12294 12295 #define HTT_HL_RX_DESC_PN_OFFSET offsetof(struct hl_htt_rx_desc_base, pn_31_0) 12296 #define HTT_HL_RX_DESC_PN_WORD_OFFSET (HTT_HL_RX_DESC_PN_OFFSET >> 2) 12297 12298 12299 /* Channel information */ 12300 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff 12301 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S 0 12302 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M 0xffff0000 12303 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S 16 12304 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M 0x0000ffff 12305 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S 0 12306 #define HTT_CHAN_INFO_PHY_MODE_M 0x00ff0000 12307 #define HTT_CHAN_INFO_PHY_MODE_S 16 12308 12309 12310 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ 12311 do { \ 12312 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ 12313 (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ 12314 } while (0) 12315 #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ 12316 (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) 12317 12318 12319 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ 12320 do { \ 12321 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ 12322 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ 12323 } while (0) 12324 #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ 12325 (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) 12326 12327 12328 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ 12329 do { \ 12330 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ 12331 (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ 12332 } while (0) 12333 #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ 12334 (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) 12335 12336 12337 #define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ 12338 do { \ 12339 HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ 12340 (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ 12341 } while (0) 12342 #define HTT_CHAN_INFO_PHY_MODE_GET(word) \ 12343 (((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S) 12344 12345 /* 12346 * @brief target -> host message definition for FW offloaded pkts 12347 * 12348 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND 12349 * 12350 * @details 12351 * The following field definitions describe the format of the firmware 12352 * offload deliver message sent from the target to the host. 12353 * 12354 * definition for struct htt_tx_offload_deliver_ind_hdr_t 12355 * 12356 * |31 20|19 16|15 13|12 8|7 5|4|3|2 0| 12357 * |----------------------------+--------+-----+---------------+-----+-+-+----| 12358 * | reserved_1 | msg type | 12359 * |--------------------------------------------------------------------------| 12360 * | phy_timestamp_l32 | 12361 * |--------------------------------------------------------------------------| 12362 * | WORD2 (see below) | 12363 * |--------------------------------------------------------------------------| 12364 * | seqno | framectrl | 12365 * |--------------------------------------------------------------------------| 12366 * | reserved_3 | vdev_id | tid_num| 12367 * |--------------------------------------------------------------------------| 12368 * | reserved_4 | tx_mpdu_bytes |F|STAT| 12369 * |--------------------------------------------------------------------------| 12370 * 12371 * where: 12372 * STAT = status 12373 * F = format (802.3 vs. 802.11) 12374 * 12375 * definition for word 2 12376 * 12377 * |31 26|25| 24 |23 | 22 |21 19|18 17|16 9|8 6|5 2|1 0| 12378 * |--------+--+----+---+----+-----+-----+---------------------+----+-----+---| 12379 * |reserv_2|BF|LDPC|SGI|STBC| BW | NSS | RSSI |RATE| MCS |PR | 12380 * |--------------------------------------------------------------------------| 12381 * 12382 * where: 12383 * PR = preamble 12384 * BF = beamformed 12385 */ 12386 12387 PREPACK struct htt_tx_offload_deliver_ind_hdr_t 12388 { 12389 A_UINT32 /* word 0 */ 12390 msg_type:8, /* [ 7: 0] */ 12391 reserved_1:24; /* [31: 8] */ 12392 A_UINT32 phy_timestamp_l32; /* word 1 [31:0] */ 12393 A_UINT32 /* word 2 */ 12394 /* preamble: 12395 * 0-OFDM, 12396 * 1-CCk, 12397 * 2-HT, 12398 * 3-VHT 12399 */ 12400 preamble: 2, /* [1:0] */ 12401 /* mcs: 12402 * In case of HT preamble interpret 12403 * MCS along with NSS. 12404 * Valid values for HT are 0 to 7. 12405 * HT mcs 0 with NSS 2 is mcs 8. 12406 * Valid values for VHT are 0 to 9. 12407 */ 12408 mcs: 4, /* [5:2] */ 12409 /* rate: 12410 * This is applicable only for 12411 * CCK and OFDM preamble type 12412 * rate 0: OFDM 48 Mbps, 12413 * 1: OFDM 24 Mbps, 12414 * 2: OFDM 12 Mbps 12415 * 3: OFDM 6 Mbps 12416 * 4: OFDM 54 Mbps 12417 * 5: OFDM 36 Mbps 12418 * 6: OFDM 18 Mbps 12419 * 7: OFDM 9 Mbps 12420 * rate 0: CCK 11 Mbps Long 12421 * 1: CCK 5.5 Mbps Long 12422 * 2: CCK 2 Mbps Long 12423 * 3: CCK 1 Mbps Long 12424 * 4: CCK 11 Mbps Short 12425 * 5: CCK 5.5 Mbps Short 12426 * 6: CCK 2 Mbps Short 12427 */ 12428 rate : 3, /* [ 8: 6] */ 12429 rssi : 8, /* [16: 9] units=dBm */ 12430 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 12431 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 12432 stbc : 1, /* [22] */ 12433 sgi : 1, /* [23] */ 12434 ldpc : 1, /* [24] */ 12435 beamformed: 1, /* [25] */ 12436 reserved_2: 6; /* [31:26] */ 12437 A_UINT32 /* word 3 */ 12438 framectrl:16, /* [15: 0] */ 12439 seqno:16; /* [31:16] */ 12440 A_UINT32 /* word 4 */ 12441 tid_num:5, /* [ 4: 0] actual TID number */ 12442 vdev_id:8, /* [12: 5] */ 12443 reserved_3:19; /* [31:13] */ 12444 A_UINT32 /* word 5 */ 12445 /* status: 12446 * 0: tx_ok 12447 * 1: retry 12448 * 2: drop 12449 * 3: filtered 12450 * 4: abort 12451 * 5: tid delete 12452 * 6: sw abort 12453 * 7: dropped by peer migration 12454 */ 12455 status:3, /* [2:0] */ 12456 format:1, /* [3] 0: 802.3 format, 1: 802.11 format */ 12457 tx_mpdu_bytes:16, /* [19:4] */ 12458 /* Indicates retry count of offloaded/local generated Data tx frames */ 12459 tx_retry_cnt:6, /* [25:20] */ 12460 reserved_4:6; /* [31:26] */ 12461 } POSTPACK; 12462 12463 /* FW offload deliver ind message header fields */ 12464 12465 /* DWORD one */ 12466 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M 0xffffffff 12467 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S 0 12468 12469 /* DWORD two */ 12470 #define HTT_FW_OFFLOAD_IND_PREAMBLE_M 0x00000003 12471 #define HTT_FW_OFFLOAD_IND_PREAMBLE_S 0 12472 #define HTT_FW_OFFLOAD_IND_MCS_M 0x0000003c 12473 #define HTT_FW_OFFLOAD_IND_MCS_S 2 12474 #define HTT_FW_OFFLOAD_IND_RATE_M 0x000001c0 12475 #define HTT_FW_OFFLOAD_IND_RATE_S 6 12476 #define HTT_FW_OFFLOAD_IND_RSSI_M 0x0001fe00 12477 #define HTT_FW_OFFLOAD_IND_RSSI_S 9 12478 #define HTT_FW_OFFLOAD_IND_NSS_M 0x00060000 12479 #define HTT_FW_OFFLOAD_IND_NSS_S 17 12480 #define HTT_FW_OFFLOAD_IND_BW_M 0x00380000 12481 #define HTT_FW_OFFLOAD_IND_BW_S 19 12482 #define HTT_FW_OFFLOAD_IND_STBC_M 0x00400000 12483 #define HTT_FW_OFFLOAD_IND_STBC_S 22 12484 #define HTT_FW_OFFLOAD_IND_SGI_M 0x00800000 12485 #define HTT_FW_OFFLOAD_IND_SGI_S 23 12486 #define HTT_FW_OFFLOAD_IND_LDPC_M 0x01000000 12487 #define HTT_FW_OFFLOAD_IND_LDPC_S 24 12488 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_M 0x02000000 12489 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_S 25 12490 12491 /* DWORD three*/ 12492 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_M 0x0000ffff 12493 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_S 0 12494 #define HTT_FW_OFFLOAD_IND_SEQNO_M 0xffff0000 12495 #define HTT_FW_OFFLOAD_IND_SEQNO_S 16 12496 12497 /* DWORD four */ 12498 #define HTT_FW_OFFLOAD_IND_TID_NUM_M 0x0000001f 12499 #define HTT_FW_OFFLOAD_IND_TID_NUM_S 0 12500 #define HTT_FW_OFFLOAD_IND_VDEV_ID_M 0x00001fe0 12501 #define HTT_FW_OFFLOAD_IND_VDEV_ID_S 5 12502 12503 /* DWORD five */ 12504 #define HTT_FW_OFFLOAD_IND_STATUS_M 0x00000007 12505 #define HTT_FW_OFFLOAD_IND_STATUS_S 0 12506 #define HTT_FW_OFFLOAD_IND_FORMAT_M 0x00000008 12507 #define HTT_FW_OFFLOAD_IND_FORMAT_S 3 12508 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M 0x000ffff0 12509 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S 4 12510 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M 0x03f00000 12511 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S 20 12512 12513 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_SET(word, value) \ 12514 do { \ 12515 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32, value); \ 12516 (word) |= (value) << HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S; \ 12517 } while (0) 12518 #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_GET(word) \ 12519 (((word) & HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M) >> HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S) 12520 12521 #define HTT_FW_OFFLOAD_IND_PREAMBLE_SET(word, value) \ 12522 do { \ 12523 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PREAMBLE, value); \ 12524 (word) |= (value) << HTT_FW_OFFLOAD_IND_PREAMBLE_S; \ 12525 } while (0) 12526 #define HTT_FW_OFFLOAD_IND_PREAMBLE_GET(word) \ 12527 (((word) & HTT_FW_OFFLOAD_IND_PREAMBLE_M) >> HTT_FW_OFFLOAD_IND_PREAMBLE_S) 12528 12529 #define HTT_FW_OFFLOAD_IND_MCS_SET(word, value) \ 12530 do { \ 12531 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_MCS, value); \ 12532 (word) |= (value) << HTT_FW_OFFLOAD_IND_MCS_S; \ 12533 } while (0) 12534 #define HTT_FW_OFFLOAD_IND_MCS_GET(word) \ 12535 (((word) & HTT_FW_OFFLOAD_IND_MCS_M) >> HTT_FW_OFFLOAD_IND_MCS_S) 12536 12537 #define HTT_FW_OFFLOAD_IND_RATE_SET(word, value) \ 12538 do { \ 12539 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RATE, value); \ 12540 (word) |= (value) << HTT_FW_OFFLOAD_IND_RATE_S; \ 12541 } while (0) 12542 #define HTT_FW_OFFLOAD_IND_RATE_GET(word) \ 12543 (((word) & HTT_FW_OFFLOAD_IND_RATE_M) >> HTT_FW_OFFLOAD_IND_RATE_S) 12544 12545 #define HTT_FW_OFFLOAD_IND_RSSI_SET(word, value) \ 12546 do { \ 12547 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RSSI, value); \ 12548 (word) |= (value) << HTT_FW_OFFLOAD_IND_RSSI_S; \ 12549 } while (0) 12550 #define HTT_FW_OFFLOAD_IND_RSSI_GET(word) \ 12551 (((word) & HTT_FW_OFFLOAD_IND_RSSI_M) >> HTT_FW_OFFLOAD_IND_RSSI_S) 12552 12553 12554 #define HTT_FW_OFFLOAD_IND_NSS_SET(word, value) \ 12555 do { \ 12556 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_NSS, value); \ 12557 (word) |= (value) << HTT_FW_OFFLOAD_IND_NSS_S; \ 12558 } while (0) 12559 #define HTT_FW_OFFLOAD_IND_NSS_GET(word) \ 12560 (((word) & HTT_FW_OFFLOAD_IND_NSS_M) >> HTT_FW_OFFLOAD_IND_NSS_S) 12561 12562 #define HTT_FW_OFFLOAD_IND_BW_SET(word, value) \ 12563 do { \ 12564 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BW, value); \ 12565 (word) |= (value) << HTT_FW_OFFLOAD_IND_BW_S; \ 12566 } while (0) 12567 #define HTT_FW_OFFLOAD_IND_BW_GET(word) \ 12568 (((word) & HTT_FW_OFFLOAD_IND_BW_M) >> HTT_FW_OFFLOAD_IND_BW_S) 12569 12570 12571 #define HTT_FW_OFFLOAD_IND_STBC_SET(word, value) \ 12572 do { \ 12573 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STBC, value); \ 12574 (word) |= (value) << HTT_FW_OFFLOAD_IND_STBC_S; \ 12575 } while (0) 12576 #define HTT_FW_OFFLOAD_IND_STBC_GET(word) \ 12577 (((word) & HTT_FW_OFFLOAD_IND_STBC_M) >> HTT_FW_OFFLOAD_IND_STBC_S) 12578 12579 12580 #define HTT_FW_OFFLOAD_IND_SGI_SET(word, value) \ 12581 do { \ 12582 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SGI, value); \ 12583 (word) |= (value) << HTT_FW_OFFLOAD_IND_SGI_S; \ 12584 } while (0) 12585 #define HTT_FW_OFFLOAD_IND_SGI_GET(word) \ 12586 (((word) & HTT_FW_OFFLOAD_IND_SGI_M) >> HTT_FW_OFFLOAD_IND_SGI_S) 12587 12588 #define HTT_FW_OFFLOAD_IND_LDPC_SET(word, value) \ 12589 do { \ 12590 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_LDPC, value); \ 12591 (word) |= (value) << HTT_FW_OFFLOAD_IND_LDPC_S; \ 12592 } while (0) 12593 #define HTT_FW_OFFLOAD_IND_LDPC_GET(word) \ 12594 (((word) & HTT_FW_OFFLOAD_IND_LDPC_M) >> HTT_FW_OFFLOAD_IND_LDPC_S) 12595 12596 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_SET(word, value) \ 12597 do { \ 12598 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BEAMFORMED, value); \ 12599 (word) |= (value) << HTT_FW_OFFLOAD_IND_BEAMFORMED_S; \ 12600 } while (0) 12601 #define HTT_FW_OFFLOAD_IND_BEAMFORMED_GET(word) \ 12602 (((word) & HTT_FW_OFFLOAD_IND_BEAMFORMED_M) >> HTT_FW_OFFLOAD_IND_BEAMFORMED_S) 12603 12604 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_SET(word, value) \ 12605 do { \ 12606 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FRAMECTRL, value); \ 12607 (word) |= (value) << HTT_FW_OFFLOAD_IND_FRAMECTRL_S; \ 12608 } while (0) 12609 #define HTT_FW_OFFLOAD_IND_FRAMECTRL_GET(word) \ 12610 (((word) & HTT_FW_OFFLOAD_IND_FRAMECTRL_M) >> HTT_FW_OFFLOAD_IND_FRAMECTRL_S) 12611 12612 12613 #define HTT_FW_OFFLOAD_IND_SEQNO_SET(word, value) \ 12614 do { \ 12615 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SEQNO, value); \ 12616 (word) |= (value) << HTT_FW_OFFLOAD_IND_SEQNO_S; \ 12617 } while (0) 12618 #define HTT_FW_OFFLOAD_IND_SEQNO_GET(word) \ 12619 (((word) & HTT_FW_OFFLOAD_IND_SEQNO_M) >> HTT_FW_OFFLOAD_IND_SEQNO_S) 12620 12621 #define HTT_FW_OFFLOAD_IND_TID_NUM_SET(word, value) \ 12622 do { \ 12623 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TID_NUM, value); \ 12624 (word) |= (value) << HTT_FW_OFFLOAD_IND_TID_NUM_S; \ 12625 } while (0) 12626 #define HTT_FW_OFFLOAD_IND_TID_NUM_GET(word) \ 12627 (((word) & HTT_FW_OFFLOAD_IND_TID_NUM_M) >> HTT_FW_OFFLOAD_IND_TID_NUM_S) 12628 12629 #define HTT_FW_OFFLOAD_IND_VDEV_ID_SET(word, value) \ 12630 do { \ 12631 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_VDEV_ID, value); \ 12632 (word) |= (value) << HTT_FW_OFFLOAD_IND_VDEV_ID_S; \ 12633 } while (0) 12634 #define HTT_FW_OFFLOAD_IND_VDEV_ID_GET(word) \ 12635 (((word) & HTT_FW_OFFLOAD_IND_VDEV_ID_M) >> HTT_FW_OFFLOAD_IND_VDEV_ID_S) 12636 12637 #define HTT_FW_OFFLOAD_IND_STATUS_SET(word, value) \ 12638 do { \ 12639 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STATUS, value); \ 12640 (word) |= (value) << HTT_FW_OFFLOAD_IND_STATUS_S; \ 12641 } while (0) 12642 #define HTT_FW_OFFLOAD_IND_STATUS_GET(word) \ 12643 (((word) & HTT_FW_OFFLOAD_IND_STATUS_M) >> HTT_FW_OFFLOAD_IND_STATUS_M) 12644 12645 12646 #define HTT_FW_OFFLOAD_IND_FORMAT_SET(word, value) \ 12647 do { \ 12648 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FORMAT, value); \ 12649 (word) |= (value) << HTT_FW_OFFLOAD_IND_FORMAT_S; \ 12650 } while (0) 12651 #define HTT_FW_OFFLOAD_IND_FORMAT_GET(word) \ 12652 (((word) & HTT_FW_OFFLOAD_IND_FORMAT_M) >> HTT_FW_OFFLOAD_IND_FORMAT_S) 12653 12654 12655 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_SET(word, value) \ 12656 do { \ 12657 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES, value); \ 12658 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S; \ 12659 } while (0) 12660 #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_GET(word) \ 12661 (((word) & HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M) >> HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S) 12662 12663 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_SET(word, value) \ 12664 do { \ 12665 HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_RETRY_CNT, value); \ 12666 (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S; \ 12667 } while (0) 12668 #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_GET(word) \ 12669 (((word) & HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M) >> HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S) 12670 12671 12672 /* 12673 * @brief target -> host rx reorder flush message definition 12674 * 12675 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FLUSH 12676 * 12677 * @details 12678 * The following field definitions describe the format of the rx flush 12679 * message sent from the target to the host. 12680 * The message consists of a 4-octet header, followed by one or more 12681 * 4-octet payload information elements. 12682 * 12683 * |31 24|23 8|7 0| 12684 * |--------------------------------------------------------------| 12685 * | TID | peer ID | msg type | 12686 * |--------------------------------------------------------------| 12687 * | seq num end | seq num start | MPDU status | reserved | 12688 * |--------------------------------------------------------------| 12689 * First DWORD: 12690 * - MSG_TYPE 12691 * Bits 7:0 12692 * Purpose: identifies this as an rx flush message 12693 * Value: 0x2 (HTT_T2H_MSG_TYPE_RX_FLUSH) 12694 * - PEER_ID 12695 * Bits 23:8 (only bits 18:8 actually used) 12696 * Purpose: identify which peer's rx data is being flushed 12697 * Value: (rx) peer ID 12698 * - TID 12699 * Bits 31:24 (only bits 27:24 actually used) 12700 * Purpose: Specifies which traffic identifier's rx data is being flushed 12701 * Value: traffic identifier 12702 * Second DWORD: 12703 * - MPDU_STATUS 12704 * Bits 15:8 12705 * Purpose: 12706 * Indicate whether the flushed MPDUs should be discarded or processed. 12707 * Value: 12708 * 0x1: send the MPDUs from the rx reorder buffer to subsequent 12709 * stages of rx processing 12710 * other: discard the MPDUs 12711 * It is anticipated that flush messages will always have 12712 * MPDU status == 1, but the status flag is included for 12713 * flexibility. 12714 * - SEQ_NUM_START 12715 * Bits 23:16 12716 * Purpose: 12717 * Indicate the start of a series of consecutive MPDUs being flushed. 12718 * Not all MPDUs within this range are necessarily valid - the host 12719 * must check each sequence number within this range to see if the 12720 * corresponding MPDU is actually present. 12721 * Value: 12722 * The sequence number for the first MPDU in the sequence. 12723 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12724 * - SEQ_NUM_END 12725 * Bits 30:24 12726 * Purpose: 12727 * Indicate the end of a series of consecutive MPDUs being flushed. 12728 * Value: 12729 * The sequence number one larger than the sequence number of the 12730 * last MPDU being flushed. 12731 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12732 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] inclusive 12733 * are to be released for further rx processing. 12734 * Not all MPDUs within this range are necessarily valid - the host 12735 * must check each sequence number within this range to see if the 12736 * corresponding MPDU is actually present. 12737 */ 12738 /* first DWORD */ 12739 #define HTT_RX_FLUSH_PEER_ID_M 0xffff00 12740 #define HTT_RX_FLUSH_PEER_ID_S 8 12741 #define HTT_RX_FLUSH_TID_M 0xff000000 12742 #define HTT_RX_FLUSH_TID_S 24 12743 /* second DWORD */ 12744 #define HTT_RX_FLUSH_MPDU_STATUS_M 0x0000ff00 12745 #define HTT_RX_FLUSH_MPDU_STATUS_S 8 12746 #define HTT_RX_FLUSH_SEQ_NUM_START_M 0x00ff0000 12747 #define HTT_RX_FLUSH_SEQ_NUM_START_S 16 12748 #define HTT_RX_FLUSH_SEQ_NUM_END_M 0xff000000 12749 #define HTT_RX_FLUSH_SEQ_NUM_END_S 24 12750 12751 #define HTT_RX_FLUSH_BYTES 8 12752 12753 #define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ 12754 do { \ 12755 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ 12756 (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ 12757 } while (0) 12758 #define HTT_RX_FLUSH_PEER_ID_GET(word) \ 12759 (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) 12760 12761 #define HTT_RX_FLUSH_TID_SET(word, value) \ 12762 do { \ 12763 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ 12764 (word) |= (value) << HTT_RX_FLUSH_TID_S; \ 12765 } while (0) 12766 #define HTT_RX_FLUSH_TID_GET(word) \ 12767 (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) 12768 12769 #define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ 12770 do { \ 12771 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ 12772 (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ 12773 } while (0) 12774 #define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ 12775 (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) 12776 12777 #define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ 12778 do { \ 12779 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ 12780 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ 12781 } while (0) 12782 #define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ 12783 (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> HTT_RX_FLUSH_SEQ_NUM_START_S) 12784 12785 #define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ 12786 do { \ 12787 HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ 12788 (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ 12789 } while (0) 12790 #define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ 12791 (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) 12792 12793 /* 12794 * @brief target -> host rx pn check indication message 12795 * 12796 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_PN_IND 12797 * 12798 * @details 12799 * The following field definitions describe the format of the Rx PN check 12800 * indication message sent from the target to the host. 12801 * The message consists of a 4-octet header, followed by the start and 12802 * end sequence numbers to be released, followed by the PN IEs. Each PN 12803 * IE is one octet containing the sequence number that failed the PN 12804 * check. 12805 * 12806 * |31 24|23 8|7 0| 12807 * |--------------------------------------------------------------| 12808 * | TID | peer ID | msg type | 12809 * |--------------------------------------------------------------| 12810 * | Reserved | PN IE count | seq num end | seq num start| 12811 * |--------------------------------------------------------------| 12812 * l : PN IE 2 | PN IE 1 | PN IE 0 | 12813 * |--------------------------------------------------------------| 12814 12815 * First DWORD: 12816 * - MSG_TYPE 12817 * Bits 7:0 12818 * Purpose: Identifies this as an rx pn check indication message 12819 * Value: 0x10 (HTT_T2H_MSG_TYPE_RX_PN_IND) 12820 * - PEER_ID 12821 * Bits 23:8 (only bits 18:8 actually used) 12822 * Purpose: identify which peer 12823 * Value: (rx) peer ID 12824 * - TID 12825 * Bits 31:24 (only bits 27:24 actually used) 12826 * Purpose: identify traffic identifier 12827 * Value: traffic identifier 12828 * Second DWORD: 12829 * - SEQ_NUM_START 12830 * Bits 7:0 12831 * Purpose: 12832 * Indicates the starting sequence number of the MPDU in this 12833 * series of MPDUs that went though PN check. 12834 * Value: 12835 * The sequence number for the first MPDU in the sequence. 12836 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12837 * - SEQ_NUM_END 12838 * Bits 15:8 12839 * Purpose: 12840 * Indicates the ending sequence number of the MPDU in this 12841 * series of MPDUs that went though PN check. 12842 * Value: 12843 * The sequence number one larger then the sequence number of the last 12844 * MPDU being flushed. 12845 * This sequence number is the 6 LSBs of the 802.11 sequence number. 12846 * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] have been checked 12847 * for invalid PN numbers and are ready to be released for further processing. 12848 * Not all MPDUs within this range are necessarily valid - the host 12849 * must check each sequence number within this range to see if the 12850 * corresponding MPDU is actually present. 12851 * - PN_IE_COUNT 12852 * Bits 23:16 12853 * Purpose: 12854 * Used to determine the variable number of PN information elements in this 12855 * message 12856 * 12857 * PN information elements: 12858 * - PN_IE_x- 12859 * Purpose: 12860 * Each PN information element contains the sequence number of the MPDU that 12861 * has failed the target PN check. 12862 * Value: 12863 * Contains the 6 LSBs of the 802.11 sequence number corresponding to the MPDU 12864 * that failed the PN check. 12865 */ 12866 /* first DWORD */ 12867 #define HTT_RX_PN_IND_PEER_ID_M 0xffff00 12868 #define HTT_RX_PN_IND_PEER_ID_S 8 12869 #define HTT_RX_PN_IND_TID_M 0xff000000 12870 #define HTT_RX_PN_IND_TID_S 24 12871 /* second DWORD */ 12872 #define HTT_RX_PN_IND_SEQ_NUM_START_M 0x000000ff 12873 #define HTT_RX_PN_IND_SEQ_NUM_START_S 0 12874 #define HTT_RX_PN_IND_SEQ_NUM_END_M 0x0000ff00 12875 #define HTT_RX_PN_IND_SEQ_NUM_END_S 8 12876 #define HTT_RX_PN_IND_PN_IE_CNT_M 0x00ff0000 12877 #define HTT_RX_PN_IND_PN_IE_CNT_S 16 12878 12879 #define HTT_RX_PN_IND_BYTES 8 12880 12881 #define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ 12882 do { \ 12883 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ 12884 (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ 12885 } while (0) 12886 #define HTT_RX_PN_IND_PEER_ID_GET(word) \ 12887 (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) 12888 12889 #define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ 12890 do { \ 12891 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ 12892 (word) |= (value) << HTT_RX_PN_IND_TID_S; \ 12893 } while (0) 12894 #define HTT_RX_PN_IND_EXT_TID_GET(word) \ 12895 (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) 12896 12897 #define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ 12898 do { \ 12899 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ 12900 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ 12901 } while (0) 12902 #define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ 12903 (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> HTT_RX_PN_IND_SEQ_NUM_START_S) 12904 12905 #define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ 12906 do { \ 12907 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ 12908 (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ 12909 } while (0) 12910 #define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ 12911 (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) 12912 12913 #define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ 12914 do { \ 12915 HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ 12916 (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ 12917 } while (0) 12918 #define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ 12919 (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) 12920 12921 /* 12922 * @brief target -> host rx offload deliver message for LL system 12923 * 12924 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND 12925 * 12926 * @details 12927 * In a low latency system this message is sent whenever the offload 12928 * manager flushes out the packets it has coalesced in its coalescing buffer. 12929 * The DMA of the actual packets into host memory is done before sending out 12930 * this message. This message indicates only how many MSDUs to reap. The 12931 * peer ID, vdev ID, tid and MSDU length are copied inline into the header 12932 * portion of the MSDU while DMA'ing into the host memory. Unlike the packets 12933 * DMA'd by the MAC directly into host memory these packets do not contain 12934 * the MAC descriptors in the header portion of the packet. Instead they contain 12935 * the peer ID, vdev ID, tid and MSDU length. Also when the host receives this 12936 * message, the packets are delivered directly to the NW stack without going 12937 * through the regular reorder buffering and PN checking path since it has 12938 * already been done in target. 12939 * 12940 * |31 24|23 16|15 8|7 0| 12941 * |-----------------------------------------------------------------------| 12942 * | Total MSDU count | reserved | msg type | 12943 * |-----------------------------------------------------------------------| 12944 * 12945 * @brief target -> host rx offload deliver message for HL system 12946 * 12947 * @details 12948 * In a high latency system this message is sent whenever the offload manager 12949 * flushes out the packets it has coalesced in its coalescing buffer. The 12950 * actual packets are also carried along with this message. When the host 12951 * receives this message, it is expected to deliver these packets to the NW 12952 * stack directly instead of routing them through the reorder buffering and 12953 * PN checking path since it has already been done in target. 12954 * 12955 * |31 24|23 16|15 8|7 0| 12956 * |-----------------------------------------------------------------------| 12957 * | Total MSDU count | reserved | msg type | 12958 * |-----------------------------------------------------------------------| 12959 * | peer ID | MSDU length | 12960 * |-----------------------------------------------------------------------| 12961 * | MSDU payload | FW Desc | tid | vdev ID | 12962 * |-----------------------------------------------------------------------| 12963 * | MSDU payload contd. | 12964 * |-----------------------------------------------------------------------| 12965 * | peer ID | MSDU length | 12966 * |-----------------------------------------------------------------------| 12967 * | MSDU payload | FW Desc | tid | vdev ID | 12968 * |-----------------------------------------------------------------------| 12969 * | MSDU payload contd. | 12970 * |-----------------------------------------------------------------------| 12971 * 12972 */ 12973 /* first DWORD */ 12974 #define HTT_RX_OFFLOAD_DELIVER_IND_HDR_BYTES 4 12975 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_HDR_BYTES 7 12976 12977 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M 0xffff0000 12978 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S 16 12979 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M 0x0000ffff 12980 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S 0 12981 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M 0xffff0000 12982 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S 16 12983 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M 0x000000ff 12984 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S 0 12985 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M 0x0000ff00 12986 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S 8 12987 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000 12988 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16 12989 12990 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ 12991 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) 12992 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ 12993 do { \ 12994 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ 12995 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ 12996 } while (0) 12997 12998 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ 12999 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) 13000 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ 13001 do { \ 13002 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ 13003 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ 13004 } while (0) 13005 13006 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ 13007 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) 13008 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ 13009 do { \ 13010 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ 13011 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ 13012 } while (0) 13013 13014 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ 13015 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) 13016 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ 13017 do { \ 13018 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ 13019 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ 13020 } while (0) 13021 13022 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ 13023 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) 13024 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ 13025 do { \ 13026 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ 13027 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ 13028 } while (0) 13029 13030 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ 13031 (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) 13032 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ 13033 do { \ 13034 HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ 13035 (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ 13036 } while (0) 13037 13038 /** 13039 * @brief target -> host rx peer map/unmap message definition 13040 * 13041 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP 13042 * 13043 * @details 13044 * The following diagram shows the format of the rx peer map message sent 13045 * from the target to the host. This layout assumes the target operates 13046 * as little-endian. 13047 * 13048 * This message always contains a SW peer ID. The main purpose of the 13049 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13050 * with, so that the host can use that peer ID to determine which peer 13051 * transmitted the rx frame. This SW peer ID is sometimes also used for 13052 * other purposes, such as identifying during tx completions which peer 13053 * the tx frames in question were transmitted to. 13054 * 13055 * In certain generations of chips, the peer map message also contains 13056 * a HW peer ID. This HW peer ID is used during rx --> tx frame forwarding 13057 * to identify which peer the frame needs to be forwarded to (i.e. the 13058 * peer associated with the Destination MAC Address within the packet), 13059 * and particularly which vdev needs to transmit the frame (for cases 13060 * of inter-vdev rx --> tx forwarding). The HW peer id here is the same 13061 * meaning as AST_INDEX_0. 13062 * This DA-based peer ID that is provided for certain rx frames 13063 * (the rx frames that need to be re-transmitted as tx frames) 13064 * is the ID that the HW uses for referring to the peer in question, 13065 * rather than the peer ID that the SW+FW use to refer to the peer. 13066 * 13067 * 13068 * |31 24|23 16|15 8|7 0| 13069 * |-----------------------------------------------------------------------| 13070 * | SW peer ID | VDEV ID | msg type | 13071 * |-----------------------------------------------------------------------| 13072 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13073 * |-----------------------------------------------------------------------| 13074 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13075 * |-----------------------------------------------------------------------| 13076 * 13077 * 13078 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP 13079 * 13080 * The following diagram shows the format of the rx peer unmap message sent 13081 * from the target to the host. 13082 * 13083 * |31 24|23 16|15 8|7 0| 13084 * |-----------------------------------------------------------------------| 13085 * | SW peer ID | VDEV ID | msg type | 13086 * |-----------------------------------------------------------------------| 13087 * 13088 * The following field definitions describe the format of the rx peer map 13089 * and peer unmap messages sent from the target to the host. 13090 * - MSG_TYPE 13091 * Bits 7:0 13092 * Purpose: identifies this as an rx peer map or peer unmap message 13093 * Value: peer map -> 0x3 (HTT_T2H_MSG_TYPE_PEER_MAP), 13094 * peer unmap -> 0x4 (HTT_T2H_MSG_TYPE_PEER_UNMAP) 13095 * - VDEV_ID 13096 * Bits 15:8 13097 * Purpose: Indicates which virtual device the peer is associated 13098 * with. 13099 * Value: vdev ID (used in the host to look up the vdev object) 13100 * - PEER_ID (a.k.a. SW_PEER_ID) 13101 * Bits 31:16 13102 * Purpose: The peer ID (index) that WAL is allocating (map) or 13103 * freeing (unmap) 13104 * Value: (rx) peer ID 13105 * - MAC_ADDR_L32 (peer map only) 13106 * Bits 31:0 13107 * Purpose: Identifies which peer node the peer ID is for. 13108 * Value: lower 4 bytes of peer node's MAC address 13109 * - MAC_ADDR_U16 (peer map only) 13110 * Bits 15:0 13111 * Purpose: Identifies which peer node the peer ID is for. 13112 * Value: upper 2 bytes of peer node's MAC address 13113 * - HW_PEER_ID 13114 * Bits 31:16 13115 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13116 * address, so for rx frames marked for rx --> tx forwarding, the 13117 * host can determine from the HW peer ID provided as meta-data with 13118 * the rx frame which peer the frame is supposed to be forwarded to. 13119 * Value: ID used by the MAC HW to identify the peer 13120 */ 13121 #define HTT_RX_PEER_MAP_VDEV_ID_M 0xff00 13122 #define HTT_RX_PEER_MAP_VDEV_ID_S 8 13123 #define HTT_RX_PEER_MAP_PEER_ID_M 0xffff0000 13124 #define HTT_RX_PEER_MAP_PEER_ID_S 16 13125 #define HTT_RX_PEER_MAP_SW_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M /* alias */ 13126 #define HTT_RX_PEER_MAP_SW_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S /* alias */ 13127 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 13128 #define HTT_RX_PEER_MAP_MAC_ADDR_L32_S 0 13129 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff 13130 #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0 13131 #define HTT_RX_PEER_MAP_HW_PEER_ID_M 0xffff0000 13132 #define HTT_RX_PEER_MAP_HW_PEER_ID_S 16 13133 13134 #define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ 13135 #define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ 13136 do { \ 13137 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ 13138 (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ 13139 } while (0) 13140 #define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ 13141 #define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ 13142 (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) 13143 13144 #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \ 13145 do { \ 13146 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 13147 (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ 13148 } while (0) 13149 #define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ 13150 (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) 13151 #define HTT_RX_PEER_MAP_SW_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET /* alias */ 13152 #define HTT_RX_PEER_MAP_SW_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET /* alias */ 13153 13154 #define HTT_RX_PEER_MAP_HW_PEER_ID_SET(word, value) \ 13155 do { \ 13156 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_HW_PEER_ID, value); \ 13157 (word) |= (value) << HTT_RX_PEER_MAP_HW_PEER_ID_S; \ 13158 } while (0) 13159 #define HTT_RX_PEER_MAP_HW_PEER_ID_GET(word) \ 13160 (((word) & HTT_RX_PEER_MAP_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_HW_PEER_ID_S) 13161 13162 #define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 13163 #define HTT_RX_PEER_MAP_HW_PEER_ID_OFFSET 8 /* bytes */ 13164 13165 #define HTT_RX_PEER_MAP_BYTES 12 13166 13167 13168 #define HTT_RX_PEER_UNMAP_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M 13169 #define HTT_RX_PEER_UNMAP_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S 13170 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_M HTT_RX_PEER_MAP_SW_PEER_ID_M 13171 #define HTT_RX_PEER_UNMAP_SW_PEER_ID_S HTT_RX_PEER_MAP_SW_PEER_ID_S 13172 13173 #define HTT_RX_PEER_UNMAP_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET 13174 #define HTT_RX_PEER_UNMAP_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET 13175 13176 #define HTT_RX_PEER_UNMAP_VDEV_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET 13177 #define HTT_RX_PEER_UNMAP_VDEV_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET 13178 13179 #define HTT_RX_PEER_UNMAP_BYTES 4 13180 13181 13182 /** 13183 * @brief target -> host rx peer map V2 message definition 13184 * 13185 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V2 13186 * 13187 * @details 13188 * The following diagram shows the format of the rx peer map v2 message sent 13189 * from the target to the host. This layout assumes the target operates 13190 * as little-endian. 13191 * 13192 * This message always contains a SW peer ID. The main purpose of the 13193 * SW peer ID is to tell the host what peer ID rx packets will be tagged 13194 * with, so that the host can use that peer ID to determine which peer 13195 * transmitted the rx frame. This SW peer ID is sometimes also used for 13196 * other purposes, such as identifying during tx completions which peer 13197 * the tx frames in question were transmitted to. 13198 * 13199 * The peer map v2 message also contains a HW peer ID. This HW peer ID 13200 * is used during rx --> tx frame forwarding to identify which peer the 13201 * frame needs to be forwarded to (i.e. the peer associated with the 13202 * Destination MAC Address within the packet), and particularly which vdev 13203 * needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding). 13204 * This DA-based peer ID that is provided for certain rx frames 13205 * (the rx frames that need to be re-transmitted as tx frames) 13206 * is the ID that the HW uses for referring to the peer in question, 13207 * rather than the peer ID that the SW+FW use to refer to the peer. 13208 * 13209 * The HW peer id here is the same meaning as AST_INDEX_0. 13210 * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1, 13211 * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through 13212 * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension 13213 * AST is valid. 13214 * 13215 * |31 28|27 24|23 21|20|19 17|16|15 8|7 0| 13216 * |-------------------------------------------------------------------------| 13217 * | SW peer ID | VDEV ID | msg type | 13218 * |-------------------------------------------------------------------------| 13219 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13220 * |-------------------------------------------------------------------------| 13221 * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 | 13222 * |-------------------------------------------------------------------------| 13223 * | Reserved_21_31 |OA|ASTVM|NH| AST Hash Value | 13224 * |-------------------------------------------------------------------------| 13225 * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 | 13226 * |-------------------------------------------------------------------------| 13227 * |TID valid low pri| TID valid hi pri | AST index 2 | 13228 * |-------------------------------------------------------------------------| 13229 * | LMAC/PMAC_RXPCU AST index | AST index 3 | 13230 * |-------------------------------------------------------------------------| 13231 * | Reserved_2 | 13232 * |-------------------------------------------------------------------------| 13233 * Where: 13234 * NH = Next Hop 13235 * ASTVM = AST valid mask 13236 * OA = on-chip AST valid bit 13237 * ASTFM = AST flow mask 13238 * 13239 * The following field definitions describe the format of the rx peer map v2 13240 * messages sent from the target to the host. 13241 * - MSG_TYPE 13242 * Bits 7:0 13243 * Purpose: identifies this as an rx peer map v2 message 13244 * Value: peer map v2 -> 0x1e (HTT_T2H_MSG_TYPE_PEER_MAP_V2) 13245 * - VDEV_ID 13246 * Bits 15:8 13247 * Purpose: Indicates which virtual device the peer is associated with. 13248 * Value: vdev ID (used in the host to look up the vdev object) 13249 * - SW_PEER_ID 13250 * Bits 31:16 13251 * Purpose: The peer ID (index) that WAL is allocating 13252 * Value: (rx) peer ID 13253 * - MAC_ADDR_L32 13254 * Bits 31:0 13255 * Purpose: Identifies which peer node the peer ID is for. 13256 * Value: lower 4 bytes of peer node's MAC address 13257 * - MAC_ADDR_U16 13258 * Bits 15:0 13259 * Purpose: Identifies which peer node the peer ID is for. 13260 * Value: upper 2 bytes of peer node's MAC address 13261 * - HW_PEER_ID / AST_INDEX_0 13262 * Bits 31:16 13263 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13264 * address, so for rx frames marked for rx --> tx forwarding, the 13265 * host can determine from the HW peer ID provided as meta-data with 13266 * the rx frame which peer the frame is supposed to be forwarded to. 13267 * Value: ID used by the MAC HW to identify the peer 13268 * - AST_HASH_VALUE 13269 * Bits 15:0 13270 * Purpose: Indicates AST Hash value is required for the TCL AST index 13271 * override feature. 13272 * - NEXT_HOP 13273 * Bit 16 13274 * Purpose: Bit indicates that a next_hop AST entry is used for WDS 13275 * (Wireless Distribution System). 13276 * - AST_VALID_MASK 13277 * Bits 19:17 13278 * Purpose: Indicate if the AST 1 through AST 3 are valid 13279 * - ONCHIP_AST_VALID_FLAG 13280 * Bit 20 13281 * Purpose: Indicate if the on-chip AST index field (ONCHIP_AST_IDX) 13282 * is valid. 13283 * - AST_INDEX_1 13284 * Bits 15:0 13285 * Purpose: indicate the second AST index for this peer 13286 * - AST_0_FLOW_MASK 13287 * Bits 19:16 13288 * Purpose: identify the which flow the AST 0 entry corresponds to. 13289 * - AST_1_FLOW_MASK 13290 * Bits 23:20 13291 * Purpose: identify the which flow the AST 1 entry corresponds to. 13292 * - AST_2_FLOW_MASK 13293 * Bits 27:24 13294 * Purpose: identify the which flow the AST 2 entry corresponds to. 13295 * - AST_3_FLOW_MASK 13296 * Bits 31:28 13297 * Purpose: identify the which flow the AST 3 entry corresponds to. 13298 * - AST_INDEX_2 13299 * Bits 15:0 13300 * Purpose: indicate the third AST index for this peer 13301 * - TID_VALID_HI_PRI 13302 * Bits 23:16 13303 * Purpose: identify if this peer's TIDs 0-7 support HI priority flow 13304 * - TID_VALID_LOW_PRI 13305 * Bits 31:24 13306 * Purpose: identify if this peer's TIDs 0-7 support Low priority flow 13307 * - AST_INDEX_3 13308 * Bits 15:0 13309 * Purpose: indicate the fourth AST index for this peer 13310 * - ONCHIP_AST_IDX / RESERVED 13311 * Bits 31:16 13312 * Purpose: This field is valid only when split AST feature is enabled. 13313 * The ONCHIP_AST_VALID_FLAG identifies whether this field is valid. 13314 * If valid, identifies the HW peer ID corresponding to the peer MAC 13315 * address, this ast_idx is used for LMAC modules for RXPCU. 13316 * Value: ID used by the LMAC HW to identify the peer 13317 */ 13318 #define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00 13319 #define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8 13320 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 0xffff0000 13321 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 16 13322 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 0xffffffff 13323 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 0 13324 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 0xffff 13325 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 0 13326 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_M 0xffff0000 13327 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_S 16 13328 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M 0x0000ffff 13329 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0 13330 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000 13331 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16 13332 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000 13333 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17 13334 13335 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M 0x00100000 13336 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S 20 13337 13338 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff 13339 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0 13340 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000 13341 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16 13342 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000 13343 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20 13344 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000 13345 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24 13346 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000 13347 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28 13348 13349 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff 13350 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0 13351 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000 13352 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16 13353 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000 13354 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24 13355 13356 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff 13357 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0 13358 13359 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M 0xffff0000 13360 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S 16 13361 13362 #define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \ 13363 do { \ 13364 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_VDEV_ID, value); \ 13365 (word) |= (value) << HTT_RX_PEER_MAP_V2_VDEV_ID_S; \ 13366 } while (0) 13367 #define HTT_RX_PEER_MAP_V2_VDEV_ID_GET(word) \ 13368 (((word) & HTT_RX_PEER_MAP_V2_VDEV_ID_M) >> HTT_RX_PEER_MAP_V2_VDEV_ID_S) 13369 13370 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET(word, value) \ 13371 do { \ 13372 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_SW_PEER_ID, value); \ 13373 (word) |= (value) << HTT_RX_PEER_MAP_V2_SW_PEER_ID_S; \ 13374 } while (0) 13375 #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET(word) \ 13376 (((word) & HTT_RX_PEER_MAP_V2_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_SW_PEER_ID_S) 13377 13378 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_SET(word, value) \ 13379 do { \ 13380 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_HW_PEER_ID, value); \ 13381 (word) |= (value) << HTT_RX_PEER_MAP_V2_HW_PEER_ID_S; \ 13382 } while (0) 13383 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_GET(word) \ 13384 (((word) & HTT_RX_PEER_MAP_V2_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_HW_PEER_ID_S) 13385 13386 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_SET(word, value) \ 13387 do { \ 13388 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_HASH_VALUE, value); \ 13389 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S; \ 13390 } while (0) 13391 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_GET(word) \ 13392 (((word) & HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S) 13393 13394 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_SET(word, value) \ 13395 do { \ 13396 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M, value); \ 13397 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S; \ 13398 } while (0) 13399 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_GET(word) \ 13400 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S) 13401 13402 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_SET(word, value) \ 13403 do { \ 13404 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_NEXT_HOP, value); \ 13405 (word) |= (value) << HTT_RX_PEER_MAP_V2_NEXT_HOP_S; \ 13406 } while (0) 13407 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \ 13408 (((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S) 13409 13410 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \ 13411 do { \ 13412 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \ 13413 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \ 13414 } while (0) 13415 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \ 13416 (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S) 13417 13418 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 13419 do { \ 13420 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M, value); \ 13421 (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S; \ 13422 } while (0) 13423 #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_MASK_GET(word) \ 13424 (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S) 13425 13426 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \ 13427 do { \ 13428 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \ 13429 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \ 13430 } while (0) 13431 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \ 13432 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S) 13433 13434 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \ 13435 do { \ 13436 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \ 13437 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \ 13438 } while (0) 13439 #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \ 13440 (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S) 13441 13442 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \ 13443 do { \ 13444 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \ 13445 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \ 13446 } while (0) 13447 #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \ 13448 (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S) 13449 13450 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \ 13451 do { \ 13452 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \ 13453 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \ 13454 } while (0) 13455 #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \ 13456 (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S) 13457 13458 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \ 13459 do { \ 13460 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \ 13461 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \ 13462 } while (0) 13463 #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \ 13464 (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S) 13465 13466 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \ 13467 do { \ 13468 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \ 13469 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \ 13470 } while (0) 13471 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \ 13472 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S) 13473 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \ 13474 do { \ 13475 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \ 13476 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \ 13477 } while (0) 13478 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \ 13479 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S) 13480 13481 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \ 13482 do { \ 13483 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \ 13484 (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \ 13485 } while (0) 13486 #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \ 13487 (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S) 13488 13489 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \ 13490 do { \ 13491 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \ 13492 (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \ 13493 } while (0) 13494 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \ 13495 (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S) 13496 13497 13498 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 13499 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */ 13500 #define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */ 13501 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */ 13502 #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */ 13503 #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */ 13504 #define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */ 13505 #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */ 13506 #define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */ 13507 #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */ 13508 #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */ 13509 13510 #define HTT_RX_PEER_MAP_V2_BYTES 32 13511 13512 /** 13513 * @brief target -> host rx peer map V3 message definition 13514 * 13515 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V3 13516 * 13517 * @details 13518 * The following diagram shows the format of the rx peer map v3 message sent 13519 * from the target to the host. 13520 * Format inherits HTT_T2H_MSG_TYPE_PEER_MAP_V2 published above 13521 * This layout assumes the target operates as little-endian. 13522 * 13523 * |31 24|23 20|19|18|17|16|15 8|7 0| 13524 * |-----------------+--------+--+--+--+--+-----------------+-----------------| 13525 * | SW peer ID | VDEV ID | msg type | 13526 * |-----------------+--------------------+-----------------+-----------------| 13527 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13528 * |-----------------+--------------------+-----------------+-----------------| 13529 * | Multicast SW peer ID | MAC addr 5 | MAC addr 4 | 13530 * |-----------------+--------+-----------+-----------------+-----------------| 13531 * | HTT_MSDU_IDX_ |RESERVED| CACHE_ | | 13532 * | VALID_MASK |(4bits) | SET_NUM | HW peer ID / AST index | 13533 * | (8bits) | | (4bits) | | 13534 * |-----------------+--------+--+--+--+--------------------------------------| 13535 * | RESERVED |E |O | | | 13536 * | (13bits) |A |A |NH| on-Chip PMAC_RXPCU AST index | 13537 * | |V |V | | | 13538 * |-----------------+--------------------+-----------------------------------| 13539 * | HTT_MSDU_IDX_ | RESERVED | | 13540 * | VALID_MASK_EXT | (8bits) | EXT AST index | 13541 * | (8bits) | | | 13542 * |-----------------+--------------------+-----------------------------------| 13543 * | Reserved_2 | 13544 * |--------------------------------------------------------------------------| 13545 * | Reserved_3 | 13546 * |--------------------------------------------------------------------------| 13547 * 13548 * Where: 13549 * EAV = EXT_AST_VALID flag, for "EXT AST index" 13550 * OAV = ONCHIP_AST_VALID flag, for "on-Chip PMAC_RXPCU AST index" 13551 * NH = Next Hop 13552 * The following field definitions describe the format of the rx peer map v3 13553 * messages sent from the target to the host. 13554 * - MSG_TYPE 13555 * Bits 7:0 13556 * Purpose: identifies this as a peer map v3 message 13557 * Value: 0x2b (HTT_T2H_MSG_TYPE_PEER_MAP_V3) 13558 * - VDEV_ID 13559 * Bits 15:8 13560 * Purpose: Indicates which virtual device the peer is associated with. 13561 * - SW_PEER_ID 13562 * Bits 31:16 13563 * Purpose: The peer ID (index) that WAL has allocated for this peer. 13564 * - MAC_ADDR_L32 13565 * Bits 31:0 13566 * Purpose: Identifies which peer node the peer ID is for. 13567 * Value: lower 4 bytes of peer node's MAC address 13568 * - MAC_ADDR_U16 13569 * Bits 15:0 13570 * Purpose: Identifies which peer node the peer ID is for. 13571 * Value: upper 2 bytes of peer node's MAC address 13572 * - MULTICAST_SW_PEER_ID 13573 * Bits 31:16 13574 * Purpose: The multicast peer ID (index) 13575 * Value: set to HTT_INVALID_PEER if not valid 13576 * - HW_PEER_ID / AST_INDEX 13577 * Bits 15:0 13578 * Purpose: Identifies the HW peer ID corresponding to the peer MAC 13579 * address, so for rx frames marked for rx --> tx forwarding, the 13580 * host can determine from the HW peer ID provided as meta-data with 13581 * the rx frame which peer the frame is supposed to be forwarded to. 13582 * - CACHE_SET_NUM 13583 * Bits 19:16 13584 * Purpose: Cache Set Number for AST_INDEX 13585 * Cache set number that should be used to cache the index based 13586 * search results, for address and flow search. 13587 * This value should be equal to LSB 4 bits of the hash value 13588 * of match data, in case of search index points to an entry which 13589 * may be used in content based search also. The value can be 13590 * anything when the entry pointed by search index will not be 13591 * used for content based search. 13592 * - HTT_MSDU_IDX_VALID_MASK 13593 * Bits 31:24 13594 * Purpose: Shows MSDU indexes valid mask for AST_INDEX 13595 * - ONCHIP_AST_IDX / RESERVED 13596 * Bits 15:0 13597 * Purpose: This field is valid only when split AST feature is enabled. 13598 * The ONCHIP_AST_VALID flag identifies whether this field is valid. 13599 * If valid, identifies the HW peer ID corresponding to the peer MAC 13600 * address, this ast_idx is used for LMAC modules for RXPCU. 13601 * - NEXT_HOP 13602 * Bits 16 13603 * Purpose: Flag indicates next_hop AST entry used for WDS 13604 * (Wireless Distribution System). 13605 * - ONCHIP_AST_VALID 13606 * Bits 17 13607 * Purpose: Flag indicates valid data behind of the ONCHIP_AST_IDX field 13608 * - EXT_AST_VALID 13609 * Bits 18 13610 * Purpose: Flag indicates valid data behind of the EXT_AST_INDEX field 13611 * - EXT_AST_INDEX 13612 * Bits 15:0 13613 * Purpose: This field describes Extended AST index 13614 * Valid if EXT_AST_VALID flag set 13615 * - HTT_MSDU_IDX_VALID_MASK_EXT 13616 * Bits 31:24 13617 * Purpose: Shows MSDU indexes valid mask for EXT_AST_INDEX 13618 */ 13619 /* dword 0 */ 13620 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_M 0xffff0000 13621 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_S 16 13622 #define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00 13623 #define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8 13624 /* dword 1 */ 13625 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_M 0xffffffff 13626 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_S 0 13627 /* dword 2 */ 13628 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_M 0x0000ffff 13629 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_S 0 13630 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M 0xffff0000 13631 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S 16 13632 /* dword 3 */ 13633 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M 0xff000000 13634 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S 24 13635 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000 13636 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16 13637 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff 13638 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0 13639 /* dword 4 */ 13640 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000 13641 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18 13642 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000 13643 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17 13644 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000 13645 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16 13646 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff 13647 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0 13648 /* dword 5 */ 13649 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M 0xff000000 13650 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S 24 13651 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff 13652 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0 13653 13654 #define HTT_RX_PEER_MAP_V3_VDEV_ID_SET(word, value) \ 13655 do { \ 13656 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_VDEV_ID, value); \ 13657 (word) |= (value) << HTT_RX_PEER_MAP_V3_VDEV_ID_S; \ 13658 } while (0) 13659 #define HTT_RX_PEER_MAP_V3_VDEV_ID_GET(word) \ 13660 (((word) & HTT_RX_PEER_MAP_V3_VDEV_ID_M) >> HTT_RX_PEER_MAP_V3_VDEV_ID_S) 13661 13662 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_SET(word, value) \ 13663 do { \ 13664 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_SW_PEER_ID, value); \ 13665 (word) |= (value) << HTT_RX_PEER_MAP_V3_SW_PEER_ID_S; \ 13666 } while (0) 13667 #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_GET(word) \ 13668 (((word) & HTT_RX_PEER_MAP_V3_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_SW_PEER_ID_S) 13669 13670 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_SET(word, value) \ 13671 do { \ 13672 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID, value); \ 13673 (word) |= (value) << HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S; \ 13674 } while (0) 13675 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_GET(word) \ 13676 (((word) & HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S) 13677 13678 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_SET(word, value) \ 13679 do { \ 13680 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_HW_PEER_ID, value); \ 13681 (word) |= (value) << HTT_RX_PEER_MAP_V3_HW_PEER_ID_S; \ 13682 } while (0) 13683 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_GET(word) \ 13684 (((word) & HTT_RX_PEER_MAP_V3_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_HW_PEER_ID_S) 13685 13686 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_SET(word, value) \ 13687 do { \ 13688 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CACHE_SET_NUM, value); \ 13689 (word) |= (value) << HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S; \ 13690 } while (0) 13691 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_GET(word) \ 13692 (((word) & HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M) >> HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S) 13693 13694 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_SET(word, value) \ 13695 do { \ 13696 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST, value); \ 13697 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S; \ 13698 } while (0) 13699 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_GET(word) \ 13700 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S) 13701 13702 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_SET(word, value) \ 13703 do { \ 13704 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX, value); \ 13705 (word) |= (value) << HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S; \ 13706 } while (0) 13707 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_GET(word) \ 13708 (((word) & HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S) 13709 13710 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_SET(word, value) \ 13711 do { \ 13712 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_NEXT_HOP, value); \ 13713 (word) |= (value) << HTT_RX_PEER_MAP_V3_NEXT_HOP_S; \ 13714 } while (0) 13715 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_GET(word) \ 13716 (((word) & HTT_RX_PEER_MAP_V3_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V3_NEXT_HOP_S) 13717 13718 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_SET(word, value) \ 13719 do { \ 13720 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG, value); \ 13721 (word) |= (value) << HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S; \ 13722 } while (0) 13723 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_GET(word) \ 13724 (((word) & HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S) 13725 13726 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_SET(word, value) \ 13727 do { \ 13728 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG, value); \ 13729 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S; \ 13730 } while (0) 13731 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_GET(word) \ 13732 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S) 13733 13734 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_SET(word, value) \ 13735 do { \ 13736 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_IDX, value); \ 13737 (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S; \ 13738 } while (0) 13739 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_GET(word) \ 13740 (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S) 13741 13742 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_SET(word, value) \ 13743 do { \ 13744 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST, value); \ 13745 (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S; \ 13746 } while (0) 13747 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_GET(word) \ 13748 (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S) 13749 13750 #define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */ 13751 #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */ 13752 #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */ 13753 #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */ 13754 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */ 13755 #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */ 13756 #define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */ 13757 #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */ 13758 #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */ 13759 #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */ 13760 #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */ 13761 13762 #define HTT_RX_PEER_MAP_V3_BYTES 32 13763 13764 /** 13765 * @brief target -> host rx peer unmap V2 message definition 13766 * 13767 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 13768 * 13769 * The following diagram shows the format of the rx peer unmap message sent 13770 * from the target to the host. 13771 * 13772 * |31 24|23 16|15 8|7 0| 13773 * |-----------------------------------------------------------------------| 13774 * | SW peer ID | VDEV ID | msg type | 13775 * |-----------------------------------------------------------------------| 13776 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13777 * |-----------------------------------------------------------------------| 13778 * | Reserved_17_31 | Next Hop | MAC addr 5 | MAC addr 4 | 13779 * |-----------------------------------------------------------------------| 13780 * | Peer Delete Duration | 13781 * |-----------------------------------------------------------------------| 13782 * | Reserved_0 | WDS Free Count | 13783 * |-----------------------------------------------------------------------| 13784 * | Reserved_1 | 13785 * |-----------------------------------------------------------------------| 13786 * | Reserved_2 | 13787 * |-----------------------------------------------------------------------| 13788 * 13789 * 13790 * The following field definitions describe the format of the rx peer unmap 13791 * messages sent from the target to the host. 13792 * - MSG_TYPE 13793 * Bits 7:0 13794 * Purpose: identifies this as an rx peer unmap v2 message 13795 * Value: peer unmap v2 -> 0x1f (HTT_T2H_MSG_TYPE_PEER_UNMAP_V2) 13796 * - VDEV_ID 13797 * Bits 15:8 13798 * Purpose: Indicates which virtual device the peer is associated 13799 * with. 13800 * Value: vdev ID (used in the host to look up the vdev object) 13801 * - SW_PEER_ID 13802 * Bits 31:16 13803 * Purpose: The peer ID (index) that WAL is freeing 13804 * Value: (rx) peer ID 13805 * - MAC_ADDR_L32 13806 * Bits 31:0 13807 * Purpose: Identifies which peer node the peer ID is for. 13808 * Value: lower 4 bytes of peer node's MAC address 13809 * - MAC_ADDR_U16 13810 * Bits 15:0 13811 * Purpose: Identifies which peer node the peer ID is for. 13812 * Value: upper 2 bytes of peer node's MAC address 13813 * - NEXT_HOP 13814 * Bits 16 13815 * Purpose: Bit indicates next_hop AST entry used for WDS 13816 * (Wireless Distribution System). 13817 * - PEER_DELETE_DURATION 13818 * Bits 31:0 13819 * Purpose: Time taken to delete peer, in msec, 13820 * Used for monitoring / debugging PEER delete response delay 13821 * - PEER_WDS_FREE_COUNT 13822 * Bits 15:0 13823 * Purpose: Count of WDS entries deleted associated to peer deleted 13824 */ 13825 13826 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_M HTT_RX_PEER_MAP_V2_VDEV_ID_M 13827 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_S HTT_RX_PEER_MAP_V2_VDEV_ID_S 13828 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_M HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 13829 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_S HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 13830 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_M HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 13831 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_S HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 13832 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_M HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 13833 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_S HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 13834 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_M HTT_RX_PEER_MAP_V2_NEXT_HOP_M 13835 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_S HTT_RX_PEER_MAP_V2_NEXT_HOP_S 13836 13837 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M 0xffffffff 13838 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S 0 13839 13840 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M 0x0000ffff 13841 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S 0 13842 13843 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_SET HTT_RX_PEER_MAP_V2_VDEV_ID_SET 13844 #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_GET HTT_RX_PEER_MAP_V2_VDEV_ID_GET 13845 13846 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_SET HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET 13847 #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_GET HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET 13848 13849 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_SET HTT_RX_PEER_MAP_V2_NEXT_HOP_SET 13850 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_GET HTT_RX_PEER_MAP_V2_NEXT_HOP_GET 13851 13852 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_SET(word, value) \ 13853 do { \ 13854 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION, value); \ 13855 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S; \ 13856 } while (0) 13857 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_GET(word) \ 13858 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M) >> HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S) 13859 13860 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_SET(word, value) \ 13861 do { \ 13862 HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT, value); \ 13863 (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S; \ 13864 } while (0) 13865 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_GET(word) \ 13866 (((word) & HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M) >> HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S) 13867 13868 #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_OFFSET 4 /* bytes */ 13869 #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_OFFSET 8 /* bytes */ 13870 #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_OFFSET 12 /* bytes */ 13871 #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_OFFSET 16 /* bytes */ 13872 13873 #define HTT_RX_PEER_UNMAP_V2_BYTES 28 13874 13875 /** 13876 * @brief target -> host rx peer mlo map message definition 13877 * 13878 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP 13879 * 13880 * @details 13881 * The following diagram shows the format of the rx mlo peer map message sent 13882 * from the target to the host. This layout assumes the target operates 13883 * as little-endian. 13884 * 13885 * MCC: 13886 * One HTT_MLO_PEER_MAP is sent after PEER_ASSOC received on first LINK for both STA and SAP. 13887 * 13888 * WIN: 13889 * One HTT_MLO_PEER_MAP is sent after peers are created on all the links for both AP and STA. 13890 * It will be sent on the Assoc Link. 13891 * 13892 * This message always contains a MLO peer ID. The main purpose of the 13893 * MLO peer ID is to tell the host what peer ID rx packets will be tagged 13894 * with, so that the host can use that MLO peer ID to determine which peer 13895 * transmitted the rx frame. 13896 * 13897 * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0| 13898 * |-------------------------------------------------------------------------| 13899 * |RSVD | PRC |NUMLINK| MLO peer ID | msg type | 13900 * |-------------------------------------------------------------------------| 13901 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 13902 * |-------------------------------------------------------------------------| 13903 * | RSVD_16_31 | MAC addr 5 | MAC addr 4 | 13904 * |-------------------------------------------------------------------------| 13905 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | 13906 * |-------------------------------------------------------------------------| 13907 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | 13908 * |-------------------------------------------------------------------------| 13909 * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | 13910 * |-------------------------------------------------------------------------| 13911 * |RSVD | 13912 * |-------------------------------------------------------------------------| 13913 * |RSVD | 13914 * |-------------------------------------------------------------------------| 13915 * | htt_tlv_hdr_t | 13916 * |-------------------------------------------------------------------------| 13917 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13918 * |-------------------------------------------------------------------------| 13919 * | htt_tlv_hdr_t | 13920 * |-------------------------------------------------------------------------| 13921 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13922 * |-------------------------------------------------------------------------| 13923 * | htt_tlv_hdr_t | 13924 * |-------------------------------------------------------------------------| 13925 * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | 13926 * |-------------------------------------------------------------------------| 13927 * 13928 * Where: 13929 * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26 13930 * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29 13931 * V (valid) - 1 Bit Bit17 13932 * CHIPID - 3 Bits 13933 * TIDMASK - 8 Bits 13934 * CACHE_SET_NUM - 8 Bits 13935 * 13936 * The following field definitions describe the format of the rx MLO peer map 13937 * messages sent from the target to the host. 13938 * - MSG_TYPE 13939 * Bits 7:0 13940 * Purpose: identifies this as an rx mlo peer map message 13941 * Value: 0x29 (HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP) 13942 * 13943 * - MLO_PEER_ID 13944 * Bits 23:8 13945 * Purpose: The MLO peer ID (index). 13946 * For MCC, FW will allocate it. For WIN, Host will allocate it. 13947 * Value: MLO peer ID 13948 * 13949 * - NUMLINK 13950 * Bits: 26:24 (3Bits) 13951 * Purpose: Indicate the max number of logical links supported per client. 13952 * Value: number of logical links 13953 * 13954 * - PRC 13955 * Bits: 29:27 (3Bits) 13956 * Purpose: Indicate the Primary REO CHIPID. The ID can be used to indicate 13957 * if there is migration of the primary chip. 13958 * Value: Primary REO CHIPID 13959 * 13960 * - MAC_ADDR_L32 13961 * Bits 31:0 13962 * Purpose: Identifies which mlo peer node the mlo peer ID is for. 13963 * Value: lower 4 bytes of peer node's MAC address 13964 * 13965 * - MAC_ADDR_U16 13966 * Bits 15:0 13967 * Purpose: Identifies which peer node the peer ID is for. 13968 * Value: upper 2 bytes of peer node's MAC address 13969 * 13970 * - PRIMARY_TCL_AST_IDX 13971 * Bits 15:0 13972 * Purpose: Primary TCL AST index for this peer. 13973 * 13974 * - V 13975 * 1 Bit Position 16 13976 * Purpose: If the ast idx is valid. 13977 * 13978 * - CHIPID 13979 * Bits 19:17 13980 * Purpose: Identifies which chip id of PRIMARY_TCL_AST_IDX 13981 * 13982 * - TIDMASK 13983 * Bits 27:20 13984 * Purpose: LINK to TID mapping for PRIMARY_TCL_AST_IDX 13985 * 13986 * - CACHE_SET_NUM 13987 * Bits 31:28 13988 * Purpose: Cache Set Number for PRIMARY_TCL_AST_IDX 13989 * Cache set number that should be used to cache the index based 13990 * search results, for address and flow search. 13991 * This value should be equal to LSB four bits of the hash value 13992 * of match data, in case of search index points to an entry which 13993 * may be used in content based search also. The value can be 13994 * anything when the entry pointed by search index will not be 13995 * used for content based search. 13996 * 13997 * - htt_tlv_hdr_t 13998 * Purpose: Provide link specific chip,vdev and sw_peer IDs 13999 * 14000 * Bits 11:0 14001 * Purpose: tag equal to MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS. 14002 * 14003 * Bits 23:12 14004 * Purpose: Length, Length of the value that follows the header 14005 * 14006 * Bits 31:28 14007 * Purpose: Reserved. 14008 * 14009 * 14010 * - SW_PEER_ID 14011 * Bits 15:0 14012 * Purpose: The peer ID (index) that WAL is allocating 14013 * Value: (rx) peer ID 14014 * 14015 * - VDEV_ID 14016 * Bits 23:16 14017 * Purpose: Indicates which virtual device the peer is associated with. 14018 * Value: vdev ID (used in the host to look up the vdev object) 14019 * 14020 * - CHIPID 14021 * Bits 26:24 14022 * Purpose: Indicates which Chip id the peer is associated with. 14023 * Value: chip ID (Provided by Host as part of QMI exchange) 14024 */ 14025 typedef enum { 14026 MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS, 14027 } MLO_PEER_MAP_TLV_TAG_ID; 14028 14029 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 0x00ffff00 14030 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 8 14031 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M 0x07000000 14032 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S 24 14033 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M 0x38000000 14034 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S 27 14035 14036 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_M 0xffffffff 14037 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_S 0 14038 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff 14039 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0 14040 14041 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff 14042 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0 14043 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000 14044 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S 16 14045 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M 0x000E0000 14046 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S 17 14047 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M 0x00F00000 14048 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S 20 14049 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M 0xF0000000 14050 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S 28 14051 14052 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_M 0x00000fff 14053 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_S 0 14054 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M 0x00fff000 14055 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S 12 14056 14057 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M 0x0000ffff 14058 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S 0 14059 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_M 0x00ff0000 14060 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_S 16 14061 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_M 0x07000000 14062 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_S 24 14063 14064 14065 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET(word, value) \ 14066 do { \ 14067 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_MLO_PEER_ID, value); \ 14068 (word) |= (value) << HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S; \ 14069 } while (0) 14070 #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET(word) \ 14071 (((word) & HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S) 14072 14073 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_SET(word, value) \ 14074 do { \ 14075 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS, value); \ 14076 (word) |= (value) << HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S; \ 14077 } while (0) 14078 #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_GET(word) \ 14079 (((word) & HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M) >> HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S) 14080 14081 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \ 14082 do { \ 14083 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \ 14084 (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \ 14085 } while (0) 14086 #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ 14087 (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) 14088 14089 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \ 14090 do { \ 14091 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \ 14092 (word) |= (value) << HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S; \ 14093 } while (0) 14094 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_GET(word) \ 14095 (((word) & HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S) 14096 14097 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_SET(word, value) \ 14098 do { \ 14099 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG, value); \ 14100 (word) |= (value) << HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S; \ 14101 } while (0) 14102 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_GET(word) \ 14103 (((word) & HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S) 14104 14105 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_SET(word, value) \ 14106 do { \ 14107 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX, value); \ 14108 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S; \ 14109 } while (0) 14110 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_GET(word) \ 14111 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S) 14112 14113 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_SET(word, value) \ 14114 do { \ 14115 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX, value); \ 14116 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S; \ 14117 } while (0) 14118 #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_GET(word) \ 14119 (((word) & HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S) 14120 14121 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_SET(word, value) \ 14122 do { \ 14123 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX, value); \ 14124 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S; \ 14125 } while (0) 14126 #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_GET(word) \ 14127 (((word) & HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S) 14128 14129 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_SET(word, value) \ 14130 do { \ 14131 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_TAG, value); \ 14132 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_TAG_S; \ 14133 } while (0) 14134 #define HTT_RX_MLO_PEER_MAP_TLV_TAG_GET(word) \ 14135 (((word) & HTT_RX_MLO_PEER_MAP_TLV_TAG_M) >> HTT_RX_MLO_PEER_MAP_TLV_TAG_S) 14136 14137 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_SET(word, value) \ 14138 do { \ 14139 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_LENGTH, value); \ 14140 (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S; \ 14141 } while (0) 14142 #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_GET(word) \ 14143 (((word) & HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M) >> HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S) 14144 14145 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_SET(word, value) \ 14146 do { \ 14147 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_SW_PEER_ID, value); \ 14148 (word) |= (value) << HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S; \ 14149 } while (0) 14150 #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_GET(word) \ 14151 (((word) & HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S) 14152 14153 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_SET(word, value) \ 14154 do { \ 14155 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_VDEV_ID, value); \ 14156 (word) |= (value) << HTT_RX_MLO_PEER_MAP_VDEV_ID_S; \ 14157 } while (0) 14158 #define HTT_RX_MLO_PEER_MAP_VDEV_ID_GET(word) \ 14159 (((word) & HTT_RX_MLO_PEER_MAP_VDEV_ID_M) >> HTT_RX_MLO_PEER_MAP_VDEV_ID_S) 14160 14161 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_SET(word, value) \ 14162 do { \ 14163 HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID, value); \ 14164 (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_S; \ 14165 } while (0) 14166 #define HTT_RX_MLO_PEER_MAP_CHIP_ID_GET(word) \ 14167 (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_S) 14168 14169 14170 #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ 14171 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */ 14172 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */ 14173 #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */ 14174 #define HTT_RX_MLO_PEER_MAP_TLV_OFFSET 32 /* bytes */ 14175 14176 #define HTT_RX_MLO_PEER_MAP_FIXED_BYTES 8*4 /* 8 Dwords. Does not include the TLV header and the TLV */ 14177 14178 14179 /* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP 14180 * 14181 * The following diagram shows the format of the rx mlo peer unmap message sent 14182 * from the target to the host. 14183 * 14184 * |31 24|23 16|15 8|7 0| 14185 * |-----------------------------------------------------------------------| 14186 * | RSVD_24_31 | MLO peer ID | msg type | 14187 * |-----------------------------------------------------------------------| 14188 */ 14189 14190 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_M HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 14191 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_S HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 14192 14193 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET 14194 #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET 14195 14196 /** 14197 * @brief target -> host peer extended event for additional information 14198 * 14199 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT 14200 * 14201 * @details 14202 * The following diagram shows the format of the peer extended message sent 14203 * from the target to the host. This layout assumes the target operates 14204 * as little-endian. 14205 * 14206 * This message always contains a SW peer ID. The main purpose of the 14207 * SW peer ID is to tell the host what peer ID logical link id will be tagged 14208 * with, so that the host can use that peer ID to determine which link 14209 * transmitted the rx/tx frame. 14210 * 14211 * This message also contains MLO logical link id assigned to peer 14212 * with sw_peer_id if it is valid ML link peer. 14213 * 14214 * 14215 * |31 28|27 24|23 20|19|18 16|15 8|7 0| 14216 * |---------------------------------------------------------------------------| 14217 * | VDEV_ID | SW peer ID | msg type | 14218 * |---------------------------------------------------------------------------| 14219 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 14220 * |---------------------------------------------------------------------------| 14221 * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 | 14222 * |---------------------------------------------------------------------------| 14223 * | Reserved | 14224 * |---------------------------------------------------------------------------| 14225 * | Reserved | 14226 * |---------------------------------------------------------------------------| 14227 * 14228 * Where: 14229 * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte 14230 * V (valid) - 1 Bit Bit19 of 3rd byte 14231 * 14232 * The following field definitions describe the format of the rx peer extended 14233 * event messages sent from the target to the host. 14234 * MSG_TYPE 14235 * Bits 7:0 14236 * Purpose: identifies this as an rx MLO peer extended information message 14237 * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT) 14238 * - PEER_ID (a.k.a. SW_PEER_ID) 14239 * Bits 8:23 14240 * Purpose: The peer ID (index) that WAL has allocated 14241 * Value: (rx) peer ID 14242 * - VDEV_ID 14243 * Bits 24:31 14244 * Purpose: Gives the vdev id of peer with peer_id as above. 14245 * Value: VDEV ID of wal_peer 14246 * 14247 * - MAC_ADDR_L32 14248 * Bits 31:0 14249 * Purpose: Identifies which peer node the peer ID is for. 14250 * Value: lower 4 bytes of peer node's MAC address 14251 * 14252 * - MAC_ADDR_U16 14253 * Bits 15:0 14254 * Purpose: Identifies which peer node the peer ID is for. 14255 * Value: upper 2 bytes of peer node's MAC address 14256 * Rest all bits are reserved for future expansion 14257 * - LOGICAL_LINK_ID 14258 * Bits 18:16 14259 * Purpose: Gives the logical link id of peer with peer_id as above. This 14260 * field should be taken alongwith LOGICAL_LINK_ID_VALID 14261 * Value: Logical link id used by wal_peer 14262 * - LOGICAL_LINK_ID_VALID 14263 * Bit 19 14264 * Purpose: Clarifies whether the logical link id of peer with peer_id as 14265 * is valid or not 14266 * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not 14267 */ 14268 #define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00 14269 #define HTT_RX_PEER_EXTENDED_PEER_ID_S 8 14270 #define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000 14271 #define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24 14272 14273 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff 14274 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0 14275 14276 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff 14277 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0 14278 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000 14279 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16 14280 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000 14281 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19 14282 14283 14284 #define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \ 14285 do { \ 14286 HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ 14287 (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \ 14288 } while (0) 14289 #define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \ 14290 (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S) 14291 14292 #define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \ 14293 do { \ 14294 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \ 14295 (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \ 14296 } while (0) 14297 #define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \ 14298 (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S) 14299 14300 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \ 14301 do { \ 14302 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \ 14303 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \ 14304 } while (0) 14305 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \ 14306 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S) 14307 14308 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \ 14309 do { \ 14310 HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \ 14311 (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \ 14312 } while (0) 14313 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \ 14314 (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S) 14315 14316 #define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */ 14317 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */ 14318 #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */ 14319 14320 #define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */ 14321 14322 /** 14323 * @brief target -> host message specifying security parameters 14324 * 14325 * MSG_TYPE => HTT_T2H_MSG_TYPE_SEC_IND 14326 * 14327 * @details 14328 * The following diagram shows the format of the security specification 14329 * message sent from the target to the host. 14330 * This security specification message tells the host whether a PN check is 14331 * necessary on rx data frames, and if so, how large the PN counter is. 14332 * This message also tells the host about the security processing to apply 14333 * to defragmented rx frames - specifically, whether a Message Integrity 14334 * Check is required, and the Michael key to use. 14335 * 14336 * |31 24|23 16|15|14 8|7 0| 14337 * |-----------------------------------------------------------------------| 14338 * | peer ID | U| security type | msg type | 14339 * |-----------------------------------------------------------------------| 14340 * | Michael Key K0 | 14341 * |-----------------------------------------------------------------------| 14342 * | Michael Key K1 | 14343 * |-----------------------------------------------------------------------| 14344 * | WAPI RSC Low0 | 14345 * |-----------------------------------------------------------------------| 14346 * | WAPI RSC Low1 | 14347 * |-----------------------------------------------------------------------| 14348 * | WAPI RSC Hi0 | 14349 * |-----------------------------------------------------------------------| 14350 * | WAPI RSC Hi1 | 14351 * |-----------------------------------------------------------------------| 14352 * 14353 * The following field definitions describe the format of the security 14354 * indication message sent from the target to the host. 14355 * - MSG_TYPE 14356 * Bits 7:0 14357 * Purpose: identifies this as a security specification message 14358 * Value: 0xb (HTT_T2H_MSG_TYPE_SEC_IND) 14359 * - SEC_TYPE 14360 * Bits 14:8 14361 * Purpose: specifies which type of security applies to the peer 14362 * Value: htt_sec_type enum value 14363 * - UNICAST 14364 * Bit 15 14365 * Purpose: whether this security is applied to unicast or multicast data 14366 * Value: 1 -> unicast, 0 -> multicast 14367 * - PEER_ID 14368 * Bits 31:16 14369 * Purpose: The ID number for the peer the security specification is for 14370 * Value: peer ID 14371 * - MICHAEL_KEY_K0 14372 * Bits 31:0 14373 * Purpose: 4-byte word that forms the 1st half of the TKIP Michael key 14374 * Value: Michael Key K0 (if security type is TKIP) 14375 * - MICHAEL_KEY_K1 14376 * Bits 31:0 14377 * Purpose: 4-byte word that forms the 2nd half of the TKIP Michael key 14378 * Value: Michael Key K1 (if security type is TKIP) 14379 * - WAPI_RSC_LOW0 14380 * Bits 31:0 14381 * Purpose: 4-byte word that forms the 1st quarter of the 16 byte WAPI RSC 14382 * Value: WAPI RSC Low0 (if security type is WAPI) 14383 * - WAPI_RSC_LOW1 14384 * Bits 31:0 14385 * Purpose: 4-byte word that forms the 2nd quarter of the 16 byte WAPI RSC 14386 * Value: WAPI RSC Low1 (if security type is WAPI) 14387 * - WAPI_RSC_HI0 14388 * Bits 31:0 14389 * Purpose: 4-byte word that forms the 3rd quarter of the 16 byte WAPI RSC 14390 * Value: WAPI RSC Hi0 (if security type is WAPI) 14391 * - WAPI_RSC_HI1 14392 * Bits 31:0 14393 * Purpose: 4-byte word that forms the 4th quarter of the 16 byte WAPI RSC 14394 * Value: WAPI RSC Hi1 (if security type is WAPI) 14395 */ 14396 14397 #define HTT_SEC_IND_SEC_TYPE_M 0x00007f00 14398 #define HTT_SEC_IND_SEC_TYPE_S 8 14399 #define HTT_SEC_IND_UNICAST_M 0x00008000 14400 #define HTT_SEC_IND_UNICAST_S 15 14401 #define HTT_SEC_IND_PEER_ID_M 0xffff0000 14402 #define HTT_SEC_IND_PEER_ID_S 16 14403 14404 #define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ 14405 do { \ 14406 HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ 14407 (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ 14408 } while (0) 14409 #define HTT_SEC_IND_SEC_TYPE_GET(word) \ 14410 (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) 14411 14412 #define HTT_SEC_IND_UNICAST_SET(word, value) \ 14413 do { \ 14414 HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ 14415 (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ 14416 } while (0) 14417 #define HTT_SEC_IND_UNICAST_GET(word) \ 14418 (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) 14419 14420 #define HTT_SEC_IND_PEER_ID_SET(word, value) \ 14421 do { \ 14422 HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ 14423 (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ 14424 } while (0) 14425 #define HTT_SEC_IND_PEER_ID_GET(word) \ 14426 (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) 14427 14428 14429 #define HTT_SEC_IND_BYTES 28 14430 14431 14432 /** 14433 * @brief target -> host rx ADDBA / DELBA message definitions 14434 * 14435 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA 14436 * 14437 * @details 14438 * The following diagram shows the format of the rx ADDBA message sent 14439 * from the target to the host: 14440 * 14441 * |31 20|19 16|15 8|7 0| 14442 * |---------------------------------------------------------------------| 14443 * | peer ID | TID | window size | msg type | 14444 * |---------------------------------------------------------------------| 14445 * 14446 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA 14447 * 14448 * The following diagram shows the format of the rx DELBA message sent 14449 * from the target to the host: 14450 * 14451 * |31 20|19 16|15 10|9 8|7 0| 14452 * |---------------------------------------------------------------------| 14453 * | peer ID | TID | window size | IR| msg type | 14454 * |---------------------------------------------------------------------| 14455 * 14456 * The following field definitions describe the format of the rx ADDBA 14457 * and DELBA messages sent from the target to the host. 14458 * - MSG_TYPE 14459 * Bits 7:0 14460 * Purpose: identifies this as an rx ADDBA or DELBA message 14461 * Value: ADDBA -> 0x5 (HTT_T2H_MSG_TYPE_RX_ADDBA), 14462 * DELBA -> 0x6 (HTT_T2H_MSG_TYPE_RX_DELBA) 14463 * - IR (initiator / recipient) 14464 * Bits 9:8 (DELBA only) 14465 * Purpose: specify whether the DELBA handshake was initiated by the 14466 * local STA/AP, or by the peer STA/AP 14467 * Value: 14468 * 0 - unspecified 14469 * 1 - initiator (a.k.a. originator) 14470 * 2 - recipient (a.k.a. responder) 14471 * 3 - unused / reserved 14472 * - WIN_SIZE 14473 * Bits 15:8 for ADDBA, bits 15:10 for DELBA 14474 * Purpose: Specifies the length of the block ack window (max = 64). 14475 * Value: 14476 * block ack window length specified by the received ADDBA/DELBA 14477 * management message. 14478 * - TID 14479 * Bits 19:16 14480 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 14481 * Value: 14482 * TID specified by the received ADDBA or DELBA management message. 14483 * - PEER_ID 14484 * Bits 31:20 14485 * Purpose: Identifies which peer sent the ADDBA / DELBA. 14486 * Value: 14487 * ID (hash value) used by the host for fast, direct lookup of 14488 * host SW peer info, including rx reorder states. 14489 */ 14490 #define HTT_RX_ADDBA_WIN_SIZE_M 0xff00 14491 #define HTT_RX_ADDBA_WIN_SIZE_S 8 14492 #define HTT_RX_ADDBA_TID_M 0xf0000 14493 #define HTT_RX_ADDBA_TID_S 16 14494 #define HTT_RX_ADDBA_PEER_ID_M 0xfff00000 14495 #define HTT_RX_ADDBA_PEER_ID_S 20 14496 14497 #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \ 14498 do { \ 14499 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ 14500 (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ 14501 } while (0) 14502 #define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ 14503 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 14504 14505 #define HTT_RX_ADDBA_TID_SET(word, value) \ 14506 do { \ 14507 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ 14508 (word) |= (value) << HTT_RX_ADDBA_TID_S; \ 14509 } while (0) 14510 #define HTT_RX_ADDBA_TID_GET(word) \ 14511 (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) 14512 14513 #define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ 14514 do { \ 14515 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ 14516 (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ 14517 } while (0) 14518 #define HTT_RX_ADDBA_PEER_ID_GET(word) \ 14519 (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) 14520 14521 #define HTT_RX_ADDBA_BYTES 4 14522 14523 14524 #define HTT_RX_DELBA_INITIATOR_M 0x00000300 14525 #define HTT_RX_DELBA_INITIATOR_S 8 14526 #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00 14527 #define HTT_RX_DELBA_WIN_SIZE_S 10 14528 #define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M 14529 #define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S 14530 #define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M 14531 #define HTT_RX_DELBA_PEER_ID_S HTT_RX_ADDBA_PEER_ID_S 14532 14533 #define HTT_RX_DELBA_TID_SET HTT_RX_ADDBA_TID_SET 14534 #define HTT_RX_DELBA_TID_GET HTT_RX_ADDBA_TID_GET 14535 #define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET 14536 #define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET 14537 14538 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 14539 do { \ 14540 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 14541 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 14542 } while (0) 14543 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 14544 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 14545 14546 #define HTT_RX_DELBA_WIN_SIZE_SET(word, value) \ 14547 do { \ 14548 HTT_CHECK_SET_VAL(HTT_RX_DELBA_WIN_SIZE, value); \ 14549 (word) |= (value) << HTT_RX_DELBA_WIN_SIZE_S; \ 14550 } while (0) 14551 #define HTT_RX_DELBA_WIN_SIZE_GET(word) \ 14552 (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S) 14553 14554 #define HTT_RX_DELBA_BYTES 4 14555 14556 14557 /** 14558 * @brief target -> host rx ADDBA / DELBA message definitions 14559 * 14560 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN 14561 * 14562 * @details 14563 * The following diagram shows the format of the rx ADDBA extn message sent 14564 * from the target to the host: 14565 * 14566 * |31 20|19 16|15 13|12 8|7 0| 14567 * |---------------------------------------------------------------------| 14568 * | peer ID | TID | reserved | msg type | 14569 * |---------------------------------------------------------------------| 14570 * | reserved | window size | 14571 * |---------------------------------------------------------------------| 14572 * 14573 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA_EXTN 14574 * 14575 * The following diagram shows the format of the rx DELBA message sent 14576 * from the target to the host: 14577 * 14578 * |31 20|19 16|15 13|12 10|9 8|7 0| 14579 * |---------------------------------------------------------------------| 14580 * | peer ID | TID | reserved | IR| msg type | 14581 * |---------------------------------------------------------------------| 14582 * | reserved | window size | 14583 * |---------------------------------------------------------------------| 14584 * 14585 * The following field definitions describe the format of the rx ADDBA 14586 * and DELBA messages sent from the target to the host. 14587 * - MSG_TYPE 14588 * Bits 7:0 14589 * Purpose: identifies this as an rx ADDBA or DELBA message 14590 * Value: ADDBA -> 0x31 (HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN), 14591 * DELBA -> 0x32 (HTT_T2H_MSG_TYPE_RX_DELBA_EXTN) 14592 * - IR (initiator / recipient) 14593 * Bits 9:8 (DELBA only) 14594 * Purpose: specify whether the DELBA handshake was initiated by the 14595 * local STA/AP, or by the peer STA/AP 14596 * Value: 14597 * 0 - unspecified 14598 * 1 - initiator (a.k.a. originator) 14599 * 2 - recipient (a.k.a. responder) 14600 * 3 - unused / reserved 14601 * Value: 14602 * block ack window length specified by the received ADDBA/DELBA 14603 * management message. 14604 * - TID 14605 * Bits 19:16 14606 * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. 14607 * Value: 14608 * TID specified by the received ADDBA or DELBA management message. 14609 * - PEER_ID 14610 * Bits 31:20 14611 * Purpose: Identifies which peer sent the ADDBA / DELBA. 14612 * Value: 14613 * ID (hash value) used by the host for fast, direct lookup of 14614 * host SW peer info, including rx reorder states. 14615 * == DWORD 1 14616 * - WIN_SIZE 14617 * Bits 12:0 for ADDBA, bits 12:0 for DELBA 14618 * Purpose: Specifies the length of the block ack window (max = 8191). 14619 */ 14620 14621 #define HTT_RX_ADDBA_EXTN_TID_M 0xf0000 14622 #define HTT_RX_ADDBA_EXTN_TID_S 16 14623 #define HTT_RX_ADDBA_EXTN_PEER_ID_M 0xfff00000 14624 #define HTT_RX_ADDBA_EXTN_PEER_ID_S 20 14625 14626 /*--- Dword 0 ---*/ 14627 #define HTT_RX_ADDBA_EXTN_TID_SET(word, value) \ 14628 do { \ 14629 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_TID, value); \ 14630 (word) |= (value) << HTT_RX_ADDBA_EXTN_TID_S; \ 14631 } while (0) 14632 #define HTT_RX_ADDBA_EXTN_TID_GET(word) \ 14633 (((word) & HTT_RX_ADDBA_EXTN_TID_M) >> HTT_RX_ADDBA_EXTN_TID_S) 14634 14635 #define HTT_RX_ADDBA_EXTN_PEER_ID_SET(word, value) \ 14636 do { \ 14637 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_PEER_ID, value); \ 14638 (word) |= (value) << HTT_RX_ADDBA_EXTN_PEER_ID_S; \ 14639 } while (0) 14640 #define HTT_RX_ADDBA_EXTN_PEER_ID_GET(word) \ 14641 (((word) & HTT_RX_ADDBA_EXTN_PEER_ID_M) >> HTT_RX_ADDBA_EXTN_PEER_ID_S) 14642 14643 /*--- Dword 1 ---*/ 14644 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_M 0x1fff 14645 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_S 0 14646 14647 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_SET(word, value) \ 14648 do { \ 14649 HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_WIN_SIZE, value); \ 14650 (word) |= (value) << HTT_RX_ADDBA_EXTN_WIN_SIZE_S; \ 14651 } while (0) 14652 14653 #define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \ 14654 (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) 14655 14656 #define HTT_RX_ADDBA_EXTN_BYTES 8 14657 14658 14659 #define HTT_RX_DELBA_EXTN_INITIATOR_M 0x00000300 14660 #define HTT_RX_DELBA_EXTN_INITIATOR_S 8 14661 #define HTT_RX_DELBA_EXTN_TID_M 0xf0000 14662 #define HTT_RX_DELBA_EXTN_TID_S 16 14663 #define HTT_RX_DELBA_EXTN_PEER_ID_M 0xfff00000 14664 #define HTT_RX_DELBA_EXTN_PEER_ID_S 20 14665 14666 /*--- Dword 0 ---*/ 14667 #define HTT_RX_DELBA_INITIATOR_SET(word, value) \ 14668 do { \ 14669 HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \ 14670 (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \ 14671 } while (0) 14672 #define HTT_RX_DELBA_INITIATOR_GET(word) \ 14673 (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S) 14674 14675 #define HTT_RX_DELBA_EXTN_TID_SET(word, value) \ 14676 do { \ 14677 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_TID, value); \ 14678 (word) |= (value) << HTT_RX_DELBA_EXTN_TID_S; \ 14679 } while (0) 14680 #define HTT_RX_DELBA_EXTN_TID_GET(word) \ 14681 (((word) & HTT_RX_DELBA_EXTN_TID_M) >> HTT_RX_DELBA_EXTN_TID_S) 14682 14683 #define HTT_RX_DELBA_EXTN_PEER_ID_SET(word, value) \ 14684 do { \ 14685 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_PEER_ID, value); \ 14686 (word) |= (value) << HTT_RX_DELBA_EXTN_PEER_ID_S; \ 14687 } while (0) 14688 #define HTT_RX_DELBA_EXTN_PEER_ID_GET(word) \ 14689 (((word) & HTT_RX_DELBA_EXTN_PEER_ID_M) >> HTT_RX_DELBA_EXTN_PEER_ID_S) 14690 14691 /*--- Dword 1 ---*/ 14692 #define HTT_RX_DELBA_EXTN_WIN_SIZE_M 0x1fff 14693 #define HTT_RX_DELBA_EXTN_WIN_SIZE_S 0 14694 14695 #define HTT_RX_DELBA_EXTN_WIN_SIZE_SET(word, value) \ 14696 do { \ 14697 HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_WIN_SIZE, value); \ 14698 (word) |= (value) << HTT_RX_DELBA_EXTN_WIN_SIZE_S; \ 14699 } while (0) 14700 #define HTT_RX_DELBA_EXTN_WIN_SIZE_GET(word) \ 14701 (((word) & HTT_RX_DELBA_EXTN_WIN_SIZE_M) >> HTT_RX_DELBA_EXTN_WIN_SIZE_S) 14702 14703 #define HTT_RX_DELBA_EXTN_BYTES 8 14704 14705 14706 /** 14707 * @brief tx queue group information element definition 14708 * 14709 * @details 14710 * The following diagram shows the format of the tx queue group 14711 * information element, which can be included in target --> host 14712 * messages to specify the number of tx "credits" (tx descriptors 14713 * for LL, or tx buffers for HL) available to a particular group 14714 * of host-side tx queues, and which host-side tx queues belong to 14715 * the group. 14716 * 14717 * |31|30 24|23 16|15|14|13 0| 14718 * |------------------------------------------------------------------------| 14719 * | X| reserved | tx queue grp ID | A| S| credit count | 14720 * |------------------------------------------------------------------------| 14721 * | vdev ID mask | AC mask | 14722 * |------------------------------------------------------------------------| 14723 * 14724 * The following definitions describe the fields within the tx queue group 14725 * information element: 14726 * - credit_count 14727 * Bits 13:1 14728 * Purpose: specify how many tx credits are available to the tx queue group 14729 * Value: An absolute or relative, positive or negative credit value 14730 * The 'A' bit specifies whether the value is absolute or relative. 14731 * The 'S' bit specifies whether the value is positive or negative. 14732 * A negative value can only be relative, not absolute. 14733 * An absolute value replaces any prior credit value the host has for 14734 * the tx queue group in question. 14735 * A relative value is added to the prior credit value the host has for 14736 * the tx queue group in question. 14737 * - sign 14738 * Bit 14 14739 * Purpose: specify whether the credit count is positive or negative 14740 * Value: 0 -> positive, 1 -> negative 14741 * - absolute 14742 * Bit 15 14743 * Purpose: specify whether the credit count is absolute or relative 14744 * Value: 0 -> relative, 1 -> absolute 14745 * - txq_group_id 14746 * Bits 23:16 14747 * Purpose: indicate which tx queue group's credit and/or membership are 14748 * being specified 14749 * Value: 0 to max_tx_queue_groups-1 14750 * - reserved 14751 * Bits 30:16 14752 * Value: 0x0 14753 * - eXtension 14754 * Bit 31 14755 * Purpose: specify whether another tx queue group info element follows 14756 * Value: 0 -> no more tx queue group information elements 14757 * 1 -> another tx queue group information element immediately follows 14758 * - ac_mask 14759 * Bits 15:0 14760 * Purpose: specify which Access Categories belong to the tx queue group 14761 * Value: bit-OR of masks for the ACs (WMM and extension) that belong to 14762 * the tx queue group. 14763 * The AC bit-mask values are obtained by left-shifting by the 14764 * corresponding HTT_AC_WMM enum values, e.g. (1 << HTT_AC_WMM_BE) == 0x1 14765 * - vdev_id_mask 14766 * Bits 31:16 14767 * Purpose: specify which vdev's tx queues belong to the tx queue group 14768 * Value: bit-OR of masks based on the IDs of the vdevs whose tx queues 14769 * belong to the tx queue group. 14770 * For example, if vdev IDs 1 and 4 belong to a tx queue group, the 14771 * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12 14772 */ 14773 PREPACK struct htt_txq_group { 14774 A_UINT32 14775 credit_count: 14, 14776 sign: 1, 14777 absolute: 1, 14778 tx_queue_group_id: 8, 14779 reserved0: 7, 14780 extension: 1; 14781 A_UINT32 14782 ac_mask: 16, 14783 vdev_id_mask: 16; 14784 } POSTPACK; 14785 14786 /* first word */ 14787 #define HTT_TXQ_GROUP_CREDIT_COUNT_S 0 14788 #define HTT_TXQ_GROUP_CREDIT_COUNT_M 0x00003fff 14789 #define HTT_TXQ_GROUP_SIGN_S 14 14790 #define HTT_TXQ_GROUP_SIGN_M 0x00004000 14791 #define HTT_TXQ_GROUP_ABS_S 15 14792 #define HTT_TXQ_GROUP_ABS_M 0x00008000 14793 #define HTT_TXQ_GROUP_ID_S 16 14794 #define HTT_TXQ_GROUP_ID_M 0x00ff0000 14795 #define HTT_TXQ_GROUP_EXT_S 31 14796 #define HTT_TXQ_GROUP_EXT_M 0x80000000 14797 /* second word */ 14798 #define HTT_TXQ_GROUP_AC_MASK_S 0 14799 #define HTT_TXQ_GROUP_AC_MASK_M 0x0000ffff 14800 #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16 14801 #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000 14802 14803 #define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ 14804 do { \ 14805 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ 14806 ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ 14807 } while (0) 14808 #define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ 14809 (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> HTT_TXQ_GROUP_CREDIT_COUNT_S) 14810 14811 #define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ 14812 do { \ 14813 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ 14814 ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ 14815 } while (0) 14816 #define HTT_TXQ_GROUP_SIGN_GET(_info) \ 14817 (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) 14818 14819 #define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ 14820 do { \ 14821 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ 14822 ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ 14823 } while (0) 14824 #define HTT_TXQ_GROUP_ABS_GET(_info) \ 14825 (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) 14826 14827 #define HTT_TXQ_GROUP_ID_SET(_info, _val) \ 14828 do { \ 14829 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ 14830 ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ 14831 } while (0) 14832 #define HTT_TXQ_GROUP_ID_GET(_info) \ 14833 (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) 14834 14835 #define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ 14836 do { \ 14837 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ 14838 ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ 14839 } while (0) 14840 #define HTT_TXQ_GROUP_EXT_GET(_info) \ 14841 (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) 14842 14843 #define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ 14844 do { \ 14845 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ 14846 ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ 14847 } while (0) 14848 #define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ 14849 (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) 14850 14851 #define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ 14852 do { \ 14853 HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ 14854 ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ 14855 } while (0) 14856 #define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ 14857 (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> HTT_TXQ_GROUP_VDEV_ID_MASK_S) 14858 14859 /** 14860 * @brief target -> host TX completion indication message definition 14861 * 14862 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_COMPL_IND 14863 * 14864 * @details 14865 * The following diagram shows the format of the TX completion indication sent 14866 * from the target to the host 14867 * 14868 * |31 30|29|28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 14869 * |-------------------------------------------------------------------| 14870 * header: |rsvd |A4|A3|A2|TP|A1|A0| num | t_i| tid |status| msg_type | 14871 * |-------------------------------------------------------------------| 14872 * payload:| MSDU1 ID | MSDU0 ID | 14873 * |-------------------------------------------------------------------| 14874 * : MSDU3 ID | MSDU2 ID : 14875 * |-------------------------------------------------------------------| 14876 * | struct htt_tx_compl_ind_append_retries | 14877 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14878 * | struct htt_tx_compl_ind_append_tx_tstamp | 14879 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14880 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 14881 * |-------------------------------------------------------------------| 14882 * : MSDU3 ACK RSSI | MSDU2 ACK RSSI : 14883 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14884 * | MSDU0 tx_tsf64_low | 14885 * |-------------------------------------------------------------------| 14886 * | MSDU0 tx_tsf64_high | 14887 * |-------------------------------------------------------------------| 14888 * | MSDU1 tx_tsf64_low | 14889 * |-------------------------------------------------------------------| 14890 * | MSDU1 tx_tsf64_high | 14891 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14892 * | phy_timestamp | 14893 * |-------------------------------------------------------------------| 14894 * | rate specs (see below) | 14895 * |-------------------------------------------------------------------| 14896 * | seqctrl | framectrl | 14897 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 14898 * Where: 14899 * A0 = append (a.k.a. append0) 14900 * A1 = append1 14901 * TP = MSDU tx power presence 14902 * A2 = append2 14903 * A3 = append3 14904 * A4 = append4 14905 * 14906 * The following field definitions describe the format of the TX completion 14907 * indication sent from the target to the host 14908 * Header fields: 14909 * - msg_type 14910 * Bits 7:0 14911 * Purpose: identifies this as HTT TX completion indication 14912 * Value: 0x7 (HTT_T2H_MSG_TYPE_TX_COMPL_IND) 14913 * - status 14914 * Bits 10:8 14915 * Purpose: the TX completion status of payload fragmentations descriptors 14916 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 14917 * - tid 14918 * Bits 14:11 14919 * Purpose: the tid associated with those fragmentation descriptors. It is 14920 * valid or not, depending on the tid_invalid bit. 14921 * Value: 0 to 15 14922 * - tid_invalid 14923 * Bits 15:15 14924 * Purpose: this bit indicates whether the tid field is valid or not 14925 * Value: 0 indicates valid; 1 indicates invalid 14926 * - num 14927 * Bits 23:16 14928 * Purpose: the number of payload in this indication 14929 * Value: 1 to 255 14930 * - append (a.k.a. append0) 14931 * Bits 24:24 14932 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 14933 * the number of tx retries for one MSDU at the end of this message 14934 * Value: 0 indicates no appending; 1 indicates appending 14935 * - append1 14936 * Bits 25:25 14937 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 14938 * contains the timestamp info for each TX msdu id in payload. 14939 * The order of the timestamps matches the order of the MSDU IDs. 14940 * Note that a big-endian host needs to account for the reordering 14941 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 14942 * conversion) when determining which tx timestamp corresponds to 14943 * which MSDU ID. 14944 * Value: 0 indicates no appending; 1 indicates appending 14945 * - msdu_tx_power_presence 14946 * Bits 26:26 14947 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 14948 * for each MSDU referenced by the TX_COMPL_IND message. 14949 * The tx power is reported in 0.5 dBm units. 14950 * The order of the per-MSDU tx power reports matches the order 14951 * of the MSDU IDs. 14952 * Note that a big-endian host needs to account for the reordering 14953 * of MSDU IDs within each 4-byte MSDU ID pair (during endianness 14954 * conversion) when determining which Tx Power corresponds to 14955 * which MSDU ID. 14956 * Value: 0 indicates MSDU tx power reports are not appended, 14957 * 1 indicates MSDU tx power reports are appended 14958 * - append2 14959 * Bits 27:27 14960 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 14961 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 14962 * matches the order of the MSDU IDs. Although the ACK RSSI is the 14963 * same for all MSDUs within a single PPDU, the RSSI is duplicated 14964 * for each MSDU, for convenience. 14965 * The ACK RSSI values are valid when status is COMPLETE_OK (and 14966 * this append2 bit is set). 14967 * The ACK RSSI values are SNR in dB, i.e. are the RSSI in units of 14968 * dB above the noise floor. 14969 * Value: 0 indicates MSDU ACK RSSI values are not appended, 14970 * 1 indicates MSDU ACK RSSI values are appended. 14971 * - append3 14972 * Bits 28:28 14973 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tsf64 which 14974 * contains the tx tsf info based on wlan global TSF for 14975 * each TX msdu id in payload. 14976 * The order of the tx tsf matches the order of the MSDU IDs. 14977 * The struct htt_tx_compl_ind_append_tx_tsf64 contains two 32-bits 14978 * values to indicate the the lower 32 bits and higher 32 bits of 14979 * the tx tsf. 14980 * The tx_tsf64 here represents the time MSDU was acked and the 14981 * tx_tsf64 has microseconds units. 14982 * Value: 0 indicates no appending; 1 indicates appending 14983 * - append4 14984 * Bits 29:29 14985 * Purpose: Indicate whether data frame control fields and fields required 14986 * for radio tap header are appended for each MSDU in TX_COMP_IND 14987 * message. The order of the this message matches the order of 14988 * the MSDU IDs. 14989 * Value: 0 indicates frame control fields and fields required for 14990 * radio tap header values are not appended, 14991 * 1 indicates frame control fields and fields required for 14992 * radio tap header values are appended. 14993 * Payload fields: 14994 * - hmsdu_id 14995 * Bits 15:0 14996 * Purpose: this ID is used to track the Tx buffer in host 14997 * Value: 0 to "size of host MSDU descriptor pool - 1" 14998 */ 14999 15000 PREPACK struct htt_tx_data_hdr_information { 15001 A_UINT32 phy_timestamp_l32; /* word 0 [31:0] */ 15002 A_UINT32 /* word 1 */ 15003 /* preamble: 15004 * 0-OFDM, 15005 * 1-CCk, 15006 * 2-HT, 15007 * 3-VHT 15008 */ 15009 preamble: 2, /* [1:0] */ 15010 /* mcs: 15011 * In case of HT preamble interpret 15012 * MCS along with NSS. 15013 * Valid values for HT are 0 to 7. 15014 * HT mcs 0 with NSS 2 is mcs 8. 15015 * Valid values for VHT are 0 to 9. 15016 */ 15017 mcs: 4, /* [5:2] */ 15018 /* rate: 15019 * This is applicable only for 15020 * CCK and OFDM preamble type 15021 * rate 0: OFDM 48 Mbps, 15022 * 1: OFDM 24 Mbps, 15023 * 2: OFDM 12 Mbps 15024 * 3: OFDM 6 Mbps 15025 * 4: OFDM 54 Mbps 15026 * 5: OFDM 36 Mbps 15027 * 6: OFDM 18 Mbps 15028 * 7: OFDM 9 Mbps 15029 * rate 0: CCK 11 Mbps Long 15030 * 1: CCK 5.5 Mbps Long 15031 * 2: CCK 2 Mbps Long 15032 * 3: CCK 1 Mbps Long 15033 * 4: CCK 11 Mbps Short 15034 * 5: CCK 5.5 Mbps Short 15035 * 6: CCK 2 Mbps Short 15036 */ 15037 rate : 3, /* [ 8: 6] */ 15038 rssi : 8, /* [16: 9] units=dBm */ 15039 nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */ 15040 bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */ 15041 stbc : 1, /* [22] */ 15042 sgi : 1, /* [23] */ 15043 ldpc : 1, /* [24] */ 15044 beamformed: 1, /* [25] */ 15045 /* tx_retry_cnt: 15046 * Indicates retry count of data tx frames provided by the host. 15047 */ 15048 tx_retry_cnt: 6; /* [31:26] */ 15049 A_UINT32 /* word 2 */ 15050 framectrl:16, /* [15: 0] */ 15051 seqno:16; /* [31:16] */ 15052 } POSTPACK; 15053 15054 15055 #define HTT_TX_COMPL_IND_STATUS_S 8 15056 #define HTT_TX_COMPL_IND_STATUS_M 0x00000700 15057 #define HTT_TX_COMPL_IND_TID_S 11 15058 #define HTT_TX_COMPL_IND_TID_M 0x00007800 15059 #define HTT_TX_COMPL_IND_TID_INV_S 15 15060 #define HTT_TX_COMPL_IND_TID_INV_M 0x00008000 15061 #define HTT_TX_COMPL_IND_NUM_S 16 15062 #define HTT_TX_COMPL_IND_NUM_M 0x00ff0000 15063 #define HTT_TX_COMPL_IND_APPEND_S 24 15064 #define HTT_TX_COMPL_IND_APPEND_M 0x01000000 15065 #define HTT_TX_COMPL_IND_APPEND1_S 25 15066 #define HTT_TX_COMPL_IND_APPEND1_M 0x02000000 15067 #define HTT_TX_COMPL_IND_TX_POWER_S 26 15068 #define HTT_TX_COMPL_IND_TX_POWER_M 0x04000000 15069 #define HTT_TX_COMPL_IND_APPEND2_S 27 15070 #define HTT_TX_COMPL_IND_APPEND2_M 0x08000000 15071 #define HTT_TX_COMPL_IND_APPEND3_S 28 15072 #define HTT_TX_COMPL_IND_APPEND3_M 0x10000000 15073 #define HTT_TX_COMPL_IND_APPEND4_S 29 15074 #define HTT_TX_COMPL_IND_APPEND4_M 0x20000000 15075 15076 #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \ 15077 do { \ 15078 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ 15079 ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ 15080 } while (0) 15081 #define HTT_TX_COMPL_IND_STATUS_GET(_info) \ 15082 (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) 15083 #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \ 15084 do { \ 15085 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ 15086 ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ 15087 } while (0) 15088 #define HTT_TX_COMPL_IND_NUM_GET(_info) \ 15089 (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) 15090 #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \ 15091 do { \ 15092 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ 15093 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ 15094 } while (0) 15095 #define HTT_TX_COMPL_IND_TID_GET(_info) \ 15096 (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) 15097 #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \ 15098 do { \ 15099 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ 15100 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ 15101 } while (0) 15102 #define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ 15103 (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ 15104 HTT_TX_COMPL_IND_TID_INV_S) 15105 #define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ 15106 do { \ 15107 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ 15108 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ 15109 } while (0) 15110 #define HTT_TX_COMPL_IND_APPEND_GET(_info) \ 15111 (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) 15112 #define HTT_TX_COMPL_IND_APPEND1_SET(_info, _val) \ 15113 do { \ 15114 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND1, _val); \ 15115 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND1_S)); \ 15116 } while (0) 15117 #define HTT_TX_COMPL_IND_APPEND1_GET(_info) \ 15118 (((_info) & HTT_TX_COMPL_IND_APPEND1_M) >> HTT_TX_COMPL_IND_APPEND1_S) 15119 #define HTT_TX_COMPL_IND_TX_POWER_SET(_info, _val) \ 15120 do { \ 15121 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TX_POWER, _val); \ 15122 ((_info) |= ((_val) << HTT_TX_COMPL_IND_TX_POWER_S)); \ 15123 } while (0) 15124 #define HTT_TX_COMPL_IND_TX_POWER_GET(_info) \ 15125 (((_info) & HTT_TX_COMPL_IND_TX_POWER_M) >> HTT_TX_COMPL_IND_TX_POWER_S) 15126 #define HTT_TX_COMPL_IND_APPEND2_SET(_info, _val) \ 15127 do { \ 15128 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND2, _val); \ 15129 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND2_S)); \ 15130 } while (0) 15131 #define HTT_TX_COMPL_IND_APPEND2_GET(_info) \ 15132 (((_info) & HTT_TX_COMPL_IND_APPEND2_M) >> HTT_TX_COMPL_IND_APPEND2_S) 15133 #define HTT_TX_COMPL_IND_APPEND3_SET(_info, _val) \ 15134 do { \ 15135 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND3, _val); \ 15136 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND3_S)); \ 15137 } while (0) 15138 #define HTT_TX_COMPL_IND_APPEND3_GET(_info) \ 15139 (((_info) & HTT_TX_COMPL_IND_APPEND3_M) >> HTT_TX_COMPL_IND_APPEND3_S) 15140 #define HTT_TX_COMPL_IND_APPEND4_SET(_info, _val) \ 15141 do { \ 15142 HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND4, _val); \ 15143 ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND4_S)); \ 15144 } while (0) 15145 #define HTT_TX_COMPL_IND_APPEND4_GET(_info) \ 15146 (((_info) & HTT_TX_COMPL_IND_APPEND4_M) >> HTT_TX_COMPL_IND_APPEND4_S) 15147 15148 #define HTT_TX_COMPL_INV_TX_POWER 0xffff 15149 15150 #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16) 15151 #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1) 15152 15153 #define HTT_TX_COMPL_INV_MSDU_ID 0xffff 15154 15155 #define HTT_TX_COMPL_IND_STAT_OK 0 15156 /* DISCARD: 15157 * current meaning: 15158 * MSDUs were queued for transmission but filtered by HW or SW 15159 * without any over the air attempts 15160 * legacy meaning (HL Rome): 15161 * MSDUs were discarded by the target FW without any over the air 15162 * attempts due to lack of space 15163 */ 15164 #define HTT_TX_COMPL_IND_STAT_DISCARD 1 15165 /* NO_ACK: 15166 * MSDUs were transmitted (repeatedly) but no ACK was received from the peer 15167 */ 15168 #define HTT_TX_COMPL_IND_STAT_NO_ACK 2 15169 /* POSTPONE: 15170 * temporarily-undeliverable MSDUs were deleted to free up space, but should 15171 * be downloaded again later (in the appropriate order), when they are 15172 * deliverable. 15173 */ 15174 #define HTT_TX_COMPL_IND_STAT_POSTPONE 3 15175 /* 15176 * The PEER_DEL tx completion status is used for HL cases 15177 * where the peer the frame is for has been deleted. 15178 * The host has already discarded its copy of the frame, but 15179 * it still needs the tx completion to restore its credit. 15180 */ 15181 #define HTT_TX_COMPL_IND_STAT_PEER_DEL 4 15182 /* DROP: MSDUs dropped due to lack of space (congestion control) */ 15183 #define HTT_TX_COMPL_IND_STAT_DROP 5 15184 #define HTT_TX_COMPL_IND_STAT_HOST_INSPECT 6 15185 15186 15187 #define HTT_TX_COMPL_IND_APPEND_SET_MORE_RETRY(f) ((f) |= 0x1) 15188 #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1)) 15189 15190 PREPACK struct htt_tx_compl_ind_base { 15191 A_UINT32 hdr; 15192 A_UINT16 payload[1/*or more*/]; 15193 } POSTPACK; 15194 15195 PREPACK struct htt_tx_compl_ind_append_retries { 15196 A_UINT16 msdu_id; 15197 A_UINT8 tx_retries; 15198 A_UINT8 flag; /* Bit 0, 1: another append_retries struct is appended 15199 0: this is the last append_retries struct */ 15200 } POSTPACK; 15201 15202 PREPACK struct htt_tx_compl_ind_append_tx_tstamp { 15203 A_UINT32 timestamp[1/*or more*/]; 15204 } POSTPACK; 15205 15206 PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { 15207 A_UINT32 tx_tsf64_low; 15208 A_UINT32 tx_tsf64_high; 15209 } POSTPACK; 15210 15211 /* htt_tx_data_hdr_information payload extension fields: */ 15212 15213 /* DWORD zero */ 15214 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M 0xffffffff 15215 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S 0 15216 15217 /* DWORD one */ 15218 #define HTT_FW_TX_DATA_HDR_PREAMBLE_M 0x00000003 15219 #define HTT_FW_TX_DATA_HDR_PREAMBLE_S 0 15220 #define HTT_FW_TX_DATA_HDR_MCS_M 0x0000003c 15221 #define HTT_FW_TX_DATA_HDR_MCS_S 2 15222 #define HTT_FW_TX_DATA_HDR_RATE_M 0x000001c0 15223 #define HTT_FW_TX_DATA_HDR_RATE_S 6 15224 #define HTT_FW_TX_DATA_HDR_RSSI_M 0x0001fe00 15225 #define HTT_FW_TX_DATA_HDR_RSSI_S 9 15226 #define HTT_FW_TX_DATA_HDR_NSS_M 0x00060000 15227 #define HTT_FW_TX_DATA_HDR_NSS_S 17 15228 #define HTT_FW_TX_DATA_HDR_BW_M 0x00380000 15229 #define HTT_FW_TX_DATA_HDR_BW_S 19 15230 #define HTT_FW_TX_DATA_HDR_STBC_M 0x00400000 15231 #define HTT_FW_TX_DATA_HDR_STBC_S 22 15232 #define HTT_FW_TX_DATA_HDR_SGI_M 0x00800000 15233 #define HTT_FW_TX_DATA_HDR_SGI_S 23 15234 #define HTT_FW_TX_DATA_HDR_LDPC_M 0x01000000 15235 #define HTT_FW_TX_DATA_HDR_LDPC_S 24 15236 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_M 0x02000000 15237 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_S 25 15238 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M 0xfc000000 15239 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S 26 15240 15241 /* DWORD two */ 15242 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_M 0x0000ffff 15243 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_S 0 15244 #define HTT_FW_TX_DATA_HDR_SEQNO_M 0xffff0000 15245 #define HTT_FW_TX_DATA_HDR_SEQNO_S 16 15246 15247 15248 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_SET(word, value) \ 15249 do { \ 15250 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32, value); \ 15251 (word) |= (value) << HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S; \ 15252 } while (0) 15253 #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_GET(word) \ 15254 (((word) & HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M) >> HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S) 15255 15256 #define HTT_FW_TX_DATA_HDR_PREAMBLE_SET(word, value) \ 15257 do { \ 15258 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PREAMBLE, value); \ 15259 (word) |= (value) << HTT_FW_TX_DATA_HDR_PREAMBLE_S; \ 15260 } while (0) 15261 #define HTT_FW_TX_DATA_HDR_PREAMBLE_GET(word) \ 15262 (((word) & HTT_FW_TX_DATA_HDR_PREAMBLE_M) >> HTT_FW_TX_DATA_HDR_PREAMBLE_S) 15263 15264 #define HTT_FW_TX_DATA_HDR_MCS_SET(word, value) \ 15265 do { \ 15266 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_MCS, value); \ 15267 (word) |= (value) << HTT_FW_TX_DATA_HDR_MCS_S; \ 15268 } while (0) 15269 #define HTT_FW_TX_DATA_HDR_MCS_GET(word) \ 15270 (((word) & HTT_FW_TX_DATA_HDR_MCS_M) >> HTT_FW_TX_DATA_HDR_MCS_S) 15271 15272 #define HTT_FW_TX_DATA_HDR_RATE_SET(word, value) \ 15273 do { \ 15274 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RATE, value); \ 15275 (word) |= (value) << HTT_FW_TX_DATA_HDR_RATE_S; \ 15276 } while (0) 15277 #define HTT_FW_TX_DATA_HDR_RATE_GET(word) \ 15278 (((word) & HTT_FW_TX_DATA_HDR_RATE_M) >> HTT_FW_TX_DATA_HDR_RATE_S) 15279 15280 #define HTT_FW_TX_DATA_HDR_RSSI_SET(word, value) \ 15281 do { \ 15282 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RSSI, value); \ 15283 (word) |= (value) << HTT_FW_TX_DATA_HDR_RSSI_S; \ 15284 } while (0) 15285 #define HTT_FW_TX_DATA_HDR_RSSI_GET(word) \ 15286 (((word) & HTT_FW_TX_DATA_HDR_RSSI_M) >> HTT_FW_TX_DATA_HDR_RSSI_S) 15287 15288 15289 #define HTT_FW_TX_DATA_HDR_NSS_SET(word, value) \ 15290 do { \ 15291 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_NSS, value); \ 15292 (word) |= (value) << HTT_FW_TX_DATA_HDR_NSS_S; \ 15293 } while (0) 15294 #define HTT_FW_TX_DATA_HDR_NSS_GET(word) \ 15295 (((word) & HTT_FW_TX_DATA_HDR_NSS_M) >> HTT_FW_TX_DATA_HDR_NSS_S) 15296 15297 #define HTT_FW_TX_DATA_HDR_BW_SET(word, value) \ 15298 do { \ 15299 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BW, value); \ 15300 (word) |= (value) << HTT_FW_TX_DATA_HDR_BW_S; \ 15301 } while (0) 15302 #define HTT_FW_TX_DATA_HDR_BW_GET(word) \ 15303 (((word) & HTT_FW_TX_DATA_HDR_BW_M) >> HTT_FW_TX_DATA_HDR_BW_S) 15304 15305 15306 #define HTT_FW_TX_DATA_HDR_STBC_SET(word, value) \ 15307 do { \ 15308 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_STBC, value); \ 15309 (word) |= (value) << HTT_FW_TX_DATA_HDR_STBC_S; \ 15310 } while (0) 15311 #define HTT_FW_TX_DATA_HDR_STBC_GET(word) \ 15312 (((word) & HTT_FW_TX_DATA_HDR_STBC_M) >> HTT_FW_TX_DATA_HDR_STBC_S) 15313 15314 15315 #define HTT_FW_TX_DATA_HDR_SGI_SET(word, value) \ 15316 do { \ 15317 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SGI, value); \ 15318 (word) |= (value) << HTT_FW_TX_DATA_HDR_SGI_S; \ 15319 } while (0) 15320 #define HTT_FW_TX_DATA_HDR_SGI_GET(word) \ 15321 (((word) & HTT_FW_TX_DATA_HDR_SGI_M) >> HTT_FW_TX_DATA_HDR_SGI_S) 15322 15323 #define HTT_FW_TX_DATA_HDR_LDPC_SET(word, value) \ 15324 do { \ 15325 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_LDPC, value); \ 15326 (word) |= (value) << HTT_FW_TX_DATA_HDR_LDPC_S; \ 15327 } while (0) 15328 #define HTT_FW_TX_DATA_HDR_LDPC_GET(word) \ 15329 (((word) & HTT_FW_TX_DATA_HDR_LDPC_M) >> HTT_FW_TX_DATA_HDR_LDPC_S) 15330 15331 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_SET(word, value) \ 15332 do { \ 15333 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BEAMFORMED, value); \ 15334 (word) |= (value) << HTT_FW_TX_DATA_HDR_BEAMFORMED_S; \ 15335 } while (0) 15336 #define HTT_FW_TX_DATA_HDR_BEAMFORMED_GET(word) \ 15337 (((word) & HTT_FW_TX_DATA_HDR_BEAMFORMED_M) >> HTT_FW_TX_DATA_HDR_BEAMFORMED_S) 15338 15339 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_SET(word, value) \ 15340 do { \ 15341 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_TX_RETRY_CNT, value); \ 15342 (word) |= (value) << HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S; \ 15343 } while (0) 15344 #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_GET(word) \ 15345 (((word) & HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M) >> HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S) 15346 15347 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_SET(word, value) \ 15348 do { \ 15349 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_FRAMECTRL, value); \ 15350 (word) |= (value) << HTT_FW_TX_DATA_HDR_FRAMECTRL_S; \ 15351 } while (0) 15352 #define HTT_FW_TX_DATA_HDR_FRAMECTRL_GET(word) \ 15353 (((word) & HTT_FW_TX_DATA_HDR_FRAMECTRL_M) >> HTT_FW_TX_DATA_HDR_FRAMECTRL_S) 15354 15355 15356 #define HTT_FW_TX_DATA_HDR_SEQNO_SET(word, value) \ 15357 do { \ 15358 HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SEQNO, value); \ 15359 (word) |= (value) << HTT_FW_TX_DATA_HDR_SEQNO_S; \ 15360 } while (0) 15361 #define HTT_FW_TX_DATA_HDR_SEQNO_GET(word) \ 15362 (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S) 15363 15364 15365 /** 15366 * @brief target -> host software UMAC TX completion indication message 15367 * 15368 * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND 15369 * 15370 * @details 15371 * The following diagram shows the format of the soft UMAC TX completion 15372 * indication sent from the target to the host 15373 * 15374 * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| 15375 * |-------------------------------------+----------------+------------| 15376 * hdr: | rsvd | msdu_cnt | msg_type | 15377 * pyld: |===================================================================| 15378 * MSDU 0| buf addr low (bits 31:0) | 15379 * |-----------------------------------------------+------+------------| 15380 * | SW buffer cookie | RS | buf addr hi| 15381 * |--------+--+--+-------------+--------+---------+------+------------| 15382 * | rsvd0 | M| V| tx count | TID | SW peer ID | 15383 * |--------+--+--+-------------+--------+----------------------+------| 15384 * | frametype | TQM status number | RELR | 15385 * |-----+-----+-----------------------------------+--+-+-+-----+------| 15386 * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | 15387 * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| 15388 * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| 15389 * |--------+-------------------------+--+------+-----+--+-+-----+---+-| 15390 * | PPDU transmission TSF | 15391 * |-------------------------------------------------------------------| 15392 * | rsvd3 | 15393 * |===================================================================| 15394 * MSDU 1| buf addr low (bits 31:0) | 15395 * : ... : 15396 * | rsvd3 | 15397 * |===================================================================| 15398 * etc. 15399 * 15400 * Where: 15401 * RS = release source 15402 * V = valid 15403 * M = multicast 15404 * RELR = release reason 15405 * F = first MSDU 15406 * L = last MSDU 15407 * A = MSDU is part of A-MSDU 15408 * I = rate info valid 15409 * PKTYP = packet type 15410 * S = STBC 15411 * LC = LDPC 15412 * OF = OFDMA transmission 15413 */ 15414 typedef enum { 15415 /* 0 (REASON_FRAME_ACKED): 15416 * Corresponds to tqm_release_reason = <enum 0 tqm_rr_frame_acked>; 15417 * frame is removed because an ACK of BA for it was received. 15418 */ 15419 HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, 15420 15421 /* 1 (REASON_REMOVE_CMD_FW): 15422 * Corresponds to tqm_release_reason = <enum 1 tqm_rr_rem_cmd_rem>; 15423 * frame is removed because a remove command of type "Remove_mpdus" 15424 * initiated by SW. 15425 */ 15426 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, 15427 15428 /* 2 (REASON_REMOVE_CMD_TX): 15429 * Corresponds to tqm_release_reason = <enum 2 tqm_rr_rem_cmd_tx>; 15430 * frame is removed because a remove command of type 15431 * "Remove_transmitted_mpdus" initiated by SW. 15432 */ 15433 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, 15434 15435 /* 3 (REASON_REMOVE_CMD_NOTX): 15436 * Corresponds to tqm_release_reason = <enum 3 tqm_rr_rem_cmd_notx>; 15437 * frame is removed because a remove command of type 15438 * "Remove_untransmitted_mpdus" initiated by SW. 15439 */ 15440 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, 15441 15442 /* 4 (REASON_REMOVE_CMD_AGED): 15443 * Corresponds to tqm_release_reason = <enum 4 tqm_rr_rem_cmd_aged>; 15444 * frame is removed because a remove command of type "Remove_aged_mpdus" 15445 * or "Remove_aged_msdus" initiated by SW. 15446 */ 15447 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, 15448 15449 /* 5 (RELEASE_FW_REASON1): 15450 * Corresponds to tqm_release_reason = <enum 5 tqm_fw_reason1>; 15451 * frame is removed because a remove command where fw indicated that 15452 * remove reason is fw_reason1. 15453 */ 15454 HTT_TX_MSDU_RELEASE_FW_REASON1, 15455 15456 /* 6 (RELEASE_FW_REASON2): 15457 * Corresponds to tqm_release_reason = <enum 6 tqm_fw_reason2>; 15458 * frame is removed because a remove command where fw indicated that 15459 * remove reason is fw_reason1. 15460 */ 15461 HTT_TX_MSDU_RELEASE_FW_REASON2, 15462 15463 /* 7 (RELEASE_FW_REASON3): 15464 * Corresponds to tqm_release_reason = <enum 7 tqm_fw_reason3>; 15465 * frame is removed because a remove command where fw indicated that 15466 * remove reason is fw_reason1. 15467 */ 15468 HTT_TX_MSDU_RELEASE_FW_REASON3, 15469 15470 /* 8 (REASON_REMOVE_CMD_DISABLEQ): 15471 * Corresponds to tqm_release_reason = <enum 8 tqm_rr_rem_cmd_disable_queue> 15472 * frame is removed because a remove command of type 15473 * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" 15474 * initiated by SW. 15475 */ 15476 HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, 15477 15478 /* 9 (REASON_DROP_MISC): 15479 * Corresponds to sw_release_reason = Packet dropped by FW due to 15480 * any discard reason that is not categorized as MSDU TTL expired. 15481 * Examples: TXDE ENQ layer dropped the packet due to peer delete, 15482 * tid delete, no resource credit available. 15483 */ 15484 HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, 15485 15486 /* 10 (REASON_DROP_TTL): 15487 * Corresponds to sw_release_reason = Packet dropped by FW due to 15488 * discard reason that frame is not transmitted due to MSDU TTL expired. 15489 */ 15490 HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, 15491 15492 /* 11 - available for use */ 15493 /* 12 - available for use */ 15494 /* 13 - available for use */ 15495 /* 14 - available for use */ 15496 /* 15 - available for use */ 15497 15498 HTT_TX_MSDU_RELEASE_REASON_MAX = 16 15499 } htt_t2h_tx_msdu_release_reason_e; 15500 15501 typedef enum { 15502 /* 0 (RELEASE_SOURCE_FW): 15503 * MSDU released by FW even before the frame was queued to TQM-L HW. 15504 */ 15505 HTT_TX_MSDU_RELEASE_SOURCE_FW, 15506 15507 /* 1 (RELEASE_SOURCE_TQM_LITE): 15508 * MSDU released by TQM-L HW. 15509 */ 15510 HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, 15511 15512 HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 15513 } htt_t2h_tx_msdu_release_source_e; 15514 15515 struct htt_t2h_tx_buffer_addr_info { /* 2 words */ 15516 A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ 15517 A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ 15518 /* release_source: 15519 * holds a htt_t2h_tx_msdu_release_source_e enum value 15520 */ 15521 release_source : 3, /* [10:8] */ 15522 sw_buffer_cookie : 21; /* [31:11] */ 15523 /* NOTE: 15524 * To preserve backwards compatibility, 15525 * no new fields can be added in this struct. 15526 */ 15527 }; 15528 15529 /* member definitions of htt_t2h_tx_buffer_addr_info */ 15530 15531 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF 15532 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 15533 15534 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ 15535 do { \ 15536 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ 15537 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ 15538 } while (0) 15539 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ 15540 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) 15541 15542 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF 15543 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 15544 15545 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ 15546 do { \ 15547 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ 15548 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ 15549 } while (0) 15550 #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ 15551 (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) 15552 15553 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 15554 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 15555 15556 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ 15557 do { \ 15558 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ 15559 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ 15560 } while (0) 15561 #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ 15562 (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) 15563 15564 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 15565 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 15566 15567 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 15568 do { \ 15569 HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ 15570 (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ 15571 } while (0) 15572 #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ 15573 (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) 15574 15575 struct htt_t2h_tx_rate_stats_info { /* 2 words */ 15576 /* word 0 */ 15577 A_UINT32 15578 /* tx_rate_stats_info_valid: 15579 * Indicates if the tx rate stats below are valid. 15580 */ 15581 tx_rate_stats_info_valid : 1, /* [0] */ 15582 /* transmit_bw: 15583 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15584 * Indicates the BW of the upcoming transmission that shall likely 15585 * start in about 3 -4 us on the medium: 15586 * <enum 0 transmit_bw_20_MHz> 15587 * <enum 1 transmit_bw_40_MHz> 15588 * <enum 2 transmit_bw_80_MHz> 15589 * <enum 3 transmit_bw_160_MHz> 15590 * <enum 4 transmit_bw_320_MHz> 15591 */ 15592 transmit_bw : 3, /* [3:1] */ 15593 /* transmit_pkt_type: 15594 * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15595 * Field filled in by PDG. 15596 * Not valid when in SW transmit mode 15597 * The packet type 15598 * <enum_type PKT_TYPE_ENUM> 15599 * Type: enum Definition Name: PKT_TYPE_ENUM 15600 * enum number enum name Description 15601 * ------------------------------------ 15602 * 0 dot11a 802.11a PPDU type 15603 * 1 dot11b 802.11b PPDU type 15604 * 2 dot11n_mm 802.11n Mixed Mode PPDU type 15605 * 3 dot11ac 802.11ac PPDU type 15606 * 4 dot11ax 802.11ax PPDU type 15607 * 5 dot11ba 802.11ba (WUR) PPDU type 15608 * 6 dot11be 802.11be PPDU type 15609 * 7 dot11az 802.11az (ranging) PPDU type 15610 */ 15611 transmit_pkt_type : 4, /* [7:4] */ 15612 /* transmit_stbc: 15613 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15614 * Field filled in by PDG. 15615 * Not valid when in SW transmit mode 15616 * When set, STBC transmission rate was used. 15617 */ 15618 transmit_stbc : 1, /* [8] */ 15619 /* transmit_ldpc: 15620 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15621 * Field filled in by PDG. 15622 * Not valid when in SW transmit mode 15623 * When set, use LDPC transmission rates 15624 */ 15625 transmit_ldpc : 1, /* [9] */ 15626 /* transmit_sgi: 15627 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15628 * Field filled in by PDG. 15629 * Not valid when in SW transmit mode 15630 * <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used for HE 15631 * <enum 1 0_4_us_sgi > Legacy short GI. Can also be used for HE 15632 * <enum 2 1_6_us_sgi > HE related GI 15633 * <enum 3 3_2_us_sgi > HE related GI 15634 * <legal 0 - 3> 15635 */ 15636 transmit_sgi : 2, /* [11:10] */ 15637 /* transmit_mcs: 15638 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15639 * Field filled in by PDG. 15640 * Not valid when in SW transmit mode 15641 * 15642 * For details, refer to MCS_TYPE description 15643 * <legal all> 15644 * Pkt_type Related definition of MCS_TYPE 15645 * dot11b This field is the rate: 15646 * 0: CCK 11 Mbps Long 15647 * 1: CCK 5.5 Mbps Long 15648 * 2: CCK 2 Mbps Long 15649 * 3: CCK 1 Mbps Long 15650 * 4: CCK 11 Mbps Short 15651 * 5: CCK 5.5 Mbps Short 15652 * 6: CCK 2 Mbps Short 15653 * NOTE: The numbering here is NOT the same as the as MAC gives 15654 * in the "rate" field in the SIG given to the PHY. 15655 * The MAC will do an internal translation. 15656 * 15657 * Dot11a This field is the rate: 15658 * 0: OFDM 48 Mbps 15659 * 1: OFDM 24 Mbps 15660 * 2: OFDM 12 Mbps 15661 * 3: OFDM 6 Mbps 15662 * 4: OFDM 54 Mbps 15663 * 5: OFDM 36 Mbps 15664 * 6: OFDM 18 Mbps 15665 * 7: OFDM 9 Mbps 15666 * NOTE: The numbering here is NOT the same as the as MAC gives 15667 * in the "rate" field in the SIG given to the PHY. 15668 * The MAC will do an internal translation. 15669 * 15670 * Dot11n_mm (mixed mode) This field represends the MCS. 15671 * 0: HT MCS 0 (BPSK 1/2) 15672 * 1: HT MCS 1 (QPSK 1/2) 15673 * 2: HT MCS 2 (QPSK 3/4) 15674 * 3: HT MCS 3 (16-QAM 1/2) 15675 * 4: HT MCS 4 (16-QAM 3/4) 15676 * 5: HT MCS 5 (64-QAM 2/3) 15677 * 6: HT MCS 6 (64-QAM 3/4) 15678 * 7: HT MCS 7 (64-QAM 5/6) 15679 * NOTE: To get higher MCS's use the nss field to indicate the 15680 * number of spatial streams. 15681 * 15682 * Dot11ac This field represends the MCS. 15683 * 0: VHT MCS 0 (BPSK 1/2) 15684 * 1: VHT MCS 1 (QPSK 1/2) 15685 * 2: VHT MCS 2 (QPSK 3/4) 15686 * 3: VHT MCS 3 (16-QAM 1/2) 15687 * 4: VHT MCS 4 (16-QAM 3/4) 15688 * 5: VHT MCS 5 (64-QAM 2/3) 15689 * 6: VHT MCS 6 (64-QAM 3/4) 15690 * 7: VHT MCS 7 (64-QAM 5/6) 15691 * 8: VHT MCS 8 (256-QAM 3/4) 15692 * 9: VHT MCS 9 (256-QAM 5/6) 15693 * 10: VHT MCS 10 (1024-QAM 3/4) 15694 * 11: VHT MCS 11 (1024-QAM 5/6) 15695 * NOTE: There are several illegal VHT rates due to fractional 15696 * number of bits per symbol. 15697 * Below are the illegal rates for 4 streams and lower: 15698 * 20 MHz, 1 stream, MCS 9 15699 * 20 MHz, 2 stream, MCS 9 15700 * 20 MHz, 4 stream, MCS 9 15701 * 80 MHz, 3 stream, MCS 6 15702 * 160 MHz, 3 stream, MCS 9 (Unsupported) 15703 * 160 MHz, 4 stream, MCS 7 (Unsupported) 15704 * 15705 * dot11ax This field represends the MCS. 15706 * 0: HE MCS 0 (BPSK 1/2) 15707 * 1: HE MCS 1 (QPSK 1/2) 15708 * 2: HE MCS 2 (QPSK 3/4) 15709 * 3: HE MCS 3 (16-QAM 1/2) 15710 * 4: HE MCS 4 (16-QAM 3/4) 15711 * 5: HE MCS 5 (64-QAM 2/3) 15712 * 6: HE MCS 6 (64-QAM 3/4) 15713 * 7: HE MCS 7 (64-QAM 5/6) 15714 * 8: HE MCS 8 (256-QAM 3/4) 15715 * 9: HE MCS 9 (256-QAM 5/6) 15716 * 10: HE MCS 10 (1024-QAM 3/4) 15717 * 11: HE MCS 11 (1024-QAM 5/6) 15718 * 12: HE MCS 12 (4096-QAM 3/4) 15719 * 13: HE MCS 13 (4096-QAM 5/6) 15720 * 15721 * dot11ba This field is the rate: 15722 * 0: LDR 15723 * 1: HDR 15724 * 2: Exclusive rate 15725 */ 15726 transmit_mcs : 4, /* [15:12] */ 15727 /* ofdma_transmission: 15728 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15729 * Field filled in by PDG. 15730 * Set when the transmission was an OFDMA transmission (DL or UL). 15731 * <legal all> 15732 */ 15733 ofdma_transmission : 1, /* [16] */ 15734 /* tones_in_ru: 15735 * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. 15736 * Field filled in by PDG. 15737 * Not valid when in SW transmit mode 15738 * The number of tones in the RU used. 15739 * <legal all> 15740 */ 15741 tones_in_ru : 12, /* [28:17] */ 15742 rsvd2 : 3; /* [31:29] */ 15743 15744 /* word 1 */ 15745 /* ppdu_transmission_tsf: 15746 * Based on a HWSCH configuration register setting, 15747 * this field either contains: 15748 * Lower 32 bits of the TSF, snapshot of this value when transmission 15749 * of the PPDU containing the frame finished. 15750 * OR 15751 * Lower 32 bits of the TSF, snapshot of this value when transmission 15752 * of the PPDU containing the frame started. 15753 * <legal all> 15754 */ 15755 A_UINT32 ppdu_transmission_tsf; 15756 15757 /* NOTE: 15758 * To preserve backwards compatibility, 15759 * no new fields can be added in this struct. 15760 */ 15761 }; 15762 15763 /* member definitions of htt_t2h_tx_rate_stats_info */ 15764 15765 #define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 15766 #define HTT_TX_RATE_STATS_INFO_VALID_S 0 15767 15768 #define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ 15769 do { \ 15770 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ 15771 (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ 15772 } while (0) 15773 #define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ 15774 (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) 15775 15776 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E 15777 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 15778 15779 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ 15780 do { \ 15781 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ 15782 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ 15783 } while (0) 15784 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ 15785 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) 15786 15787 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 15788 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 15789 15790 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ 15791 do { \ 15792 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ 15793 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ 15794 } while (0) 15795 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ 15796 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) 15797 15798 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 15799 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 15800 15801 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ 15802 do { \ 15803 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ 15804 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ 15805 } while (0) 15806 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ 15807 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) 15808 15809 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 15810 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 15811 15812 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ 15813 do { \ 15814 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ 15815 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ 15816 } while (0) 15817 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ 15818 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) 15819 15820 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 15821 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 15822 15823 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ 15824 do { \ 15825 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ 15826 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ 15827 } while (0) 15828 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ 15829 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) 15830 15831 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 15832 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 15833 15834 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ 15835 do { \ 15836 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ 15837 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ 15838 } while (0) 15839 #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ 15840 (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) 15841 15842 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 15843 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 15844 15845 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ 15846 do { \ 15847 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ 15848 (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ 15849 } while (0) 15850 #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ 15851 (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) 15852 15853 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 15854 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 15855 15856 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ 15857 do { \ 15858 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ 15859 (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ 15860 } while (0) 15861 #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ 15862 (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) 15863 15864 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF 15865 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 15866 15867 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ 15868 do { \ 15869 HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ 15870 (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ 15871 } while (0) 15872 #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ 15873 (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) 15874 15875 struct htt_t2h_tx_msdu_info { /* 8 words */ 15876 /* words 0 + 1 */ 15877 struct htt_t2h_tx_buffer_addr_info addr_info; 15878 15879 /* word 2 */ 15880 A_UINT32 15881 sw_peer_id : 16, 15882 tid : 4, 15883 transmit_cnt : 7, 15884 valid : 1, 15885 mcast : 1, 15886 rsvd0 : 3; 15887 15888 /* word 3 */ 15889 A_UINT32 15890 release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ 15891 tqm_status_number : 24, 15892 frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ 15893 15894 /* word 4 */ 15895 A_UINT32 15896 /* ack_frame_rssi: 15897 * If this frame is removed as the result of the 15898 * reception of an ACK or BA, this field indicates 15899 * the RSSI of the received ACK or BA frame. 15900 * When the frame is removed as result of a direct 15901 * remove command from the SW, this field is set 15902 * to 0x0 (which is never a valid value when real 15903 * RSSI is available). 15904 * Units: dB w.r.t noise floor 15905 */ 15906 ack_frame_rssi : 8, 15907 first_msdu : 1, 15908 last_msdu : 1, 15909 msdu_part_of_amsdu : 1, 15910 buffer_timestamp : 19, /* units = TU = 1024 microseconds */ 15911 rsvd1 : 2; 15912 15913 /* words 5 + 6 */ 15914 struct htt_t2h_tx_rate_stats_info tx_rate_stats; 15915 15916 /* word 7 */ 15917 /* rsvd3: 15918 * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] 15919 * is not sufficient 15920 */ 15921 A_UINT32 rsvd3; 15922 15923 /* NOTE: 15924 * To preserve backwards compatibility, 15925 * no new fields can be added in this struct. 15926 */ 15927 }; 15928 15929 /* member definitions of htt_t2h_tx_msdu_info */ 15930 15931 #define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF 15932 #define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 15933 15934 #define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ 15935 do { \ 15936 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ 15937 (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ 15938 } while (0) 15939 #define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ 15940 (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) 15941 15942 #define HTT_TX_MSDU_INFO_TID_M 0x000F0000 15943 #define HTT_TX_MSDU_INFO_TID_S 16 15944 15945 #define HTT_TX_MSDU_INFO_TID_SET(word, value) \ 15946 do { \ 15947 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ 15948 (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ 15949 } while (0) 15950 #define HTT_TX_MSDU_INFO_TID_GET(word) \ 15951 (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) 15952 15953 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 15954 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 15955 15956 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ 15957 do { \ 15958 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ 15959 (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ 15960 } while (0) 15961 #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ 15962 (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) 15963 15964 #define HTT_TX_MSDU_INFO_VALID_M 0x08000000 15965 #define HTT_TX_MSDU_INFO_VALID_S 27 15966 15967 #define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ 15968 do { \ 15969 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ 15970 (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ 15971 } while (0) 15972 #define HTT_TX_MSDU_INFO_VALID_GET(word) \ 15973 (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) 15974 15975 #define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 15976 #define HTT_TX_MSDU_INFO_MCAST_S 28 15977 15978 #define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ 15979 do { \ 15980 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ 15981 (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ 15982 } while (0) 15983 #define HTT_TX_MSDU_INFO_MCAST_GET(word) \ 15984 (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) 15985 15986 #define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F 15987 #define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 15988 15989 #define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ 15990 do { \ 15991 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ 15992 (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ 15993 } while (0) 15994 #define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ 15995 (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) 15996 15997 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 15998 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 15999 16000 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ 16001 do { \ 16002 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ 16003 (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ 16004 } while (0) 16005 #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ 16006 (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) 16007 16008 #define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 16009 #define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 16010 16011 #define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ 16012 do { \ 16013 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ 16014 (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ 16015 } while (0) 16016 #define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ 16017 (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) 16018 16019 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF 16020 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 16021 16022 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ 16023 do { \ 16024 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ 16025 (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ 16026 } while (0) 16027 #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ 16028 (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) 16029 16030 #define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 16031 #define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 16032 16033 #define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ 16034 do { \ 16035 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ 16036 (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ 16037 } while (0) 16038 #define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ 16039 (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) 16040 16041 #define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 16042 #define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 16043 16044 #define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ 16045 do { \ 16046 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ 16047 (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ 16048 } while (0) 16049 #define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ 16050 (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) 16051 16052 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 16053 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 16054 16055 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ 16056 do { \ 16057 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ 16058 (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ 16059 } while (0) 16060 #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ 16061 (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) 16062 16063 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 16064 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 16065 16066 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ 16067 do { \ 16068 HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ 16069 (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ 16070 } while (0) 16071 #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ 16072 (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) 16073 16074 struct htt_t2h_soft_umac_tx_compl_ind { 16075 A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ 16076 msdu_cnt : 8, /* min: 0, max: 255 */ 16077 rsvd0 : 16; 16078 /* NOTE: 16079 * To preserve backwards compatibility, 16080 * no new fields can be added in this struct. 16081 */ 16082 /* 16083 * append here: 16084 * struct htt_t2h_tx_msdu_info payload[1(or more)] 16085 * for all the msdu's that are part of this completion. 16086 */ 16087 }; 16088 16089 /* member definitions of htt_t2h_soft_umac_tx_compl_ind */ 16090 16091 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 16092 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 16093 16094 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ 16095 do { \ 16096 HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ 16097 (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ 16098 } while (0) 16099 #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ 16100 (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) 16101 16102 16103 /** 16104 * @brief target -> host rate-control update indication message 16105 * 16106 * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND) 16107 * 16108 * @details 16109 * The following diagram shows the format of the RC Update message 16110 * sent from the target to the host, while processing the tx-completion 16111 * of a transmitted PPDU. 16112 * 16113 * |31 24|23 16|15 8|7 0| 16114 * |-------------------------------------------------------------| 16115 * | peer ID | vdev ID | msg_type | 16116 * |-------------------------------------------------------------| 16117 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 16118 * |-------------------------------------------------------------| 16119 * | reserved | num elems | MAC addr 5 | MAC addr 4 | 16120 * |-------------------------------------------------------------| 16121 * | : | 16122 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16123 * | : | 16124 * |-------------------------------------------------------------| 16125 * | : | 16126 * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : 16127 * | : | 16128 * |-------------------------------------------------------------| 16129 * : : 16130 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16131 * 16132 */ 16133 16134 typedef struct { 16135 A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ 16136 A_UINT32 rate_code_flags; 16137 A_UINT32 flags; /* Encodes information such as excessive 16138 retransmission, aggregate, some info 16139 from .11 frame control, 16140 STBC, LDPC, (SGI and Tx Chain Mask 16141 are encoded in ptx_rc->flags field), 16142 AMPDU truncation (BT/time based etc.), 16143 RTS/CTS attempt */ 16144 16145 A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ 16146 A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ 16147 A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ 16148 A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ 16149 A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ 16150 A_UINT32 is_probe; /* Valid if probing. Else, 0 */ 16151 } HTT_RC_TX_DONE_PARAMS; 16152 16153 #define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS)) /* bytes */ 16154 #define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ 16155 16156 #define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ 16157 #define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ 16158 16159 #define HTT_RC_UPDATE_VDEVID_S 8 16160 #define HTT_RC_UPDATE_VDEVID_M 0xff00 16161 #define HTT_RC_UPDATE_PEERID_S 16 16162 #define HTT_RC_UPDATE_PEERID_M 0xffff0000 16163 16164 #define HTT_RC_UPDATE_NUM_ELEMS_S 16 16165 #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000 16166 16167 #define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ 16168 do { \ 16169 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ 16170 ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ 16171 } while (0) 16172 16173 #define HTT_RC_UPDATE_VDEVID_GET(_info) \ 16174 (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) 16175 16176 #define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ 16177 do { \ 16178 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ 16179 ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ 16180 } while (0) 16181 16182 #define HTT_RC_UPDATE_PEERID_GET(_info) \ 16183 (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) 16184 16185 #define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ 16186 do { \ 16187 HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ 16188 ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ 16189 } while (0) 16190 16191 #define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ 16192 (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) 16193 16194 /** 16195 * @brief target -> host rx fragment indication message definition 16196 * 16197 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FRAG_IND 16198 * 16199 * @details 16200 * The following field definitions describe the format of the rx fragment 16201 * indication message sent from the target to the host. 16202 * The rx fragment indication message shares the format of the 16203 * rx indication message, but not all fields from the rx indication message 16204 * are relevant to the rx fragment indication message. 16205 * 16206 * 16207 * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| 16208 * |-----------+-------------------+---------------------+-------------| 16209 * | peer ID | |FV| ext TID | msg type | 16210 * |-------------------------------------------------------------------| 16211 * | | flush | flush | 16212 * | | end | start | 16213 * | | seq num | seq num | 16214 * |-------------------------------------------------------------------| 16215 * | reserved | FW rx desc bytes | 16216 * |-------------------------------------------------------------------| 16217 * | | FW MSDU Rx | 16218 * | | desc B0 | 16219 * |-------------------------------------------------------------------| 16220 * Header fields: 16221 * - MSG_TYPE 16222 * Bits 7:0 16223 * Purpose: identifies this as an rx fragment indication message 16224 * Value: 0xa (HTT_T2H_MSG_TYPE_RX_FRAG_IND) 16225 * - EXT_TID 16226 * Bits 12:8 16227 * Purpose: identify the traffic ID of the rx data, including 16228 * special "extended" TID values for multicast, broadcast, and 16229 * non-QoS data frames 16230 * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS 16231 * - FLUSH_VALID (FV) 16232 * Bit 13 16233 * Purpose: indicate whether the flush IE (start/end sequence numbers) 16234 * is valid 16235 * Value: 16236 * 1 -> flush IE is valid and needs to be processed 16237 * 0 -> flush IE is not valid and should be ignored 16238 * - PEER_ID 16239 * Bits 31:16 16240 * Purpose: Identify, by ID, which peer sent the rx data 16241 * Value: ID of the peer who sent the rx data 16242 * - FLUSH_SEQ_NUM_START 16243 * Bits 5:0 16244 * Purpose: Indicate the start of a series of MPDUs to flush 16245 * Not all MPDUs within this series are necessarily valid - the host 16246 * must check each sequence number within this range to see if the 16247 * corresponding MPDU is actually present. 16248 * This field is only valid if the FV bit is set. 16249 * Value: 16250 * The sequence number for the first MPDUs to check to flush. 16251 * The sequence number is masked by 0x3f. 16252 * - FLUSH_SEQ_NUM_END 16253 * Bits 11:6 16254 * Purpose: Indicate the end of a series of MPDUs to flush 16255 * Value: 16256 * The sequence number one larger than the sequence number of the 16257 * last MPDU to check to flush. 16258 * The sequence number is masked by 0x3f. 16259 * Not all MPDUs within this series are necessarily valid - the host 16260 * must check each sequence number within this range to see if the 16261 * corresponding MPDU is actually present. 16262 * This field is only valid if the FV bit is set. 16263 * Rx descriptor fields: 16264 * - FW_RX_DESC_BYTES 16265 * Bits 15:0 16266 * Purpose: Indicate how many bytes in the Rx indication are used for 16267 * FW Rx descriptors 16268 * Value: 1 16269 */ 16270 #define HTT_RX_FRAG_IND_HDR_PREFIX_SIZE32 2 16271 16272 #define HTT_RX_FRAG_IND_FW_DESC_BYTE_OFFSET 12 16273 16274 #define HTT_RX_FRAG_IND_EXT_TID_SET HTT_RX_IND_EXT_TID_SET 16275 #define HTT_RX_FRAG_IND_EXT_TID_GET HTT_RX_IND_EXT_TID_GET 16276 16277 #define HTT_RX_FRAG_IND_PEER_ID_SET HTT_RX_IND_PEER_ID_SET 16278 #define HTT_RX_FRAG_IND_PEER_ID_GET HTT_RX_IND_PEER_ID_GET 16279 16280 #define HTT_RX_FRAG_IND_FLUSH_VALID_SET HTT_RX_IND_FLUSH_VALID_SET 16281 #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET 16282 16283 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \ 16284 HTT_RX_IND_FLUSH_SEQ_NUM_START_SET 16285 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \ 16286 HTT_RX_IND_FLUSH_SEQ_NUM_START_GET 16287 16288 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ 16289 HTT_RX_IND_FLUSH_SEQ_NUM_END_SET 16290 #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ 16291 HTT_RX_IND_FLUSH_SEQ_NUM_END_GET 16292 16293 #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET 16294 16295 #define HTT_RX_FRAG_IND_BYTES \ 16296 (4 /* msg hdr */ + \ 16297 4 /* flush spec */ + \ 16298 4 /* (unused) FW rx desc bytes spec */ + \ 16299 4 /* FW rx desc */) 16300 16301 /** 16302 * @brief target -> host test message definition 16303 * 16304 * MSG_TYPE => HTT_T2H_MSG_TYPE_TEST 16305 * 16306 * @details 16307 * The following field definitions describe the format of the test 16308 * message sent from the target to the host. 16309 * The message consists of a 4-octet header, followed by a variable 16310 * number of 32-bit integer values, followed by a variable number 16311 * of 8-bit character values. 16312 * 16313 * |31 16|15 8|7 0| 16314 * |-----------------------------------------------------------| 16315 * | num chars | num ints | msg type | 16316 * |-----------------------------------------------------------| 16317 * | int 0 | 16318 * |-----------------------------------------------------------| 16319 * | int 1 | 16320 * |-----------------------------------------------------------| 16321 * | ... | 16322 * |-----------------------------------------------------------| 16323 * | char 3 | char 2 | char 1 | char 0 | 16324 * |-----------------------------------------------------------| 16325 * | | | ... | char 4 | 16326 * |-----------------------------------------------------------| 16327 * - MSG_TYPE 16328 * Bits 7:0 16329 * Purpose: identifies this as a test message 16330 * Value: HTT_MSG_TYPE_TEST 16331 * - NUM_INTS 16332 * Bits 15:8 16333 * Purpose: indicate how many 32-bit integers follow the message header 16334 * - NUM_CHARS 16335 * Bits 31:16 16336 * Purpose: indicate how many 8-bit characters follow the series of integers 16337 */ 16338 #define HTT_RX_TEST_NUM_INTS_M 0xff00 16339 #define HTT_RX_TEST_NUM_INTS_S 8 16340 #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000 16341 #define HTT_RX_TEST_NUM_CHARS_S 16 16342 16343 #define HTT_RX_TEST_NUM_INTS_SET(word, value) \ 16344 do { \ 16345 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ 16346 (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ 16347 } while (0) 16348 #define HTT_RX_TEST_NUM_INTS_GET(word) \ 16349 (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) 16350 16351 #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \ 16352 do { \ 16353 HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ 16354 (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ 16355 } while (0) 16356 #define HTT_RX_TEST_NUM_CHARS_GET(word) \ 16357 (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) 16358 16359 /** 16360 * @brief target -> host packet log message 16361 * 16362 * MSG_TYPE => HTT_T2H_MSG_TYPE_PKTLOG 16363 * 16364 * @details 16365 * The following field definitions describe the format of the packet log 16366 * message sent from the target to the host. 16367 * The message consists of a 4-octet header,followed by a variable number 16368 * of 32-bit character values. 16369 * 16370 * |31 16|15 12|11 10|9 8|7 0| 16371 * |------------------------------------------------------------------| 16372 * | payload_size | rsvd |pdev_id|mac_id| msg type | 16373 * |------------------------------------------------------------------| 16374 * | payload | 16375 * |------------------------------------------------------------------| 16376 * - MSG_TYPE 16377 * Bits 7:0 16378 * Purpose: identifies this as a pktlog message 16379 * Value: 0x8 (HTT_T2H_MSG_TYPE_PKTLOG) 16380 * - mac_id 16381 * Bits 9:8 16382 * Purpose: identifies which MAC/PHY instance generated this pktlog info 16383 * Value: 0-3 16384 * - pdev_id 16385 * Bits 11:10 16386 * Purpose: pdev_id 16387 * Value: 0-3 16388 * 0 (for rings at SOC level), 16389 * 1/2/3 PDEV -> 0/1/2 16390 * - payload_size 16391 * Bits 31:16 16392 * Purpose: explicitly specify the payload size 16393 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 16394 */ 16395 PREPACK struct htt_pktlog_msg { 16396 A_UINT32 header; 16397 A_UINT32 payload[1/* or more */]; 16398 } POSTPACK; 16399 16400 #define HTT_T2H_PKTLOG_MAC_ID_M 0x00000300 16401 #define HTT_T2H_PKTLOG_MAC_ID_S 8 16402 16403 #define HTT_T2H_PKTLOG_PDEV_ID_M 0x00000C00 16404 #define HTT_T2H_PKTLOG_PDEV_ID_S 10 16405 16406 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_M 0xFFFF0000 16407 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_S 16 16408 16409 #define HTT_T2H_PKTLOG_MAC_ID_SET(word, value) \ 16410 do { \ 16411 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_MAC_ID, value); \ 16412 (word) |= (value) << HTT_T2H_PKTLOG_MAC_ID_S; \ 16413 } while (0) 16414 #define HTT_T2H_PKTLOG_MAC_ID_GET(word) \ 16415 (((word) & HTT_T2H_PKTLOG_MAC_ID_M) >> \ 16416 HTT_T2H_PKTLOG_MAC_ID_S) 16417 16418 #define HTT_T2H_PKTLOG_PDEV_ID_SET(word, value) \ 16419 do { \ 16420 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PDEV_ID, value); \ 16421 (word) |= (value) << HTT_T2H_PKTLOG_PDEV_ID_S; \ 16422 } while (0) 16423 #define HTT_T2H_PKTLOG_PDEV_ID_GET(word) \ 16424 (((word) & HTT_T2H_PKTLOG_PDEV_ID_M) >> \ 16425 HTT_T2H_PKTLOG_PDEV_ID_S) 16426 16427 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_SET(word, value) \ 16428 do { \ 16429 HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PAYLOAD_SIZE, value); \ 16430 (word) |= (value) << HTT_T2H_PKTLOG_PAYLOAD_SIZE_S; \ 16431 } while (0) 16432 #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_GET(word) \ 16433 (((word) & HTT_T2H_PKTLOG_PAYLOAD_SIZE_M) >> \ 16434 HTT_T2H_PKTLOG_PAYLOAD_SIZE_S) 16435 16436 /* 16437 * Rx reorder statistics 16438 * NB: all the fields must be defined in 4 octets size. 16439 */ 16440 struct rx_reorder_stats { 16441 /* Non QoS MPDUs received */ 16442 A_UINT32 deliver_non_qos; 16443 /* MPDUs received in-order */ 16444 A_UINT32 deliver_in_order; 16445 /* Flush due to reorder timer expired */ 16446 A_UINT32 deliver_flush_timeout; 16447 /* Flush due to move out of window */ 16448 A_UINT32 deliver_flush_oow; 16449 /* Flush due to DELBA */ 16450 A_UINT32 deliver_flush_delba; 16451 /* MPDUs dropped due to FCS error */ 16452 A_UINT32 fcs_error; 16453 /* MPDUs dropped due to monitor mode non-data packet */ 16454 A_UINT32 mgmt_ctrl; 16455 /* Unicast-data MPDUs dropped due to invalid peer */ 16456 A_UINT32 invalid_peer; 16457 /* MPDUs dropped due to duplication (non aggregation) */ 16458 A_UINT32 dup_non_aggr; 16459 /* MPDUs dropped due to processed before */ 16460 A_UINT32 dup_past; 16461 /* MPDUs dropped due to duplicate in reorder queue */ 16462 A_UINT32 dup_in_reorder; 16463 /* Reorder timeout happened */ 16464 A_UINT32 reorder_timeout; 16465 /* invalid bar ssn */ 16466 A_UINT32 invalid_bar_ssn; 16467 /* reorder reset due to bar ssn */ 16468 A_UINT32 ssn_reset; 16469 /* Flush due to delete peer */ 16470 A_UINT32 deliver_flush_delpeer; 16471 /* Flush due to offload*/ 16472 A_UINT32 deliver_flush_offload; 16473 /* Flush due to out of buffer*/ 16474 A_UINT32 deliver_flush_oob; 16475 /* MPDUs dropped due to PN check fail */ 16476 A_UINT32 pn_fail; 16477 /* MPDUs dropped due to unable to allocate memory */ 16478 A_UINT32 store_fail; 16479 /* Number of times the tid pool alloc succeeded */ 16480 A_UINT32 tid_pool_alloc_succ; 16481 /* Number of times the MPDU pool alloc succeeded */ 16482 A_UINT32 mpdu_pool_alloc_succ; 16483 /* Number of times the MSDU pool alloc succeeded */ 16484 A_UINT32 msdu_pool_alloc_succ; 16485 /* Number of times the tid pool alloc failed */ 16486 A_UINT32 tid_pool_alloc_fail; 16487 /* Number of times the MPDU pool alloc failed */ 16488 A_UINT32 mpdu_pool_alloc_fail; 16489 /* Number of times the MSDU pool alloc failed */ 16490 A_UINT32 msdu_pool_alloc_fail; 16491 /* Number of times the tid pool freed */ 16492 A_UINT32 tid_pool_free; 16493 /* Number of times the MPDU pool freed */ 16494 A_UINT32 mpdu_pool_free; 16495 /* Number of times the MSDU pool freed */ 16496 A_UINT32 msdu_pool_free; 16497 /* number of MSDUs undelivered to HTT and queued to Data Rx MSDU free list*/ 16498 A_UINT32 msdu_queued; 16499 /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ 16500 A_UINT32 msdu_recycled; 16501 /* Number of MPDUs with invalid peer but A2 found in AST */ 16502 A_UINT32 invalid_peer_a2_in_ast; 16503 /* Number of MPDUs with invalid peer but A3 found in AST */ 16504 A_UINT32 invalid_peer_a3_in_ast; 16505 /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ 16506 A_UINT32 invalid_peer_bmc_mpdus; 16507 /* Number of MSDUs with err attention word */ 16508 A_UINT32 rxdesc_err_att; 16509 /* Number of MSDUs with flag of peer_idx_invalid */ 16510 A_UINT32 rxdesc_err_peer_idx_inv; 16511 /* Number of MSDUs with flag of peer_idx_timeout */ 16512 A_UINT32 rxdesc_err_peer_idx_to; 16513 /* Number of MSDUs with flag of overflow */ 16514 A_UINT32 rxdesc_err_ov; 16515 /* Number of MSDUs with flag of msdu_length_err */ 16516 A_UINT32 rxdesc_err_msdu_len; 16517 /* Number of MSDUs with flag of mpdu_length_err */ 16518 A_UINT32 rxdesc_err_mpdu_len; 16519 /* Number of MSDUs with flag of tkip_mic_err */ 16520 A_UINT32 rxdesc_err_tkip_mic; 16521 /* Number of MSDUs with flag of decrypt_err */ 16522 A_UINT32 rxdesc_err_decrypt; 16523 /* Number of MSDUs with flag of fcs_err */ 16524 A_UINT32 rxdesc_err_fcs; 16525 /* Number of Unicast (bc_mc bit is not set in attention word) 16526 * frames with invalid peer handler 16527 */ 16528 A_UINT32 rxdesc_uc_msdus_inv_peer; 16529 /* Number of unicast frame directly (direct bit is set in attention word) 16530 * to DUT with invalid peer handler 16531 */ 16532 A_UINT32 rxdesc_direct_msdus_inv_peer; 16533 /* Number of Broadcast/Multicast (bc_mc bit set in attention word) 16534 * frames with invalid peer handler 16535 */ 16536 A_UINT32 rxdesc_bmc_msdus_inv_peer; 16537 /* Number of MSDUs dropped due to no first MSDU flag */ 16538 A_UINT32 rxdesc_no_1st_msdu; 16539 /* Number of MSDUs dropped due to ring overflow */ 16540 A_UINT32 msdu_drop_ring_ov; 16541 /* Number of MSDUs dropped due to FC mismatch */ 16542 A_UINT32 msdu_drop_fc_mismatch; 16543 /* Number of MSDUs dropped due to mgt frame in Remote ring */ 16544 A_UINT32 msdu_drop_mgmt_remote_ring; 16545 /* Number of MSDUs dropped due to errors not reported in attention word */ 16546 A_UINT32 msdu_drop_misc; 16547 /* Number of MSDUs go to offload before reorder */ 16548 A_UINT32 offload_msdu_wal; 16549 /* Number of data frame dropped by offload after reorder */ 16550 A_UINT32 offload_msdu_reorder; 16551 /* Number of MPDUs with sequence number in the past and within the BA window */ 16552 A_UINT32 dup_past_within_window; 16553 /* Number of MPDUs with sequence number in the past and outside the BA window */ 16554 A_UINT32 dup_past_outside_window; 16555 /* Number of MSDUs with decrypt/MIC error */ 16556 A_UINT32 rxdesc_err_decrypt_mic; 16557 /* Number of data MSDUs received on both local and remote rings */ 16558 A_UINT32 data_msdus_on_both_rings; 16559 /* MPDUs never filled */ 16560 A_UINT32 holes_not_filled; 16561 }; 16562 16563 16564 /* 16565 * Rx Remote buffer statistics 16566 * NB: all the fields must be defined in 4 octets size. 16567 */ 16568 struct rx_remote_buffer_mgmt_stats { 16569 /* Total number of MSDUs reaped for Rx processing */ 16570 A_UINT32 remote_reaped; 16571 /* MSDUs recycled within firmware */ 16572 A_UINT32 remote_recycled; 16573 /* MSDUs stored by Data Rx */ 16574 A_UINT32 data_rx_msdus_stored; 16575 /* Number of HTT indications from WAL Rx MSDU */ 16576 A_UINT32 wal_rx_ind; 16577 /* Number of unconsumed HTT indications from WAL Rx MSDU */ 16578 A_UINT32 wal_rx_ind_unconsumed; 16579 /* Number of HTT indications from Data Rx MSDU */ 16580 A_UINT32 data_rx_ind; 16581 /* Number of unconsumed HTT indications from Data Rx MSDU */ 16582 A_UINT32 data_rx_ind_unconsumed; 16583 /* Number of HTT indications from ATHBUF */ 16584 A_UINT32 athbuf_rx_ind; 16585 /* Number of remote buffers requested for refill */ 16586 A_UINT32 refill_buf_req; 16587 /* Number of remote buffers filled by the host */ 16588 A_UINT32 refill_buf_rsp; 16589 /* Number of times MAC hw_index = f/w write_index */ 16590 A_INT32 mac_no_bufs; 16591 /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ 16592 A_INT32 fw_indices_equal; 16593 /* Number of times f/w finds no buffers to post */ 16594 A_INT32 host_no_bufs; 16595 }; 16596 16597 /* 16598 * TXBF MU/SU packets and NDPA statistics 16599 * NB: all the fields must be defined in 4 octets size. 16600 */ 16601 struct rx_txbf_musu_ndpa_pkts_stats { 16602 A_UINT32 number_mu_pkts; /* number of TXBF MU packets received */ 16603 A_UINT32 number_su_pkts; /* number of TXBF SU packets received */ 16604 A_UINT32 txbf_directed_ndpa_count; /* number of TXBF directed NDPA */ 16605 A_UINT32 txbf_ndpa_retry_count; /* number of TXBF retried NDPA */ 16606 A_UINT32 txbf_total_ndpa_count; /* total number of TXBF NDPA */ 16607 16608 A_UINT32 reserved[3]; /* must be set to 0x0 */ 16609 }; 16610 16611 16612 /* 16613 * htt_dbg_stats_status - 16614 * present - The requested stats have been delivered in full. 16615 * This indicates that either the stats information was contained 16616 * in its entirety within this message, or else this message 16617 * completes the delivery of the requested stats info that was 16618 * partially delivered through earlier STATS_CONF messages. 16619 * partial - The requested stats have been delivered in part. 16620 * One or more subsequent STATS_CONF messages with the same 16621 * cookie value will be sent to deliver the remainder of the 16622 * information. 16623 * error - The requested stats could not be delivered, for example due 16624 * to a shortage of memory to construct a message holding the 16625 * requested stats. 16626 * invalid - The requested stat type is either not recognized, or the 16627 * target is configured to not gather the stats type in question. 16628 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16629 * series_done - This special value indicates that no further stats info 16630 * elements are present within a series of stats info elems 16631 * (within a stats upload confirmation message). 16632 */ 16633 enum htt_dbg_stats_status { 16634 HTT_DBG_STATS_STATUS_PRESENT = 0, 16635 HTT_DBG_STATS_STATUS_PARTIAL = 1, 16636 HTT_DBG_STATS_STATUS_ERROR = 2, 16637 HTT_DBG_STATS_STATUS_INVALID = 3, 16638 16639 16640 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 16641 }; 16642 16643 /** 16644 * @brief target -> host statistics upload 16645 * 16646 * MSG_TYPE => HTT_T2H_MSG_TYPE_STATS_CONF 16647 * 16648 * @details 16649 * The following field definitions describe the format of the HTT target 16650 * to host stats upload confirmation message. 16651 * The message contains a cookie echoed from the HTT host->target stats 16652 * upload request, which identifies which request the confirmation is 16653 * for, and a series of tag-length-value stats information elements. 16654 * The tag-length header for each stats info element also includes a 16655 * status field, to indicate whether the request for the stat type in 16656 * question was fully met, partially met, unable to be met, or invalid 16657 * (if the stat type in question is disabled in the target). 16658 * A special value of all 1's in this status field is used to indicate 16659 * the end of the series of stats info elements. 16660 * 16661 * 16662 * |31 16|15 8|7 5|4 0| 16663 * |------------------------------------------------------------| 16664 * | reserved | msg type | 16665 * |------------------------------------------------------------| 16666 * | cookie LSBs | 16667 * |------------------------------------------------------------| 16668 * | cookie MSBs | 16669 * |------------------------------------------------------------| 16670 * | stats entry length | reserved | S |stat type| 16671 * |------------------------------------------------------------| 16672 * | | 16673 * | type-specific stats info | 16674 * | | 16675 * |------------------------------------------------------------| 16676 * | stats entry length | reserved | S |stat type| 16677 * |------------------------------------------------------------| 16678 * | | 16679 * | type-specific stats info | 16680 * | | 16681 * |------------------------------------------------------------| 16682 * | n/a | reserved | 111 | n/a | 16683 * |------------------------------------------------------------| 16684 * Header fields: 16685 * - MSG_TYPE 16686 * Bits 7:0 16687 * Purpose: identifies this is a statistics upload confirmation message 16688 * Value: 0x9 (HTT_T2H_MSG_TYPE_STATS_CONF) 16689 * - COOKIE_LSBS 16690 * Bits 31:0 16691 * Purpose: Provide a mechanism to match a target->host stats confirmation 16692 * message with its preceding host->target stats request message. 16693 * Value: LSBs of the opaque cookie specified by the host-side requestor 16694 * - COOKIE_MSBS 16695 * Bits 31:0 16696 * Purpose: Provide a mechanism to match a target->host stats confirmation 16697 * message with its preceding host->target stats request message. 16698 * Value: MSBs of the opaque cookie specified by the host-side requestor 16699 * 16700 * Stats Information Element tag-length header fields: 16701 * - STAT_TYPE 16702 * Bits 4:0 16703 * Purpose: identifies the type of statistics info held in the 16704 * following information element 16705 * Value: htt_dbg_stats_type 16706 * - STATUS 16707 * Bits 7:5 16708 * Purpose: indicate whether the requested stats are present 16709 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 16710 * the completion of the stats entry series 16711 * - LENGTH 16712 * Bits 31:16 16713 * Purpose: indicate the stats information size 16714 * Value: This field specifies the number of bytes of stats information 16715 * that follows the element tag-length header. 16716 * It is expected but not required that this length is a multiple of 16717 * 4 bytes. Even if the length is not an integer multiple of 4, the 16718 * subsequent stats entry header will begin on a 4-byte aligned 16719 * boundary. 16720 */ 16721 #define HTT_T2H_STATS_COOKIE_SIZE 8 16722 16723 #define HTT_T2H_STATS_CONF_TAIL_SIZE 4 16724 16725 #define HTT_T2H_STATS_CONF_HDR_SIZE 4 16726 16727 #define HTT_T2H_STATS_CONF_TLV_HDR_SIZE 4 16728 16729 #define HTT_T2H_STATS_CONF_TLV_TYPE_M 0x0000001f 16730 #define HTT_T2H_STATS_CONF_TLV_TYPE_S 0 16731 #define HTT_T2H_STATS_CONF_TLV_STATUS_M 0x000000e0 16732 #define HTT_T2H_STATS_CONF_TLV_STATUS_S 5 16733 #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000 16734 #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16 16735 16736 #define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ 16737 do { \ 16738 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ 16739 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ 16740 } while (0) 16741 #define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ 16742 (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ 16743 HTT_T2H_STATS_CONF_TLV_TYPE_S) 16744 16745 #define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ 16746 do { \ 16747 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ 16748 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ 16749 } while (0) 16750 #define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ 16751 (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ 16752 HTT_T2H_STATS_CONF_TLV_STATUS_S) 16753 16754 #define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ 16755 do { \ 16756 HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ 16757 (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ 16758 } while (0) 16759 #define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ 16760 (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ 16761 HTT_T2H_STATS_CONF_TLV_LENGTH_S) 16762 16763 #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18 16764 #define HTT_MAX_AGGR 64 16765 #define HTT_HL_MAX_AGGR 18 16766 16767 /** 16768 * @brief host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 16769 * 16770 * MSG_TYPE => HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG 16771 * 16772 * @details 16773 * The following field definitions describe the format of the HTT host 16774 * to target frag_desc/msdu_ext bank configuration message. 16775 * The message contains the based address and the min and max id of the 16776 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 16777 * MSDU_EXT/FRAG_DESC. 16778 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 16779 * In peregrine the firmware will use fragment_desc_ptr but in WIFI2.0 16780 * the hardware does the mapping/translation. 16781 * 16782 * Total banks that can be configured is configured to 16. 16783 * 16784 * This should be called before any TX has be initiated by the HTT 16785 * 16786 * |31 16|15 8|7 5|4 0| 16787 * |------------------------------------------------------------| 16788 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 16789 * |------------------------------------------------------------| 16790 * | BANK0_BASE_ADDRESS (bits 31:0) | 16791 #if HTT_PADDR64 16792 * | BANK0_BASE_ADDRESS (bits 63:32) | 16793 #endif 16794 * |------------------------------------------------------------| 16795 * | ... | 16796 * |------------------------------------------------------------| 16797 * | BANK15_BASE_ADDRESS (bits 31:0) | 16798 #if HTT_PADDR64 16799 * | BANK15_BASE_ADDRESS (bits 63:32) | 16800 #endif 16801 * |------------------------------------------------------------| 16802 * | BANK0_MAX_ID | BANK0_MIN_ID | 16803 * |------------------------------------------------------------| 16804 * | ... | 16805 * |------------------------------------------------------------| 16806 * | BANK15_MAX_ID | BANK15_MIN_ID | 16807 * |------------------------------------------------------------| 16808 * Header fields: 16809 * - MSG_TYPE 16810 * Bits 7:0 16811 * Value: 0x6 (HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG) 16812 * for systems with 64-bit format for bus addresses: 16813 * - BANKx_BASE_ADDRESS_LO 16814 * Bits 31:0 16815 * Purpose: Provide a mechanism to specify the base address of the 16816 * MSDU_EXT bank physical/bus address. 16817 * Value: lower 4 bytes of MSDU_EXT bank physical / bus address 16818 * - BANKx_BASE_ADDRESS_HI 16819 * Bits 31:0 16820 * Purpose: Provide a mechanism to specify the base address of the 16821 * MSDU_EXT bank physical/bus address. 16822 * Value: higher 4 bytes of MSDU_EXT bank physical / bus address 16823 * for systems with 32-bit format for bus addresses: 16824 * - BANKx_BASE_ADDRESS 16825 * Bits 31:0 16826 * Purpose: Provide a mechanism to specify the base address of the 16827 * MSDU_EXT bank physical/bus address. 16828 * Value: MSDU_EXT bank physical / bus address 16829 * - BANKx_MIN_ID 16830 * Bits 15:0 16831 * Purpose: Provide a mechanism to specify the min index that needs to 16832 * mapped. 16833 * - BANKx_MAX_ID 16834 * Bits 31:16 16835 * Purpose: Provide a mechanism to specify the max index that needs to 16836 * mapped. 16837 * 16838 */ 16839 16840 /** @todo Compress the fields to fit MAX HTT Message size, until then configure to a 16841 * safe value. 16842 * @note MAX supported banks is 16. 16843 */ 16844 #define HTT_TX_MSDU_EXT_BANK_MAX 4 16845 16846 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_M 0x300 16847 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_S 8 16848 16849 #define HTT_H2T_FRAG_DESC_BANK_SWAP_M 0x400 16850 #define HTT_H2T_FRAG_DESC_BANK_SWAP_S 10 16851 16852 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M 0xff0000 16853 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S 16 16854 16855 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M 0xff000000 16856 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S 24 16857 16858 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M 0xffff 16859 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S 0 16860 16861 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000 16862 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16 16863 16864 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ 16865 do { \ 16866 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ 16867 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ 16868 } while (0) 16869 #define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ 16870 (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> HTT_H2T_FRAG_DESC_BANK_PDEVID_S) 16871 16872 #define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ 16873 do { \ 16874 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value); \ 16875 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S); \ 16876 } while (0) 16877 #define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ 16878 (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> HTT_H2T_FRAG_DESC_BANK_SWAP_S) 16879 16880 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ 16881 do { \ 16882 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ 16883 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ 16884 } while (0) 16885 #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ 16886 (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) 16887 16888 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ 16889 do { \ 16890 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ 16891 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ 16892 } while (0) 16893 #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ 16894 (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) 16895 16896 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ 16897 do { \ 16898 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ 16899 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ 16900 } while (0) 16901 #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ 16902 (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) 16903 16904 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ 16905 do { \ 16906 HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ 16907 (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ 16908 } while (0) 16909 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ 16910 (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) 16911 16912 16913 /* 16914 * TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T: 16915 * This macro defines a htt_tx_frag_descXXX_bank_cfg_t in which any physical 16916 * addresses are stored in a XXX-bit field. 16917 * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and 16918 * htt_tx_frag_desc64_bank_cfg_t structs. 16919 */ 16920 #define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ 16921 _paddr_bits_, \ 16922 _paddr__bank_base_address_) \ 16923 PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ 16924 /** word 0 \ 16925 * msg_type: 8, \ 16926 * pdev_id: 2, \ 16927 * swap: 1, \ 16928 * reserved0: 5, \ 16929 * num_banks: 8, \ 16930 * desc_size: 8; \ 16931 */ \ 16932 A_UINT32 word0; \ 16933 /* \ 16934 * If bank_base_address is 64 bits, the upper / lower halves are stored \ 16935 * in little-endian order (bytes 0-3 in the first A_UINT32, bytes 4-7 in \ 16936 * the second A_UINT32). \ 16937 */ \ 16938 _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ 16939 A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ 16940 } POSTPACK 16941 /* define htt_tx_frag_desc32_bank_cfg_t */ 16942 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address)); 16943 /* define htt_tx_frag_desc64_bank_cfg_t */ 16944 TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); 16945 /* 16946 * Make htt_tx_frag_desc_bank_cfg_t be an alias for either 16947 * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t 16948 */ 16949 #if HTT_PADDR64 16950 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t 16951 #else 16952 #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t 16953 #endif 16954 16955 /** 16956 * @brief target -> host HTT TX Credit total count update message definition 16957 * 16958 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND 16959 * 16960 *|31 16|15|14 9| 8 |7 0 | 16961 *|---------------------+--+----------+-------+----------| 16962 *|cur htt credit delta | Q| reserved | sign | msg type | 16963 *|------------------------------------------------------| 16964 * 16965 * Header fields: 16966 * - MSG_TYPE 16967 * Bits 7:0 16968 * Purpose: identifies this as a htt tx credit delta update message 16969 * Value: 0xf (HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND) 16970 * - SIGN 16971 * Bits 8 16972 * identifies whether credit delta is positive or negative 16973 * Value: 16974 * - 0x0: credit delta is positive, rebalance in some buffers 16975 * - 0x1: credit delta is negative, rebalance out some buffers 16976 * - reserved 16977 * Bits 14:9 16978 * Value: 0x0 16979 * - TXQ_GRP 16980 * Bit 15 16981 * Purpose: indicates whether any tx queue group information elements 16982 * are appended to the tx credit update message 16983 * Value: 0 -> no tx queue group information element is present 16984 * 1 -> a tx queue group information element immediately follows 16985 * - DELTA_COUNT 16986 * Bits 31:16 16987 * Purpose: Specify current htt credit delta absolute count 16988 */ 16989 16990 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 16991 #define HTT_TX_CREDIT_SIGN_BIT_S 8 16992 #define HTT_TX_CREDIT_TXQ_GRP_M 0x00008000 16993 #define HTT_TX_CREDIT_TXQ_GRP_S 15 16994 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 16995 #define HTT_TX_CREDIT_DELTA_ABS_S 16 16996 16997 16998 #define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ 16999 do { \ 17000 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ 17001 (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ 17002 } while (0) 17003 17004 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ 17005 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) 17006 17007 #define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ 17008 do { \ 17009 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ 17010 (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ 17011 } while (0) 17012 17013 #define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ 17014 (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) 17015 17016 #define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ 17017 do { \ 17018 HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ 17019 (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ 17020 } while (0) 17021 17022 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ 17023 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) 17024 17025 17026 #define HTT_TX_CREDIT_MSG_BYTES 4 17027 17028 #define HTT_TX_CREDIT_SIGN_BIT_POSITIVE 0x0 17029 #define HTT_TX_CREDIT_SIGN_BIT_NEGATIVE 0x1 17030 17031 17032 /** 17033 * @brief HTT WDI_IPA Operation Response Message 17034 * 17035 * MSG_TYPE => HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE 17036 * 17037 * @details 17038 * HTT WDI_IPA Operation Response message is sent by target 17039 * to host confirming suspend or resume operation. 17040 * |31 24|23 16|15 8|7 0| 17041 * |----------------+----------------+----------------+----------------| 17042 * | op_code | Rsvd | msg_type | 17043 * |-------------------------------------------------------------------| 17044 * | Rsvd | Response len | 17045 * |-------------------------------------------------------------------| 17046 * | | 17047 * | Response-type specific info | 17048 * | | 17049 * | | 17050 * |-------------------------------------------------------------------| 17051 * Header fields: 17052 * - MSG_TYPE 17053 * Bits 7:0 17054 * Purpose: Identifies this as WDI_IPA Operation Response message 17055 * value: = 0x14 (HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE) 17056 * - OP_CODE 17057 * Bits 31:16 17058 * Purpose: Identifies the operation target is responding to (e.g. TX suspend) 17059 * value: = enum htt_wdi_ipa_op_code 17060 * - RSP_LEN 17061 * Bits 16:0 17062 * Purpose: length for the response-type specific info 17063 * value: = length in bytes for response-type specific info 17064 * For example, if OP_CODE == HTT_WDI_IPA_OPCODE_DBG_STATS, the 17065 * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t). 17066 */ 17067 17068 PREPACK struct htt_wdi_ipa_op_response_t 17069 { 17070 /* DWORD 0: flags and meta-data */ 17071 A_UINT32 17072 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17073 reserved1: 8, 17074 op_code: 16; 17075 A_UINT32 17076 rsp_len: 16, 17077 reserved2: 16; 17078 } POSTPACK; 17079 17080 #define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ 17081 17082 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000 17083 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16 17084 17085 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff 17086 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0 17087 17088 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ 17089 (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) 17090 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ 17091 do { \ 17092 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ 17093 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ 17094 } while (0) 17095 17096 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ 17097 (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) 17098 #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ 17099 do { \ 17100 HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ 17101 ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ 17102 } while (0) 17103 17104 17105 enum htt_phy_mode { 17106 htt_phy_mode_11a = 0, 17107 htt_phy_mode_11g = 1, 17108 htt_phy_mode_11b = 2, 17109 htt_phy_mode_11g_only = 3, 17110 htt_phy_mode_11na_ht20 = 4, 17111 htt_phy_mode_11ng_ht20 = 5, 17112 htt_phy_mode_11na_ht40 = 6, 17113 htt_phy_mode_11ng_ht40 = 7, 17114 htt_phy_mode_11ac_vht20 = 8, 17115 htt_phy_mode_11ac_vht40 = 9, 17116 htt_phy_mode_11ac_vht80 = 10, 17117 htt_phy_mode_11ac_vht20_2g = 11, 17118 htt_phy_mode_11ac_vht40_2g = 12, 17119 htt_phy_mode_11ac_vht80_2g = 13, 17120 htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ 17121 htt_phy_mode_11ac_vht160 = 15, 17122 17123 htt_phy_mode_max, 17124 }; 17125 17126 /** 17127 * @brief target -> host HTT channel change indication 17128 * 17129 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CHANGE 17130 * 17131 * @details 17132 * Specify when a channel change occurs. 17133 * This allows the host to precisely determine which rx frames arrived 17134 * on the old channel and which rx frames arrived on the new channel. 17135 * 17136 *|31 |7 0 | 17137 *|-------------------------------------------+----------| 17138 *| reserved | msg type | 17139 *|------------------------------------------------------| 17140 *| primary_chan_center_freq_mhz | 17141 *|------------------------------------------------------| 17142 *| contiguous_chan1_center_freq_mhz | 17143 *|------------------------------------------------------| 17144 *| contiguous_chan2_center_freq_mhz | 17145 *|------------------------------------------------------| 17146 *| phy_mode | 17147 *|------------------------------------------------------| 17148 * 17149 * Header fields: 17150 * - MSG_TYPE 17151 * Bits 7:0 17152 * Purpose: identifies this as a htt channel change indication message 17153 * Value: 0x15 (HTT_T2H_MSG_TYPE_CHAN_CHANGE) 17154 * - PRIMARY_CHAN_CENTER_FREQ_MHZ 17155 * Bits 31:0 17156 * Purpose: identify the (center of the) new 20 MHz primary channel 17157 * Value: center frequency of the 20 MHz primary channel, in MHz units 17158 * - CONTIG_CHAN1_CENTER_FREQ_MHZ 17159 * Bits 31:0 17160 * Purpose: identify the (center of the) contiguous frequency range 17161 * comprising the new channel. 17162 * For example, if the new channel is a 80 MHz channel extending 17163 * 60 MHz beyond the primary channel, this field would be 30 larger 17164 * than the primary channel center frequency field. 17165 * Value: center frequency of the contiguous frequency range comprising 17166 * the full channel in MHz units 17167 * (80+80 channels also use the CONTIG_CHAN2 field) 17168 * - CONTIG_CHAN2_CENTER_FREQ_MHZ 17169 * Bits 31:0 17170 * Purpose: Identify the (center of the) 80 MHz extension frequency range 17171 * within a VHT 80+80 channel. 17172 * This field is only relevant for VHT 80+80 channels. 17173 * Value: center frequency of the 80 MHz extension channel in a VHT 80+80 17174 * channel (arbitrary value for cases besides VHT 80+80) 17175 * - PHY_MODE 17176 * Bits 31:0 17177 * Purpose: specify the PHY channel's type (legacy vs. HT vs. VHT), width, 17178 * and band 17179 * Value: htt_phy_mode enum value 17180 */ 17181 17182 PREPACK struct htt_chan_change_t 17183 { 17184 /* DWORD 0: flags and meta-data */ 17185 A_UINT32 17186 msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ 17187 reserved1: 24; 17188 A_UINT32 primary_chan_center_freq_mhz; 17189 A_UINT32 contig_chan1_center_freq_mhz; 17190 A_UINT32 contig_chan2_center_freq_mhz; 17191 A_UINT32 phy_mode; 17192 } POSTPACK; 17193 /* 17194 * Due to historical / backwards-compatibility reasons, maintain the 17195 * below htt_chan_change_msg struct definition, which needs to be 17196 * consistent with the above htt_chan_change_t struct definition 17197 * (aside from the htt_chan_change_t definition including the msg_type 17198 * dword within the message, and the htt_chan_change_msg only containing 17199 * the payload of the message that follows the msg_type dword). 17200 */ 17201 PREPACK struct htt_chan_change_msg { 17202 A_UINT32 chan_mhz; /* frequency in mhz */ 17203 A_UINT32 band_center_freq1; /* Center frequency 1 in MHz */ 17204 A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ 17205 A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */ 17206 } POSTPACK; 17207 17208 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff 17209 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S 0 17210 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M 0xffffffff 17211 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S 0 17212 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M 0xffffffff 17213 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S 0 17214 #define HTT_CHAN_CHANGE_PHY_MODE_M 0xffffffff 17215 #define HTT_CHAN_CHANGE_PHY_MODE_S 0 17216 17217 17218 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ 17219 do { \ 17220 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value);\ 17221 (word) |= (value) << HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ 17222 } while (0) 17223 #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ 17224 (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ 17225 >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) 17226 17227 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ 17228 do { \ 17229 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value);\ 17230 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ 17231 } while (0) 17232 #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ 17233 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ 17234 >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) 17235 17236 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ 17237 do { \ 17238 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value);\ 17239 (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ 17240 } while (0) 17241 #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ 17242 (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ 17243 >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) 17244 17245 #define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ 17246 do { \ 17247 HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value);\ 17248 (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ 17249 } while (0) 17250 #define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ 17251 (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ 17252 >> HTT_CHAN_CHANGE_PHY_MODE_S) 17253 17254 #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t) 17255 17256 17257 /** 17258 * @brief rx offload packet error message 17259 * 17260 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR 17261 * 17262 * @details 17263 * HTT_RX_OFLD_PKT_ERR message is sent by target to host to indicate err 17264 * of target payload like mic err. 17265 * 17266 * |31 24|23 16|15 8|7 0| 17267 * |----------------+----------------+----------------+----------------| 17268 * | tid | vdev_id | msg_sub_type | msg_type | 17269 * |-------------------------------------------------------------------| 17270 * : (sub-type dependent content) : 17271 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 17272 * Header fields: 17273 * - msg_type 17274 * Bits 7:0 17275 * Purpose: Identifies this as HTT_RX_OFLD_PKT_ERR message 17276 * value: 0x16 (HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR) 17277 * - msg_sub_type 17278 * Bits 15:8 17279 * Purpose: Identifies which type of rx error is reported by this message 17280 * value: htt_rx_ofld_pkt_err_type 17281 * - vdev_id 17282 * Bits 23:16 17283 * Purpose: Identifies which vdev received the erroneous rx frame 17284 * value: 17285 * - tid 17286 * Bits 31:24 17287 * Purpose: Identifies the traffic type of the rx frame 17288 * value: 17289 * 17290 * - The payload fields used if the sub-type == MIC error are shown below. 17291 * Note - MIC err is per MSDU, while PN is per MPDU. 17292 * The FW will discard the whole MPDU if any MSDU within the MPDU is marked 17293 * with MIC err in A-MSDU case, so FW will send only one HTT message 17294 * with the PN of this MPDU attached to indicate MIC err for one MPDU 17295 * instead of sending separate HTT messages for each wrong MSDU within 17296 * the MPDU. 17297 * 17298 * |31 24|23 16|15 8|7 0| 17299 * |----------------+----------------+----------------+----------------| 17300 * | Rsvd | key_id | peer_id | 17301 * |-------------------------------------------------------------------| 17302 * | receiver MAC addr 31:0 | 17303 * |-------------------------------------------------------------------| 17304 * | Rsvd | receiver MAC addr 47:32 | 17305 * |-------------------------------------------------------------------| 17306 * | transmitter MAC addr 31:0 | 17307 * |-------------------------------------------------------------------| 17308 * | Rsvd | transmitter MAC addr 47:32 | 17309 * |-------------------------------------------------------------------| 17310 * | PN 31:0 | 17311 * |-------------------------------------------------------------------| 17312 * | Rsvd | PN 47:32 | 17313 * |-------------------------------------------------------------------| 17314 * - peer_id 17315 * Bits 15:0 17316 * Purpose: identifies which peer is frame is from 17317 * value: 17318 * - key_id 17319 * Bits 23:16 17320 * Purpose: identifies key_id of rx frame 17321 * value: 17322 * - RA_31_0 (receiver MAC addr 31:0) 17323 * Bits 31:0 17324 * Purpose: identifies by MAC address which vdev received the frame 17325 * value: MAC address lower 4 bytes 17326 * - RA_47_32 (receiver MAC addr 47:32) 17327 * Bits 15:0 17328 * Purpose: identifies by MAC address which vdev received the frame 17329 * value: MAC address upper 2 bytes 17330 * - TA_31_0 (transmitter MAC addr 31:0) 17331 * Bits 31:0 17332 * Purpose: identifies by MAC address which peer transmitted the frame 17333 * value: MAC address lower 4 bytes 17334 * - TA_47_32 (transmitter MAC addr 47:32) 17335 * Bits 15:0 17336 * Purpose: identifies by MAC address which peer transmitted the frame 17337 * value: MAC address upper 2 bytes 17338 * - PN_31_0 17339 * Bits 31:0 17340 * Purpose: Identifies pn of rx frame 17341 * value: PN lower 4 bytes 17342 * - PN_47_32 17343 * Bits 15:0 17344 * Purpose: Identifies pn of rx frame 17345 * value: 17346 * TKIP or CCMP: PN upper 2 bytes 17347 * WAPI: PN bytes 6:5 (bytes 15:7 not included in this message) 17348 */ 17349 17350 enum htt_rx_ofld_pkt_err_type { 17351 HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, 17352 HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, 17353 }; 17354 17355 /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */ 17356 #define HTT_RX_OFLD_PKT_ERR_HDR_BYTES 4 17357 17358 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M 0x0000ff00 17359 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S 8 17360 17361 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_M 0x00ff0000 17362 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_S 16 17363 17364 #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000 17365 #define HTT_RX_OFLD_PKT_ERR_TID_S 24 17366 17367 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ 17368 (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ 17369 >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) 17370 #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ 17371 do { \ 17372 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ 17373 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ 17374 } while (0) 17375 17376 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ 17377 (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) 17378 #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ 17379 do { \ 17380 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ 17381 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ 17382 } while (0) 17383 17384 #define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ 17385 (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) 17386 #define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ 17387 do { \ 17388 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ 17389 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ 17390 } while (0) 17391 17392 /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */ 17393 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28 17394 17395 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M 0x0000ffff 17396 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S 0 17397 17398 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M 0x00ff0000 17399 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S 16 17400 17401 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M 0xffffffff 17402 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S 0 17403 17404 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M 0x0000ffff 17405 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S 0 17406 17407 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M 0xffffffff 17408 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S 0 17409 17410 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M 0x0000ffff 17411 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S 0 17412 17413 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M 0xffffffff 17414 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S 0 17415 17416 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff 17417 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0 17418 17419 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ 17420 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ 17421 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) 17422 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ 17423 do { \ 17424 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ 17425 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ 17426 } while (0) 17427 17428 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ 17429 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ 17430 HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) 17431 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ 17432 do { \ 17433 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ 17434 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ 17435 } while (0) 17436 17437 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ 17438 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ 17439 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) 17440 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ 17441 do { \ 17442 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ 17443 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ 17444 } while (0) 17445 17446 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ 17447 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ 17448 HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) 17449 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ 17450 do { \ 17451 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ 17452 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ 17453 } while (0) 17454 17455 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ 17456 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ 17457 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) 17458 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ 17459 do { \ 17460 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ 17461 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ 17462 } while (0) 17463 17464 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ 17465 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ 17466 HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) 17467 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ 17468 do { \ 17469 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ 17470 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ 17471 } while (0) 17472 17473 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ 17474 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ 17475 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) 17476 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ 17477 do { \ 17478 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ 17479 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ 17480 } while (0) 17481 17482 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ 17483 (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ 17484 HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) 17485 #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ 17486 do { \ 17487 HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ 17488 ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ 17489 } while (0) 17490 17491 /** 17492 * @brief target -> host peer rate report message 17493 * 17494 * MSG_TYPE => HTT_T2H_MSG_TYPE_RATE_REPORT 17495 * 17496 * @details 17497 * HTT_T2H_MSG_TYPE_RATE_REPORT message is sent by target to host to indicate the 17498 * justified rate of all the peers. 17499 * 17500 * |31 24|23 16|15 8|7 0| 17501 * |----------------+----------------+----------------+----------------| 17502 * | peer_count | | msg_type | 17503 * |-------------------------------------------------------------------| 17504 * : Payload (variant number of peer rate report) : 17505 * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: 17506 * Header fields: 17507 * - msg_type 17508 * Bits 7:0 17509 * Purpose: Identifies this as HTT_T2H_MSG_TYPE_RATE_REPORT message. 17510 * value: 0x17 (HTT_T2H_MSG_TYPE_RATE_REPORT) 17511 * - reserved 17512 * Bits 15:8 17513 * Purpose: 17514 * value: 17515 * - peer_count 17516 * Bits 31:16 17517 * Purpose: Specify how many peer rate report elements are present in the payload. 17518 * value: 17519 * 17520 * Payload: 17521 * There are variant number of peer rate report follow the first 32 bits. 17522 * The peer rate report is defined as follows. 17523 * 17524 * |31 20|19 16|15 0| 17525 * |-----------------------+---------+---------------------------------|- 17526 * | reserved | phy | peer_id | \ 17527 * |-------------------------------------------------------------------| -> report #0 17528 * | rate | / 17529 * |-----------------------+---------+---------------------------------|- 17530 * | reserved | phy | peer_id | \ 17531 * |-------------------------------------------------------------------| -> report #1 17532 * | rate | / 17533 * |-----------------------+---------+---------------------------------|- 17534 * | reserved | phy | peer_id | \ 17535 * |-------------------------------------------------------------------| -> report #2 17536 * | rate | / 17537 * |-------------------------------------------------------------------|- 17538 * : : 17539 * : : 17540 * : : 17541 * :-------------------------------------------------------------------: 17542 * 17543 * - peer_id 17544 * Bits 15:0 17545 * Purpose: identify the peer 17546 * value: 17547 * - phy 17548 * Bits 19:16 17549 * Purpose: identify which phy is in use 17550 * value: 0=11b, 1=11a/g, 2=11n, 3=11ac. 17551 * Please see enum htt_peer_report_phy_type for detail. 17552 * - reserved 17553 * Bits 31:20 17554 * Purpose: 17555 * value: 17556 * - rate 17557 * Bits 31:0 17558 * Purpose: represent the justified rate of the peer specified by peer_id 17559 * value: 17560 */ 17561 17562 enum htt_peer_rate_report_phy_type { 17563 HTT_PEER_RATE_REPORT_11B = 0, 17564 HTT_PEER_RATE_REPORT_11A_G, 17565 HTT_PEER_RATE_REPORT_11N, 17566 HTT_PEER_RATE_REPORT_11AC, 17567 }; 17568 17569 #define HTT_PEER_RATE_REPORT_SIZE 8 17570 17571 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M 0xffff0000 17572 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S 16 17573 17574 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_M 0x0000ffff 17575 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_S 0 17576 17577 #define HTT_PEER_RATE_REPORT_MSG_PHY_M 0x000f0000 17578 #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16 17579 17580 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \ 17581 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ 17582 >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) 17583 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \ 17584 do { \ 17585 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ 17586 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ 17587 } while (0) 17588 17589 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \ 17590 (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ 17591 >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) 17592 #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \ 17593 do { \ 17594 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ 17595 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ 17596 } while (0) 17597 17598 #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \ 17599 (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ 17600 >> HTT_PEER_RATE_REPORT_MSG_PHY_S) 17601 #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \ 17602 do { \ 17603 HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ 17604 ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ 17605 } while (0) 17606 17607 /** 17608 * @brief target -> host flow pool map message 17609 * 17610 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_MAP 17611 * 17612 * @details 17613 * HTT_T2H_MSG_TYPE_FLOW_POOL_MAP message is sent by the target when setting up 17614 * a flow of descriptors. 17615 * 17616 * This message is in TLV format and indicates the parameters to be setup a 17617 * flow in the host. Each entry indicates that a particular flow ID is ready to 17618 * receive descriptors from a specified pool. 17619 * 17620 * The message would appear as follows: 17621 * 17622 * |31 24|23 16|15 8|7 0| 17623 * |----------------+----------------+----------------+----------------| 17624 * header | reserved | num_flows | msg_type | 17625 * |-------------------------------------------------------------------| 17626 * | | 17627 * : payload : 17628 * | | 17629 * |-------------------------------------------------------------------| 17630 * 17631 * The header field is one DWORD long and is interpreted as follows: 17632 * b'0:7 - msg_type: Set to 0x18 (HTT_T2H_MSG_TYPE_FLOW_POOL_MAP) 17633 * b'8-15 - num_flows: This will indicate the number of flows being setup in 17634 * this message 17635 * b'16-31 - reserved: These bits are reserved for future use 17636 * 17637 * Payload: 17638 * The payload would contain multiple objects of the following structure. Each 17639 * object represents a flow. 17640 * 17641 * |31 24|23 16|15 8|7 0| 17642 * |----------------+----------------+----------------+----------------| 17643 * header | reserved | num_flows | msg_type | 17644 * |-------------------------------------------------------------------| 17645 * payload0| flow_type | 17646 * |-------------------------------------------------------------------| 17647 * | flow_id | 17648 * |-------------------------------------------------------------------| 17649 * | reserved0 | flow_pool_id | 17650 * |-------------------------------------------------------------------| 17651 * | reserved1 | flow_pool_size | 17652 * |-------------------------------------------------------------------| 17653 * | reserved2 | 17654 * |-------------------------------------------------------------------| 17655 * payload1| flow_type | 17656 * |-------------------------------------------------------------------| 17657 * | flow_id | 17658 * |-------------------------------------------------------------------| 17659 * | reserved0 | flow_pool_id | 17660 * |-------------------------------------------------------------------| 17661 * | reserved1 | flow_pool_size | 17662 * |-------------------------------------------------------------------| 17663 * | reserved2 | 17664 * |-------------------------------------------------------------------| 17665 * | . | 17666 * | . | 17667 * | . | 17668 * |-------------------------------------------------------------------| 17669 * 17670 * Each payload is 5 DWORDS long and is interpreted as follows: 17671 * dword0 - b'0:31 - flow_type: This indicates the type of the entity to which 17672 * this flow is associated. It can be VDEV, peer, 17673 * or tid (AC). Based on enum htt_flow_type. 17674 * 17675 * dword1 - b'0:31 - flow_id: Identifier for the flow corresponding to this 17676 * object. For flow_type vdev it is set to the 17677 * vdevid, for peer it is peerid and for tid, it is 17678 * tid_num. 17679 * 17680 * dword2 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being used 17681 * in the host for this flow 17682 * b'16:31 - reserved0: This field in reserved for the future. In case 17683 * we have a hierarchical implementation (HCM) of 17684 * pools, it can be used to indicate the ID of the 17685 * parent-pool. 17686 * 17687 * dword3 - b'0:15 - flow_pool_size: Size of the pool in number of descriptors. 17688 * Descriptors for this flow will be 17689 * allocated from this pool in the host. 17690 * b'16:31 - reserved1: This field in reserved for the future. In case 17691 * we have a hierarchical implementation of pools, 17692 * it can be used to indicate the max number of 17693 * descriptors in the pool. The b'0:15 can be used 17694 * to indicate min number of descriptors in the 17695 * HCM scheme. 17696 * 17697 * dword4 - b'0:31 - reserved2: This field in reserved for the future. In case 17698 * we have a hierarchical implementation of pools, 17699 * b'0:15 can be used to indicate the 17700 * priority-based borrowing (PBB) threshold of 17701 * the flow's pool. The b'16:31 are still left 17702 * reserved. 17703 */ 17704 17705 enum htt_flow_type { 17706 FLOW_TYPE_VDEV = 0, 17707 /* Insert new flow types above this line */ 17708 }; 17709 17710 PREPACK struct htt_flow_pool_map_payload_t { 17711 A_UINT32 flow_type; 17712 A_UINT32 flow_id; 17713 A_UINT32 flow_pool_id:16, 17714 reserved0:16; 17715 A_UINT32 flow_pool_size:16, 17716 reserved1:16; 17717 A_UINT32 reserved2; 17718 } POSTPACK; 17719 17720 #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32)) 17721 17722 #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \ 17723 (sizeof(struct htt_flow_pool_map_payload_t)) 17724 17725 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00 17726 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8 17727 17728 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_M 0xffffffff 17729 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_S 0 17730 17731 #define HTT_FLOW_POOL_MAP_FLOW_ID_M 0xffffffff 17732 #define HTT_FLOW_POOL_MAP_FLOW_ID_S 0 17733 17734 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M 0x0000ffff 17735 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S 0 17736 17737 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff 17738 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0 17739 17740 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ 17741 (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) 17742 17743 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ 17744 (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) 17745 17746 #define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ 17747 (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) 17748 17749 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ 17750 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ 17751 HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) 17752 17753 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ 17754 (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ 17755 HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) 17756 17757 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ 17758 do { \ 17759 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ 17760 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ 17761 } while (0) 17762 17763 #define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ 17764 do { \ 17765 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ 17766 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ 17767 } while (0) 17768 17769 #define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ 17770 do { \ 17771 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ 17772 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ 17773 } while (0) 17774 17775 #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ 17776 do { \ 17777 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ 17778 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ 17779 } while (0) 17780 17781 #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ 17782 do { \ 17783 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ 17784 ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ 17785 } while (0) 17786 17787 /** 17788 * @brief target -> host flow pool unmap message 17789 * 17790 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP 17791 * 17792 * @details 17793 * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP message is sent by the target when tearing 17794 * down a flow of descriptors. 17795 * This message indicates that for the flow (whose ID is provided) is wanting 17796 * to stop receiving descriptors. This flow ID corresponds to the ID of the 17797 * pool of descriptors from where descriptors are being allocated for this 17798 * flow. When a flow (and its pool) are unmapped, all the child-pools will also 17799 * be unmapped by the host. 17800 * 17801 * The message would appear as follows: 17802 * 17803 * |31 24|23 16|15 8|7 0| 17804 * |----------------+----------------+----------------+----------------| 17805 * | reserved0 | msg_type | 17806 * |-------------------------------------------------------------------| 17807 * | flow_type | 17808 * |-------------------------------------------------------------------| 17809 * | flow_id | 17810 * |-------------------------------------------------------------------| 17811 * | reserved1 | flow_pool_id | 17812 * |-------------------------------------------------------------------| 17813 * 17814 * The message is interpreted as follows: 17815 * dword0 - b'0:7 - msg_type: This will be set to 0x19 17816 * (HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP) 17817 * b'8:31 - reserved0: Reserved for future use 17818 * 17819 * dword1 - b'0:31 - flow_type: This indicates the type of the entity to which 17820 * this flow is associated. It can be VDEV, peer, 17821 * or tid (AC). Based on enum htt_flow_type. 17822 * 17823 * dword2 - b'0:31 - flow_id: Identifier for the flow corresponding to this 17824 * object. For flow_type vdev it is set to the 17825 * vdevid, for peer it is peerid and for tid, it is 17826 * tid_num. 17827 * 17828 * dword3 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being 17829 * used in the host for this flow 17830 * b'16:31 - reserved0: This field in reserved for the future. 17831 * 17832 */ 17833 17834 PREPACK struct htt_flow_pool_unmap_t { 17835 A_UINT32 msg_type:8, 17836 reserved0:24; 17837 A_UINT32 flow_type; 17838 A_UINT32 flow_id; 17839 A_UINT32 flow_pool_id:16, 17840 reserved1:16; 17841 } POSTPACK; 17842 17843 #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t)) 17844 17845 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M 0xffffffff 17846 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S 0 17847 17848 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_M 0xffffffff 17849 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_S 0 17850 17851 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff 17852 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0 17853 17854 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ 17855 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ 17856 HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) 17857 17858 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ 17859 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) 17860 17861 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ 17862 (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ 17863 HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) 17864 17865 #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ 17866 do { \ 17867 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ 17868 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ 17869 } while (0) 17870 17871 #define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ 17872 do { \ 17873 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ 17874 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ 17875 } while (0) 17876 17877 #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ 17878 do { \ 17879 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ 17880 ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ 17881 } while (0) 17882 17883 17884 /** 17885 * @brief target -> host SRING setup done message 17886 * 17887 * MSG_TYPE => HTT_T2H_MSG_TYPE_SRING_SETUP_DONE 17888 * 17889 * @details 17890 * HTT_T2H_MSG_TYPE_SRING_SETUP_DONE message is sent by the target when 17891 * SRNG ring setup is done 17892 * 17893 * This message indicates whether the last setup operation is successful. 17894 * It will be sent to host when host set respose_required bit in 17895 * HTT_H2T_MSG_TYPE_SRING_SETUP. 17896 * The message would appear as follows: 17897 * 17898 * |31 24|23 16|15 8|7 0| 17899 * |--------------- +----------------+----------------+----------------| 17900 * | setup_status | ring_id | pdev_id | msg_type | 17901 * |-------------------------------------------------------------------| 17902 * 17903 * The message is interpreted as follows: 17904 * dword0 - b'0:7 - msg_type: This will be set to 0x1a 17905 * (HTT_T2H_MSG_TYPE_SRING_SETUP_DONE) 17906 * b'8:15 - pdev_id: 17907 * 0 (for rings at SOC/UMAC level), 17908 * 1/2/3 mac id (for rings at LMAC level) 17909 * b'16:23 - ring_id: Identify the ring which is set up 17910 * More details can be got from enum htt_srng_ring_id 17911 * b'24:31 - setup_status: Indicate status of setup operation 17912 * Refer to htt_ring_setup_status 17913 */ 17914 17915 PREPACK struct htt_sring_setup_done_t { 17916 A_UINT32 msg_type: 8, 17917 pdev_id: 8, 17918 ring_id: 8, 17919 setup_status: 8; 17920 } POSTPACK; 17921 17922 enum htt_ring_setup_status { 17923 htt_ring_setup_status_ok = 0, 17924 htt_ring_setup_status_error, 17925 }; 17926 17927 #define HTT_SRING_SETUP_DONE_SZ (sizeof(struct htt_sring_setup_done_t)) 17928 17929 #define HTT_SRING_SETUP_DONE_PDEV_ID_M 0x0000ff00 17930 #define HTT_SRING_SETUP_DONE_PDEV_ID_S 8 17931 #define HTT_SRING_SETUP_DONE_PDEV_ID_GET(_var) \ 17932 (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \ 17933 HTT_SRING_SETUP_DONE_PDEV_ID_S) 17934 #define HTT_SRING_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 17935 do { \ 17936 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \ 17937 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 17938 } while (0) 17939 17940 #define HTT_SRING_SETUP_DONE_RING_ID_M 0x00ff0000 17941 #define HTT_SRING_SETUP_DONE_RING_ID_S 16 17942 #define HTT_SRING_SETUP_DONE_RING_ID_GET(_var) \ 17943 (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \ 17944 HTT_SRING_SETUP_DONE_RING_ID_S) 17945 #define HTT_SRING_SETUP_DONE_RING_ID_SET(_var, _val) \ 17946 do { \ 17947 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \ 17948 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \ 17949 } while (0) 17950 17951 #define HTT_SRING_SETUP_DONE_STATUS_M 0xff000000 17952 #define HTT_SRING_SETUP_DONE_STATUS_S 24 17953 #define HTT_SRING_SETUP_DONE_STATUS_GET(_var) \ 17954 (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \ 17955 HTT_SRING_SETUP_DONE_STATUS_S) 17956 #define HTT_SRING_SETUP_DONE_STATUS_SET(_var, _val) \ 17957 do { \ 17958 HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \ 17959 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \ 17960 } while (0) 17961 17962 17963 /** 17964 * @brief target -> flow map flow info 17965 * 17966 * MSG_TYPE => HTT_T2H_MSG_TYPE_MAP_FLOW_INFO 17967 * 17968 * @details 17969 * HTT TX map flow entry with tqm flow pointer 17970 * Sent from firmware to host to add tqm flow pointer in corresponding 17971 * flow search entry. Flow metadata is replayed back to host as part of this 17972 * struct to enable host to find the specific flow search entry 17973 * 17974 * The message would appear as follows: 17975 * 17976 * |31 28|27 18|17 14|13 8|7 0| 17977 * |-------+------------------------------------------+----------------| 17978 * | rsvd0 | fse_hsh_idx | msg_type | 17979 * |-------------------------------------------------------------------| 17980 * | rsvd1 | tid | peer_id | 17981 * |-------------------------------------------------------------------| 17982 * | tqm_flow_pntr_lo | 17983 * |-------------------------------------------------------------------| 17984 * | tqm_flow_pntr_hi | 17985 * |-------------------------------------------------------------------| 17986 * | fse_meta_data | 17987 * |-------------------------------------------------------------------| 17988 * 17989 * The message is interpreted as follows: 17990 * 17991 * dword0 - b'0:7 - msg_type: This will be set to 0x1b 17992 * (HTT_T2H_MSG_TYPE_MAP_FLOW_INFO) 17993 * 17994 * dword0 - b'8:27 - fse_hsh_idx: Flow search table index provided by host 17995 * for this flow entry 17996 * 17997 * dword0 - b'28:31 - rsvd0: Reserved for future use 17998 * 17999 * dword1 - b'0:13 - peer_id: Software peer id given by host during association 18000 * 18001 * dword1 - b'14:17 - tid 18002 * 18003 * dword1 - b'18:31 - rsvd1: Reserved for future use 18004 * 18005 * dword2 - b'0:31 - tqm_flow_pntr_lo: Lower 32 bits of TQM flow pointer 18006 * 18007 * dword3 - b'0:31 - tqm_flow_pntr_hi: Higher 32 bits of TQM flow pointer 18008 * 18009 * dword4 - b'0:31 - fse_meta_data: Replay back TX flow search metadata 18010 * given by host 18011 */ 18012 PREPACK struct htt_tx_map_flow_info { 18013 A_UINT32 18014 msg_type: 8, 18015 fse_hsh_idx: 20, 18016 rsvd0: 4; 18017 A_UINT32 18018 peer_id: 14, 18019 tid: 4, 18020 rsvd1: 14; 18021 A_UINT32 tqm_flow_pntr_lo; 18022 A_UINT32 tqm_flow_pntr_hi; 18023 struct htt_tx_flow_metadata fse_meta_data; 18024 } POSTPACK; 18025 18026 /* DWORD 0 */ 18027 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M 0x0fffff00 18028 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S 8 18029 18030 /* DWORD 1 */ 18031 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_M 0x00003fff 18032 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_S 0 18033 #define HTT_TX_MAP_FLOW_INFO_TID_M 0x0003c000 18034 #define HTT_TX_MAP_FLOW_INFO_TID_S 14 18035 18036 /* DWORD 0 */ 18037 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_GET(_var) \ 18038 (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \ 18039 HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S) 18040 #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_SET(_var, _val) \ 18041 do { \ 18042 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \ 18043 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \ 18044 } while (0) 18045 18046 /* DWORD 1 */ 18047 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_GET(_var) \ 18048 (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \ 18049 HTT_TX_MAP_FLOW_INFO_PEER_ID_S) 18050 #define HTT_TX_MAP_FLOW_INFO_PEER_ID_SET(_var, _val) \ 18051 do { \ 18052 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \ 18053 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \ 18054 } while (0) 18055 18056 #define HTT_TX_MAP_FLOW_INFO_TID_GET(_var) \ 18057 (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \ 18058 HTT_TX_MAP_FLOW_INFO_TID_S) 18059 #define HTT_TX_MAP_FLOW_INFO_TID_SET(_var, _val) \ 18060 do { \ 18061 HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \ 18062 ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \ 18063 } while (0) 18064 18065 18066 /* 18067 * htt_dbg_ext_stats_status - 18068 * present - The requested stats have been delivered in full. 18069 * This indicates that either the stats information was contained 18070 * in its entirety within this message, or else this message 18071 * completes the delivery of the requested stats info that was 18072 * partially delivered through earlier STATS_CONF messages. 18073 * partial - The requested stats have been delivered in part. 18074 * One or more subsequent STATS_CONF messages with the same 18075 * cookie value will be sent to deliver the remainder of the 18076 * information. 18077 * error - The requested stats could not be delivered, for example due 18078 * to a shortage of memory to construct a message holding the 18079 * requested stats. 18080 * invalid - The requested stat type is either not recognized, or the 18081 * target is configured to not gather the stats type in question. 18082 */ 18083 enum htt_dbg_ext_stats_status { 18084 HTT_DBG_EXT_STATS_STATUS_PRESENT = 0, 18085 HTT_DBG_EXT_STATS_STATUS_PARTIAL = 1, 18086 HTT_DBG_EXT_STATS_STATUS_ERROR = 2, 18087 HTT_DBG_EXT_STATS_STATUS_INVALID = 3, 18088 }; 18089 18090 /** 18091 * @brief target -> host ppdu stats upload 18092 * 18093 * MSG_TYPE => HTT_T2H_MSG_TYPE_PPDU_STATS_IND 18094 * 18095 * @details 18096 * The following field definitions describe the format of the HTT target 18097 * to host ppdu stats indication message. 18098 * 18099 * 18100 * |31 24|23 16|15 12|11 10|9 8|7 0 | 18101 * |-----------------------------+-------+-------+--------+---------------| 18102 * | payload_size | rsvd |pdev_id|mac_id | msg type | 18103 * |-------------+---------------+-------+-------+--------+---------------| 18104 * | tgt_private | ppdu_id | 18105 * |-------------+--------------------------------------------------------| 18106 * | Timestamp in us | 18107 * |----------------------------------------------------------------------| 18108 * | reserved | 18109 * |----------------------------------------------------------------------| 18110 * | type-specific stats info | 18111 * | (see htt_ppdu_stats.h) | 18112 * |----------------------------------------------------------------------| 18113 * Header fields: 18114 * - MSG_TYPE 18115 * Bits 7:0 18116 * Purpose: Identifies this is a PPDU STATS indication 18117 * message. 18118 * Value: 0x1d (HTT_T2H_MSG_TYPE_PPDU_STATS_IND) 18119 * - mac_id 18120 * Bits 9:8 18121 * Purpose: mac_id of this ppdu_id 18122 * Value: 0-3 18123 * - pdev_id 18124 * Bits 11:10 18125 * Purpose: pdev_id of this ppdu_id 18126 * Value: 0-3 18127 * 0 (for rings at SOC level), 18128 * 1/2/3 PDEV -> 0/1/2 18129 * - payload_size 18130 * Bits 31:16 18131 * Purpose: total tlv size 18132 * Value: payload_size in bytes 18133 */ 18134 #define HTT_T2H_PPDU_STATS_IND_HDR_SIZE 16 18135 18136 #define HTT_T2H_PPDU_STATS_MAC_ID_M 0x00000300 18137 #define HTT_T2H_PPDU_STATS_MAC_ID_S 8 18138 18139 #define HTT_T2H_PPDU_STATS_PDEV_ID_M 0x00000C00 18140 #define HTT_T2H_PPDU_STATS_PDEV_ID_S 10 18141 18142 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 18143 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 18144 18145 #define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF 18146 #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 18147 /* bits 31:24 are used by the target for internal purposes */ 18148 18149 #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ 18150 do { \ 18151 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_MAC_ID, value); \ 18152 (word) |= (value) << HTT_T2H_PPDU_STATS_MAC_ID_S; \ 18153 } while (0) 18154 #define HTT_T2H_PPDU_STATS_MAC_ID_GET(word) \ 18155 (((word) & HTT_T2H_PPDU_STATS_MAC_ID_M) >> \ 18156 HTT_T2H_PPDU_STATS_MAC_ID_S) 18157 18158 #define HTT_T2H_PPDU_STATS_PDEV_ID_SET(word, value) \ 18159 do { \ 18160 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PDEV_ID, value); \ 18161 (word) |= (value) << HTT_T2H_PPDU_STATS_PDEV_ID_S; \ 18162 } while (0) 18163 #define HTT_T2H_PPDU_STATS_PDEV_ID_GET(word) \ 18164 (((word) & HTT_T2H_PPDU_STATS_PDEV_ID_M) >> \ 18165 HTT_T2H_PPDU_STATS_PDEV_ID_S) 18166 18167 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_SET(word, value) \ 18168 do { \ 18169 HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PAYLOAD_SIZE, value); \ 18170 (word) |= (value) << HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S; \ 18171 } while (0) 18172 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_GET(word) \ 18173 (((word) & HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M) >> \ 18174 HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S) 18175 18176 #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ 18177 do { \ 18178 /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ 18179 (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ 18180 } while (0) 18181 #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ 18182 (((word) & HTT_T2H_PPDU_STATS_PPDU_ID_M) >> \ 18183 HTT_T2H_PPDU_STATS_PPDU_ID_S) 18184 18185 /* htt_t2h_ppdu_stats_ind_hdr_t 18186 * This struct contains the fields within the header of the 18187 * HTT_T2H_PPDU_STATS_IND message, preceding the type-specific 18188 * stats info. 18189 * This struct assumes little-endian layout, and thus is only 18190 * suitable for use within processors known to be little-endian 18191 * (such as the target). 18192 * In contrast, the above macros provide endian-portable methods 18193 * to get and set the bitfields within this PPDU_STATS_IND header. 18194 */ 18195 typedef struct { 18196 A_UINT32 msg_type: 8, /* bits 7:0 */ 18197 mac_id: 2, /* bits 9:8 */ 18198 pdev_id: 2, /* bits 11:10 */ 18199 reserved1: 4, /* bits 15:12 */ 18200 payload_size: 16; /* bits 31:16 */ 18201 A_UINT32 ppdu_id; 18202 A_UINT32 timestamp_us; 18203 A_UINT32 reserved2; 18204 } htt_t2h_ppdu_stats_ind_hdr_t; 18205 18206 /** 18207 * @brief target -> host extended statistics upload 18208 * 18209 * MSG_TYPE => HTT_T2H_MSG_TYPE_EXT_STATS_CONF 18210 * 18211 * @details 18212 * The following field definitions describe the format of the HTT target 18213 * to host stats upload confirmation message. 18214 * The message contains a cookie echoed from the HTT host->target stats 18215 * upload request, which identifies which request the confirmation is 18216 * for, and a single stats can span over multiple HTT stats indication 18217 * due to the HTT message size limitation so every HTT ext stats indication 18218 * will have tag-length-value stats information elements. 18219 * The tag-length header for each HTT stats IND message also includes a 18220 * status field, to indicate whether the request for the stat type in 18221 * question was fully met, partially met, unable to be met, or invalid 18222 * (if the stat type in question is disabled in the target). 18223 * A Done bit 1's indicate the end of the of stats info elements. 18224 * 18225 * 18226 * |31 16|15 12|11|10 8|7 5|4 0| 18227 * |--------------------------------------------------------------| 18228 * | reserved | msg type | 18229 * |--------------------------------------------------------------| 18230 * | cookie LSBs | 18231 * |--------------------------------------------------------------| 18232 * | cookie MSBs | 18233 * |--------------------------------------------------------------| 18234 * | stats entry length | rsvd | D| S | stat type | 18235 * |--------------------------------------------------------------| 18236 * | type-specific stats info | 18237 * | (see htt_stats.h) | 18238 * |--------------------------------------------------------------| 18239 * Header fields: 18240 * - MSG_TYPE 18241 * Bits 7:0 18242 * Purpose: Identifies this is a extended statistics upload confirmation 18243 * message. 18244 * Value: 0x1c (HTT_T2H_MSG_TYPE_EXT_STATS_CONF) 18245 * - COOKIE_LSBS 18246 * Bits 31:0 18247 * Purpose: Provide a mechanism to match a target->host stats confirmation 18248 * message with its preceding host->target stats request message. 18249 * Value: LSBs of the opaque cookie specified by the host-side requestor 18250 * - COOKIE_MSBS 18251 * Bits 31:0 18252 * Purpose: Provide a mechanism to match a target->host stats confirmation 18253 * message with its preceding host->target stats request message. 18254 * Value: MSBs of the opaque cookie specified by the host-side requestor 18255 * 18256 * Stats Information Element tag-length header fields: 18257 * - STAT_TYPE 18258 * Bits 7:0 18259 * Purpose: identifies the type of statistics info held in the 18260 * following information element 18261 * Value: htt_dbg_ext_stats_type 18262 * - STATUS 18263 * Bits 10:8 18264 * Purpose: indicate whether the requested stats are present 18265 * Value: htt_dbg_ext_stats_status 18266 * - DONE 18267 * Bits 11 18268 * Purpose: 18269 * Indicates the completion of the stats entry, this will be the last 18270 * stats conf HTT segment for the requested stats type. 18271 * Value: 18272 * 0 -> the stats retrieval is ongoing 18273 * 1 -> the stats retrieval is complete 18274 * - LENGTH 18275 * Bits 31:16 18276 * Purpose: indicate the stats information size 18277 * Value: This field specifies the number of bytes of stats information 18278 * that follows the element tag-length header. 18279 * It is expected but not required that this length is a multiple of 18280 * 4 bytes. 18281 */ 18282 #define HTT_T2H_EXT_STATS_COOKIE_SIZE 8 18283 18284 #define HTT_T2H_EXT_STATS_CONF_HDR_SIZE 4 18285 18286 #define HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 4 18287 18288 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M 0x000000ff 18289 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S 0 18290 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M 0x00000700 18291 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S 8 18292 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_M 0x00000800 18293 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_S 11 18294 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M 0xffff0000 18295 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S 16 18296 18297 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_SET(word, value) \ 18298 do { \ 18299 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_TYPE, value); \ 18300 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S; \ 18301 } while (0) 18302 #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_GET(word) \ 18303 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M) >> \ 18304 HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S) 18305 18306 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_SET(word, value) \ 18307 do { \ 18308 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_STATUS, value); \ 18309 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S; \ 18310 } while (0) 18311 #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_GET(word) \ 18312 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M) >> \ 18313 HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S) 18314 18315 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_SET(word, value) \ 18316 do { \ 18317 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_DONE, value); \ 18318 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_DONE_S; \ 18319 } while (0) 18320 #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_GET(word) \ 18321 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_DONE_M) >> \ 18322 HTT_T2H_EXT_STATS_CONF_TLV_DONE_S) 18323 18324 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_SET(word, value) \ 18325 do { \ 18326 HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_LENGTH, value); \ 18327 (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S; \ 18328 } while (0) 18329 #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_GET(word) \ 18330 (((word) & HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M) >> \ 18331 HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S) 18332 18333 18334 /** 18335 * @brief target -> host streaming statistics upload 18336 * 18337 * MSG_TYPE => HTT_T2H_MSG_TYPE_STREAMING_STATS_IND 18338 * 18339 * @details 18340 * The following field definitions describe the format of the HTT target 18341 * to host streaming stats upload indication message. 18342 * The host can use a STREAMING_STATS_REQ message to enable the target to 18343 * produce an ongoing series of STREAMING_STATS_IND messages, and can also 18344 * use the STREAMING_STATS_REQ message to halt the target's production of 18345 * STREAMING_STATS_IND messages. 18346 * The STREAMING_STATS_IND message contains a payload of TLVs containing 18347 * the stats enabled by the host's STREAMING_STATS_REQ message. 18348 * 18349 * |31 8|7 0| 18350 * |--------------------------------------------------------------| 18351 * | reserved | msg type | 18352 * |--------------------------------------------------------------| 18353 * | type-specific stats info | 18354 * | (see htt_stats.h) | 18355 * |--------------------------------------------------------------| 18356 * Header fields: 18357 * - MSG_TYPE 18358 * Bits 7:0 18359 * Purpose: Identifies this as a streaming statistics upload indication 18360 * message. 18361 * Value: 0x2f (HTT_T2H_MSG_TYPE_STREAMING_STATS_IND) 18362 */ 18363 18364 #define HTT_T2H_STREAMING_STATS_IND_HDR_SIZE 4 18365 18366 18367 typedef enum { 18368 HTT_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */ 18369 HTT_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */ 18370 HTT_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */ 18371 HTT_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ 18372 HTT_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ 18373 HTT_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ 18374 /* Reserved from 128 - 255 for target internal use.*/ 18375 HTT_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ 18376 } HTT_PEER_TYPE; 18377 18378 /** macro to convert MAC address from char array to HTT word format */ 18379 #define HTT_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr, phtt_mac_addr) do { \ 18380 (phtt_mac_addr)->mac_addr31to0 = \ 18381 (((c_macaddr)[0] << 0) | \ 18382 ((c_macaddr)[1] << 8) | \ 18383 ((c_macaddr)[2] << 16) | \ 18384 ((c_macaddr)[3] << 24)); \ 18385 (phtt_mac_addr)->mac_addr47to32 = ((c_macaddr)[4] | ((c_macaddr)[5] << 8));\ 18386 } while (0) 18387 18388 /** 18389 * @brief target -> host monitor mac header indication message 18390 * 18391 * MSG_TYPE => HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND 18392 * 18393 * @details 18394 * The following diagram shows the format of the monitor mac header message 18395 * sent from the target to the host. 18396 * This message is primarily sent when promiscuous rx mode is enabled. 18397 * One message is sent per rx PPDU. 18398 * 18399 * |31 24|23 16|15 8|7 0| 18400 * |-------------------------------------------------------------| 18401 * | peer_id | reserved0 | msg_type | 18402 * |-------------------------------------------------------------| 18403 * | reserved1 | num_mpdu | 18404 * |-------------------------------------------------------------| 18405 * | struct hw_rx_desc | 18406 * | (see wal_rx_desc.h) | 18407 * |-------------------------------------------------------------| 18408 * | struct ieee80211_frame_addr4 | 18409 * | (see ieee80211_defs.h) | 18410 * |-------------------------------------------------------------| 18411 * | struct ieee80211_frame_addr4 | 18412 * | (see ieee80211_defs.h) | 18413 * |-------------------------------------------------------------| 18414 * | ...... | 18415 * |-------------------------------------------------------------| 18416 * 18417 * Header fields: 18418 * - msg_type 18419 * Bits 7:0 18420 * Purpose: Identifies this is a monitor mac header indication message. 18421 * Value: 0x20 (HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND) 18422 * - peer_id 18423 * Bits 31:16 18424 * Purpose: Software peer id given by host during association, 18425 * During promiscuous mode, the peer ID will be invalid (0xFF) 18426 * for rx PPDUs received from unassociated peers. 18427 * Value: peer ID (for associated peers) or 0xFF (for unassociated peers) 18428 * - num_mpdu 18429 * Bits 15:0 18430 * Purpose: The number of MPDU frame headers (struct ieee80211_frame_addr4) 18431 * delivered within the message. 18432 * Value: 1 to 32 18433 * num_mpdu is limited to a maximum value of 32, due to buffer 18434 * size limits. For PPDUs with more than 32 MPDUs, only the 18435 * ieee80211_frame_addr4 headers from the first 32 MPDUs within 18436 * the PPDU will be provided. 18437 */ 18438 #define HTT_T2H_MONITOR_MAC_HEADER_IND_HDR_SIZE 8 18439 18440 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M 0xFFFF0000 18441 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S 16 18442 18443 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M 0x0000FFFF 18444 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S 0 18445 18446 18447 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_SET(word, value) \ 18448 do { \ 18449 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_PEER_ID, value); \ 18450 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S; \ 18451 } while (0) 18452 #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_GET(word) \ 18453 (((word) & HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M) >> \ 18454 HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S) 18455 18456 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_SET(word, value) \ 18457 do { \ 18458 HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU, value); \ 18459 (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S; \ 18460 } while (0) 18461 #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_GET(word) \ 18462 (((word) & HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M) >> \ 18463 HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S) 18464 18465 /** 18466 * @brief target -> host flow pool resize Message 18467 * 18468 * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE 18469 * 18470 * @details 18471 * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE message is sent by the target when 18472 * the flow pool associated with the specified ID is resized 18473 * 18474 * The message would appear as follows: 18475 * 18476 * |31 16|15 8|7 0| 18477 * |---------------------------------+----------------+----------------| 18478 * | reserved0 | Msg type | 18479 * |-------------------------------------------------------------------| 18480 * | flow pool new size | flow pool ID | 18481 * |-------------------------------------------------------------------| 18482 * 18483 * The message is interpreted as follows: 18484 * b'0:7 - msg_type: This will be set to 0x21 18485 * (HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE) 18486 * 18487 * b'0:15 - flow pool ID: Existing flow pool ID 18488 * 18489 * b'16:31 - flow pool new size: new pool size for existing flow pool ID 18490 * 18491 */ 18492 18493 PREPACK struct htt_flow_pool_resize_t { 18494 A_UINT32 msg_type:8, 18495 reserved0:24; 18496 A_UINT32 flow_pool_id:16, 18497 flow_pool_new_size:16; 18498 } POSTPACK; 18499 18500 #define HTT_FLOW_POOL_RESIZE_SZ (sizeof(struct htt_flow_pool_resize_t)) 18501 18502 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M 0x0000ffff 18503 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S 0 18504 18505 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M 0xffff0000 18506 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S 16 18507 18508 18509 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_GET(_var) \ 18510 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M) >> \ 18511 HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S) 18512 18513 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_SET(_var, _val) \ 18514 do { \ 18515 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID, _val); \ 18516 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)); \ 18517 } while (0) 18518 18519 18520 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_GET(_var) \ 18521 (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M) >> \ 18522 HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S) 18523 18524 #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_SET(_var, _val) \ 18525 do { \ 18526 HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE, _val); \ 18527 ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \ 18528 } while (0) 18529 18530 18531 18532 #define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC 18533 #define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */ 18534 #define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4 18535 #define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \ 18536 (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES) 18537 #define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4 18538 #define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4 18539 /* 18540 * The read and write indices point to the data within the host buffer. 18541 * Because the first 4 bytes of the host buffer is used for the read index and 18542 * the next 4 bytes for the write index, the data itself starts at offset 8. 18543 * The read index and write index are the byte offsets from the base of the 18544 * meta-data buffer, and thus have a minimum value of 8 rather than 0. 18545 * Refer the ASCII text picture below. 18546 */ 18547 #define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \ 18548 (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \ 18549 HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES) 18550 18551 /* 18552 *************************************************************************** 18553 * 18554 * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 18555 * 18556 *************************************************************************** 18557 * 18558 * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used 18559 * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by 18560 * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is 18561 * written into the Host memory region mentioned below. 18562 * 18563 * Read index is updated by the Host. At any point of time, the read index will 18564 * indicate the index that will next be read by the Host. The read index is 18565 * in units of bytes offset from the base of the meta-data buffer. 18566 * 18567 * Write index is updated by the FW. At any point of time, the write index will 18568 * indicate from where the FW can start writing any new data. The write index is 18569 * in units of bytes offset from the base of the meta-data buffer. 18570 * 18571 * If the Host is not fast enough in reading the CFR data, any new capture data 18572 * would be dropped if there is no space left to write the new captures. 18573 * 18574 * The last 4 bytes of the memory region will have the magic pattern 18575 * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does 18576 * not overrun the host buffer. 18577 * 18578 * ,--------------------. read and write indices store the 18579 * | | byte offset from the base of the 18580 * | ,--------+--------. meta-data buffer to the next 18581 * | | | | location within the data buffer 18582 * | | v v that will be read / written 18583 * ************************************************************************ 18584 * * Read * Write * * Magic * 18585 * * index * index * CFR data1 ...... CFR data N * pattern * 18586 * * (4 bytes) * (4 bytes) * * (4 bytes)* 18587 * ************************************************************************ 18588 * |<---------- data buffer ---------->| 18589 * 18590 * |<----------------- meta-data buffer allocated in Host ----------------| 18591 * 18592 * Note: 18593 * - Considering the 4 bytes needed to store the Read index (R) and the 18594 * Write index (W), the initial value is as follows: 18595 * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX 18596 * - Buffer empty condition: 18597 * R = W 18598 * 18599 * Regarding CFR data format: 18600 * -------------------------- 18601 * 18602 * Each CFR tone is stored in HW as 16-bits with the following format: 18603 * {bits[15:12], bits[11:6], bits[5:0]} = 18604 * {unsigned exponent (4 bits), 18605 * signed mantissa_real (6 bits), 18606 * signed mantissa_imag (6 bits)} 18607 * 18608 * CFR_real = mantissa_real * 2^(exponent-5) 18609 * CFR_imag = mantissa_imag * 2^(exponent-5) 18610 * 18611 * 18612 * The CFR data is written to the 16-bit unsigned output array (buff) in 18613 * ascending tone order. For example, the Legacy20 CFR is output as follows: 18614 * 18615 * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]] 18616 * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]] 18617 * . 18618 * . 18619 * . 18620 * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]] 18621 * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]] 18622 */ 18623 18624 /* Bandwidth of peer CFR captures */ 18625 typedef enum { 18626 HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0, 18627 HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1, 18628 HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, 18629 HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, 18630 HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, 18631 HTT_PEER_CFR_CAPTURE_BW_MAX, 18632 } HTT_PEER_CFR_CAPTURE_BW; 18633 18634 /* Mode of the peer CFR captures. The type of RX frame for which the CFR 18635 * was captured 18636 */ 18637 typedef enum { 18638 HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0, 18639 HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1, 18640 HTT_PEER_CFR_CAPTURE_MODE_HT = 2, 18641 HTT_PEER_CFR_CAPTURE_MODE_VHT = 3, 18642 HTT_PEER_CFR_CAPTURE_MODE_MAX, 18643 } HTT_PEER_CFR_CAPTURE_MODE; 18644 18645 typedef enum { 18646 /* This message type is currently used for the below purpose: 18647 * 18648 * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the 18649 * wmi_peer_cfr_capture_cmd. 18650 * If payload_present bit is set to 0 then the associated memory region 18651 * gets allocated through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID. 18652 * If payload_present bit is set to 1 then CFR dump is part of the HTT 18653 * message; the CFR dump will be present at the end of the message, 18654 * after the chan_phy_mode. 18655 */ 18656 HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1, 18657 18658 /* Always keep this last */ 18659 HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX, 18660 } HTT_PEER_CFR_CAPTURE_MSG_TYPE; 18661 18662 /** 18663 * @brief target -> host CFR dump completion indication message definition 18664 * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1. 18665 * 18666 * MSG_TYPE => HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND 18667 * 18668 * @details 18669 * The following diagram shows the format of the Channel Frequency Response 18670 * (CFR) dump completion indication. This inidcation is sent to the Host when 18671 * the channel capture of a peer is copied by Firmware into the Host memory 18672 * 18673 * ************************************************************************** 18674 * 18675 * Message format when the CFR capture message type is 18676 * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' 18677 * 18678 * ************************************************************************** 18679 * 18680 * |31 16|15 |8|7 0| 18681 * |----------------------------------------------------------------| 18682 * header: | reserved |P| msg_type | 18683 * word 0 | | | | 18684 * |----------------------------------------------------------------| 18685 * payload: | cfr_capture_msg_type | 18686 * word 1 | | 18687 * |----------------------------------------------------------------| 18688 * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id | 18689 * word 2 | | | | | | | | | 18690 * |----------------------------------------------------------------| 18691 * | mac_addr31to0 | 18692 * word 3 | | 18693 * |----------------------------------------------------------------| 18694 * | unused / reserved | mac_addr47to32 | 18695 * word 4 | | | 18696 * |----------------------------------------------------------------| 18697 * | index | 18698 * word 5 | | 18699 * |----------------------------------------------------------------| 18700 * | length | 18701 * word 6 | | 18702 * |----------------------------------------------------------------| 18703 * | timestamp | 18704 * word 7 | | 18705 * |----------------------------------------------------------------| 18706 * | counter | 18707 * word 8 | | 18708 * |----------------------------------------------------------------| 18709 * | chan_mhz | 18710 * word 9 | | 18711 * |----------------------------------------------------------------| 18712 * | band_center_freq1 | 18713 * word 10 | | 18714 * |----------------------------------------------------------------| 18715 * | band_center_freq2 | 18716 * word 11 | | 18717 * |----------------------------------------------------------------| 18718 * | chan_phy_mode | 18719 * word 12 | | 18720 * |----------------------------------------------------------------| 18721 * where, 18722 * P - payload present bit (payload_present explained below) 18723 * req_id - memory request id (mem_req_id explained below) 18724 * S - status field (status explained below) 18725 * capbw - capture bandwidth (capture_bw explained below) 18726 * mode - mode of capture (mode explained below) 18727 * sts - space time streams (sts_count explained below) 18728 * chbw - channel bandwidth (channel_bw explained below) 18729 * captype - capture type (cap_type explained below) 18730 * 18731 * The following field definitions describe the format of the CFR dump 18732 * completion indication sent from the target to the host 18733 * 18734 * Header fields: 18735 * 18736 * Word 0 18737 * - msg_type 18738 * Bits 7:0 18739 * Purpose: Identifies this as CFR TX completion indication 18740 * Value: 0x22 (HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND) 18741 * - payload_present 18742 * Bit 8 18743 * Purpose: Identifies how CFR data is sent to host 18744 * Value: 0 - If CFR Payload is written to host memory 18745 * 1 - If CFR Payload is sent as part of HTT message 18746 * (This is the requirement for SDIO/USB where it is 18747 * not possible to write CFR data to host memory) 18748 * - reserved 18749 * Bits 31:9 18750 * Purpose: Reserved 18751 * Value: 0 18752 * 18753 * Payload fields: 18754 * 18755 * Word 1 18756 * - cfr_capture_msg_type 18757 * Bits 31:0 18758 * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE 18759 * to specify the format used for the remainder of the message 18760 * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18761 * (currently only MSG_TYPE_1 is defined) 18762 * 18763 * Word 2 18764 * - mem_req_id 18765 * Bits 6:0 18766 * Purpose: Contain the mem request id of the region where the CFR capture 18767 * has been stored - of type WMI_HOST_MEM_REQ_ID 18768 * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID (if payload_present is 1, 18769 this value is invalid) 18770 * - status 18771 * Bit 7 18772 * Purpose: Boolean value carrying the status of the CFR capture of the peer 18773 * Value: 1 (True) - Successful; 0 (False) - Not successful 18774 * - capture_bw 18775 * Bits 10:8 18776 * Purpose: Carry the bandwidth of the CFR capture 18777 * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW 18778 * - mode 18779 * Bits 13:11 18780 * Purpose: Carry the mode of the rx frame for which the CFR was captured 18781 * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE 18782 * - sts_count 18783 * Bits 16:14 18784 * Purpose: Carry the number of space time streams 18785 * Value: Number of space time streams 18786 * - channel_bw 18787 * Bits 19:17 18788 * Purpose: Carry the bandwidth of the channel of the vdev performing the 18789 * measurement 18790 * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW) 18791 * - cap_type 18792 * Bits 23:20 18793 * Purpose: Carry the type of the capture 18794 * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD) 18795 * - vdev_id 18796 * Bits 31:24 18797 * Purpose: Carry the virtual device id 18798 * Value: vdev ID 18799 * 18800 * Word 3 18801 * - mac_addr31to0 18802 * Bits 31:0 18803 * Purpose: Contain the bits 31:0 of the peer MAC address 18804 * Value: Bits 31:0 of the peer MAC address 18805 * 18806 * Word 4 18807 * - mac_addr47to32 18808 * Bits 15:0 18809 * Purpose: Contain the bits 47:32 of the peer MAC address 18810 * Value: Bits 47:32 of the peer MAC address 18811 * 18812 * Word 5 18813 * - index 18814 * Bits 31:0 18815 * Purpose: Contain the index at which this CFR dump was written in the Host 18816 * allocated memory. This index is the number of bytes from the base address. 18817 * Value: Index position 18818 * 18819 * Word 6 18820 * - length 18821 * Bits 31:0 18822 * Purpose: Carry the length of the CFR capture of the peer, in bytes 18823 * Value: Length of the CFR capture of the peer 18824 * 18825 * Word 7 18826 * - timestamp 18827 * Bits 31:0 18828 * Purpose: Carry the time at which the CFR was captured in the hardware. The 18829 * clock used for this timestamp is private to the target and not visible to 18830 * the host i.e., Host can interpret only the relative timestamp deltas from 18831 * one message to the next, but can't interpret the absolute timestamp from a 18832 * single message. 18833 * Value: Timestamp in microseconds 18834 * 18835 * Word 8 18836 * - counter 18837 * Bits 31:0 18838 * Purpose: Carry the count of the current CFR capture from FW. This is 18839 * helpful to identify any drops in FW in any scenario (e.g., lack of space 18840 * in host memory) 18841 * Value: Count of the current CFR capture 18842 * 18843 * Word 9 18844 * - chan_mhz 18845 * Bits 31:0 18846 * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV 18847 * Value: Primary 20 channel frequency 18848 * 18849 * Word 10 18850 * - band_center_freq1 18851 * Bits 31:0 18852 * Purpose: Carry the center frequency 1 in MHz of the VDEV 18853 * Value: Center frequency 1 in MHz 18854 * 18855 * Word 11 18856 * - band_center_freq2 18857 * Bits 31:0 18858 * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of 18859 * the VDEV 18860 * 80plus80 mode 18861 * Value: Center frequency 2 in MHz 18862 * 18863 * Word 12 18864 * - chan_phy_mode 18865 * Bits 31:0 18866 * Purpose: Carry the phy mode of the channel, of the VDEV 18867 * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h 18868 */ 18869 PREPACK struct htt_cfr_dump_ind_type_1 { 18870 A_UINT32 mem_req_id:7, 18871 status:1, 18872 capture_bw:3, 18873 mode:3, 18874 sts_count:3, 18875 channel_bw:3, 18876 cap_type:4, 18877 vdev_id:8; 18878 htt_mac_addr addr; 18879 A_UINT32 index; 18880 A_UINT32 length; 18881 A_UINT32 timestamp; 18882 A_UINT32 counter; 18883 struct htt_chan_change_msg chan; 18884 } POSTPACK; 18885 18886 PREPACK struct htt_cfr_dump_compl_ind { 18887 A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */ 18888 union { 18889 /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */ 18890 struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1; 18891 /* If there is a need to change the memory layout and its associated 18892 * HTT indication format, a new CFR capture message type can be 18893 * introduced and added into this union. 18894 */ 18895 }; 18896 } POSTPACK; 18897 18898 /* 18899 * Get / set macros for the bit fields within WORD-1 of htt_cfr_dump_compl_ind, 18900 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18901 */ 18902 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M 0x00000100 18903 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S 8 18904 18905 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_SET(word, value) \ 18906 do { \ 18907 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID, value); \ 18908 (word) |= (value) << HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S; \ 18909 } while(0) 18910 #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_GET(word) \ 18911 (((word) & HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M) >> \ 18912 HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S) 18913 18914 /* 18915 * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind, 18916 * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 18917 */ 18918 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F 18919 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0 18920 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080 18921 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7 18922 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700 18923 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8 18924 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800 18925 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11 18926 #define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000 18927 #define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14 18928 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000 18929 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17 18930 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000 18931 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20 18932 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000 18933 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24 18934 18935 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \ 18936 do { \ 18937 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \ 18938 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \ 18939 } while (0) 18940 #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \ 18941 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \ 18942 HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S) 18943 18944 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \ 18945 do { \ 18946 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \ 18947 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \ 18948 } while (0) 18949 #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \ 18950 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \ 18951 HTT_T2H_CFR_DUMP_TYPE1_STATUS_S) 18952 18953 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \ 18954 do { \ 18955 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \ 18956 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \ 18957 } while (0) 18958 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \ 18959 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \ 18960 HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S) 18961 18962 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \ 18963 do { \ 18964 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \ 18965 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \ 18966 } while (0) 18967 #define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \ 18968 (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \ 18969 HTT_T2H_CFR_DUMP_TYPE1_MODE_S) 18970 18971 #define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \ 18972 do { \ 18973 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \ 18974 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \ 18975 } while (0) 18976 #define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \ 18977 (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \ 18978 HTT_T2H_CFR_DUMP_TYPE1_STS_S) 18979 18980 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \ 18981 do { \ 18982 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \ 18983 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \ 18984 } while (0) 18985 #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \ 18986 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \ 18987 HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S) 18988 18989 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \ 18990 do { \ 18991 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \ 18992 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \ 18993 } while (0) 18994 #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \ 18995 (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \ 18996 HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S) 18997 18998 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \ 18999 do { \ 19000 HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \ 19001 (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \ 19002 } while (0) 19003 #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \ 19004 (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \ 19005 HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S) 19006 19007 19008 /** 19009 * @brief target -> host peer (PPDU) stats message 19010 * 19011 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_STATS_IND 19012 * 19013 * @details 19014 * This message is generated by FW when FW is sending stats to host 19015 * about one or more PPDUs that the FW has transmitted to one or more peers. 19016 * This message is sent autonomously by the target rather than upon request 19017 * by the host. 19018 * The following field definitions describe the format of the HTT target 19019 * to host peer stats indication message. 19020 * 19021 * The HTT_T2H PPDU_STATS_IND message has a header followed by one 19022 * or more PPDU stats records. 19023 * Each PPDU stats record uses a htt_tx_ppdu_stats_info TLV. 19024 * If the details of N PPDUS are sent in one PEER_STATS_IND message, 19025 * then the message would start with the 19026 * header, followed by N htt_tx_ppdu_stats_info structures, as depicted 19027 * below. 19028 * 19029 * |31 16|15|14|13 11|10 9|8|7 0| 19030 * |-------------------------------------------------------------| 19031 * | reserved |MSG_TYPE | 19032 * |-------------------------------------------------------------| 19033 * rec 0 | TLV header | 19034 * rec 0 |-------------------------------------------------------------| 19035 * rec 0 | ppdu successful bytes | 19036 * rec 0 |-------------------------------------------------------------| 19037 * rec 0 | ppdu retry bytes | 19038 * rec 0 |-------------------------------------------------------------| 19039 * rec 0 | ppdu failed bytes | 19040 * rec 0 |-------------------------------------------------------------| 19041 * rec 0 | peer id | S|SG| BW | BA |A|rate code| 19042 * rec 0 |-------------------------------------------------------------| 19043 * rec 0 | retried MSDUs | successful MSDUs | 19044 * rec 0 |-------------------------------------------------------------| 19045 * rec 0 | TX duration | failed MSDUs | 19046 * rec 0 |-------------------------------------------------------------| 19047 * ... 19048 * |-------------------------------------------------------------| 19049 * rec N | TLV header | 19050 * rec N |-------------------------------------------------------------| 19051 * rec N | ppdu successful bytes | 19052 * rec N |-------------------------------------------------------------| 19053 * rec N | ppdu retry bytes | 19054 * rec N |-------------------------------------------------------------| 19055 * rec N | ppdu failed bytes | 19056 * rec N |-------------------------------------------------------------| 19057 * rec N | peer id | S|SG| BW | BA |A|rate code| 19058 * rec N |-------------------------------------------------------------| 19059 * rec N | retried MSDUs | successful MSDUs | 19060 * rec N |-------------------------------------------------------------| 19061 * rec N | TX duration | failed MSDUs | 19062 * rec N |-------------------------------------------------------------| 19063 * 19064 * where: 19065 * A = is A-MPDU flag 19066 * BA = block-ack failure flags 19067 * BW = bandwidth spec 19068 * SG = SGI enabled spec 19069 * S = skipped rate ctrl 19070 * One htt_tx_ppdu_stats_info instance will have stats for one PPDU 19071 * 19072 * Header 19073 * ------ 19074 * dword0 - b'0:7 - msg_type : 0x23 (HTT_T2H_MSG_TYPE_PEER_STATS_IND) 19075 * dword0 - b'8:31 - reserved : Reserved for future use 19076 * 19077 * payload include below peer_stats information 19078 * -------------------------------------------- 19079 * @TLV : HTT_PPDU_STATS_INFO_TLV 19080 * @tx_success_bytes : total successful bytes in the PPDU. 19081 * @tx_retry_bytes : total retried bytes in the PPDU. 19082 * @tx_failed_bytes : total failed bytes in the PPDU. 19083 * @tx_ratecode : rate code used for the PPDU. 19084 * @is_ampdu : Indicates PPDU is AMPDU or not. 19085 * @ba_ack_failed : BA/ACK failed for this PPDU 19086 * b00 -> BA received 19087 * b01 -> BA failed once 19088 * b10 -> BA failed twice, when HW retry is enabled. 19089 * @bw : BW 19090 * b00 -> 20 MHz 19091 * b01 -> 40 MHz 19092 * b10 -> 80 MHz 19093 * b11 -> 160 MHz (or 80+80) 19094 * @sg : SGI enabled 19095 * @s : skipped ratectrl 19096 * @peer_id : peer id 19097 * @tx_success_msdus : successful MSDUs 19098 * @tx_retry_msdus : retried MSDUs 19099 * @tx_failed_msdus : MSDUs dropped in FW after max retry 19100 * @tx_duration : Tx duration for the PPDU (microsecond units) 19101 */ 19102 19103 19104 /** 19105 * @brief target -> host backpressure event 19106 * 19107 * MSG_TYPE => HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND 19108 * 19109 * @details 19110 * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID message is sent by the target when 19111 * continuous backpressure is seen in the LMAC/ UMAC rings software rings. 19112 * This message will only be sent if the backpressure condition has existed 19113 * continuously for an initial period (100 ms). 19114 * Repeat messages with updated information will be sent after each 19115 * subsequent period (100 ms) as long as the backpressure remains unabated. 19116 * This message indicates the ring id along with current head and tail index 19117 * locations (i.e. write and read indices). 19118 * The backpressure time indicates the time in ms for which continuous 19119 * backpressure has been observed in the ring. 19120 * 19121 * The message format is as follows: 19122 * 19123 * |31 24|23 16|15 8|7 0| 19124 * |----------------+----------------+----------------+----------------| 19125 * | ring_id | ring_type | pdev_id | msg_type | 19126 * |-------------------------------------------------------------------| 19127 * | tail_idx | head_idx | 19128 * |-------------------------------------------------------------------| 19129 * | backpressure_time_ms | 19130 * |-------------------------------------------------------------------| 19131 * 19132 * The message is interpreted as follows: 19133 * dword0 - b'0:7 - msg_type: This will be set to 0x24 19134 * (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND) 19135 * b'8:15 - pdev_id: 0 indicates msg is for UMAC ring. 19136 * 1, 2, 3 indicates pdev_id 0,1,2 and 19137 * the msg is for LMAC ring. 19138 * b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type. 19139 * b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/ 19140 * htt_backpressure_lmac_ring_id. This represents 19141 * the ring id for which continuous backpressure 19142 * is seen 19143 * 19144 * dword1 - b'0:15 - head_idx: This indicates the current head index of 19145 * the ring indicated by the ring_id 19146 * 19147 * dword1 - b'16:31 - tail_idx: This indicates the current tail index of 19148 * the ring indicated by the ring id 19149 * 19150 * dword2 - b'0:31 - backpressure_time_ms: Indicates how long continuous 19151 * backpressure has been seen in the ring 19152 * indicated by the ring_id. 19153 * Units = milliseconds 19154 */ 19155 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_M 0x0000ff00 19156 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_S 8 19157 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_M 0x00ff0000 19158 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_S 16 19159 #define HTT_T2H_RX_BKPRESSURE_RINGID_M 0xff000000 19160 #define HTT_T2H_RX_BKPRESSURE_RINGID_S 24 19161 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M 0x0000ffff 19162 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S 0 19163 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M 0xffff0000 19164 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S 16 19165 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_M 0xffffffff 19166 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_S 0 19167 19168 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_SET(word, value) \ 19169 do { \ 19170 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_PDEV_ID, value); \ 19171 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_PDEV_ID_S; \ 19172 } while (0) 19173 #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_GET(word) \ 19174 (((word) & HTT_T2H_RX_BKPRESSURE_PDEV_ID_M) >> \ 19175 HTT_T2H_RX_BKPRESSURE_PDEV_ID_S) 19176 19177 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_SET(word, value) \ 19178 do { \ 19179 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RING_TYPE, value); \ 19180 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RING_TYPE_S; \ 19181 } while (0) 19182 #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_GET(word) \ 19183 (((word) & HTT_T2H_RX_BKPRESSURE_RING_TYPE_M) >> \ 19184 HTT_T2H_RX_BKPRESSURE_RING_TYPE_S) 19185 19186 #define HTT_T2H_RX_BKPRESSURE_RINGID_SET(word, value) \ 19187 do { \ 19188 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RINGID, value); \ 19189 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RINGID_S; \ 19190 } while (0) 19191 #define HTT_T2H_RX_BKPRESSURE_RINGID_GET(word) \ 19192 (((word) & HTT_T2H_RX_BKPRESSURE_RINGID_M) >> \ 19193 HTT_T2H_RX_BKPRESSURE_RINGID_S) 19194 19195 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_SET(word, value) \ 19196 do { \ 19197 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_HEAD_IDX, value); \ 19198 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S; \ 19199 } while (0) 19200 #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_GET(word) \ 19201 (((word) & HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M) >> \ 19202 HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S) 19203 19204 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_SET(word, value) \ 19205 do { \ 19206 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TAIL_IDX, value); \ 19207 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S; \ 19208 } while (0) 19209 #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_GET(word) \ 19210 (((word) & HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M) >> \ 19211 HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S) 19212 19213 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_SET(word, value) \ 19214 do { \ 19215 HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TIME_MS, value); \ 19216 (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TIME_MS_S; \ 19217 } while (0) 19218 #define HTT_T2H_RX_BKPRESSURE_TIME_MS_GET(word) \ 19219 (((word) & HTT_T2H_RX_BKPRESSURE_TIME_MS_M) >> \ 19220 HTT_T2H_RX_BKPRESSURE_TIME_MS_S) 19221 19222 enum htt_backpressure_ring_type { 19223 HTT_SW_RING_TYPE_UMAC, 19224 HTT_SW_RING_TYPE_LMAC, 19225 HTT_SW_RING_TYPE_MAX, 19226 }; 19227 19228 /* Ring id for which the message is sent to host */ 19229 enum htt_backpressure_umac_ringid { 19230 HTT_SW_RING_IDX_REO_REO2SW1_RING, 19231 HTT_SW_RING_IDX_REO_REO2SW2_RING, 19232 HTT_SW_RING_IDX_REO_REO2SW3_RING, 19233 HTT_SW_RING_IDX_REO_REO2SW4_RING, 19234 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 19235 HTT_SW_RING_IDX_REO_REO2TCL_RING, 19236 HTT_SW_RING_IDX_REO_REO2FW_RING, 19237 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 19238 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 19239 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 19240 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 19241 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 19242 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 19243 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 19244 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 19245 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 19246 HTT_SW_RING_IDX_REO_REO_CMD_RING, 19247 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 19248 HTT_SW_UMAC_RING_IDX_MAX, 19249 }; 19250 19251 enum htt_backpressure_lmac_ringid { 19252 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 19253 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 19254 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 19255 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 19256 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 19257 HTT_SW_RING_IDX_RXDMA2FW_RING, 19258 HTT_SW_RING_IDX_RXDMA2SW_RING, 19259 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 19260 HTT_SW_RING_IDX_RXDMA2REO_RING, 19261 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 19262 HTT_SW_RING_IDX_MONITOR_BUF_RING, 19263 HTT_SW_RING_IDX_MONITOR_DESC_RING, 19264 HTT_SW_RING_IDX_MONITOR_DEST_RING, 19265 HTT_SW_LMAC_RING_IDX_MAX, 19266 }; 19267 19268 PREPACK struct htt_t2h_msg_bkpressure_event_ind_t { 19269 A_UINT32 msg_type: 8, /* HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND */ 19270 pdev_id: 8, 19271 ring_type: 8, /* htt_backpressure_ring_type */ 19272 /* 19273 * ring_id holds an enum value from either 19274 * htt_backpressure_umac_ringid or 19275 * htt_backpressure_lmac_ringid, based on 19276 * the ring_type setting. 19277 */ 19278 ring_id: 8; 19279 A_UINT16 head_idx; 19280 A_UINT16 tail_idx; 19281 A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */ 19282 } POSTPACK; 19283 19284 19285 /* 19286 * Defines two 32 bit words that can be used by the target to indicate a per 19287 * user RU allocation and rate information. 19288 * 19289 * This information is currently provided in the "sw_response_reference_ptr" 19290 * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the 19291 * "rx_ppdu_end_user_stats" TLV. 19292 * 19293 * VALID: 19294 * The consumer of these words must explicitly check the valid bit, 19295 * and only attempt interpretation of any of the remaining fields if 19296 * the valid bit is set to 1. 19297 * 19298 * VERSION: 19299 * The consumer of these words must also explicitly check the version bit, 19300 * and only use the V0 definition if the VERSION field is set to 0. 19301 * 19302 * Version 1 is currently undefined, with the exception of the VALID and 19303 * VERSION fields. 19304 * 19305 * Version 0: 19306 * 19307 * The fields below are duplicated per BW. 19308 * 19309 * The consumer must determine which BW field to use, based on the UL OFDMA 19310 * PPDU BW indicated by HW. 19311 * 19312 * RU_START: RU26 start index for the user. 19313 * Note that this is always using the RU26 index, regardless 19314 * of the actual RU assigned to the user 19315 * (i.e. the second RU52 is RU_START 2, RU_SIZE 19316 * HTT_UL_OFDMA_V0_RU_SIZE_RU_52) 19317 * 19318 * For example, 20MHz (the value in the top row is RU_START) 19319 * 19320 * RU Size 0 (26): |0|1|2|3|4|5|6|7|8| 19321 * RU Size 1 (52): | | | | | | 19322 * RU Size 2 (106): | | | | 19323 * RU Size 3 (242): | | 19324 * 19325 * RU_SIZE: Indicates the RU size, as defined by enum 19326 * htt_ul_ofdma_user_info_ru_size. 19327 * 19328 * LDPC: LDPC enabled (if 0, BCC is used) 19329 * 19330 * DCM: DCM enabled 19331 * 19332 * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0| 19333 * |---------------------------------+--------------------------------| 19334 * |Ver|Valid| FW internal | 19335 * |---------------------------------+--------------------------------| 19336 * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS| 19337 * |---------------------------------+--------------------------------| 19338 */ 19339 19340 enum htt_ul_ofdma_user_info_ru_size { 19341 HTT_UL_OFDMA_V0_RU_SIZE_RU_26, 19342 HTT_UL_OFDMA_V0_RU_SIZE_RU_52, 19343 HTT_UL_OFDMA_V0_RU_SIZE_RU_106, 19344 HTT_UL_OFDMA_V0_RU_SIZE_RU_242, 19345 HTT_UL_OFDMA_V0_RU_SIZE_RU_484, 19346 HTT_UL_OFDMA_V0_RU_SIZE_RU_996, 19347 HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 19348 }; 19349 19350 /* htt_up_ofdma_user_info_v0 provides an abstract view of the info */ 19351 struct htt_ul_ofdma_user_info_v0 { 19352 A_UINT32 word0; 19353 A_UINT32 word1; 19354 }; 19355 19356 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ 19357 A_UINT32 w0_fw_rsvd:29; \ 19358 A_UINT32 w0_manual_ulofdma_trig:1; \ 19359 A_UINT32 w0_valid:1; \ 19360 A_UINT32 w0_version:1; 19361 19362 struct htt_ul_ofdma_user_info_v0_bitmap_w0 { 19363 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 19364 }; 19365 19366 #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 \ 19367 A_UINT32 w1_nss:3; \ 19368 A_UINT32 w1_mcs:4; \ 19369 A_UINT32 w1_ldpc:1; \ 19370 A_UINT32 w1_dcm:1; \ 19371 A_UINT32 w1_ru_start:7; \ 19372 A_UINT32 w1_ru_size:3; \ 19373 A_UINT32 w1_trig_type:4; \ 19374 A_UINT32 w1_unused:9; 19375 struct htt_ul_ofdma_user_info_v0_bitmap_w1 { 19376 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 19377 }; 19378 19379 19380 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ 19381 A_UINT32 w0_fw_rsvd:27; \ 19382 A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ 19383 A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ 19384 A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ 19385 19386 struct htt_ul_ofdma_user_info_v1_bitmap_w0 { 19387 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 19388 }; 19389 19390 #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 \ 19391 A_UINT32 w1_unused_0_to_18:19; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ \ 19392 A_UINT32 w1_trig_type:4; \ 19393 A_UINT32 w1_unused_23_to_31:9; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ 19394 19395 struct htt_ul_ofdma_user_info_v1_bitmap_w1 { 19396 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 19397 }; 19398 19399 19400 /* htt_ul_ofdma_user_info_v0_bitmap shows what bitfields are within the info */ 19401 PREPACK struct htt_ul_ofdma_user_info_v0_bitmap { 19402 union { 19403 A_UINT32 word0; 19404 struct { 19405 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 19406 }; 19407 }; 19408 union { 19409 A_UINT32 word1; 19410 struct { 19411 HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 19412 }; 19413 }; 19414 } POSTPACK; 19415 19416 /* 19417 * htt_ul_ofdma_user_info_v1_bitmap bits are aligned to 19418 * htt_ul_ofdma_user_info_v0_bitmap, based on the w0_version 19419 * this should be picked. 19420 */ 19421 PREPACK struct htt_ul_ofdma_user_info_v1_bitmap { 19422 union { 19423 A_UINT32 word0; 19424 struct { 19425 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 19426 }; 19427 }; 19428 union { 19429 A_UINT32 word1; 19430 struct { 19431 HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 19432 }; 19433 }; 19434 } POSTPACK; 19435 19436 19437 enum HTT_UL_OFDMA_TRIG_TYPE { 19438 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0, 19439 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP, 19440 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR, 19441 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS, 19442 HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR, 19443 }; 19444 19445 19446 #define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0)) 19447 19448 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff 19449 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 19450 19451 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 19452 #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 19453 19454 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 19455 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 19456 19457 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000 19458 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31 19459 19460 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007 19461 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0 19462 19463 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078 19464 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3 19465 19466 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080 19467 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7 19468 19469 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100 19470 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8 19471 19472 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00 19473 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9 19474 19475 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000 19476 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16 19477 19478 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000 19479 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19 19480 19481 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000 19482 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23 19483 19484 /*--- word 0 ---*/ 19485 19486 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \ 19487 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S) 19488 19489 #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \ 19490 do { \ 19491 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \ 19492 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \ 19493 } while (0) 19494 19495 19496 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \ 19497 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S) 19498 19499 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \ 19500 do { \ 19501 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \ 19502 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \ 19503 } while (0) 19504 19505 19506 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \ 19507 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S) 19508 19509 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \ 19510 do { \ 19511 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \ 19512 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \ 19513 } while (0) 19514 19515 19516 /*--- word 1 ---*/ 19517 19518 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \ 19519 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S) 19520 19521 #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \ 19522 do { \ 19523 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \ 19524 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \ 19525 } while (0) 19526 19527 19528 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \ 19529 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S) 19530 19531 #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \ 19532 do { \ 19533 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \ 19534 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \ 19535 } while (0) 19536 19537 19538 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \ 19539 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S) 19540 19541 #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \ 19542 do { \ 19543 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \ 19544 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \ 19545 } while (0) 19546 19547 19548 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \ 19549 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S) 19550 19551 #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \ 19552 do { \ 19553 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \ 19554 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \ 19555 } while (0) 19556 19557 19558 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \ 19559 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S) 19560 19561 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \ 19562 do { \ 19563 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \ 19564 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \ 19565 } while (0) 19566 19567 19568 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \ 19569 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S) 19570 19571 #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \ 19572 do { \ 19573 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \ 19574 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \ 19575 } while (0) 19576 19577 19578 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \ 19579 (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S) 19580 19581 #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \ 19582 do { \ 19583 HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \ 19584 ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \ 19585 } while (0) 19586 19587 /** 19588 * @brief target -> host channel calibration data message 19589 * 19590 * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CALDATA 19591 * 19592 * @brief host -> target channel calibration data message 19593 * 19594 * MSG_TYPE => HTT_H2T_MSG_TYPE_CHAN_CALDATA 19595 * 19596 * @details 19597 * The following field definitions describe the format of the channel 19598 * calibration data message sent from the target to the host when 19599 * MSG_TYPE is HTT_T2H_MSG_TYPE_CHAN_CALDATA, and sent from the host 19600 * to the target when MSG_TYPE is HTT_H2T_MSG_TYPE_CHAN_CALDATA. 19601 * The message is defined as htt_chan_caldata_msg followed by a variable 19602 * number of 32-bit character values. 19603 * 19604 * |31 21|20|19 16|15 13| 12|11 8|7 0| 19605 * |------------------------------------------------------------------| 19606 * | rsv | A| frag | rsv |ck_v| sub_type| msg type | 19607 * |------------------------------------------------------------------| 19608 * | payload size | mhz | 19609 * |------------------------------------------------------------------| 19610 * | center frequency 2 | center frequency 1 | 19611 * |------------------------------------------------------------------| 19612 * | check sum | 19613 * |------------------------------------------------------------------| 19614 * | payload | 19615 * |------------------------------------------------------------------| 19616 * message info field: 19617 * - MSG_TYPE 19618 * Bits 7:0 19619 * Purpose: identifies this as a channel calibration data message 19620 * Value: 0x25 (HTT_T2H_MSG_TYPE_CHAN_CALDATA) 19621 * 0x14 (HTT_H2T_MSG_TYPE_CHAN_CALDATA) 19622 * - SUB_TYPE 19623 * Bits 11:8 19624 * Purpose: T2H: indicates whether target is providing chan cal data 19625 * to the host to store, or requesting that the host 19626 * download previously-stored data. 19627 * H2T: indicates whether the host is providing the requested 19628 * channel cal data, or if it is rejecting the data 19629 * request because it does not have the requested data. 19630 * Value: see HTT_T2H_MSG_CHAN_CALDATA_xxx defs 19631 * - CHKSUM_VALID 19632 * Bit 12 19633 * Purpose: indicates if the checksum field is valid 19634 * value: 19635 * - FRAG 19636 * Bit 19:16 19637 * Purpose: indicates the fragment index for message 19638 * value: 0 for first fragment, 1 for second fragment, ... 19639 * - APPEND 19640 * Bit 20 19641 * Purpose: indicates if this is the last fragment 19642 * value: 0 = final fragment, 1 = more fragments will be appended 19643 * 19644 * channel and payload size field 19645 * - MHZ 19646 * Bits 15:0 19647 * Purpose: indicates the channel primary frequency 19648 * Value: 19649 * - PAYLOAD_SIZE 19650 * Bits 31:16 19651 * Purpose: indicates the bytes of calibration data in payload 19652 * Value: 19653 * 19654 * center frequency field 19655 * - CENTER FREQUENCY 1 19656 * Bits 15:0 19657 * Purpose: indicates the channel center frequency 19658 * Value: channel center frequency, in MHz units 19659 * - CENTER FREQUENCY 2 19660 * Bits 31:16 19661 * Purpose: indicates the secondary channel center frequency, 19662 * only for 11acvht 80plus80 mode 19663 * Value: secondary channel center frequency, in MHz units, if applicable 19664 * 19665 * checksum field 19666 * - CHECK_SUM 19667 * Bits 31:0 19668 * Purpose: check the payload data, it is just for this fragment. 19669 * This is intended for the target to check that the channel 19670 * calibration data returned by the host is the unmodified data 19671 * that was previously provided to the host by the target. 19672 * value: checksum of fragment payload 19673 */ 19674 PREPACK struct htt_chan_caldata_msg { 19675 /* DWORD 0: message info */ 19676 A_UINT32 19677 msg_type: 8, 19678 sub_type: 4 , 19679 chksum_valid: 1, /** 1:valid, 0:invalid */ 19680 reserved1: 3, 19681 frag_idx: 4, /** fragment index for calibration data */ 19682 appending: 1, /** 0: no fragment appending, 19683 * 1: extra fragment appending */ 19684 reserved2: 11; 19685 19686 /* DWORD 1: channel and payload size */ 19687 A_UINT32 19688 mhz: 16, /** primary 20 MHz channel frequency in mhz */ 19689 payload_size: 16; /** unit: bytes */ 19690 19691 /* DWORD 2: center frequency */ 19692 A_UINT32 19693 band_center_freq1: 16, /** Center frequency 1 in MHz */ 19694 band_center_freq2: 16; /** Center frequency 2 in MHz, 19695 * valid only for 11acvht 80plus80 mode */ 19696 19697 /* DWORD 3: check sum */ 19698 A_UINT32 chksum; 19699 19700 /* variable length for calibration data */ 19701 A_UINT32 payload[1/* or more */]; 19702 } POSTPACK; 19703 19704 /* T2H SUBTYPE */ 19705 #define HTT_T2H_MSG_CHAN_CALDATA_REQ 0 19706 #define HTT_T2H_MSG_CHAN_CALDATA_UPLOAD 1 19707 19708 /* H2T SUBTYPE */ 19709 #define HTT_H2T_MSG_CHAN_CALDATA_REJ 0 19710 #define HTT_H2T_MSG_CHAN_CALDATA_DOWNLOAD 1 19711 19712 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_S 8 19713 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_M 0x00000f00 19714 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_GET(_var) \ 19715 (((_var) & HTT_CHAN_CALDATA_MSG_SUB_TYPE_M) >> HTT_CHAN_CALDATA_MSG_SUB_TYPE_S) 19716 #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_SET(_var, _val) \ 19717 do { \ 19718 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_SUB_TYPE, _val); \ 19719 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_SUB_TYPE_S)); \ 19720 } while (0) 19721 19722 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_S 12 19723 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_M 0x00001000 19724 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_GET(_var) \ 19725 (((_var) & HTT_CHAN_CALDATA_MSG_CHKSUM_V_M) >> HTT_CHAN_CALDATA_MSG_CHKSUM_V_S) 19726 #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_SET(_var, _val) \ 19727 do { \ 19728 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_CHKSUM_V, _val); \ 19729 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_CHKSUM_V_S)); \ 19730 } while (0) 19731 19732 19733 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_S 16 19734 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_M 0x000f0000 19735 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_GET(_var) \ 19736 (((_var) & HTT_CHAN_CALDATA_MSG_FRAG_IDX_M) >> HTT_CHAN_CALDATA_MSG_FRAG_IDX_S) 19737 #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_SET(_var, _val) \ 19738 do { \ 19739 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FRAG_IDX, _val); \ 19740 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FRAG_IDX_S)); \ 19741 } while (0) 19742 19743 #define HTT_CHAN_CALDATA_MSG_APPENDING_S 20 19744 #define HTT_CHAN_CALDATA_MSG_APPENDING_M 0x00100000 19745 #define HTT_CHAN_CALDATA_MSG_APPENDING_GET(_var) \ 19746 (((_var) & HTT_CHAN_CALDATA_MSG_APPENDING_M) >> HTT_CHAN_CALDATA_MSG_APPENDING_S) 19747 #define HTT_CHAN_CALDATA_MSG_APPENDING_SET(_var, _val) \ 19748 do { \ 19749 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_APPENDING, _val); \ 19750 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_APPENDING_S)); \ 19751 } while (0) 19752 19753 #define HTT_CHAN_CALDATA_MSG_MHZ_S 0 19754 #define HTT_CHAN_CALDATA_MSG_MHZ_M 0x0000ffff 19755 #define HTT_CHAN_CALDATA_MSG_MHZ_GET(_var) \ 19756 (((_var) & HTT_CHAN_CALDATA_MSG_MHZ_M) >> HTT_CHAN_CALDATA_MSG_MHZ_S) 19757 #define HTT_CHAN_CALDATA_MSG_MHZ_SET(_var, _val) \ 19758 do { \ 19759 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_MHZ, _val); \ 19760 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_MHZ_S)); \ 19761 } while (0) 19762 19763 19764 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_S 16 19765 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_M 0xffff0000 19766 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_GET(_var) \ 19767 (((_var) & HTT_CHAN_CALDATA_MSG_PLD_SIZE_M) >> HTT_CHAN_CALDATA_MSG_PLD_SIZE_S) 19768 #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_SET(_var, _val) \ 19769 do { \ 19770 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_PLD_SIZE, _val); \ 19771 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_PLD_SIZE_S)); \ 19772 } while (0) 19773 19774 19775 #define HTT_CHAN_CALDATA_MSG_FREQ1_S 0 19776 #define HTT_CHAN_CALDATA_MSG_FREQ1_M 0x0000ffff 19777 #define HTT_CHAN_CALDATA_MSG_FREQ1_GET(_var) \ 19778 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ1_M) >> HTT_CHAN_CALDATA_MSG_FREQ1_S) 19779 #define HTT_CHAN_CALDATA_MSG_FREQ1_SET(_var, _val) \ 19780 do { \ 19781 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ1, _val); \ 19782 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ1_S)); \ 19783 } while (0) 19784 19785 #define HTT_CHAN_CALDATA_MSG_FREQ2_S 16 19786 #define HTT_CHAN_CALDATA_MSG_FREQ2_M 0xffff0000 19787 #define HTT_CHAN_CALDATA_MSG_FREQ2_GET(_var) \ 19788 (((_var) & HTT_CHAN_CALDATA_MSG_FREQ2_M) >> HTT_CHAN_CALDATA_MSG_FREQ2_S) 19789 #define HTT_CHAN_CALDATA_MSG_FREQ2_SET(_var, _val) \ 19790 do { \ 19791 HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ2, _val); \ 19792 ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \ 19793 } while (0) 19794 19795 19796 /** 19797 * @brief target -> host FSE CMEM based send 19798 * 19799 * MSG_TYPE => HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND 19800 * 19801 * @details 19802 * HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND message is sent by the target when 19803 * FSE placement in CMEM is enabled. 19804 * 19805 * This message sends the non-secure CMEM base address. 19806 * It will be sent to host in response to message 19807 * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG. 19808 * The message would appear as follows: 19809 * 19810 * |31 24|23 16|15 8|7 0| 19811 * |----------------+----------------+----------------+----------------| 19812 * | reserved | num_entries | msg_type | 19813 * |----------------+----------------+----------------+----------------| 19814 * | base_address_lo | 19815 * |----------------+----------------+----------------+----------------| 19816 * | base_address_hi | 19817 * |-------------------------------------------------------------------| 19818 * 19819 * The message is interpreted as follows: 19820 * dword0 - b'0:7 - msg_type: This will be set to 0x27 19821 * (HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND) 19822 * b'8:15 - number_entries: Indicated the number of entries 19823 * programmed. 19824 * b'16:31 - reserved. 19825 * dword1 - b'0:31 - base_address_lo: Indicate lower 32 bits of 19826 * CMEM base address 19827 * dword2 - b'0:31 - base_address_hi: Indicate upper 32 bits of 19828 * CMEM base address 19829 */ 19830 19831 PREPACK struct htt_cmem_base_send_t { 19832 A_UINT32 msg_type: 8, 19833 num_entries: 8, 19834 reserved: 16; 19835 A_UINT32 base_address_lo; 19836 A_UINT32 base_address_hi; 19837 } POSTPACK; 19838 19839 #define HTT_CMEM_BASE_SEND_SIZE (sizeof(struct htt_cmem_base_send_t)) 19840 19841 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_M 0x0000FF00 19842 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_S 8 19843 19844 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_GET(_var) \ 19845 (((_var) & HTT_CMEM_BASE_SEND_NUM_ENTRIES_M) >> \ 19846 HTT_CMEM_BASE_SEND_NUM_ENTRIES_S) 19847 19848 #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_SET(_var, _val) \ 19849 do { \ 19850 HTT_CHECK_SET_VAL(HTT_CMEM_BASE_SEND_NUM_ENTRIES, _val); \ 19851 ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ 19852 } while (0) 19853 19854 /** 19855 * @brief - HTT PPDU ID format 19856 * 19857 * @details 19858 * The following field definitions describe the format of the PPDU ID. 19859 * The PPDU ID is truncated to 24 bits for TLVs from TQM. 19860 * 19861 * |31 30|29 24| 23|22 21|20 19|18 17|16 12|11 0| 19862 * +-------------------------------------------------------------------------- 19863 * |rsvd |seq_cmd_type|tqm_cmd|rsvd |seq_idx|mac_id| hwq_ id | sch id | 19864 * +-------------------------------------------------------------------------- 19865 * 19866 * sch id :Schedule command id 19867 * Bits [11 : 0] : monotonically increasing counter to track the 19868 * PPDU posted to a specific transmit queue. 19869 * 19870 * hwq_id: Hardware Queue ID. 19871 * Bits [16 : 12] : Indicates the queue id in the hardware transmit queue. 19872 * 19873 * mac_id: MAC ID 19874 * Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct 19875 * 19876 * seq_idx: Sequence index. 19877 * Bits [21 : 19] : Sequence index indicates all the PPDU belonging to 19878 * a particular TXOP. 19879 * 19880 * tqm_cmd: HWSCH/TQM flag. 19881 * Bit [23] : Always set to 0. 19882 * 19883 * seq_cmd_type: Sequence command type. 19884 * Bit [29 : 24] : Indicates the frame type for the current sequence. 19885 * Refer to enum HTT_STATS_FTYPE for values. 19886 */ 19887 PREPACK struct htt_ppdu_id { 19888 A_UINT32 19889 sch_id: 12, 19890 hwq_id: 5, 19891 mac_id: 2, 19892 seq_idx: 2, 19893 reserved1: 2, 19894 tqm_cmd: 1, 19895 seq_cmd_type: 6, 19896 reserved2: 2; 19897 } POSTPACK; 19898 19899 #define HTT_PPDU_ID_SCH_ID_S 0 19900 #define HTT_PPDU_ID_SCH_ID_M 0x00000fff 19901 #define HTT_PPDU_ID_SCH_ID_GET(_var) \ 19902 (((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S) 19903 19904 #define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \ 19905 do { \ 19906 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \ 19907 ((_var) |= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \ 19908 } while (0) 19909 19910 #define HTT_PPDU_ID_HWQ_ID_S 12 19911 #define HTT_PPDU_ID_HWQ_ID_M 0x0001f000 19912 #define HTT_PPDU_ID_HWQ_ID_GET(_var) \ 19913 (((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S) 19914 19915 #define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \ 19916 do { \ 19917 HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \ 19918 ((_var) |= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \ 19919 } while (0) 19920 19921 #define HTT_PPDU_ID_MAC_ID_S 17 19922 #define HTT_PPDU_ID_MAC_ID_M 0x00060000 19923 #define HTT_PPDU_ID_MAC_ID_GET(_var) \ 19924 (((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S) 19925 19926 #define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \ 19927 do { \ 19928 HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \ 19929 ((_var) |= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \ 19930 } while (0) 19931 19932 #define HTT_PPDU_ID_SEQ_IDX_S 19 19933 #define HTT_PPDU_ID_SEQ_IDX_M 0x00180000 19934 #define HTT_PPDU_ID_SEQ_IDX_GET(_var) \ 19935 (((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S) 19936 19937 #define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \ 19938 do { \ 19939 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \ 19940 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \ 19941 } while (0) 19942 19943 #define HTT_PPDU_ID_TQM_CMD_S 23 19944 #define HTT_PPDU_ID_TQM_CMD_M 0x00800000 19945 #define HTT_PPDU_ID_TQM_CMD_GET(_var) \ 19946 (((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S) 19947 19948 #define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \ 19949 do { \ 19950 HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \ 19951 ((_var) |= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \ 19952 } while (0) 19953 19954 #define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24 19955 #define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000 19956 #define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \ 19957 (((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S) 19958 19959 #define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \ 19960 do { \ 19961 HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \ 19962 ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \ 19963 } while (0) 19964 19965 /** 19966 * @brief target -> RX PEER METADATA V0 format 19967 * Host will know the peer metadata version from the wmi_service_ready_ext2 19968 * message from target, and will confirm to the target which peer metadata 19969 * version to use in the wmi_init message. 19970 * 19971 * The following diagram shows the format of the RX PEER METADATA. 19972 * 19973 * |31 24|23 16|15 8|7 0| 19974 * |-----------------------------------------------------------------------| 19975 * | Reserved | VDEV ID | PEER ID | 19976 * |-----------------------------------------------------------------------| 19977 */ 19978 PREPACK struct htt_rx_peer_metadata_v0 { 19979 A_UINT32 19980 peer_id: 16, 19981 vdev_id: 8, 19982 reserved1: 8; 19983 } POSTPACK; 19984 19985 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_S 0 19986 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_M 0x0000ffff 19987 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_GET(_var) \ 19988 (((_var) & HTT_RX_PEER_META_DATA_V0_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V0_PEER_ID_S) 19989 19990 #define HTT_RX_PEER_META_DATA_V0_PEER_ID_SET(_var, _val) \ 19991 do { \ 19992 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_PEER_ID, _val); \ 19993 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_PEER_ID_S)); \ 19994 } while (0) 19995 19996 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_S 16 19997 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_M 0x00ff0000 19998 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_GET(_var) \ 19999 (((_var) & HTT_RX_PEER_META_DATA_V0_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V0_VDEV_ID_S) 20000 20001 #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_SET(_var, _val) \ 20002 do { \ 20003 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_VDEV_ID, _val); \ 20004 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_VDEV_ID_S)); \ 20005 } while (0) 20006 20007 /** 20008 * @brief target -> RX PEER METADATA V1 format 20009 * Host will know the peer metadata version from the wmi_service_ready_ext2 20010 * message from target, and will confirm to the target which peer metadata 20011 * version to use in the wmi_init message. 20012 * 20013 * The following diagram shows the format of the RX PEER METADATA V1 format. 20014 * 20015 * |31 29|28 26|25 24|23 16|15 14| 13 |12 0| 20016 * |---------------------------------------------------------------------------| 20017 * |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID| 20018 * |---------------------------------------------------------------------------| 20019 */ 20020 PREPACK struct htt_rx_peer_metadata_v1 { 20021 A_UINT32 20022 peer_id: 13, 20023 ml_peer_valid: 1, 20024 logical_link_id: 2, 20025 vdev_id: 8, 20026 lmac_id: 2, 20027 chip_id: 3, 20028 reserved2: 3; 20029 } POSTPACK; 20030 20031 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_S 0 20032 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_M 0x00001fff 20033 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_GET(_var) \ 20034 (((_var) & HTT_RX_PEER_META_DATA_V1_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1_PEER_ID_S) 20035 20036 #define HTT_RX_PEER_META_DATA_V1_PEER_ID_SET(_var, _val) \ 20037 do { \ 20038 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_PEER_ID, _val); \ 20039 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_PEER_ID_S)); \ 20040 } while (0) 20041 20042 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S 13 20043 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M 0x00002000 20044 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_GET(_var) \ 20045 (((_var) & HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S) 20046 20047 #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_SET(_var, _val) \ 20048 do { \ 20049 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID, _val); \ 20050 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S)); \ 20051 } while (0) 20052 20053 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_S 16 20054 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_M 0x00ff0000 20055 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \ 20056 (((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S) 20057 20058 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S 14 20059 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M 0x0000c000 20060 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \ 20061 (((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S) 20062 20063 #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \ 20064 do { \ 20065 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val); \ 20066 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \ 20067 } while (0) 20068 20069 #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \ 20070 do { \ 20071 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val); \ 20072 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)); \ 20073 } while (0) 20074 20075 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_S 24 20076 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_M 0x03000000 20077 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_GET(_var) \ 20078 (((_var) & HTT_RX_PEER_META_DATA_V1_LMAC_ID_M) >> HTT_RX_PEER_META_DATA_V1_LMAC_ID_S) 20079 20080 #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_SET(_var, _val) \ 20081 do { \ 20082 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LMAC_ID, _val); \ 20083 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LMAC_ID_S)); \ 20084 } while (0) 20085 20086 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_S 26 20087 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_M 0x1c000000 20088 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_GET(_var) \ 20089 (((_var) & HTT_RX_PEER_META_DATA_V1_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1_CHIP_ID_S) 20090 20091 #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_SET(_var, _val) \ 20092 do { \ 20093 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_CHIP_ID, _val); \ 20094 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ 20095 } while (0) 20096 20097 /** 20098 * @brief target -> RX PEER METADATA V1A format 20099 * Host will know the peer metadata version from the wmi_service_ready_ext2 20100 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20101 * and will confirm to the target which peer metadata version to use in the 20102 * wmi_init message. 20103 * 20104 * The following diagram shows the format of the RX PEER METADATA V1A format. 20105 * 20106 * |31 29|28 26|25 22|21 14| 13 |12 0| 20107 * |-------------------------------------------------------------------| 20108 * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20109 * |-------------------------------------------------------------------| 20110 */ 20111 PREPACK struct htt_rx_peer_metadata_v1a { 20112 A_UINT32 20113 peer_id: 13, 20114 ml_peer_valid: 1, 20115 vdev_id: 8, 20116 logical_link_id: 4, 20117 chip_id: 3, 20118 reserved2: 3; 20119 } POSTPACK; 20120 20121 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 20122 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff 20123 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ 20124 (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) 20125 20126 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ 20127 do { \ 20128 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ 20129 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ 20130 } while (0) 20131 20132 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 20133 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 20134 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ 20135 (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) 20136 20137 #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ 20138 do { \ 20139 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ 20140 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ 20141 } while (0) 20142 20143 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 20144 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 20145 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ 20146 (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) 20147 20148 #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ 20149 do { \ 20150 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ 20151 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ 20152 } while (0) 20153 20154 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 20155 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 20156 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ 20157 (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) 20158 20159 #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ 20160 do { \ 20161 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ 20162 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ 20163 } while (0) 20164 20165 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 20166 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 20167 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ 20168 (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) 20169 20170 #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ 20171 do { \ 20172 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ 20173 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ 20174 } while (0) 20175 20176 20177 /** 20178 * @brief target -> RX PEER METADATA V1B format 20179 * Host will know the peer metadata version from the wmi_service_ready_ext2 20180 * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, 20181 * and will confirm to the target which peer metadata version to use in the 20182 * wmi_init message. 20183 * 20184 * The following diagram shows the format of the RX PEER METADATA V1B format. 20185 * 20186 * |31 29|28 26|25 22|21 14| 13 |12 0| 20187 * |--------------------------------------------------------------| 20188 * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| 20189 * |--------------------------------------------------------------| 20190 */ 20191 PREPACK struct htt_rx_peer_metadata_v1b { 20192 A_UINT32 20193 peer_id: 13, 20194 ml_peer_valid: 1, 20195 vdev_id: 8, 20196 hw_link_id: 4, 20197 chip_id: 3, 20198 reserved2: 3; 20199 } POSTPACK; 20200 20201 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 20202 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff 20203 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ 20204 (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) 20205 20206 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ 20207 do { \ 20208 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ 20209 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ 20210 } while (0) 20211 20212 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 20213 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 20214 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ 20215 (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) 20216 20217 #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ 20218 do { \ 20219 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ 20220 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ 20221 } while (0) 20222 20223 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 20224 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 20225 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ 20226 (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) 20227 20228 #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ 20229 do { \ 20230 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ 20231 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ 20232 } while (0) 20233 20234 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 20235 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 20236 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ 20237 (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) 20238 20239 #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ 20240 do { \ 20241 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ 20242 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ 20243 } while (0) 20244 20245 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 20246 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 20247 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ 20248 (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) 20249 20250 #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ 20251 do { \ 20252 HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ 20253 ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ 20254 } while (0) 20255 20256 /* generic variables for masks and shifts for various fields */ 20257 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; 20258 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; 20259 20260 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; 20261 extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; 20262 20263 /* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ 20264 extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); 20265 extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); 20266 20267 extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); 20268 extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); 20269 20270 extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); 20271 extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); 20272 20273 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); 20274 extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20275 20276 extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); 20277 extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); 20278 20279 extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); 20280 extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); 20281 20282 extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); 20283 extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); 20284 20285 20286 /* 20287 * In some systems, the host SW wants to specify priorities between 20288 * different MSDU / flow queues within the same peer-TID. 20289 * The below enums are used for the host to identify to the target 20290 * which MSDU queue's priority it wants to adjust. 20291 */ 20292 20293 /* 20294 * The MSDUQ index describe index of TCL HW, where each index is 20295 * used for queuing particular types of MSDUs. 20296 * The different MSDU queue types are defined in HTT_MSDU_QTYPE. 20297 */ 20298 enum HTT_MSDUQ_INDEX { 20299 HTT_MSDUQ_INDEX_NON_UDP, /* NON UDP MSDUQ index */ 20300 HTT_MSDUQ_INDEX_UDP, /* UDP MSDUQ index */ 20301 20302 HTT_MSDUQ_INDEX_CUSTOM_PRIO_0, /* Latency priority 0 index */ 20303 HTT_MSDUQ_INDEX_CUSTOM_PRIO_1, /* Latency priority 1 index */ 20304 20305 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_0, /* High num TID cases/ MLO dedicate link cases */ 20306 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_1, /* High num TID cases/ MLO dedicate link cases */ 20307 20308 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_2, /* High num TID cases/ MLO dedicate link cases */ 20309 HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_3, /* High num TID cases/ MLO dedicate link cases */ 20310 20311 HTT_MSDUQ_MAX_INDEX, 20312 }; 20313 20314 /* MSDU qtype definition */ 20315 enum HTT_MSDU_QTYPE { 20316 /* 20317 * The LATENCY_CRIT_0 and LATENCY_CRIT_1 queue types don't have a fixed 20318 * relative priority. Instead, the relative priority of CRIT_0 versus 20319 * CRIT_1 is controlled by the FW, through the configuration parameters 20320 * it applies to the queues. 20321 */ 20322 HTT_MSDU_QTYPE_LATENCY_CRIT_0, /* Specified MSDUQ index used for latency critical 0 */ 20323 HTT_MSDU_QTYPE_LATENCY_CRIT_1, /* Specified MSDUQ index used for latency critical 1 */ 20324 HTT_MSDU_QTYPE_UDP, /* Specifies MSDUQ index used for UDP flow */ 20325 HTT_MSDU_QTYPE_NON_UDP, /* Specifies MSDUQ index used for non-udp flow */ 20326 HTT_MSDU_QTYPE_HOL, /* Specified MSDUQ index used for Head of Line */ 20327 HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */ 20328 HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */ 20329 HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */ 20330 20331 20332 /* New MSDU_QTYPE should be added above this line */ 20333 /* 20334 * Below QTYPE_MAX will increase if additional QTYPEs are defined 20335 * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in 20336 * any host/target message definitions. The QTYPE_MAX value can 20337 * only be used internally within the host or within the target. 20338 * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX 20339 * it must regard the unexpected value as a default qtype value, 20340 * or ignore it. 20341 */ 20342 HTT_MSDU_QTYPE_MAX, 20343 HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */ 20344 }; 20345 20346 enum HTT_MSDUQ_LEGACY_FLOW_INDEX { 20347 HTT_MSDUQ_LEGACY_HI_PRI_FLOW_INDEX = 0, 20348 HTT_MSDUQ_LEGACY_LO_PRI_FLOW_INDEX = 1, 20349 HTT_MSDUQ_LEGACY_UDP_FLOW_INDEX = 2, 20350 HTT_MSDUQ_LEGACY_NON_UDP_FLOW_INDEX = 3, 20351 }; 20352 20353 /** 20354 * @brief target -> host mlo timestamp offset indication 20355 * 20356 * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 20357 * 20358 * @details 20359 * The following field definitions describe the format of the HTT target 20360 * to host mlo timestamp offset indication message. 20361 * 20362 * 20363 * |31 16|15 12|11 10|9 8|7 0 | 20364 * |----------------------------------------------------------------------| 20365 * | mac_clk_freq_mhz | rsvd |chip_id|pdev_id| msg type | 20366 * |----------------------------------------------------------------------| 20367 * | Sync time stamp lo in us | 20368 * |----------------------------------------------------------------------| 20369 * | Sync time stamp hi in us | 20370 * |----------------------------------------------------------------------| 20371 * | mlo time stamp offset lo in us | 20372 * |----------------------------------------------------------------------| 20373 * | mlo time stamp offset hi in us | 20374 * |----------------------------------------------------------------------| 20375 * | mlo time stamp offset clocks in clock ticks | 20376 * |----------------------------------------------------------------------| 20377 * |31 26|25 16|15 0 | 20378 * |rsvd2 | mlo time stamp | mlo time stamp compensation in us | 20379 * | | compensation in clks | | 20380 * |----------------------------------------------------------------------| 20381 * |31 22|21 0 | 20382 * | rsvd 3 | mlo time stamp comp timer period | 20383 * |----------------------------------------------------------------------| 20384 * The message is interpreted as follows: 20385 * 20386 * dword0 - b'0:7 - msg_type: This will be set to 20387 * HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 20388 * value: 0x28 20389 * 20390 * dword0 - b'9:8 - pdev_id 20391 * 20392 * dword0 - b'11:10 - chip_id 20393 * 20394 * dword0 - b'15:12 - rsvd1: Reserved for future use 20395 * 20396 * dword0 - b'31:16 - mac clock frequency of the mac HW block in MHz 20397 * 20398 * dword1 - b'31:0 - lower 32 bits of the WLAN global time stamp (in us) at 20399 * which last sync interrupt was received 20400 * 20401 * dword2 - b'31:0 - upper 32 bits of the WLAN global time stamp (in us) at 20402 * which last sync interrupt was received 20403 * 20404 * dword3 - b'31:0 - lower 32 bits of the MLO time stamp offset in us 20405 * 20406 * dword4 - b'31:0 - upper 32 bits of the MLO time stamp offset in us 20407 * 20408 * dword5 - b'31:0 - MLO time stamp offset in clock ticks for sub us 20409 * 20410 * dword6 - b'15:0 - MLO time stamp compensation applied in us 20411 * 20412 * dword6 - b'25:16 - MLO time stamp compensation applied in clock ticks 20413 * for sub us resolution 20414 * 20415 * dword6 - b'31:26 - rsvd2: Reserved for future use 20416 * 20417 * dword7 - b'21:0 - period of MLO compensation timer at which compensation 20418 * is applied, in us 20419 * 20420 * dword7 - b'31:22 - rsvd3: Reserved for future use 20421 */ 20422 20423 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M 0x000000FF 20424 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S 0 20425 20426 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M 0x00000300 20427 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S 8 20428 20429 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M 0x00000C00 20430 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S 10 20431 20432 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M 0xFFFF0000 20433 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S 16 20434 20435 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M 0x0000FFFF 20436 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S 0 20437 20438 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M 0x03FF0000 20439 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S 16 20440 20441 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M 0x003FFFFF 20442 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S 0 20443 20444 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_GET(_var) \ 20445 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S) 20446 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_SET(_var, _val) \ 20447 do { \ 20448 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE, _val); \ 20449 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)); \ 20450 } while (0) 20451 20452 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_GET(_var) \ 20453 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S) 20454 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_SET(_var, _val) \ 20455 do { \ 20456 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID, _val); \ 20457 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)); \ 20458 } while (0) 20459 20460 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_GET(_var) \ 20461 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S) 20462 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_SET(_var, _val) \ 20463 do { \ 20464 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID, _val); \ 20465 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)); \ 20466 } while (0) 20467 20468 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_GET(_var) \ 20469 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M) >> \ 20470 HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S) 20471 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_SET(_var, _val) \ 20472 do { \ 20473 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ, _val); \ 20474 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)); \ 20475 } while (0) 20476 20477 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_GET(_var) \ 20478 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M) >> \ 20479 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S) 20480 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_SET(_var, _val) \ 20481 do { \ 20482 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US, _val); \ 20483 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)); \ 20484 } while (0) 20485 20486 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_GET(_var) \ 20487 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M) >> \ 20488 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S) 20489 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_SET(_var, _val) \ 20490 do { \ 20491 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS, _val); \ 20492 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)); \ 20493 } while (0) 20494 20495 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_GET(_var) \ 20496 (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M) >> \ 20497 HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S) 20498 #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_SET(_var, _val) \ 20499 do { \ 20500 HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US, _val); \ 20501 ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)); \ 20502 } while (0) 20503 20504 typedef struct { 20505 A_UINT32 msg_type: 8, /* bits 7:0 */ 20506 pdev_id: 2, /* bits 9:8 */ 20507 chip_id: 2, /* bits 11:10 */ 20508 reserved1: 4, /* bits 15:12 */ 20509 mac_clk_freq_mhz: 16; /* bits 31:16 */ 20510 A_UINT32 sync_timestamp_lo_us; 20511 A_UINT32 sync_timestamp_hi_us; 20512 A_UINT32 mlo_timestamp_offset_lo_us; 20513 A_UINT32 mlo_timestamp_offset_hi_us; 20514 A_UINT32 mlo_timestamp_offset_clks; 20515 A_UINT32 mlo_timestamp_comp_us: 16, /* bits 15:0 */ 20516 mlo_timestamp_comp_clks: 10, /* bits 25:16 */ 20517 reserved2: 6; /* bits 31:26 */ 20518 A_UINT32 mlo_timestamp_comp_timer_period_us: 22, /* bits 21:0 */ 20519 reserved3: 10; /* bits 31:22 */ 20520 } htt_t2h_mlo_offset_ind_t; 20521 20522 /* 20523 * @brief target -> host VDEV TX RX STATS 20524 * 20525 * MSG_TYPE => HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND 20526 * 20527 * @details 20528 * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message is sent by the target 20529 * every periodic interval programmed in HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG. 20530 * After the host sends an initial HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG, 20531 * this HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message will be sent 20532 * periodically by target even in the absence of any further HTT request 20533 * messages from host. 20534 * 20535 * The message is formatted as follows: 20536 * 20537 * |31 16|15 8|7 0| 20538 * |---------------------------------+----------------+----------------| 20539 * | payload_size | pdev_id | msg_type | 20540 * |---------------------------------+----------------+----------------| 20541 * | reserved0 | 20542 * |-------------------------------------------------------------------| 20543 * | reserved1 | 20544 * |-------------------------------------------------------------------| 20545 * | reserved2 | 20546 * |-------------------------------------------------------------------| 20547 * | | 20548 * | VDEV specific Tx Rx stats info | 20549 * | | 20550 * |-------------------------------------------------------------------| 20551 * 20552 * The message is interpreted as follows: 20553 * dword0 - b'0:7 - msg_type: This will be set to 0x2c 20554 * (HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND) 20555 * b'8:15 - pdev_id 20556 * b'16:31 - size in bytes of the payload that follows the 16-byte 20557 * message header fields (msg_type through reserved2) 20558 * dword1 - b'0:31 - reserved0. 20559 * dword2 - b'0:31 - reserved1. 20560 * dword3 - b'0:31 - reserved2. 20561 */ 20562 typedef struct { 20563 A_UINT32 msg_type: 8, 20564 pdev_id: 8, 20565 payload_size: 16; 20566 A_UINT32 reserved0; 20567 A_UINT32 reserved1; 20568 A_UINT32 reserved2; 20569 } htt_t2h_vdevs_txrx_stats_periodic_hdr_t; 20570 20571 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_HDR_SIZE 16 20572 20573 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M 0x0000FF00 20574 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S 8 20575 20576 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 20577 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S) 20578 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 20579 do { \ 20580 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID, _val); \ 20581 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S)); \ 20582 } while (0) 20583 20584 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M 0xFFFF0000 20585 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S 16 20586 20587 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_GET(_var) \ 20588 (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S) 20589 #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_SET(_var, _val) \ 20590 do { \ 20591 HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE, _val); \ 20592 ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S)); \ 20593 } while (0) 20594 20595 /* SOC related stats */ 20596 typedef struct { 20597 htt_tlv_hdr_t tlv_hdr; 20598 20599 /* When TQM is not able to find the peers during Tx, then it drops the packets 20600 * This can be due to either the peer is deleted or deletion is ongoing 20601 * */ 20602 A_UINT32 inv_peers_msdu_drop_count_lo; 20603 A_UINT32 inv_peers_msdu_drop_count_hi; 20604 } htt_t2h_soc_txrx_stats_common_tlv; 20605 20606 /* VDEV HW Tx/Rx stats */ 20607 typedef struct { 20608 htt_tlv_hdr_t tlv_hdr; 20609 A_UINT32 vdev_id; 20610 20611 /* Rx msdu byte cnt */ 20612 A_UINT32 rx_msdu_byte_cnt_lo; 20613 A_UINT32 rx_msdu_byte_cnt_hi; 20614 20615 /* Rx msdu cnt */ 20616 A_UINT32 rx_msdu_cnt_lo; 20617 A_UINT32 rx_msdu_cnt_hi; 20618 20619 /* tx msdu byte cnt */ 20620 A_UINT32 tx_msdu_byte_cnt_lo; 20621 A_UINT32 tx_msdu_byte_cnt_hi; 20622 20623 /* tx msdu cnt */ 20624 A_UINT32 tx_msdu_cnt_lo; 20625 A_UINT32 tx_msdu_cnt_hi; 20626 20627 /* tx excessive retry discarded msdu cnt */ 20628 A_UINT32 tx_msdu_excessive_retry_discard_cnt_lo; 20629 A_UINT32 tx_msdu_excessive_retry_discard_cnt_hi; 20630 20631 /* TX congestion ctrl msdu drop cnt */ 20632 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_lo; 20633 A_UINT32 tx_msdu_cong_ctrl_drop_cnt_hi; 20634 20635 /* discarded tx msdus cnt coz of time to live expiry */ 20636 A_UINT32 tx_msdu_ttl_expire_drop_cnt_lo; 20637 A_UINT32 tx_msdu_ttl_expire_drop_cnt_hi; 20638 20639 /* tx excessive retry discarded msdu byte cnt */ 20640 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_lo; 20641 A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_hi; 20642 20643 /* TX congestion ctrl msdu drop byte cnt */ 20644 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_lo; 20645 A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_hi; 20646 20647 /* discarded tx msdus byte cnt coz of time to live expiry */ 20648 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_lo; 20649 A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_hi; 20650 20651 /* TQM bypass frame cnt */ 20652 A_UINT32 tqm_bypass_frame_cnt_lo; 20653 A_UINT32 tqm_bypass_frame_cnt_hi; 20654 20655 /* TQM bypass byte cnt */ 20656 A_UINT32 tqm_bypass_byte_cnt_lo; 20657 A_UINT32 tqm_bypass_byte_cnt_hi; 20658 } htt_t2h_vdev_txrx_stats_hw_stats_tlv; 20659 20660 /* 20661 * MSG_TYPE => HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF 20662 * 20663 * @details 20664 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF message is sent by the target in 20665 * response to a SAWF_DEF_QUEUES_MAP_REPORT_REQ from the host. 20666 * The SAWF_DEF_QUEUES_MAP_REPORT_CONF will show which service class 20667 * the default MSDU queues of each of the specified TIDs for the peer 20668 * specified in the SAWF_DEF_QUEUES_MAP_REPORT_REQ message are linked to. 20669 * If the default MSDU queues of a given TID within the peer are not linked 20670 * to a service class, the svc_class_id field for that TID will have a 20671 * 0xff HTT_SAWF_SVC_CLASS_INVALID_ID value to indicate the default MSDU 20672 * queues for that TID are not mapped to any service class. 20673 * 20674 * |31 16|15 8|7 0| 20675 * |------------------------------+--------------+--------------| 20676 * | peer ID | reserved | msg type | 20677 * |------------------------------+--------------+------+-------| 20678 * | reserved | svc class ID | TID | 20679 * |------------------------------------------------------------| 20680 * ... 20681 * |------------------------------------------------------------| 20682 * | reserved | svc class ID | TID | 20683 * |------------------------------------------------------------| 20684 * Header fields: 20685 * dword0 - b'7:0 - msg_type: This will be set to 20686 * 0x2d (HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF) 20687 * b'31:16 - peer ID 20688 * dword1 - b'7:0 - TID 20689 * b'15:8 - svc class ID 20690 * (dword2, etc. same format as dword1) 20691 */ 20692 20693 #define HTT_SAWF_SVC_CLASS_INVALID_ID 0xff 20694 20695 PREPACK struct htt_t2h_sawf_def_queues_map_report_conf { 20696 A_UINT32 msg_type :8, 20697 reserved0 :8, 20698 peer_id :16; 20699 struct { 20700 A_UINT32 tid :8, 20701 svc_class_id :8, 20702 reserved1 :16; 20703 } tid_reports[1/*or more*/]; 20704 } POSTPACK; 20705 20706 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_HDR_BYTES 4 /* msg_type, peer_id */ 20707 #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_ELEM_BYTES 4 /* TID, svc_class_id */ 20708 20709 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M 0xFFFF0000 20710 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S 16 20711 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_GET(_var) \ 20712 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M) >> \ 20713 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S) 20714 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_SET(_var, _val) \ 20715 do { \ 20716 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID, _val); \ 20717 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S)); \ 20718 } while (0) 20719 20720 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M 0x000000FF 20721 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S 0 20722 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_GET(_var) \ 20723 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M) >> \ 20724 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S) 20725 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_SET(_var, _val) \ 20726 do { \ 20727 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID, _val); \ 20728 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S)); \ 20729 } while (0) 20730 20731 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M 0x0000FF00 20732 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S 8 20733 #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_GET(_var) \ 20734 (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M) >> \ 20735 HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S) 20736 #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_SET(_var, _val) \ 20737 do { \ 20738 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID, _val); \ 20739 ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S)); \ 20740 } while (0) 20741 20742 20743 /* 20744 * MSG_TYPE => HTT_T2H_SAWF_MSDUQ_INFO_IND 20745 * 20746 * @details 20747 * When SAWF is enabled and a flow is mapped to a policy during the traffic 20748 * flow if the flow is seen the associated service class is conveyed to the 20749 * target via TCL Data Command. Target on the other hand internally creates the 20750 * MSDUQ. Once the target creates the MSDUQ the target sends the information 20751 * of the newly created MSDUQ and some other identifiers to uniquely identity 20752 * the newly created MSDUQ 20753 * 20754 * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0| 20755 * |------------------------------+------------------------+--------------| 20756 * | peer ID | HTT qtype | msg type | 20757 * |---------------------------------+--------------+--+---+-------+------| 20758 * | reserved |AST list index|FO|WC | HLOS | remap| 20759 * | | | | | TID | TID | 20760 * |---------------------+------------------------------------------------| 20761 * | reserved1 | tgt_opaque_id | 20762 * |---------------------+------------------------------------------------| 20763 * 20764 * Header fields: 20765 * 20766 * dword0 - b'7:0 - msg_type: This will be set to 20767 * 0x2e (HTT_T2H_SAWF_MSDUQ_INFO_IND) 20768 * b'15:8 - HTT qtype 20769 * b'31:16 - peer ID 20770 * 20771 * dword1 - b'3:0 - remap TID, as assigned in firmware 20772 * b'7:4 - HLOS TID, as sent by host in TCL Data Command 20773 * hlos_tid : Common to Lithium and Beryllium 20774 * b'9:8 - who_classify_info_sel (WC), as sent by host in 20775 * TCL Data Command : Beryllium 20776 * b10 - flow_override (FO), as sent by host in 20777 * TCL Data Command: Beryllium 20778 * b11:14 - ast_list_idx 20779 * Array index into the list of extension AST entries 20780 * (not the actual AST 16-bit index). 20781 * The ast_list_idx is one-based, with the following 20782 * range of values: 20783 * - legacy targets supporting 16 user-defined 20784 * MSDU queues: 1-2 20785 * - legacy targets supporting 48 user-defined 20786 * MSDU queues: 1-6 20787 * - new targets: 0 (peer_id is used instead) 20788 * Note that since ast_list_idx is one-based, 20789 * the host will need to subtract 1 to use it as an 20790 * index into a list of extension AST entries. 20791 * b15:31 - reserved 20792 * 20793 * dword2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a 20794 * unique MSDUQ id in firmware 20795 * b'24:31 - reserved1 20796 */ 20797 PREPACK struct htt_t2h_sawf_msduq_event { 20798 A_UINT32 msg_type : 8, 20799 htt_qtype : 8, 20800 peer_id :16; 20801 20802 A_UINT32 remap_tid : 4, 20803 hlos_tid : 4, 20804 who_classify_info_sel : 2, 20805 flow_override : 1, 20806 ast_list_idx : 4, 20807 reserved :17; 20808 20809 A_UINT32 tgt_opaque_id :24, 20810 reserved1 : 8; 20811 } POSTPACK; 20812 20813 #define HTT_SAWF_MSDUQ_INFO_SIZE (sizeof(struct htt_t2h_sawf_msduq_event)) 20814 20815 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M 0x0000FF00 20816 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S 8 20817 20818 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_GET(_var) \ 20819 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M) >> \ 20820 HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S) 20821 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_SET(_var, _val) \ 20822 do { \ 20823 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE, _val); \ 20824 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S));\ 20825 } while (0) 20826 20827 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M 0xFFFF0000 20828 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S 16 20829 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_GET(_var) \ 20830 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M) >> \ 20831 HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S) 20832 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_SET(_var, _val) \ 20833 do { \ 20834 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID, _val); \ 20835 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S)); \ 20836 } while (0) 20837 20838 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M 0x0000000F 20839 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S 0 20840 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_GET(_var) \ 20841 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M) >> \ 20842 HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S) 20843 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_SET(_var, _val) \ 20844 do { \ 20845 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID, _val); \ 20846 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S)); \ 20847 } while (0) 20848 20849 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M 0x000000F0 20850 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S 4 20851 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_GET(_var) \ 20852 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M) >> \ 20853 HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S) 20854 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_SET(_var, _val) \ 20855 do { \ 20856 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID, _val); \ 20857 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S)); \ 20858 } while (0) 20859 20860 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M 0x00000300 20861 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S 8 20862 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_GET(_var) \ 20863 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M) >> \ 20864 HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S) 20865 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_SET(_var, _val) \ 20866 do { \ 20867 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL, _val); \ 20868 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S)); \ 20869 } while (0) 20870 20871 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M 0x00000400 20872 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S 10 20873 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_GET(_var) \ 20874 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M) >> \ 20875 HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S) 20876 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_SET(_var, _val) \ 20877 do { \ 20878 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE, _val); \ 20879 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)); \ 20880 } while (0) 20881 20882 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M 0x00007800 20883 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S 11 20884 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_GET(_var) \ 20885 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M) >> \ 20886 HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S) 20887 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_SET(_var, _val) \ 20888 do { \ 20889 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX, _val); \ 20890 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)); \ 20891 } while (0) 20892 20893 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M 0x00FFFFFF 20894 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S 0 20895 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_GET(_var) \ 20896 (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID) >> \ 20897 HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S) 20898 #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_SET(_var, _val) \ 20899 do { \ 20900 HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID, _val); \ 20901 ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S)); \ 20902 } while (0) 20903 20904 20905 /** 20906 * @brief target -> PPDU id format indication 20907 * 20908 * MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND 20909 * 20910 * @details 20911 * The following field definitions describe the format of the HTT target 20912 * to host PPDU ID format indication message. 20913 * hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command. 20914 * ring_id :- HWSCH ring id in which this PPDU was enqueued. 20915 * seq_idx :- Sequence control index of this PPDU. 20916 * link_id :- HW link ID of the link in which the PPDU was enqueued. 20917 * seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.) 20918 * tqm_cmd:- 20919 * 20920 * |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 | 20921 * |--------------------------------------------------+------------------------| 20922 * | rsvd0 | msg type | 20923 * |-----+----------+----------+---------+-----+----------+----------+---------| 20924 * |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V | 20925 * |-----+----------+----------+---------+-----+----------+----------+---------| 20926 * |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V| 20927 * |-----+----------+----------+---------+-----+----------+----------+---------| 20928 * |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V| 20929 * |-----+----------+----------+---------+-----+----------+----------+---------| 20930 * |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V | 20931 * |-----+----------+----------+---------+-----+----------+----------+---------| 20932 * Where: OF = bit offset, NB = number of bits, V = valid 20933 * The message is interpreted as follows: 20934 * 20935 * dword0 - b'7:0 - msg_type: This will be set to 20936 * HTT_T2H_PPDU_ID_FMT_IND 20937 * value: 0x30 20938 * 20939 * dword0 - b'31:8 - reserved 20940 * 20941 * dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not 20942 * 20943 * dword1 - b'5:1 - number of bits in hwsch_cmd_id 20944 * 20945 * dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits) 20946 * 20947 * dword1 - b'15:11 - reserved for future use 20948 * 20949 * dword1 - b'16:16 - field to indicate whether ring_id is valid or not 20950 * 20951 * dword1 - b'21:17 - number of bits in ring_id 20952 * 20953 * dword1 - b'26:22 - offset of ring_id (in number of bits) 20954 * 20955 * dword1 - b'31:27 - reserved for future use 20956 * 20957 * dword2 - b'0:0 - field to indicate whether sequence index is valid or not 20958 * 20959 * dword2 - b'5:1 - number of bits in sequence index 20960 * 20961 * dword2 - b'10:6 - offset of sequence index (in number of bits) 20962 * 20963 * dword2 - b'15:11 - reserved for future use 20964 * 20965 * dword2 - b'16:16 - field to indicate whether link_id is valid or not 20966 * 20967 * dword2 - b'21:17 - number of bits in link_id 20968 * 20969 * dword2 - b'26:22 - offset of link_id (in number of bits) 20970 * 20971 * dword2 - b'31:27 - reserved for future use 20972 * 20973 * dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not 20974 * 20975 * dword3 - b'5:1 - number of bits in seq_cmd_type 20976 * 20977 * dword3 - b'10:6 - offset of seq_cmd_type (in number of bits) 20978 * 20979 * dword3 - b'15:11 - reserved for future use 20980 * 20981 * dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not 20982 * 20983 * dword3 - b'21:17 - number of bits in tqm_cmd 20984 * 20985 * dword3 - b'26:22 - offset of tqm_cmd (in number of bits) 20986 * 20987 * dword3 - b'31:27 - reserved for future use 20988 * 20989 * dword4 - b'0:0 - field to indicate whether mac_id is valid or not 20990 * 20991 * dword4 - b'5:1 - number of bits in mac_id 20992 * 20993 * dword4 - b'10:6 - offset of mac_id (in number of bits) 20994 * 20995 * dword4 - b'15:11 - reserved for future use 20996 * 20997 * dword4 - b'16:16 - field to indicate whether crc is valid or not 20998 * 20999 * dword4 - b'21:17 - number of bits in crc 21000 * 21001 * dword4 - b'26:22 - offset of crc (in number of bits) 21002 * 21003 * dword4 - b'31:27 - reserved for future use 21004 * 21005 */ 21006 21007 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001 21008 #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0 21009 21010 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E 21011 #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1 21012 21013 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0 21014 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6 21015 21016 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000 21017 #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16 21018 21019 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000 21020 #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17 21021 21022 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000 21023 #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22 21024 21025 21026 /* macros for accessing lower 16 bits in dword */ 21027 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \ 21028 do { \ 21029 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \ 21030 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \ 21031 } while (0) 21032 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \ 21033 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S) 21034 21035 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \ 21036 do { \ 21037 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \ 21038 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \ 21039 } while (0) 21040 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \ 21041 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S) 21042 21043 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \ 21044 do { \ 21045 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \ 21046 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \ 21047 } while (0) 21048 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \ 21049 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S) 21050 21051 /* macros for accessing upper 16 bits in dword */ 21052 #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \ 21053 do { \ 21054 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \ 21055 (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \ 21056 } while (0) 21057 #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \ 21058 (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S) 21059 21060 #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \ 21061 do { \ 21062 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \ 21063 (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \ 21064 } while (0) 21065 #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \ 21066 (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S) 21067 21068 #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \ 21069 do { \ 21070 HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \ 21071 (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \ 21072 } while (0) 21073 #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \ 21074 (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S) 21075 21076 21077 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \ 21078 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21079 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \ 21080 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21081 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \ 21082 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21083 21084 #define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \ 21085 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21086 #define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \ 21087 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21088 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \ 21089 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21090 21091 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \ 21092 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21093 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \ 21094 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21095 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \ 21096 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21097 21098 #define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \ 21099 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21100 #define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \ 21101 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21102 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \ 21103 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21104 21105 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \ 21106 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21107 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \ 21108 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21109 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \ 21110 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21111 21112 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \ 21113 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21114 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \ 21115 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21116 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \ 21117 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21118 21119 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \ 21120 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0 21121 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \ 21122 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0 21123 #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \ 21124 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0 21125 21126 #define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \ 21127 HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16 21128 #define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \ 21129 HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16 21130 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \ 21131 HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16 21132 21133 21134 /* offsets in number dwords */ 21135 #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1 21136 #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1 21137 #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2 21138 #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2 21139 #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3 21140 #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3 21141 #define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4 21142 #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4 21143 21144 21145 typedef struct { 21146 A_UINT32 msg_type: 8, /* bits 7:0 */ 21147 rsvd0: 24;/* bits 31:8 */ 21148 A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */ 21149 hwsch_cmd_id_bits: 5, /* bits 5:1 */ 21150 hwsch_cmd_id_offset: 5, /* bits 10:6 */ 21151 rsvd1: 5, /* bits 15:11 */ 21152 ring_id_valid: 1, /* bits 16:16 */ 21153 ring_id_bits: 5, /* bits 21:17 */ 21154 ring_id_offset: 5, /* bits 26:22 */ 21155 rsvd2: 5; /* bits 31:27 */ 21156 A_UINT32 seq_idx_valid: 1, /* bits 0:0 */ 21157 seq_idx_bits: 5, /* bits 5:1 */ 21158 seq_idx_offset: 5, /* bits 10:6 */ 21159 rsvd3: 5, /* bits 15:11 */ 21160 link_id_valid: 1, /* bits 16:16 */ 21161 link_id_bits: 5, /* bits 21:17 */ 21162 link_id_offset: 5, /* bits 26:22 */ 21163 rsvd4: 5; /* bits 31:27 */ 21164 A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */ 21165 seq_cmd_type_bits: 5, /* bits 5:1 */ 21166 seq_cmd_type_offset: 5, /* bits 10:6 */ 21167 rsvd5: 5, /* bits 15:11 */ 21168 tqm_cmd_valid: 1, /* bits 16:16 */ 21169 tqm_cmd_bits: 5, /* bits 21:17 */ 21170 tqm_cmd_offset: 5, /* bits 26:12 */ 21171 rsvd6: 5; /* bits 31:27 */ 21172 A_UINT32 mac_id_valid: 1, /* bits 0:0 */ 21173 mac_id_bits: 5, /* bits 5:1 */ 21174 mac_id_offset: 5, /* bits 10:6 */ 21175 rsvd8: 5, /* bits 15:11 */ 21176 crc_valid: 1, /* bits 16:16 */ 21177 crc_bits: 5, /* bits 21:17 */ 21178 crc_offset: 5, /* bits 26:12 */ 21179 rsvd9: 5; /* bits 31:27 */ 21180 } htt_t2h_ppdu_id_fmt_ind_t; 21181 21182 21183 /** 21184 * @brief target -> host RX_CCE_SUPER_RULE setup done message 21185 * 21186 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE 21187 * 21188 * @details 21189 * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target 21190 * when RX_CCE_SUPER_RULE setup is done 21191 * 21192 * This message shows the configuration results after the setup operation. 21193 * It will always be sent to host. 21194 * The message would appear as follows: 21195 * 21196 * |31 24|23 16|15 8|7 0| 21197 * |-----------------+-----------------+----------------+----------------| 21198 * | result | response_type | pdev_id | msg_type | 21199 * |---------------------------------------------------------------------| 21200 * 21201 * The message is interpreted as follows: 21202 * dword0 - b'0:7 - msg_type: This will be set to 0x33 21203 * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) 21204 * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on 21205 * b'16:23 - response_type: Indicate the response type of this setup 21206 * done msg 21207 * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, 21208 * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST 21209 * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21210 * response to HTT_RX_CCE_SUPER_RULE_INSTALL 21211 * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21212 * response to HTT_RX_CCE_SUPER_RULE_RELEASE 21213 * b'24:31 - result: Indicate result of setup operation 21214 * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE: 21215 * b'24 - is_rule_enough: indicate if there are 21216 * enough free cce rule slots 21217 * 0: not enough 21218 * 1: enough 21219 * b'25:31 - avail_rule_num: indicate the number of 21220 * remaining free cce rule slots, only makes sense 21221 * when is_rule_enough = 0 21222 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE: 21223 * b'24 - cfg_result_0: indicate the config result 21224 * of RX_CCE_SUPER_RULE_0 21225 * 0: Install/Uninstall fails 21226 * 1: Install/Uninstall succeeds 21227 * b'25 - cfg_result_1: indicate the config result 21228 * of RX_CCE_SUPER_RULE_1 21229 * 0: Install/Uninstall fails 21230 * 1: Install/Uninstall succeeds 21231 * b'26:31 - reserved 21232 * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE: 21233 * b'24 - cfg_result_0: indicate the config result 21234 * of RX_CCE_SUPER_RULE_0 21235 * 0: Release fails 21236 * 1: Release succeeds 21237 * b'25 - cfg_result_1: indicate the config result 21238 * of RX_CCE_SUPER_RULE_1 21239 * 0: Release fails 21240 * 1: Release succeeds 21241 * b'26:31 - reserved 21242 */ 21243 21244 enum htt_rx_cce_super_rule_setup_done_response_type { 21245 HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0, 21246 HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, 21247 HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, 21248 21249 /*All reply type should be before this*/ 21250 HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE, 21251 }; 21252 21253 PREPACK struct htt_rx_cce_super_rule_setup_done_t { 21254 A_UINT8 msg_type; 21255 A_UINT8 pdev_id; 21256 A_UINT8 response_type; 21257 union { 21258 struct { 21259 /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */ 21260 A_UINT8 is_rule_enough: 1, 21261 avail_rule_num: 7; 21262 }; 21263 struct { 21264 /* 21265 * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and 21266 * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE 21267 */ 21268 A_UINT8 cfg_result_0: 1, 21269 cfg_result_1: 1, 21270 rsvd: 6; 21271 }; 21272 } result; 21273 } POSTPACK; 21274 21275 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) 21276 21277 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 21278 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 21279 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ 21280 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ 21281 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) 21282 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ 21283 do { \ 21284 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ 21285 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ 21286 } while (0) 21287 21288 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 21289 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 21290 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ 21291 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ 21292 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) 21293 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ 21294 do { \ 21295 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ 21296 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ 21297 } while (0) 21298 21299 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000 21300 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24 21301 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ 21302 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ 21303 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S) 21304 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ 21305 do { \ 21306 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ 21307 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ 21308 } while (0) 21309 21310 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000 21311 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24 21312 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \ 21313 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \ 21314 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S) 21315 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \ 21316 do { \ 21317 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \ 21318 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \ 21319 } while (0) 21320 21321 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000 21322 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25 21323 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \ 21324 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \ 21325 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S) 21326 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \ 21327 do { \ 21328 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \ 21329 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \ 21330 } while (0) 21331 21332 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000 21333 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24 21334 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \ 21335 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \ 21336 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S) 21337 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \ 21338 do { \ 21339 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \ 21340 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \ 21341 } while (0) 21342 21343 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000 21344 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25 21345 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \ 21346 (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \ 21347 HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S) 21348 #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \ 21349 do { \ 21350 HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \ 21351 ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ 21352 } while (0) 21353 21354 /** 21355 * THE BELOW MESSAGE HAS BEEN DEPRECATED 21356 *====================================== 21357 * @brief target -> host CoDel MSDU queue latencies array configuration 21358 * 21359 * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND 21360 * 21361 * @details 21362 * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used 21363 * by the target to inform the host of the location and size of the DDR array of 21364 * per MSDU queue latency metrics. This array is updated by the host and 21365 * read by the target. The target uses these metric values to determine 21366 * which MSDU queues have latencies exceeding their CoDel latency target. 21367 * 21368 * |31 16|15 8|7 0| 21369 * |-------------------------------------------+----------| 21370 * | number of array elements | reserved | MSG_TYPE | 21371 * |-------------------------------------------+----------| 21372 * | array physical address, low bits | 21373 * |------------------------------------------------------| 21374 * | array physical address, high bits | 21375 * |------------------------------------------------------| 21376 * Header fields: 21377 * - MSG_TYPE 21378 * Bits 7:0 21379 * Purpose: Identifies this as a CoDel MSDU queue latencies 21380 * array configuration message. 21381 * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND) 21382 * - NUM_ELEM 21383 * Bits 31:16 21384 * Purpose: Inform the host of the length of the MSDU queue latencies array. 21385 * Value: Specifies the number of elements in the MSDU queue latency 21386 * metrics array. This value is the same as the maximum number of 21387 * MSDU queues supported by the target. 21388 * Since each array element is 16 bits, the size in bytes of the 21389 * MSDU queue latency metrics array is twice the number of elements. 21390 * - PADDR_LOW 21391 * Bits 31:0 21392 * Purpose: Inform the host of the MSDU queue latencies array's location. 21393 * Value: Lower 32 bits of the physical address of the MSDU queue latency 21394 * metrics array. 21395 * - PADDR_HIGH 21396 * Bits 31:0 21397 * Purpose: Inform the host of the MSDU queue latencies array's location. 21398 * Value: Upper 32 bits of the physical address of the MSDU queue latency 21399 * metrics array. 21400 */ 21401 typedef struct { 21402 A_UINT32 msg_type: 8, /* bits 7:0 */ 21403 reserved: 8, /* bits 15:8 */ 21404 num_elem: 16; /* bits 31:16 */ 21405 A_UINT32 paddr_low; 21406 A_UINT32 paddr_high; 21407 } htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */ 21408 21409 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ 21410 21411 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000 21412 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16 21413 21414 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \ 21415 (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \ 21416 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S) 21417 #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \ 21418 do { \ 21419 HTT_CHECK_SET_VAL( \ 21420 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \ 21421 ((_var) |= ((_val) << \ 21422 HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \ 21423 } while (0) 21424 21425 /* 21426 * This CoDel MSDU queue latencies array whose location and number of 21427 * elements are specified by this HTT_T2H message consists of 16-bit elements 21428 * that each specify a statistical summary (min) of a MSDU queue's latency, 21429 * using milliseconds units. 21430 */ 21431 #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 21432 21433 21434 /** 21435 * @brief target -> host rx completion indication message definition 21436 * 21437 * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND 21438 * 21439 * @details 21440 * The following diagram shows the format of the Rx completion indication sent 21441 * from the target to the host 21442 * 21443 * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| 21444 * |---------------+----------------------------+----------------| 21445 * | vdev_id | peer_id | msg_type | 21446 * hdr: |---------------+--------------------------+-+----------------| 21447 * | rsvd0 |F| msdu_cnt | 21448 * pyld: |==========================================+=+================| 21449 * MSDU 0 | buf addr lo (bits 31:0) | 21450 * |-----+--------------------------------------+----------------| 21451 * |rsvd1| SW buffer cookie | buf addr hi | 21452 * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| 21453 * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| 21454 * |-------------------------------------------------+---------+-| 21455 * | rsvd3 | err info|E| 21456 * |=================================================+=========+=| 21457 * MSDU 1 | buf addr lo (bits 31:0) | 21458 * : ... : 21459 * | rsvd3 | err info|E| 21460 * |-------------------------------------------------------------| 21461 * Where: 21462 * F = fragment 21463 * M = MPDU retry bit 21464 * R = raw MPDU frame 21465 * F = first MSDU in MPDU 21466 * L = last MSDU in MPDU 21467 * C = MSDU continuation 21468 * S = Souce Addr is valid 21469 * D = Dest Addr is valid 21470 * MC = Dest Addr is multicast / broadcast 21471 * W = is first MSDU after WoW wakeup 21472 * R2 = rsvd2 21473 * E = error valid 21474 */ 21475 21476 /* htt_t2h_rx_data_msdu_err: 21477 * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field 21478 * when FW forwards MSDU to host. 21479 */ 21480 typedef enum htt_t2h_rx_data_msdu_err { 21481 /* ERR_DECRYPT: 21482 * FW sets this when rxdma_error_code = <enum 3 rxdma_decrypt_err>. 21483 * host maintains error stats, recycles buffer. 21484 */ 21485 HTT_RXDATA_ERR_DECRYPT = 0, 21486 21487 /* ERR_TKIP_MIC: 21488 * FW sets this when rxdma_error_code = <enum 4 rxdma_tkip_mic_err>. 21489 * Host maintains error stats, recycles buffer, sends notification to 21490 * middleware. 21491 */ 21492 HTT_RXDATA_ERR_TKIP_MIC = 1, 21493 21494 /* ERR_UNENCRYPTED: 21495 * FW sets this when rxdma_error_code = <enum 5 rxdma_unecrypted_err>. 21496 * Host maintains error stats, recycles buffer. 21497 */ 21498 HTT_RXDATA_ERR_UNENCRYPTED = 2, 21499 21500 /* ERR_MSDU_LIMIT: 21501 * FW sets this when rxdma_error_code = <enum 7 rxdma_msdu_limit_err>. 21502 * Host maintains error stats, recycles buffer. 21503 */ 21504 HTT_RXDATA_ERR_MSDU_LIMIT = 3, 21505 21506 /* ERR_FLUSH_REQUEST: 21507 * FW sets this when rxdma_error_code = <enum 13 rxdma_flush_request>. 21508 * Host maintains error stats, recycles buffer. 21509 */ 21510 HTT_RXDATA_ERR_FLUSH_REQUEST = 4, 21511 21512 /* ERR_OOR: 21513 * FW full reorder layer maps this error to <enum 7 regular_frame_OOR>. 21514 * Host maintains error stats, recycles buffer mainly for low 21515 * TCP KPI debugging. 21516 */ 21517 HTT_RXDATA_ERR_OOR = 5, 21518 21519 /* ERR_2K_JUMP: 21520 * FW full reorder layer maps this error to <enum 5 regular_frame_2k_jump>. 21521 * Host maintains error stats, recycles buffer mainly for low 21522 * TCP KPI debugging. 21523 */ 21524 HTT_RXDATA_ERR_2K_JUMP = 6, 21525 21526 /* ERR_ZERO_LEN_MSDU: 21527 * FW sets this error flag for a 0 length MSDU. 21528 * Host maintains error stats, recycles buffer. 21529 */ 21530 HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, 21531 21532 /* ERR_INVALID_PEER: 21533 * FW sets this error flag when MSDU is recived from invalid PEER 21534 * HOST decides to send DEAUTH or not, recyles buffer. 21535 */ 21536 HTT_RXDATA_ERR_INVALID_PEER = 8, 21537 21538 /* add new error codes here */ 21539 21540 HTT_RXDATA_ERR_MAX = 32 21541 } htt_t2h_rx_data_msdu_err_e; 21542 21543 struct htt_t2h_rx_data_ind_t 21544 { 21545 A_UINT32 /* word 0 */ 21546 /* msg_type: 21547 * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. 21548 */ 21549 msg_type: 8, 21550 peer_id: 16, /* This will provide peer data */ 21551 vdev_id: 8; /* This will provide vdev id info */ 21552 A_UINT32 /* word 1 */ 21553 /* msdu_cnt: 21554 * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. 21555 */ 21556 msdu_cnt: 8, 21557 frag: 1, /* this bit will be set for 802.11 frag MPDU */ 21558 rsvd0: 23; 21559 /* NOTE: 21560 * To preserve backwards compatibility, 21561 * no new fields can be added in this struct. 21562 */ 21563 }; 21564 21565 struct htt_t2h_rx_data_msdu_info 21566 { 21567 A_UINT32 /* word 0 */ 21568 buffer_addr_low : 32; 21569 A_UINT32 /* word 1 */ 21570 buffer_addr_high : 8, 21571 sw_buffer_cookie : 21, 21572 /* fw_offloads_inspected: 21573 * When reo_destination_indication is 6 in reo_entrance_ring 21574 * of the RXDMA2REO MPDU upload, all the MSDUs that are part 21575 * of the MPDU are inspected by FW offloads layer, subsequently 21576 * the MSDUs are qualified to be host interested. 21577 * In such case the fw_offloads_inspected is set to 1, else 0. 21578 * This will assist host to not consider such MSDUs for FISA 21579 * flow addition. 21580 */ 21581 fw_offloads_inspected : 1, 21582 rsvd1 : 2; 21583 A_UINT32 /* word 2 */ 21584 mpdu_retry_bit : 1, /* used for stats maintenance */ 21585 raw_mpdu_frame : 1, /* used for pkt drop and processing */ 21586 first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 21587 last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ 21588 msdu_continuation : 1, /* used for MSDU scatter/gather support */ 21589 sa_is_valid : 1, /* used for HW issue check in 21590 * is_sa_da_idx_valid() */ 21591 da_is_valid : 1, /* used for HW issue check and 21592 * intra-BSS forwarding */ 21593 da_is_mcbc : 1, 21594 tid_info : 8, /* used for stats maintenance */ 21595 msdu_length : 14, 21596 is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU 21597 * provided by fw after WoW exit */ 21598 rsvd2 : 1; 21599 A_UINT32 /* word 3 */ 21600 error_valid : 1, /* Set if the MSDU has any error */ 21601 error_info : 5, /* If error_valid is TRUE, then refer to 21602 * "htt_t2h_rx_data_msdu_err_e" for 21603 * checking error reason. */ 21604 rsvd3 : 26; 21605 /* NOTE: 21606 * To preserve backwards compatibility, 21607 * no new fields can be added in this struct. 21608 */ 21609 }; 21610 21611 /* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words 21612 * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead 21613 * for every Rx DATA IND sent by FW to host. 21614 */ 21615 #define HTT_RX_DATA_IND_HDR_SIZE (2*4) 21616 /* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words 21617 * This is the size of each MSDU detail that will be piggybacked with the 21618 * RX IND header. 21619 */ 21620 #define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) 21621 21622 /* member definitions of htt_t2h_rx_data_ind_t */ 21623 21624 #define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 21625 #define HTT_RX_DATA_IND_PEER_ID_S 8 21626 21627 #define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ 21628 do { \ 21629 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ 21630 (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ 21631 } while (0) 21632 #define HTT_RX_DATA_IND_PEER_ID_GET(word) \ 21633 (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) 21634 21635 #define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 21636 #define HTT_RX_DATA_IND_VDEV_ID_S 24 21637 21638 #define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ 21639 do { \ 21640 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ 21641 (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ 21642 } while (0) 21643 #define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ 21644 (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) 21645 21646 #define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff 21647 #define HTT_RX_DATA_IND_MSDU_CNT_S 0 21648 21649 #define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ 21650 do { \ 21651 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ 21652 (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ 21653 } while (0) 21654 #define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ 21655 (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) 21656 21657 #define HTT_RX_DATA_IND_FRAG_M 0x00000100 21658 #define HTT_RX_DATA_IND_FRAG_S 8 21659 21660 #define HTT_RX_DATA_IND_FRAG_SET(word, value) \ 21661 do { \ 21662 HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ 21663 (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ 21664 } while (0) 21665 #define HTT_RX_DATA_IND_FRAG_GET(word) \ 21666 (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) 21667 21668 /* member definitions of htt_t2h_rx_data_msdu_info */ 21669 21670 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF 21671 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 21672 21673 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF 21674 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 21675 21676 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ 21677 do { \ 21678 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ 21679 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ 21680 } while (0) 21681 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ 21682 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) 21683 21684 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ 21685 do { \ 21686 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ 21687 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ 21688 } while (0) 21689 #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ 21690 (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) 21691 21692 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 21693 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 21694 21695 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ 21696 do { \ 21697 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ 21698 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ 21699 } while (0) 21700 #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ 21701 (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) 21702 21703 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000 21704 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29 21705 21706 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \ 21707 do { \ 21708 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \ 21709 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \ 21710 } while (0) 21711 #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \ 21712 (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S) 21713 21714 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 21715 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 21716 21717 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ 21718 do { \ 21719 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ 21720 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ 21721 } while (0) 21722 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ 21723 (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) 21724 21725 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 21726 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 21727 21728 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ 21729 do { \ 21730 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ 21731 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ 21732 } while (0) 21733 #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ 21734 (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) 21735 21736 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 21737 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 21738 21739 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ 21740 do { \ 21741 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ 21742 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ 21743 } while (0) 21744 #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ 21745 (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) 21746 21747 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 21748 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 21749 21750 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ 21751 do { \ 21752 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ 21753 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ 21754 } while (0) 21755 #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ 21756 (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) 21757 21758 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 21759 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 21760 21761 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ 21762 do { \ 21763 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ 21764 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ 21765 } while (0) 21766 #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ 21767 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) 21768 21769 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 21770 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 21771 21772 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ 21773 do { \ 21774 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ 21775 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ 21776 } while (0) 21777 #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ 21778 (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) 21779 21780 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 21781 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 21782 21783 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ 21784 do { \ 21785 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ 21786 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ 21787 } while (0) 21788 #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ 21789 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) 21790 21791 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 21792 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 21793 21794 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ 21795 do { \ 21796 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ 21797 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ 21798 } while (0) 21799 #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ 21800 (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) 21801 21802 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 21803 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 21804 21805 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ 21806 do { \ 21807 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ 21808 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ 21809 } while (0) 21810 #define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ 21811 (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) 21812 21813 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 21814 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 21815 21816 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ 21817 do { \ 21818 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ 21819 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ 21820 } while (0) 21821 #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ 21822 (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) 21823 21824 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 21825 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 21826 21827 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ 21828 do { \ 21829 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ 21830 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ 21831 } while (0) 21832 #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ 21833 (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) 21834 21835 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 21836 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 21837 21838 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ 21839 do { \ 21840 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ 21841 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ 21842 } while (0) 21843 #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ 21844 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) 21845 21846 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E 21847 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 21848 21849 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ 21850 do { \ 21851 HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ 21852 (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ 21853 } while (0) 21854 #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ 21855 (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) 21856 21857 21858 /** 21859 * @brief target -> Primary peer migration message to host 21860 * 21861 * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND 21862 * 21863 * @details 21864 * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target 21865 * to host to flush & set-up the RX rings to new primary peer 21866 * 21867 * The message would appear as follows: 21868 * 21869 * |31 16|15 12|11 8|7 0| 21870 * |-------------------------------+---------+---------+--------------| 21871 * | vdev ID | pdev ID | chip ID | msg type | 21872 * |-------------------------------+---------+---------+--------------| 21873 * | ML peer ID | SW peer ID | 21874 * |-------------------------------+----------------------------------| 21875 * 21876 * The message is interpreted as follows: 21877 * dword0 - b'0:7 - msg_type: This will be set to 0x37 21878 * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) 21879 * b'8:11 - chip_id: Indicate which chip has been chosen as primary 21880 * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen 21881 * as primary 21882 * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen 21883 * as primary 21884 * 21885 * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer 21886 * chosen as primary 21887 * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the 21888 * primary peer belongs. 21889 */ 21890 typedef struct { 21891 A_UINT32 msg_type: 8, /* bits 7:0 */ 21892 chip_id: 4, /* bits 11:8 */ 21893 pdev_id: 4, /* bits 15:12 */ 21894 vdev_id: 16; /* bits 31:16 */ 21895 A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ 21896 ml_peer_id: 16; /* bits 31:16 */ 21897 } htt_t2h_primary_link_peer_migrate_ind_t; 21898 21899 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 21900 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 21901 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ 21902 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ 21903 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) 21904 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ 21905 do { \ 21906 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ 21907 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ 21908 } while (0) 21909 21910 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 21911 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 21912 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ 21913 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ 21914 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) 21915 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ 21916 do { \ 21917 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ 21918 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ 21919 } while (0) 21920 21921 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 21922 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 21923 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ 21924 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ 21925 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) 21926 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ 21927 do { \ 21928 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ 21929 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ 21930 } while (0) 21931 21932 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF 21933 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 21934 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ 21935 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ 21936 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) 21937 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ 21938 do { \ 21939 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ 21940 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ 21941 } while (0) 21942 21943 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 21944 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 21945 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ 21946 (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ 21947 HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) 21948 #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ 21949 do { \ 21950 HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ 21951 ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ 21952 } while (0) 21953 21954 /** 21955 * @brief target -> host rx peer AST override message defenition 21956 * 21957 * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND 21958 * 21959 * @details 21960 * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above 21961 * where in the dummy ast index is provided to the host. 21962 * This new message below is sent to the host at run time from the TX_DE 21963 * exception path when a SAWF flow is detected for a peer. 21964 * This is sent up once per SAWF peer. 21965 * This layout assumes the target operates as little-endian. 21966 * 21967 * |31 24|23 16|15 8|7 0| 21968 * |--------------------------------------+-----------------+-----------------| 21969 * | SW peer ID | vdev ID | msg type | 21970 * |-----------------+--------------------+-----------------+-----------------| 21971 * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | 21972 * |-----------------+--------------------+-----------------+-----------------| 21973 * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | 21974 * |--------------------------------------+-----------------+-----------------| 21975 * | reserved | dummy AST Index #2 | 21976 * |--------------------------------------+-----------------------------------| 21977 * 21978 * The following field definitions describe the format of the peer ast override 21979 * index messages sent from the target to the host. 21980 * - MSG_TYPE 21981 * Bits 7:0 21982 * Purpose: identifies this as a peer map v3 message 21983 * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) 21984 * - VDEV_ID 21985 * Bits 15:8 21986 * Purpose: Indicates which virtual device the peer is associated with. 21987 * - SW_PEER_ID 21988 * Bits 31:16 21989 * Purpose: The peer ID (index) that WAL has allocated for this peer. 21990 * - MAC_ADDR_L32 21991 * Bits 31:0 21992 * Purpose: Identifies which peer node the peer ID is for. 21993 * Value: lower 4 bytes of peer node's MAC address 21994 * - MAC_ADDR_U16 21995 * Bits 15:0 21996 * Purpose: Identifies which peer node the peer ID is for. 21997 * Value: upper 2 bytes of peer node's MAC address 21998 * - AST_INDEX1 21999 * Bits 31:16 22000 * Purpose: The 1st extra AST index used to identify user defined MSDUQ 22001 * - AST_INDEX2 22002 * Bits 15:0 22003 * Purpose: The 2nd extra AST index used to identify user defined MSDUQ 22004 */ 22005 22006 /* dword 0 */ 22007 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 22008 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 22009 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 22010 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 22011 /* dword 1 */ 22012 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff 22013 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 22014 /* dword 2 */ 22015 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff 22016 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 22017 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 22018 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 22019 /* dword 3 */ 22020 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff 22021 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 22022 22023 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ 22024 do { \ 22025 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ 22026 (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ 22027 } while (0) 22028 #define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ 22029 (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) 22030 22031 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ 22032 do { \ 22033 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ 22034 (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ 22035 } while (0) 22036 #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ 22037 (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) 22038 22039 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ 22040 do { \ 22041 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ 22042 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ 22043 } while (0) 22044 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ 22045 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) 22046 22047 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ 22048 do { \ 22049 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ 22050 (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ 22051 } while (0) 22052 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ 22053 (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) 22054 22055 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ 22056 do { \ 22057 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ 22058 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ 22059 } while (0) 22060 #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ 22061 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) 22062 22063 22064 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ 22065 do { \ 22066 HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ 22067 (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ 22068 } while (0) 22069 #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ 22070 (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) 22071 22072 22073 #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ 22074 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ 22075 #define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ 22076 22077 #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 22078 22079 22080 /** 22081 * @brief target -> periodic report of tx latency to host 22082 * 22083 * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND 22084 * 22085 * @details 22086 * The message starts with a message header followed by one or more 22087 * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev. 22088 * After each upload, these tx latency stats will be reset. 22089 * 22090 * |31 24|23 16|15 14|13 10|9 8|7 0| 22091 * +-------------------------+-----+-----+---+----------| 22092 * hdr | |pyld elem sz| | GR | P | msg type | 22093 *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22094 * pyld | peer ID | 22095 * |----------------------------------------------------| 22096 * | peer_tx_latency[0] | 22097 * |----------------------------------------------------| 22098 * 1st | peer_tx_latency[1] | 22099 * peer |----------------------------------------------------| 22100 * | peer_tx_latency[2] | 22101 * |----------------------------------------------------| 22102 * | peer_tx_latency[3] | 22103 * |----------------------------------------------------| 22104 * | avg latency | 22105 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22106 * | peer ID | 22107 * |----------------------------------------------------| 22108 * | peer_tx_latency[0] | 22109 * |----------------------------------------------------| 22110 * 2nd | peer_tx_latency[1] | 22111 * peer |----------------------------------------------------| 22112 * | peer_tx_latency[2] | 22113 * |----------------------------------------------------| 22114 * | peer_tx_latency[3] | 22115 * |----------------------------------------------------| 22116 * | avg latency | 22117 * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| 22118 * Where: 22119 * P = pdev ID 22120 * GR = granularity 22121 * 22122 * @details 22123 * htt_t2h_tx_latency_stats_periodic_hdr_t: 22124 * - msg_type 22125 * Bits 7:0 22126 * Purpose: identifies this as a tx latency report message 22127 * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND) 22128 * - pdev_id 22129 * Bits 9:8 22130 * Purpose: Indicates which pdev this message is associated with. 22131 * - granularity 22132 * Bits 13:10 22133 * Purpose: specifies the granulairty of each tx latency bucket in MS. 22134 * There are 4 buckets in total. E.g. if granularity is set to 5 ms, 22135 * then the ranges for the 4 latency histogram buckets will be 22136 * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively. 22137 * - payload_elem_size 22138 * Bits 23:16 22139 * Purpose: specifies the size of each element within the msg's payload 22140 * In other words, this field specified the value of 22141 * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's 22142 * revision of the htt_t2h_peer_tx_latency_stats definition. 22143 * If the payload_elem_size reported in the message exceeds the 22144 * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22145 * revision of the htt_t2h_peer_tx_latency_stats definition, 22146 * the host shall ignore the excess data. 22147 * Conversely, if the payload_elem_size reported in the message is 22148 * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's 22149 * revision of the htt_t2h_peer_tx_latency_stats definition, 22150 * the host shall use 0x0 values for the portion of the data not 22151 * provided by the target. 22152 * The host can compare the payload_elem_size to the total size of 22153 * the message minus the size of the message header to determine 22154 * how many peer payload elements are present in the message. 22155 * - sw_peer_id 22156 * Purpose: The peer to which the following stats belong 22157 * - peer_tx_latency 22158 * Purpose: tx latency histogram for this peer, with 4 buckets whose 22159 * size (in milliseconds) is specified by the granularity field 22160 * - avg_latency 22161 * Purpose: average tx latency (in ms) for this peer in this report interval 22162 */ 22163 typedef struct { 22164 A_UINT32 msg_type: 8, 22165 pdev_id: 2, 22166 granularity: 4, 22167 reserved1: 2, 22168 payload_elem_size: 8, 22169 reserved2: 8; 22170 } htt_t2h_tx_latency_stats_periodic_hdr_t; 22171 22172 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \ 22173 (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t)) 22174 #define HTT_PEER_TX_LATENCY_REPORT_BINS 4 22175 22176 typedef struct _htt_tx_latency_stats { 22177 A_UINT32 peer_id; 22178 A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS]; 22179 A_UINT32 avg_latency; 22180 } htt_t2h_peer_tx_latency_stats; 22181 22182 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300 22183 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8 22184 22185 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ 22186 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S) 22187 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ 22188 do { \ 22189 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \ 22190 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \ 22191 } while (0) 22192 22193 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00 22194 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10 22195 22196 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \ 22197 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S) 22198 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \ 22199 do { \ 22200 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \ 22201 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ 22202 } while (0) 22203 22204 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000 22205 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16 22206 22207 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ 22208 (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) 22209 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \ 22210 do { \ 22211 HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \ 22212 ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \ 22213 } while (0) 22214 22215 22216 22217 #endif 22218