1  /* SPDX-License-Identifier: GPL-2.0-only */
2  /*
3   * Copyright(c) 2020 Intel Corporation
4   *
5   * Author: Cezary Rojewski <cezary.rojewski@intel.com>
6   */
7  
8  #ifndef __SND_SOC_INTEL_CATPT_REGS_H
9  #define __SND_SOC_INTEL_CATPT_REGS_H
10  
11  #include <linux/bitops.h>
12  #include <linux/iopoll.h>
13  #include <uapi/linux/pci_regs.h>
14  
15  #define CATPT_SHIM_REGS_SIZE	4096
16  #define CATPT_DMA_REGS_SIZE	1024
17  #define CATPT_DMA_COUNT		2
18  #define CATPT_SSP_REGS_SIZE	512
19  
20  /* DSP Shim registers */
21  
22  #define CATPT_SHIM_CS1		0x00
23  #define CATPT_SHIM_ISC		0x18
24  #define CATPT_SHIM_ISD		0x20
25  #define CATPT_SHIM_IMC		0x28
26  #define CATPT_SHIM_IMD		0x30
27  #define CATPT_SHIM_IPCC		0x38
28  #define CATPT_SHIM_IPCD		0x40
29  #define CATPT_SHIM_CLKCTL	0x78
30  #define CATPT_SHIM_CS2		0x80
31  #define CATPT_SHIM_LTRC		0xE0
32  #define CATPT_SHIM_HMDC		0xE8
33  
34  #define CATPT_CS_LPCS		BIT(31)
35  #define CATPT_CS_SFCR(ssp)	BIT(27 + (ssp))
36  #define CATPT_CS_S1IOCS		BIT(23)
37  #define CATPT_CS_S0IOCS		BIT(21)
38  #define CATPT_CS_PCE		BIT(15)
39  #define CATPT_CS_SDPM(ssp)	BIT(11 + (ssp))
40  #define CATPT_CS_STALL		BIT(10)
41  #define CATPT_CS_DCS		GENMASK(6, 4)
42  /* b100 DSP core & audio fabric high clock */
43  #define CATPT_CS_DCS_HIGH	(0x4 << 4)
44  #define CATPT_CS_SBCS(ssp)	BIT(2 + (ssp))
45  #define CATPT_CS_RST		BIT(1)
46  
47  #define CATPT_ISC_IPCDB		BIT(1)
48  #define CATPT_ISC_IPCCD		BIT(0)
49  #define CATPT_ISD_DCPWM		BIT(31)
50  #define CATPT_ISD_IPCCB		BIT(1)
51  #define CATPT_ISD_IPCDD		BIT(0)
52  
53  #define CATPT_IMC_IPCDB		BIT(1)
54  #define CATPT_IMC_IPCCD		BIT(0)
55  #define CATPT_IMD_IPCCB		BIT(1)
56  #define CATPT_IMD_IPCDD		BIT(0)
57  
58  #define CATPT_IPCC_BUSY		BIT(31)
59  #define CATPT_IPCC_DONE		BIT(30)
60  #define CATPT_IPCD_BUSY		BIT(31)
61  #define CATPT_IPCD_DONE		BIT(30)
62  
63  #define CATPT_CLKCTL_CFCIP	BIT(31)
64  #define CATPT_CLKCTL_SMOS	GENMASK(25, 24)
65  
66  #define CATPT_HMDC_HDDA(e, ch)	BIT(8 * (e) + (ch))
67  
68  /* defaults to reset SHIM registers to after each power cycle */
69  #define CATPT_CS_DEFAULT	0x8480040E
70  #define CATPT_ISC_DEFAULT	0x0
71  #define CATPT_ISD_DEFAULT	0x0
72  #define CATPT_IMC_DEFAULT	0x7FFF0003
73  #define CATPT_IMD_DEFAULT	0x7FFF0003
74  #define CATPT_IPCC_DEFAULT	0x0
75  #define CATPT_IPCD_DEFAULT	0x0
76  #define CATPT_CLKCTL_DEFAULT	0x7FF
77  #define CATPT_CS2_DEFAULT	0x0
78  #define CATPT_LTRC_DEFAULT	0x0
79  #define CATPT_HMDC_DEFAULT	0x0
80  
81  /* PCI Configuration registers */
82  
83  #define CATPT_PCI_PMCAPID	0x80
84  #define CATPT_PCI_PMCS		(CATPT_PCI_PMCAPID + PCI_PM_CTRL)
85  #define CATPT_PCI_VDRTCTL0	0xA0
86  #define CATPT_PCI_VDRTCTL2	0xA8
87  
88  #define CATPT_VDRTCTL2_DTCGE	BIT(10)
89  #define CATPT_VDRTCTL2_DCLCGE	BIT(1)
90  #define CATPT_VDRTCTL2_CGEALL	0xF7F
91  
92  /* LPT PCI Configuration bits */
93  
94  #define LPT_VDRTCTL0_DSRAMPGE(b)	BIT(16 + (b))
95  #define LPT_VDRTCTL0_DSRAMPGE_MASK	GENMASK(31, 16)
96  #define LPT_VDRTCTL0_ISRAMPGE(b)	BIT(6 + (b))
97  #define LPT_VDRTCTL0_ISRAMPGE_MASK	GENMASK(15, 6)
98  #define LPT_VDRTCTL0_D3SRAMPGD		BIT(2)
99  #define LPT_VDRTCTL0_D3PGD		BIT(1)
100  #define LPT_VDRTCTL0_APLLSE		BIT(0)
101  
102  /* WPT PCI Configuration bits */
103  
104  #define WPT_VDRTCTL0_DSRAMPGE(b)	BIT(12 + (b))
105  #define WPT_VDRTCTL0_DSRAMPGE_MASK	GENMASK(31, 12)
106  #define WPT_VDRTCTL0_ISRAMPGE(b)	BIT(2 + (b))
107  #define WPT_VDRTCTL0_ISRAMPGE_MASK	GENMASK(11, 2)
108  #define WPT_VDRTCTL0_D3SRAMPGD		BIT(1)
109  #define WPT_VDRTCTL0_D3PGD		BIT(0)
110  
111  #define WPT_VDRTCTL2_APLLSE		BIT(31)
112  
113  /* defaults to reset SSP registers to after each power cycle */
114  #define CATPT_SSC0_DEFAULT		0x0
115  #define CATPT_SSC1_DEFAULT		0x0
116  #define CATPT_SSS_DEFAULT		0xF004
117  #define CATPT_SSIT_DEFAULT		0x0
118  #define CATPT_SSD_DEFAULT		0xC43893A3
119  #define CATPT_SSTO_DEFAULT		0x0
120  #define CATPT_SSPSP_DEFAULT		0x0
121  #define CATPT_SSTSA_DEFAULT		0x0
122  #define CATPT_SSRSA_DEFAULT		0x0
123  #define CATPT_SSTSS_DEFAULT		0x0
124  #define CATPT_SSCR2_DEFAULT		0x0
125  #define CATPT_SSPSP2_DEFAULT		0x0
126  
127  /* Physically the same block, access address differs between host and dsp */
128  #define CATPT_DSP_DRAM_OFFSET		0x400000
129  #define catpt_to_host_offset(offset)	((offset) & ~(CATPT_DSP_DRAM_OFFSET))
130  #define catpt_to_dsp_offset(offset)	((offset) | CATPT_DSP_DRAM_OFFSET)
131  
132  #define CATPT_MEMBLOCK_SIZE	0x8000
133  #define catpt_num_dram(cdev)	(hweight_long((cdev)->spec->dram_mask))
134  #define catpt_num_iram(cdev)	(hweight_long((cdev)->spec->iram_mask))
135  #define catpt_dram_size(cdev)	(catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE)
136  #define catpt_iram_size(cdev)	(catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE)
137  
138  /* registry I/O helpers */
139  
140  #define catpt_shim_addr(cdev) \
141  	((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
142  #define catpt_dma_addr(cdev, dma) \
143  	((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma])
144  #define catpt_ssp_addr(cdev, ssp) \
145  	((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp])
146  #define catpt_inbox_addr(cdev) \
147  	((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset)
148  #define catpt_outbox_addr(cdev) \
149  	((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset)
150  
151  #define catpt_writel_ssp(cdev, ssp, reg, val) \
152  	writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
153  
154  #define catpt_readl_shim(cdev, reg) \
155  	readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
156  #define catpt_writel_shim(cdev, reg, val) \
157  	writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
158  #define catpt_updatel_shim(cdev, reg, mask, val) \
159  	catpt_writel_shim(cdev, reg, \
160  			  (catpt_readl_shim(cdev, reg) & ~(mask)) | (val))
161  
162  #define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \
163  	readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \
164  			   val, cond, delay_us, timeout_us)
165  
166  #define catpt_readl_pci(cdev, reg) \
167  	readl(cdev->pci_ba + CATPT_PCI_##reg)
168  #define catpt_writel_pci(cdev, reg, val) \
169  	writel(val, cdev->pci_ba + CATPT_PCI_##reg)
170  #define catpt_updatel_pci(cdev, reg, mask, val) \
171  	catpt_writel_pci(cdev, reg, \
172  			 (catpt_readl_pci(cdev, reg) & ~(mask)) | (val))
173  
174  #define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \
175  	readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \
176  			   val, cond, delay_us, timeout_us)
177  
178  #endif
179