1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3  * Copyright (C) 2023 DH electronics GmbH
4  */
5 
6 #include "imx6ull-dhcor-som.dtsi"
7 
8 / {
9 	aliases {
10 		/delete-property/ spi2;
11 		/delete-property/ spi3;
12 		i2c0 = &i2c2;
13 		i2c1 = &i2c1;
14 		mmc2 = &usdhc2;
15 		rtc0 = &rtc_i2c;
16 		rtc1 = &snvs_rtc;
17 		serial0 = &uart1;
18 		serial1 = &uart6; /* DHCOM UART2, special hardware required */
19 		serial2 = &uart3;
20 		serial3 = &uart2; /* Use BT UART always as ttymxc3 */
21 		serial4 = &uart4;
22 		serial5 = &uart5;
23 		spi0 = &ecspi1;
24 		spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
25 	};
26 
27 	chosen {
28 		stdout-path = "serial0:115200n8";
29 	};
30 
31 	reg_ext_3v3_ref: regulator-ext-3v3-ref {
32 		compatible = "regulator-fixed";
33 		regulator-always-on;
34 		regulator-max-microvolt = <3300000>;
35 		regulator-min-microvolt = <3300000>;
36 		regulator-name = "VCC_3V3_REF";
37 	};
38 
39 	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
40 		compatible = "regulator-fixed";
41 		regulator-max-microvolt = <5000000>;
42 		regulator-min-microvolt = <5000000>;
43 		regulator-name = "usb-otg1-vbus";
44 	};
45 
46 	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
47 		compatible = "regulator-fixed";
48 		gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
49 		regulator-max-microvolt = <5000000>;
50 		regulator-min-microvolt = <5000000>;
51 		regulator-name = "usb-otg2-vbus";
52 	};
53 
54 	/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
55 	usdhc1_pwrseq: usdhc1-pwrseq {
56 		compatible = "mmc-pwrseq-simple";
57 		reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
58 	};
59 };
60 
61 /* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
62 &bluetooth {
63 	shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
64 };
65 
66 &can1 {
67 	pinctrl-0 = <&pinctrl_flexcan1>;
68 	pinctrl-names = "default";
69 	status = "okay";
70 };
71 
72 /*
73  * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
74  * Only if this pins are used as CAN interface enable it on board layer.
75  */
76 &can2 {
77 	pinctrl-0 = <&pinctrl_flexcan2>;
78 	pinctrl-names = "default";
79 };
80 
81 /* DHCOM SPI1 */
82 &ecspi1 {
83 	cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
84 	pinctrl-0 = <&pinctrl_ecspi1>;
85 	pinctrl-names = "default";
86 	status = "okay";
87 };
88 
89 /*
90  * DHCOM SPI2
91  * Special hardware required that uses the pins of FEC2. Therefore this SPI
92  * interface can only be used if FEC2 is disabled.
93  */
94 &ecspi4 {
95 	cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
96 	pinctrl-0 = <&pinctrl_ecspi4>;
97 	pinctrl-names = "default";
98 };
99 
100 /* DHCOM ETH1 */
101 &fec1 {
102 	phy-handle = <&mdio2_phy0>;
103 	phy-mode = "rmii";
104 	pinctrl-0 = <&pinctrl_fec1>;
105 	pinctrl-names = "default";
106 	status = "okay";
107 };
108 
109 /* DHCOM ETH2 */
110 &fec2 {
111 	phy-handle = <&mdio2_phy1>;
112 	phy-mode = "rmii";
113 	pinctrl-0 = <&pinctrl_fec2>;
114 	pinctrl-names = "default";
115 	status = "okay";
116 
117 	mdio {
118 		#address-cells = <1>;
119 		#size-cells = <0>;
120 
121 		mdio2_phy0: ethernet-phy@0 {
122 			compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
123 				     "ethernet-phy-ieee802.3-c22";
124 			reg = <0>;
125 			clock-names = "rmii-ref";
126 			clocks = <&clks IMX6UL_CLK_ENET_REF>;
127 			interrupt-parent = <&gpio5>;
128 			interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
129 			pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
130 			pinctrl-names = "default";
131 			reset-assert-us = <500>;
132 			reset-deassert-us = <500>;
133 			reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
134 			smsc,disable-energy-detect; /* Make plugin detection reliable */
135 		};
136 
137 		mdio2_phy1: ethernet-phy@1 {
138 			compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
139 				     "ethernet-phy-ieee802.3-c22";
140 			reg = <1>;
141 			clock-names = "rmii-ref";
142 			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
143 			interrupt-parent = <&gpio5>;
144 			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
145 			pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
146 			pinctrl-names = "default";
147 			reset-assert-us = <500>;
148 			reset-deassert-us = <500>;
149 			reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
150 			smsc,disable-energy-detect; /* Make plugin detection reliable */
151 		};
152 	};
153 };
154 
155 &gpio1 {
156 	gpio-line-names =
157 		"", "", "", "",
158 		"", "", "", "",
159 		"", "", "", "DHCOM-INT",
160 		"", "", "", "",
161 		"", "", "DHCOM-I", "",
162 		"", "", "", "",
163 		"", "", "", "",
164 		"", "", "", "";
165 	pinctrl-0 = <&pinctrl_spi1_switch
166 		     &pinctrl_dhcom_i &pinctrl_dhcom_int>;
167 	pinctrl-names = "default";
168 };
169 
170 &gpio4 {
171 	gpio-line-names =
172 		"", "", "", "",
173 		"", "", "", "",
174 		"", "", "", "",
175 		"", "", "", "",
176 		"", "DHCOM-L", "DHCOM-K", "DHCOM-M",
177 		"DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
178 		"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
179 		"DHCOM-N", "", "", "";
180 	pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
181 		     &pinctrl_dhcom_l &pinctrl_dhcom_m
182 		     &pinctrl_dhcom_n &pinctrl_dhcom_o
183 		     &pinctrl_dhcom_p &pinctrl_dhcom_q
184 		     &pinctrl_dhcom_r &pinctrl_dhcom_s
185 		     &pinctrl_dhcom_t &pinctrl_dhcom_u>;
186 	pinctrl-names = "default";
187 };
188 
189 &gpio5 {
190 	gpio-line-names =
191 		"DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
192 		"DHCOM-E", "", "", "DHCOM-F",
193 		"DHCOM-G", "DHCOM-H", "", "",
194 		"", "", "", "",
195 		"", "", "", "",
196 		"", "", "", "",
197 		"", "", "", "",
198 		"", "", "", "";
199 	pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
200 		     &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
201 		     &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
202 		     &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
203 	pinctrl-names = "default";
204 };
205 
206 /* DHCOM I2C2 */
207 &i2c1 {
208 	rtc_i2c: rtc@32 {
209 		compatible = "microcrystal,rv8803";
210 		reg = <0x32>;
211 	};
212 
213 	/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
214 	eeprom@50 {
215 		compatible = "atmel,24c02";
216 		reg = <0x50>;
217 		pagesize = <16>;
218 	};
219 
220 	/* TI ADC101C027 */
221 	adc@51 {
222 		compatible = "ti,adc101c";
223 		reg = <0x51>;
224 		vref-supply = <&reg_ext_3v3_ref>;
225 	};
226 
227 	/* TI ADC101C027 */
228 	adc@52 {
229 		compatible = "ti,adc101c";
230 		reg = <0x52>;
231 		vref-supply = <&reg_ext_3v3_ref>;
232 	};
233 
234 	/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
235 	eeprom@53 {
236 		compatible = "atmel,24c02";
237 		reg = <0x53>;
238 		pagesize = <16>;
239 	};
240 };
241 
242 /* DHCOM I2C1 */
243 &i2c2 {
244 	clock-frequency = <100000>;
245 	pinctrl-0 = <&pinctrl_i2c2>;
246 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
247 	pinctrl-names = "default", "gpio";
248 	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
249 	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
250 	status = "okay";
251 };
252 
253 &lcdif {
254 	pinctrl-0 = <&pinctrl_lcdif>;
255 	pinctrl-names = "default";
256 };
257 
258 &pwm1 {
259 	pinctrl-0 = <&pinctrl_pwm1>;
260 	pinctrl-names = "default";
261 };
262 
263 &sai2 {
264 	assigned-clock-rates = <320000000>;
265 	assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
266 	pinctrl-0 = <&pinctrl_sai2>;
267 	pinctrl-names = "default";
268 };
269 
270 &tsc {
271 	measure-delay-time = <0xffff>;
272 	pinctrl-0 = <&pinctrl_tsc>;
273 	pinctrl-names = "default";
274 	pre-charge-time = <0xfff>;
275 	touchscreen-average-samples = <32>;
276 	xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
277 };
278 
279 /* DHCOM UART1 */
280 &uart1 {
281 	pinctrl-0 = <&pinctrl_uart1>;
282 	pinctrl-names = "default";
283 	status = "okay";
284 };
285 
286 /*
287  * DHCOM UART2 (alternative)
288  * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
289  * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
290  * removed from GPIO hog muxing.
291  */
292 &uart6 {
293 	pinctrl-0 = <&pinctrl_uart6>;
294 	pinctrl-names = "default";
295 	uart-has-rtscts;
296 };
297 
298 &usbotg1 {
299 	adp-disable;
300 	disable-over-current;
301 	dr_mode = "otg";
302 	hnp-disable;
303 	pinctrl-0 = <&pinctrl_usbotg1>;
304 	pinctrl-names = "default";
305 	srp-disable;
306 	vbus-supply = <&reg_usb_otg1_vbus>;
307 	status = "okay";
308 };
309 
310 &usbotg2 {
311 	disable-over-current; /* Overcurrent pin is used for TSC */
312 	dr_mode = "host";
313 	pinctrl-0 = <&pinctrl_usbotg2>;
314 	pinctrl-names = "default";
315 	tpl-support;
316 	vbus-supply = <&reg_usb_otg2_vbus>;
317 	status = "okay";
318 };
319 
320 &usbphy1 {
321 	fsl,tx-d-cal = <106>;
322 };
323 
324 &usbphy2 {
325 	fsl,tx-d-cal = <106>;
326 };
327 
328 /* WiFi on LGA */
329 &usdhc1 {
330 	mmc-pwrseq = <&usdhc1_pwrseq>;
331 };
332 
333 /* eMMC on module */
334 &usdhc2 {
335 	bus-width = <8>;
336 	no-1-8-v;
337 	non-removable;
338 	pinctrl-0 = <&pinctrl_usdhc2>;
339 	pinctrl-names = "default";
340 	vmmc-supply = <&vcc_3v3>;
341 	vqmmc-supply = <&vcc_3v3>;
342 	status = "okay";
343 };
344 
345 &iomuxc {
346 	/* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
347 	pinctrl_dhcom_i: dhcom-i-grp {
348 		fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x400120b0>;
349 	};
350 
351 	pinctrl_dhcom_j: dhcom-j-grp {
352 		fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20	0x400120b0>;
353 	};
354 
355 	pinctrl_dhcom_k: dhcom-k-grp {
356 		fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x400120b0>;
357 	};
358 
359 	pinctrl_dhcom_l: dhcom-l-grp {
360 		fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17	0x400120b0>;
361 	};
362 
363 	pinctrl_dhcom_m: dhcom-m-grp {
364 		fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19	0x400120b0>;
365 	};
366 
367 	pinctrl_dhcom_n: dhcom-n-grp {
368 		fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x400120b0>;
369 	};
370 
371 	pinctrl_dhcom_o: dhcom-o-grp {
372 		fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x400120b0>;
373 	};
374 
375 	pinctrl_dhcom_p: dhcom-p-grp {
376 		fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x400120b0>;
377 	};
378 
379 	pinctrl_dhcom_q: dhcom-q-grp {
380 		fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x400120b0>;
381 	};
382 
383 	pinctrl_dhcom_r: dhcom-r-grp {
384 		fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24	0x400120b0>;
385 	};
386 
387 	pinctrl_dhcom_s: dhcom-s-grp {
388 		fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x400120b0>;
389 	};
390 
391 	pinctrl_dhcom_t: dhcom-t-grp {
392 		fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x400120b0>;
393 	};
394 
395 	pinctrl_dhcom_u: dhcom-u-grp {
396 		fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x400120b0>;
397 	};
398 
399 	pinctrl_dhcom_int: dhcom-int-grp {
400 		fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11	0x400120b0>;
401 	};
402 
403 	pinctrl_ecspi1: ecspi1-grp {
404 		fsl,pins = <
405 			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100b1
406 			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x100b1
407 			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x100b1
408 			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x1b0b0 /* SS0 */
409 		>;
410 	};
411 
412 	pinctrl_ecspi4: ecspi4-grp {
413 		fsl,pins = <
414 			MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO	0x100b1
415 			MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI	0x100b1
416 			MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK	0x100b1
417 			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0 /* SS0 */
418 		>;
419 	};
420 
421 	pinctrl_fec1: fec1-grp {
422 		fsl,pins = <
423 			/* FEC1 uses MDIO bus from FEC2 */
424 			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
425 			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
426 			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
427 			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
428 			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b010
429 			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b010
430 			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b010
431 			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b010
432 		>;
433 	};
434 
435 	pinctrl_fec1_phy: fec1-phy-grp {
436 		fsl,pins = <
437 			MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0xb0 /* SMSC PHY reset */
438 		>;
439 	};
440 
441 	pinctrl_fec2: fec2-grp {
442 		fsl,pins = <
443 			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
444 			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
445 			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
446 			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
447 			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
448 			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
449 			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
450 			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
451 			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
452 			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
453 		>;
454 	};
455 
456 	pinctrl_fec2_phy: fec2-phy-grp {
457 		fsl,pins = <
458 			MX6UL_PAD_LCD_DATA19__GPIO3_IO24	0xb0 /* SMSC PHY reset */
459 		>;
460 	};
461 
462 	pinctrl_flexcan1: flexcan1-grp {
463 		fsl,pins = <
464 			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
465 			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
466 		>;
467 	};
468 
469 	pinctrl_flexcan2: flexcan2-grp {
470 		fsl,pins = <
471 			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
472 			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
473 		>;
474 	};
475 
476 	pinctrl_i2c2: i2c2-grp {
477 		fsl,pins = <
478 			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
479 			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
480 		>;
481 	};
482 
483 	pinctrl_i2c2_gpio: i2c2-gpio-grp {
484 		fsl,pins = <
485 			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x4001b8b0
486 			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31	0x4001b8b0
487 		>;
488 	};
489 
490 	pinctrl_lcdif: lcdif-grp {
491 		fsl,pins = <
492 			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
493 			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
494 			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
495 			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
496 			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
497 			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
498 			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
499 			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
500 			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
501 			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
502 			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
503 			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
504 			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
505 			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
506 			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
507 			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
508 			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
509 			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
510 			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
511 			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
512 			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
513 			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
514 		>;
515 	};
516 
517 	pinctrl_pwm1: pwm1-grp {
518 		fsl,pins = <
519 			MX6UL_PAD_GPIO1_IO08__PWM1_OUT		0x110b0
520 		>;
521 	};
522 
523 	pinctrl_sai2: sai2-grp {
524 		fsl,pins = <
525 			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
526 			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
527 			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
528 			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
529 		>;
530 	};
531 
532 	pinctrl_tsc: tsc-grp {
533 		fsl,pins = <
534 			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
535 			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
536 			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
537 			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
538 		>;
539 	};
540 
541 	pinctrl_uart1: uart1-grp {
542 		fsl,pins = <
543 			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
544 			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
545 		>;
546 	};
547 
548 	pinctrl_uart6: uart6-grp {
549 		fsl,pins = <
550 			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
551 			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
552 			MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS	0x1b0b1
553 			MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS	0x1b0b1
554 		>;
555 	};
556 
557 	pinctrl_usbotg1: usbotg1-grp {
558 		fsl,pins = <
559 			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
560 		>;
561 	};
562 
563 	pinctrl_usbotg2: usbotg2-grp {
564 		fsl,pins = <
565 			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x120b0
566 		>;
567 	};
568 
569 	pinctrl_usdhc2: usdhc2-grp {
570 		fsl,pins = <
571 			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
572 			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
573 			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
574 			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
575 			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
576 			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
577 			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
578 			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
579 			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
580 			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
581 			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x17059 /* SD2 Reset */
582 		>;
583 	};
584 };
585 
586 &iomuxc_snvs {
587 	/* DHCOM GPIOs A..H */
588 	pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
589 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x400120b0>;
590 	};
591 
592 	pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
593 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x400120b0>;
594 	};
595 
596 	pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
597 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x400120b0>;
598 	};
599 
600 	pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
601 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x400120b0>;
602 	};
603 
604 	pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
605 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x400120b0>;
606 	};
607 
608 	pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
609 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x400120b0>;
610 	};
611 
612 	pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
613 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x400120b0>;
614 	};
615 
616 	pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
617 		fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x400120b0>;
618 	};
619 
620 	pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
621 		fsl,pins = <
622 			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0xb1 /* SMSC PHY Int */
623 		>;
624 	};
625 
626 	pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
627 		fsl,pins = <
628 			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0xb1 /* SMSC PHY Int */
629 		>;
630 	};
631 };
632