1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 SiFive 4 * Copyright (C) 2018 Andes Technology Corporation 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 * 7 */ 8 9 #ifndef _RISCV_PMU_H 10 #define _RISCV_PMU_H 11 12 #include <linux/perf_event.h> 13 #include <linux/ptrace.h> 14 #include <linux/interrupt.h> 15 16 #ifdef CONFIG_RISCV_PMU 17 18 /* 19 * The RISCV_MAX_COUNTERS parameter should be specified. 20 */ 21 22 #define RISCV_MAX_COUNTERS 64 23 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) 24 #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" 25 #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" 26 27 #define RISCV_PMU_STOP_FLAG_RESET 1 28 29 #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 30 31 struct cpu_hw_events { 32 /* currently enabled events */ 33 int n_events; 34 /* Counter overflow interrupt */ 35 int irq; 36 /* currently enabled events */ 37 struct perf_event *events[RISCV_MAX_COUNTERS]; 38 /* currently enabled hardware counters */ 39 DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); 40 /* currently enabled firmware counters */ 41 DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); 42 /* The virtual address of the shared memory where counter snapshot will be taken */ 43 void *snapshot_addr; 44 /* The physical address of the shared memory where counter snapshot will be taken */ 45 phys_addr_t snapshot_addr_phys; 46 /* Boolean flag to indicate setup is already done */ 47 bool snapshot_set_done; 48 /* A shadow copy of the counter values to avoid clobbering during multiple SBI calls */ 49 u64 snapshot_cval_shcopy[RISCV_MAX_COUNTERS]; 50 }; 51 52 struct riscv_pmu { 53 struct pmu pmu; 54 char *name; 55 56 irqreturn_t (*handle_irq)(int irq_num, void *dev); 57 58 unsigned long cmask; 59 u64 (*ctr_read)(struct perf_event *event); 60 int (*ctr_get_idx)(struct perf_event *event); 61 int (*ctr_get_width)(int idx); 62 void (*ctr_clear_idx)(struct perf_event *event); 63 void (*ctr_start)(struct perf_event *event, u64 init_val); 64 void (*ctr_stop)(struct perf_event *event, unsigned long flag); 65 int (*event_map)(struct perf_event *event, u64 *config); 66 void (*event_init)(struct perf_event *event); 67 void (*event_mapped)(struct perf_event *event, struct mm_struct *mm); 68 void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm); 69 uint8_t (*csr_index)(struct perf_event *event); 70 71 struct cpu_hw_events __percpu *hw_events; 72 struct hlist_node node; 73 struct notifier_block riscv_pm_nb; 74 }; 75 76 #define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu)) 77 78 void riscv_pmu_start(struct perf_event *event, int flags); 79 void riscv_pmu_stop(struct perf_event *event, int flags); 80 unsigned long riscv_pmu_ctr_read_csr(unsigned long csr); 81 int riscv_pmu_event_set_period(struct perf_event *event); 82 uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event); 83 u64 riscv_pmu_event_update(struct perf_event *event); 84 #ifdef CONFIG_RISCV_PMU_LEGACY 85 void riscv_pmu_legacy_skip_init(void); 86 #else riscv_pmu_legacy_skip_init(void)87 static inline void riscv_pmu_legacy_skip_init(void) {}; 88 #endif 89 struct riscv_pmu *riscv_pmu_alloc(void); 90 #ifdef CONFIG_RISCV_PMU_SBI 91 int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); 92 #endif 93 94 #endif /* CONFIG_RISCV_PMU */ 95 96 #endif /* _RISCV_PMU_H */ 97