1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
7
8 #ifndef __DWC2_CORE_H__
9 #define __DWC2_CORE_H__
10
11 #include <linux/acpi.h>
12 #include <linux/phy/phy.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/usb/gadget.h>
15 #include <linux/usb/otg.h>
16 #include <linux/usb/phy.h>
17 #include "hw.h"
18
19 /*
20 * Suggested defines for tracers:
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
24 */
25
26 #define DWC2_TRACE_SCHEDULER no_printk
27 #define DWC2_TRACE_SCHEDULER_VB no_printk
28
29 /* Detailed scheduler tracing, but won't overwhelm console */
30 #define dwc2_sch_dbg(hsotg, fmt, ...) \
31 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
32 dev_name(hsotg->dev), ##__VA_ARGS__)
33
34 /* Verbose scheduler tracing */
35 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
36 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
37 dev_name(hsotg->dev), ##__VA_ARGS__)
38
39 /* Maximum number of Endpoints/HostChannels */
40 #define MAX_EPS_CHANNELS 16
41
42 /* dwc2-hsotg declarations */
43 static const char * const dwc2_hsotg_supply_names[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
46 };
47
48 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
49
50 /*
51 * EP0_MPS_LIMIT
52 *
53 * Unfortunately there seems to be a limit of the amount of data that can
54 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
55 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * MPS is set to 64.
57 *
58 * This means if we are wanting to move >127 bytes of data, we need to
59 * split the transactions up, but just doing one packet at a time does
60 * not work (this may be an implicit DATA0 PID on first packet of the
61 * transaction) and doing 2 packets is outside the controller's limits.
62 *
63 * If we try to lower the MPS size for EP0, then no transfers work properly
64 * for EP0, and the system will fail basic enumeration. As no cause for this
65 * has currently been found, we cannot support any large IN transfers for
66 * EP0.
67 */
68 #define EP0_MPS_LIMIT 64
69
70 struct dwc2_hsotg;
71 struct dwc2_hsotg_req;
72
73 /**
74 * struct dwc2_hsotg_ep - driver endpoint definition.
75 * @ep: The gadget layer representation of the endpoint.
76 * @name: The driver generated name for the endpoint.
77 * @queue: Queue of requests for this endpoint.
78 * @parent: Reference back to the parent device structure.
79 * @req: The current request that the endpoint is processing. This is
80 * used to indicate an request has been loaded onto the endpoint
81 * and has yet to be completed (maybe due to data move, or simply
82 * awaiting an ack from the core all the data has been completed).
83 * @debugfs: File entry for debugfs file for this endpoint.
84 * @dir_in: Set to true if this endpoint is of the IN direction, which
85 * means that it is sending data to the Host.
86 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
87 * @index: The index for the endpoint registers.
88 * @mc: Multi Count - number of transactions per microframe
89 * @interval: Interval for periodic endpoints, in frames or microframes.
90 * @name: The name array passed to the USB core.
91 * @halted: Set if the endpoint has been halted.
92 * @periodic: Set if this is a periodic ep, such as Interrupt
93 * @isochronous: Set if this is a isochronous ep
94 * @send_zlp: Set if we need to send a zero-length packet.
95 * @wedged: Set if ep is wedged.
96 * @desc_list_dma: The DMA address of descriptor chain currently in use.
97 * @desc_list: Pointer to descriptor DMA chain head currently in use.
98 * @desc_count: Count of entries within the DMA descriptor chain of EP.
99 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
100 * @compl_desc: index of next descriptor to be completed by xFerComplete
101 * @total_data: The total number of data bytes done.
102 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
103 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
104 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
105 * @last_load: The offset of data for the last start of request.
106 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
107 * @target_frame: Targeted frame num to setup next ISOC transfer
108 * @frame_overrun: Indicates SOF number overrun in DSTS
109 *
110 * This is the driver's state for each registered endpoint, allowing it
111 * to keep track of transactions that need doing. Each endpoint has a
112 * lock to protect the state, to try and avoid using an overall lock
113 * for the host controller as much as possible.
114 *
115 * For periodic IN endpoints, we have fifo_size and fifo_load to try
116 * and keep track of the amount of data in the periodic FIFO for each
117 * of these as we don't have a status register that tells us how much
118 * is in each of them. (note, this may actually be useless information
119 * as in shared-fifo mode periodic in acts like a single-frame packet
120 * buffer than a fifo)
121 */
122 struct dwc2_hsotg_ep {
123 struct usb_ep ep;
124 struct list_head queue;
125 struct dwc2_hsotg *parent;
126 struct dwc2_hsotg_req *req;
127 struct dentry *debugfs;
128
129 unsigned long total_data;
130 unsigned int size_loaded;
131 unsigned int last_load;
132 unsigned int fifo_load;
133 unsigned short fifo_size;
134 unsigned short fifo_index;
135
136 unsigned char dir_in;
137 unsigned char map_dir;
138 unsigned char index;
139 unsigned char mc;
140 u16 interval;
141
142 unsigned int halted:1;
143 unsigned int periodic:1;
144 unsigned int isochronous:1;
145 unsigned int send_zlp:1;
146 unsigned int wedged:1;
147 unsigned int target_frame;
148 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
149 bool frame_overrun;
150
151 dma_addr_t desc_list_dma;
152 struct dwc2_dma_desc *desc_list;
153 u8 desc_count;
154
155 unsigned int next_desc;
156 unsigned int compl_desc;
157
158 char name[10];
159 };
160
161 /**
162 * struct dwc2_hsotg_req - data transfer request
163 * @req: The USB gadget request
164 * @queue: The list of requests for the endpoint this is queued for.
165 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
166 */
167 struct dwc2_hsotg_req {
168 struct usb_request req;
169 struct list_head queue;
170 void *saved_req_buf;
171 };
172
173 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
174 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
175 #define call_gadget(_hs, _entry) \
176 do { \
177 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
178 (_hs)->driver && (_hs)->driver->_entry) { \
179 spin_unlock(&_hs->lock); \
180 (_hs)->driver->_entry(&(_hs)->gadget); \
181 spin_lock(&_hs->lock); \
182 } \
183 } while (0)
184 #else
185 #define call_gadget(_hs, _entry) do {} while (0)
186 #endif
187
188 struct dwc2_hsotg;
189 struct dwc2_host_chan;
190
191 /* Device States */
192 enum dwc2_lx_state {
193 DWC2_L0, /* On state */
194 DWC2_L1, /* LPM sleep state */
195 DWC2_L2, /* USB suspend state */
196 DWC2_L3, /* Off state */
197 };
198
199 /* Gadget ep0 states */
200 enum dwc2_ep0_state {
201 DWC2_EP0_SETUP,
202 DWC2_EP0_DATA_IN,
203 DWC2_EP0_DATA_OUT,
204 DWC2_EP0_STATUS_IN,
205 DWC2_EP0_STATUS_OUT,
206 };
207
208 /**
209 * struct dwc2_core_params - Parameters for configuring the core
210 *
211 * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters,
212 * used to setup the:
213 * - HNP and SRP capable
214 * - SRP Only capable
215 * - No HNP/SRP capable (always available)
216 * Defaults to best available option
217 * - OTG revision number the device is compliant with, in binary-coded
218 * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps)
219 * @host_dma: Specifies whether to use slave or DMA mode for accessing
220 * the data FIFOs. The driver will automatically detect the
221 * value for this parameter if none is specified.
222 * 0 - Slave (always available)
223 * 1 - DMA (default, if available)
224 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
225 * address DMA mode or descriptor DMA mode for accessing
226 * the data FIFOs. The driver will automatically detect the
227 * value for this if none is specified.
228 * 0 - Address DMA
229 * 1 - Descriptor DMA (default, if available)
230 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
231 * address DMA mode or descriptor DMA mode for accessing
232 * the data FIFOs in Full Speed mode only. The driver
233 * will automatically detect the value for this if none is
234 * specified.
235 * 0 - Address DMA
236 * 1 - Descriptor DMA in FS (default, if available)
237 * @speed: Specifies the maximum speed of operation in host and
238 * device mode. The actual speed depends on the speed of
239 * the attached device and the value of phy_type.
240 * 0 - High Speed
241 * (default when phy_type is UTMI+ or ULPI)
242 * 1 - Full Speed
243 * (default when phy_type is Full Speed)
244 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
245 * 1 - Allow dynamic FIFO sizing (default, if available)
246 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
247 * are enabled for non-periodic IN endpoints in device
248 * mode.
249 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
250 * dynamic FIFO sizing is enabled
251 * 16 to 32768
252 * Actual maximum value is autodetected and also
253 * the default.
254 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
255 * in host mode when dynamic FIFO sizing is enabled
256 * 16 to 32768
257 * Actual maximum value is autodetected and also
258 * the default.
259 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
260 * host mode when dynamic FIFO sizing is enabled
261 * 16 to 32768
262 * Actual maximum value is autodetected and also
263 * the default.
264 * @max_transfer_size: The maximum transfer size supported, in bytes
265 * 2047 to 65,535
266 * Actual maximum value is autodetected and also
267 * the default.
268 * @max_packet_count: The maximum number of packets in a transfer
269 * 15 to 511
270 * Actual maximum value is autodetected and also
271 * the default.
272 * @host_channels: The number of host channel registers to use
273 * 1 to 16
274 * Actual maximum value is autodetected and also
275 * the default.
276 * @phy_type: Specifies the type of PHY interface to use. By default,
277 * the driver will automatically detect the phy_type.
278 * 0 - Full Speed Phy
279 * 1 - UTMI+ Phy
280 * 2 - ULPI Phy
281 * Defaults to best available option (2, 1, then 0)
282 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
283 * is applicable for a phy_type of UTMI+ or ULPI. (For a
284 * ULPI phy_type, this parameter indicates the data width
285 * between the MAC and the ULPI Wrapper.) Also, this
286 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
287 * parameter was set to "8 and 16 bits", meaning that the
288 * core has been configured to work at either data path
289 * width.
290 * 8 or 16 (default 16 if available)
291 * @eusb2_disc: Specifies whether eUSB2 PHY disconnect support flow
292 * applicable or no. Applicable in device mode of HSOTG
293 * and HS IOT cores v5.00 or higher.
294 * 0 - eUSB2 PHY disconnect support flow not applicable
295 * 1 - eUSB2 PHY disconnect support flow applicable
296 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
297 * data rate. This parameter is only applicable if phy_type
298 * is ULPI.
299 * 0 - single data rate ULPI interface with 8 bit wide
300 * data bus (default)
301 * 1 - double data rate ULPI interface with 4 bit wide
302 * data bus
303 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
304 * external supply to drive the VBus
305 * 0 - Internal supply (default)
306 * 1 - External supply
307 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
308 * speed PHY. This parameter is only applicable if phy_type
309 * is FS.
310 * 0 - No (default)
311 * 1 - Yes
312 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
313 * 0 - Disable (default)
314 * 1 - Enable
315 * @acg_enable: For enabling Active Clock Gating in the controller
316 * 0 - No
317 * 1 - Yes
318 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
319 * 0 - No (default)
320 * 1 - Yes
321 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
322 * when attached to a Full Speed or Low Speed device in
323 * host mode.
324 * 0 - Don't support low power mode (default)
325 * 1 - Support low power mode
326 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
327 * when connected to a Low Speed device in host
328 * mode. This parameter is applicable only if
329 * host_support_fs_ls_low_power is enabled.
330 * 0 - 48 MHz
331 * (default when phy_type is UTMI+ or ULPI)
332 * 1 - 6 MHz
333 * (default when phy_type is Full Speed)
334 * @oc_disable: Flag to disable overcurrent condition.
335 * 0 - Allow overcurrent condition to get detected
336 * 1 - Disable overcurrent condtion to get detected
337 * @ts_dline: Enable Term Select Dline pulsing
338 * 0 - No (default)
339 * 1 - Yes
340 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
341 * 0 - No (default for core < 2.92a)
342 * 1 - Yes (default for core >= 2.92a)
343 * @ahbcfg: This field allows the default value of the GAHBCFG
344 * register to be overridden
345 * -1 - GAHBCFG value will be set to 0x06
346 * (INCR, default)
347 * all others - GAHBCFG value will be overridden with
348 * this value
349 * Not all bits can be controlled like this, the
350 * bits defined by GAHBCFG_CTRL_MASK are controlled
351 * by the driver and are ignored in this
352 * configuration value.
353 * @uframe_sched: True to enable the microframe scheduler
354 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
355 * Disable CONIDSTSCHNG controller interrupt in such
356 * case.
357 * 0 - No (default)
358 * 1 - Yes
359 * @power_down: Specifies whether the controller support power_down.
360 * If power_down is enabled, the controller will enter
361 * power_down in both peripheral and host mode when
362 * needed.
363 * 0 - No (default)
364 * 1 - Partial power down
365 * 2 - Hibernation
366 * @no_clock_gating: Specifies whether to avoid clock gating feature.
367 * 0 - No (use clock gating)
368 * 1 - Yes (avoid it)
369 * @lpm: Enable LPM support.
370 * 0 - No
371 * 1 - Yes
372 * @lpm_clock_gating: Enable core PHY clock gating.
373 * 0 - No
374 * 1 - Yes
375 * @besl: Enable LPM Errata support.
376 * 0 - No
377 * 1 - Yes
378 * @hird_threshold_en: HIRD or HIRD Threshold enable.
379 * 0 - No
380 * 1 - Yes
381 * @hird_threshold: Value of BESL or HIRD Threshold.
382 * @ref_clk_per: Indicates in terms of pico seconds the period
383 * of ref_clk.
384 * 62500 - 16MHz
385 * 58823 - 17MHz
386 * 52083 - 19.2MHz
387 * 50000 - 20MHz
388 * 41666 - 24MHz
389 * 33333 - 30MHz (default)
390 * 25000 - 40MHz
391 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
392 * the controller should generate an interrupt if the
393 * device had been in L1 state until that period.
394 * This is used by SW to initiate Remote WakeUp in the
395 * controller so as to sync to the uF number from the host.
396 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
397 * register.
398 * 0 - Deactivate the transceiver (default)
399 * 1 - Activate the transceiver
400 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
401 * detection using GGPIO register.
402 * 0 - Deactivate the external level detection (default)
403 * 1 - Activate the external level detection
404 * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent
405 * detection.
406 * 0 - Deactivate the overcurrent detection
407 * 1 - Activate the overcurrent detection (default)
408 * @g_dma: Enables gadget dma usage (default: autodetect).
409 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
410 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
411 * DWORDS from 16-32768 (default: 2048 if
412 * possible, otherwise autodetect).
413 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
414 * DWORDS from 16-32768 (default: 1024 if
415 * possible, otherwise autodetect).
416 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
417 * mode. Each value corresponds to one EP
418 * starting from EP1 (max 15 values). Sizes are
419 * in DWORDS with possible values from
420 * 16-32768 (default: 256, 256, 256, 256, 768,
421 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
422 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
423 * while full&low speed device connect. And change speed
424 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
425 * 0 - No (default)
426 * 1 - Yes
427 * @service_interval: Enable service interval based scheduling.
428 * 0 - No
429 * 1 - Yes
430 *
431 * The following parameters may be specified when starting the module. These
432 * parameters define how the DWC_otg controller should be configured. A
433 * value of -1 (or any other out of range value) for any parameter means
434 * to read the value from hardware (if possible) or use the builtin
435 * default described above.
436 */
437 struct dwc2_core_params {
438 struct usb_otg_caps otg_caps;
439 u8 phy_type;
440 #define DWC2_PHY_TYPE_PARAM_FS 0
441 #define DWC2_PHY_TYPE_PARAM_UTMI 1
442 #define DWC2_PHY_TYPE_PARAM_ULPI 2
443
444 u8 speed;
445 #define DWC2_SPEED_PARAM_HIGH 0
446 #define DWC2_SPEED_PARAM_FULL 1
447 #define DWC2_SPEED_PARAM_LOW 2
448
449 u8 phy_utmi_width;
450 bool eusb2_disc;
451 bool phy_ulpi_ddr;
452 bool phy_ulpi_ext_vbus;
453 bool enable_dynamic_fifo;
454 bool en_multiple_tx_fifo;
455 bool i2c_enable;
456 bool acg_enable;
457 bool ulpi_fs_ls;
458 bool ts_dline;
459 bool reload_ctl;
460 bool uframe_sched;
461 bool external_id_pin_ctl;
462
463 int power_down;
464 #define DWC2_POWER_DOWN_PARAM_NONE 0
465 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1
466 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
467 bool no_clock_gating;
468
469 bool lpm;
470 bool lpm_clock_gating;
471 bool besl;
472 bool hird_threshold_en;
473 bool service_interval;
474 u8 hird_threshold;
475 bool activate_stm_fs_transceiver;
476 bool activate_stm_id_vb_detection;
477 bool activate_ingenic_overcurrent_detection;
478 bool ipg_isoc_en;
479 u16 max_packet_count;
480 u32 max_transfer_size;
481 u32 ahbcfg;
482
483 /* GREFCLK parameters */
484 u32 ref_clk_per;
485 u16 sof_cnt_wkup_alert;
486
487 /* Host parameters */
488 bool host_dma;
489 bool dma_desc_enable;
490 bool dma_desc_fs_enable;
491 bool host_support_fs_ls_low_power;
492 bool host_ls_low_power_phy_clk;
493 bool oc_disable;
494
495 u8 host_channels;
496 u16 host_rx_fifo_size;
497 u16 host_nperio_tx_fifo_size;
498 u16 host_perio_tx_fifo_size;
499
500 /* Gadget parameters */
501 bool g_dma;
502 bool g_dma_desc;
503 u32 g_rx_fifo_size;
504 u32 g_np_tx_fifo_size;
505 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
506
507 bool change_speed_quirk;
508 };
509
510 /**
511 * struct dwc2_hw_params - Autodetected parameters.
512 *
513 * These parameters are the various parameters read from hardware
514 * registers during initialization. They typically contain the best
515 * supported or maximum value that can be configured in the
516 * corresponding dwc2_core_params value.
517 *
518 * The values that are not in dwc2_core_params are documented below.
519 *
520 * @op_mode: Mode of Operation
521 * 0 - HNP- and SRP-Capable OTG (Host & Device)
522 * 1 - SRP-Capable OTG (Host & Device)
523 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
524 * 3 - SRP-Capable Device
525 * 4 - Non-OTG Device
526 * 5 - SRP-Capable Host
527 * 6 - Non-OTG Host
528 * @arch: Architecture
529 * 0 - Slave only
530 * 1 - External DMA
531 * 2 - Internal DMA
532 * @ipg_isoc_en: This feature indicates that the controller supports
533 * the worst-case scenario of Rx followed by Rx
534 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
535 * specification for any token following ISOC OUT token.
536 * 0 - Don't support
537 * 1 - Support
538 * @power_optimized: Are power optimizations enabled?
539 * @num_dev_ep: Number of device endpoints available
540 * @num_dev_in_eps: Number of device IN endpoints available
541 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
542 * available
543 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
544 * Depth
545 * 0 to 30
546 * @host_perio_tx_q_depth:
547 * Host Mode Periodic Request Queue Depth
548 * 2, 4 or 8
549 * @nperio_tx_q_depth:
550 * Non-Periodic Request Queue Depth
551 * 2, 4 or 8
552 * @hs_phy_type: High-speed PHY interface type
553 * 0 - High-speed interface not supported
554 * 1 - UTMI+
555 * 2 - ULPI
556 * 3 - UTMI+ and ULPI
557 * @fs_phy_type: Full-speed PHY interface type
558 * 0 - Full speed interface not supported
559 * 1 - Dedicated full speed interface
560 * 2 - FS pins shared with UTMI+ pins
561 * 3 - FS pins shared with ULPI pins
562 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
563 * @hibernation: Is hibernation enabled?
564 * @utmi_phy_data_width: UTMI+ PHY data width
565 * 0 - 8 bits
566 * 1 - 16 bits
567 * 2 - 8 or 16 bits
568 * @snpsid: Value from SNPSID register
569 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
570 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
571 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
572 * address DMA mode or descriptor DMA mode for accessing
573 * the data FIFOs. The driver will automatically detect the
574 * value for this if none is specified.
575 * 0 - Address DMA
576 * 1 - Descriptor DMA (default, if available)
577 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
578 * 1 - Allow dynamic FIFO sizing (default, if available)
579 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
580 * are enabled for non-periodic IN endpoints in device
581 * mode.
582 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
583 * in host mode when dynamic FIFO sizing is enabled
584 * 16 to 32768
585 * Actual maximum value is autodetected and also
586 * the default.
587 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
588 * host mode when dynamic FIFO sizing is enabled
589 * 16 to 32768
590 * Actual maximum value is autodetected and also
591 * the default.
592 * @max_transfer_size: The maximum transfer size supported, in bytes
593 * 2047 to 65,535
594 * Actual maximum value is autodetected and also
595 * the default.
596 * @max_packet_count: The maximum number of packets in a transfer
597 * 15 to 511
598 * Actual maximum value is autodetected and also
599 * the default.
600 * @host_channels: The number of host channel registers to use
601 * 1 to 16
602 * Actual maximum value is autodetected and also
603 * the default.
604 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
605 * in device mode when dynamic FIFO sizing is enabled
606 * 16 to 32768
607 * Actual maximum value is autodetected and also
608 * the default.
609 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
610 * speed PHY. This parameter is only applicable if phy_type
611 * is FS.
612 * 0 - No (default)
613 * 1 - Yes
614 * @acg_enable: For enabling Active Clock Gating in the controller
615 * 0 - Disable
616 * 1 - Enable
617 * @lpm_mode: For enabling Link Power Management in the controller
618 * 0 - Disable
619 * 1 - Enable
620 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
621 * FIFO sizing is enabled 16 to 32768
622 * Actual maximum value is autodetected and also
623 * the default.
624 * @service_interval_mode: For enabling service interval based scheduling in the
625 * controller.
626 * 0 - Disable
627 * 1 - Enable
628 */
629 struct dwc2_hw_params {
630 unsigned op_mode:3;
631 unsigned arch:2;
632 unsigned dma_desc_enable:1;
633 unsigned enable_dynamic_fifo:1;
634 unsigned en_multiple_tx_fifo:1;
635 unsigned rx_fifo_size:16;
636 unsigned host_nperio_tx_fifo_size:16;
637 unsigned dev_nperio_tx_fifo_size:16;
638 unsigned host_perio_tx_fifo_size:16;
639 unsigned nperio_tx_q_depth:3;
640 unsigned host_perio_tx_q_depth:3;
641 unsigned dev_token_q_depth:5;
642 unsigned max_transfer_size:26;
643 unsigned max_packet_count:11;
644 unsigned host_channels:5;
645 unsigned hs_phy_type:2;
646 unsigned fs_phy_type:2;
647 unsigned i2c_enable:1;
648 unsigned acg_enable:1;
649 unsigned num_dev_ep:4;
650 unsigned num_dev_in_eps : 4;
651 unsigned num_dev_perio_in_ep:4;
652 unsigned total_fifo_size:16;
653 unsigned power_optimized:1;
654 unsigned hibernation:1;
655 unsigned utmi_phy_data_width:2;
656 unsigned lpm_mode:1;
657 unsigned ipg_isoc_en:1;
658 unsigned service_interval_mode:1;
659 u32 snpsid;
660 u32 dev_ep_dirs;
661 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
662 };
663
664 /* Size of control and EP0 buffers */
665 #define DWC2_CTRL_BUFF_SIZE 8
666
667 /**
668 * struct dwc2_gregs_backup - Holds global registers state before
669 * entering partial power down
670 * @gotgctl: Backup of GOTGCTL register
671 * @gintmsk: Backup of GINTMSK register
672 * @gahbcfg: Backup of GAHBCFG register
673 * @gusbcfg: Backup of GUSBCFG register
674 * @grxfsiz: Backup of GRXFSIZ register
675 * @gnptxfsiz: Backup of GNPTXFSIZ register
676 * @gi2cctl: Backup of GI2CCTL register
677 * @glpmcfg: Backup of GLPMCFG register
678 * @gdfifocfg: Backup of GDFIFOCFG register
679 * @pcgcctl: Backup of PCGCCTL register
680 * @pcgcctl1: Backup of PCGCCTL1 register
681 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
682 * @gpwrdn: Backup of GPWRDN register
683 * @valid: True if registers values backuped.
684 */
685 struct dwc2_gregs_backup {
686 u32 gotgctl;
687 u32 gintmsk;
688 u32 gahbcfg;
689 u32 gusbcfg;
690 u32 grxfsiz;
691 u32 gnptxfsiz;
692 u32 gi2cctl;
693 u32 glpmcfg;
694 u32 pcgcctl;
695 u32 pcgcctl1;
696 u32 gdfifocfg;
697 u32 gpwrdn;
698 bool valid;
699 };
700
701 /**
702 * struct dwc2_dregs_backup - Holds device registers state before
703 * entering partial power down
704 * @dcfg: Backup of DCFG register
705 * @dctl: Backup of DCTL register
706 * @daintmsk: Backup of DAINTMSK register
707 * @diepmsk: Backup of DIEPMSK register
708 * @doepmsk: Backup of DOEPMSK register
709 * @diepctl: Backup of DIEPCTL register
710 * @dieptsiz: Backup of DIEPTSIZ register
711 * @diepdma: Backup of DIEPDMA register
712 * @doepctl: Backup of DOEPCTL register
713 * @doeptsiz: Backup of DOEPTSIZ register
714 * @doepdma: Backup of DOEPDMA register
715 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
716 * @valid: True if registers values backuped.
717 */
718 struct dwc2_dregs_backup {
719 u32 dcfg;
720 u32 dctl;
721 u32 daintmsk;
722 u32 diepmsk;
723 u32 doepmsk;
724 u32 diepctl[MAX_EPS_CHANNELS];
725 u32 dieptsiz[MAX_EPS_CHANNELS];
726 u32 diepdma[MAX_EPS_CHANNELS];
727 u32 doepctl[MAX_EPS_CHANNELS];
728 u32 doeptsiz[MAX_EPS_CHANNELS];
729 u32 doepdma[MAX_EPS_CHANNELS];
730 u32 dtxfsiz[MAX_EPS_CHANNELS];
731 bool valid;
732 };
733
734 /**
735 * struct dwc2_hregs_backup - Holds host registers state before
736 * entering partial power down
737 * @hcfg: Backup of HCFG register
738 * @hflbaddr: Backup of HFLBADDR register
739 * @haintmsk: Backup of HAINTMSK register
740 * @hcchar: Backup of HCCHAR register
741 * @hcsplt: Backup of HCSPLT register
742 * @hcintmsk: Backup of HCINTMSK register
743 * @hctsiz: Backup of HCTSIZ register
744 * @hdma: Backup of HCDMA register
745 * @hcdmab: Backup of HCDMAB register
746 * @hprt0: Backup of HPTR0 register
747 * @hfir: Backup of HFIR register
748 * @hptxfsiz: Backup of HPTXFSIZ register
749 * @valid: True if registers values backuped.
750 */
751 struct dwc2_hregs_backup {
752 u32 hcfg;
753 u32 hflbaddr;
754 u32 haintmsk;
755 u32 hcchar[MAX_EPS_CHANNELS];
756 u32 hcsplt[MAX_EPS_CHANNELS];
757 u32 hcintmsk[MAX_EPS_CHANNELS];
758 u32 hctsiz[MAX_EPS_CHANNELS];
759 u32 hcidma[MAX_EPS_CHANNELS];
760 u32 hcidmab[MAX_EPS_CHANNELS];
761 u32 hprt0;
762 u32 hfir;
763 u32 hptxfsiz;
764 bool valid;
765 };
766
767 /*
768 * Constants related to high speed periodic scheduling
769 *
770 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
771 * reservation point of view it's assumed that the schedule goes right back to
772 * the beginning after the end of the schedule.
773 *
774 * What does that mean for scheduling things with a long interval? It means
775 * we'll reserve time for them in every possible microframe that they could
776 * ever be scheduled in. ...but we'll still only actually schedule them as
777 * often as they were requested.
778 *
779 * We keep our schedule in a "bitmap" structure. This simplifies having
780 * to keep track of and merge intervals: we just let the bitmap code do most
781 * of the heavy lifting. In a way scheduling is much like memory allocation.
782 *
783 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
784 * supposed to schedule for periodic transfers). That's according to spec.
785 *
786 * Note that though we only schedule 80% of each microframe, the bitmap that we
787 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
788 * space for each uFrame).
789 *
790 * Requirements:
791 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
792 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
793 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
794 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
795 */
796 #define DWC2_US_PER_UFRAME 125
797 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
798
799 #define DWC2_HS_SCHEDULE_UFRAMES 8
800 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
801 DWC2_HS_PERIODIC_US_PER_UFRAME)
802
803 /*
804 * Constants related to low speed scheduling
805 *
806 * For high speed we schedule every 1us. For low speed that's a bit overkill,
807 * so we make up a unit called a "slice" that's worth 25us. There are 40
808 * slices in a full frame and we can schedule 36 of those (90%) for periodic
809 * transfers.
810 *
811 * Our low speed schedule can be as short as 1 frame or could be longer. When
812 * we only schedule 1 frame it means that we'll need to reserve a time every
813 * frame even for things that only transfer very rarely, so something that runs
814 * every 2048 frames will get time reserved in every frame. Our low speed
815 * schedule can be longer and we'll be able to handle more overlap, but that
816 * will come at increased memory cost and increased time to schedule.
817 *
818 * Note: one other advantage of a short low speed schedule is that if we mess
819 * up and miss scheduling we can jump in and use any of the slots that we
820 * happened to reserve.
821 *
822 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
823 * the schedule. There will be one schedule per TT.
824 *
825 * Requirements:
826 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
827 */
828 #define DWC2_US_PER_SLICE 25
829 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
830
831 #define DWC2_ROUND_US_TO_SLICE(us) \
832 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
833 DWC2_US_PER_SLICE)
834
835 #define DWC2_LS_PERIODIC_US_PER_FRAME \
836 900
837 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
838 (DWC2_LS_PERIODIC_US_PER_FRAME / \
839 DWC2_US_PER_SLICE)
840
841 #define DWC2_LS_SCHEDULE_FRAMES 1
842 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
843 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
844
845 /**
846 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
847 * and periodic schedules
848 *
849 * These are common for both host and peripheral modes:
850 *
851 * @dev: The struct device pointer
852 * @regs: Pointer to controller regs
853 * @hw_params: Parameters that were autodetected from the
854 * hardware registers
855 * @params: Parameters that define how the core should be configured
856 * @op_state: The operational State, during transitions (a_host=>
857 * a_peripheral and b_device=>b_host) this may not match
858 * the core, but allows the software to determine
859 * transitions
860 * @dr_mode: Requested mode of operation, one of following:
861 * - USB_DR_MODE_PERIPHERAL
862 * - USB_DR_MODE_HOST
863 * - USB_DR_MODE_OTG
864 * @role_sw: usb_role_switch handle
865 * @role_sw_default_mode: default operation mode of controller while usb role
866 * is USB_ROLE_NONE
867 * @hcd_enabled: Host mode sub-driver initialization indicator.
868 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
869 * @ll_hw_enabled: Status of low-level hardware resources.
870 * @hibernated: True if core is hibernated
871 * @in_ppd: True if core is partial power down mode.
872 * @bus_suspended: True if bus is suspended
873 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
874 * remote wakeup.
875 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
876 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
877 * suspend if we need USB to wake us up.
878 * @frame_number: Frame number read from the core. For both device
879 * and host modes. The value ranges are from 0
880 * to HFNUM_MAX_FRNUM.
881 * @phy: The otg phy transceiver structure for phy control.
882 * @uphy: The otg phy transceiver structure for old USB phy
883 * control.
884 * @plat: The platform specific configuration data. This can be
885 * removed once all SoCs support usb transceiver.
886 * @supplies: Definition of USB power supplies
887 * @vbus_supply: Regulator supplying vbus.
888 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
889 * supply ID and VBUS detection hardware.
890 * @lock: Spinlock that protects all the driver data structures
891 * @priv: Stores a pointer to the struct usb_hcd
892 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
893 * transfer are in process of being queued
894 * @srp_success: Stores status of SRP request in the case of a FS PHY
895 * with an I2C interface
896 * @wq_otg: Workqueue object used for handling of some interrupts
897 * @wf_otg: Work object for handling Connector ID Status Change
898 * interrupt
899 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
900 * @lx_state: Lx state of connected device
901 * @gr_backup: Backup of global registers during suspend
902 * @dr_backup: Backup of device registers during suspend
903 * @hr_backup: Backup of host registers during suspend
904 * @needs_byte_swap: Specifies whether the opposite endianness.
905 *
906 * These are for host mode:
907 *
908 * @flags: Flags for handling root port state changes
909 * @flags.d32: Contain all root port flags
910 * @flags.b: Separate root port flags from each other
911 * @flags.b.port_connect_status_change: True if root port connect status
912 * changed
913 * @flags.b.port_connect_status: True if device connected to root port
914 * @flags.b.port_reset_change: True if root port reset status changed
915 * @flags.b.port_enable_change: True if root port enable status changed
916 * @flags.b.port_suspend_change: True if root port suspend status changed
917 * @flags.b.port_over_current_change: True if root port over current state
918 * changed.
919 * @flags.b.port_l1_change: True if root port l1 status changed
920 * @flags.b.reserved: Reserved bits of root port register
921 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
922 * Transfers associated with these QHs are not currently
923 * assigned to a host channel.
924 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
925 * Transfers associated with these QHs are currently
926 * assigned to a host channel.
927 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
928 * non-periodic schedule
929 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
930 * Transfers associated with these QHs are not currently
931 * assigned to a host channel.
932 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
933 * list of QHs for periodic transfers that are _not_
934 * scheduled for the next frame. Each QH in the list has an
935 * interval counter that determines when it needs to be
936 * scheduled for execution. This scheduling mechanism
937 * allows only a simple calculation for periodic bandwidth
938 * used (i.e. must assume that all periodic transfers may
939 * need to execute in the same frame). However, it greatly
940 * simplifies scheduling and should be sufficient for the
941 * vast majority of OTG hosts, which need to connect to a
942 * small number of peripherals at one time. Items move from
943 * this list to periodic_sched_ready when the QH interval
944 * counter is 0 at SOF.
945 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
946 * the next frame, but have not yet been assigned to host
947 * channels. Items move from this list to
948 * periodic_sched_assigned as host channels become
949 * available during the current frame.
950 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
951 * frame that are assigned to host channels. Items move
952 * from this list to periodic_sched_queued as the
953 * transactions for the QH are queued to the DWC_otg
954 * controller.
955 * @periodic_sched_queued: List of periodic QHs that have been queued for
956 * execution. Items move from this list to either
957 * periodic_sched_inactive or periodic_sched_ready when the
958 * channel associated with the transfer is released. If the
959 * interval for the QH is 1, the item moves to
960 * periodic_sched_ready because it must be rescheduled for
961 * the next frame. Otherwise, the item moves to
962 * periodic_sched_inactive.
963 * @split_order: List keeping track of channels doing splits, in order.
964 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
965 * This value is in microseconds per (micro)frame. The
966 * assumption is that all periodic transfers may occur in
967 * the same (micro)frame.
968 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
969 * host is in high speed mode; low speed schedules are
970 * stored elsewhere since we need one per TT.
971 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
972 * SOF enable/disable.
973 * @free_hc_list: Free host channels in the controller. This is a list of
974 * struct dwc2_host_chan items.
975 * @periodic_channels: Number of host channels assigned to periodic transfers.
976 * Currently assuming that there is a dedicated host
977 * channel for each periodic transaction and at least one
978 * host channel is available for non-periodic transactions.
979 * @non_periodic_channels: Number of host channels assigned to non-periodic
980 * transfers
981 * @available_host_channels: Number of host channels available for the
982 * microframe scheduler to use
983 * @hc_ptr_array: Array of pointers to the host channel descriptors.
984 * Allows accessing a host channel descriptor given the
985 * host channel number. This is useful in interrupt
986 * handlers.
987 * @status_buf: Buffer used for data received during the status phase of
988 * a control transfer.
989 * @status_buf_dma: DMA address for status_buf
990 * @start_work: Delayed work for handling host A-cable connection
991 * @reset_work: Delayed work for handling a port reset
992 * @phy_reset_work: Work structure for doing a PHY reset
993 * @otg_port: OTG port number
994 * @frame_list: Frame list
995 * @frame_list_dma: Frame list DMA address
996 * @frame_list_sz: Frame list size
997 * @desc_gen_cache: Kmem cache for generic descriptors
998 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
999 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
1000 *
1001 * These are for peripheral mode:
1002 *
1003 * @driver: USB gadget driver
1004 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1005 * @num_of_eps: Number of available EPs (excluding EP0)
1006 * @debug_root: Root directrory for debugfs.
1007 * @ep0_reply: Request used for ep0 reply.
1008 * @ep0_buff: Buffer for EP0 reply data, if needed.
1009 * @ctrl_buff: Buffer for EP0 control requests.
1010 * @ctrl_req: Request for EP0 control packets.
1011 * @ep0_state: EP0 control transfers state
1012 * @delayed_status: true when gadget driver asks for delayed status
1013 * @test_mode: USB test mode requested by the host
1014 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1015 * remote-wakeup signalling
1016 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1017 * @setup_desc: EP0 setup stage desc chain pointer
1018 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1019 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1020 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1021 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
1022 * @irq: Interrupt request line number
1023 * @clk: Pointer to otg clock
1024 * @utmi_clk: Pointer to utmi_clk clock
1025 * @reset: Pointer to dwc2 reset controller
1026 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1027 * @regset: A pointer to a struct debugfs_regset32, which contains
1028 * a pointer to an array of register definitions, the
1029 * array size and the base address where the register bank
1030 * is to be found.
1031 * @last_frame_num: Number of last frame. Range from 0 to 32768
1032 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1033 * defined, for missed SOFs tracking. Array holds that
1034 * frame numbers, which not equal to last_frame_num +1
1035 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1036 * defined, for missed SOFs tracking.
1037 * If current_frame_number != last_frame_num+1
1038 * then last_frame_num added to this array
1039 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1040 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1041 * 0 - if missed SOFs frame numbers not dumbed
1042 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1043 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1044 * then that fifo is used
1045 * @gadget: Represents a usb gadget device
1046 * @connected: Used in slave mode. True if device connected with host
1047 * @eps_in: The IN endpoints being supplied to the gadget framework
1048 * @eps_out: The OUT endpoints being supplied to the gadget framework
1049 * @new_connection: Used in host mode. True if there are new connected
1050 * device
1051 * @enabled: Indicates the enabling state of controller
1052 *
1053 */
1054 struct dwc2_hsotg {
1055 struct device *dev;
1056 void __iomem *regs;
1057 /** Params detected from hardware */
1058 struct dwc2_hw_params hw_params;
1059 /** Params to actually use */
1060 struct dwc2_core_params params;
1061 enum usb_otg_state op_state;
1062 enum usb_dr_mode dr_mode;
1063 struct usb_role_switch *role_sw;
1064 enum usb_dr_mode role_sw_default_mode;
1065 unsigned int hcd_enabled:1;
1066 unsigned int gadget_enabled:1;
1067 unsigned int ll_hw_enabled:1;
1068 unsigned int hibernated:1;
1069 unsigned int in_ppd:1;
1070 bool bus_suspended;
1071 unsigned int reset_phy_on_wake:1;
1072 unsigned int need_phy_for_wake:1;
1073 unsigned int phy_off_for_suspend:1;
1074 u16 frame_number;
1075
1076 struct phy *phy;
1077 struct usb_phy *uphy;
1078 struct dwc2_hsotg_plat *plat;
1079 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1080 struct regulator *vbus_supply;
1081 struct regulator *usb33d;
1082
1083 spinlock_t lock;
1084 void *priv;
1085 int irq;
1086 struct clk *clk;
1087 struct clk *utmi_clk;
1088 struct reset_control *reset;
1089 struct reset_control *reset_ecc;
1090
1091 unsigned int queuing_high_bandwidth:1;
1092 unsigned int srp_success:1;
1093
1094 struct workqueue_struct *wq_otg;
1095 struct work_struct wf_otg;
1096 struct timer_list wkp_timer;
1097 enum dwc2_lx_state lx_state;
1098 struct dwc2_gregs_backup gr_backup;
1099 struct dwc2_dregs_backup dr_backup;
1100 struct dwc2_hregs_backup hr_backup;
1101
1102 struct dentry *debug_root;
1103 struct debugfs_regset32 *regset;
1104 bool needs_byte_swap;
1105
1106 /* DWC OTG HW Release versions */
1107 #define DWC2_CORE_REV_4_30a 0x4f54430a
1108 #define DWC2_CORE_REV_2_71a 0x4f54271a
1109 #define DWC2_CORE_REV_2_72a 0x4f54272a
1110 #define DWC2_CORE_REV_2_80a 0x4f54280a
1111 #define DWC2_CORE_REV_2_90a 0x4f54290a
1112 #define DWC2_CORE_REV_2_91a 0x4f54291a
1113 #define DWC2_CORE_REV_2_92a 0x4f54292a
1114 #define DWC2_CORE_REV_2_94a 0x4f54294a
1115 #define DWC2_CORE_REV_3_00a 0x4f54300a
1116 #define DWC2_CORE_REV_3_10a 0x4f54310a
1117 #define DWC2_CORE_REV_4_00a 0x4f54400a
1118 #define DWC2_CORE_REV_4_20a 0x4f54420a
1119 #define DWC2_CORE_REV_5_00a 0x4f54500a
1120 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
1121 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
1122 #define DWC2_HS_IOT_REV_5_00a 0x5532500a
1123 #define DWC2_CORE_REV_MASK 0x0000ffff
1124
1125 /* DWC OTG HW Core ID */
1126 #define DWC2_OTG_ID 0x4f540000
1127 #define DWC2_FS_IOT_ID 0x55310000
1128 #define DWC2_HS_IOT_ID 0x55320000
1129
1130 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1131 union dwc2_hcd_internal_flags {
1132 u32 d32;
1133 struct {
1134 unsigned port_connect_status_change:1;
1135 unsigned port_connect_status:1;
1136 unsigned port_reset_change:1;
1137 unsigned port_enable_change:1;
1138 unsigned port_suspend_change:1;
1139 unsigned port_over_current_change:1;
1140 unsigned port_l1_change:1;
1141 unsigned reserved:25;
1142 } b;
1143 } flags;
1144
1145 struct list_head non_periodic_sched_inactive;
1146 struct list_head non_periodic_sched_waiting;
1147 struct list_head non_periodic_sched_active;
1148 struct list_head *non_periodic_qh_ptr;
1149 struct list_head periodic_sched_inactive;
1150 struct list_head periodic_sched_ready;
1151 struct list_head periodic_sched_assigned;
1152 struct list_head periodic_sched_queued;
1153 struct list_head split_order;
1154 u16 periodic_usecs;
1155 DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US);
1156 u16 periodic_qh_count;
1157 bool new_connection;
1158
1159 u16 last_frame_num;
1160
1161 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1162 #define FRAME_NUM_ARRAY_SIZE 1000
1163 u16 *frame_num_array;
1164 u16 *last_frame_num_array;
1165 int frame_num_idx;
1166 int dumped_frame_num_array;
1167 #endif
1168
1169 struct list_head free_hc_list;
1170 int periodic_channels;
1171 int non_periodic_channels;
1172 int available_host_channels;
1173 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1174 u8 *status_buf;
1175 dma_addr_t status_buf_dma;
1176 #define DWC2_HCD_STATUS_BUF_SIZE 64
1177
1178 struct delayed_work start_work;
1179 struct delayed_work reset_work;
1180 struct work_struct phy_reset_work;
1181 u8 otg_port;
1182 u32 *frame_list;
1183 dma_addr_t frame_list_dma;
1184 u32 frame_list_sz;
1185 struct kmem_cache *desc_gen_cache;
1186 struct kmem_cache *desc_hsisoc_cache;
1187 struct kmem_cache *unaligned_cache;
1188 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1189
1190 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1191
1192 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1193 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1194 /* Gadget structures */
1195 struct usb_gadget_driver *driver;
1196 int fifo_mem;
1197 unsigned int dedicated_fifos:1;
1198 unsigned char num_of_eps;
1199 u32 fifo_map;
1200
1201 struct usb_request *ep0_reply;
1202 struct usb_request *ctrl_req;
1203 void *ep0_buff;
1204 void *ctrl_buff;
1205 enum dwc2_ep0_state ep0_state;
1206 unsigned delayed_status : 1;
1207 u8 test_mode;
1208
1209 dma_addr_t setup_desc_dma[2];
1210 struct dwc2_dma_desc *setup_desc[2];
1211 dma_addr_t ctrl_in_desc_dma;
1212 struct dwc2_dma_desc *ctrl_in_desc;
1213 dma_addr_t ctrl_out_desc_dma;
1214 struct dwc2_dma_desc *ctrl_out_desc;
1215
1216 struct usb_gadget gadget;
1217 unsigned int enabled:1;
1218 unsigned int connected:1;
1219 unsigned int remote_wakeup_allowed:1;
1220 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1221 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1222 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1223 };
1224
1225 /* Normal architectures just use readl/write */
dwc2_readl(struct dwc2_hsotg * hsotg,u32 offset)1226 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1227 {
1228 u32 val;
1229
1230 val = readl(hsotg->regs + offset);
1231 if (hsotg->needs_byte_swap)
1232 return swab32(val);
1233 else
1234 return val;
1235 }
1236
dwc2_writel(struct dwc2_hsotg * hsotg,u32 value,u32 offset)1237 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1238 {
1239 if (hsotg->needs_byte_swap)
1240 writel(swab32(value), hsotg->regs + offset);
1241 else
1242 writel(value, hsotg->regs + offset);
1243
1244 #ifdef DWC2_LOG_WRITES
1245 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1246 #endif
1247 }
1248
dwc2_readl_rep(struct dwc2_hsotg * hsotg,u32 offset,void * buffer,unsigned int count)1249 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1250 void *buffer, unsigned int count)
1251 {
1252 if (count) {
1253 u32 *buf = buffer;
1254
1255 do {
1256 u32 x = dwc2_readl(hsotg, offset);
1257 *buf++ = x;
1258 } while (--count);
1259 }
1260 }
1261
dwc2_writel_rep(struct dwc2_hsotg * hsotg,u32 offset,const void * buffer,unsigned int count)1262 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1263 const void *buffer, unsigned int count)
1264 {
1265 if (count) {
1266 const u32 *buf = buffer;
1267
1268 do {
1269 dwc2_writel(hsotg, *buf++, offset);
1270 } while (--count);
1271 }
1272 }
1273
1274 /* Reasons for halting a host channel */
1275 enum dwc2_halt_status {
1276 DWC2_HC_XFER_NO_HALT_STATUS,
1277 DWC2_HC_XFER_COMPLETE,
1278 DWC2_HC_XFER_URB_COMPLETE,
1279 DWC2_HC_XFER_ACK,
1280 DWC2_HC_XFER_NAK,
1281 DWC2_HC_XFER_NYET,
1282 DWC2_HC_XFER_STALL,
1283 DWC2_HC_XFER_XACT_ERR,
1284 DWC2_HC_XFER_FRAME_OVERRUN,
1285 DWC2_HC_XFER_BABBLE_ERR,
1286 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1287 DWC2_HC_XFER_AHB_ERR,
1288 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1289 DWC2_HC_XFER_URB_DEQUEUE,
1290 };
1291
1292 /* Core version information */
dwc2_is_iot(struct dwc2_hsotg * hsotg)1293 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1294 {
1295 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1296 }
1297
dwc2_is_fs_iot(struct dwc2_hsotg * hsotg)1298 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1299 {
1300 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1301 }
1302
dwc2_is_hs_iot(struct dwc2_hsotg * hsotg)1303 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1304 {
1305 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1306 }
1307
1308 /*
1309 * The following functions support initialization of the core driver component
1310 * and the DWC_otg controller
1311 */
1312 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1313 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1314 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
1315 bool restore);
1316 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1317 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1318 int reset, int is_host);
1319 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1320 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1321
1322 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1323 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1324
1325 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1326
1327 int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1328
1329 /*
1330 * Common core Functions.
1331 * The following functions support managing the DWC_otg controller in either
1332 * device or host mode.
1333 */
1334 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1335 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1336 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1337
1338 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1339 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1340
1341 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1342 int is_host);
1343 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1344 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1345
1346 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1347 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup);
1348
1349 /* This function should be called on every hardware interrupt. */
1350 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1351
1352 /* The device ID match table */
1353 extern const struct of_device_id dwc2_of_match_table[];
1354 extern const struct acpi_device_id dwc2_acpi_match[];
1355 extern const struct pci_device_id dwc2_pci_ids[];
1356
1357 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1358 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1359
1360 /* Common polling functions */
1361 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1362 u32 timeout);
1363 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1364 u32 timeout);
1365 /* Parameters */
1366 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1367 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1368
1369 /*
1370 * The following functions check the controller's OTG operation mode
1371 * capability (GHWCFG2.OTG_MODE).
1372 *
1373 * These functions can be used before the internal hsotg->hw_params
1374 * are read in and cached so they always read directly from the
1375 * GHWCFG2 register.
1376 */
1377 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1378 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1379 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1380 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1381
1382 /*
1383 * Returns the mode of operation, host or device
1384 */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1385 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1386 {
1387 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1388 }
1389
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1390 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1391 {
1392 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1393 }
1394
1395 int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1396 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1397 void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1398 void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1399
1400 /*
1401 * Dump core registers and SPRAM
1402 */
1403 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1404 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1405 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1406
1407 /* Gadget defines */
1408 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1409 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1410 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1411 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1412 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1413 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1414 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1415 bool reset);
1416 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1417 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1418 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1419 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1420 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1421 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1422 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1423 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1424 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1425 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1426 int rem_wakeup, int reset);
1427 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1428 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1429 bool restore);
1430 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
1431 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1432 int rem_wakeup);
1433 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1434 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1435 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1436 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1437 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1438 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
1439 { hsotg->fifo_map = 0; }
1440 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1441 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1442 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1443 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1444 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1445 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1446 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg)1447 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1448 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1449 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1450 bool reset) {}
dwc2_hsotg_core_disconnect(struct dwc2_hsotg * hsotg)1451 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1452 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1453 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1454 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1455 int testmode)
1456 { return 0; }
1457 #define dwc2_is_device_connected(hsotg) (0)
1458 #define dwc2_is_device_enabled(hsotg) (0)
dwc2_backup_device_registers(struct dwc2_hsotg * hsotg)1459 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1460 { return 0; }
dwc2_restore_device_registers(struct dwc2_hsotg * hsotg,int remote_wakeup)1461 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1462 int remote_wakeup)
1463 { return 0; }
dwc2_gadget_enter_hibernation(struct dwc2_hsotg * hsotg)1464 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1465 { return 0; }
dwc2_gadget_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1466 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1467 int rem_wakeup, int reset)
1468 { return 0; }
dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg * hsotg)1469 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1470 { return 0; }
dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg * hsotg,bool restore)1471 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1472 bool restore)
1473 { return 0; }
dwc2_gadget_enter_clock_gating(struct dwc2_hsotg * hsotg)1474 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1475 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1476 int rem_wakeup) {}
dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg * hsotg)1477 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1478 { return 0; }
dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg * hsotg)1479 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1480 { return 0; }
dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg * hsotg)1481 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1482 { return 0; }
dwc2_gadget_init_lpm(struct dwc2_hsotg * hsotg)1483 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_program_ref_clk(struct dwc2_hsotg * hsotg)1484 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1485 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
1486 #endif
1487
1488 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1489 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1490 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1491 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1492 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1493 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1494 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1495 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
1496 int dwc2_port_resume(struct dwc2_hsotg *hsotg);
1497 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1498 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1499 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1500 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1501 int rem_wakeup, int reset);
1502 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1503 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1504 int rem_wakeup, bool restore);
1505 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
1506 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
1507 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1508 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1509 { schedule_work(&hsotg->phy_reset_work); }
1510 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1511 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1512 { return 0; }
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)1513 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1514 int us)
1515 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1516 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1517 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1518 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1519 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_core_init(struct dwc2_hsotg * hsotg,bool initial_setup)1520 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1521 { return 0; }
dwc2_port_suspend(struct dwc2_hsotg * hsotg,u16 windex)1522 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1523 { return 0; }
dwc2_port_resume(struct dwc2_hsotg * hsotg)1524 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
1525 { return 0; }
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1526 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1527 { return 0; }
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)1528 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1529 { return 0; }
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)1530 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1531 { return 0; }
dwc2_host_enter_hibernation(struct dwc2_hsotg * hsotg)1532 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1533 { return 0; }
dwc2_host_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1534 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1535 int rem_wakeup, int reset)
1536 { return 0; }
dwc2_host_enter_partial_power_down(struct dwc2_hsotg * hsotg)1537 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1538 { return 0; }
dwc2_host_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)1539 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1540 int rem_wakeup, bool restore)
1541 { return 0; }
dwc2_host_enter_clock_gating(struct dwc2_hsotg * hsotg)1542 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_host_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1543 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
1544 int rem_wakeup) {}
dwc2_host_can_poweroff_phy(struct dwc2_hsotg * dwc2)1545 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1546 { return false; }
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1547 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1548
1549 #endif
1550
1551 #endif /* __DWC2_CORE_H__ */
1552