1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PIC32 Integrated Serial Driver. 4 * 5 * Copyright (C) 2015 Microchip Technology, Inc. 6 * 7 * Authors: 8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> 9 */ 10 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_irq.h> 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/console.h> 20 #include <linux/clk.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/delay.h> 25 26 #include <asm/mach-pic32/pic32.h> 27 28 /* UART name and device definitions */ 29 #define PIC32_DEV_NAME "pic32-uart" 30 #define PIC32_MAX_UARTS 6 31 #define PIC32_SDEV_NAME "ttyPIC" 32 33 #define PIC32_UART_DFLT_BRATE 9600 34 #define PIC32_UART_TX_FIFO_DEPTH 8 35 #define PIC32_UART_RX_FIFO_DEPTH 8 36 37 #define PIC32_UART_MODE 0x00 38 #define PIC32_UART_STA 0x10 39 #define PIC32_UART_TX 0x20 40 #define PIC32_UART_RX 0x30 41 #define PIC32_UART_BRG 0x40 42 43 /* struct pic32_sport - pic32 serial port descriptor 44 * @port: uart port descriptor 45 * @idx: port index 46 * @irq_fault: virtual fault interrupt number 47 * @irq_fault_name: irq fault name 48 * @irq_rx: virtual rx interrupt number 49 * @irq_rx_name: irq rx name 50 * @irq_tx: virtual tx interrupt number 51 * @irq_tx_name: irq tx name 52 * @cts_gpiod: clear to send GPIO 53 * @dev: device descriptor 54 **/ 55 struct pic32_sport { 56 struct uart_port port; 57 int idx; 58 59 int irq_fault; 60 const char *irq_fault_name; 61 int irq_rx; 62 const char *irq_rx_name; 63 int irq_tx; 64 const char *irq_tx_name; 65 bool enable_tx_irq; 66 67 struct gpio_desc *cts_gpiod; 68 69 struct clk *clk; 70 71 struct device *dev; 72 }; 73 to_pic32_sport(struct uart_port * port)74 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port) 75 { 76 return container_of(port, struct pic32_sport, port); 77 } 78 pic32_uart_writel(struct pic32_sport * sport,u32 reg,u32 val)79 static inline void pic32_uart_writel(struct pic32_sport *sport, 80 u32 reg, u32 val) 81 { 82 __raw_writel(val, sport->port.membase + reg); 83 } 84 pic32_uart_readl(struct pic32_sport * sport,u32 reg)85 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg) 86 { 87 return __raw_readl(sport->port.membase + reg); 88 } 89 90 /* pic32 uart mode register bits */ 91 #define PIC32_UART_MODE_ON BIT(15) 92 #define PIC32_UART_MODE_FRZ BIT(14) 93 #define PIC32_UART_MODE_SIDL BIT(13) 94 #define PIC32_UART_MODE_IREN BIT(12) 95 #define PIC32_UART_MODE_RTSMD BIT(11) 96 #define PIC32_UART_MODE_RESV1 BIT(10) 97 #define PIC32_UART_MODE_UEN1 BIT(9) 98 #define PIC32_UART_MODE_UEN0 BIT(8) 99 #define PIC32_UART_MODE_WAKE BIT(7) 100 #define PIC32_UART_MODE_LPBK BIT(6) 101 #define PIC32_UART_MODE_ABAUD BIT(5) 102 #define PIC32_UART_MODE_RXINV BIT(4) 103 #define PIC32_UART_MODE_BRGH BIT(3) 104 #define PIC32_UART_MODE_PDSEL1 BIT(2) 105 #define PIC32_UART_MODE_PDSEL0 BIT(1) 106 #define PIC32_UART_MODE_STSEL BIT(0) 107 108 /* pic32 uart status register bits */ 109 #define PIC32_UART_STA_UTXISEL1 BIT(15) 110 #define PIC32_UART_STA_UTXISEL0 BIT(14) 111 #define PIC32_UART_STA_UTXINV BIT(13) 112 #define PIC32_UART_STA_URXEN BIT(12) 113 #define PIC32_UART_STA_UTXBRK BIT(11) 114 #define PIC32_UART_STA_UTXEN BIT(10) 115 #define PIC32_UART_STA_UTXBF BIT(9) 116 #define PIC32_UART_STA_TRMT BIT(8) 117 #define PIC32_UART_STA_URXISEL1 BIT(7) 118 #define PIC32_UART_STA_URXISEL0 BIT(6) 119 #define PIC32_UART_STA_ADDEN BIT(5) 120 #define PIC32_UART_STA_RIDLE BIT(4) 121 #define PIC32_UART_STA_PERR BIT(3) 122 #define PIC32_UART_STA_FERR BIT(2) 123 #define PIC32_UART_STA_OERR BIT(1) 124 #define PIC32_UART_STA_URXDA BIT(0) 125 126 /* pic32_sport pointer for console use */ 127 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; 128 pic32_wait_deplete_txbuf(struct pic32_sport * sport)129 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) 130 { 131 /* wait for tx empty, otherwise chars will be lost or corrupted */ 132 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) 133 udelay(1); 134 } 135 136 /* serial core request to check if uart tx buffer is empty */ pic32_uart_tx_empty(struct uart_port * port)137 static unsigned int pic32_uart_tx_empty(struct uart_port *port) 138 { 139 struct pic32_sport *sport = to_pic32_sport(port); 140 u32 val = pic32_uart_readl(sport, PIC32_UART_STA); 141 142 return (val & PIC32_UART_STA_TRMT) ? 1 : 0; 143 } 144 145 /* serial core request to set UART outputs */ pic32_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)146 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 147 { 148 struct pic32_sport *sport = to_pic32_sport(port); 149 150 /* set loopback mode */ 151 if (mctrl & TIOCM_LOOP) 152 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 153 PIC32_UART_MODE_LPBK); 154 else 155 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 156 PIC32_UART_MODE_LPBK); 157 } 158 159 /* serial core request to return the state of misc UART input pins */ pic32_uart_get_mctrl(struct uart_port * port)160 static unsigned int pic32_uart_get_mctrl(struct uart_port *port) 161 { 162 struct pic32_sport *sport = to_pic32_sport(port); 163 unsigned int mctrl = 0; 164 165 /* get the state of CTS input pin for this port */ 166 if (!sport->cts_gpiod) 167 mctrl |= TIOCM_CTS; 168 else if (gpiod_get_value(sport->cts_gpiod)) 169 mctrl |= TIOCM_CTS; 170 171 /* DSR and CD are not supported in PIC32, so return 1 172 * RI is not supported in PIC32, so return 0 173 */ 174 mctrl |= TIOCM_CD; 175 mctrl |= TIOCM_DSR; 176 177 return mctrl; 178 } 179 180 /* stop tx and start tx are not called in pairs, therefore a flag indicates 181 * the status of irq to control the irq-depth. 182 */ pic32_uart_irqtxen(struct pic32_sport * sport,u8 en)183 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) 184 { 185 if (en && !sport->enable_tx_irq) { 186 enable_irq(sport->irq_tx); 187 sport->enable_tx_irq = true; 188 } else if (!en && sport->enable_tx_irq) { 189 /* use disable_irq_nosync() and not disable_irq() to avoid self 190 * imposed deadlock by not waiting for irq handler to end, 191 * since this callback is called from interrupt context. 192 */ 193 disable_irq_nosync(sport->irq_tx); 194 sport->enable_tx_irq = false; 195 } 196 } 197 198 /* serial core request to disable tx ASAP (used for flow control) */ pic32_uart_stop_tx(struct uart_port * port)199 static void pic32_uart_stop_tx(struct uart_port *port) 200 { 201 struct pic32_sport *sport = to_pic32_sport(port); 202 203 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 204 return; 205 206 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 207 return; 208 209 /* wait for tx empty */ 210 pic32_wait_deplete_txbuf(sport); 211 212 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 213 PIC32_UART_STA_UTXEN); 214 pic32_uart_irqtxen(sport, 0); 215 } 216 217 /* serial core request to (re)enable tx */ pic32_uart_start_tx(struct uart_port * port)218 static void pic32_uart_start_tx(struct uart_port *port) 219 { 220 struct pic32_sport *sport = to_pic32_sport(port); 221 222 pic32_uart_irqtxen(sport, 1); 223 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 224 PIC32_UART_STA_UTXEN); 225 } 226 227 /* serial core request to stop rx, called before port shutdown */ pic32_uart_stop_rx(struct uart_port * port)228 static void pic32_uart_stop_rx(struct uart_port *port) 229 { 230 struct pic32_sport *sport = to_pic32_sport(port); 231 232 /* disable rx interrupts */ 233 disable_irq(sport->irq_rx); 234 235 /* receiver Enable bit OFF */ 236 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 237 PIC32_UART_STA_URXEN); 238 } 239 240 /* serial core request to start/stop emitting break char */ pic32_uart_break_ctl(struct uart_port * port,int ctl)241 static void pic32_uart_break_ctl(struct uart_port *port, int ctl) 242 { 243 struct pic32_sport *sport = to_pic32_sport(port); 244 unsigned long flags; 245 246 uart_port_lock_irqsave(port, &flags); 247 248 if (ctl) 249 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 250 PIC32_UART_STA_UTXBRK); 251 else 252 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 253 PIC32_UART_STA_UTXBRK); 254 255 uart_port_unlock_irqrestore(port, flags); 256 } 257 258 /* get port type in string format */ pic32_uart_type(struct uart_port * port)259 static const char *pic32_uart_type(struct uart_port *port) 260 { 261 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; 262 } 263 264 /* read all chars in rx fifo and send them to core */ pic32_uart_do_rx(struct uart_port * port)265 static void pic32_uart_do_rx(struct uart_port *port) 266 { 267 struct pic32_sport *sport = to_pic32_sport(port); 268 struct tty_port *tty; 269 unsigned int max_count; 270 271 /* limit number of char read in interrupt, should not be 272 * higher than fifo size anyway since we're much faster than 273 * serial port 274 */ 275 max_count = PIC32_UART_RX_FIFO_DEPTH; 276 277 uart_port_lock(port); 278 279 tty = &port->state->port; 280 281 do { 282 u32 sta_reg, c; 283 char flag; 284 285 /* get overrun/fifo empty information from status register */ 286 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); 287 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { 288 289 /* fifo reset is required to clear interrupt */ 290 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 291 PIC32_UART_STA_OERR); 292 293 port->icount.overrun++; 294 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 295 } 296 297 /* Can at least one more character can be read? */ 298 if (!(sta_reg & PIC32_UART_STA_URXDA)) 299 break; 300 301 /* read the character and increment the rx counter */ 302 c = pic32_uart_readl(sport, PIC32_UART_RX); 303 304 port->icount.rx++; 305 flag = TTY_NORMAL; 306 c &= 0xff; 307 308 if (unlikely((sta_reg & PIC32_UART_STA_PERR) || 309 (sta_reg & PIC32_UART_STA_FERR))) { 310 311 /* do stats first */ 312 if (sta_reg & PIC32_UART_STA_PERR) 313 port->icount.parity++; 314 if (sta_reg & PIC32_UART_STA_FERR) 315 port->icount.frame++; 316 317 /* update flag wrt read_status_mask */ 318 sta_reg &= port->read_status_mask; 319 320 if (sta_reg & PIC32_UART_STA_FERR) 321 flag = TTY_FRAME; 322 if (sta_reg & PIC32_UART_STA_PERR) 323 flag = TTY_PARITY; 324 } 325 326 if (uart_handle_sysrq_char(port, c)) 327 continue; 328 329 if ((sta_reg & port->ignore_status_mask) == 0) 330 tty_insert_flip_char(tty, c, flag); 331 332 } while (--max_count); 333 334 uart_port_unlock(port); 335 336 tty_flip_buffer_push(tty); 337 } 338 339 /* fill tx fifo with chars to send, stop when fifo is about to be full 340 * or when all chars have been sent. 341 */ pic32_uart_do_tx(struct uart_port * port)342 static void pic32_uart_do_tx(struct uart_port *port) 343 { 344 struct pic32_sport *sport = to_pic32_sport(port); 345 struct tty_port *tport = &port->state->port; 346 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; 347 348 if (port->x_char) { 349 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); 350 port->icount.tx++; 351 port->x_char = 0; 352 return; 353 } 354 355 if (uart_tx_stopped(port)) { 356 pic32_uart_stop_tx(port); 357 return; 358 } 359 360 if (kfifo_is_empty(&tport->xmit_fifo)) 361 goto txq_empty; 362 363 /* keep stuffing chars into uart tx buffer 364 * 1) until uart fifo is full 365 * or 366 * 2) until the circ buffer is empty 367 * (all chars have been sent) 368 * or 369 * 3) until the max count is reached 370 * (prevents lingering here for too long in certain cases) 371 */ 372 while (!(PIC32_UART_STA_UTXBF & 373 pic32_uart_readl(sport, PIC32_UART_STA))) { 374 unsigned char c; 375 376 if (!uart_fifo_get(port, &c)) 377 break; 378 pic32_uart_writel(sport, PIC32_UART_TX, c); 379 380 if (--max_count == 0) 381 break; 382 } 383 384 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 385 uart_write_wakeup(port); 386 387 if (kfifo_is_empty(&tport->xmit_fifo)) 388 goto txq_empty; 389 390 return; 391 392 txq_empty: 393 pic32_uart_irqtxen(sport, 0); 394 } 395 396 /* RX interrupt handler */ pic32_uart_rx_interrupt(int irq,void * dev_id)397 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) 398 { 399 struct uart_port *port = dev_id; 400 401 pic32_uart_do_rx(port); 402 403 return IRQ_HANDLED; 404 } 405 406 /* TX interrupt handler */ pic32_uart_tx_interrupt(int irq,void * dev_id)407 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) 408 { 409 struct uart_port *port = dev_id; 410 unsigned long flags; 411 412 uart_port_lock_irqsave(port, &flags); 413 pic32_uart_do_tx(port); 414 uart_port_unlock_irqrestore(port, flags); 415 416 return IRQ_HANDLED; 417 } 418 419 /* FAULT interrupt handler */ pic32_uart_fault_interrupt(int irq,void * dev_id)420 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) 421 { 422 /* do nothing: pic32_uart_do_rx() handles faults. */ 423 return IRQ_HANDLED; 424 } 425 426 /* enable rx & tx operation on uart */ pic32_uart_en_and_unmask(struct uart_port * port)427 static void pic32_uart_en_and_unmask(struct uart_port *port) 428 { 429 struct pic32_sport *sport = to_pic32_sport(port); 430 431 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 432 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 433 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 434 PIC32_UART_MODE_ON); 435 } 436 437 /* disable rx & tx operation on uart */ pic32_uart_dsbl_and_mask(struct uart_port * port)438 static void pic32_uart_dsbl_and_mask(struct uart_port *port) 439 { 440 struct pic32_sport *sport = to_pic32_sport(port); 441 442 /* wait for tx empty, otherwise chars will be lost or corrupted */ 443 pic32_wait_deplete_txbuf(sport); 444 445 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 446 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 447 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 448 PIC32_UART_MODE_ON); 449 } 450 451 /* serial core request to initialize uart and start rx operation */ pic32_uart_startup(struct uart_port * port)452 static int pic32_uart_startup(struct uart_port *port) 453 { 454 struct pic32_sport *sport = to_pic32_sport(port); 455 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; 456 unsigned long flags; 457 int ret; 458 459 local_irq_save(flags); 460 461 ret = clk_prepare_enable(sport->clk); 462 if (ret) { 463 local_irq_restore(flags); 464 goto out_done; 465 } 466 467 /* clear status and mode registers */ 468 pic32_uart_writel(sport, PIC32_UART_MODE, 0); 469 pic32_uart_writel(sport, PIC32_UART_STA, 0); 470 471 /* disable uart and mask all interrupts */ 472 pic32_uart_dsbl_and_mask(port); 473 474 /* set default baud */ 475 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); 476 477 local_irq_restore(flags); 478 479 /* Each UART of a PIC32 has three interrupts therefore, 480 * we setup driver to register the 3 irqs for the device. 481 * 482 * For each irq request_irq() is called with interrupt disabled. 483 * And the irq is enabled as soon as we are ready to handle them. 484 */ 485 sport->enable_tx_irq = false; 486 487 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", 488 pic32_uart_type(port), 489 sport->idx); 490 if (!sport->irq_fault_name) { 491 dev_err(port->dev, "%s: kasprintf err!", __func__); 492 ret = -ENOMEM; 493 goto out_disable_clk; 494 } 495 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); 496 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, 497 IRQF_NO_THREAD, sport->irq_fault_name, port); 498 if (ret) { 499 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 500 __func__, sport->irq_fault, ret, 501 pic32_uart_type(port)); 502 goto out_f; 503 } 504 505 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", 506 pic32_uart_type(port), 507 sport->idx); 508 if (!sport->irq_rx_name) { 509 dev_err(port->dev, "%s: kasprintf err!", __func__); 510 ret = -ENOMEM; 511 goto out_f; 512 } 513 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); 514 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, 515 IRQF_NO_THREAD, sport->irq_rx_name, port); 516 if (ret) { 517 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 518 __func__, sport->irq_rx, ret, 519 pic32_uart_type(port)); 520 goto out_r; 521 } 522 523 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", 524 pic32_uart_type(port), 525 sport->idx); 526 if (!sport->irq_tx_name) { 527 dev_err(port->dev, "%s: kasprintf err!", __func__); 528 ret = -ENOMEM; 529 goto out_r; 530 } 531 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); 532 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, 533 IRQF_NO_THREAD, sport->irq_tx_name, port); 534 if (ret) { 535 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 536 __func__, sport->irq_tx, ret, 537 pic32_uart_type(port)); 538 goto out_t; 539 } 540 541 local_irq_save(flags); 542 543 /* set rx interrupt on first receive */ 544 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 545 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); 546 547 /* set interrupt on empty */ 548 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 549 PIC32_UART_STA_UTXISEL1); 550 551 /* enable all interrupts and eanable uart */ 552 pic32_uart_en_and_unmask(port); 553 554 local_irq_restore(flags); 555 556 enable_irq(sport->irq_rx); 557 558 return 0; 559 560 out_t: 561 free_irq(sport->irq_tx, port); 562 kfree(sport->irq_tx_name); 563 out_r: 564 free_irq(sport->irq_rx, port); 565 kfree(sport->irq_rx_name); 566 out_f: 567 free_irq(sport->irq_fault, port); 568 kfree(sport->irq_fault_name); 569 out_disable_clk: 570 clk_disable_unprepare(sport->clk); 571 out_done: 572 return ret; 573 } 574 575 /* serial core request to flush & disable uart */ pic32_uart_shutdown(struct uart_port * port)576 static void pic32_uart_shutdown(struct uart_port *port) 577 { 578 struct pic32_sport *sport = to_pic32_sport(port); 579 unsigned long flags; 580 581 /* disable uart */ 582 uart_port_lock_irqsave(port, &flags); 583 pic32_uart_dsbl_and_mask(port); 584 uart_port_unlock_irqrestore(port, flags); 585 clk_disable_unprepare(sport->clk); 586 587 /* free all 3 interrupts for this UART */ 588 free_irq(sport->irq_fault, port); 589 kfree(sport->irq_fault_name); 590 free_irq(sport->irq_tx, port); 591 kfree(sport->irq_tx_name); 592 free_irq(sport->irq_rx, port); 593 kfree(sport->irq_rx_name); 594 } 595 596 /* serial core request to change current uart setting */ pic32_uart_set_termios(struct uart_port * port,struct ktermios * new,const struct ktermios * old)597 static void pic32_uart_set_termios(struct uart_port *port, 598 struct ktermios *new, 599 const struct ktermios *old) 600 { 601 struct pic32_sport *sport = to_pic32_sport(port); 602 unsigned int baud; 603 unsigned int quot; 604 unsigned long flags; 605 606 uart_port_lock_irqsave(port, &flags); 607 608 /* disable uart and mask all interrupts while changing speed */ 609 pic32_uart_dsbl_and_mask(port); 610 611 /* stop bit options */ 612 if (new->c_cflag & CSTOPB) 613 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 614 PIC32_UART_MODE_STSEL); 615 else 616 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 617 PIC32_UART_MODE_STSEL); 618 619 /* parity options */ 620 if (new->c_cflag & PARENB) { 621 if (new->c_cflag & PARODD) { 622 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 623 PIC32_UART_MODE_PDSEL1); 624 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 625 PIC32_UART_MODE_PDSEL0); 626 } else { 627 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 628 PIC32_UART_MODE_PDSEL0); 629 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 630 PIC32_UART_MODE_PDSEL1); 631 } 632 } else { 633 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 634 PIC32_UART_MODE_PDSEL1 | 635 PIC32_UART_MODE_PDSEL0); 636 } 637 /* if hw flow ctrl, then the pins must be specified in device tree */ 638 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) { 639 /* enable hardware flow control */ 640 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 641 PIC32_UART_MODE_UEN1); 642 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 643 PIC32_UART_MODE_UEN0); 644 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 645 PIC32_UART_MODE_RTSMD); 646 } else { 647 /* disable hardware flow control */ 648 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 649 PIC32_UART_MODE_UEN1); 650 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 651 PIC32_UART_MODE_UEN0); 652 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 653 PIC32_UART_MODE_RTSMD); 654 } 655 656 /* Always 8-bit */ 657 new->c_cflag |= CS8; 658 659 /* Mark/Space parity is not supported */ 660 new->c_cflag &= ~CMSPAR; 661 662 /* update baud */ 663 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 664 quot = uart_get_divisor(port, baud) - 1; 665 pic32_uart_writel(sport, PIC32_UART_BRG, quot); 666 uart_update_timeout(port, new->c_cflag, baud); 667 668 if (tty_termios_baud_rate(new)) 669 tty_termios_encode_baud_rate(new, baud, baud); 670 671 /* enable uart */ 672 pic32_uart_en_and_unmask(port); 673 674 uart_port_unlock_irqrestore(port, flags); 675 } 676 677 /* serial core request to claim uart iomem */ pic32_uart_request_port(struct uart_port * port)678 static int pic32_uart_request_port(struct uart_port *port) 679 { 680 struct platform_device *pdev = to_platform_device(port->dev); 681 struct resource *res_mem; 682 683 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 684 if (unlikely(!res_mem)) 685 return -EINVAL; 686 687 if (!request_mem_region(port->mapbase, resource_size(res_mem), 688 "pic32_uart_mem")) 689 return -EBUSY; 690 691 port->membase = devm_ioremap(port->dev, port->mapbase, 692 resource_size(res_mem)); 693 if (!port->membase) { 694 dev_err(port->dev, "Unable to map registers\n"); 695 release_mem_region(port->mapbase, resource_size(res_mem)); 696 return -ENOMEM; 697 } 698 699 return 0; 700 } 701 702 /* serial core request to release uart iomem */ pic32_uart_release_port(struct uart_port * port)703 static void pic32_uart_release_port(struct uart_port *port) 704 { 705 struct platform_device *pdev = to_platform_device(port->dev); 706 struct resource *res_mem; 707 unsigned int res_size; 708 709 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 if (unlikely(!res_mem)) 711 return; 712 res_size = resource_size(res_mem); 713 714 release_mem_region(port->mapbase, res_size); 715 } 716 717 /* serial core request to do any port required auto-configuration */ pic32_uart_config_port(struct uart_port * port,int flags)718 static void pic32_uart_config_port(struct uart_port *port, int flags) 719 { 720 if (flags & UART_CONFIG_TYPE) { 721 if (pic32_uart_request_port(port)) 722 return; 723 port->type = PORT_PIC32; 724 } 725 } 726 727 /* serial core request to check that port information in serinfo are suitable */ pic32_uart_verify_port(struct uart_port * port,struct serial_struct * serinfo)728 static int pic32_uart_verify_port(struct uart_port *port, 729 struct serial_struct *serinfo) 730 { 731 if (port->type != PORT_PIC32) 732 return -EINVAL; 733 if (port->irq != serinfo->irq) 734 return -EINVAL; 735 if (port->iotype != serinfo->io_type) 736 return -EINVAL; 737 if (port->mapbase != (unsigned long)serinfo->iomem_base) 738 return -EINVAL; 739 740 return 0; 741 } 742 743 /* serial core callbacks */ 744 static const struct uart_ops pic32_uart_ops = { 745 .tx_empty = pic32_uart_tx_empty, 746 .get_mctrl = pic32_uart_get_mctrl, 747 .set_mctrl = pic32_uart_set_mctrl, 748 .start_tx = pic32_uart_start_tx, 749 .stop_tx = pic32_uart_stop_tx, 750 .stop_rx = pic32_uart_stop_rx, 751 .break_ctl = pic32_uart_break_ctl, 752 .startup = pic32_uart_startup, 753 .shutdown = pic32_uart_shutdown, 754 .set_termios = pic32_uart_set_termios, 755 .type = pic32_uart_type, 756 .release_port = pic32_uart_release_port, 757 .request_port = pic32_uart_request_port, 758 .config_port = pic32_uart_config_port, 759 .verify_port = pic32_uart_verify_port, 760 }; 761 762 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 763 /* output given char */ pic32_console_putchar(struct uart_port * port,unsigned char ch)764 static void pic32_console_putchar(struct uart_port *port, unsigned char ch) 765 { 766 struct pic32_sport *sport = to_pic32_sport(port); 767 768 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 769 return; 770 771 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 772 return; 773 774 /* wait for tx empty */ 775 pic32_wait_deplete_txbuf(sport); 776 777 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); 778 } 779 780 /* console core request to output given string */ pic32_console_write(struct console * co,const char * s,unsigned int count)781 static void pic32_console_write(struct console *co, const char *s, 782 unsigned int count) 783 { 784 struct pic32_sport *sport = pic32_sports[co->index]; 785 786 /* call uart helper to deal with \r\n */ 787 uart_console_write(&sport->port, s, count, pic32_console_putchar); 788 } 789 790 /* console core request to setup given console, find matching uart 791 * port and setup it. 792 */ pic32_console_setup(struct console * co,char * options)793 static int pic32_console_setup(struct console *co, char *options) 794 { 795 struct pic32_sport *sport; 796 int baud = 115200; 797 int bits = 8; 798 int parity = 'n'; 799 int flow = 'n'; 800 int ret = 0; 801 802 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) 803 return -ENODEV; 804 805 sport = pic32_sports[co->index]; 806 if (!sport) 807 return -ENODEV; 808 809 ret = clk_prepare_enable(sport->clk); 810 if (ret) 811 return ret; 812 813 if (options) 814 uart_parse_options(options, &baud, &parity, &bits, &flow); 815 816 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 817 } 818 819 static struct uart_driver pic32_uart_driver; 820 static struct console pic32_console = { 821 .name = PIC32_SDEV_NAME, 822 .write = pic32_console_write, 823 .device = uart_console_device, 824 .setup = pic32_console_setup, 825 .flags = CON_PRINTBUFFER, 826 .index = -1, 827 .data = &pic32_uart_driver, 828 }; 829 #define PIC32_SCONSOLE (&pic32_console) 830 pic32_console_init(void)831 static int __init pic32_console_init(void) 832 { 833 register_console(&pic32_console); 834 return 0; 835 } 836 console_initcall(pic32_console_init); 837 838 /* 839 * Late console initialization. 840 */ pic32_late_console_init(void)841 static int __init pic32_late_console_init(void) 842 { 843 if (!console_is_registered(&pic32_console)) 844 register_console(&pic32_console); 845 846 return 0; 847 } 848 849 core_initcall(pic32_late_console_init); 850 851 #else 852 #define PIC32_SCONSOLE NULL 853 #endif 854 855 static struct uart_driver pic32_uart_driver = { 856 .owner = THIS_MODULE, 857 .driver_name = PIC32_DEV_NAME, 858 .dev_name = PIC32_SDEV_NAME, 859 .nr = PIC32_MAX_UARTS, 860 .cons = PIC32_SCONSOLE, 861 }; 862 pic32_uart_probe(struct platform_device * pdev)863 static int pic32_uart_probe(struct platform_device *pdev) 864 { 865 struct device *dev = &pdev->dev; 866 struct device_node *np = dev->of_node; 867 struct pic32_sport *sport; 868 int uart_idx = 0; 869 struct resource *res_mem; 870 struct uart_port *port; 871 int ret; 872 873 uart_idx = of_alias_get_id(np, "serial"); 874 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) 875 return -EINVAL; 876 877 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 878 if (!res_mem) 879 return -EINVAL; 880 881 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 882 if (!sport) 883 return -ENOMEM; 884 885 sport->idx = uart_idx; 886 sport->irq_fault = irq_of_parse_and_map(np, 0); 887 sport->irq_rx = irq_of_parse_and_map(np, 1); 888 sport->irq_tx = irq_of_parse_and_map(np, 2); 889 sport->clk = devm_clk_get(&pdev->dev, NULL); 890 if (IS_ERR(sport->clk)) 891 return PTR_ERR(sport->clk); 892 sport->dev = &pdev->dev; 893 894 /* Hardware flow control: gpios 895 * !Note: Basically, CTS is needed for reading the status. 896 */ 897 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN); 898 if (IS_ERR(sport->cts_gpiod)) 899 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n"); 900 gpiod_set_consumer_name(sport->cts_gpiod, "CTS"); 901 902 pic32_sports[uart_idx] = sport; 903 port = &sport->port; 904 port->iotype = UPIO_MEM; 905 port->mapbase = res_mem->start; 906 port->ops = &pic32_uart_ops; 907 port->flags = UPF_BOOT_AUTOCONF; 908 port->dev = &pdev->dev; 909 port->fifosize = PIC32_UART_TX_FIFO_DEPTH; 910 port->uartclk = clk_get_rate(sport->clk); 911 port->line = uart_idx; 912 913 ret = uart_add_one_port(&pic32_uart_driver, port); 914 if (ret) { 915 port->membase = NULL; 916 dev_err(port->dev, "%s: uart add port error!\n", __func__); 917 goto err; 918 } 919 920 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 921 if (uart_console_registered(port)) { 922 /* The peripheral clock has been enabled by console_setup, 923 * so disable it till the port is used. 924 */ 925 clk_disable_unprepare(sport->clk); 926 } 927 #endif 928 929 platform_set_drvdata(pdev, port); 930 931 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", 932 __func__, uart_idx); 933 934 return 0; 935 err: 936 /* automatic unroll of sport and gpios */ 937 return ret; 938 } 939 pic32_uart_remove(struct platform_device * pdev)940 static void pic32_uart_remove(struct platform_device *pdev) 941 { 942 struct uart_port *port = platform_get_drvdata(pdev); 943 struct pic32_sport *sport = to_pic32_sport(port); 944 945 uart_remove_one_port(&pic32_uart_driver, port); 946 clk_disable_unprepare(sport->clk); 947 platform_set_drvdata(pdev, NULL); 948 pic32_sports[sport->idx] = NULL; 949 } 950 951 static const struct of_device_id pic32_serial_dt_ids[] = { 952 { .compatible = "microchip,pic32mzda-uart" }, 953 { /* sentinel */ } 954 }; 955 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); 956 957 static struct platform_driver pic32_uart_platform_driver = { 958 .probe = pic32_uart_probe, 959 .remove_new = pic32_uart_remove, 960 .driver = { 961 .name = PIC32_DEV_NAME, 962 .of_match_table = of_match_ptr(pic32_serial_dt_ids), 963 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32), 964 }, 965 }; 966 pic32_uart_init(void)967 static int __init pic32_uart_init(void) 968 { 969 int ret; 970 971 ret = uart_register_driver(&pic32_uart_driver); 972 if (ret) { 973 pr_err("failed to register %s:%d\n", 974 pic32_uart_driver.driver_name, ret); 975 return ret; 976 } 977 978 ret = platform_driver_register(&pic32_uart_platform_driver); 979 if (ret) { 980 pr_err("fail to register pic32 uart\n"); 981 uart_unregister_driver(&pic32_uart_driver); 982 } 983 984 return ret; 985 } 986 arch_initcall(pic32_uart_init); 987 pic32_uart_exit(void)988 static void __exit pic32_uart_exit(void) 989 { 990 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 991 unregister_console(&pic32_console); 992 #endif 993 platform_driver_unregister(&pic32_uart_platform_driver); 994 uart_unregister_driver(&pic32_uart_driver); 995 } 996 module_exit(pic32_uart_exit); 997 998 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); 999 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); 1000 MODULE_LICENSE("GPL v2"); 1001