1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2024 NXP
4 */
5
6 #include <linux/init.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/platform_device.h>
11
12 #include "pinctrl-imx.h"
13
14 enum imx91_pads {
15 IMX91_PAD_DAP_TDI = 0,
16 IMX91_PAD_DAP_TMS_SWDIO = 1,
17 IMX91_PAD_DAP_TCLK_SWCLK = 2,
18 IMX91_PAD_DAP_TDO_TRACESWO = 3,
19 IMX91_PAD_GPIO_IO00 = 4,
20 IMX91_PAD_GPIO_IO01 = 5,
21 IMX91_PAD_GPIO_IO02 = 6,
22 IMX91_PAD_GPIO_IO03 = 7,
23 IMX91_PAD_GPIO_IO04 = 8,
24 IMX91_PAD_GPIO_IO05 = 9,
25 IMX91_PAD_GPIO_IO06 = 10,
26 IMX91_PAD_GPIO_IO07 = 11,
27 IMX91_PAD_GPIO_IO08 = 12,
28 IMX91_PAD_GPIO_IO09 = 13,
29 IMX91_PAD_GPIO_IO10 = 14,
30 IMX91_PAD_GPIO_IO11 = 15,
31 IMX91_PAD_GPIO_IO12 = 16,
32 IMX91_PAD_GPIO_IO13 = 17,
33 IMX91_PAD_GPIO_IO14 = 18,
34 IMX91_PAD_GPIO_IO15 = 19,
35 IMX91_PAD_GPIO_IO16 = 20,
36 IMX91_PAD_GPIO_IO17 = 21,
37 IMX91_PAD_GPIO_IO18 = 22,
38 IMX91_PAD_GPIO_IO19 = 23,
39 IMX91_PAD_GPIO_IO20 = 24,
40 IMX91_PAD_GPIO_IO21 = 25,
41 IMX91_PAD_GPIO_IO22 = 26,
42 IMX91_PAD_GPIO_IO23 = 27,
43 IMX91_PAD_GPIO_IO24 = 28,
44 IMX91_PAD_GPIO_IO25 = 29,
45 IMX91_PAD_GPIO_IO26 = 30,
46 IMX91_PAD_GPIO_IO27 = 31,
47 IMX91_PAD_GPIO_IO28 = 32,
48 IMX91_PAD_GPIO_IO29 = 33,
49 IMX91_PAD_CCM_CLKO1 = 34,
50 IMX91_PAD_CCM_CLKO2 = 35,
51 IMX91_PAD_CCM_CLKO3 = 36,
52 IMX91_PAD_CCM_CLKO4 = 37,
53 IMX91_PAD_ENET1_MDC = 38,
54 IMX91_PAD_ENET1_MDIO = 39,
55 IMX91_PAD_ENET1_TD3 = 40,
56 IMX91_PAD_ENET1_TD2 = 41,
57 IMX91_PAD_ENET1_TD1 = 42,
58 IMX91_PAD_ENET1_TD0 = 43,
59 IMX91_PAD_ENET1_TX_CTL = 44,
60 IMX91_PAD_ENET1_TXC = 45,
61 IMX91_PAD_ENET1_RX_CTL = 46,
62 IMX91_PAD_ENET1_RXC = 47,
63 IMX91_PAD_ENET1_RD0 = 48,
64 IMX91_PAD_ENET1_RD1 = 49,
65 IMX91_PAD_ENET1_RD2 = 50,
66 IMX91_PAD_ENET1_RD3 = 51,
67 IMX91_PAD_ENET2_MDC = 52,
68 IMX91_PAD_ENET2_MDIO = 53,
69 IMX91_PAD_ENET2_TD3 = 54,
70 IMX91_PAD_ENET2_TD2 = 55,
71 IMX91_PAD_ENET2_TD1 = 56,
72 IMX91_PAD_ENET2_TD0 = 57,
73 IMX91_PAD_ENET2_TX_CTL = 58,
74 IMX91_PAD_ENET2_TXC = 59,
75 IMX91_PAD_ENET2_RX_CTL = 60,
76 IMX91_PAD_ENET2_RXC = 61,
77 IMX91_PAD_ENET2_RD0 = 62,
78 IMX91_PAD_ENET2_RD1 = 63,
79 IMX91_PAD_ENET2_RD2 = 64,
80 IMX91_PAD_ENET2_RD3 = 65,
81 IMX91_PAD_SD1_CLK = 66,
82 IMX91_PAD_SD1_CMD = 67,
83 IMX91_PAD_SD1_DATA0 = 68,
84 IMX91_PAD_SD1_DATA1 = 69,
85 IMX91_PAD_SD1_DATA2 = 70,
86 IMX91_PAD_SD1_DATA3 = 71,
87 IMX91_PAD_SD1_DATA4 = 72,
88 IMX91_PAD_SD1_DATA5 = 73,
89 IMX91_PAD_SD1_DATA6 = 74,
90 IMX91_PAD_SD1_DATA7 = 75,
91 IMX91_PAD_SD1_STROBE = 76,
92 IMX91_PAD_SD2_VSELECT = 77,
93 IMX91_PAD_SD3_CLK = 78,
94 IMX91_PAD_SD3_CMD = 79,
95 IMX91_PAD_SD3_DATA0 = 80,
96 IMX91_PAD_SD3_DATA1 = 81,
97 IMX91_PAD_SD3_DATA2 = 82,
98 IMX91_PAD_SD3_DATA3 = 83,
99 IMX91_PAD_SD2_CD_B = 84,
100 IMX91_PAD_SD2_CLK = 85,
101 IMX91_PAD_SD2_CMD = 86,
102 IMX91_PAD_SD2_DATA0 = 87,
103 IMX91_PAD_SD2_DATA1 = 88,
104 IMX91_PAD_SD2_DATA2 = 89,
105 IMX91_PAD_SD2_DATA3 = 90,
106 IMX91_PAD_SD2_RESET_B = 91,
107 IMX91_PAD_I2C1_SCL = 92,
108 IMX91_PAD_I2C1_SDA = 93,
109 IMX91_PAD_I2C2_SCL = 94,
110 IMX91_PAD_I2C2_SDA = 95,
111 IMX91_PAD_UART1_RXD = 96,
112 IMX91_PAD_UART1_TXD = 97,
113 IMX91_PAD_UART2_RXD = 98,
114 IMX91_PAD_UART2_TXD = 99,
115 IMX91_PAD_PDM_CLK = 100,
116 IMX91_PAD_PDM_BIT_STREAM0 = 101,
117 IMX91_PAD_PDM_BIT_STREAM1 = 102,
118 IMX91_PAD_SAI1_TXFS = 103,
119 IMX91_PAD_SAI1_TXC = 104,
120 IMX91_PAD_SAI1_TXD0 = 105,
121 IMX91_PAD_SAI1_RXD0 = 106,
122 IMX91_PAD_WDOG_ANY = 107,
123 };
124
125 /* Pad names for the pinmux subsystem */
126 static const struct pinctrl_pin_desc imx91_pinctrl_pads[] = {
127 IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDI),
128 IMX_PINCTRL_PIN(IMX91_PAD_DAP_TMS_SWDIO),
129 IMX_PINCTRL_PIN(IMX91_PAD_DAP_TCLK_SWCLK),
130 IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDO_TRACESWO),
131 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO00),
132 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO01),
133 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO02),
134 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO03),
135 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO04),
136 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO05),
137 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO06),
138 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO07),
139 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO08),
140 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO09),
141 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO10),
142 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO11),
143 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO12),
144 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO13),
145 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO14),
146 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO15),
147 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO16),
148 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO17),
149 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO18),
150 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO19),
151 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO20),
152 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO21),
153 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO22),
154 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO23),
155 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO24),
156 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO25),
157 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO26),
158 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO27),
159 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO28),
160 IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO29),
161 IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO1),
162 IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO2),
163 IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO3),
164 IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO4),
165 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDC),
166 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDIO),
167 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD3),
168 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD2),
169 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD1),
170 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD0),
171 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TX_CTL),
172 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TXC),
173 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RX_CTL),
174 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RXC),
175 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD0),
176 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD1),
177 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD2),
178 IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD3),
179 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDC),
180 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDIO),
181 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD3),
182 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD2),
183 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD1),
184 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD0),
185 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TX_CTL),
186 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TXC),
187 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RX_CTL),
188 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RXC),
189 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD0),
190 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD1),
191 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD2),
192 IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD3),
193 IMX_PINCTRL_PIN(IMX91_PAD_SD1_CLK),
194 IMX_PINCTRL_PIN(IMX91_PAD_SD1_CMD),
195 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA0),
196 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA1),
197 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA2),
198 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA3),
199 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA4),
200 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA5),
201 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA6),
202 IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA7),
203 IMX_PINCTRL_PIN(IMX91_PAD_SD1_STROBE),
204 IMX_PINCTRL_PIN(IMX91_PAD_SD2_VSELECT),
205 IMX_PINCTRL_PIN(IMX91_PAD_SD3_CLK),
206 IMX_PINCTRL_PIN(IMX91_PAD_SD3_CMD),
207 IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA0),
208 IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA1),
209 IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA2),
210 IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA3),
211 IMX_PINCTRL_PIN(IMX91_PAD_SD2_CD_B),
212 IMX_PINCTRL_PIN(IMX91_PAD_SD2_CLK),
213 IMX_PINCTRL_PIN(IMX91_PAD_SD2_CMD),
214 IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA0),
215 IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA1),
216 IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA2),
217 IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA3),
218 IMX_PINCTRL_PIN(IMX91_PAD_SD2_RESET_B),
219 IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SCL),
220 IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SDA),
221 IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SCL),
222 IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SDA),
223 IMX_PINCTRL_PIN(IMX91_PAD_UART1_RXD),
224 IMX_PINCTRL_PIN(IMX91_PAD_UART1_TXD),
225 IMX_PINCTRL_PIN(IMX91_PAD_UART2_RXD),
226 IMX_PINCTRL_PIN(IMX91_PAD_UART2_TXD),
227 IMX_PINCTRL_PIN(IMX91_PAD_PDM_CLK),
228 IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM0),
229 IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM1),
230 IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXFS),
231 IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXC),
232 IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXD0),
233 IMX_PINCTRL_PIN(IMX91_PAD_SAI1_RXD0),
234 IMX_PINCTRL_PIN(IMX91_PAD_WDOG_ANY),
235 };
236
237 static const struct imx_pinctrl_soc_info imx91_pinctrl_info = {
238 .pins = imx91_pinctrl_pads,
239 .npins = ARRAY_SIZE(imx91_pinctrl_pads),
240 .flags = ZERO_OFFSET_VALID,
241 };
242
imx91_pinctrl_probe(struct platform_device * pdev)243 static int imx91_pinctrl_probe(struct platform_device *pdev)
244 {
245 return imx_pinctrl_probe(pdev, &imx91_pinctrl_info);
246 }
247
248 static const struct of_device_id imx91_pinctrl_of_match[] = {
249 { .compatible = "fsl,imx91-iomuxc", },
250 { /* sentinel */ }
251 };
252 MODULE_DEVICE_TABLE(of, imx91_pinctrl_of_match);
253
254 static struct platform_driver imx91_pinctrl_driver = {
255 .driver = {
256 .name = "imx91-pinctrl",
257 .of_match_table = imx91_pinctrl_of_match,
258 .suppress_bind_attrs = true,
259 },
260 .probe = imx91_pinctrl_probe,
261 };
262
imx91_pinctrl_init(void)263 static int __init imx91_pinctrl_init(void)
264 {
265 return platform_driver_register(&imx91_pinctrl_driver);
266 }
267 arch_initcall(imx91_pinctrl_init);
268
269 MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
270 MODULE_DESCRIPTION("NXP i.MX91 pinctrl driver");
271 MODULE_LICENSE("GPL");
272