1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "debug.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_rfk_table.h"
13 #include "rtw8852a_table.h"
14
_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)15 static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
16 {
17 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n",
18 rtwdev->dbcc_en, phy_idx);
19
20 if (!rtwdev->dbcc_en)
21 return RF_AB;
22
23 if (phy_idx == RTW89_PHY_0)
24 return RF_A;
25 else
26 return RF_B;
27 }
28
29 static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
30 static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
31 #define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852a_backup_bb_regs)
32 #define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852a_backup_rf_regs)
33
_rfk_backup_bb_reg(struct rtw89_dev * rtwdev,u32 backup_bb_reg_val[])34 static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
35 {
36 u32 i;
37
38 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
39 backup_bb_reg_val[i] =
40 rtw89_phy_read32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
41 MASKDWORD);
42 rtw89_debug(rtwdev, RTW89_DBG_RFK,
43 "[IQK]backup bb reg : %x, value =%x\n",
44 rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
45 }
46 }
47
_rfk_backup_rf_reg(struct rtw89_dev * rtwdev,u32 backup_rf_reg_val[],u8 rf_path)48 static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
49 u8 rf_path)
50 {
51 u32 i;
52
53 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
54 backup_rf_reg_val[i] =
55 rtw89_read_rf(rtwdev, rf_path,
56 rtw8852a_backup_rf_regs[i], RFREG_MASK);
57 rtw89_debug(rtwdev, RTW89_DBG_RFK,
58 "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path,
59 rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
60 }
61 }
62
_rfk_restore_bb_reg(struct rtw89_dev * rtwdev,u32 backup_bb_reg_val[])63 static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
64 u32 backup_bb_reg_val[])
65 {
66 u32 i;
67
68 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
69 rtw89_phy_write32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
70 MASKDWORD, backup_bb_reg_val[i]);
71 rtw89_debug(rtwdev, RTW89_DBG_RFK,
72 "[IQK]restore bb reg : %x, value =%x\n",
73 rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
74 }
75 }
76
_rfk_restore_rf_reg(struct rtw89_dev * rtwdev,u32 backup_rf_reg_val[],u8 rf_path)77 static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
78 u32 backup_rf_reg_val[], u8 rf_path)
79 {
80 u32 i;
81
82 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
83 rtw89_write_rf(rtwdev, rf_path, rtw8852a_backup_rf_regs[i],
84 RFREG_MASK, backup_rf_reg_val[i]);
85
86 rtw89_debug(rtwdev, RTW89_DBG_RFK,
87 "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path,
88 rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
89 }
90 }
91
_wait_rx_mode(struct rtw89_dev * rtwdev,u8 kpath)92 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
93 {
94 u8 path;
95 u32 rf_mode;
96 int ret;
97
98 for (path = 0; path < RF_PATH_MAX; path++) {
99 if (!(kpath & BIT(path)))
100 continue;
101
102 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
103 2, 5000, false, rtwdev, path, 0x00,
104 RR_MOD_MASK);
105 rtw89_debug(rtwdev, RTW89_DBG_RFK,
106 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
107 path, ret);
108 }
109 }
110
_dack_dump(struct rtw89_dev * rtwdev)111 static void _dack_dump(struct rtw89_dev *rtwdev)
112 {
113 struct rtw89_dack_info *dack = &rtwdev->dack;
114 u8 i;
115 u8 t;
116
117 rtw89_debug(rtwdev, RTW89_DBG_RFK,
118 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
119 dack->addck_d[0][0], dack->addck_d[0][1]);
120 rtw89_debug(rtwdev, RTW89_DBG_RFK,
121 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
122 dack->addck_d[1][0], dack->addck_d[1][1]);
123 rtw89_debug(rtwdev, RTW89_DBG_RFK,
124 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
125 dack->dadck_d[0][0], dack->dadck_d[0][1]);
126 rtw89_debug(rtwdev, RTW89_DBG_RFK,
127 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
128 dack->dadck_d[1][0], dack->dadck_d[1][1]);
129
130 rtw89_debug(rtwdev, RTW89_DBG_RFK,
131 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
132 dack->biask_d[0][0], dack->biask_d[0][1]);
133 rtw89_debug(rtwdev, RTW89_DBG_RFK,
134 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
135 dack->biask_d[1][0], dack->biask_d[1][1]);
136
137 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
138 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
139 t = dack->msbk_d[0][0][i];
140 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
141 }
142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
143 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
144 t = dack->msbk_d[0][1][i];
145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
146 }
147 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
148 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
149 t = dack->msbk_d[1][0][i];
150 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
151 }
152 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
153 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
154 t = dack->msbk_d[1][1][i];
155 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
156 }
157 }
158
_afe_init(struct rtw89_dev * rtwdev)159 static void _afe_init(struct rtw89_dev *rtwdev)
160 {
161 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_afe_init_defs_tbl);
162 }
163
_addck_backup(struct rtw89_dev * rtwdev)164 static void _addck_backup(struct rtw89_dev *rtwdev)
165 {
166 struct rtw89_dack_info *dack = &rtwdev->dack;
167
168 rtw89_phy_write32_clr(rtwdev, R_S0_RXDC2, B_S0_RXDC2_SEL);
169 dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
170 B_S0_ADDCK_Q);
171 dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
172 B_S0_ADDCK_I);
173
174 rtw89_phy_write32_clr(rtwdev, R_S1_RXDC2, B_S1_RXDC2_SEL);
175 dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
176 B_S1_ADDCK_Q);
177 dack->addck_d[1][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
178 B_S1_ADDCK_I);
179 }
180
_addck_reload(struct rtw89_dev * rtwdev)181 static void _addck_reload(struct rtw89_dev *rtwdev)
182 {
183 struct rtw89_dack_info *dack = &rtwdev->dack;
184
185 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]);
186 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2, B_S0_RXDC2_Q2,
187 (dack->addck_d[0][1] >> 6));
188 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_Q,
189 (dack->addck_d[0][1] & 0x3f));
190 rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN);
191 rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]);
192 rtw89_phy_write32_mask(rtwdev, R_S1_RXDC2, B_S1_RXDC2_Q2,
193 (dack->addck_d[1][1] >> 6));
194 rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_Q,
195 (dack->addck_d[1][1] & 0x3f));
196 rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN);
197 }
198
_dack_backup_s0(struct rtw89_dev * rtwdev)199 static void _dack_backup_s0(struct rtw89_dev *rtwdev)
200 {
201 struct rtw89_dack_info *dack = &rtwdev->dack;
202 u8 i;
203
204 rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN);
205 rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN);
206 rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
207
208 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
209 rtw89_phy_write32_mask(rtwdev, R_S0_DACKI, B_S0_DACKI_AR, i);
210 dack->msbk_d[0][0][i] =
211 (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI7, B_S0_DACKI7_K);
212 rtw89_phy_write32_mask(rtwdev, R_S0_DACKQ, B_S0_DACKQ_AR, i);
213 dack->msbk_d[0][1][i] =
214 (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ7, B_S0_DACKQ7_K);
215 }
216 dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2,
217 B_S0_DACKI2_K);
218 dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2,
219 B_S0_DACKQ2_K);
220 dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8,
221 B_S0_DACKI8_K) - 8;
222 dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8,
223 B_S0_DACKQ8_K) - 8;
224 }
225
_dack_backup_s1(struct rtw89_dev * rtwdev)226 static void _dack_backup_s1(struct rtw89_dev *rtwdev)
227 {
228 struct rtw89_dack_info *dack = &rtwdev->dack;
229 u8 i;
230
231 rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN);
232 rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN);
233 rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
234
235 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
236 rtw89_phy_write32_mask(rtwdev, R_S1_DACKI, B_S1_DACKI_AR, i);
237 dack->msbk_d[1][0][i] =
238 (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI7, B_S1_DACKI_K);
239 rtw89_phy_write32_mask(rtwdev, R_S1_DACKQ, B_S1_DACKQ_AR, i);
240 dack->msbk_d[1][1][i] =
241 (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ7, B_S1_DACKQ7_K);
242 }
243 dack->biask_d[1][0] =
244 (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI2, B_S1_DACKI2_K);
245 dack->biask_d[1][1] =
246 (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ2, B_S1_DACKQ2_K);
247 dack->dadck_d[1][0] =
248 (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI8, B_S1_DACKI8_K) - 8;
249 dack->dadck_d[1][1] =
250 (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ8, B_S1_DACKQ8_K) - 8;
251 }
252
_dack_reload_by_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 index)253 static void _dack_reload_by_path(struct rtw89_dev *rtwdev,
254 enum rtw89_rf_path path, u8 index)
255 {
256 struct rtw89_dack_info *dack = &rtwdev->dack;
257 u32 tmp = 0, tmp_offset, tmp_reg;
258 u8 i;
259 u32 idx_offset, path_offset;
260
261 if (index == 0)
262 idx_offset = 0;
263 else
264 idx_offset = 0x50;
265
266 if (path == RF_PATH_A)
267 path_offset = 0;
268 else
269 path_offset = 0x2000;
270
271 tmp_offset = idx_offset + path_offset;
272 /* msbk_d: 15/14/13/12 */
273 tmp = 0x0;
274 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
275 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
276 tmp_reg = 0x5e14 + tmp_offset;
277 rtw89_phy_write32(rtwdev, tmp_reg, tmp);
278 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
279 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
280 /* msbk_d: 11/10/9/8 */
281 tmp = 0x0;
282 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
283 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
284 tmp_reg = 0x5e18 + tmp_offset;
285 rtw89_phy_write32(rtwdev, tmp_reg, tmp);
286 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
287 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
288 /* msbk_d: 7/6/5/4 */
289 tmp = 0x0;
290 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
291 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
292 tmp_reg = 0x5e1c + tmp_offset;
293 rtw89_phy_write32(rtwdev, tmp_reg, tmp);
294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
295 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
296 /* msbk_d: 3/2/1/0 */
297 tmp = 0x0;
298 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
299 tmp |= dack->msbk_d[path][index][i] << (i * 8);
300 tmp_reg = 0x5e20 + tmp_offset;
301 rtw89_phy_write32(rtwdev, tmp_reg, tmp);
302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
303 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
304 /* dadak_d/biask_d */
305 tmp = 0x0;
306 tmp = (dack->biask_d[path][index] << 22) |
307 (dack->dadck_d[path][index] << 14);
308 tmp_reg = 0x5e24 + tmp_offset;
309 rtw89_phy_write32(rtwdev, tmp_reg, tmp);
310 }
311
_dack_reload(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)312 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
313 {
314 u8 i;
315
316 for (i = 0; i < 2; i++)
317 _dack_reload_by_path(rtwdev, path, i);
318
319 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
320 &rtw8852a_rfk_dack_reload_defs_a_tbl,
321 &rtw8852a_rfk_dack_reload_defs_b_tbl);
322 }
323
324 #define ADDC_T_AVG 100
_check_addc(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)325 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
326 {
327 s32 dc_re = 0, dc_im = 0;
328 u32 tmp;
329 u32 i;
330
331 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
332 &rtw8852a_rfk_check_addc_defs_a_tbl,
333 &rtw8852a_rfk_check_addc_defs_b_tbl);
334
335 for (i = 0; i < ADDC_T_AVG; i++) {
336 tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
337 dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
338 dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
339 }
340
341 dc_re /= ADDC_T_AVG;
342 dc_im /= ADDC_T_AVG;
343
344 rtw89_debug(rtwdev, RTW89_DBG_RFK,
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
346 }
347
_addck(struct rtw89_dev * rtwdev)348 static void _addck(struct rtw89_dev *rtwdev)
349 {
350 struct rtw89_dack_info *dack = &rtwdev->dack;
351 u32 val;
352 int ret;
353
354 /* S0 */
355 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_a_tbl);
356
357 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
358 _check_addc(rtwdev, RF_PATH_A);
359
360 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_a_tbl);
361
362 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
363 false, rtwdev, 0x1e00, BIT(0));
364 if (ret) {
365 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
366 dack->addck_timeout[0] = true;
367 }
368 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
369 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
370 _check_addc(rtwdev, RF_PATH_A);
371
372 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_a_tbl);
373
374 /* S1 */
375 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_b_tbl);
376
377 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
378 _check_addc(rtwdev, RF_PATH_B);
379
380 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_b_tbl);
381
382 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
383 false, rtwdev, 0x3e00, BIT(0));
384 if (ret) {
385 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
386 dack->addck_timeout[1] = true;
387 }
388 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
389 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
390 _check_addc(rtwdev, RF_PATH_B);
391
392 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_b_tbl);
393 }
394
_check_dadc(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)395 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
396 {
397 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
398 &rtw8852a_rfk_check_dadc_defs_f_a_tbl,
399 &rtw8852a_rfk_check_dadc_defs_f_b_tbl);
400
401 _check_addc(rtwdev, path);
402
403 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
404 &rtw8852a_rfk_check_dadc_defs_r_a_tbl,
405 &rtw8852a_rfk_check_dadc_defs_r_b_tbl);
406 }
407
_dack_s0(struct rtw89_dev * rtwdev)408 static void _dack_s0(struct rtw89_dev *rtwdev)
409 {
410 struct rtw89_dack_info *dack = &rtwdev->dack;
411 u32 val;
412 int ret;
413
414 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_a_tbl);
415
416 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
417 false, rtwdev, 0x5e28, BIT(15));
418 ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
419 false, rtwdev, 0x5e78, BIT(15));
420 if (ret) {
421 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
422 dack->msbk_timeout[0] = true;
423 }
424 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
425
426 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_a_tbl);
427
428 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
429 false, rtwdev, 0x5e48, BIT(17));
430 ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
431 false, rtwdev, 0x5e98, BIT(17));
432 if (ret) {
433 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADACK timeout\n");
434 dack->dadck_timeout[0] = true;
435 }
436 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
437
438 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_a_tbl);
439
440 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
441 _check_dadc(rtwdev, RF_PATH_A);
442
443 _dack_backup_s0(rtwdev);
444 _dack_reload(rtwdev, RF_PATH_A);
445
446 rtw89_phy_write32_clr(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
447 }
448
_dack_s1(struct rtw89_dev * rtwdev)449 static void _dack_s1(struct rtw89_dev *rtwdev)
450 {
451 struct rtw89_dack_info *dack = &rtwdev->dack;
452 u32 val;
453 int ret;
454
455 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_b_tbl);
456
457 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
458 false, rtwdev, 0x7e28, BIT(15));
459 ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
460 false, rtwdev, 0x7e78, BIT(15));
461 if (ret) {
462 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
463 dack->msbk_timeout[1] = true;
464 }
465 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
466
467 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_b_tbl);
468
469 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
470 false, rtwdev, 0x7e48, BIT(17));
471 ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
472 false, rtwdev, 0x7e98, BIT(17));
473 if (ret) {
474 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
475 dack->dadck_timeout[1] = true;
476 }
477 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
478
479 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_b_tbl);
480
481 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
482 _check_dadc(rtwdev, RF_PATH_B);
483
484 _dack_backup_s1(rtwdev);
485 _dack_reload(rtwdev, RF_PATH_B);
486
487 rtw89_phy_write32_clr(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
488 }
489
_dack(struct rtw89_dev * rtwdev)490 static void _dack(struct rtw89_dev *rtwdev)
491 {
492 _dack_s0(rtwdev);
493 _dack_s1(rtwdev);
494 }
495
_dac_cal(struct rtw89_dev * rtwdev,bool force,enum rtw89_chanctx_idx chanctx_idx)496 static void _dac_cal(struct rtw89_dev *rtwdev, bool force,
497 enum rtw89_chanctx_idx chanctx_idx)
498 {
499 struct rtw89_dack_info *dack = &rtwdev->dack;
500 u32 rf0_0, rf1_0;
501 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB, chanctx_idx);
502
503 dack->dack_done = false;
504 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n");
505 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
506 rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
507 rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
508 _afe_init(rtwdev);
509 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
510 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
511 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001);
512 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001);
513 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
514 _addck(rtwdev);
515 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
516 _addck_backup(rtwdev);
517 _addck_reload(rtwdev);
518 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
519 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001);
520 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
521 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
522 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
523 _dack(rtwdev);
524 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
525 _dack_dump(rtwdev);
526 dack->dack_done = true;
527 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
528 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
529 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
530 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
531 dack->dack_cnt++;
532 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
533 }
534
535 #define RTW8852A_NCTL_VER 0xd
536 #define RTW8852A_IQK_VER 0x2a
537 #define RTW8852A_IQK_SS 2
538 #define RTW8852A_IQK_THR_REK 8
539 #define RTW8852A_IQK_CFIR_GROUP_NR 4
540
541 enum rtw8852a_iqk_type {
542 ID_TXAGC,
543 ID_FLOK_COARSE,
544 ID_FLOK_FINE,
545 ID_TXK,
546 ID_RXAGC,
547 ID_RXK,
548 ID_NBTXK,
549 ID_NBRXK,
550 };
551
_iqk_read_fft_dbcc0(struct rtw89_dev * rtwdev,u8 path)552 static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path)
553 {
554 u8 i = 0x0;
555 u32 fft[6] = {0x0};
556
557 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
558 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000);
559 fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
560 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000);
561 fft[1] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
562 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000);
563 fft[2] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
564 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000);
565 fft[3] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
566 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000);
567 fft[4] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
568 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000);
569 fft[5] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
570 for (i = 0; i < 6; i++)
571 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x,fft[%x]= %x\n",
572 path, i, fft[i]);
573 }
574
_iqk_read_xym_dbcc0(struct rtw89_dev * rtwdev,u8 path)575 static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path)
576 {
577 u8 i = 0x0;
578 u32 tmp = 0x0;
579
580 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
581 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path);
582 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1);
583
584 for (i = 0x0; i < 0x18; i++) {
585 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i);
586 rtw89_phy_write32_clr(rtwdev, R_NCTL_N2, MASKDWORD);
587 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
588 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n",
589 path, BIT(path), tmp);
590 udelay(1);
591 }
592 rtw89_phy_write32_clr(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX);
593 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
594 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100);
595 udelay(1);
596 }
597
_iqk_read_txcfir_dbcc0(struct rtw89_dev * rtwdev,u8 path,u8 group)598 static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
599 u8 group)
600 {
601 static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
602 {0x8f20, 0x8f54, 0x8f88, 0x8fbc},
603 {0x9320, 0x9354, 0x9388, 0x93bc},
604 };
605 u8 idx = 0x0;
606 u32 tmp = 0x0;
607 u32 base_addr;
608
609 if (path >= RTW8852A_IQK_SS) {
610 rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
611 return;
612 }
613 if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
614 rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
615 return;
616 }
617
618 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
619 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
620
621 base_addr = base_addrs[path][group];
622
623 for (idx = 0; idx < 0x0d; idx++) {
624 tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
625 rtw89_debug(rtwdev, RTW89_DBG_RFK,
626 "[IQK] %x = %x\n",
627 base_addr + (idx << 2), tmp);
628 }
629
630 if (path == 0x0) {
631 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
632 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C0, MASKDWORD);
633 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp);
634 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C1, MASKDWORD);
635 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp);
636 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C2, MASKDWORD);
637 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp);
638 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C3, MASKDWORD);
639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp);
640 } else {
641 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
642 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C0, MASKDWORD);
643 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp);
644 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C1, MASKDWORD);
645 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp);
646 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C2, MASKDWORD);
647 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp);
648 tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C3, MASKDWORD);
649 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp);
650 }
651 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
652 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc);
653 udelay(1);
654 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
655 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
656 BIT(path), tmp);
657 }
658
_iqk_read_rxcfir_dbcc0(struct rtw89_dev * rtwdev,u8 path,u8 group)659 static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
660 u8 group)
661 {
662 static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
663 {0x8d00, 0x8d44, 0x8d88, 0x8dcc},
664 {0x9100, 0x9144, 0x9188, 0x91cc},
665 };
666 u8 idx = 0x0;
667 u32 tmp = 0x0;
668 u32 base_addr;
669
670 if (path >= RTW8852A_IQK_SS) {
671 rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
672 return;
673 }
674 if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
675 rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
676 return;
677 }
678
679 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
680 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
681
682 base_addr = base_addrs[path][group];
683 for (idx = 0; idx < 0x10; idx++) {
684 tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
685 rtw89_debug(rtwdev, RTW89_DBG_RFK,
686 "[IQK]%x = %x\n",
687 base_addr + (idx << 2), tmp);
688 }
689
690 if (path == 0x0) {
691 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
692 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C0, MASKDWORD);
693 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp);
694 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C1, MASKDWORD);
695 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp);
696 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C2, MASKDWORD);
697 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp);
698 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C3, MASKDWORD);
699 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp);
700 } else {
701 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
702 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C0, MASKDWORD);
703 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp);
704 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C1, MASKDWORD);
705 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp);
706 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C2, MASKDWORD);
707 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp);
708 tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C3, MASKDWORD);
709 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp);
710 }
711 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
712 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd);
713 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
714 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
715 BIT(path), tmp);
716 }
717
_iqk_sram(struct rtw89_dev * rtwdev,u8 path)718 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
719 {
720 u32 tmp = 0x0;
721 u32 i = 0x0;
722
723 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
724 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
725 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
726 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
727 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
728
729 for (i = 0; i <= 0x9f; i++) {
730 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
731 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
732 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
733 }
734
735 for (i = 0; i <= 0x9f; i++) {
736 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
737 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
739 }
740 rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX2, MASKDWORD);
741 rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX, MASKDWORD);
742 }
743
_iqk_rxk_setting(struct rtw89_dev * rtwdev,u8 path)744 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
745 {
746 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
747 u32 tmp = 0x0;
748
749 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
750 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3);
751 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
752 udelay(1);
753 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3);
754 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
755 udelay(1);
756 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
757 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0);
758 udelay(1);
759 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
760 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
761
762 switch (iqk_info->iqk_band[path]) {
763 case RTW89_BAND_2G:
764 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
765 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
766 break;
767 case RTW89_BAND_5G:
768 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
769 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5);
770 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
771 break;
772 default:
773 break;
774 }
775 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
776 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
779 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
780 fsleep(128);
781 }
782
_iqk_check_cal(struct rtw89_dev * rtwdev,u8 path,u8 ktype)783 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
784 {
785 u32 tmp;
786 u32 val;
787 int ret;
788
789 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200,
790 false, rtwdev, 0xbff8, MASKBYTE0);
791 if (ret)
792 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n");
793 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
795 tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
796 rtw89_debug(rtwdev, RTW89_DBG_RFK,
797 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
798
799 return false;
800 }
801
_iqk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,u8 ktype,enum rtw89_chanctx_idx chanctx_idx)802 static bool _iqk_one_shot(struct rtw89_dev *rtwdev,
803 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype,
804 enum rtw89_chanctx_idx chanctx_idx)
805 {
806 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
807 bool fail = false;
808 u32 iqk_cmd = 0x0;
809 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path, chanctx_idx);
810 u32 addr_rfc_ctl = 0x0;
811
812 if (path == RF_PATH_A)
813 addr_rfc_ctl = 0x5864;
814 else
815 addr_rfc_ctl = 0x7864;
816
817 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
818 switch (ktype) {
819 case ID_TXAGC:
820 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
821 break;
822 case ID_FLOK_COARSE:
823 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
824 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
825 iqk_cmd = 0x108 | (1 << (4 + path));
826 break;
827 case ID_FLOK_FINE:
828 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
829 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
830 iqk_cmd = 0x208 | (1 << (4 + path));
831 break;
832 case ID_TXK:
833 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
834 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
835 iqk_cmd = 0x008 | (1 << (path + 4)) |
836 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
837 break;
838 case ID_RXAGC:
839 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
840 break;
841 case ID_RXK:
842 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
843 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
844 iqk_cmd = 0x008 | (1 << (path + 4)) |
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
846 break;
847 case ID_NBTXK:
848 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
849 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
850 iqk_cmd = 0x308 | (1 << (4 + path));
851 break;
852 case ID_NBRXK:
853 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
854 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
855 iqk_cmd = 0x608 | (1 << (4 + path));
856 break;
857 default:
858 return false;
859 }
860
861 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
862 rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
863 udelay(1);
864 fail = _iqk_check_cal(rtwdev, path, ktype);
865 if (iqk_info->iqk_xym_en)
866 _iqk_read_xym_dbcc0(rtwdev, path);
867 if (iqk_info->iqk_fft_en)
868 _iqk_read_fft_dbcc0(rtwdev, path);
869 if (iqk_info->iqk_sram_en)
870 _iqk_sram(rtwdev, path);
871 if (iqk_info->iqk_cfir_en) {
872 if (ktype == ID_TXK) {
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0);
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1);
875 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2);
876 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3);
877 } else {
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0);
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1);
880 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2);
881 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3);
882 }
883 }
884
885 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
886
887 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
888
889 return fail;
890 }
891
_rxk_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)892 static bool _rxk_group_sel(struct rtw89_dev *rtwdev,
893 enum rtw89_phy_idx phy_idx, u8 path,
894 enum rtw89_chanctx_idx chanctx_idx)
895 {
896 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
897 static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0};
898 static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30};
899 static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1};
900 static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0};
901 static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a};
902 static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0};
903 u8 gp = 0x0;
904 bool fail = false;
905 u32 rf0 = 0x0;
906
907 for (gp = 0; gp < 0x4; gp++) {
908 switch (iqk_info->iqk_band[path]) {
909 case RTW89_BAND_2G:
910 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]);
911 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]);
912 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]);
913 break;
914 case RTW89_BAND_5G:
915 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]);
916 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]);
917 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]);
918 break;
919 default:
920 break;
921 }
922 rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
923 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
924 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI,
925 rf0 | iqk_info->syn1to2);
926 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
927 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
928 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
929 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
930 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
931 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1);
932 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
933 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK, chanctx_idx);
934 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
935 }
936
937 switch (iqk_info->iqk_band[path]) {
938 case RTW89_BAND_2G:
939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
940 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
941 break;
942 case RTW89_BAND_5G:
943 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
944 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
945 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
946 break;
947 default:
948 break;
949 }
950 iqk_info->nb_rxcfir[path] = 0x40000000;
951 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
952 B_IQK_RES_RXCFIR, 0x5);
953 iqk_info->is_wb_rxiqk[path] = true;
954 return false;
955 }
956
_iqk_nbrxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)957 static bool _iqk_nbrxk(struct rtw89_dev *rtwdev,
958 enum rtw89_phy_idx phy_idx, u8 path,
959 enum rtw89_chanctx_idx chanctx_idx)
960 {
961 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
962 u8 group = 0x0;
963 u32 rf0 = 0x0, tmp = 0x0;
964 u32 idxrxgain_a = 0x1a0;
965 u32 idxattc2_a = 0x00;
966 u32 idxattc1_a = 0x5;
967 u32 idxrxgain_g = 0x1E0;
968 u32 idxattc2_g = 0x15;
969 u32 idxattc1_g = 0x0;
970 bool fail = false;
971
972 switch (iqk_info->iqk_band[path]) {
973 case RTW89_BAND_2G:
974 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g);
975 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g);
976 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g);
977 break;
978 case RTW89_BAND_5G:
979 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a);
980 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a);
981 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a);
982 break;
983 default:
984 break;
985 }
986 rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
987 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
988 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI,
989 rf0 | iqk_info->syn1to2);
990 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
991 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
992 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
993 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
994 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
995 B_CFIR_LUT_GP, group);
996 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN);
997 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
998 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK, chanctx_idx);
999
1000 switch (iqk_info->iqk_band[path]) {
1001 case RTW89_BAND_2G:
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1004 break;
1005 case RTW89_BAND_5G:
1006 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
1007 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1008 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
1009 break;
1010 default:
1011 break;
1012 }
1013 if (!fail) {
1014 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1015 iqk_info->nb_rxcfir[path] = tmp | 0x2;
1016 } else {
1017 iqk_info->nb_rxcfir[path] = 0x40000002;
1018 }
1019 return fail;
1020 }
1021
_iqk_rxclk_setting(struct rtw89_dev * rtwdev,u8 path)1022 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
1023 {
1024 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1025
1026 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1027 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1028 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8),
1029 MASKDWORD, 0x4d000a08);
1030 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1031 B_P0_RXCK_VAL, 0x2);
1032 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1033 rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON);
1034 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1);
1035 } else {
1036 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8),
1037 MASKDWORD, 0x44000a08);
1038 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1039 B_P0_RXCK_VAL, 0x1);
1040 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1041 rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON);
1042 rtw89_phy_write32_clr(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL);
1043 }
1044 }
1045
_txk_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1046 static bool _txk_group_sel(struct rtw89_dev *rtwdev,
1047 enum rtw89_phy_idx phy_idx, u8 path,
1048 enum rtw89_chanctx_idx chanctx_idx)
1049 {
1050 static const u32 a_txgain[4] = {0xE466, 0x646D, 0xE4E2, 0x64ED};
1051 static const u32 g_txgain[4] = {0x60e8, 0x60f0, 0x61e8, 0x61ED};
1052 static const u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b};
1053 static const u32 g_itqt[4] = {0x09, 0x12, 0x12, 0x12};
1054 static const u32 g_attsmxr[4] = {0x0, 0x1, 0x1, 0x1};
1055 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1056 bool fail = false;
1057 u8 gp = 0x0;
1058 u32 tmp = 0x0;
1059
1060 for (gp = 0x0; gp < 0x4; gp++) {
1061 switch (iqk_info->iqk_band[path]) {
1062 case RTW89_BAND_2G:
1063 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1064 B_RFGAIN_BND, 0x08);
1065 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL,
1066 g_txgain[gp]);
1067 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1,
1068 g_attsmxr[gp]);
1069 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0,
1070 g_attsmxr[gp]);
1071 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1072 MASKDWORD, g_itqt[gp]);
1073 break;
1074 case RTW89_BAND_5G:
1075 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1076 B_RFGAIN_BND, 0x04);
1077 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL,
1078 a_txgain[gp]);
1079 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1080 MASKDWORD, a_itqt[gp]);
1081 break;
1082 default:
1083 break;
1084 }
1085 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1086 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1087 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
1088 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1089 B_CFIR_LUT_GP, gp);
1090 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
1091 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK, chanctx_idx);
1092 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail);
1093 }
1094
1095 iqk_info->nb_txcfir[path] = 0x40000000;
1096 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1097 B_IQK_RES_TXCFIR, 0x5);
1098 iqk_info->is_wb_txiqk[path] = true;
1099 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1100 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1101 BIT(path), tmp);
1102 return false;
1103 }
1104
_iqk_nbtxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1105 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev,
1106 enum rtw89_phy_idx phy_idx, u8 path,
1107 enum rtw89_chanctx_idx chanctx_idx)
1108 {
1109 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1110 u8 group = 0x2;
1111 u32 a_mode_txgain = 0x64e2;
1112 u32 g_mode_txgain = 0x61e8;
1113 u32 attsmxr = 0x1;
1114 u32 itqt = 0x12;
1115 u32 tmp = 0x0;
1116 bool fail = false;
1117
1118 switch (iqk_info->iqk_band[path]) {
1119 case RTW89_BAND_2G:
1120 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1121 B_RFGAIN_BND, 0x08);
1122 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain);
1123 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr);
1124 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr);
1125 break;
1126 case RTW89_BAND_5G:
1127 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1128 B_RFGAIN_BND, 0x04);
1129 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain);
1130 break;
1131 default:
1132 break;
1133 }
1134 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1135 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1136 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
1137 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group);
1138 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1139 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
1140 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK, chanctx_idx);
1141 if (!fail) {
1142 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1143 iqk_info->nb_txcfir[path] = tmp | 0x2;
1144 } else {
1145 iqk_info->nb_txcfir[path] = 0x40000002;
1146 }
1147 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1149 BIT(path), tmp);
1150 return fail;
1151 }
1152
_lok_res_table(struct rtw89_dev * rtwdev,u8 path,u8 ibias)1153 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
1154 {
1155 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1156
1157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
1159 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1160 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
1161 else
1162 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
1163 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
1164 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1165 }
1166
_lok_finetune_check(struct rtw89_dev * rtwdev,u8 path)1167 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1168 {
1169 bool is_fail = false;
1170 u32 tmp = 0x0;
1171 u32 core_i = 0x0;
1172 u32 core_q = 0x0;
1173
1174 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1175 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK][FineLOK] S%x, 0x58 = 0x%x\n",
1176 path, tmp);
1177 core_i = FIELD_GET(RR_TXMO_COI, tmp);
1178 core_q = FIELD_GET(RR_TXMO_COQ, tmp);
1179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i);
1180 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q);
1181
1182 if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d)
1183 is_fail = true;
1184 return is_fail;
1185 }
1186
_iqk_lok(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1187 static bool _iqk_lok(struct rtw89_dev *rtwdev,
1188 enum rtw89_phy_idx phy_idx, u8 path,
1189 enum rtw89_chanctx_idx chanctx_idx)
1190 {
1191 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1192 u32 rf0 = 0x0;
1193 u8 itqt = 0x12;
1194 bool fail = false;
1195 bool tmp = false;
1196
1197 switch (iqk_info->iqk_band[path]) {
1198 case RTW89_BAND_2G:
1199 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0);
1200 itqt = 0x09;
1201 break;
1202 case RTW89_BAND_5G:
1203 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0);
1204 itqt = 0x12;
1205 break;
1206 default:
1207 break;
1208 }
1209 rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
1210 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1211 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF1, B_IQK_DIF1_TXPI,
1212 rf0 | iqk_info->syn1to2);
1213 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1214 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1215 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1);
1216 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0);
1217 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN);
1218 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
1219 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1220 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE, chanctx_idx);
1221 iqk_info->lok_cor_fail[0][path] = tmp;
1222 fsleep(10);
1223 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1224 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE, chanctx_idx);
1225 iqk_info->lok_fin_fail[0][path] = tmp;
1226 fail = _lok_finetune_check(rtwdev, path);
1227 return fail;
1228 }
1229
_iqk_txk_setting(struct rtw89_dev * rtwdev,u8 path)1230 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1231 {
1232 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1233
1234 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1235 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
1236 udelay(1);
1237 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
1238 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
1239 udelay(1);
1240 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
1241 udelay(1);
1242 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
1243 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
1244 switch (iqk_info->iqk_band[path]) {
1245 case RTW89_BAND_2G:
1246 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00);
1247 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1248 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1249 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1);
1250 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1251 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1252 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1253 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1254 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000);
1255 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1256 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1257 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1258 0x403e0 | iqk_info->syn1to2);
1259 udelay(1);
1260 break;
1261 case RTW89_BAND_5G:
1262 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
1263 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1264 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7);
1265 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1266 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1267 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1268 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100);
1269 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1270 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1271 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1);
1272 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0);
1273 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1274 0x403e0 | iqk_info->syn1to2);
1275 udelay(1);
1276 break;
1277 default:
1278 break;
1279 }
1280 }
1281
_iqk_txclk_setting(struct rtw89_dev * rtwdev,u8 path)1282 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
1283 {
1284 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1285 }
1286
_iqk_info_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1287 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1288 u8 path)
1289 {
1290 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1291 u32 tmp = 0x0;
1292 bool flag = 0x0;
1293
1294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
1295 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
1296 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
1297 iqk_info->lok_cor_fail[0][path]);
1298 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
1299 iqk_info->lok_fin_fail[0][path]);
1300 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path,
1301 iqk_info->iqk_tx_fail[0][path]);
1302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path,
1303 iqk_info->iqk_rx_fail[0][path]);
1304 flag = iqk_info->lok_cor_fail[0][path];
1305 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag);
1306 flag = iqk_info->lok_fin_fail[0][path];
1307 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag);
1308 flag = iqk_info->iqk_tx_fail[0][path];
1309 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag);
1310 flag = iqk_info->iqk_rx_fail[0][path];
1311 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag);
1312
1313 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1314 iqk_info->bp_iqkenable[path] = tmp;
1315 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1316 iqk_info->bp_txkresult[path] = tmp;
1317 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1318 iqk_info->bp_rxkresult[path] = tmp;
1319
1320 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT,
1321 (u8)iqk_info->iqk_times);
1322
1323 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4));
1324 if (tmp != 0x0)
1325 iqk_info->iqk_fail_cnt++;
1326 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4),
1327 iqk_info->iqk_fail_cnt);
1328 }
1329
1330 static
_iqk_by_path(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1331 void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path,
1332 enum rtw89_chanctx_idx chanctx_idx)
1333 {
1334 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1335 bool lok_is_fail = false;
1336 u8 ibias = 0x1;
1337 u8 i = 0;
1338
1339 _iqk_txclk_setting(rtwdev, path);
1340
1341 for (i = 0; i < 3; i++) {
1342 _lok_res_table(rtwdev, path, ibias++);
1343 _iqk_txk_setting(rtwdev, path);
1344 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path, chanctx_idx);
1345 if (!lok_is_fail)
1346 break;
1347 }
1348 if (iqk_info->is_nbiqk)
1349 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path,
1350 chanctx_idx);
1351 else
1352 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path,
1353 chanctx_idx);
1354
1355 _iqk_rxclk_setting(rtwdev, path);
1356 _iqk_rxk_setting(rtwdev, path);
1357 if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G)
1358 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path,
1359 chanctx_idx);
1360 else
1361 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path,
1362 chanctx_idx);
1363
1364 _iqk_info_iqk(rtwdev, phy_idx, path);
1365 }
1366
_iqk_get_ch_info(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path,enum rtw89_chanctx_idx chanctx_idx)1367 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev,
1368 enum rtw89_phy_idx phy, u8 path,
1369 enum rtw89_chanctx_idx chanctx_idx)
1370 {
1371 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1372 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1373 u32 reg_rf18 = 0x0, reg_35c = 0x0;
1374 u8 idx = 0;
1375 u8 get_empty_table = false;
1376
1377 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1378 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
1379 if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
1380 get_empty_table = true;
1381 break;
1382 }
1383 }
1384 if (!get_empty_table) {
1385 idx = iqk_info->iqk_table_idx[path] + 1;
1386 if (idx > RTW89_IQK_CHS_NR - 1)
1387 idx = 0;
1388 }
1389 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1390 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]cfg ch = %d\n", reg_rf18);
1391 reg_35c = rtw89_phy_read32_mask(rtwdev, 0x35c, 0x00000c00);
1392
1393 iqk_info->iqk_band[path] = chan->band_type;
1394 iqk_info->iqk_bw[path] = chan->band_width;
1395 iqk_info->iqk_ch[path] = chan->channel;
1396
1397 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1398 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1399 iqk_info->iqk_band[path]);
1400 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n",
1401 path, iqk_info->iqk_bw[path]);
1402 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n",
1403 path, iqk_info->iqk_ch[path]);
1404 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1405 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1406 rtwdev->dbcc_en ? "on" : "off",
1407 iqk_info->iqk_band[path] == 0 ? "2G" :
1408 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1409 iqk_info->iqk_ch[path],
1410 iqk_info->iqk_bw[path] == 0 ? "20M" :
1411 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1412 if (reg_35c == 0x01)
1413 iqk_info->syn1to2 = 0x1;
1414 else
1415 iqk_info->syn1to2 = 0x0;
1416
1417 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852A_IQK_VER);
1418 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16),
1419 (u8)iqk_info->iqk_band[path]);
1420 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16),
1421 (u8)iqk_info->iqk_bw[path]);
1422 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16),
1423 (u8)iqk_info->iqk_ch[path]);
1424
1425 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x000000ff, RTW8852A_NCTL_VER);
1426 }
1427
_iqk_start_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1428 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1429 u8 path, enum rtw89_chanctx_idx chanctx_idx)
1430 {
1431 _iqk_by_path(rtwdev, phy_idx, path, chanctx_idx);
1432 }
1433
_iqk_restore(struct rtw89_dev * rtwdev,u8 path)1434 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1435 {
1436 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1437
1438 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1439 iqk_info->nb_txcfir[path]);
1440 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1441 iqk_info->nb_rxcfir[path]);
1442 rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD);
1443 rtw89_phy_write32_clr(rtwdev, R_MDPK_RX_DCK, MASKDWORD);
1444 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1445 rtw89_phy_write32_clr(rtwdev, R_KPATH_CFG, MASKDWORD);
1446 rtw89_phy_write32_clr(rtwdev, R_GAPK, B_GAPK_ADR);
1447 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1448 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN);
1449 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4);
1450 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1451 rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW);
1452 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002);
1453 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1454 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0);
1455 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1456 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1457 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0);
1458 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0);
1459 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1460 }
1461
_iqk_afebb_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1462 static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
1463 enum rtw89_phy_idx phy_idx, u8 path)
1464 {
1465 const struct rtw89_rfk_tbl *tbl;
1466
1467 switch (_kpath(rtwdev, phy_idx)) {
1468 case RF_A:
1469 tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl;
1470 break;
1471 case RF_B:
1472 tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl;
1473 break;
1474 default:
1475 tbl = &rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl;
1476 break;
1477 }
1478
1479 rtw89_rfk_parser(rtwdev, tbl);
1480 }
1481
_iqk_preset(struct rtw89_dev * rtwdev,u8 path)1482 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1483 {
1484 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1485 u8 idx = iqk_info->iqk_table_idx[path];
1486
1487 if (rtwdev->dbcc_en) {
1488 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
1489 B_COEF_SEL_IQC, path & 0x1);
1490 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1491 B_CFIR_LUT_G2, path & 0x1);
1492 } else {
1493 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
1494 B_COEF_SEL_IQC, idx);
1495 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1496 B_CFIR_LUT_G2, idx);
1497 }
1498 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1499 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1500 rtw89_phy_write32_clr(rtwdev, R_NCTL_RW, MASKDWORD);
1501 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
1502 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, MASKDWORD, 0x00200000);
1503 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000);
1504 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD);
1505 }
1506
_iqk_macbb_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1507 static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
1508 enum rtw89_phy_idx phy_idx, u8 path)
1509 {
1510 const struct rtw89_rfk_tbl *tbl;
1511
1512 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===> %s\n", __func__);
1513
1514 switch (_kpath(rtwdev, phy_idx)) {
1515 case RF_A:
1516 tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl;
1517 break;
1518 case RF_B:
1519 tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl;
1520 break;
1521 default:
1522 tbl = &rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl;
1523 break;
1524 }
1525
1526 rtw89_rfk_parser(rtwdev, tbl);
1527 }
1528
_iqk_dbcc(struct rtw89_dev * rtwdev,u8 path,enum rtw89_chanctx_idx chanctx_idx)1529 static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path,
1530 enum rtw89_chanctx_idx chanctx_idx)
1531 {
1532 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1533 u8 phy_idx = 0x0;
1534
1535 iqk_info->iqk_times++;
1536
1537 if (path == 0x0)
1538 phy_idx = RTW89_PHY_0;
1539 else
1540 phy_idx = RTW89_PHY_1;
1541
1542 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1543 _iqk_macbb_setting(rtwdev, phy_idx, path);
1544 _iqk_preset(rtwdev, path);
1545 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx);
1546 _iqk_restore(rtwdev, path);
1547 _iqk_afebb_restore(rtwdev, phy_idx, path);
1548 }
1549
_rck(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)1550 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1551 {
1552 u32 rf_reg5, rck_val = 0;
1553 u32 val;
1554 int ret;
1555
1556 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
1557
1558 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1559
1560 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1561 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1562
1563 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n",
1564 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
1565
1566 /* RCK trigger */
1567 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
1568
1569 ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 20,
1570 false, rtwdev, path, 0x1c, BIT(3));
1571 if (ret)
1572 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n");
1573
1574 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
1575 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
1576
1577 /* RCK_ADC_OFFSET */
1578 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4);
1579
1580 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1);
1581 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0);
1582
1583 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1584
1585 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1586 "[RCK] RF 0x1b / 0x1c / 0x1d = 0x%x / 0x%x / 0x%x\n",
1587 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK),
1588 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK),
1589 rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK));
1590 }
1591
_iqk_init(struct rtw89_dev * rtwdev)1592 static void _iqk_init(struct rtw89_dev *rtwdev)
1593 {
1594 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1595 u8 ch, path;
1596
1597 rtw89_phy_write32_clr(rtwdev, R_IQKINF, MASKDWORD);
1598 if (iqk_info->is_iqk_init)
1599 return;
1600
1601 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1602 iqk_info->is_iqk_init = true;
1603 iqk_info->is_nbiqk = false;
1604 iqk_info->iqk_fft_en = false;
1605 iqk_info->iqk_sram_en = false;
1606 iqk_info->iqk_cfir_en = false;
1607 iqk_info->iqk_xym_en = false;
1608 iqk_info->iqk_times = 0x0;
1609
1610 for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) {
1611 iqk_info->iqk_channel[ch] = 0x0;
1612 for (path = 0; path < RTW8852A_IQK_SS; path++) {
1613 iqk_info->lok_cor_fail[ch][path] = false;
1614 iqk_info->lok_fin_fail[ch][path] = false;
1615 iqk_info->iqk_tx_fail[ch][path] = false;
1616 iqk_info->iqk_rx_fail[ch][path] = false;
1617 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1618 iqk_info->iqk_table_idx[path] = 0x0;
1619 }
1620 }
1621 }
1622
_doiqk(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1623 static void _doiqk(struct rtw89_dev *rtwdev, bool force,
1624 enum rtw89_phy_idx phy_idx, u8 path,
1625 enum rtw89_chanctx_idx chanctx_idx)
1626 {
1627 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1628 u32 backup_bb_val[BACKUP_BB_REGS_NR];
1629 u32 backup_rf_val[RTW8852A_IQK_SS][BACKUP_RF_REGS_NR];
1630 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
1631
1632 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
1633
1634 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1635 "[IQK]==========IQK start!!!!!==========\n");
1636 iqk_info->iqk_times++;
1637 iqk_info->version = RTW8852A_IQK_VER;
1638
1639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1640 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1641 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
1642 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1643 _iqk_macbb_setting(rtwdev, phy_idx, path);
1644 _iqk_preset(rtwdev, path);
1645 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx);
1646 _iqk_restore(rtwdev, path);
1647 _iqk_afebb_restore(rtwdev, phy_idx, path);
1648 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
1649 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1650 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
1651 }
1652
_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool force,enum rtw89_chanctx_idx chanctx_idx)1653 static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force,
1654 enum rtw89_chanctx_idx chanctx_idx)
1655 {
1656 switch (_kpath(rtwdev, phy_idx)) {
1657 case RF_A:
1658 _doiqk(rtwdev, force, phy_idx, RF_PATH_A, chanctx_idx);
1659 break;
1660 case RF_B:
1661 _doiqk(rtwdev, force, phy_idx, RF_PATH_B, chanctx_idx);
1662 break;
1663 case RF_AB:
1664 _doiqk(rtwdev, force, phy_idx, RF_PATH_A, chanctx_idx);
1665 _doiqk(rtwdev, force, phy_idx, RF_PATH_B, chanctx_idx);
1666 break;
1667 default:
1668 break;
1669 }
1670 }
1671
1672 #define RXDCK_VER_8852A 0xe
1673
_set_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,bool is_afe,enum rtw89_chanctx_idx chanctx_idx)1674 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1675 enum rtw89_rf_path path, bool is_afe,
1676 enum rtw89_chanctx_idx chanctx_idx)
1677 {
1678 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx);
1679 u32 ori_val;
1680
1681 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1682 "[RX_DCK] ==== S%d RX DCK (by %s)====\n",
1683 path, is_afe ? "AFE" : "RFC");
1684
1685 ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD);
1686
1687 if (is_afe) {
1688 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1689 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1690 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1691 B_P0_RXCK_VAL, 0x3);
1692 rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN);
1693 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13),
1694 B_S0_RXDC2_AVG, 0x3);
1695 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
1696 rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK);
1697 rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST);
1698 rtw89_phy_write32_set(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST);
1699 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_CRXBB, 0x1);
1700 }
1701
1702 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f);
1703 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe);
1704
1705 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_START);
1706
1707 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1708 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1709
1710 fsleep(600);
1711
1712 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_STOP);
1713
1714 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1715
1716 if (is_afe) {
1717 rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1718 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1719 MASKDWORD, ori_val);
1720 }
1721 }
1722
_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool is_afe,enum rtw89_chanctx_idx chanctx_idx)1723 static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1724 bool is_afe, enum rtw89_chanctx_idx chanctx_idx)
1725 {
1726 u8 path, kpath, dck_tune;
1727 u32 rf_reg5;
1728 u32 addr;
1729
1730 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1731 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",
1732 RXDCK_VER_8852A, rtwdev->hal.cv);
1733
1734 kpath = _kpath(rtwdev, phy);
1735
1736 for (path = 0; path < 2; path++) {
1737 if (!(kpath & BIT(path)))
1738 continue;
1739
1740 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1741 dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
1742
1743 if (rtwdev->is_tssi_mode[path]) {
1744 addr = 0x5818 + (path << 13);
1745 /* TSSI pause */
1746 rtw89_phy_write32_set(rtwdev, addr, BIT(30));
1747 }
1748
1749 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1750 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
1751 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1752 _set_rx_dck(rtwdev, phy, path, is_afe, chanctx_idx);
1753 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
1754 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1755
1756 if (rtwdev->is_tssi_mode[path]) {
1757 addr = 0x5818 + (path << 13);
1758 /* TSSI resume */
1759 rtw89_phy_write32_clr(rtwdev, addr, BIT(30));
1760 }
1761 }
1762 }
1763
1764 #define RTW8852A_RF_REL_VERSION 34
1765 #define RTW8852A_DPK_VER 0x10
1766 #define RTW8852A_DPK_TH_AVG_NUM 4
1767 #define RTW8852A_DPK_RF_PATH 2
1768 #define RTW8852A_DPK_KIP_REG_NUM 2
1769
1770 enum rtw8852a_dpk_id {
1771 LBK_RXIQK = 0x06,
1772 SYNC = 0x10,
1773 MDPK_IDL = 0x11,
1774 MDPK_MPA = 0x12,
1775 GAIN_LOSS = 0x13,
1776 GAIN_CAL = 0x14,
1777 };
1778
_rf_direct_cntrl(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_bybb)1779 static void _rf_direct_cntrl(struct rtw89_dev *rtwdev,
1780 enum rtw89_rf_path path, bool is_bybb)
1781 {
1782 if (is_bybb)
1783 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1784 else
1785 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1786 }
1787
1788 static void _dpk_onoff(struct rtw89_dev *rtwdev,
1789 enum rtw89_rf_path path, bool off);
1790
_dpk_bkup_kip(struct rtw89_dev * rtwdev,u32 * reg,u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM],u8 path)1791 static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, u32 *reg,
1792 u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM],
1793 u8 path)
1794 {
1795 u8 i;
1796
1797 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) {
1798 reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev,
1799 reg[i] + (path << 8),
1800 MASKDWORD);
1801 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
1802 reg[i] + (path << 8), reg_bkup[path][i]);
1803 }
1804 }
1805
_dpk_reload_kip(struct rtw89_dev * rtwdev,u32 * reg,u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM],u8 path)1806 static void _dpk_reload_kip(struct rtw89_dev *rtwdev, u32 *reg,
1807 u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path)
1808 {
1809 u8 i;
1810
1811 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) {
1812 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8),
1813 MASKDWORD, reg_bkup[path][i]);
1814 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n",
1815 reg[i] + (path << 8), reg_bkup[path][i]);
1816 }
1817 }
1818
_dpk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw8852a_dpk_id id,enum rtw89_chanctx_idx chanctx_idx)1819 static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1820 enum rtw89_rf_path path, enum rtw8852a_dpk_id id,
1821 enum rtw89_chanctx_idx chanctx_idx)
1822 {
1823 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx);
1824 u16 dpk_cmd = 0x0;
1825 u32 val;
1826 int ret;
1827
1828 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4)));
1829
1830 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_START);
1831
1832 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
1833 rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
1834
1835 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
1836 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0);
1837
1838 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
1839
1840 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_STOP);
1841
1842 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1843 "[DPK] one-shot for %s = 0x%x (ret=%d)\n",
1844 id == 0x06 ? "LBK_RXIQK" :
1845 id == 0x10 ? "SYNC" :
1846 id == 0x11 ? "MDPK_IDL" :
1847 id == 0x12 ? "MDPK_MPA" :
1848 id == 0x13 ? "GAIN_LOSS" : "PWR_CAL",
1849 dpk_cmd, ret);
1850
1851 if (ret) {
1852 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1853 "[DPK] one-shot over 20ms!!!!\n");
1854 return 1;
1855 }
1856
1857 return 0;
1858 }
1859
_dpk_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)1860 static void _dpk_rx_dck(struct rtw89_dev *rtwdev,
1861 enum rtw89_phy_idx phy,
1862 enum rtw89_rf_path path,
1863 enum rtw89_chanctx_idx chanctx_idx)
1864 {
1865 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
1866 _set_rx_dck(rtwdev, phy, path, false, chanctx_idx);
1867 }
1868
_dpk_information(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)1869 static void _dpk_information(struct rtw89_dev *rtwdev,
1870 enum rtw89_phy_idx phy,
1871 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1872 {
1873 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1874 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1875 u8 kidx = dpk->cur_idx[path];
1876
1877 dpk->bp[path][kidx].band = chan->band_type;
1878 dpk->bp[path][kidx].ch = chan->channel;
1879 dpk->bp[path][kidx].bw = chan->band_width;
1880
1881 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1882 "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1883 path, dpk->cur_idx[path], phy,
1884 rtwdev->is_tssi_mode[path] ? "on" : "off",
1885 rtwdev->dbcc_en ? "on" : "off",
1886 dpk->bp[path][kidx].band == 0 ? "2G" :
1887 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1888 dpk->bp[path][kidx].ch,
1889 dpk->bp[path][kidx].bw == 0 ? "20M" :
1890 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1891 }
1892
_dpk_bb_afe_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kpath)1893 static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev,
1894 enum rtw89_phy_idx phy,
1895 enum rtw89_rf_path path, u8 kpath)
1896 {
1897 switch (kpath) {
1898 case RF_A:
1899 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl);
1900
1901 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x0)
1902 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1903
1904 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl);
1905 break;
1906 case RF_B:
1907 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl);
1908
1909 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x1)
1910 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1911
1912 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl);
1913 break;
1914 case RF_AB:
1915 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl);
1916 break;
1917 default:
1918 break;
1919 }
1920 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1921 "[DPK] Set BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
1922 }
1923
_dpk_bb_afe_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kpath)1924 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev,
1925 enum rtw89_phy_idx phy,
1926 enum rtw89_rf_path path, u8 kpath)
1927 {
1928 switch (kpath) {
1929 case RF_A:
1930 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl);
1931 break;
1932 case RF_B:
1933 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl);
1934 break;
1935 case RF_AB:
1936 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl);
1937 break;
1938 default:
1939 break;
1940 }
1941 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1942 "[DPK] Restore BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
1943 }
1944
_dpk_tssi_pause(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_pause)1945 static void _dpk_tssi_pause(struct rtw89_dev *rtwdev,
1946 enum rtw89_rf_path path, bool is_pause)
1947 {
1948 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1949 B_P0_TSSI_TRK_EN, is_pause);
1950
1951 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1952 is_pause ? "pause" : "resume");
1953 }
1954
_dpk_kip_setting(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)1955 static void _dpk_kip_setting(struct rtw89_dev *rtwdev,
1956 enum rtw89_rf_path path, u8 kidx)
1957 {
1958 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1959 rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x00093f3f);
1960 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
1961 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1962 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG, B_DPK_CFG_IDX, 0x2);
1963 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/
1964 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2),
1965 MASKDWORD, 0x003f2e2e);
1966 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1967 MASKDWORD, 0x005b5b5b);
1968
1969 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP setting for S%d[%d]!!\n",
1970 path, kidx);
1971 }
1972
_dpk_kip_restore(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)1973 static void _dpk_kip_restore(struct rtw89_dev *rtwdev,
1974 enum rtw89_rf_path path)
1975 {
1976 rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD);
1977 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1978 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1979 rtw89_phy_write32_clr(rtwdev, R_KIP_CLK, MASKDWORD);
1980
1981 if (rtwdev->hal.cv > CHIP_CBV)
1982 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1);
1983
1984 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1985 }
1986
_dpk_lbk_rxiqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)1987 static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev,
1988 enum rtw89_phy_idx phy,
1989 enum rtw89_rf_path path,
1990 enum rtw89_chanctx_idx chanctx_idx)
1991 {
1992 u8 cur_rxbb;
1993
1994 cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
1995
1996 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl);
1997
1998 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
1999 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
2000 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2);
2001 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK,
2002 rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK));
2003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
2004 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
2005 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
2006
2007 fsleep(70);
2008
2009 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f);
2010
2011 if (cur_rxbb <= 0xa)
2012 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3);
2013 else if (cur_rxbb <= 0x10 && cur_rxbb >= 0xb)
2014 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1);
2015 else
2016 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0);
2017
2018 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
2019
2020 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK, chanctx_idx);
2021
2022 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2023 rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD));
2024
2025 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
2026 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0);
2027 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/
2028 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK);
2029
2030 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl);
2031 }
2032
_dpk_get_thermal(struct rtw89_dev * rtwdev,u8 kidx,enum rtw89_rf_path path)2033 static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx,
2034 enum rtw89_rf_path path)
2035 {
2036 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2037
2038 dpk->bp[path][kidx].ther_dpk =
2039 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2040
2041 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n",
2042 dpk->bp[path][kidx].ther_dpk);
2043 }
2044
_dpk_set_tx_pwr(struct rtw89_dev * rtwdev,u8 gain,enum rtw89_rf_path path)2045 static u8 _dpk_set_tx_pwr(struct rtw89_dev *rtwdev, u8 gain,
2046 enum rtw89_rf_path path)
2047 {
2048 u8 txagc_ori = 0x38;
2049
2050 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori);
2051
2052 return txagc_ori;
2053 }
2054
_dpk_rf_setting(struct rtw89_dev * rtwdev,u8 gain,enum rtw89_rf_path path,u8 kidx)2055 static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain,
2056 enum rtw89_rf_path path, u8 kidx)
2057 {
2058 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2059
2060 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2061 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b);
2062 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
2063 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4);
2064 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0);
2065 } else {
2066 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e);
2067 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7);
2068 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3);
2069 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3);
2070 }
2071 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
2072 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
2073 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
2074
2075 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2076 "[DPK] RF 0x0/0x1/0x1a = 0x%x/ 0x%x/ 0x%x\n",
2077 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
2078 rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK),
2079 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
2080 }
2081
_dpk_manual_txcfir(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_manual)2082 static void _dpk_manual_txcfir(struct rtw89_dev *rtwdev,
2083 enum rtw89_rf_path path, bool is_manual)
2084 {
2085 u8 tmp_pad, tmp_txbb;
2086
2087 if (is_manual) {
2088 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1);
2089 tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD);
2090 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8),
2091 B_RFGAIN_PAD, tmp_pad);
2092
2093 tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB);
2094 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8),
2095 B_RFGAIN_TXBB, tmp_txbb);
2096
2097 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8),
2098 B_LOAD_COEF_CFIR, 0x1);
2099 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8),
2100 B_LOAD_COEF_CFIR);
2101
2102 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1);
2103
2104 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2105 "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", tmp_pad,
2106 tmp_txbb);
2107 } else {
2108 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN);
2109 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2110 "[DPK] disable manual switch TXCFIR\n");
2111 }
2112 }
2113
_dpk_bypass_rxcfir(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_bypass)2114 static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev,
2115 enum rtw89_rf_path path, bool is_bypass)
2116 {
2117 if (is_bypass) {
2118 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
2119 B_RXIQC_BYPASS2, 0x1);
2120 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
2121 B_RXIQC_BYPASS, 0x1);
2122 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2123 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
2124 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
2125 MASKDWORD));
2126 } else {
2127 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
2128 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
2129 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2130 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
2131 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
2132 MASKDWORD));
2133 }
2134 }
2135
2136 static
_dpk_tpg_sel(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)2137 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2138 {
2139 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2140
2141 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2142 rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F);
2143 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
2144 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
2145 else
2146 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
2147
2148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n",
2149 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2150 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2151 }
2152
_dpk_table_select(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx,u8 gain)2153 static void _dpk_table_select(struct rtw89_dev *rtwdev,
2154 enum rtw89_rf_path path, u8 kidx, u8 gain)
2155 {
2156 u8 val;
2157
2158 val = 0x80 + kidx * 0x20 + gain * 0x10;
2159 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
2160 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2161 "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx,
2162 gain, val);
2163 }
2164
_dpk_sync_check(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)2165 static bool _dpk_sync_check(struct rtw89_dev *rtwdev,
2166 enum rtw89_rf_path path)
2167 {
2168 #define DPK_SYNC_TH_DC_I 200
2169 #define DPK_SYNC_TH_DC_Q 200
2170 #define DPK_SYNC_TH_CORR 170
2171 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2172 u16 dc_i, dc_q;
2173 u8 corr_val, corr_idx;
2174
2175 rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL);
2176
2177 corr_idx = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
2178 corr_val = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
2179
2180 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2181 "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx,
2182 corr_val);
2183
2184 dpk->corr_idx[path][0] = corr_idx;
2185 dpk->corr_val[path][0] = corr_val;
2186
2187 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
2188
2189 dc_i = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2190 dc_q = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
2191
2192 dc_i = abs(sign_extend32(dc_i, 11));
2193 dc_q = abs(sign_extend32(dc_q, 11));
2194
2195 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n",
2196 path, dc_i, dc_q);
2197
2198 dpk->dc_i[path][0] = dc_i;
2199 dpk->dc_q[path][0] = dc_q;
2200
2201 if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q ||
2202 corr_val < DPK_SYNC_TH_CORR)
2203 return true;
2204 else
2205 return false;
2206 }
2207
_dpk_sync(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,enum rtw89_chanctx_idx chanctx_idx)2208 static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2209 enum rtw89_rf_path path, u8 kidx,
2210 enum rtw89_chanctx_idx chanctx_idx)
2211 {
2212 _dpk_tpg_sel(rtwdev, path, kidx);
2213 _dpk_one_shot(rtwdev, phy, path, SYNC, chanctx_idx);
2214 return _dpk_sync_check(rtwdev, path); /*1= fail*/
2215 }
2216
_dpk_dgain_read(struct rtw89_dev * rtwdev)2217 static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
2218 {
2219 u16 dgain = 0x0;
2220
2221 rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL);
2222
2223 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_SYNERR);
2224
2225 dgain = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2226
2227 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain,
2228 dgain);
2229
2230 return dgain;
2231 }
2232
_dpk_dgain_mapping(struct rtw89_dev * rtwdev,u16 dgain)2233 static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain)
2234 {
2235 s8 offset;
2236
2237 if (dgain >= 0x783)
2238 offset = 0x6;
2239 else if (dgain <= 0x782 && dgain >= 0x551)
2240 offset = 0x3;
2241 else if (dgain <= 0x550 && dgain >= 0x3c4)
2242 offset = 0x0;
2243 else if (dgain <= 0x3c3 && dgain >= 0x2aa)
2244 offset = -3;
2245 else if (dgain <= 0x2a9 && dgain >= 0x1e3)
2246 offset = -6;
2247 else if (dgain <= 0x1e2 && dgain >= 0x156)
2248 offset = -9;
2249 else if (dgain <= 0x155)
2250 offset = -12;
2251 else
2252 offset = 0x0;
2253
2254 return offset;
2255 }
2256
_dpk_gainloss_read(struct rtw89_dev * rtwdev)2257 static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
2258 {
2259 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
2260 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
2261 return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
2262 }
2263
_dpk_gainloss(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,enum rtw89_chanctx_idx chanctx_idx)2264 static void _dpk_gainloss(struct rtw89_dev *rtwdev,
2265 enum rtw89_phy_idx phy, enum rtw89_rf_path path,
2266 u8 kidx, enum rtw89_chanctx_idx chanctx_idx)
2267 {
2268 _dpk_table_select(rtwdev, path, kidx, 1);
2269 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS, chanctx_idx);
2270 }
2271
2272 #define DPK_TXAGC_LOWER 0x2e
2273 #define DPK_TXAGC_UPPER 0x3f
2274 #define DPK_TXAGC_INVAL 0xff
2275
_dpk_set_offset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,s8 gain_offset)2276 static u8 _dpk_set_offset(struct rtw89_dev *rtwdev,
2277 enum rtw89_rf_path path, s8 gain_offset)
2278 {
2279 u8 txagc;
2280
2281 txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK);
2282
2283 if (txagc - gain_offset < DPK_TXAGC_LOWER)
2284 txagc = DPK_TXAGC_LOWER;
2285 else if (txagc - gain_offset > DPK_TXAGC_UPPER)
2286 txagc = DPK_TXAGC_UPPER;
2287 else
2288 txagc = txagc - gain_offset;
2289
2290 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc);
2291
2292 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n",
2293 gain_offset, txagc);
2294 return txagc;
2295 }
2296
2297 enum dpk_agc_step {
2298 DPK_AGC_STEP_SYNC_DGAIN,
2299 DPK_AGC_STEP_GAIN_ADJ,
2300 DPK_AGC_STEP_GAIN_LOSS_IDX,
2301 DPK_AGC_STEP_GL_GT_CRITERION,
2302 DPK_AGC_STEP_GL_LT_CRITERION,
2303 DPK_AGC_STEP_SET_TX_GAIN,
2304 };
2305
_dpk_pas_read(struct rtw89_dev * rtwdev,bool is_check)2306 static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
2307 {
2308 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
2309 u8 i;
2310
2311 rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_pas_read_defs_tbl);
2312
2313 if (is_check) {
2314 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
2315 val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2316 val1_i = abs(sign_extend32(val1_i, 11));
2317 val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2318 val1_q = abs(sign_extend32(val1_q, 11));
2319 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
2320 val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2321 val2_i = abs(sign_extend32(val2_i, 11));
2322 val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2323 val2_q = abs(sign_extend32(val2_q, 11));
2324
2325 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
2326 phy_div(val1_i * val1_i + val1_q * val1_q,
2327 val2_i * val2_i + val2_q * val2_q));
2328
2329 } else {
2330 for (i = 0; i < 32; i++) {
2331 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
2332 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2333 "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
2334 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
2335 }
2336 }
2337 if ((val1_i * val1_i + val1_q * val1_q) >=
2338 ((val2_i * val2_i + val2_q * val2_q) * 8 / 5))
2339 return 1;
2340 else
2341 return 0;
2342 }
2343
_dpk_agc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 init_txagc,bool loss_only,enum rtw89_chanctx_idx chanctx_idx)2344 static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2345 enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
2346 bool loss_only, enum rtw89_chanctx_idx chanctx_idx)
2347 {
2348 #define DPK_AGC_ADJ_LMT 6
2349 #define DPK_DGAIN_UPPER 1922
2350 #define DPK_DGAIN_LOWER 342
2351 #define DPK_RXBB_UPPER 0x1f
2352 #define DPK_RXBB_LOWER 0
2353 #define DPK_GL_CRIT 7
2354 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2355 u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0;
2356 u8 agc_cnt = 0;
2357 bool limited_rxbb = false;
2358 s8 offset = 0;
2359 u16 dgain = 0;
2360 u8 step = DPK_AGC_STEP_SYNC_DGAIN;
2361 bool goout = false;
2362
2363 tmp_txagc = init_txagc;
2364
2365 do {
2366 switch (step) {
2367 case DPK_AGC_STEP_SYNC_DGAIN:
2368 if (_dpk_sync(rtwdev, phy, path, kidx, chanctx_idx)) {
2369 tmp_txagc = DPK_TXAGC_INVAL;
2370 goout = true;
2371 break;
2372 }
2373
2374 dgain = _dpk_dgain_read(rtwdev);
2375
2376 if (loss_only || limited_rxbb)
2377 step = DPK_AGC_STEP_GAIN_LOSS_IDX;
2378 else
2379 step = DPK_AGC_STEP_GAIN_ADJ;
2380 break;
2381
2382 case DPK_AGC_STEP_GAIN_ADJ:
2383 tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2384 offset = _dpk_dgain_mapping(rtwdev, dgain);
2385
2386 if (tmp_rxbb + offset > DPK_RXBB_UPPER) {
2387 tmp_rxbb = DPK_RXBB_UPPER;
2388 limited_rxbb = true;
2389 } else if (tmp_rxbb + offset < DPK_RXBB_LOWER) {
2390 tmp_rxbb = DPK_RXBB_LOWER;
2391 limited_rxbb = true;
2392 } else {
2393 tmp_rxbb = tmp_rxbb + offset;
2394 }
2395
2396 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb);
2397 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2398 "[DPK] Adjust RXBB (%d) = 0x%x\n", offset,
2399 tmp_rxbb);
2400 if (offset != 0 || agc_cnt == 0) {
2401 if (chan->band_width < RTW89_CHANNEL_WIDTH_80)
2402 _dpk_bypass_rxcfir(rtwdev, path, true);
2403 else
2404 _dpk_lbk_rxiqk(rtwdev, phy, path,
2405 chanctx_idx);
2406 }
2407 if (dgain > DPK_DGAIN_UPPER || dgain < DPK_DGAIN_LOWER)
2408 step = DPK_AGC_STEP_SYNC_DGAIN;
2409 else
2410 step = DPK_AGC_STEP_GAIN_LOSS_IDX;
2411
2412 agc_cnt++;
2413 break;
2414
2415 case DPK_AGC_STEP_GAIN_LOSS_IDX:
2416 _dpk_gainloss(rtwdev, phy, path, kidx, chanctx_idx);
2417 tmp_gl_idx = _dpk_gainloss_read(rtwdev);
2418
2419 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
2420 tmp_gl_idx > DPK_GL_CRIT)
2421 step = DPK_AGC_STEP_GL_GT_CRITERION;
2422 else if (tmp_gl_idx == 0)
2423 step = DPK_AGC_STEP_GL_LT_CRITERION;
2424 else
2425 step = DPK_AGC_STEP_SET_TX_GAIN;
2426 break;
2427
2428 case DPK_AGC_STEP_GL_GT_CRITERION:
2429 if (tmp_txagc == DPK_TXAGC_LOWER) {
2430 goout = true;
2431 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2432 "[DPK] Txagc@lower bound!!\n");
2433 } else {
2434 tmp_txagc = _dpk_set_offset(rtwdev, path, 3);
2435 }
2436 step = DPK_AGC_STEP_GAIN_LOSS_IDX;
2437 agc_cnt++;
2438 break;
2439
2440 case DPK_AGC_STEP_GL_LT_CRITERION:
2441 if (tmp_txagc == DPK_TXAGC_UPPER) {
2442 goout = true;
2443 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2444 "[DPK] Txagc@upper bound!!\n");
2445 } else {
2446 tmp_txagc = _dpk_set_offset(rtwdev, path, -2);
2447 }
2448 step = DPK_AGC_STEP_GAIN_LOSS_IDX;
2449 agc_cnt++;
2450 break;
2451
2452 case DPK_AGC_STEP_SET_TX_GAIN:
2453 tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx);
2454 goout = true;
2455 agc_cnt++;
2456 break;
2457
2458 default:
2459 goout = true;
2460 break;
2461 }
2462 } while (!goout && (agc_cnt < DPK_AGC_ADJ_LMT));
2463
2464 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2465 "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc,
2466 tmp_rxbb);
2467
2468 return tmp_txagc;
2469 }
2470
_dpk_set_mdpd_para(struct rtw89_dev * rtwdev,u8 order)2471 static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
2472 {
2473 switch (order) {
2474 case 0:
2475 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2476 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
2477 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1);
2478 break;
2479 case 1:
2480 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2481 rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
2482 rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
2483 break;
2484 case 2:
2485 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2486 rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
2487 rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
2488 break;
2489 default:
2490 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2491 "[DPK] Wrong MDPD order!!(0x%x)\n", order);
2492 break;
2493 }
2494
2495 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2496 "[DPK] Set MDPD order to 0x%x for IDL\n", order);
2497 }
2498
_dpk_idl_mpa(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 gain,enum rtw89_chanctx_idx chanctx_idx)2499 static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2500 enum rtw89_rf_path path, u8 kidx, u8 gain,
2501 enum rtw89_chanctx_idx chanctx_idx)
2502 {
2503 _dpk_set_mdpd_para(rtwdev, 0x0);
2504 _dpk_table_select(rtwdev, path, kidx, 1);
2505 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL, chanctx_idx);
2506 }
2507
_dpk_fill_result(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx,u8 gain,u8 txagc)2508 static void _dpk_fill_result(struct rtw89_dev *rtwdev,
2509 enum rtw89_rf_path path, u8 kidx, u8 gain,
2510 u8 txagc)
2511 {
2512 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2513
2514 u16 pwsf = 0x78;
2515 u8 gs = 0x5b;
2516
2517 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx);
2518
2519 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2520 "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc,
2521 pwsf, gs);
2522
2523 dpk->bp[path][kidx].txagc_dpk = txagc;
2524 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
2525 0x3F << ((gain << 3) + (kidx << 4)), txagc);
2526
2527 dpk->bp[path][kidx].pwsf = pwsf;
2528 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2529 0x1FF << (gain << 4), pwsf);
2530
2531 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2532 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD);
2533
2534 dpk->bp[path][kidx].gs = gs;
2535 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2536 MASKDWORD, 0x065b5b5b);
2537
2538 rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD);
2539
2540 rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL);
2541 }
2542
_dpk_reload_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)2543 static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2544 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
2545 {
2546 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2547 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2548 bool is_reload = false;
2549 u8 idx, cur_band, cur_ch;
2550
2551 cur_band = chan->band_type;
2552 cur_ch = chan->channel;
2553
2554 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) {
2555 if (cur_band != dpk->bp[path][idx].band ||
2556 cur_ch != dpk->bp[path][idx].ch)
2557 continue;
2558
2559 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2560 B_COEF_SEL_MDPD, idx);
2561 dpk->cur_idx[path] = idx;
2562 is_reload = true;
2563 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2564 "[DPK] reload S%d[%d] success\n", path, idx);
2565 }
2566
2567 return is_reload;
2568 }
2569
_dpk_main(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 gain,enum rtw89_chanctx_idx chanctx_idx)2570 static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2571 enum rtw89_rf_path path, u8 gain,
2572 enum rtw89_chanctx_idx chanctx_idx)
2573 {
2574 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2575 u8 txagc = 0, kidx = dpk->cur_idx[path];
2576 bool is_fail = false;
2577
2578 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2579 "[DPK] ========= S%d[%d] DPK Start =========\n", path,
2580 kidx);
2581
2582 _rf_direct_cntrl(rtwdev, path, false);
2583 txagc = _dpk_set_tx_pwr(rtwdev, gain, path);
2584 _dpk_rf_setting(rtwdev, gain, path, kidx);
2585 _dpk_rx_dck(rtwdev, phy, path, chanctx_idx);
2586
2587 _dpk_kip_setting(rtwdev, path, kidx);
2588 _dpk_manual_txcfir(rtwdev, path, true);
2589 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx);
2590 if (txagc == DPK_TXAGC_INVAL)
2591 is_fail = true;
2592 _dpk_get_thermal(rtwdev, kidx, path);
2593
2594 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain, chanctx_idx);
2595 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2596 _dpk_fill_result(rtwdev, path, kidx, gain, txagc);
2597 _dpk_manual_txcfir(rtwdev, path, false);
2598
2599 if (!is_fail)
2600 dpk->bp[path][kidx].path_ok = true;
2601 else
2602 dpk->bp[path][kidx].path_ok = false;
2603
2604 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2605 is_fail ? "Check" : "Success");
2606
2607 return is_fail;
2608 }
2609
_dpk_cal_select(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy,u8 kpath,enum rtw89_chanctx_idx chanctx_idx)2610 static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
2611 enum rtw89_phy_idx phy, u8 kpath,
2612 enum rtw89_chanctx_idx chanctx_idx)
2613 {
2614 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2615 u32 backup_bb_val[BACKUP_BB_REGS_NR];
2616 u32 backup_rf_val[RTW8852A_DPK_RF_PATH][BACKUP_RF_REGS_NR];
2617 u32 kip_bkup[RTW8852A_DPK_RF_PATH][RTW8852A_DPK_KIP_REG_NUM] = {{0}};
2618 u32 kip_reg[] = {R_RXIQC, R_IQK_RES};
2619 u8 path;
2620 bool is_fail = true, reloaded[RTW8852A_DPK_RF_PATH] = {false};
2621
2622 if (dpk->is_dpk_reload_en) {
2623 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2624 if (!(kpath & BIT(path)))
2625 continue;
2626
2627 reloaded[path] = _dpk_reload_check(rtwdev, phy, path,
2628 chanctx_idx);
2629 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2630 dpk->cur_idx[path] = !dpk->cur_idx[path];
2631 else
2632 _dpk_onoff(rtwdev, path, false);
2633 }
2634 } else {
2635 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++)
2636 dpk->cur_idx[path] = 0;
2637 }
2638
2639 if ((kpath == RF_A && reloaded[RF_PATH_A]) ||
2640 (kpath == RF_B && reloaded[RF_PATH_B]) ||
2641 (kpath == RF_AB && reloaded[RF_PATH_A] && reloaded[RF_PATH_B]))
2642 return;
2643
2644 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
2645
2646 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2647 if (!(kpath & BIT(path)) || reloaded[path])
2648 continue;
2649 if (rtwdev->is_tssi_mode[path])
2650 _dpk_tssi_pause(rtwdev, path, true);
2651 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2652 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2653 _dpk_information(rtwdev, phy, path, chanctx_idx);
2654 }
2655
2656 _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
2657
2658 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2659 if (!(kpath & BIT(path)) || reloaded[path])
2660 continue;
2661
2662 is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx);
2663 _dpk_onoff(rtwdev, path, is_fail);
2664 }
2665
2666 _dpk_bb_afe_restore(rtwdev, phy, path, kpath);
2667 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
2668
2669 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2670 if (!(kpath & BIT(path)) || reloaded[path])
2671 continue;
2672
2673 _dpk_kip_restore(rtwdev, path);
2674 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2675 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2676 if (rtwdev->is_tssi_mode[path])
2677 _dpk_tssi_pause(rtwdev, path, false);
2678 }
2679 }
2680
_dpk_bypass_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_chanctx_idx chanctx_idx)2681 static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2682 enum rtw89_chanctx_idx chanctx_idx)
2683 {
2684 struct rtw89_fem_info *fem = &rtwdev->fem;
2685 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2686
2687 if (fem->epa_2g && chan->band_type == RTW89_BAND_2G) {
2688 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2689 "[DPK] Skip DPK due to 2G_ext_PA exist!!\n");
2690 return true;
2691 } else if (fem->epa_5g && chan->band_type == RTW89_BAND_5G) {
2692 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2693 "[DPK] Skip DPK due to 5G_ext_PA exist!!\n");
2694 return true;
2695 }
2696
2697 return false;
2698 }
2699
_dpk_force_bypass(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)2700 static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
2701 {
2702 u8 path, kpath;
2703
2704 kpath = _kpath(rtwdev, phy);
2705
2706 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2707 if (kpath & BIT(path))
2708 _dpk_onoff(rtwdev, path, true);
2709 }
2710 }
2711
_dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool force,enum rtw89_chanctx_idx chanctx_idx)2712 static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2713 bool force, enum rtw89_chanctx_idx chanctx_idx)
2714 {
2715 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2716 "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n",
2717 RTW8852A_DPK_VER, rtwdev->hal.cv,
2718 RTW8852A_RF_REL_VERSION);
2719
2720 if (_dpk_bypass_check(rtwdev, phy, chanctx_idx))
2721 _dpk_force_bypass(rtwdev, phy);
2722 else
2723 _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy),
2724 chanctx_idx);
2725 }
2726
_dpk_onoff(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool off)2727 static void _dpk_onoff(struct rtw89_dev *rtwdev,
2728 enum rtw89_rf_path path, bool off)
2729 {
2730 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2731 u8 val, kidx = dpk->cur_idx[path];
2732
2733 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
2734
2735 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2736 MASKBYTE3, 0x6 | val);
2737
2738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2739 kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
2740 }
2741
_dpk_track(struct rtw89_dev * rtwdev)2742 static void _dpk_track(struct rtw89_dev *rtwdev)
2743 {
2744 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2745 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2746 u8 path, kidx;
2747 u8 trk_idx = 0, txagc_rf = 0;
2748 s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0;
2749 u16 pwsf[2];
2750 u8 cur_ther;
2751 s8 delta_ther[2] = {0};
2752
2753 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2754 kidx = dpk->cur_idx[path];
2755
2756 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2757 "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
2758 path, kidx, dpk->bp[path][kidx].ch);
2759
2760 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2761
2762 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2763 "[DPK_TRK] thermal now = %d\n", cur_ther);
2764
2765 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2766 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
2767
2768 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2769 delta_ther[path] = delta_ther[path] * 3 / 2;
2770 else
2771 delta_ther[path] = delta_ther[path] * 5 / 2;
2772
2773 txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2774 RR_MODOPT_M_TXPWR);
2775
2776 if (rtwdev->is_tssi_mode[path]) {
2777 trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
2778
2779 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2780 "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n",
2781 txagc_rf, trk_idx);
2782
2783 txagc_bb =
2784 (s8)rtw89_phy_read32_mask(rtwdev,
2785 R_TXAGC_BB + (path << 13),
2786 MASKBYTE2);
2787 txagc_bb_tp =
2788 (u8)rtw89_phy_read32_mask(rtwdev,
2789 R_TXAGC_TP + (path << 13),
2790 B_TXAGC_TP);
2791
2792 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2793 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
2794 txagc_bb_tp, txagc_bb);
2795
2796 txagc_ofst =
2797 (s8)rtw89_phy_read32_mask(rtwdev,
2798 R_TXAGC_BB + (path << 13),
2799 MASKBYTE3);
2800
2801 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2802 "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n",
2803 txagc_ofst, delta_ther[path]);
2804
2805 if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
2806 BIT(15)) == 0x1)
2807 txagc_ofst = 0;
2808
2809 if (txagc_rf != 0 && cur_ther != 0)
2810 ini_diff = txagc_ofst + delta_ther[path];
2811
2812 if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13),
2813 B_P0_TXDPD) == 0x0) {
2814 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp -
2815 txagc_bb + ini_diff +
2816 tssi_info->extra_ofst[path];
2817 pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp -
2818 txagc_bb + ini_diff +
2819 tssi_info->extra_ofst[path];
2820 } else {
2821 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff +
2822 tssi_info->extra_ofst[path];
2823 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff +
2824 tssi_info->extra_ofst[path];
2825 }
2826
2827 } else {
2828 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2829 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2830 }
2831
2832 if (rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS) == 0x0 &&
2833 txagc_rf != 0) {
2834 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2835 "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n",
2836 pwsf[0], pwsf[1]);
2837
2838 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2839 0x000001FF, pwsf[0]);
2840 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2841 0x01FF0000, pwsf[1]);
2842 }
2843 }
2844 }
2845
_tssi_rf_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2846 static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2847 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2848 {
2849 enum rtw89_band band = chan->band_type;
2850
2851 if (band == RTW89_BAND_2G)
2852 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2853 else
2854 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2855 }
2856
_tssi_set_sys(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)2857 static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2858 const struct rtw89_chan *chan)
2859 {
2860 enum rtw89_band band = chan->band_type;
2861
2862 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_sys_defs_tbl);
2863 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2864 &rtw8852a_tssi_sys_defs_2g_tbl,
2865 &rtw8852a_tssi_sys_defs_5g_tbl);
2866 }
2867
_tssi_ini_txpwr_ctrl_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2868 static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2869 enum rtw89_rf_path path,
2870 const struct rtw89_chan *chan)
2871 {
2872 enum rtw89_band band = chan->band_type;
2873
2874 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2875 &rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl,
2876 &rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl);
2877 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2878 &rtw8852a_tssi_txpwr_ctrl_bb_defs_2g_tbl,
2879 &rtw8852a_tssi_txpwr_ctrl_bb_defs_5g_tbl);
2880 }
2881
_tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2882 static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
2883 enum rtw89_phy_idx phy,
2884 enum rtw89_rf_path path)
2885 {
2886 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2887 &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl,
2888 &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl);
2889 }
2890
_tssi_set_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2891 static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2892 enum rtw89_rf_path path)
2893 {
2894 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2895 &rtw8852a_tssi_dck_defs_a_tbl,
2896 &rtw8852a_tssi_dck_defs_b_tbl);
2897 }
2898
_tssi_set_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2899 static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2900 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2901 {
2902 #define __get_val(ptr, idx) \
2903 ({ \
2904 s8 *__ptr = (ptr); \
2905 u8 __idx = (idx), __i, __v; \
2906 u32 __val = 0; \
2907 for (__i = 0; __i < 4; __i++) { \
2908 __v = (__ptr[__idx + __i]); \
2909 __val |= (__v << (8 * __i)); \
2910 } \
2911 __val; \
2912 })
2913 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2914 u8 ch = chan->channel;
2915 u8 subband = chan->subband_type;
2916 const s8 *thm_up_a = NULL;
2917 const s8 *thm_down_a = NULL;
2918 const s8 *thm_up_b = NULL;
2919 const s8 *thm_down_b = NULL;
2920 u8 thermal = 0xff;
2921 s8 thm_ofst[64] = {0};
2922 u32 tmp = 0;
2923 u8 i, j;
2924
2925 switch (subband) {
2926 default:
2927 case RTW89_CH_2G:
2928 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_p;
2929 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_n;
2930 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_p;
2931 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_n;
2932 break;
2933 case RTW89_CH_5G_BAND_1:
2934 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0];
2935 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0];
2936 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0];
2937 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0];
2938 break;
2939 case RTW89_CH_5G_BAND_3:
2940 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[1];
2941 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[1];
2942 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[1];
2943 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[1];
2944 break;
2945 case RTW89_CH_5G_BAND_4:
2946 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[2];
2947 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[2];
2948 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[2];
2949 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[2];
2950 break;
2951 }
2952
2953 if (path == RF_PATH_A) {
2954 thermal = tssi_info->thermal[RF_PATH_A];
2955
2956 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2957 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
2958
2959 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
2960 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
2961
2962 if (thermal == 0xff) {
2963 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
2964 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
2965
2966 for (i = 0; i < 64; i += 4) {
2967 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
2968
2969 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2970 "[TSSI] write 0x%x val=0x%08x\n",
2971 0x5c00 + i, 0x0);
2972 }
2973
2974 } else {
2975 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal);
2976 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
2977 thermal);
2978
2979 i = 0;
2980 for (j = 0; j < 32; j++)
2981 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
2982 -thm_down_a[i++] :
2983 -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
2984
2985 i = 1;
2986 for (j = 63; j >= 32; j--)
2987 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
2988 thm_up_a[i++] :
2989 thm_up_a[DELTA_SWINGIDX_SIZE - 1];
2990
2991 for (i = 0; i < 64; i += 4) {
2992 tmp = __get_val(thm_ofst, i);
2993 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
2994
2995 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2996 "[TSSI] write 0x%x val=0x%08x\n",
2997 0x5c00 + i, tmp);
2998 }
2999 }
3000 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
3001 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
3002
3003 } else {
3004 thermal = tssi_info->thermal[RF_PATH_B];
3005
3006 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3007 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal);
3008
3009 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0);
3010 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1);
3011
3012 if (thermal == 0xff) {
3013 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32);
3014 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32);
3015
3016 for (i = 0; i < 64; i += 4) {
3017 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0);
3018
3019 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3020 "[TSSI] write 0x%x val=0x%08x\n",
3021 0x7c00 + i, 0x0);
3022 }
3023
3024 } else {
3025 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal);
3026 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL,
3027 thermal);
3028
3029 i = 0;
3030 for (j = 0; j < 32; j++)
3031 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
3032 -thm_down_b[i++] :
3033 -thm_down_b[DELTA_SWINGIDX_SIZE - 1];
3034
3035 i = 1;
3036 for (j = 63; j >= 32; j--)
3037 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
3038 thm_up_b[i++] :
3039 thm_up_b[DELTA_SWINGIDX_SIZE - 1];
3040
3041 for (i = 0; i < 64; i += 4) {
3042 tmp = __get_val(thm_ofst, i);
3043 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp);
3044
3045 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3046 "[TSSI] write 0x%x val=0x%08x\n",
3047 0x7c00 + i, tmp);
3048 }
3049 }
3050 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1);
3051 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0);
3052 }
3053 #undef __get_val
3054 }
3055
_tssi_set_dac_gain_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3056 static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3057 enum rtw89_rf_path path)
3058 {
3059 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3060 &rtw8852a_tssi_dac_gain_tbl_defs_a_tbl,
3061 &rtw8852a_tssi_dac_gain_tbl_defs_b_tbl);
3062 }
3063
_tssi_slope_cal_org(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3064 static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3065 enum rtw89_rf_path path)
3066 {
3067 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3068 &rtw8852a_tssi_slope_cal_org_defs_a_tbl,
3069 &rtw8852a_tssi_slope_cal_org_defs_b_tbl);
3070 }
3071
_tssi_set_rf_gap_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3072 static void _tssi_set_rf_gap_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3073 enum rtw89_rf_path path)
3074 {
3075 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3076 &rtw8852a_tssi_rf_gap_tbl_defs_a_tbl,
3077 &rtw8852a_tssi_rf_gap_tbl_defs_b_tbl);
3078 }
3079
_tssi_set_slope(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3080 static void _tssi_set_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3081 enum rtw89_rf_path path)
3082 {
3083 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3084 &rtw8852a_tssi_slope_defs_a_tbl,
3085 &rtw8852a_tssi_slope_defs_b_tbl);
3086 }
3087
_tssi_set_track(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3088 static void _tssi_set_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3089 enum rtw89_rf_path path)
3090 {
3091 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3092 &rtw8852a_tssi_track_defs_a_tbl,
3093 &rtw8852a_tssi_track_defs_b_tbl);
3094 }
3095
_tssi_set_txagc_offset_mv_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)3096 static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
3097 enum rtw89_phy_idx phy,
3098 enum rtw89_rf_path path)
3099 {
3100 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3101 &rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl,
3102 &rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl);
3103 }
3104
_tssi_pak(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3105 static void _tssi_pak(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3106 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3107 {
3108 u8 subband = chan->subband_type;
3109
3110 switch (subband) {
3111 default:
3112 case RTW89_CH_2G:
3113 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3114 &rtw8852a_tssi_pak_defs_a_2g_tbl,
3115 &rtw8852a_tssi_pak_defs_b_2g_tbl);
3116 break;
3117 case RTW89_CH_5G_BAND_1:
3118 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3119 &rtw8852a_tssi_pak_defs_a_5g_1_tbl,
3120 &rtw8852a_tssi_pak_defs_b_5g_1_tbl);
3121 break;
3122 case RTW89_CH_5G_BAND_3:
3123 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3124 &rtw8852a_tssi_pak_defs_a_5g_3_tbl,
3125 &rtw8852a_tssi_pak_defs_b_5g_3_tbl);
3126 break;
3127 case RTW89_CH_5G_BAND_4:
3128 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3129 &rtw8852a_tssi_pak_defs_a_5g_4_tbl,
3130 &rtw8852a_tssi_pak_defs_b_5g_4_tbl);
3131 break;
3132 }
3133 }
3134
_tssi_enable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)3135 static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3136 {
3137 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3138 u8 i;
3139
3140 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
3141 _tssi_set_track(rtwdev, phy, i);
3142 _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i);
3143
3144 rtw89_rfk_parser_by_cond(rtwdev, i == RF_PATH_A,
3145 &rtw8852a_tssi_enable_defs_a_tbl,
3146 &rtw8852a_tssi_enable_defs_b_tbl);
3147
3148 tssi_info->base_thermal[i] =
3149 ewma_thermal_read(&rtwdev->phystat.avg_thermal[i]);
3150 rtwdev->is_tssi_mode[i] = true;
3151 }
3152 }
3153
_tssi_disable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)3154 static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3155 {
3156 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl);
3157
3158 rtwdev->is_tssi_mode[RF_PATH_A] = false;
3159 rtwdev->is_tssi_mode[RF_PATH_B] = false;
3160 }
3161
_tssi_get_cck_group(struct rtw89_dev * rtwdev,u8 ch)3162 static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
3163 {
3164 switch (ch) {
3165 case 1 ... 2:
3166 return 0;
3167 case 3 ... 5:
3168 return 1;
3169 case 6 ... 8:
3170 return 2;
3171 case 9 ... 11:
3172 return 3;
3173 case 12 ... 13:
3174 return 4;
3175 case 14:
3176 return 5;
3177 }
3178
3179 return 0;
3180 }
3181
3182 #define TSSI_EXTRA_GROUP_BIT (BIT(31))
3183 #define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
3184 #define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
3185 #define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
3186 #define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3187
_tssi_get_ofdm_group(struct rtw89_dev * rtwdev,u8 ch)3188 static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
3189 {
3190 switch (ch) {
3191 case 1 ... 2:
3192 return 0;
3193 case 3 ... 5:
3194 return 1;
3195 case 6 ... 8:
3196 return 2;
3197 case 9 ... 11:
3198 return 3;
3199 case 12 ... 14:
3200 return 4;
3201 case 36 ... 40:
3202 return 5;
3203 case 41 ... 43:
3204 return TSSI_EXTRA_GROUP(5);
3205 case 44 ... 48:
3206 return 6;
3207 case 49 ... 51:
3208 return TSSI_EXTRA_GROUP(6);
3209 case 52 ... 56:
3210 return 7;
3211 case 57 ... 59:
3212 return TSSI_EXTRA_GROUP(7);
3213 case 60 ... 64:
3214 return 8;
3215 case 100 ... 104:
3216 return 9;
3217 case 105 ... 107:
3218 return TSSI_EXTRA_GROUP(9);
3219 case 108 ... 112:
3220 return 10;
3221 case 113 ... 115:
3222 return TSSI_EXTRA_GROUP(10);
3223 case 116 ... 120:
3224 return 11;
3225 case 121 ... 123:
3226 return TSSI_EXTRA_GROUP(11);
3227 case 124 ... 128:
3228 return 12;
3229 case 129 ... 131:
3230 return TSSI_EXTRA_GROUP(12);
3231 case 132 ... 136:
3232 return 13;
3233 case 137 ... 139:
3234 return TSSI_EXTRA_GROUP(13);
3235 case 140 ... 144:
3236 return 14;
3237 case 149 ... 153:
3238 return 15;
3239 case 154 ... 156:
3240 return TSSI_EXTRA_GROUP(15);
3241 case 157 ... 161:
3242 return 16;
3243 case 162 ... 164:
3244 return TSSI_EXTRA_GROUP(16);
3245 case 165 ... 169:
3246 return 17;
3247 case 170 ... 172:
3248 return TSSI_EXTRA_GROUP(17);
3249 case 173 ... 177:
3250 return 18;
3251 }
3252
3253 return 0;
3254 }
3255
_tssi_get_trim_group(struct rtw89_dev * rtwdev,u8 ch)3256 static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
3257 {
3258 switch (ch) {
3259 case 1 ... 8:
3260 return 0;
3261 case 9 ... 14:
3262 return 1;
3263 case 36 ... 48:
3264 return 2;
3265 case 52 ... 64:
3266 return 3;
3267 case 100 ... 112:
3268 return 4;
3269 case 116 ... 128:
3270 return 5;
3271 case 132 ... 144:
3272 return 6;
3273 case 149 ... 177:
3274 return 7;
3275 }
3276
3277 return 0;
3278 }
3279
_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3280 static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3281 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3282 {
3283 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3284 u8 ch = chan->channel;
3285 u32 gidx, gidx_1st, gidx_2nd;
3286 s8 de_1st = 0;
3287 s8 de_2nd = 0;
3288 s8 val;
3289
3290 gidx = _tssi_get_ofdm_group(rtwdev, ch);
3291
3292 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3293 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3294 path, gidx);
3295
3296 if (IS_TSSI_EXTRA_GROUP(gidx)) {
3297 gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx);
3298 gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx);
3299 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3300 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3301 val = (de_1st + de_2nd) / 2;
3302
3303 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3304 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3305 path, val, de_1st, de_2nd);
3306 } else {
3307 val = tssi_info->tssi_mcs[path][gidx];
3308
3309 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3310 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3311 }
3312
3313 return val;
3314 }
3315
_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3316 static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
3317 enum rtw89_phy_idx phy,
3318 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3319 {
3320 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3321 u8 ch = chan->channel;
3322 u32 tgidx, tgidx_1st, tgidx_2nd;
3323 s8 tde_1st = 0;
3324 s8 tde_2nd = 0;
3325 s8 val;
3326
3327 tgidx = _tssi_get_trim_group(rtwdev, ch);
3328
3329 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3330 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3331 path, tgidx);
3332
3333 if (IS_TSSI_EXTRA_GROUP(tgidx)) {
3334 tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
3335 tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
3336 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3337 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3338 val = (tde_1st + tde_2nd) / 2;
3339
3340 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3341 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3342 path, val, tde_1st, tde_2nd);
3343 } else {
3344 val = tssi_info->tssi_trim[path][tgidx];
3345
3346 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3347 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3348 path, val);
3349 }
3350
3351 return val;
3352 }
3353
_tssi_set_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)3354 static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev,
3355 enum rtw89_phy_idx phy, const struct rtw89_chan *chan)
3356 {
3357 #define __DE_MASK 0x003ff000
3358 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3359 static const u32 r_cck_long[RF_PATH_NUM_8852A] = {0x5858, 0x7858};
3360 static const u32 r_cck_short[RF_PATH_NUM_8852A] = {0x5860, 0x7860};
3361 static const u32 r_mcs_20m[RF_PATH_NUM_8852A] = {0x5838, 0x7838};
3362 static const u32 r_mcs_40m[RF_PATH_NUM_8852A] = {0x5840, 0x7840};
3363 static const u32 r_mcs_80m[RF_PATH_NUM_8852A] = {0x5848, 0x7848};
3364 static const u32 r_mcs_80m_80m[RF_PATH_NUM_8852A] = {0x5850, 0x7850};
3365 static const u32 r_mcs_5m[RF_PATH_NUM_8852A] = {0x5828, 0x7828};
3366 static const u32 r_mcs_10m[RF_PATH_NUM_8852A] = {0x5830, 0x7830};
3367 u8 ch = chan->channel;
3368 u8 i, gidx;
3369 s8 ofdm_de;
3370 s8 trim_de;
3371 s32 val;
3372
3373 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
3374 phy, ch);
3375
3376 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
3377 gidx = _tssi_get_cck_group(rtwdev, ch);
3378 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3379 val = tssi_info->tssi_cck[i][gidx] + trim_de;
3380
3381 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3382 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3383 i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
3384
3385 rtw89_phy_write32_mask(rtwdev, r_cck_long[i], __DE_MASK, val);
3386 rtw89_phy_write32_mask(rtwdev, r_cck_short[i], __DE_MASK, val);
3387
3388 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3389 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
3390 r_cck_long[i],
3391 rtw89_phy_read32_mask(rtwdev, r_cck_long[i],
3392 __DE_MASK));
3393
3394 ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i, chan);
3395 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3396 val = ofdm_de + trim_de;
3397
3398 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3399 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3400 i, ofdm_de, trim_de);
3401
3402 rtw89_phy_write32_mask(rtwdev, r_mcs_20m[i], __DE_MASK, val);
3403 rtw89_phy_write32_mask(rtwdev, r_mcs_40m[i], __DE_MASK, val);
3404 rtw89_phy_write32_mask(rtwdev, r_mcs_80m[i], __DE_MASK, val);
3405 rtw89_phy_write32_mask(rtwdev, r_mcs_80m_80m[i], __DE_MASK, val);
3406 rtw89_phy_write32_mask(rtwdev, r_mcs_5m[i], __DE_MASK, val);
3407 rtw89_phy_write32_mask(rtwdev, r_mcs_10m[i], __DE_MASK, val);
3408
3409 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3410 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
3411 r_mcs_20m[i],
3412 rtw89_phy_read32_mask(rtwdev, r_mcs_20m[i],
3413 __DE_MASK));
3414 }
3415 #undef __DE_MASK
3416 }
3417
_tssi_track(struct rtw89_dev * rtwdev)3418 static void _tssi_track(struct rtw89_dev *rtwdev)
3419 {
3420 static const u32 tx_gain_scale_table[] = {
3421 0x400, 0x40e, 0x41d, 0x427, 0x43c, 0x44c, 0x45c, 0x46c,
3422 0x400, 0x39d, 0x3ab, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f1
3423 };
3424 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3425 u8 path;
3426 u8 cur_ther;
3427 s32 delta_ther = 0, gain_offset_int, gain_offset_float;
3428 s8 gain_offset;
3429
3430 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] %s:\n",
3431 __func__);
3432
3433 if (!rtwdev->is_tssi_mode[RF_PATH_A])
3434 return;
3435 if (!rtwdev->is_tssi_mode[RF_PATH_B])
3436 return;
3437
3438 for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) {
3439 if (!tssi_info->tssi_tracking_check[path]) {
3440 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] return!!!\n");
3441 continue;
3442 }
3443
3444 cur_ther = (u8)rtw89_phy_read32_mask(rtwdev,
3445 R_TSSI_THER + (path << 13),
3446 B_TSSI_THER);
3447
3448 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0)
3449 continue;
3450
3451 delta_ther = cur_ther - tssi_info->base_thermal[path];
3452
3453 gain_offset = (s8)delta_ther * 15 / 10;
3454
3455 tssi_info->extra_ofst[path] = gain_offset;
3456
3457 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3458 "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n",
3459 tssi_info->base_thermal[path], gain_offset, path);
3460
3461 gain_offset_int = gain_offset >> 3;
3462 gain_offset_float = gain_offset & 7;
3463
3464 if (gain_offset_int > 15)
3465 gain_offset_int = 15;
3466 else if (gain_offset_int < -16)
3467 gain_offset_int = -16;
3468
3469 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13),
3470 B_DPD_OFT_EN, 0x1);
3471
3472 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13),
3473 B_TXGAIN_SCALE_EN, 0x1);
3474
3475 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13),
3476 B_DPD_OFT_ADDR, gain_offset_int);
3477
3478 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13),
3479 B_TXGAIN_SCALE_OFT,
3480 tx_gain_scale_table[gain_offset_float]);
3481 }
3482 }
3483
_tssi_high_power(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)3484 static void _tssi_high_power(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3485 const struct rtw89_chan *chan)
3486 {
3487 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3488 u8 ch = chan->channel, ch_tmp;
3489 u8 bw = chan->band_width;
3490 u8 band = chan->band_type;
3491 u8 subband = chan->subband_type;
3492 s8 power;
3493 s32 xdbm;
3494
3495 if (bw == RTW89_CHANNEL_WIDTH_40)
3496 ch_tmp = ch - 2;
3497 else if (bw == RTW89_CHANNEL_WIDTH_80)
3498 ch_tmp = ch - 6;
3499 else
3500 ch_tmp = ch;
3501
3502 power = rtw89_phy_read_txpwr_limit(rtwdev, band, bw, RTW89_1TX,
3503 RTW89_RS_MCS, RTW89_NONBF, ch_tmp);
3504
3505 xdbm = power * 100 / 4;
3506
3507 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d xdbm=%d\n",
3508 __func__, phy, xdbm);
3509
3510 if (xdbm > 1800 && subband == RTW89_CH_2G) {
3511 tssi_info->tssi_tracking_check[RF_PATH_A] = true;
3512 tssi_info->tssi_tracking_check[RF_PATH_B] = true;
3513 } else {
3514 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_tracking_defs_tbl);
3515 tssi_info->extra_ofst[RF_PATH_A] = 0;
3516 tssi_info->extra_ofst[RF_PATH_B] = 0;
3517 tssi_info->tssi_tracking_check[RF_PATH_A] = false;
3518 tssi_info->tssi_tracking_check[RF_PATH_B] = false;
3519 }
3520 }
3521
_tssi_hw_tx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path,s16 pwr_dbm,u8 enable,const struct rtw89_chan * chan)3522 static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3523 u8 path, s16 pwr_dbm, u8 enable, const struct rtw89_chan *chan)
3524 {
3525 rtw8852a_bb_set_plcp_tx(rtwdev);
3526 rtw8852a_bb_cfg_tx_path(rtwdev, path);
3527 rtw8852a_bb_set_power(rtwdev, pwr_dbm, phy);
3528 rtw8852a_bb_set_pmac_pkt_tx(rtwdev, enable, 20, 5000, 0, phy, chan);
3529 }
3530
_tssi_pre_tx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_chanctx_idx chanctx_idx)3531 static void _tssi_pre_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3532 enum rtw89_chanctx_idx chanctx_idx)
3533 {
3534 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3535 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3536 const struct rtw89_chip_info *mac_reg = rtwdev->chip;
3537 u8 ch = chan->channel, ch_tmp;
3538 u8 bw = chan->band_width;
3539 u8 band = chan->band_type;
3540 u32 tx_en;
3541 u8 phy_map = rtw89_btc_phymap(rtwdev, phy, 0, chanctx_idx);
3542 s8 power;
3543 s16 xdbm;
3544 u32 i, tx_counter = 0;
3545
3546 if (bw == RTW89_CHANNEL_WIDTH_40)
3547 ch_tmp = ch - 2;
3548 else if (bw == RTW89_CHANNEL_WIDTH_80)
3549 ch_tmp = ch - 6;
3550 else
3551 ch_tmp = ch;
3552
3553 power = rtw89_phy_read_txpwr_limit(rtwdev, band, RTW89_CHANNEL_WIDTH_20,
3554 RTW89_1TX, RTW89_RS_OFDM,
3555 RTW89_NONBF, ch_tmp);
3556
3557 xdbm = (power * 100) >> mac_reg->txpwr_factor_mac;
3558
3559 if (xdbm > 1800)
3560 xdbm = 68;
3561 else
3562 xdbm = power * 2;
3563
3564 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3565 "[TSSI] %s: phy=%d org_power=%d xdbm=%d\n",
3566 __func__, phy, power, xdbm);
3567
3568 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
3569 rtw89_chip_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL);
3570 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy));
3571 tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
3572
3573 _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, true, chan);
3574 mdelay(15);
3575 _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, false, chan);
3576
3577 tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD) -
3578 tx_counter;
3579
3580 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0xc000 &&
3581 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0x0) {
3582 for (i = 0; i < 6; i++) {
3583 tssi_info->default_txagc_offset[RF_PATH_A] =
3584 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB,
3585 MASKBYTE3);
3586
3587 if (tssi_info->default_txagc_offset[RF_PATH_A] != 0x0)
3588 break;
3589 }
3590 }
3591
3592 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0xc000 &&
3593 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0x0) {
3594 for (i = 0; i < 6; i++) {
3595 tssi_info->default_txagc_offset[RF_PATH_B] =
3596 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1,
3597 MASKBYTE3);
3598
3599 if (tssi_info->default_txagc_offset[RF_PATH_B] != 0x0)
3600 break;
3601 }
3602 }
3603
3604 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3605 "[TSSI] %s: tx counter=%d\n",
3606 __func__, tx_counter);
3607
3608 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3609 "[TSSI] Backup R_TXAGC_BB=0x%x R_TXAGC_BB_S1=0x%x\n",
3610 tssi_info->default_txagc_offset[RF_PATH_A],
3611 tssi_info->default_txagc_offset[RF_PATH_B]);
3612
3613 rtw8852a_bb_tx_mode_switch(rtwdev, phy, 0);
3614
3615 rtw89_chip_resume_sch_tx(rtwdev, phy, tx_en);
3616 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
3617 }
3618
rtw8852a_rck(struct rtw89_dev * rtwdev)3619 void rtw8852a_rck(struct rtw89_dev *rtwdev)
3620 {
3621 u8 path;
3622
3623 for (path = 0; path < 2; path++)
3624 _rck(rtwdev, path);
3625 }
3626
rtw8852a_dack(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx chanctx_idx)3627 void rtw8852a_dack(struct rtw89_dev *rtwdev,
3628 enum rtw89_chanctx_idx chanctx_idx)
3629 {
3630 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0, chanctx_idx);
3631
3632 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START);
3633 _dac_cal(rtwdev, false, chanctx_idx);
3634 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);
3635 }
3636
rtw8852a_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3637 void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3638 enum rtw89_chanctx_idx chanctx_idx)
3639 {
3640 u32 tx_en;
3641 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3642
3643 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
3644 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3645 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3646
3647 _iqk_init(rtwdev);
3648 if (rtwdev->dbcc_en)
3649 _iqk_dbcc(rtwdev, phy_idx, chanctx_idx);
3650 else
3651 _iqk(rtwdev, phy_idx, false, chanctx_idx);
3652
3653 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3654 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
3655 }
3656
rtw8852a_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool is_afe,enum rtw89_chanctx_idx chanctx_idx)3657 void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3658 bool is_afe, enum rtw89_chanctx_idx chanctx_idx)
3659 {
3660 u32 tx_en;
3661 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3662
3663 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
3664 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3665 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3666
3667 _rx_dck(rtwdev, phy_idx, is_afe, chanctx_idx);
3668
3669 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3670 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
3671 }
3672
rtw8852a_dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3673 void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3674 enum rtw89_chanctx_idx chanctx_idx)
3675 {
3676 u32 tx_en;
3677 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3678
3679 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
3680 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3681 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3682
3683 rtwdev->dpk.is_dpk_enable = true;
3684 rtwdev->dpk.is_dpk_reload_en = false;
3685 _dpk(rtwdev, phy_idx, false, chanctx_idx);
3686
3687 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3688 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
3689 }
3690
rtw8852a_dpk_track(struct rtw89_dev * rtwdev)3691 void rtw8852a_dpk_track(struct rtw89_dev *rtwdev)
3692 {
3693 _dpk_track(rtwdev);
3694 }
3695
rtw8852a_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_chanctx_idx chanctx_idx)3696 void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3697 enum rtw89_chanctx_idx chanctx_idx)
3698 {
3699 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3700 u8 i;
3701
3702 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n",
3703 __func__, phy);
3704
3705 _tssi_disable(rtwdev, phy);
3706
3707 for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) {
3708 _tssi_rf_setting(rtwdev, phy, i, chan);
3709 _tssi_set_sys(rtwdev, phy, chan);
3710 _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i, chan);
3711 _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
3712 _tssi_set_dck(rtwdev, phy, i);
3713 _tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3714 _tssi_set_dac_gain_tbl(rtwdev, phy, i);
3715 _tssi_slope_cal_org(rtwdev, phy, i);
3716 _tssi_set_rf_gap_tbl(rtwdev, phy, i);
3717 _tssi_set_slope(rtwdev, phy, i);
3718 _tssi_pak(rtwdev, phy, i, chan);
3719 }
3720
3721 _tssi_enable(rtwdev, phy);
3722 _tssi_set_efuse_to_de(rtwdev, phy, chan);
3723 _tssi_high_power(rtwdev, phy, chan);
3724 _tssi_pre_tx(rtwdev, phy, chanctx_idx);
3725 }
3726
rtw8852a_tssi_scan(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)3727 void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3728 const struct rtw89_chan *chan)
3729 {
3730 u8 i;
3731
3732 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n",
3733 __func__, phy);
3734
3735 if (!rtwdev->is_tssi_mode[RF_PATH_A])
3736 return;
3737 if (!rtwdev->is_tssi_mode[RF_PATH_B])
3738 return;
3739
3740 _tssi_disable(rtwdev, phy);
3741
3742 for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) {
3743 _tssi_rf_setting(rtwdev, phy, i, chan);
3744 _tssi_set_sys(rtwdev, phy, chan);
3745 _tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3746 _tssi_pak(rtwdev, phy, i, chan);
3747 }
3748
3749 _tssi_enable(rtwdev, phy);
3750 _tssi_set_efuse_to_de(rtwdev, phy, chan);
3751 }
3752
rtw8852a_tssi_track(struct rtw89_dev * rtwdev)3753 void rtw8852a_tssi_track(struct rtw89_dev *rtwdev)
3754 {
3755 _tssi_track(rtwdev);
3756 }
3757
3758 static
_rtw8852a_tssi_avg_scan(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)3759 void _rtw8852a_tssi_avg_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3760 {
3761 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3762 return;
3763
3764 /* disable */
3765 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl);
3766
3767 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x0);
3768 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x0);
3769
3770 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x0);
3771 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x0);
3772
3773 /* enable */
3774 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_enable_defs_ab_tbl);
3775 }
3776
3777 static
_rtw8852a_tssi_set_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)3778 void _rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3779 {
3780 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3781 return;
3782
3783 /* disable */
3784 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl);
3785
3786 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x4);
3787 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2);
3788
3789 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x4);
3790 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2);
3791
3792 /* enable */
3793 rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_enable_defs_ab_tbl);
3794 }
3795
rtw8852a_tssi_set_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool enable)3796 static void rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev,
3797 enum rtw89_phy_idx phy, bool enable)
3798 {
3799 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3800 return;
3801
3802 if (enable) {
3803 /* SCAN_START */
3804 _rtw8852a_tssi_avg_scan(rtwdev, phy);
3805 } else {
3806 /* SCAN_END */
3807 _rtw8852a_tssi_set_avg(rtwdev, phy);
3808 }
3809 }
3810
rtw8852a_tssi_default_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool enable)3811 static void rtw8852a_tssi_default_txagc(struct rtw89_dev *rtwdev,
3812 enum rtw89_phy_idx phy, bool enable)
3813 {
3814 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3815 u8 i;
3816
3817 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3818 return;
3819
3820 if (enable) {
3821 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0xc000 &&
3822 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0x0) {
3823 for (i = 0; i < 6; i++) {
3824 tssi_info->default_txagc_offset[RF_PATH_A] =
3825 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB,
3826 B_TXAGC_BB);
3827 if (tssi_info->default_txagc_offset[RF_PATH_A])
3828 break;
3829 }
3830 }
3831
3832 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0xc000 &&
3833 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0x0) {
3834 for (i = 0; i < 6; i++) {
3835 tssi_info->default_txagc_offset[RF_PATH_B] =
3836 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1,
3837 B_TXAGC_BB_S1);
3838 if (tssi_info->default_txagc_offset[RF_PATH_B])
3839 break;
3840 }
3841 }
3842 } else {
3843 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT,
3844 tssi_info->default_txagc_offset[RF_PATH_A]);
3845 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT,
3846 tssi_info->default_txagc_offset[RF_PATH_B]);
3847
3848 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
3849 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
3850
3851 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0);
3852 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1);
3853 }
3854 }
3855
rtw8852a_wifi_scan_notify(struct rtw89_dev * rtwdev,bool scan_start,enum rtw89_phy_idx phy_idx)3856 void rtw8852a_wifi_scan_notify(struct rtw89_dev *rtwdev,
3857 bool scan_start, enum rtw89_phy_idx phy_idx)
3858 {
3859 if (scan_start) {
3860 rtw8852a_tssi_default_txagc(rtwdev, phy_idx, true);
3861 rtw8852a_tssi_set_avg(rtwdev, phy_idx, true);
3862 } else {
3863 rtw8852a_tssi_default_txagc(rtwdev, phy_idx, false);
3864 rtw8852a_tssi_set_avg(rtwdev, phy_idx, false);
3865 }
3866 }
3867