1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_MAX_MAC_ID_NUM 32 21 #define RTW_MAX_SEC_CAM_NUM 32 22 #define MAX_PG_CAM_BACKUP_NUM 8 23 24 #define RTW_SCAN_MAX_SSIDS 4 25 26 #define RTW_MAX_PATTERN_NUM 12 27 #define RTW_MAX_PATTERN_MASK_SIZE 16 28 #define RTW_MAX_PATTERN_SIZE 128 29 30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 31 32 #define RFREG_MASK 0xfffff 33 #define INV_RF_DATA 0xffffffff 34 #define TX_PAGE_SIZE_SHIFT 7 35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 36 37 #define RTW_CHANNEL_WIDTH_MAX 3 38 #define RTW_RF_PATH_MAX 4 39 #define HW_FEATURE_LEN 13 40 41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 42 43 extern bool rtw_bf_support; 44 extern bool rtw_disable_lps_deep_mode; 45 extern unsigned int rtw_debug_mask; 46 extern bool rtw_edcca_enabled; 47 extern const struct ieee80211_ops rtw_ops; 48 49 #define RTW_MAX_CHANNEL_NUM_2G 14 50 #define RTW_MAX_CHANNEL_NUM_5G 49 51 52 struct rtw_dev; 53 struct rtw_debugfs; 54 55 enum rtw_hci_type { 56 RTW_HCI_TYPE_PCIE, 57 RTW_HCI_TYPE_USB, 58 RTW_HCI_TYPE_SDIO, 59 60 RTW_HCI_TYPE_UNDEFINE, 61 }; 62 63 struct rtw_hci { 64 struct rtw_hci_ops *ops; 65 enum rtw_hci_type type; 66 67 u32 rpwm_addr; 68 u32 cpwm_addr; 69 70 u8 bulkout_num; 71 }; 72 73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 77 78 #define IS_CH_5G_BAND_MID(channel) \ 79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 80 81 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 82 #define IS_CH_5G_BAND(channel) \ 83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 85 86 enum rtw_supported_band { 87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 90 }; 91 92 /* now, support up to 80M bw */ 93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 94 95 enum rtw_bandwidth { 96 RTW_CHANNEL_WIDTH_20 = 0, 97 RTW_CHANNEL_WIDTH_40 = 1, 98 RTW_CHANNEL_WIDTH_80 = 2, 99 RTW_CHANNEL_WIDTH_160 = 3, 100 RTW_CHANNEL_WIDTH_80_80 = 4, 101 RTW_CHANNEL_WIDTH_5 = 5, 102 RTW_CHANNEL_WIDTH_10 = 6, 103 }; 104 105 enum rtw_sc_offset { 106 RTW_SC_DONT_CARE = 0, 107 RTW_SC_20_UPPER = 1, 108 RTW_SC_20_LOWER = 2, 109 RTW_SC_20_UPMOST = 3, 110 RTW_SC_20_LOWEST = 4, 111 RTW_SC_40_UPPER = 9, 112 RTW_SC_40_LOWER = 10, 113 }; 114 115 enum rtw_net_type { 116 RTW_NET_NO_LINK = 0, 117 RTW_NET_AD_HOC = 1, 118 RTW_NET_MGD_LINKED = 2, 119 RTW_NET_AP_MODE = 3, 120 }; 121 122 enum rtw_rf_type { 123 RF_1T1R = 0, 124 RF_1T2R = 1, 125 RF_2T2R = 2, 126 RF_2T3R = 3, 127 RF_2T4R = 4, 128 RF_3T3R = 5, 129 RF_3T4R = 6, 130 RF_4T4R = 7, 131 RF_TYPE_MAX, 132 }; 133 134 enum rtw_rf_path { 135 RF_PATH_A = 0, 136 RF_PATH_B = 1, 137 RF_PATH_C = 2, 138 RF_PATH_D = 3, 139 }; 140 141 enum rtw_bb_path { 142 BB_PATH_A = BIT(0), 143 BB_PATH_B = BIT(1), 144 BB_PATH_C = BIT(2), 145 BB_PATH_D = BIT(3), 146 147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 153 154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 160 }; 161 162 enum rtw_rate_section { 163 RTW_RATE_SECTION_CCK = 0, 164 RTW_RATE_SECTION_OFDM, 165 RTW_RATE_SECTION_HT_1S, 166 RTW_RATE_SECTION_HT_2S, 167 RTW_RATE_SECTION_VHT_1S, 168 RTW_RATE_SECTION_VHT_2S, 169 170 /* keep last */ 171 RTW_RATE_SECTION_MAX, 172 }; 173 174 enum rtw_wireless_set { 175 WIRELESS_CCK = 0x00000001, 176 WIRELESS_OFDM = 0x00000002, 177 WIRELESS_HT = 0x00000004, 178 WIRELESS_VHT = 0x00000008, 179 }; 180 181 #define HT_STBC_EN BIT(0) 182 #define VHT_STBC_EN BIT(1) 183 #define HT_LDPC_EN BIT(0) 184 #define VHT_LDPC_EN BIT(1) 185 186 enum rtw_chip_type { 187 RTW_CHIP_TYPE_8822B, 188 RTW_CHIP_TYPE_8822C, 189 RTW_CHIP_TYPE_8723D, 190 RTW_CHIP_TYPE_8821C, 191 RTW_CHIP_TYPE_8703B, 192 }; 193 194 enum rtw_tx_queue_type { 195 /* the order of AC queues matters */ 196 RTW_TX_QUEUE_BK = 0x0, 197 RTW_TX_QUEUE_BE = 0x1, 198 RTW_TX_QUEUE_VI = 0x2, 199 RTW_TX_QUEUE_VO = 0x3, 200 201 RTW_TX_QUEUE_BCN = 0x4, 202 RTW_TX_QUEUE_MGMT = 0x5, 203 RTW_TX_QUEUE_HI0 = 0x6, 204 RTW_TX_QUEUE_H2C = 0x7, 205 /* keep it last */ 206 RTK_MAX_TX_QUEUE_NUM 207 }; 208 209 enum rtw_rx_queue_type { 210 RTW_RX_QUEUE_MPDU = 0x0, 211 RTW_RX_QUEUE_C2H = 0x1, 212 /* keep it last */ 213 RTK_MAX_RX_QUEUE_NUM 214 }; 215 216 enum rtw_fw_type { 217 RTW_NORMAL_FW = 0x0, 218 RTW_WOWLAN_FW = 0x1, 219 }; 220 221 enum rtw_rate_index { 222 RTW_RATEID_BGN_40M_2SS = 0, 223 RTW_RATEID_BGN_40M_1SS = 1, 224 RTW_RATEID_BGN_20M_2SS = 2, 225 RTW_RATEID_BGN_20M_1SS = 3, 226 RTW_RATEID_GN_N2SS = 4, 227 RTW_RATEID_GN_N1SS = 5, 228 RTW_RATEID_BG = 6, 229 RTW_RATEID_G = 7, 230 RTW_RATEID_B_20M = 8, 231 RTW_RATEID_ARFR0_AC_2SS = 9, 232 RTW_RATEID_ARFR1_AC_1SS = 10, 233 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 234 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 235 RTW_RATEID_ARFR4_AC_3SS = 13, 236 RTW_RATEID_ARFR5_N_3SS = 14, 237 RTW_RATEID_ARFR7_N_4SS = 15, 238 RTW_RATEID_ARFR6_AC_4SS = 16 239 }; 240 241 enum rtw_trx_desc_rate { 242 DESC_RATE1M = 0x00, 243 DESC_RATE2M = 0x01, 244 DESC_RATE5_5M = 0x02, 245 DESC_RATE11M = 0x03, 246 247 DESC_RATE6M = 0x04, 248 DESC_RATE9M = 0x05, 249 DESC_RATE12M = 0x06, 250 DESC_RATE18M = 0x07, 251 DESC_RATE24M = 0x08, 252 DESC_RATE36M = 0x09, 253 DESC_RATE48M = 0x0a, 254 DESC_RATE54M = 0x0b, 255 256 DESC_RATEMCS0 = 0x0c, 257 DESC_RATEMCS1 = 0x0d, 258 DESC_RATEMCS2 = 0x0e, 259 DESC_RATEMCS3 = 0x0f, 260 DESC_RATEMCS4 = 0x10, 261 DESC_RATEMCS5 = 0x11, 262 DESC_RATEMCS6 = 0x12, 263 DESC_RATEMCS7 = 0x13, 264 DESC_RATEMCS8 = 0x14, 265 DESC_RATEMCS9 = 0x15, 266 DESC_RATEMCS10 = 0x16, 267 DESC_RATEMCS11 = 0x17, 268 DESC_RATEMCS12 = 0x18, 269 DESC_RATEMCS13 = 0x19, 270 DESC_RATEMCS14 = 0x1a, 271 DESC_RATEMCS15 = 0x1b, 272 DESC_RATEMCS16 = 0x1c, 273 DESC_RATEMCS17 = 0x1d, 274 DESC_RATEMCS18 = 0x1e, 275 DESC_RATEMCS19 = 0x1f, 276 DESC_RATEMCS20 = 0x20, 277 DESC_RATEMCS21 = 0x21, 278 DESC_RATEMCS22 = 0x22, 279 DESC_RATEMCS23 = 0x23, 280 DESC_RATEMCS24 = 0x24, 281 DESC_RATEMCS25 = 0x25, 282 DESC_RATEMCS26 = 0x26, 283 DESC_RATEMCS27 = 0x27, 284 DESC_RATEMCS28 = 0x28, 285 DESC_RATEMCS29 = 0x29, 286 DESC_RATEMCS30 = 0x2a, 287 DESC_RATEMCS31 = 0x2b, 288 289 DESC_RATEVHT1SS_MCS0 = 0x2c, 290 DESC_RATEVHT1SS_MCS1 = 0x2d, 291 DESC_RATEVHT1SS_MCS2 = 0x2e, 292 DESC_RATEVHT1SS_MCS3 = 0x2f, 293 DESC_RATEVHT1SS_MCS4 = 0x30, 294 DESC_RATEVHT1SS_MCS5 = 0x31, 295 DESC_RATEVHT1SS_MCS6 = 0x32, 296 DESC_RATEVHT1SS_MCS7 = 0x33, 297 DESC_RATEVHT1SS_MCS8 = 0x34, 298 DESC_RATEVHT1SS_MCS9 = 0x35, 299 300 DESC_RATEVHT2SS_MCS0 = 0x36, 301 DESC_RATEVHT2SS_MCS1 = 0x37, 302 DESC_RATEVHT2SS_MCS2 = 0x38, 303 DESC_RATEVHT2SS_MCS3 = 0x39, 304 DESC_RATEVHT2SS_MCS4 = 0x3a, 305 DESC_RATEVHT2SS_MCS5 = 0x3b, 306 DESC_RATEVHT2SS_MCS6 = 0x3c, 307 DESC_RATEVHT2SS_MCS7 = 0x3d, 308 DESC_RATEVHT2SS_MCS8 = 0x3e, 309 DESC_RATEVHT2SS_MCS9 = 0x3f, 310 311 DESC_RATEVHT3SS_MCS0 = 0x40, 312 DESC_RATEVHT3SS_MCS1 = 0x41, 313 DESC_RATEVHT3SS_MCS2 = 0x42, 314 DESC_RATEVHT3SS_MCS3 = 0x43, 315 DESC_RATEVHT3SS_MCS4 = 0x44, 316 DESC_RATEVHT3SS_MCS5 = 0x45, 317 DESC_RATEVHT3SS_MCS6 = 0x46, 318 DESC_RATEVHT3SS_MCS7 = 0x47, 319 DESC_RATEVHT3SS_MCS8 = 0x48, 320 DESC_RATEVHT3SS_MCS9 = 0x49, 321 322 DESC_RATEVHT4SS_MCS0 = 0x4a, 323 DESC_RATEVHT4SS_MCS1 = 0x4b, 324 DESC_RATEVHT4SS_MCS2 = 0x4c, 325 DESC_RATEVHT4SS_MCS3 = 0x4d, 326 DESC_RATEVHT4SS_MCS4 = 0x4e, 327 DESC_RATEVHT4SS_MCS5 = 0x4f, 328 DESC_RATEVHT4SS_MCS6 = 0x50, 329 DESC_RATEVHT4SS_MCS7 = 0x51, 330 DESC_RATEVHT4SS_MCS8 = 0x52, 331 DESC_RATEVHT4SS_MCS9 = 0x53, 332 333 DESC_RATE_MAX, 334 }; 335 336 enum rtw_regulatory_domains { 337 RTW_REGD_FCC = 0, 338 RTW_REGD_MKK = 1, 339 RTW_REGD_ETSI = 2, 340 RTW_REGD_IC = 3, 341 RTW_REGD_KCC = 4, 342 RTW_REGD_ACMA = 5, 343 RTW_REGD_CHILE = 6, 344 RTW_REGD_UKRAINE = 7, 345 RTW_REGD_MEXICO = 8, 346 RTW_REGD_CN = 9, 347 RTW_REGD_QATAR = 10, 348 RTW_REGD_UK = 11, 349 350 RTW_REGD_WW, 351 RTW_REGD_MAX 352 }; 353 354 enum rtw_txq_flags { 355 RTW_TXQ_AMPDU, 356 RTW_TXQ_BLOCK_BA, 357 }; 358 359 enum rtw_flags { 360 RTW_FLAG_RUNNING, 361 RTW_FLAG_FW_RUNNING, 362 RTW_FLAG_SCANNING, 363 RTW_FLAG_POWERON, 364 RTW_FLAG_LEISURE_PS, 365 RTW_FLAG_LEISURE_PS_DEEP, 366 RTW_FLAG_DIG_DISABLE, 367 RTW_FLAG_BUSY_TRAFFIC, 368 RTW_FLAG_WOWLAN, 369 RTW_FLAG_RESTARTING, 370 RTW_FLAG_RESTART_TRIGGERING, 371 RTW_FLAG_FORCE_LOWEST_RATE, 372 373 NUM_OF_RTW_FLAGS, 374 }; 375 376 enum rtw_evm { 377 RTW_EVM_OFDM = 0, 378 RTW_EVM_1SS, 379 RTW_EVM_2SS_A, 380 RTW_EVM_2SS_B, 381 /* keep it last */ 382 RTW_EVM_NUM 383 }; 384 385 enum rtw_snr { 386 RTW_SNR_OFDM_A = 0, 387 RTW_SNR_OFDM_B, 388 RTW_SNR_OFDM_C, 389 RTW_SNR_OFDM_D, 390 RTW_SNR_1SS_A, 391 RTW_SNR_1SS_B, 392 RTW_SNR_1SS_C, 393 RTW_SNR_1SS_D, 394 RTW_SNR_2SS_A, 395 RTW_SNR_2SS_B, 396 RTW_SNR_2SS_C, 397 RTW_SNR_2SS_D, 398 /* keep it last */ 399 RTW_SNR_NUM 400 }; 401 402 enum rtw_port { 403 RTW_PORT_0 = 0, 404 RTW_PORT_1 = 1, 405 RTW_PORT_2 = 2, 406 RTW_PORT_3 = 3, 407 RTW_PORT_4 = 4, 408 RTW_PORT_NUM 409 }; 410 411 enum rtw_wow_flags { 412 RTW_WOW_FLAG_EN_MAGIC_PKT, 413 RTW_WOW_FLAG_EN_REKEY_PKT, 414 RTW_WOW_FLAG_EN_DISCONNECT, 415 416 /* keep it last */ 417 RTW_WOW_FLAG_MAX, 418 }; 419 420 /* the power index is represented by differences, which cck-1s & ht40-1s are 421 * the base values, so for 1s's differences, there are only ht20 & ofdm 422 */ 423 struct rtw_2g_1s_pwr_idx_diff { 424 #ifdef __LITTLE_ENDIAN 425 s8 ofdm:4; 426 s8 bw20:4; 427 #else 428 s8 bw20:4; 429 s8 ofdm:4; 430 #endif 431 } __packed; 432 433 struct rtw_2g_ns_pwr_idx_diff { 434 #ifdef __LITTLE_ENDIAN 435 s8 bw20:4; 436 s8 bw40:4; 437 s8 cck:4; 438 s8 ofdm:4; 439 #else 440 s8 ofdm:4; 441 s8 cck:4; 442 s8 bw40:4; 443 s8 bw20:4; 444 #endif 445 } __packed; 446 447 struct rtw_2g_txpwr_idx { 448 u8 cck_base[6]; 449 u8 bw40_base[5]; 450 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 451 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 452 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 453 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 454 }; 455 456 struct rtw_5g_ht_1s_pwr_idx_diff { 457 #ifdef __LITTLE_ENDIAN 458 s8 ofdm:4; 459 s8 bw20:4; 460 #else 461 s8 bw20:4; 462 s8 ofdm:4; 463 #endif 464 } __packed; 465 466 struct rtw_5g_ht_ns_pwr_idx_diff { 467 #ifdef __LITTLE_ENDIAN 468 s8 bw20:4; 469 s8 bw40:4; 470 #else 471 s8 bw40:4; 472 s8 bw20:4; 473 #endif 474 } __packed; 475 476 struct rtw_5g_ofdm_ns_pwr_idx_diff { 477 #ifdef __LITTLE_ENDIAN 478 s8 ofdm_3s:4; 479 s8 ofdm_2s:4; 480 s8 ofdm_4s:4; 481 s8 res:4; 482 #else 483 s8 res:4; 484 s8 ofdm_4s:4; 485 s8 ofdm_2s:4; 486 s8 ofdm_3s:4; 487 #endif 488 } __packed; 489 490 struct rtw_5g_vht_ns_pwr_idx_diff { 491 #ifdef __LITTLE_ENDIAN 492 s8 bw160:4; 493 s8 bw80:4; 494 #else 495 s8 bw80:4; 496 s8 bw160:4; 497 #endif 498 } __packed; 499 500 struct rtw_5g_txpwr_idx { 501 u8 bw40_base[14]; 502 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 503 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 504 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 505 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 506 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 507 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 508 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 509 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 510 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 511 }; 512 513 struct rtw_txpwr_idx { 514 struct rtw_2g_txpwr_idx pwr_idx_2g; 515 struct rtw_5g_txpwr_idx pwr_idx_5g; 516 }; 517 518 struct rtw_channel_params { 519 u8 center_chan; 520 u8 primary_chan; 521 u8 bandwidth; 522 }; 523 524 struct rtw_hw_reg { 525 u32 addr; 526 u32 mask; 527 }; 528 529 struct rtw_hw_reg_desc { 530 u32 addr; 531 u32 mask; 532 const char *desc; 533 }; 534 535 struct rtw_ltecoex_addr { 536 u32 ctrl; 537 u32 wdata; 538 u32 rdata; 539 }; 540 541 struct rtw_reg_domain { 542 u32 addr; 543 u32 mask; 544 #define RTW_REG_DOMAIN_MAC32 0 545 #define RTW_REG_DOMAIN_MAC16 1 546 #define RTW_REG_DOMAIN_MAC8 2 547 #define RTW_REG_DOMAIN_RF_A 3 548 #define RTW_REG_DOMAIN_RF_B 4 549 #define RTW_REG_DOMAIN_NL 0xFF 550 u8 domain; 551 }; 552 553 struct rtw_rf_sipi_addr { 554 u32 hssi_1; 555 u32 hssi_2; 556 u32 lssi_read; 557 u32 lssi_read_pi; 558 }; 559 560 struct rtw_hw_reg_offset { 561 struct rtw_hw_reg hw_reg; 562 u8 offset; 563 }; 564 565 struct rtw_backup_info { 566 u8 len; 567 u32 reg; 568 u32 val; 569 }; 570 571 enum rtw_vif_port_set { 572 PORT_SET_MAC_ADDR = BIT(0), 573 PORT_SET_BSSID = BIT(1), 574 PORT_SET_NET_TYPE = BIT(2), 575 PORT_SET_AID = BIT(3), 576 PORT_SET_BCN_CTRL = BIT(4), 577 }; 578 579 struct rtw_vif_port { 580 struct rtw_hw_reg mac_addr; 581 struct rtw_hw_reg bssid; 582 struct rtw_hw_reg net_type; 583 struct rtw_hw_reg aid; 584 struct rtw_hw_reg bcn_ctrl; 585 }; 586 587 struct rtw_tx_pkt_info { 588 u32 tx_pkt_size; 589 u8 offset; 590 u8 pkt_offset; 591 u8 tim_offset; 592 u8 mac_id; 593 u8 rate_id; 594 u8 rate; 595 u8 qsel; 596 u8 bw; 597 u8 sec_type; 598 u8 sn; 599 bool ampdu_en; 600 u8 ampdu_factor; 601 u8 ampdu_density; 602 u16 seq; 603 bool stbc; 604 bool ldpc; 605 bool dis_rate_fallback; 606 bool bmc; 607 bool use_rate; 608 bool ls; 609 bool fs; 610 bool short_gi; 611 bool report; 612 bool rts; 613 bool dis_qselseq; 614 bool en_hwseq; 615 u8 hw_ssn_sel; 616 bool nav_use_hdr; 617 bool bt_null; 618 }; 619 620 struct rtw_rx_pkt_stat { 621 bool phy_status; 622 bool icv_err; 623 bool crc_err; 624 bool decrypted; 625 bool is_c2h; 626 bool channel_invalid; 627 628 s32 signal_power; 629 u16 pkt_len; 630 u8 bw; 631 u8 drv_info_sz; 632 u8 shift; 633 u8 rate; 634 u8 mac_id; 635 u8 cam_id; 636 u8 ppdu_cnt; 637 u32 tsf_low; 638 s8 rx_power[RTW_RF_PATH_MAX]; 639 u8 rssi; 640 u8 rxsc; 641 s8 rx_snr[RTW_RF_PATH_MAX]; 642 u8 rx_evm[RTW_RF_PATH_MAX]; 643 s8 cfo_tail[RTW_RF_PATH_MAX]; 644 u16 freq; 645 u8 band; 646 647 struct rtw_sta_info *si; 648 struct ieee80211_vif *vif; 649 struct ieee80211_hdr *hdr; 650 }; 651 652 DECLARE_EWMA(tp, 10, 2); 653 654 struct rtw_traffic_stats { 655 /* units in bytes */ 656 u64 tx_unicast; 657 u64 rx_unicast; 658 659 /* count for packets */ 660 u64 tx_cnt; 661 u64 rx_cnt; 662 663 /* units in Mbps */ 664 u32 tx_throughput; 665 u32 rx_throughput; 666 struct ewma_tp tx_ewma_tp; 667 struct ewma_tp rx_ewma_tp; 668 }; 669 670 enum rtw_lps_mode { 671 RTW_MODE_ACTIVE = 0, 672 RTW_MODE_LPS = 1, 673 RTW_MODE_WMM_PS = 2, 674 }; 675 676 enum rtw_lps_deep_mode { 677 LPS_DEEP_MODE_NONE = 0, 678 LPS_DEEP_MODE_LCLK = 1, 679 LPS_DEEP_MODE_PG = 2, 680 }; 681 682 enum rtw_pwr_state { 683 RTW_RF_OFF = 0x0, 684 RTW_RF_ON = 0x4, 685 RTW_ALL_ON = 0xc, 686 }; 687 688 struct rtw_lps_conf { 689 enum rtw_lps_mode mode; 690 enum rtw_lps_deep_mode deep_mode; 691 enum rtw_lps_deep_mode wow_deep_mode; 692 enum rtw_pwr_state state; 693 u8 awake_interval; 694 u8 rlbm; 695 u8 smart_ps; 696 u8 port_id; 697 bool sec_cam_backup; 698 bool pattern_cam_backup; 699 }; 700 701 enum rtw_hw_key_type { 702 RTW_CAM_NONE = 0, 703 RTW_CAM_WEP40 = 1, 704 RTW_CAM_TKIP = 2, 705 RTW_CAM_AES = 4, 706 RTW_CAM_WEP104 = 5, 707 }; 708 709 struct rtw_cam_entry { 710 bool valid; 711 bool group; 712 u8 addr[ETH_ALEN]; 713 u8 hw_key_type; 714 struct ieee80211_key_conf *key; 715 }; 716 717 struct rtw_sec_desc { 718 /* search strategy */ 719 bool default_key_search; 720 721 u32 total_cam_num; 722 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 723 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 724 }; 725 726 struct rtw_tx_report { 727 /* protect the tx report queue */ 728 spinlock_t q_lock; 729 struct sk_buff_head queue; 730 atomic_t sn; 731 struct timer_list purge_timer; 732 }; 733 734 struct rtw_ra_report { 735 struct rate_info txrate; 736 u32 bit_rate; 737 u8 desc_rate; 738 }; 739 740 struct rtw_txq { 741 struct list_head list; 742 unsigned long flags; 743 }; 744 745 DECLARE_EWMA(rssi, 10, 16); 746 747 struct rtw_sta_info { 748 struct rtw_dev *rtwdev; 749 struct ieee80211_sta *sta; 750 struct ieee80211_vif *vif; 751 752 struct ewma_rssi avg_rssi; 753 u8 rssi_level; 754 755 u8 mac_id; 756 u8 rate_id; 757 enum rtw_bandwidth bw_mode; 758 enum rtw_rf_type rf_type; 759 u8 stbc_en:2; 760 u8 ldpc_en:2; 761 bool sgi_enable; 762 bool vht_enable; 763 u8 init_ra_lv; 764 u64 ra_mask; 765 766 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 767 768 struct rtw_ra_report ra_report; 769 770 bool use_cfg_mask; 771 struct cfg80211_bitrate_mask *mask; 772 773 struct work_struct rc_work; 774 }; 775 776 enum rtw_bfee_role { 777 RTW_BFEE_NONE, 778 RTW_BFEE_SU, 779 RTW_BFEE_MU 780 }; 781 782 struct rtw_bfee { 783 enum rtw_bfee_role role; 784 785 u16 p_aid; 786 u8 g_id; 787 u8 mac_addr[ETH_ALEN]; 788 u8 sound_dim; 789 790 /* SU-MIMO */ 791 u8 su_reg_index; 792 793 /* MU-MIMO */ 794 u16 aid; 795 }; 796 797 struct rtw_bf_info { 798 u8 bfer_mu_cnt; 799 u8 bfer_su_cnt; 800 DECLARE_BITMAP(bfer_su_reg_maping, 2); 801 u8 cur_csi_rpt_rate; 802 }; 803 804 struct rtw_vif { 805 enum rtw_net_type net_type; 806 u16 aid; 807 u8 mac_id; 808 u8 mac_addr[ETH_ALEN]; 809 u8 bssid[ETH_ALEN]; 810 u8 port; 811 u8 bcn_ctrl; 812 struct list_head rsvd_page_list; 813 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 814 const struct rtw_vif_port *conf; 815 struct cfg80211_scan_request *scan_req; 816 struct ieee80211_scan_ies *scan_ies; 817 818 struct rtw_traffic_stats stats; 819 820 struct rtw_bfee bfee; 821 }; 822 823 struct rtw_regulatory { 824 char alpha2[2]; 825 u8 txpwr_regd_2g; 826 u8 txpwr_regd_5g; 827 }; 828 829 enum rtw_regd_state { 830 RTW_REGD_STATE_WORLDWIDE, 831 RTW_REGD_STATE_PROGRAMMED, 832 RTW_REGD_STATE_SETTING, 833 834 RTW_REGD_STATE_NR, 835 }; 836 837 struct rtw_regd { 838 enum rtw_regd_state state; 839 const struct rtw_regulatory *regulatory; 840 enum nl80211_dfs_regions dfs_region; 841 }; 842 843 struct rtw_chip_ops { 844 int (*mac_init)(struct rtw_dev *rtwdev); 845 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 846 void (*shutdown)(struct rtw_dev *rtwdev); 847 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 848 void (*phy_set_param)(struct rtw_dev *rtwdev); 849 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 850 u8 bandwidth, u8 primary_chan_idx); 851 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 852 struct rtw_rx_pkt_stat *pkt_stat, 853 struct ieee80211_rx_status *rx_status); 854 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 855 u32 addr, u32 mask); 856 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 857 u32 addr, u32 mask, u32 data); 858 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 859 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 860 u32 size); 861 int (*set_antenna)(struct rtw_dev *rtwdev, 862 u32 antenna_tx, 863 u32 antenna_rx); 864 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 865 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 866 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 867 void (*phy_calibration)(struct rtw_dev *rtwdev); 868 void (*dpk_track)(struct rtw_dev *rtwdev); 869 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 870 void (*pwr_track)(struct rtw_dev *rtwdev); 871 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 872 struct rtw_bfee *bfee, bool enable); 873 void (*set_gid_table)(struct rtw_dev *rtwdev, 874 struct ieee80211_vif *vif, 875 struct ieee80211_bss_conf *conf); 876 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 877 u8 fixrate_en, u8 *new_rate); 878 void (*adaptivity_init)(struct rtw_dev *rtwdev); 879 void (*adaptivity)(struct rtw_dev *rtwdev); 880 void (*cfo_init)(struct rtw_dev *rtwdev); 881 void (*cfo_track)(struct rtw_dev *rtwdev); 882 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 883 enum rtw_bb_path tx_path_1ss, 884 enum rtw_bb_path tx_path_cck, 885 bool is_tx2_path); 886 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 887 u8 rx_path, bool is_tx2_path); 888 /* for USB/SDIO only */ 889 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 890 struct rtw_tx_pkt_info *pkt_info, 891 u8 *txdesc); 892 893 /* for coex */ 894 void (*coex_set_init)(struct rtw_dev *rtwdev); 895 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 896 u8 ctrl_type, u8 pos_type); 897 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 898 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 899 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 900 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 901 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 902 }; 903 904 #define RTW_PWR_POLLING_CNT 20000 905 906 #define RTW_PWR_CMD_READ 0x00 907 #define RTW_PWR_CMD_WRITE 0x01 908 #define RTW_PWR_CMD_POLLING 0x02 909 #define RTW_PWR_CMD_DELAY 0x03 910 #define RTW_PWR_CMD_END 0x04 911 912 /* define the base address of each block */ 913 #define RTW_PWR_ADDR_MAC 0x00 914 #define RTW_PWR_ADDR_USB 0x01 915 #define RTW_PWR_ADDR_PCIE 0x02 916 #define RTW_PWR_ADDR_SDIO 0x03 917 918 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 919 #define RTW_PWR_INTF_USB_MSK BIT(1) 920 #define RTW_PWR_INTF_PCI_MSK BIT(2) 921 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 922 923 #define RTW_PWR_CUT_TEST_MSK BIT(0) 924 #define RTW_PWR_CUT_A_MSK BIT(1) 925 #define RTW_PWR_CUT_B_MSK BIT(2) 926 #define RTW_PWR_CUT_C_MSK BIT(3) 927 #define RTW_PWR_CUT_D_MSK BIT(4) 928 #define RTW_PWR_CUT_E_MSK BIT(5) 929 #define RTW_PWR_CUT_F_MSK BIT(6) 930 #define RTW_PWR_CUT_G_MSK BIT(7) 931 #define RTW_PWR_CUT_ALL_MSK 0xFF 932 933 enum rtw_pwr_seq_cmd_delay_unit { 934 RTW_PWR_DELAY_US, 935 RTW_PWR_DELAY_MS, 936 }; 937 938 struct rtw_pwr_seq_cmd { 939 u16 offset; 940 u8 cut_mask; 941 u8 intf_mask; 942 u8 base:4; 943 u8 cmd:4; 944 u8 mask; 945 u8 value; 946 }; 947 948 enum rtw_chip_ver { 949 RTW_CHIP_VER_CUT_A = 0x00, 950 RTW_CHIP_VER_CUT_B = 0x01, 951 RTW_CHIP_VER_CUT_C = 0x02, 952 RTW_CHIP_VER_CUT_D = 0x03, 953 RTW_CHIP_VER_CUT_E = 0x04, 954 RTW_CHIP_VER_CUT_F = 0x05, 955 RTW_CHIP_VER_CUT_G = 0x06, 956 }; 957 958 #define RTW_INTF_PHY_PLATFORM_ALL 0 959 960 enum rtw_intf_phy_cut { 961 RTW_INTF_PHY_CUT_A = BIT(0), 962 RTW_INTF_PHY_CUT_B = BIT(1), 963 RTW_INTF_PHY_CUT_C = BIT(2), 964 RTW_INTF_PHY_CUT_D = BIT(3), 965 RTW_INTF_PHY_CUT_E = BIT(4), 966 RTW_INTF_PHY_CUT_F = BIT(5), 967 RTW_INTF_PHY_CUT_G = BIT(6), 968 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 969 }; 970 971 enum rtw_ip_sel { 972 RTW_IP_SEL_PHY = 0, 973 RTW_IP_SEL_MAC = 1, 974 RTW_IP_SEL_DBI = 2, 975 976 RTW_IP_SEL_UNDEF = 0xFFFF 977 }; 978 979 enum rtw_pq_map_id { 980 RTW_PQ_MAP_VO = 0x0, 981 RTW_PQ_MAP_VI = 0x1, 982 RTW_PQ_MAP_BE = 0x2, 983 RTW_PQ_MAP_BK = 0x3, 984 RTW_PQ_MAP_MG = 0x4, 985 RTW_PQ_MAP_HI = 0x5, 986 RTW_PQ_MAP_NUM = 0x6, 987 988 RTW_PQ_MAP_UNDEF, 989 }; 990 991 enum rtw_dma_mapping { 992 RTW_DMA_MAPPING_EXTRA = 0, 993 RTW_DMA_MAPPING_LOW = 1, 994 RTW_DMA_MAPPING_NORMAL = 2, 995 RTW_DMA_MAPPING_HIGH = 3, 996 997 RTW_DMA_MAPPING_MAX, 998 RTW_DMA_MAPPING_UNDEF, 999 }; 1000 1001 struct rtw_rqpn { 1002 enum rtw_dma_mapping dma_map_vo; 1003 enum rtw_dma_mapping dma_map_vi; 1004 enum rtw_dma_mapping dma_map_be; 1005 enum rtw_dma_mapping dma_map_bk; 1006 enum rtw_dma_mapping dma_map_mg; 1007 enum rtw_dma_mapping dma_map_hi; 1008 }; 1009 1010 struct rtw_prioq_addr { 1011 u32 rsvd; 1012 u32 avail; 1013 }; 1014 1015 struct rtw_prioq_addrs { 1016 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1017 bool wsize; 1018 }; 1019 1020 struct rtw_page_table { 1021 u16 hq_num; 1022 u16 nq_num; 1023 u16 lq_num; 1024 u16 exq_num; 1025 u16 gapq_num; 1026 }; 1027 1028 struct rtw_intf_phy_para { 1029 u16 offset; 1030 u16 value; 1031 u16 ip_sel; 1032 u16 cut_mask; 1033 u16 platform; 1034 }; 1035 1036 struct rtw_wow_pattern { 1037 u16 crc; 1038 u8 type; 1039 u8 valid; 1040 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1041 }; 1042 1043 struct rtw_pno_request { 1044 bool inited; 1045 u32 match_set_cnt; 1046 struct cfg80211_match_set *match_sets; 1047 u8 channel_cnt; 1048 struct ieee80211_channel *channels; 1049 struct cfg80211_sched_scan_plan scan_plan; 1050 }; 1051 1052 struct rtw_wow_param { 1053 struct ieee80211_vif *wow_vif; 1054 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1055 u8 txpause; 1056 u8 pattern_cnt; 1057 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1058 1059 bool ips_enabled; 1060 struct rtw_pno_request pno_req; 1061 }; 1062 1063 struct rtw_intf_phy_para_table { 1064 const struct rtw_intf_phy_para *usb2_para; 1065 const struct rtw_intf_phy_para *usb3_para; 1066 const struct rtw_intf_phy_para *gen1_para; 1067 const struct rtw_intf_phy_para *gen2_para; 1068 u8 n_usb2_para; 1069 u8 n_usb3_para; 1070 u8 n_gen1_para; 1071 u8 n_gen2_para; 1072 }; 1073 1074 struct rtw_table { 1075 const void *data; 1076 const u32 size; 1077 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1078 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1079 u32 addr, u32 data); 1080 enum rtw_rf_path rf_path; 1081 }; 1082 rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1083 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1084 const struct rtw_table *tbl) 1085 { 1086 (*tbl->parse)(rtwdev, tbl); 1087 } 1088 1089 enum rtw_rfe_fem { 1090 RTW_RFE_IFEM, 1091 RTW_RFE_EFEM, 1092 RTW_RFE_IFEM2G_EFEM5G, 1093 RTW_RFE_NUM, 1094 }; 1095 1096 struct rtw_rfe_def { 1097 const struct rtw_table *phy_pg_tbl; 1098 const struct rtw_table *txpwr_lmt_tbl; 1099 const struct rtw_table *agc_btg_tbl; 1100 }; 1101 1102 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1103 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1104 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1105 } 1106 1107 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1108 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1109 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1110 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1111 } 1112 1113 #define RTW_PWR_TRK_5G_1 0 1114 #define RTW_PWR_TRK_5G_2 1 1115 #define RTW_PWR_TRK_5G_3 2 1116 #define RTW_PWR_TRK_5G_NUM 3 1117 1118 #define RTW_PWR_TRK_TBL_SZ 30 1119 1120 /* This table stores the values of TX power that will be adjusted by power 1121 * tracking. 1122 * 1123 * For 5G bands, there are 3 different settings. 1124 * For 2G there are cck rate and ofdm rate with different settings. 1125 */ 1126 struct rtw_pwr_track_tbl { 1127 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1128 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1129 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1130 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1131 const u8 *pwrtrk_2gb_n; 1132 const u8 *pwrtrk_2gb_p; 1133 const u8 *pwrtrk_2ga_n; 1134 const u8 *pwrtrk_2ga_p; 1135 const u8 *pwrtrk_2g_cckb_n; 1136 const u8 *pwrtrk_2g_cckb_p; 1137 const u8 *pwrtrk_2g_ccka_n; 1138 const u8 *pwrtrk_2g_ccka_p; 1139 const s8 *pwrtrk_xtal_n; 1140 const s8 *pwrtrk_xtal_p; 1141 }; 1142 1143 enum rtw_wlan_cpu { 1144 RTW_WCPU_11AC, 1145 RTW_WCPU_11N, 1146 }; 1147 1148 enum rtw_fw_fifo_sel { 1149 RTW_FW_FIFO_SEL_TX, 1150 RTW_FW_FIFO_SEL_RX, 1151 RTW_FW_FIFO_SEL_RSVD_PAGE, 1152 RTW_FW_FIFO_SEL_REPORT, 1153 RTW_FW_FIFO_SEL_LLT, 1154 RTW_FW_FIFO_SEL_RXBUF_FW, 1155 1156 RTW_FW_FIFO_MAX, 1157 }; 1158 1159 enum rtw_fwcd_item { 1160 RTW_FWCD_TLV, 1161 RTW_FWCD_REG, 1162 RTW_FWCD_ROM, 1163 RTW_FWCD_IMEM, 1164 RTW_FWCD_DMEM, 1165 RTW_FWCD_EMEM, 1166 }; 1167 1168 /* hardware configuration for each IC */ 1169 struct rtw_chip_info { 1170 struct rtw_chip_ops *ops; 1171 u8 id; 1172 1173 const char *fw_name; 1174 enum rtw_wlan_cpu wlan_cpu; 1175 u8 tx_pkt_desc_sz; 1176 u8 tx_buf_desc_sz; 1177 u8 rx_pkt_desc_sz; 1178 u8 rx_buf_desc_sz; 1179 u32 phy_efuse_size; 1180 u32 log_efuse_size; 1181 u32 ptct_efuse_size; 1182 u32 txff_size; 1183 u32 rxff_size; 1184 u32 fw_rxff_size; 1185 u16 rsvd_drv_pg_num; 1186 u8 band; 1187 u8 page_size; 1188 u8 csi_buf_pg_num; 1189 u8 dig_max; 1190 u8 dig_min; 1191 u8 txgi_factor; 1192 bool is_pwr_by_rate_dec; 1193 bool rx_ldpc; 1194 bool tx_stbc; 1195 u8 max_power_index; 1196 u8 ampdu_density; 1197 1198 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1199 const struct rtw_fwcd_segs *fwcd_segs; 1200 1201 u8 usb_tx_agg_desc_num; 1202 1203 u8 default_1ss_tx_path; 1204 1205 bool path_div_supported; 1206 bool ht_supported; 1207 bool vht_supported; 1208 u8 lps_deep_mode_supported; 1209 1210 /* init values */ 1211 u8 sys_func_en; 1212 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1213 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1214 const struct rtw_rqpn *rqpn_table; 1215 const struct rtw_prioq_addrs *prioq_addrs; 1216 const struct rtw_page_table *page_table; 1217 const struct rtw_intf_phy_para_table *intf_table; 1218 1219 const struct rtw_hw_reg *dig; 1220 const struct rtw_hw_reg *dig_cck; 1221 u32 rf_base_addr[2]; 1222 u32 rf_sipi_addr[2]; 1223 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1224 u8 fix_rf_phy_num; 1225 const struct rtw_ltecoex_addr *ltecoex_addr; 1226 1227 const struct rtw_table *mac_tbl; 1228 const struct rtw_table *agc_tbl; 1229 const struct rtw_table *bb_tbl; 1230 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1231 const struct rtw_table *rfk_init_tbl; 1232 1233 const struct rtw_rfe_def *rfe_defs; 1234 u32 rfe_defs_size; 1235 1236 bool en_dis_dpd; 1237 u16 dpd_ratemask; 1238 u8 iqk_threshold; 1239 u8 lck_threshold; 1240 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1241 1242 u8 bfer_su_max_num; 1243 u8 bfer_mu_max_num; 1244 1245 struct rtw_hw_reg_offset *edcca_th; 1246 s8 l2h_th_ini_cs; 1247 s8 l2h_th_ini_ad; 1248 1249 const char *wow_fw_name; 1250 const struct wiphy_wowlan_support *wowlan_stub; 1251 const u8 max_sched_scan_ssids; 1252 const u16 max_scan_ie_len; 1253 1254 /* coex paras */ 1255 u32 coex_para_ver; 1256 u8 bt_desired_ver; 1257 bool scbd_support; 1258 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1259 bool ble_hid_profile_support; 1260 bool wl_mimo_ps_support; 1261 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1262 u8 bt_rssi_type; 1263 u8 ant_isolation; 1264 u8 rssi_tolerance; 1265 u8 table_sant_num; 1266 u8 table_nsant_num; 1267 u8 tdma_sant_num; 1268 u8 tdma_nsant_num; 1269 u8 bt_afh_span_bw20; 1270 u8 bt_afh_span_bw40; 1271 u8 afh_5g_num; 1272 u8 wl_rf_para_num; 1273 u8 coex_info_hw_regs_num; 1274 const u8 *bt_rssi_step; 1275 const u8 *wl_rssi_step; 1276 const struct coex_table_para *table_nsant; 1277 const struct coex_table_para *table_sant; 1278 const struct coex_tdma_para *tdma_sant; 1279 const struct coex_tdma_para *tdma_nsant; 1280 const struct coex_rf_para *wl_rf_para_tx; 1281 const struct coex_rf_para *wl_rf_para_rx; 1282 const struct coex_5g_afh_map *afh_5g; 1283 const struct rtw_hw_reg *btg_reg; 1284 const struct rtw_reg_domain *coex_info_hw_regs; 1285 u32 wl_fw_desired_ver; 1286 }; 1287 1288 enum rtw_coex_bt_state_cnt { 1289 COEX_CNT_BT_RETRY, 1290 COEX_CNT_BT_REINIT, 1291 COEX_CNT_BT_REENABLE, 1292 COEX_CNT_BT_POPEVENT, 1293 COEX_CNT_BT_SETUPLINK, 1294 COEX_CNT_BT_IGNWLANACT, 1295 COEX_CNT_BT_INQ, 1296 COEX_CNT_BT_PAGE, 1297 COEX_CNT_BT_ROLESWITCH, 1298 COEX_CNT_BT_AFHUPDATE, 1299 COEX_CNT_BT_INFOUPDATE, 1300 COEX_CNT_BT_IQK, 1301 COEX_CNT_BT_IQKFAIL, 1302 1303 COEX_CNT_BT_MAX 1304 }; 1305 1306 enum rtw_coex_wl_state_cnt { 1307 COEX_CNT_WL_SCANAP, 1308 COEX_CNT_WL_CONNPKT, 1309 COEX_CNT_WL_COEXRUN, 1310 COEX_CNT_WL_NOISY0, 1311 COEX_CNT_WL_NOISY1, 1312 COEX_CNT_WL_NOISY2, 1313 COEX_CNT_WL_5MS_NOEXTEND, 1314 COEX_CNT_WL_FW_NOTIFY, 1315 1316 COEX_CNT_WL_MAX 1317 }; 1318 1319 struct rtw_coex_rfe { 1320 bool ant_switch_exist; 1321 bool ant_switch_diversity; 1322 bool ant_switch_with_bt; 1323 u8 rfe_module_type; 1324 u8 ant_switch_polarity; 1325 1326 /* true if WLG at BTG, else at WLAG */ 1327 bool wlg_at_btg; 1328 }; 1329 1330 #define COEX_WL_TDMA_PARA_LENGTH 5 1331 1332 struct rtw_coex_dm { 1333 bool cur_ps_tdma_on; 1334 bool cur_wl_rx_low_gain_en; 1335 bool ignore_wl_act; 1336 1337 u8 reason; 1338 u8 bt_rssi_state[4]; 1339 u8 wl_rssi_state[4]; 1340 u8 wl_ch_info[3]; 1341 u8 cur_ps_tdma; 1342 u8 cur_table; 1343 u8 ps_tdma_para[5]; 1344 u8 cur_bt_pwr_lvl; 1345 u8 cur_bt_lna_lvl; 1346 u8 cur_wl_pwr_lvl; 1347 u8 bt_status; 1348 u32 cur_ant_pos_type; 1349 u32 cur_switch_status; 1350 u32 setting_tdma; 1351 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1352 }; 1353 1354 #define COEX_BTINFO_SRC_WL_FW 0x0 1355 #define COEX_BTINFO_SRC_BT_RSP 0x1 1356 #define COEX_BTINFO_SRC_BT_ACT 0x2 1357 #define COEX_BTINFO_SRC_BT_IQK 0x3 1358 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1359 #define COEX_BTINFO_SRC_H2C60 0x5 1360 #define COEX_BTINFO_SRC_MAX 0x6 1361 1362 #define COEX_INFO_FTP BIT(7) 1363 #define COEX_INFO_A2DP BIT(6) 1364 #define COEX_INFO_HID BIT(5) 1365 #define COEX_INFO_SCO_BUSY BIT(4) 1366 #define COEX_INFO_ACL_BUSY BIT(3) 1367 #define COEX_INFO_INQ_PAGE BIT(2) 1368 #define COEX_INFO_SCO_ESCO BIT(1) 1369 #define COEX_INFO_CONNECTION BIT(0) 1370 #define COEX_BTINFO_LENGTH_MAX 10 1371 #define COEX_BTINFO_LENGTH 7 1372 1373 #define COEX_BT_HIDINFO_LIST 0x0 1374 #define COEX_BT_HIDINFO_A 0x1 1375 #define COEX_BT_HIDINFO_NAME 3 1376 1377 #define COEX_BT_HIDINFO_LENGTH 6 1378 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1379 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1380 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1381 #define COEX_BT_BLE_HANDLE_THRS 0x10 1382 #define COEX_BT_HIDINFO_NOTCON 0xff 1383 1384 struct rtw_coex_hid { 1385 u8 hid_handle; 1386 u8 hid_vendor; 1387 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1388 bool hid_info_completed; 1389 bool is_game_hid; 1390 }; 1391 1392 struct rtw_coex_hid_handle_list { 1393 u8 cmd_id; 1394 u8 len; 1395 u8 subid; 1396 u8 handle_cnt; 1397 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1398 } __packed; 1399 1400 struct rtw_coex_hid_info_a { 1401 u8 cmd_id; 1402 u8 len; 1403 u8 subid; 1404 u8 handle; 1405 u8 vendor; 1406 u8 name[COEX_BT_HIDINFO_NAME]; 1407 } __packed; 1408 1409 struct rtw_coex_stat { 1410 bool bt_disabled; 1411 bool bt_disabled_pre; 1412 bool bt_link_exist; 1413 bool bt_whck_test; 1414 bool bt_inq_page; 1415 bool bt_inq_remain; 1416 bool bt_inq; 1417 bool bt_page; 1418 bool bt_ble_voice; 1419 bool bt_ble_exist; 1420 bool bt_hfp_exist; 1421 bool bt_a2dp_exist; 1422 bool bt_hid_exist; 1423 bool bt_pan_exist; /* PAN or OPP */ 1424 bool bt_opp_exist; /* OPP only */ 1425 bool bt_acl_busy; 1426 bool bt_fix_2M; 1427 bool bt_setup_link; 1428 bool bt_multi_link; 1429 bool bt_multi_link_pre; 1430 bool bt_multi_link_remain; 1431 bool bt_a2dp_sink; 1432 bool bt_a2dp_active; 1433 bool bt_reenable; 1434 bool bt_ble_scan_en; 1435 bool bt_init_scan; 1436 bool bt_slave; 1437 bool bt_418_hid_exist; 1438 bool bt_ble_hid_exist; 1439 bool bt_game_hid_exist; 1440 bool bt_hid_handle_cnt; 1441 bool bt_mailbox_reply; 1442 1443 bool wl_under_lps; 1444 bool wl_under_ips; 1445 bool wl_hi_pri_task1; 1446 bool wl_hi_pri_task2; 1447 bool wl_force_lps_ctrl; 1448 bool wl_gl_busy; 1449 bool wl_linkscan_proc; 1450 bool wl_ps_state_fail; 1451 bool wl_tx_limit_en; 1452 bool wl_ampdu_limit_en; 1453 bool wl_connected; 1454 bool wl_slot_extend; 1455 bool wl_cck_lock; 1456 bool wl_cck_lock_pre; 1457 bool wl_cck_lock_ever; 1458 bool wl_connecting; 1459 bool wl_slot_toggle; 1460 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1461 bool wl_mimo_ps; 1462 1463 u32 bt_supported_version; 1464 u32 bt_supported_feature; 1465 u32 hi_pri_tx; 1466 u32 hi_pri_rx; 1467 u32 lo_pri_tx; 1468 u32 lo_pri_rx; 1469 u32 patch_ver; 1470 u16 bt_reg_vendor_ae; 1471 u16 bt_reg_vendor_ac; 1472 s8 bt_rssi; 1473 u8 kt_ver; 1474 u8 gnt_workaround_state; 1475 u8 tdma_timer_base; 1476 u8 bt_profile_num; 1477 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1478 u8 bt_info_lb2; 1479 u8 bt_info_lb3; 1480 u8 bt_info_hb0; 1481 u8 bt_info_hb1; 1482 u8 bt_info_hb2; 1483 u8 bt_info_hb3; 1484 u8 bt_ble_scan_type; 1485 u8 bt_hid_pair_num; 1486 u8 bt_hid_slot; 1487 u8 bt_a2dp_bitpool; 1488 u8 bt_iqk_state; 1489 1490 u16 wl_beacon_interval; 1491 u8 wl_noisy_level; 1492 u8 wl_fw_dbg_info[10]; 1493 u8 wl_fw_dbg_info_pre[10]; 1494 u8 wl_rx_rate; 1495 u8 wl_tx_rate; 1496 u8 wl_rts_rx_rate; 1497 u8 wl_coex_mode; 1498 u8 wl_iot_peer; 1499 u8 ampdu_max_time; 1500 u8 wl_tput_dir; 1501 1502 u8 wl_toggle_para[6]; 1503 u8 wl_toggle_interval; 1504 1505 u16 score_board; 1506 u16 retry_limit; 1507 1508 /* counters to record bt states */ 1509 u32 cnt_bt[COEX_CNT_BT_MAX]; 1510 1511 /* counters to record wifi states */ 1512 u32 cnt_wl[COEX_CNT_WL_MAX]; 1513 1514 /* counters to record bt c2h data */ 1515 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1516 1517 u32 darfrc; 1518 u32 darfrch; 1519 1520 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1521 struct rtw_coex_hid_handle_list hid_handle_list; 1522 }; 1523 1524 struct rtw_coex { 1525 struct sk_buff_head queue; 1526 wait_queue_head_t wait; 1527 1528 bool under_5g; 1529 bool stop_dm; 1530 bool freeze; 1531 bool freerun; 1532 bool wl_rf_off; 1533 bool manual_control; 1534 1535 struct rtw_coex_stat stat; 1536 struct rtw_coex_dm dm; 1537 struct rtw_coex_rfe rfe; 1538 1539 struct delayed_work bt_relink_work; 1540 struct delayed_work bt_reenable_work; 1541 struct delayed_work defreeze_work; 1542 struct delayed_work wl_remain_work; 1543 struct delayed_work bt_remain_work; 1544 struct delayed_work wl_connecting_work; 1545 struct delayed_work bt_multi_link_remain_work; 1546 struct delayed_work wl_ccklock_work; 1547 1548 }; 1549 1550 #define DPK_RF_REG_NUM 7 1551 #define DPK_RF_PATH_NUM 2 1552 #define DPK_BB_REG_NUM 18 1553 #define DPK_CHANNEL_WIDTH_80 1 1554 1555 DECLARE_EWMA(thermal, 10, 4); 1556 1557 struct rtw_dpk_info { 1558 bool is_dpk_pwr_on; 1559 bool is_reload; 1560 1561 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1562 1563 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1564 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1565 1566 u32 gnt_control; 1567 u32 gnt_value; 1568 1569 u8 result[RTW_RF_PATH_MAX]; 1570 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1571 u32 coef[RTW_RF_PATH_MAX][20]; 1572 u16 dpk_gs[RTW_RF_PATH_MAX]; 1573 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1574 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1575 1576 u8 dpk_band; 1577 u8 dpk_ch; 1578 u8 dpk_bw; 1579 }; 1580 1581 struct rtw_phy_cck_pd_reg { 1582 u32 reg_pd; 1583 u32 mask_pd; 1584 u32 reg_cs; 1585 u32 mask_cs; 1586 }; 1587 1588 #define DACK_MSBK_BACKUP_NUM 0xf 1589 #define DACK_DCK_BACKUP_NUM 0x2 1590 1591 struct rtw_swing_table { 1592 const u8 *p[RTW_RF_PATH_MAX]; 1593 const u8 *n[RTW_RF_PATH_MAX]; 1594 }; 1595 1596 struct rtw_pkt_count { 1597 u16 num_bcn_pkt; 1598 u16 num_qry_pkt[DESC_RATE_MAX]; 1599 }; 1600 1601 DECLARE_EWMA(evm, 10, 4); 1602 DECLARE_EWMA(snr, 10, 4); 1603 1604 struct rtw_iqk_info { 1605 bool done; 1606 struct { 1607 u32 s1_x; 1608 u32 s1_y; 1609 u32 s0_x; 1610 u32 s0_y; 1611 } result; 1612 }; 1613 1614 enum rtw_rf_band { 1615 RF_BAND_2G_CCK, 1616 RF_BAND_2G_OFDM, 1617 RF_BAND_5G_L, 1618 RF_BAND_5G_M, 1619 RF_BAND_5G_H, 1620 RF_BAND_MAX 1621 }; 1622 1623 #define RF_GAIN_NUM 11 1624 #define RF_HW_OFFSET_NUM 10 1625 1626 struct rtw_gapk_info { 1627 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1628 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1629 bool txgapk_bp_done; 1630 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1631 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1632 u8 read_txgain; 1633 u8 channel; 1634 }; 1635 1636 #define EDCCA_TH_L2H_IDX 0 1637 #define EDCCA_TH_H2L_IDX 1 1638 #define EDCCA_TH_L2H_LB 48 1639 #define EDCCA_ADC_BACKOFF 12 1640 #define EDCCA_IGI_BASE 50 1641 #define EDCCA_IGI_L2H_DIFF 8 1642 #define EDCCA_L2H_H2L_DIFF 7 1643 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1644 1645 enum rtw_edcca_mode { 1646 RTW_EDCCA_NORMAL = 0, 1647 RTW_EDCCA_ADAPTIVITY = 1, 1648 }; 1649 1650 struct rtw_cfo_track { 1651 bool is_adjust; 1652 u8 crystal_cap; 1653 s32 cfo_tail[RTW_RF_PATH_MAX]; 1654 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1655 u32 packet_count; 1656 u32 packet_count_pre; 1657 }; 1658 1659 #define RRSR_INIT_2G 0x15f 1660 #define RRSR_INIT_5G 0x150 1661 1662 enum rtw_dm_cap { 1663 RTW_DM_CAP_NA, 1664 RTW_DM_CAP_TXGAPK, 1665 RTW_DM_CAP_NUM 1666 }; 1667 1668 struct rtw_dm_info { 1669 u32 cck_fa_cnt; 1670 u32 ofdm_fa_cnt; 1671 u32 total_fa_cnt; 1672 u32 cck_cca_cnt; 1673 u32 ofdm_cca_cnt; 1674 u32 total_cca_cnt; 1675 1676 u32 cck_ok_cnt; 1677 u32 cck_err_cnt; 1678 u32 ofdm_ok_cnt; 1679 u32 ofdm_err_cnt; 1680 u32 ht_ok_cnt; 1681 u32 ht_err_cnt; 1682 u32 vht_ok_cnt; 1683 u32 vht_err_cnt; 1684 1685 u8 min_rssi; 1686 u8 pre_min_rssi; 1687 u16 fa_history[4]; 1688 u8 igi_history[4]; 1689 u8 igi_bitmap; 1690 bool damping; 1691 u8 damping_cnt; 1692 u8 damping_rssi; 1693 1694 u8 cck_gi_u_bnd; 1695 u8 cck_gi_l_bnd; 1696 1697 u8 fix_rate; 1698 u8 tx_rate; 1699 u32 rrsr_val_init; 1700 u32 rrsr_mask_min; 1701 u8 thermal_avg[RTW_RF_PATH_MAX]; 1702 u8 thermal_meter_k; 1703 u8 thermal_meter_lck; 1704 s8 delta_power_index[RTW_RF_PATH_MAX]; 1705 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1706 u8 default_ofdm_index; 1707 u8 default_cck_index; 1708 bool pwr_trk_triggered; 1709 bool pwr_trk_init_trigger; 1710 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1711 s8 txagc_remnant_cck; 1712 s8 txagc_remnant_ofdm; 1713 u8 rx_cck_agc_report_type; 1714 1715 /* backup dack results for each path and I/Q */ 1716 u32 dack_adck[RTW_RF_PATH_MAX]; 1717 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1718 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1719 1720 struct rtw_dpk_info dpk_info; 1721 struct rtw_cfo_track cfo_track; 1722 1723 /* [bandwidth 0:20M/1:40M][number of path] */ 1724 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1725 u32 cck_fa_avg; 1726 u8 cck_pd_default; 1727 1728 /* save the last rx phy status for debug */ 1729 s8 rx_snr[RTW_RF_PATH_MAX]; 1730 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1731 s16 cfo_tail[RTW_RF_PATH_MAX]; 1732 u8 rssi[RTW_RF_PATH_MAX]; 1733 u8 curr_rx_rate; 1734 struct rtw_pkt_count cur_pkt_count; 1735 struct rtw_pkt_count last_pkt_count; 1736 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1737 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1738 1739 u32 dm_flags; /* enum rtw_dm_cap */ 1740 struct rtw_iqk_info iqk; 1741 struct rtw_gapk_info gapk; 1742 bool is_bt_iqk_timeout; 1743 1744 s8 l2h_th_ini; 1745 enum rtw_edcca_mode edcca_mode; 1746 u8 scan_density; 1747 }; 1748 1749 struct rtw_efuse { 1750 u32 size; 1751 u32 physical_size; 1752 u32 logical_size; 1753 u32 protect_size; 1754 1755 u8 addr[ETH_ALEN]; 1756 u8 channel_plan; 1757 u8 country_code[2]; 1758 u8 rf_board_option; 1759 u8 rfe_option; 1760 u8 power_track_type; 1761 u8 thermal_meter[RTW_RF_PATH_MAX]; 1762 u8 thermal_meter_k; 1763 u8 crystal_cap; 1764 u8 ant_div_cfg; 1765 u8 ant_div_type; 1766 u8 regd; 1767 u8 afe; 1768 1769 u8 lna_type_2g; 1770 u8 lna_type_5g; 1771 u8 glna_type; 1772 u8 alna_type; 1773 bool ext_lna_2g; 1774 bool ext_lna_5g; 1775 u8 pa_type_2g; 1776 u8 pa_type_5g; 1777 u8 gpa_type; 1778 u8 apa_type; 1779 bool ext_pa_2g; 1780 bool ext_pa_5g; 1781 u8 tx_bb_swing_setting_2g; 1782 u8 tx_bb_swing_setting_5g; 1783 1784 bool btcoex; 1785 /* bt share antenna with wifi */ 1786 bool share_ant; 1787 u8 bt_setting; 1788 1789 u8 usb_mode_switch; 1790 1791 struct { 1792 u8 hci; 1793 u8 bw; 1794 u8 ptcl; 1795 u8 nss; 1796 u8 ant_num; 1797 } hw_cap; 1798 1799 struct rtw_txpwr_idx txpwr_idx_table[4]; 1800 }; 1801 1802 struct rtw_phy_cond { 1803 #ifdef __LITTLE_ENDIAN 1804 u32 rfe:8; 1805 u32 intf:4; 1806 u32 pkg:4; 1807 u32 plat:4; 1808 u32 intf_rsvd:4; 1809 u32 cut:4; 1810 u32 branch:2; 1811 u32 neg:1; 1812 u32 pos:1; 1813 #else 1814 u32 pos:1; 1815 u32 neg:1; 1816 u32 branch:2; 1817 u32 cut:4; 1818 u32 intf_rsvd:4; 1819 u32 plat:4; 1820 u32 pkg:4; 1821 u32 intf:4; 1822 u32 rfe:8; 1823 #endif 1824 /* for intf:4 */ 1825 #define INTF_PCIE BIT(0) 1826 #define INTF_USB BIT(1) 1827 #define INTF_SDIO BIT(2) 1828 /* for branch:2 */ 1829 #define BRANCH_IF 0 1830 #define BRANCH_ELIF 1 1831 #define BRANCH_ELSE 2 1832 #define BRANCH_ENDIF 3 1833 }; 1834 1835 struct rtw_fifo_conf { 1836 /* tx fifo information */ 1837 u16 rsvd_boundary; 1838 u16 rsvd_pg_num; 1839 u16 rsvd_drv_pg_num; 1840 u16 txff_pg_num; 1841 u16 acq_pg_num; 1842 u16 rsvd_drv_addr; 1843 u16 rsvd_h2c_info_addr; 1844 u16 rsvd_h2c_sta_info_addr; 1845 u16 rsvd_h2cq_addr; 1846 u16 rsvd_cpu_instr_addr; 1847 u16 rsvd_fw_txbuf_addr; 1848 u16 rsvd_csibuf_addr; 1849 const struct rtw_rqpn *rqpn; 1850 }; 1851 1852 struct rtw_fwcd_desc { 1853 u32 size; 1854 u8 *next; 1855 u8 *data; 1856 }; 1857 1858 struct rtw_fwcd_segs { 1859 const u32 *segs; 1860 u8 num; 1861 }; 1862 1863 #define FW_CD_TYPE 0xffff 1864 #define FW_CD_LEN 4 1865 #define FW_CD_VAL 0xaabbccdd 1866 struct rtw_fw_state { 1867 const struct firmware *firmware; 1868 struct rtw_dev *rtwdev; 1869 struct completion completion; 1870 struct rtw_fwcd_desc fwcd_desc; 1871 u16 version; 1872 u8 sub_version; 1873 u8 sub_index; 1874 u16 h2c_version; 1875 u32 feature; 1876 u32 feature_ext; 1877 enum rtw_fw_type type; 1878 }; 1879 1880 enum rtw_sar_sources { 1881 RTW_SAR_SOURCE_NONE, 1882 RTW_SAR_SOURCE_COMMON, 1883 }; 1884 1885 enum rtw_sar_bands { 1886 RTW_SAR_BAND_0, 1887 RTW_SAR_BAND_1, 1888 /* RTW_SAR_BAND_2, not used now */ 1889 RTW_SAR_BAND_3, 1890 RTW_SAR_BAND_4, 1891 1892 RTW_SAR_BAND_NR, 1893 }; 1894 1895 /* the union is reserved for other kinds of SAR sources 1896 * which might not re-use same format with array common. 1897 */ 1898 union rtw_sar_cfg { 1899 s8 common[RTW_SAR_BAND_NR]; 1900 }; 1901 1902 struct rtw_sar { 1903 enum rtw_sar_sources src; 1904 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1905 }; 1906 1907 struct rtw_hal { 1908 u32 rcr; 1909 1910 u32 chip_version; 1911 u8 cut_version; 1912 u8 mp_chip; 1913 u8 oem_id; 1914 u8 pkg_type; 1915 struct rtw_phy_cond phy_cond; 1916 bool rfe_btg; 1917 1918 u8 ps_mode; 1919 u8 current_channel; 1920 u8 current_primary_channel_index; 1921 u8 current_band_width; 1922 u8 current_band_type; 1923 u8 primary_channel; 1924 1925 /* center channel for different available bandwidth, 1926 * val of (bw > current_band_width) is invalid 1927 */ 1928 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1929 1930 u8 sec_ch_offset; 1931 u8 rf_type; 1932 u8 rf_path_num; 1933 u8 rf_phy_num; 1934 u32 antenna_tx; 1935 u32 antenna_rx; 1936 u8 bfee_sts_cap; 1937 bool txrx_1ss; 1938 1939 /* protect tx power section */ 1940 struct mutex tx_power_mutex; 1941 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1942 [DESC_RATE_MAX]; 1943 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1944 [DESC_RATE_MAX]; 1945 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1946 [RTW_RATE_SECTION_MAX]; 1947 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1948 [RTW_RATE_SECTION_MAX]; 1949 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1950 [RTW_CHANNEL_WIDTH_MAX] 1951 [RTW_RATE_SECTION_MAX] 1952 [RTW_MAX_CHANNEL_NUM_2G]; 1953 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1954 [RTW_CHANNEL_WIDTH_MAX] 1955 [RTW_RATE_SECTION_MAX] 1956 [RTW_MAX_CHANNEL_NUM_5G]; 1957 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1958 [DESC_RATE_MAX]; 1959 1960 enum rtw_sar_bands sar_band; 1961 struct rtw_sar sar; 1962 1963 /* for 8821c set channel */ 1964 u32 ch_param[3]; 1965 }; 1966 1967 struct rtw_path_div { 1968 enum rtw_bb_path current_tx_path; 1969 u32 path_a_sum; 1970 u32 path_b_sum; 1971 u16 path_a_cnt; 1972 u16 path_b_cnt; 1973 }; 1974 1975 struct rtw_chan_info { 1976 int pri_ch_idx; 1977 int action_id; 1978 int bw; 1979 u8 extra_info; 1980 u8 channel; 1981 u16 timeout; 1982 }; 1983 1984 struct rtw_chan_list { 1985 u32 buf_size; 1986 u32 ch_num; 1987 u32 size; 1988 u16 addr; 1989 }; 1990 1991 struct rtw_hw_scan_info { 1992 struct ieee80211_vif *scanning_vif; 1993 u8 probe_pg_size; 1994 u8 op_pri_ch_idx; 1995 u8 op_pri_ch; 1996 u8 op_chan; 1997 u8 op_bw; 1998 }; 1999 2000 struct rtw_dev { 2001 struct ieee80211_hw *hw; 2002 struct device *dev; 2003 2004 struct rtw_hci hci; 2005 2006 struct rtw_hw_scan_info scan_info; 2007 const struct rtw_chip_info *chip; 2008 struct rtw_hal hal; 2009 struct rtw_fifo_conf fifo; 2010 struct rtw_fw_state fw; 2011 struct rtw_efuse efuse; 2012 struct rtw_sec_desc sec; 2013 struct rtw_traffic_stats stats; 2014 struct rtw_regd regd; 2015 struct rtw_bf_info bf_info; 2016 2017 struct rtw_dm_info dm_info; 2018 struct rtw_coex coex; 2019 2020 /* ensures exclusive access from mac80211 callbacks */ 2021 struct mutex mutex; 2022 2023 /* watch dog every 2 sec */ 2024 struct delayed_work watch_dog_work; 2025 u32 watch_dog_cnt; 2026 2027 struct list_head rsvd_page_list; 2028 2029 /* c2h cmd queue & handler work */ 2030 struct sk_buff_head c2h_queue; 2031 struct work_struct c2h_work; 2032 struct work_struct ips_work; 2033 struct work_struct fw_recovery_work; 2034 struct work_struct update_beacon_work; 2035 2036 /* used to protect txqs list */ 2037 spinlock_t txq_lock; 2038 struct list_head txqs; 2039 struct workqueue_struct *tx_wq; 2040 struct work_struct tx_work; 2041 struct work_struct ba_work; 2042 2043 struct rtw_tx_report tx_report; 2044 2045 struct { 2046 /* indicate the mail box to use with fw */ 2047 u8 last_box_num; 2048 u32 seq; 2049 } h2c; 2050 2051 /* lps power state & handler work */ 2052 struct rtw_lps_conf lps_conf; 2053 bool ps_enabled; 2054 bool beacon_loss; 2055 struct completion lps_leave_check; 2056 2057 struct rtw_debugfs *debugfs; 2058 2059 u8 sta_cnt; 2060 u32 rts_threshold; 2061 2062 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2063 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2064 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2065 2066 u8 mp_mode; 2067 struct rtw_path_div dm_path_div; 2068 2069 struct rtw_fw_state wow_fw; 2070 struct rtw_wow_param wow; 2071 2072 bool need_rfk; 2073 struct completion fw_scan_density; 2074 bool ap_active; 2075 2076 /* hci related data, must be last */ 2077 u8 priv[] __aligned(sizeof(void *)); 2078 }; 2079 2080 #include "hci.h" 2081 rtw_is_assoc(struct rtw_dev * rtwdev)2082 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2083 { 2084 return !!rtwdev->sta_cnt; 2085 } 2086 rtwtxq_to_txq(struct rtw_txq * rtwtxq)2087 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2088 { 2089 void *p = rtwtxq; 2090 2091 return container_of(p, struct ieee80211_txq, drv_priv); 2092 } 2093 rtwvif_to_vif(struct rtw_vif * rtwvif)2094 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2095 { 2096 void *p = rtwvif; 2097 2098 return container_of(p, struct ieee80211_vif, drv_priv); 2099 } 2100 rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2101 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2102 { 2103 if (rtwdev->chip->ops->efuse_grant) 2104 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2105 } 2106 rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2107 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2108 { 2109 if (rtwdev->chip->ops->efuse_grant) 2110 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2111 } 2112 rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)2113 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2114 { 2115 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2116 } 2117 rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)2118 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2119 { 2120 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2121 } 2122 rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2123 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2124 { 2125 return rtwdev->chip->rx_ldpc; 2126 } 2127 rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2128 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2129 { 2130 return rtwdev->chip->tx_stbc; 2131 } 2132 rtw_acquire_macid(struct rtw_dev * rtwdev)2133 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 2134 { 2135 unsigned long mac_id; 2136 2137 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 2138 if (mac_id < RTW_MAX_MAC_ID_NUM) 2139 set_bit(mac_id, rtwdev->mac_id_map); 2140 2141 return mac_id; 2142 } 2143 rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2144 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2145 { 2146 clear_bit(mac_id, rtwdev->mac_id_map); 2147 } 2148 rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2149 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2150 { 2151 if (rtwdev->chip->ops->dump_fw_crash) 2152 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2153 2154 return 0; 2155 } 2156 2157 static inline rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2158 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2159 { 2160 switch (hw_band) { 2161 default: 2162 case RTW_BAND_2G: 2163 return NL80211_BAND_2GHZ; 2164 case RTW_BAND_5G: 2165 return NL80211_BAND_5GHZ; 2166 case RTW_BAND_60G: 2167 return NL80211_BAND_60GHZ; 2168 } 2169 } 2170 2171 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2172 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2173 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2174 struct rtw_channel_params *ch_param); 2175 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2176 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2177 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2178 void rtw_restore_reg(struct rtw_dev *rtwdev, 2179 struct rtw_backup_info *bckp, u32 num); 2180 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2181 void rtw_set_channel(struct rtw_dev *rtwdev); 2182 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2183 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2184 u32 config); 2185 void rtw_tx_report_purge_timer(struct timer_list *t); 2186 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2187 bool reset_ra_mask); 2188 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2189 const u8 *mac_addr, bool hw_scan); 2190 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2191 bool hw_scan); 2192 int rtw_core_start(struct rtw_dev *rtwdev); 2193 void rtw_core_stop(struct rtw_dev *rtwdev); 2194 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2195 int rtw_core_init(struct rtw_dev *rtwdev); 2196 void rtw_core_deinit(struct rtw_dev *rtwdev); 2197 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2198 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2199 u16 rtw_desc_to_bitrate(u8 desc_rate); 2200 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2201 struct ieee80211_bss_conf *conf); 2202 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2203 struct ieee80211_vif *vif); 2204 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2205 bool fw_exist); 2206 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2207 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2208 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2209 u32 fwcd_item); 2210 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2211 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2212 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2213 u8 primary_channel, enum rtw_supported_band band, 2214 enum rtw_bandwidth bandwidth); 2215 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2216 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2217 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2218 #endif 2219