1  // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2  /* Copyright(c) 2018-2019  Realtek Corporation.
3   */
4  
5  #include "main.h"
6  #include "reg.h"
7  #include "bf.h"
8  #include "debug.h"
9  
rtw_bf_disassoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)10  void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11  		     struct ieee80211_bss_conf *bss_conf)
12  {
13  	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14  	struct rtw_bfee *bfee = &rtwvif->bfee;
15  	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16  
17  	if (bfee->role == RTW_BFEE_NONE)
18  		return;
19  
20  	if (bfee->role == RTW_BFEE_MU)
21  		bfinfo->bfer_mu_cnt--;
22  	else if (bfee->role == RTW_BFEE_SU)
23  		bfinfo->bfer_su_cnt--;
24  
25  	rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26  
27  	bfee->role = RTW_BFEE_NONE;
28  }
29  
rtw_bf_assoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)30  void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31  		  struct ieee80211_bss_conf *bss_conf)
32  {
33  	const struct rtw_chip_info *chip = rtwdev->chip;
34  	struct ieee80211_hw *hw = rtwdev->hw;
35  	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
36  	struct rtw_bfee *bfee = &rtwvif->bfee;
37  	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
38  	struct ieee80211_sta *sta;
39  	struct ieee80211_sta_vht_cap *vht_cap;
40  	struct ieee80211_sta_vht_cap *ic_vht_cap;
41  	const u8 *bssid = bss_conf->bssid;
42  	u32 sound_dim;
43  	u8 i;
44  
45  	if (!(chip->band & RTW_BAND_5G))
46  		return;
47  
48  	rcu_read_lock();
49  
50  	sta = ieee80211_find_sta(vif, bssid);
51  	if (!sta) {
52  		rcu_read_unlock();
53  
54  		rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
55  			 bssid);
56  		return;
57  	}
58  
59  	ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
60  	vht_cap = &sta->deflink.vht_cap;
61  
62  	rcu_read_unlock();
63  
64  	if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
65  	    (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
66  		if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
67  			rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
68  			return;
69  		}
70  
71  		ether_addr_copy(bfee->mac_addr, bssid);
72  		bfee->role = RTW_BFEE_MU;
73  		bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
74  		bfee->aid = vif->cfg.aid;
75  		bfinfo->bfer_mu_cnt++;
76  
77  		rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
78  	} else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
79  		   (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
80  		if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
81  			rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
82  			return;
83  		}
84  
85  		sound_dim = vht_cap->cap &
86  			    IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
87  		sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
88  
89  		ether_addr_copy(bfee->mac_addr, bssid);
90  		bfee->role = RTW_BFEE_SU;
91  		bfee->sound_dim = (u8)sound_dim;
92  		bfee->g_id = 0;
93  		bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
94  		bfinfo->bfer_su_cnt++;
95  		for (i = 0; i < chip->bfer_su_max_num; i++) {
96  			if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
97  				set_bit(i, bfinfo->bfer_su_reg_maping);
98  				bfee->su_reg_index = i;
99  				break;
100  			}
101  		}
102  
103  		rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
104  	}
105  }
106  
rtw_bf_init_bfer_entry_mu(struct rtw_dev * rtwdev,struct mu_bfer_init_para * param)107  void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
108  			       struct mu_bfer_init_para *param)
109  {
110  	u16 mu_bf_ctl = 0;
111  	u8 *addr = param->bfer_address;
112  	int i;
113  
114  	for (i = 0; i < ETH_ALEN; i++)
115  		rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
116  	rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
117  	rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
118  
119  	mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
120  	mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
121  	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
122  }
123  
rtw_bf_cfg_sounding(struct rtw_dev * rtwdev,struct rtw_vif * vif,enum rtw_trx_desc_rate rate)124  void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
125  			 enum rtw_trx_desc_rate rate)
126  {
127  	u32 psf_ctl = 0;
128  	u8 csi_rsc = 0x1;
129  
130  	psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
131  		  BIT_WMAC_USE_NDPARATE |
132  		  (csi_rsc << 13);
133  
134  	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
135  			RTW_SND_CTRL_SOUNDING);
136  	rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
137  	rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
138  	rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
139  
140  	if (vif->net_type == RTW_NET_AP_MODE)
141  		rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
142  	else
143  		rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
144  }
145  
rtw_bf_cfg_mu_bfee(struct rtw_dev * rtwdev,struct cfg_mumimo_para * param)146  void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
147  {
148  	u8 mu_tbl_sel;
149  	u8 mu_valid;
150  
151  	mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
152  		   ~BIT_MASK_R_MU_TABLE_VALID;
153  
154  	rtw_write8(rtwdev, REG_MU_TX_CTL,
155  		   (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
156  
157  	mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
158  
159  	rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
160  	rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
161  	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
162  	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
163  		    param->given_user_pos[1]);
164  
165  	rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
166  	rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
167  	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
168  	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
169  		    param->given_user_pos[3]);
170  }
171  
rtw_bf_del_bfer_entry_mu(struct rtw_dev * rtwdev)172  void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
173  {
174  	rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
175  	rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
176  	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
177  	rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
178  }
179  
rtw_bf_del_sounding(struct rtw_dev * rtwdev)180  void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
181  {
182  	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
183  }
184  
rtw_bf_enable_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)185  void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
186  			   struct rtw_bfee *bfee)
187  {
188  	u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
189  	u8 nr_index = bfee->sound_dim;
190  	u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
191  	u32 addr_bfer_info, addr_csi_rpt, csi_param;
192  	u8 i;
193  
194  	rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
195  
196  	switch (bfee->su_reg_index) {
197  	case 1:
198  		addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
199  		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
200  		break;
201  	case 0:
202  	default:
203  		addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
204  		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
205  		break;
206  	}
207  
208  	/* Sounding protocol control */
209  	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
210  			RTW_SND_CTRL_SOUNDING);
211  
212  	/* MAC address/Partial AID of Beamformer */
213  	for (i = 0; i < ETH_ALEN; i++)
214  		rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
215  
216  	csi_param = (u16)((coefficientsize << 10) |
217  			  (codebookinfo << 8) |
218  			  (grouping << 6) |
219  			  (nr_index << 3) |
220  			  nc_index);
221  	rtw_write16(rtwdev, addr_csi_rpt, csi_param);
222  
223  	/* ndp rx standby timer */
224  	rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
225  }
226  EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
227  
228  /* nc index: 1 2T2R 0 1T1R
229   * nr index: 1 use Nsts 0 use reg setting
230   * codebookinfo: 1 802.11ac 3 802.11n
231   */
rtw_bf_enable_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)232  void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
233  			   struct rtw_bfee *bfee)
234  {
235  	struct rtw_bf_info *bf_info = &rtwdev->bf_info;
236  	struct mu_bfer_init_para param;
237  	u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
238  	u8 nr_index = 1;
239  	u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
240  	u32 csi_param;
241  
242  	rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
243  
244  	csi_param = (u16)((coefficientsize << 10) |
245  			  (codebookinfo << 8) |
246  			  (grouping << 6) |
247  			  (nr_index << 3) |
248  			  nc_index);
249  
250  	rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
251  		nc_index, nr_index, grouping, codebookinfo,
252  		coefficientsize);
253  
254  	param.paid = bfee->p_aid;
255  	param.csi_para = csi_param;
256  	param.my_aid = bfee->aid & 0xfff;
257  	param.csi_length_sel = HAL_CSI_SEG_4K;
258  	ether_addr_copy(param.bfer_address, bfee->mac_addr);
259  
260  	rtw_bf_init_bfer_entry_mu(rtwdev, &param);
261  
262  	bf_info->cur_csi_rpt_rate = DESC_RATE6M;
263  	rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
264  
265  	/* accept action_no_ack */
266  	rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
267  
268  	/* accept NDPA and BF report poll */
269  	rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
270  }
271  EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
272  
rtw_bf_remove_bfee_su(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)273  void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
274  			   struct rtw_bfee *bfee)
275  {
276  	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
277  
278  	rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
279  	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
280  			RTW_SND_CTRL_REMOVE);
281  
282  	switch (bfee->su_reg_index) {
283  	case 0:
284  		rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
285  		rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
286  		rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
287  		break;
288  	case 1:
289  		rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
290  		rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
291  		rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
292  		break;
293  	}
294  
295  	clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
296  	bfee->su_reg_index = 0xFF;
297  }
298  EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
299  
rtw_bf_remove_bfee_mu(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)300  void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
301  			   struct rtw_bfee *bfee)
302  {
303  	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
304  
305  	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
306  			RTW_SND_CTRL_REMOVE);
307  
308  	rtw_bf_del_bfer_entry_mu(rtwdev);
309  
310  	if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
311  		rtw_bf_del_sounding(rtwdev);
312  }
313  EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
314  
rtw_bf_set_gid_table(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)315  void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
316  			  struct ieee80211_bss_conf *conf)
317  {
318  	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
319  	struct rtw_bfee *bfee = &rtwvif->bfee;
320  	struct cfg_mumimo_para param;
321  
322  	if (bfee->role != RTW_BFEE_MU) {
323  		rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
324  		return;
325  	}
326  
327  	param.grouping_bitmap = 0;
328  	param.mu_tx_en = 0;
329  	memset(param.sounding_sts, 0, 6);
330  	memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
331  	memcpy(param.given_user_pos, conf->mu_group.position, 16);
332  	rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
333  		param.given_gid_tab[0], param.given_user_pos[0],
334  		param.given_user_pos[1]);
335  
336  	rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
337  		param.given_gid_tab[1], param.given_user_pos[2],
338  		param.given_user_pos[3]);
339  
340  	rtw_bf_cfg_mu_bfee(rtwdev, &param);
341  }
342  EXPORT_SYMBOL(rtw_bf_set_gid_table);
343  
rtw_bf_phy_init(struct rtw_dev * rtwdev)344  void rtw_bf_phy_init(struct rtw_dev *rtwdev)
345  {
346  	u8 tmp8;
347  	u32 tmp32;
348  	u8 retry_limit = 0xA;
349  	u8 ndpa_rate = 0x10;
350  	u8 ack_policy = 3;
351  
352  	tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
353  	/* Enable P1 aggr new packet according to P0 transfer time */
354  	tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
355  	/* MU Retry Limit */
356  	tmp32 &= ~BIT_MASK_R_MU_RL;
357  	tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
358  	/* Disable Tx MU-MIMO until sounding done */
359  	tmp32 &= ~BIT_EN_MU_MIMO;
360  	/* Clear validity of MU STAs */
361  	tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
362  	rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
363  
364  	/* MU-MIMO Option as default value */
365  	tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
366  	tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
367  	rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
368  
369  	/* MU-MIMO Control as default value */
370  	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
371  	/* Set MU NDPA rate & BW source */
372  	rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
373  	/* Set NDPA Rate */
374  	rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
375  
376  	rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
377  			 DESC_RATE6M);
378  }
379  EXPORT_SYMBOL(rtw_bf_phy_init);
380  
rtw_bf_cfg_csi_rate(struct rtw_dev * rtwdev,u8 rssi,u8 cur_rate,u8 fixrate_en,u8 * new_rate)381  void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
382  			 u8 fixrate_en, u8 *new_rate)
383  {
384  	u32 csi_cfg;
385  	u16 cur_rrsr;
386  
387  	csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
388  	cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
389  
390  	if (rssi >= 40) {
391  		if (cur_rate != DESC_RATE54M) {
392  			cur_rrsr |= BIT(DESC_RATE54M);
393  			csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
394  				   BIT_SHIFT_CSI_RATE;
395  			rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
396  			rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
397  		}
398  		*new_rate = DESC_RATE54M;
399  	} else {
400  		if (cur_rate != DESC_RATE24M) {
401  			cur_rrsr &= ~BIT(DESC_RATE54M);
402  			csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
403  				   BIT_SHIFT_CSI_RATE;
404  			rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
405  			rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
406  		}
407  		*new_rate = DESC_RATE24M;
408  	}
409  }
410  EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
411