1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9 #ifndef _HW_H_ 10 #define _HW_H_ 11 12 #include "targaddrs.h" 13 14 enum ath10k_bus { 15 ATH10K_BUS_PCI, 16 ATH10K_BUS_AHB, 17 ATH10K_BUS_SDIO, 18 ATH10K_BUS_USB, 19 ATH10K_BUS_SNOC, 20 }; 21 22 #define ATH10K_FW_DIR "ath10k" 23 24 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac) 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA6174_3_2_DEVICE_ID (0x0042) 29 #define QCA99X0_2_0_DEVICE_ID (0x0040) 30 #define QCA9888_2_0_DEVICE_ID (0x0056) 31 #define QCA9984_1_0_DEVICE_ID (0x0046) 32 #define QCA9377_1_0_DEVICE_ID (0x0042) 33 #define QCA9887_1_0_DEVICE_ID (0x0050) 34 35 /* QCA988X 1.0 definitions (unsupported) */ 36 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 37 38 /* QCA988X 2.0 definitions */ 39 #define QCA988X_HW_2_0_VERSION 0x4100016c 40 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 41 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 49 50 /* QCA6174 target BMI version signatures */ 51 #define QCA6174_HW_1_0_VERSION 0x05000000 52 #define QCA6174_HW_1_1_VERSION 0x05000001 53 #define QCA6174_HW_1_3_VERSION 0x05000003 54 #define QCA6174_HW_2_1_VERSION 0x05010000 55 #define QCA6174_HW_3_0_VERSION 0x05020000 56 #define QCA6174_HW_3_2_VERSION 0x05030000 57 58 /* QCA9377 target BMI version signatures */ 59 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 60 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 61 62 enum qca6174_pci_rev { 63 QCA6174_PCI_REV_1_1 = 0x11, 64 QCA6174_PCI_REV_1_3 = 0x13, 65 QCA6174_PCI_REV_2_0 = 0x20, 66 QCA6174_PCI_REV_3_0 = 0x30, 67 }; 68 69 enum qca6174_chip_id_rev { 70 QCA6174_HW_1_0_CHIP_ID_REV = 0, 71 QCA6174_HW_1_1_CHIP_ID_REV = 1, 72 QCA6174_HW_1_3_CHIP_ID_REV = 2, 73 QCA6174_HW_2_1_CHIP_ID_REV = 4, 74 QCA6174_HW_2_2_CHIP_ID_REV = 5, 75 QCA6174_HW_3_0_CHIP_ID_REV = 8, 76 QCA6174_HW_3_1_CHIP_ID_REV = 9, 77 QCA6174_HW_3_2_CHIP_ID_REV = 10, 78 }; 79 80 enum qca9377_chip_id_rev { 81 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 82 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 83 }; 84 85 #define QCA6174_HW_2_1_FW_DIR ATH10K_FW_DIR "/QCA6174/hw2.1" 86 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 87 88 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0" 89 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 90 91 /* QCA99X0 1.0 definitions (unsupported) */ 92 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 93 94 /* QCA99X0 2.0 definitions */ 95 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 96 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 97 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 98 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 99 100 /* QCA9984 1.0 defines */ 101 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 102 #define QCA9984_HW_DEV_TYPE 0xa 103 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 104 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 105 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 106 107 /* QCA9888 2.0 defines */ 108 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 109 #define QCA9888_HW_DEV_TYPE 0xc 110 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 111 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 112 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 113 114 /* QCA9377 1.0 definitions */ 115 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 116 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 117 118 /* QCA4019 1.0 definitions */ 119 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 120 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 121 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 122 123 /* WCN3990 1.0 definitions */ 124 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 125 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0" 126 127 #define ATH10K_FW_FILE_BASE "firmware" 128 #define ATH10K_FW_API_MAX 6 129 #define ATH10K_FW_API_MIN 2 130 131 #define ATH10K_FW_API2_FILE "firmware-2.bin" 132 #define ATH10K_FW_API3_FILE "firmware-3.bin" 133 134 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 135 #define ATH10K_FW_API4_FILE "firmware-4.bin" 136 137 /* HTT id conflict fix for management frames over HTT */ 138 #define ATH10K_FW_API5_FILE "firmware-5.bin" 139 140 /* the firmware-6.bin blob */ 141 #define ATH10K_FW_API6_FILE "firmware-6.bin" 142 143 #define ATH10K_FW_UTF_FILE "utf.bin" 144 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 145 146 #define ATH10K_FW_UTF_FILE_BASE "utf" 147 148 /* includes also the null byte */ 149 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 150 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 151 152 #define ATH10K_BOARD_DATA_FILE "board.bin" 153 #define ATH10K_BOARD_API2_FILE "board-2.bin" 154 #define ATH10K_EBOARD_DATA_FILE "eboard.bin" 155 156 #define REG_DUMP_COUNT_QCA988X 60 157 158 struct ath10k_fw_ie { 159 __le32 id; 160 __le32 len; 161 u8 data[]; 162 }; 163 164 enum ath10k_fw_ie_type { 165 ATH10K_FW_IE_FW_VERSION = 0, 166 ATH10K_FW_IE_TIMESTAMP = 1, 167 ATH10K_FW_IE_FEATURES = 2, 168 ATH10K_FW_IE_FW_IMAGE = 3, 169 ATH10K_FW_IE_OTP_IMAGE = 4, 170 171 /* WMI "operations" interface version, 32 bit value. Supported from 172 * FW API 4 and above. 173 */ 174 ATH10K_FW_IE_WMI_OP_VERSION = 5, 175 176 /* HTT "operations" interface version, 32 bit value. Supported from 177 * FW API 5 and above. 178 */ 179 ATH10K_FW_IE_HTT_OP_VERSION = 6, 180 181 /* Code swap image for firmware binary */ 182 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 183 }; 184 185 enum ath10k_fw_wmi_op_version { 186 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 187 188 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 189 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 190 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 191 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 192 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 193 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 194 195 /* keep last */ 196 ATH10K_FW_WMI_OP_VERSION_MAX, 197 }; 198 199 enum ath10k_fw_htt_op_version { 200 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 201 202 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 203 204 /* also used in 10.2 and 10.2.4 branches */ 205 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 206 207 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 208 209 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 210 211 /* keep last */ 212 ATH10K_FW_HTT_OP_VERSION_MAX, 213 }; 214 215 enum ath10k_bd_ie_type { 216 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 217 ATH10K_BD_IE_BOARD = 0, 218 ATH10K_BD_IE_BOARD_EXT = 1, 219 }; 220 221 enum ath10k_bd_ie_board_type { 222 ATH10K_BD_IE_BOARD_NAME = 0, 223 ATH10K_BD_IE_BOARD_DATA = 1, 224 }; 225 226 enum ath10k_hw_rev { 227 ATH10K_HW_QCA988X, 228 ATH10K_HW_QCA6174, 229 ATH10K_HW_QCA99X0, 230 ATH10K_HW_QCA9888, 231 ATH10K_HW_QCA9984, 232 ATH10K_HW_QCA9377, 233 ATH10K_HW_QCA4019, 234 ATH10K_HW_QCA9887, 235 ATH10K_HW_WCN3990, 236 }; 237 238 struct ath10k_hw_regs { 239 u32 rtc_soc_base_address; 240 u32 rtc_wmac_base_address; 241 u32 soc_core_base_address; 242 u32 wlan_mac_base_address; 243 u32 ce_wrapper_base_address; 244 u32 ce0_base_address; 245 u32 ce1_base_address; 246 u32 ce2_base_address; 247 u32 ce3_base_address; 248 u32 ce4_base_address; 249 u32 ce5_base_address; 250 u32 ce6_base_address; 251 u32 ce7_base_address; 252 u32 ce8_base_address; 253 u32 ce9_base_address; 254 u32 ce10_base_address; 255 u32 ce11_base_address; 256 u32 soc_reset_control_si0_rst_mask; 257 u32 soc_reset_control_ce_rst_mask; 258 u32 soc_chip_id_address; 259 u32 scratch_3_address; 260 u32 fw_indicator_address; 261 u32 pcie_local_base_address; 262 u32 ce_wrap_intr_sum_host_msi_lsb; 263 u32 ce_wrap_intr_sum_host_msi_mask; 264 u32 pcie_intr_fw_mask; 265 u32 pcie_intr_ce_mask_all; 266 u32 pcie_intr_clr_address; 267 u32 cpu_pll_init_address; 268 u32 cpu_speed_address; 269 u32 core_clk_div_address; 270 }; 271 272 extern const struct ath10k_hw_regs qca988x_regs; 273 extern const struct ath10k_hw_regs qca6174_regs; 274 extern const struct ath10k_hw_regs qca99x0_regs; 275 extern const struct ath10k_hw_regs qca4019_regs; 276 extern const struct ath10k_hw_regs wcn3990_regs; 277 278 struct ath10k_hw_ce_regs_addr_map { 279 u32 msb; 280 u32 lsb; 281 u32 mask; 282 }; 283 284 struct ath10k_hw_ce_ctrl1 { 285 u32 addr; 286 u32 hw_mask; 287 u32 sw_mask; 288 u32 hw_wr_mask; 289 u32 sw_wr_mask; 290 u32 reset_mask; 291 u32 reset; 292 struct ath10k_hw_ce_regs_addr_map *src_ring; 293 struct ath10k_hw_ce_regs_addr_map *dst_ring; 294 struct ath10k_hw_ce_regs_addr_map *dmax; }; 295 296 struct ath10k_hw_ce_cmd_halt { 297 u32 status_reset; 298 u32 msb; 299 u32 mask; 300 struct ath10k_hw_ce_regs_addr_map *status; }; 301 302 struct ath10k_hw_ce_host_ie { 303 u32 copy_complete_reset; 304 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 305 306 struct ath10k_hw_ce_host_wm_regs { 307 u32 dstr_lmask; 308 u32 dstr_hmask; 309 u32 srcr_lmask; 310 u32 srcr_hmask; 311 u32 cc_mask; 312 u32 wm_mask; 313 u32 addr; 314 }; 315 316 struct ath10k_hw_ce_misc_regs { 317 u32 axi_err; 318 u32 dstr_add_err; 319 u32 srcr_len_err; 320 u32 dstr_mlen_vio; 321 u32 dstr_overflow; 322 u32 srcr_overflow; 323 u32 err_mask; 324 u32 addr; 325 }; 326 327 struct ath10k_hw_ce_dst_src_wm_regs { 328 u32 addr; 329 u32 low_rst; 330 u32 high_rst; 331 struct ath10k_hw_ce_regs_addr_map *wm_low; 332 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 333 334 struct ath10k_hw_ce_ctrl1_upd { 335 u32 shift; 336 u32 mask; 337 u32 enable; 338 }; 339 340 struct ath10k_hw_ce_regs { 341 u32 sr_base_addr_lo; 342 u32 sr_base_addr_hi; 343 u32 sr_size_addr; 344 u32 dr_base_addr_lo; 345 u32 dr_base_addr_hi; 346 u32 dr_size_addr; 347 u32 ce_cmd_addr; 348 u32 misc_ie_addr; 349 u32 sr_wr_index_addr; 350 u32 dst_wr_index_addr; 351 u32 current_srri_addr; 352 u32 current_drri_addr; 353 u32 ddr_addr_for_rri_low; 354 u32 ddr_addr_for_rri_high; 355 u32 ce_rri_low; 356 u32 ce_rri_high; 357 u32 host_ie_addr; 358 struct ath10k_hw_ce_host_wm_regs *wm_regs; 359 struct ath10k_hw_ce_misc_regs *misc_regs; 360 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 361 struct ath10k_hw_ce_cmd_halt *cmd_halt; 362 struct ath10k_hw_ce_host_ie *host_ie; 363 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 364 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; 365 struct ath10k_hw_ce_ctrl1_upd *upd; 366 }; 367 368 struct ath10k_hw_values { 369 u32 rtc_state_val_on; 370 u8 ce_count; 371 u8 msi_assign_ce_max; 372 u8 num_target_ce_config_wlan; 373 u16 ce_desc_meta_data_mask; 374 u8 ce_desc_meta_data_lsb; 375 u32 rfkill_pin; 376 u32 rfkill_cfg; 377 bool rfkill_on_level; 378 }; 379 380 extern const struct ath10k_hw_values qca988x_values; 381 extern const struct ath10k_hw_values qca6174_values; 382 extern const struct ath10k_hw_values qca99x0_values; 383 extern const struct ath10k_hw_values qca9888_values; 384 extern const struct ath10k_hw_values qca4019_values; 385 extern const struct ath10k_hw_values wcn3990_values; 386 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 387 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 388 389 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 390 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 391 392 int ath10k_hw_diag_fast_download(struct ath10k *ar, 393 u32 address, 394 const void *buffer, 395 u32 length); 396 397 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 398 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 399 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 400 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 401 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 402 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 403 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 404 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 405 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 406 407 /* Known peculiarities: 408 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 409 * - raw have FCS, nwifi doesn't 410 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 411 * param, llc/snap) are aligned to 4byte boundaries each 412 */ 413 enum ath10k_hw_txrx_mode { 414 ATH10K_HW_TXRX_RAW = 0, 415 416 /* Native Wifi decap mode is used to align IP frames to 4-byte 417 * boundaries and avoid a very expensive re-alignment in mac80211. 418 */ 419 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 420 ATH10K_HW_TXRX_ETHERNET = 2, 421 422 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 423 ATH10K_HW_TXRX_MGMT = 3, 424 }; 425 426 enum ath10k_mcast2ucast_mode { 427 ATH10K_MCAST2UCAST_DISABLED = 0, 428 ATH10K_MCAST2UCAST_ENABLED = 1, 429 }; 430 431 enum ath10k_hw_rate_ofdm { 432 ATH10K_HW_RATE_OFDM_48M = 0, 433 ATH10K_HW_RATE_OFDM_24M, 434 ATH10K_HW_RATE_OFDM_12M, 435 ATH10K_HW_RATE_OFDM_6M, 436 ATH10K_HW_RATE_OFDM_54M, 437 ATH10K_HW_RATE_OFDM_36M, 438 ATH10K_HW_RATE_OFDM_18M, 439 ATH10K_HW_RATE_OFDM_9M, 440 }; 441 442 enum ath10k_hw_rate_cck { 443 ATH10K_HW_RATE_CCK_LP_11M = 0, 444 ATH10K_HW_RATE_CCK_LP_5_5M, 445 ATH10K_HW_RATE_CCK_LP_2M, 446 ATH10K_HW_RATE_CCK_LP_1M, 447 ATH10K_HW_RATE_CCK_SP_11M, 448 ATH10K_HW_RATE_CCK_SP_5_5M, 449 ATH10K_HW_RATE_CCK_SP_2M, 450 }; 451 452 enum ath10k_hw_rate_rev2_cck { 453 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 454 ATH10K_HW_RATE_REV2_CCK_LP_2M, 455 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 456 ATH10K_HW_RATE_REV2_CCK_LP_11M, 457 ATH10K_HW_RATE_REV2_CCK_SP_2M, 458 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 459 ATH10K_HW_RATE_REV2_CCK_SP_11M, 460 }; 461 462 enum ath10k_hw_cc_wraparound_type { 463 ATH10K_HW_CC_WRAP_DISABLED = 0, 464 465 /* This type is when the HW chip has a quirky Cycle Counter 466 * wraparound which resets to 0x7fffffff instead of 0. All 467 * other CC related counters (e.g. Rx Clear Count) are divided 468 * by 2 so they never wraparound themselves. 469 */ 470 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 471 472 /* Each hw counter wrapsaround independently. When the 473 * counter overflows the repestive counter is right shifted 474 * by 1, i.e reset to 0x7fffffff, and other counters will be 475 * running unaffected. In this type of wraparound, it should 476 * be possible to report accurate Rx busy time unlike the 477 * first type. 478 */ 479 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 480 }; 481 482 enum ath10k_hw_refclk_speed { 483 ATH10K_HW_REFCLK_UNKNOWN = -1, 484 ATH10K_HW_REFCLK_48_MHZ = 0, 485 ATH10K_HW_REFCLK_19_2_MHZ = 1, 486 ATH10K_HW_REFCLK_24_MHZ = 2, 487 ATH10K_HW_REFCLK_26_MHZ = 3, 488 ATH10K_HW_REFCLK_37_4_MHZ = 4, 489 ATH10K_HW_REFCLK_38_4_MHZ = 5, 490 ATH10K_HW_REFCLK_40_MHZ = 6, 491 ATH10K_HW_REFCLK_52_MHZ = 7, 492 493 /* must be the last one */ 494 ATH10K_HW_REFCLK_COUNT, 495 }; 496 497 struct ath10k_hw_clk_params { 498 u32 refclk; 499 u32 div; 500 u32 rnfrac; 501 u32 settle_time; 502 u32 refdiv; 503 u32 outdiv; 504 }; 505 506 struct htt_rx_desc_ops; 507 508 struct ath10k_hw_params { 509 u32 id; 510 u16 dev_id; 511 enum ath10k_bus bus; 512 const char *name; 513 u32 patch_load_addr; 514 int uart_pin; 515 int led_pin; 516 u32 otp_exe_param; 517 518 /* Type of hw cycle counter wraparound logic, for more info 519 * refer enum ath10k_hw_cc_wraparound_type. 520 */ 521 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 522 523 /* Some of chip expects fragment descriptor to be continuous 524 * memory for any TX operation. Set continuous_frag_desc flag 525 * for the hardware which have such requirement. 526 */ 527 bool continuous_frag_desc; 528 529 /* CCK hardware rate table mapping for the newer chipsets 530 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 531 * are in a proper order with respect to the rate/preamble 532 */ 533 bool cck_rate_map_rev2; 534 535 u32 channel_counters_freq_hz; 536 537 /* Mgmt tx descriptors threshold for limiting probe response 538 * frames. 539 */ 540 u32 max_probe_resp_desc_thres; 541 542 u32 tx_chain_mask; 543 u32 rx_chain_mask; 544 u32 max_spatial_stream; 545 u32 cal_data_len; 546 547 struct ath10k_hw_params_fw { 548 const char *dir; 549 size_t board_size; 550 size_t ext_board_size; 551 size_t board_ext_size; 552 } fw; 553 554 /* qca99x0 family chips deliver broadcast/multicast management 555 * frames encrypted and expect software do decryption. 556 */ 557 bool sw_decrypt_mcast_mgmt; 558 559 /* Rx descriptor abstraction */ 560 const struct ath10k_htt_rx_desc_ops *rx_desc_ops; 561 562 const struct ath10k_hw_ops *hw_ops; 563 564 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 565 int decap_align_bytes; 566 567 /* hw specific clock control parameters */ 568 const struct ath10k_hw_clk_params *hw_clk; 569 int target_cpu_freq; 570 571 /* Number of bytes to be discarded for each FFT sample */ 572 int spectral_bin_discard; 573 574 /* The board may have a restricted NSS for 160 or 80+80 vs what it 575 * can do for 80Mhz. 576 */ 577 int vht160_mcs_rx_highest; 578 int vht160_mcs_tx_highest; 579 580 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 581 int n_cipher_suites; 582 583 u32 num_peers; 584 u32 ast_skid_limit; 585 u32 num_wds_entries; 586 587 /* Targets supporting physical addressing capability above 32-bits */ 588 bool target_64bit; 589 590 /* Target rx ring fill level */ 591 u32 rx_ring_fill_level; 592 593 /* target supporting shadow register for ce write */ 594 bool shadow_reg_support; 595 596 /* target supporting retention restore on ddr */ 597 bool rri_on_ddr; 598 599 /* Number of bytes to be the offset for each FFT sample */ 600 int spectral_bin_offset; 601 602 /* targets which require hw filter reset during boot up, 603 * to avoid it sending spurious acks. 604 */ 605 bool hw_filter_reset_required; 606 607 /* target supporting fw download via diag ce */ 608 bool fw_diag_ce_download; 609 610 /* target supporting fw download via large size BMI */ 611 bool bmi_large_size_download; 612 613 /* need to set uart pin if disable uart print, workaround for a 614 * firmware bug 615 */ 616 bool uart_pin_workaround; 617 618 /* Workaround for the credit size calculation */ 619 bool credit_size_workaround; 620 621 /* tx stats support over pktlog */ 622 bool tx_stats_over_pktlog; 623 624 /* provides bitrates for sta_statistics using WMI_TLV_PEER_STATS_INFO_EVENTID */ 625 bool supports_peer_stats_info; 626 627 bool dynamic_sar_support; 628 629 bool hw_restart_disconnect; 630 631 bool use_fw_tx_credits; 632 633 bool delay_unmap_buffer; 634 635 /* The hardware support multicast frame registrations */ 636 bool mcast_frame_registration; 637 }; 638 639 struct htt_resp; 640 struct htt_data_tx_completion_ext; 641 struct htt_rx_ring_rx_desc_offsets; 642 643 /* Defines needed for Rx descriptor abstraction */ 644 struct ath10k_hw_ops { 645 void (*set_coverage_class)(struct ath10k *ar, s16 value); 646 int (*enable_pll_clk)(struct ath10k *ar); 647 int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt); 648 int (*is_rssi_enable)(struct htt_resp *resp); 649 }; 650 651 extern const struct ath10k_hw_ops qca988x_ops; 652 extern const struct ath10k_hw_ops qca99x0_ops; 653 extern const struct ath10k_hw_ops qca6174_ops; 654 extern const struct ath10k_hw_ops qca6174_sdio_ops; 655 extern const struct ath10k_hw_ops wcn3990_ops; 656 657 extern const struct ath10k_hw_clk_params qca6174_clk[]; 658 659 static inline int ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params * hw,struct htt_resp * htt)660 ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw, 661 struct htt_resp *htt) 662 { 663 if (hw->hw_ops->tx_data_rssi_pad_bytes) 664 return hw->hw_ops->tx_data_rssi_pad_bytes(htt); 665 return 0; 666 } 667 668 static inline int ath10k_is_rssi_enable(struct ath10k_hw_params * hw,struct htt_resp * resp)669 ath10k_is_rssi_enable(struct ath10k_hw_params *hw, 670 struct htt_resp *resp) 671 { 672 if (hw->hw_ops->is_rssi_enable) 673 return hw->hw_ops->is_rssi_enable(resp); 674 return 0; 675 } 676 677 /* Target specific defines for MAIN firmware */ 678 #define TARGET_NUM_VDEVS 8 679 #define TARGET_NUM_PEER_AST 2 680 #define TARGET_NUM_WDS_ENTRIES 32 681 #define TARGET_DMA_BURST_SIZE 0 682 #define TARGET_MAC_AGGR_DELIM 0 683 #define TARGET_AST_SKID_LIMIT 16 684 #define TARGET_NUM_STATIONS 16 685 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 686 (TARGET_NUM_VDEVS)) 687 #define TARGET_NUM_OFFLOAD_PEERS 0 688 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 689 #define TARGET_NUM_PEER_KEYS 2 690 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 691 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 692 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 693 #define TARGET_RX_TIMEOUT_LO_PRI 100 694 #define TARGET_RX_TIMEOUT_HI_PRI 40 695 696 #define TARGET_SCAN_MAX_PENDING_REQS 4 697 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 698 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 699 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 700 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 701 #define TARGET_NUM_MCAST_GROUPS 0 702 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 703 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 704 #define TARGET_TX_DBG_LOG_SIZE 1024 705 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 706 #define TARGET_VOW_CONFIG 0 707 #define TARGET_NUM_MSDU_DESC (1024 + 400) 708 #define TARGET_MAX_FRAG_ENTRIES 0 709 710 /* Target specific defines for 10.X firmware */ 711 #define TARGET_10X_NUM_VDEVS 16 712 #define TARGET_10X_NUM_PEER_AST 2 713 #define TARGET_10X_NUM_WDS_ENTRIES 32 714 #define TARGET_10X_DMA_BURST_SIZE 0 715 #define TARGET_10X_MAC_AGGR_DELIM 0 716 #define TARGET_10X_AST_SKID_LIMIT 128 717 #define TARGET_10X_NUM_STATIONS 128 718 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 719 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 720 (TARGET_10X_NUM_VDEVS)) 721 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 722 (TARGET_10X_NUM_VDEVS)) 723 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 724 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 725 #define TARGET_10X_NUM_PEER_KEYS 2 726 #define TARGET_10X_NUM_TIDS_MAX 256 727 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 728 (TARGET_10X_NUM_PEERS) * 2) 729 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 730 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 731 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 732 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 733 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 734 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 735 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 736 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 737 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 738 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 739 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 740 #define TARGET_10X_NUM_MCAST_GROUPS 0 741 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 742 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 743 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 744 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 745 #define TARGET_10X_VOW_CONFIG 0 746 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 747 #define TARGET_10X_MAX_FRAG_ENTRIES 0 748 749 /* 10.2 parameters */ 750 #define TARGET_10_2_DMA_BURST_SIZE 0 751 752 /* Target specific defines for WMI-TLV firmware */ 753 #define TARGET_TLV_NUM_VDEVS 4 754 #define TARGET_TLV_NUM_STATIONS 32 755 #define TARGET_TLV_NUM_PEERS 33 756 #define TARGET_TLV_NUM_TDLS_VDEVS 1 757 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 758 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 759 #define TARGET_TLV_NUM_MSDU_DESC_HL 1024 760 #define TARGET_TLV_NUM_WOW_PATTERNS 22 761 #define TARGET_TLV_MGMT_NUM_MSDU_DESC (50) 762 763 /* Target specific defines for WMI-HL-1.0 firmware */ 764 #define TARGET_HL_TLV_NUM_PEERS 33 765 #define TARGET_HL_TLV_AST_SKID_LIMIT 16 766 #define TARGET_HL_TLV_NUM_WDS_ENTRIES 2 767 768 /* Target specific defines for QCA9377 high latency firmware */ 769 #define TARGET_QCA9377_HL_NUM_PEERS 15 770 771 /* Diagnostic Window */ 772 #define CE_DIAG_PIPE 7 773 774 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 775 776 /* Target specific defines for 10.4 firmware */ 777 #define TARGET_10_4_NUM_VDEVS 16 778 #define TARGET_10_4_NUM_STATIONS 32 779 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 780 (TARGET_10_4_NUM_VDEVS)) 781 #define TARGET_10_4_ACTIVE_PEERS 0 782 783 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 784 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 785 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 786 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 787 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 788 #define TARGET_10_4_NUM_PEER_KEYS 2 789 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 790 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 791 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 792 #define TARGET_10_4_AST_SKID_LIMIT 32 793 794 /* 100 ms for video, best-effort, and background */ 795 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 796 797 /* 40 ms for voice */ 798 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 799 800 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 801 #define TARGET_10_4_SCAN_MAX_REQS 4 802 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 803 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 804 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 805 806 /* Note: mcast to ucast is disabled by default */ 807 #define TARGET_10_4_NUM_MCAST_GROUPS 0 808 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 809 #define TARGET_10_4_MCAST2UCAST_MODE 0 810 811 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 812 #define TARGET_10_4_NUM_WDS_ENTRIES 32 813 #define TARGET_10_4_DMA_BURST_SIZE 1 814 #define TARGET_10_4_MAC_AGGR_DELIM 0 815 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 816 #define TARGET_10_4_VOW_CONFIG 0 817 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 818 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 819 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 820 #define TARGET_10_4_SMART_ANT_CAP 0 821 #define TARGET_10_4_BK_MIN_FREE 0 822 #define TARGET_10_4_BE_MIN_FREE 0 823 #define TARGET_10_4_VI_MIN_FREE 0 824 #define TARGET_10_4_VO_MIN_FREE 0 825 #define TARGET_10_4_RX_BATCH_MODE 1 826 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 827 #define TARGET_10_4_ATF_CONFIG 0 828 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 829 #define TARGET_10_4_QWRAP_CONFIG 0 830 831 /* TDLS config */ 832 #define TARGET_10_4_NUM_TDLS_VDEVS 1 833 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 834 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 835 836 /* Maximum number of Copy Engine's supported */ 837 #define CE_COUNT_MAX 12 838 839 /* Number of Copy Engines supported */ 840 #define CE_COUNT ar->hw_values->ce_count 841 842 /* 843 * Granted MSIs are assigned as follows: 844 * Firmware uses the first 845 * Remaining MSIs, if any, are used by Copy Engines 846 * This mapping is known to both Target firmware and Host software. 847 * It may be changed as long as Host and Target are kept in sync. 848 */ 849 /* MSI for firmware (errors, etc.) */ 850 #define MSI_ASSIGN_FW 0 851 852 /* MSIs for Copy Engines */ 853 #define MSI_ASSIGN_CE_INITIAL 1 854 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 855 856 /* as of IP3.7.1 */ 857 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 858 859 #define RTC_STATE_V_LSB 0 860 #define RTC_STATE_V_MASK 0x00000007 861 #define RTC_STATE_ADDRESS 0x0000 862 #define PCIE_SOC_WAKE_V_MASK 0x00000001 863 #define PCIE_SOC_WAKE_ADDRESS 0x0004 864 #define PCIE_SOC_WAKE_RESET 0x00000000 865 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 866 867 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 868 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 869 #define MAC_COEX_BASE_ADDRESS 0x00006000 870 #define BT_COEX_BASE_ADDRESS 0x00007000 871 #define SOC_PCIE_BASE_ADDRESS 0x00008000 872 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 873 #define WLAN_UART_BASE_ADDRESS 0x0000c000 874 #define WLAN_SI_BASE_ADDRESS 0x00010000 875 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 876 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 877 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 878 #define EFUSE_BASE_ADDRESS 0x00030000 879 #define FPGA_REG_BASE_ADDRESS 0x00039000 880 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 881 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 882 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 883 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 884 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 885 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 886 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 887 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 888 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 889 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 890 #define DBI_BASE_ADDRESS 0x00060000 891 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 892 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 893 894 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 895 #define SOC_RESET_CONTROL_OFFSET 0x00000000 896 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 897 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 898 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 899 #define SOC_CPU_CLOCK_OFFSET 0x00000020 900 #define SOC_CPU_CLOCK_STANDARD_LSB 0 901 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 902 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 903 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 904 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 905 #define SOC_LPO_CAL_OFFSET 0x000000e0 906 #define SOC_LPO_CAL_ENABLE_LSB 20 907 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 908 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 909 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 910 911 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 912 #define SOC_CHIP_ID_REV_LSB 8 913 #define SOC_CHIP_ID_REV_MASK 0x00000f00 914 915 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 916 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 917 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 918 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 919 920 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 921 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 922 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 923 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 924 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 925 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 926 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 927 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 928 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 929 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 930 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 931 932 #define CLOCK_GPIO_OFFSET 0xffffffff 933 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 934 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 935 936 #define SI_CONFIG_OFFSET 0x00000000 937 #define SI_CONFIG_ERR_INT_LSB 19 938 #define SI_CONFIG_ERR_INT_MASK 0x00080000 939 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 940 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 941 #define SI_CONFIG_I2C_LSB 16 942 #define SI_CONFIG_I2C_MASK 0x00010000 943 #define SI_CONFIG_POS_SAMPLE_LSB 7 944 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 945 #define SI_CONFIG_INACTIVE_DATA_LSB 5 946 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 947 #define SI_CONFIG_INACTIVE_CLK_LSB 4 948 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 949 #define SI_CONFIG_DIVIDER_LSB 0 950 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 951 #define SI_CS_OFFSET 0x00000004 952 #define SI_CS_DONE_ERR_LSB 10 953 #define SI_CS_DONE_ERR_MASK 0x00000400 954 #define SI_CS_DONE_INT_LSB 9 955 #define SI_CS_DONE_INT_MASK 0x00000200 956 #define SI_CS_START_LSB 8 957 #define SI_CS_START_MASK 0x00000100 958 #define SI_CS_RX_CNT_LSB 4 959 #define SI_CS_RX_CNT_MASK 0x000000f0 960 #define SI_CS_TX_CNT_LSB 0 961 #define SI_CS_TX_CNT_MASK 0x0000000f 962 963 #define SI_TX_DATA0_OFFSET 0x00000008 964 #define SI_TX_DATA1_OFFSET 0x0000000c 965 #define SI_RX_DATA0_OFFSET 0x00000010 966 #define SI_RX_DATA1_OFFSET 0x00000014 967 968 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 969 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 970 #define CORE_CTRL_ADDRESS 0x0000 971 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 972 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 973 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 974 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 975 #define CPU_INTR_ADDRESS 0x0010 976 #define FW_RAM_CONFIG_ADDRESS 0x0018 977 978 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 979 980 /* Firmware indications to the Host via SCRATCH_3 register. */ 981 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 982 #define FW_IND_EVENT_PENDING 1 983 #define FW_IND_INITIALIZED 2 984 #define FW_IND_HOST_READY 0x80000000 985 986 /* HOST_REG interrupt from firmware */ 987 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 988 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 989 990 #define DRAM_BASE_ADDRESS 0x00400000 991 992 #define PCIE_BAR_REG_ADDRESS 0x40030 993 994 #define MISSING 0 995 996 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 997 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 998 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 999 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 1000 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 1001 #define RESET_CONTROL_MBOX_RST_MASK MISSING 1002 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 1003 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 1004 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 1005 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 1006 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 1007 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 1008 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 1009 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 1010 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 1011 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 1012 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 1013 #define LOCAL_SCRATCH_OFFSET 0x18 1014 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 1015 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 1016 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 1017 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 1018 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 1019 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 1020 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 1021 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 1022 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 1023 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 1024 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 1025 #define MBOX_BASE_ADDRESS MISSING 1026 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 1027 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 1028 #define INT_STATUS_ENABLE_CPU_LSB MISSING 1029 #define INT_STATUS_ENABLE_CPU_MASK MISSING 1030 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 1031 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 1032 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 1033 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 1034 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 1035 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 1036 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 1037 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 1038 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 1039 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 1040 #define INT_STATUS_ENABLE_ADDRESS MISSING 1041 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 1042 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 1043 #define HOST_INT_STATUS_ADDRESS MISSING 1044 #define CPU_INT_STATUS_ADDRESS MISSING 1045 #define ERROR_INT_STATUS_ADDRESS MISSING 1046 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 1047 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 1048 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 1049 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 1050 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 1051 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 1052 #define COUNT_DEC_ADDRESS MISSING 1053 #define HOST_INT_STATUS_CPU_MASK MISSING 1054 #define HOST_INT_STATUS_CPU_LSB MISSING 1055 #define HOST_INT_STATUS_ERROR_MASK MISSING 1056 #define HOST_INT_STATUS_ERROR_LSB MISSING 1057 #define HOST_INT_STATUS_COUNTER_MASK MISSING 1058 #define HOST_INT_STATUS_COUNTER_LSB MISSING 1059 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 1060 #define WINDOW_DATA_ADDRESS MISSING 1061 #define WINDOW_READ_ADDR_ADDRESS MISSING 1062 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 1063 1064 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 1065 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 1066 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 1067 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 1068 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 1069 1070 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 1071 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 1072 #define QCA9887_EEPROM_ADDR_HI_LSB 8 1073 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 1074 #define QCA9887_EEPROM_ADDR_LO_LSB 16 1075 1076 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 1077 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 1078 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 1079 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 1080 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 1081 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 1082 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 1083 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 1084 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 1085 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 1086 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 1087 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 1088 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 1089 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 1090 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 1091 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1092 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1093 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1094 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1095 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1096 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1097 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1098 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1099 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1100 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1101 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1102 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1103 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1104 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1105 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1106 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1107 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1108 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1109 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1110 #define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001 1111 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1112 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1113 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1114 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1115 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1116 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1117 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1118 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1119 #define MBOX_COUNT_ADDRESS 0x00000820 1120 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1121 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1122 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1123 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1124 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1125 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1126 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1127 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1128 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1129 1130 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1131 1132 /* Register definitions for first generation ath10k cards. These cards include 1133 * a mac thich has a register allocation similar to ath9k and at least some 1134 * registers including the ones relevant for modifying the coverage class are 1135 * identical to the ath9k definitions. 1136 * These registers are usually managed by the ath10k firmware. However by 1137 * overriding them it is possible to support coverage class modifications. 1138 */ 1139 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1140 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1141 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1142 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1143 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1144 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1145 1146 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1147 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1148 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1149 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1150 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1151 1152 #define WAVE1_PHYCLK 0x801C 1153 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1154 #define WAVE1_PHYCLK_USEC_LSB 0 1155 1156 /* qca6174 PLL offset/mask */ 1157 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1158 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1159 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1160 1161 #define EFUSE_OFFSET 0x0000032c 1162 #define EFUSE_XTAL_SEL_LSB 8 1163 #define EFUSE_XTAL_SEL_MASK 0x00000700 1164 1165 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1166 #define BB_PLL_CONFIG_FRAC_LSB 0 1167 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1168 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1169 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1170 1171 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1172 #define WLAN_PLL_SETTLE_TIME_LSB 0 1173 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1174 1175 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1176 #define WLAN_PLL_CONTROL_DIV_LSB 0 1177 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1178 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1179 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1180 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1181 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1182 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1183 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1184 1185 #define RTC_SYNC_STATUS_OFFSET 0x0244 1186 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1187 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1188 /* qca6174 PLL offset/mask end */ 1189 1190 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory 1191 * region is accessed. The memory region size is 1M. 1192 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0] 1193 * is 0xX. 1194 * The following MACROs are defined to get the 0xX and the size limit. 1195 */ 1196 #define CPU_ADDR_MSB_REGION_MASK GENMASK(23, 20) 1197 #define CPU_ADDR_MSB_REGION_VAL(X) FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X) 1198 #define REGION_ACCESS_SIZE_LIMIT 0x100000 1199 #define REGION_ACCESS_SIZE_MASK (REGION_ACCESS_SIZE_LIMIT - 1) 1200 1201 #endif /* _HW_H_ */ 1202