1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Allied Vision Technologies GmbH Alvium camera driver
4   *
5   * Copyright (C) 2023 Tommaso Merciai
6   * Copyright (C) 2023 Martin Hecht
7   * Copyright (C) 2023 Avnet EMG GmbH
8   */
9  
10  #ifndef ALVIUM_CSI2_H_
11  #define ALVIUM_CSI2_H_
12  
13  #include <linux/kernel.h>
14  #include <linux/regulator/consumer.h>
15  #include <media/v4l2-cci.h>
16  #include <media/v4l2-common.h>
17  #include <media/v4l2-ctrls.h>
18  #include <media/v4l2-fwnode.h>
19  #include <media/v4l2-subdev.h>
20  
21  #define REG_BCRM_V4L2					BIT(31)
22  
23  #define REG_BCRM_V4L2_8BIT(n)				(REG_BCRM_V4L2 | CCI_REG8(n))
24  #define REG_BCRM_V4L2_16BIT(n)				(REG_BCRM_V4L2 | CCI_REG16(n))
25  #define REG_BCRM_V4L2_32BIT(n)				(REG_BCRM_V4L2 | CCI_REG32(n))
26  #define REG_BCRM_V4L2_64BIT(n)				(REG_BCRM_V4L2 | CCI_REG64(n))
27  
28  /* Basic Control Register Map register offsets (BCRM) */
29  #define REG_BCRM_MINOR_VERSION_R			CCI_REG16(0x0000)
30  #define REG_BCRM_MAJOR_VERSION_R			CCI_REG16(0x0002)
31  #define REG_BCRM_REG_ADDR_R				CCI_REG16(0x0014)
32  
33  #define REG_BCRM_FEATURE_INQUIRY_R			REG_BCRM_V4L2_64BIT(0x0008)
34  #define REG_BCRM_DEVICE_FW				REG_BCRM_V4L2_64BIT(0x0010)
35  #define REG_BCRM_WRITE_HANDSHAKE_RW			REG_BCRM_V4L2_8BIT(0x0018)
36  
37  /* Streaming Control Registers */
38  #define REG_BCRM_SUPPORTED_CSI2_LANE_COUNTS_R		REG_BCRM_V4L2_8BIT(0x0040)
39  #define REG_BCRM_CSI2_LANE_COUNT_RW			REG_BCRM_V4L2_8BIT(0x0044)
40  #define REG_BCRM_CSI2_CLOCK_MIN_R			REG_BCRM_V4L2_32BIT(0x0048)
41  #define REG_BCRM_CSI2_CLOCK_MAX_R			REG_BCRM_V4L2_32BIT(0x004c)
42  #define REG_BCRM_CSI2_CLOCK_RW				REG_BCRM_V4L2_32BIT(0x0050)
43  #define REG_BCRM_BUFFER_SIZE_R				REG_BCRM_V4L2_32BIT(0x0054)
44  
45  #define REG_BCRM_IPU_X_MIN_W				REG_BCRM_V4L2_32BIT(0x0058)
46  #define REG_BCRM_IPU_X_MAX_W				REG_BCRM_V4L2_32BIT(0x005c)
47  #define REG_BCRM_IPU_X_INC_W				REG_BCRM_V4L2_32BIT(0x0060)
48  #define REG_BCRM_IPU_Y_MIN_W				REG_BCRM_V4L2_32BIT(0x0064)
49  #define REG_BCRM_IPU_Y_MAX_W				REG_BCRM_V4L2_32BIT(0x0068)
50  #define REG_BCRM_IPU_Y_INC_W				REG_BCRM_V4L2_32BIT(0x006c)
51  #define REG_BCRM_IPU_X_R				REG_BCRM_V4L2_32BIT(0x0070)
52  #define REG_BCRM_IPU_Y_R				REG_BCRM_V4L2_32BIT(0x0074)
53  
54  #define REG_BCRM_PHY_RESET_RW				REG_BCRM_V4L2_8BIT(0x0078)
55  #define REG_BCRM_LP2HS_DELAY_RW				REG_BCRM_V4L2_32BIT(0x007c)
56  
57  /* Acquisition Control Registers */
58  #define REG_BCRM_ACQUISITION_START_RW			REG_BCRM_V4L2_8BIT(0x0080)
59  #define REG_BCRM_ACQUISITION_STOP_RW			REG_BCRM_V4L2_8BIT(0x0084)
60  #define REG_BCRM_ACQUISITION_ABORT_RW			REG_BCRM_V4L2_8BIT(0x0088)
61  #define REG_BCRM_ACQUISITION_STATUS_R			REG_BCRM_V4L2_8BIT(0x008c)
62  #define REG_BCRM_ACQUISITION_FRAME_RATE_RW		REG_BCRM_V4L2_64BIT(0x0090)
63  #define REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R		REG_BCRM_V4L2_64BIT(0x0098)
64  #define REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R		REG_BCRM_V4L2_64BIT(0x00a0)
65  #define REG_BCRM_ACQUISITION_FRAME_RATE_INC_R		REG_BCRM_V4L2_64BIT(0x00a8)
66  #define REG_BCRM_ACQUISITION_FRAME_RATE_EN_RW		REG_BCRM_V4L2_8BIT(0x00b0)
67  
68  #define REG_BCRM_FRAME_START_TRIGGER_MODE_RW		REG_BCRM_V4L2_8BIT(0x00b4)
69  #define REG_BCRM_FRAME_START_TRIGGER_SOURCE_RW		REG_BCRM_V4L2_8BIT(0x00b8)
70  #define REG_BCRM_FRAME_START_TRIGGER_ACTIVATION_RW	REG_BCRM_V4L2_8BIT(0x00bc)
71  #define REG_BCRM_FRAME_START_TRIGGER_SOFTWARE_W		REG_BCRM_V4L2_8BIT(0x00c0)
72  #define REG_BCRM_FRAME_START_TRIGGER_DELAY_RW		REG_BCRM_V4L2_32BIT(0x00c4)
73  #define REG_BCRM_EXPOSURE_ACTIVE_LINE_MODE_RW		REG_BCRM_V4L2_8BIT(0x00c8)
74  #define REG_BCRM_EXPOSURE_ACTIVE_LINE_SELECTOR_RW	REG_BCRM_V4L2_8BIT(0x00cc)
75  #define REG_BCRM_LINE_CONFIGURATION_RW			REG_BCRM_V4L2_32BIT(0x00d0)
76  
77  #define REG_BCRM_IMG_WIDTH_RW				REG_BCRM_V4L2_32BIT(0x0100)
78  #define REG_BCRM_IMG_WIDTH_MIN_R			REG_BCRM_V4L2_32BIT(0x0104)
79  #define REG_BCRM_IMG_WIDTH_MAX_R			REG_BCRM_V4L2_32BIT(0x0108)
80  #define REG_BCRM_IMG_WIDTH_INC_R			REG_BCRM_V4L2_32BIT(0x010c)
81  
82  #define REG_BCRM_IMG_HEIGHT_RW				REG_BCRM_V4L2_32BIT(0x0110)
83  #define REG_BCRM_IMG_HEIGHT_MIN_R			REG_BCRM_V4L2_32BIT(0x0114)
84  #define REG_BCRM_IMG_HEIGHT_MAX_R			REG_BCRM_V4L2_32BIT(0x0118)
85  #define REG_BCRM_IMG_HEIGHT_INC_R			REG_BCRM_V4L2_32BIT(0x011c)
86  
87  #define REG_BCRM_IMG_OFFSET_X_RW			REG_BCRM_V4L2_32BIT(0x0120)
88  #define REG_BCRM_IMG_OFFSET_X_MIN_R			REG_BCRM_V4L2_32BIT(0x0124)
89  #define REG_BCRM_IMG_OFFSET_X_MAX_R			REG_BCRM_V4L2_32BIT(0x0128)
90  #define REG_BCRM_IMG_OFFSET_X_INC_R			REG_BCRM_V4L2_32BIT(0x012c)
91  
92  #define REG_BCRM_IMG_OFFSET_Y_RW			REG_BCRM_V4L2_32BIT(0x0130)
93  #define REG_BCRM_IMG_OFFSET_Y_MIN_R			REG_BCRM_V4L2_32BIT(0x0134)
94  #define REG_BCRM_IMG_OFFSET_Y_MAX_R			REG_BCRM_V4L2_32BIT(0x0138)
95  #define REG_BCRM_IMG_OFFSET_Y_INC_R			REG_BCRM_V4L2_32BIT(0x013c)
96  
97  #define REG_BCRM_IMG_MIPI_DATA_FORMAT_RW		REG_BCRM_V4L2_32BIT(0x0140)
98  #define REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R	REG_BCRM_V4L2_64BIT(0x0148)
99  #define REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R		REG_BCRM_V4L2_8BIT(0x0150)
100  #define REG_BCRM_IMG_BAYER_PATTERN_RW			REG_BCRM_V4L2_8BIT(0x0154)
101  #define REG_BCRM_IMG_REVERSE_X_RW			REG_BCRM_V4L2_8BIT(0x0158)
102  #define REG_BCRM_IMG_REVERSE_Y_RW			REG_BCRM_V4L2_8BIT(0x015c)
103  
104  #define REG_BCRM_SENSOR_WIDTH_R				REG_BCRM_V4L2_32BIT(0x0160)
105  #define REG_BCRM_SENSOR_HEIGHT_R			REG_BCRM_V4L2_32BIT(0x0164)
106  #define REG_BCRM_WIDTH_MAX_R				REG_BCRM_V4L2_32BIT(0x0168)
107  #define REG_BCRM_HEIGHT_MAX_R				REG_BCRM_V4L2_32BIT(0x016c)
108  
109  #define REG_BCRM_EXPOSURE_TIME_RW			REG_BCRM_V4L2_64BIT(0x0180)
110  #define REG_BCRM_EXPOSURE_TIME_MIN_R			REG_BCRM_V4L2_64BIT(0x0188)
111  #define REG_BCRM_EXPOSURE_TIME_MAX_R			REG_BCRM_V4L2_64BIT(0x0190)
112  #define REG_BCRM_EXPOSURE_TIME_INC_R			REG_BCRM_V4L2_64BIT(0x0198)
113  #define REG_BCRM_EXPOSURE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x01a0)
114  
115  #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_RW		REG_BCRM_V4L2_8BIT(0x01a4)
116  #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_VALUE_RW	REG_BCRM_V4L2_32BIT(0x01a8)
117  #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MIN_R	REG_BCRM_V4L2_32BIT(0x01ac)
118  #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MAX_R	REG_BCRM_V4L2_32BIT(0x01b0)
119  #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_INC_R	REG_BCRM_V4L2_32BIT(0x01b4)
120  
121  #define REG_BCRM_BLACK_LEVEL_RW				REG_BCRM_V4L2_32BIT(0x01b8)
122  #define REG_BCRM_BLACK_LEVEL_MIN_R			REG_BCRM_V4L2_32BIT(0x01bc)
123  #define REG_BCRM_BLACK_LEVEL_MAX_R			REG_BCRM_V4L2_32BIT(0x01c0)
124  #define REG_BCRM_BLACK_LEVEL_INC_R			REG_BCRM_V4L2_32BIT(0x01c4)
125  
126  #define REG_BCRM_GAIN_RW				REG_BCRM_V4L2_64BIT(0x01c8)
127  #define REG_BCRM_GAIN_MIN_R				REG_BCRM_V4L2_64BIT(0x01d0)
128  #define REG_BCRM_GAIN_MAX_R				REG_BCRM_V4L2_64BIT(0x01d8)
129  #define REG_BCRM_GAIN_INC_R				REG_BCRM_V4L2_64BIT(0x01e0)
130  #define REG_BCRM_GAIN_AUTO_RW				REG_BCRM_V4L2_8BIT(0x01e8)
131  
132  #define REG_BCRM_GAMMA_RW				REG_BCRM_V4L2_64BIT(0x01f0)
133  #define REG_BCRM_GAMMA_MIN_R				REG_BCRM_V4L2_64BIT(0x01f8)
134  #define REG_BCRM_GAMMA_MAX_R				REG_BCRM_V4L2_64BIT(0x0200)
135  #define REG_BCRM_GAMMA_INC_R				REG_BCRM_V4L2_64BIT(0x0208)
136  
137  #define REG_BCRM_CONTRAST_VALUE_RW			REG_BCRM_V4L2_32BIT(0x0214)
138  #define REG_BCRM_CONTRAST_VALUE_MIN_R			REG_BCRM_V4L2_32BIT(0x0218)
139  #define REG_BCRM_CONTRAST_VALUE_MAX_R			REG_BCRM_V4L2_32BIT(0x021c)
140  #define REG_BCRM_CONTRAST_VALUE_INC_R			REG_BCRM_V4L2_32BIT(0x0220)
141  
142  #define REG_BCRM_SATURATION_RW				REG_BCRM_V4L2_32BIT(0x0240)
143  #define REG_BCRM_SATURATION_MIN_R			REG_BCRM_V4L2_32BIT(0x0244)
144  #define REG_BCRM_SATURATION_MAX_R			REG_BCRM_V4L2_32BIT(0x0248)
145  #define REG_BCRM_SATURATION_INC_R			REG_BCRM_V4L2_32BIT(0x024c)
146  
147  #define REG_BCRM_HUE_RW					REG_BCRM_V4L2_32BIT(0x0250)
148  #define REG_BCRM_HUE_MIN_R				REG_BCRM_V4L2_32BIT(0x0254)
149  #define REG_BCRM_HUE_MAX_R				REG_BCRM_V4L2_32BIT(0x0258)
150  #define REG_BCRM_HUE_INC_R				REG_BCRM_V4L2_32BIT(0x025c)
151  
152  #define REG_BCRM_ALL_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0260)
153  #define REG_BCRM_ALL_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0268)
154  #define REG_BCRM_ALL_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0270)
155  #define REG_BCRM_ALL_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0278)
156  
157  #define REG_BCRM_RED_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0280)
158  #define REG_BCRM_RED_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0288)
159  #define REG_BCRM_RED_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0290)
160  #define REG_BCRM_RED_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0298)
161  
162  #define REG_BCRM_GREEN_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02a0)
163  #define REG_BCRM_GREEN_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02a8)
164  #define REG_BCRM_GREEN_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02b0)
165  #define REG_BCRM_GREEN_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02b8)
166  
167  #define REG_BCRM_BLUE_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02c0)
168  #define REG_BCRM_BLUE_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02c8)
169  #define REG_BCRM_BLUE_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02d0)
170  #define REG_BCRM_BLUE_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02d8)
171  
172  #define REG_BCRM_WHITE_BALANCE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x02e0)
173  #define REG_BCRM_SHARPNESS_RW				REG_BCRM_V4L2_32BIT(0x0300)
174  #define REG_BCRM_SHARPNESS_MIN_R			REG_BCRM_V4L2_32BIT(0x0304)
175  #define REG_BCRM_SHARPNESS_MAX_R			REG_BCRM_V4L2_32BIT(0x0308)
176  #define REG_BCRM_SHARPNESS_INC_R			REG_BCRM_V4L2_32BIT(0x030c)
177  
178  #define REG_BCRM_DEVICE_TEMPERATURE_R			REG_BCRM_V4L2_32BIT(0x0310)
179  #define REG_BCRM_EXPOSURE_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0330)
180  #define REG_BCRM_EXPOSURE_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0338)
181  #define REG_BCRM_GAIN_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0340)
182  #define REG_BCRM_GAIN_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0348)
183  
184  /* Heartbeat reg*/
185  #define REG_BCRM_HEARTBEAT_RW				CCI_REG8(0x021f)
186  
187  /* GenCP Registers */
188  #define REG_GENCP_CHANGEMODE_W				CCI_REG8(0x021c)
189  #define REG_GENCP_CURRENTMODE_R				CCI_REG8(0x021d)
190  #define REG_GENCP_IN_HANDSHAKE_RW			CCI_REG8(0x001c)
191  #define REG_GENCP_OUT_SIZE_W				CCI_REG16(0x0020)
192  #define REG_GENCP_IN_SIZE_R				CCI_REG16(0x0024)
193  
194  /* defines */
195  #define REG_BCRM_HANDSHAKE_STATUS_MASK			0x01
196  #define REG_BCRM_HANDSHAKE_AVAILABLE_MASK		0x80
197  
198  #define BCRM_HANDSHAKE_W_DONE_EN_BIT			BIT(0)
199  
200  #define ALVIUM_DEFAULT_FR_HZ				10
201  #define ALVIUM_DEFAULT_PIXEL_RATE_MHZ			148000000
202  
203  #define ALVIUM_LP2HS_DELAY_MS				100
204  
205  #define BCRM_DEVICE_FW_MAJOR_MASK			GENMASK_ULL(15, 8)
206  #define BCRM_DEVICE_FW_MAJOR_SHIFT			8
207  #define BCRM_DEVICE_FW_MINOR_MASK			GENMASK_ULL(31, 16)
208  #define BCRM_DEVICE_FW_MINOR_SHIFT			16
209  #define BCRM_DEVICE_FW_PATCH_MASK			GENMASK_ULL(63, 32)
210  #define BCRM_DEVICE_FW_PATCH_SHIFT			32
211  #define BCRM_DEVICE_FW_SPEC_MASK			GENMASK_ULL(7, 0)
212  #define BCRM_DEVICE_FW_SPEC_SHIFT			0
213  
214  enum alvium_bcrm_mode {
215  	ALVIUM_BCM_MODE,
216  	ALVIUM_GENCP_MODE,
217  	ALVIUM_NUM_MODE
218  };
219  
220  enum alvium_mipi_fmt {
221  	ALVIUM_FMT_UYVY8_2X8 = 0,
222  	ALVIUM_FMT_UYVY8_1X16,
223  	ALVIUM_FMT_YUYV8_1X16,
224  	ALVIUM_FMT_YUYV8_2X8,
225  	ALVIUM_FMT_YUYV10_1X20,
226  	ALVIUM_FMT_RGB888_1X24,
227  	ALVIUM_FMT_RBG888_1X24,
228  	ALVIUM_FMT_BGR888_1X24,
229  	ALVIUM_FMT_RGB888_3X8,
230  	ALVIUM_FMT_Y8_1X8,
231  	ALVIUM_FMT_SGRBG8_1X8,
232  	ALVIUM_FMT_SRGGB8_1X8,
233  	ALVIUM_FMT_SGBRG8_1X8,
234  	ALVIUM_FMT_SBGGR8_1X8,
235  	ALVIUM_FMT_Y10_1X10,
236  	ALVIUM_FMT_SGRBG10_1X10,
237  	ALVIUM_FMT_SRGGB10_1X10,
238  	ALVIUM_FMT_SGBRG10_1X10,
239  	ALVIUM_FMT_SBGGR10_1X10,
240  	ALVIUM_FMT_Y12_1X12,
241  	ALVIUM_FMT_SGRBG12_1X12,
242  	ALVIUM_FMT_SRGGB12_1X12,
243  	ALVIUM_FMT_SGBRG12_1X12,
244  	ALVIUM_FMT_SBGGR12_1X12,
245  	ALVIUM_FMT_SBGGR14_1X14,
246  	ALVIUM_FMT_SGBRG14_1X14,
247  	ALVIUM_FMT_SRGGB14_1X14,
248  	ALVIUM_FMT_SGRBG14_1X14,
249  	ALVIUM_NUM_SUPP_MIPI_DATA_FMT
250  };
251  
252  enum alvium_av_bayer_bit {
253  	ALVIUM_BIT_BAY_NONE = -1,
254  	ALVIUM_BIT_BAY_MONO = 0,
255  	ALVIUM_BIT_BAY_GR,
256  	ALVIUM_BIT_BAY_RG,
257  	ALVIUM_BIT_BAY_GB,
258  	ALVIUM_BIT_BAY_BG,
259  	ALVIUM_NUM_BAY_AV_BIT
260  };
261  
262  enum alvium_av_mipi_bit {
263  	ALVIUM_BIT_YUV420_8_LEG = 0,
264  	ALVIUM_BIT_YUV420_8,
265  	ALVIUM_BIT_YUV420_10,
266  	ALVIUM_BIT_YUV420_8_CSPS,
267  	ALVIUM_BIT_YUV420_10_CSPS,
268  	ALVIUM_BIT_YUV422_8,
269  	ALVIUM_BIT_YUV422_10,
270  	ALVIUM_BIT_RGB888,
271  	ALVIUM_BIT_RGB666,
272  	ALVIUM_BIT_RGB565,
273  	ALVIUM_BIT_RGB555,
274  	ALVIUM_BIT_RGB444,
275  	ALVIUM_BIT_RAW6,
276  	ALVIUM_BIT_RAW7,
277  	ALVIUM_BIT_RAW8,
278  	ALVIUM_BIT_RAW10,
279  	ALVIUM_BIT_RAW12,
280  	ALVIUM_BIT_RAW14,
281  	ALVIUM_BIT_JPEG,
282  	ALVIUM_NUM_SUPP_MIPI_DATA_BIT
283  };
284  
285  struct alvium_avail_feat {
286  	u64 rev_x:1;
287  	u64 rev_y:1;
288  	u64 int_autop:1;
289  	u64 black_lvl:1;
290  	u64 gain:1;
291  	u64 gamma:1;
292  	u64 contrast:1;
293  	u64 sat:1;
294  	u64 hue:1;
295  	u64 whiteb:1;
296  	u64 sharp:1;
297  	u64 auto_exp:1;
298  	u64 auto_gain:1;
299  	u64 auto_whiteb:1;
300  	u64 dev_temp:1;
301  	u64 acq_abort:1;
302  	u64 acq_fr:1;
303  	u64 fr_trigger:1;
304  	u64 exp_acq_line:1;
305  	u64 reserved:45;
306  };
307  
308  struct alvium_avail_mipi_fmt {
309  	u64 yuv420_8_leg:1;
310  	u64 yuv420_8:1;
311  	u64 yuv420_10:1;
312  	u64 yuv420_8_csps:1;
313  	u64 yuv420_10_csps:1;
314  	u64 yuv422_8:1;
315  	u64 yuv422_10:1;
316  	u64 rgb888:1;
317  	u64 rgb666:1;
318  	u64 rgb565:1;
319  	u64 rgb555:1;
320  	u64 rgb444:1;
321  	u64 raw6:1;
322  	u64 raw7:1;
323  	u64 raw8:1;
324  	u64 raw10:1;
325  	u64 raw12:1;
326  	u64 raw14:1;
327  	u64 jpeg:1;
328  	u64 reserved:45;
329  };
330  
331  struct alvium_avail_bayer {
332  	u8 mono:1;
333  	u8 gr:1;
334  	u8 rg:1;
335  	u8 gb:1;
336  	u8 bg:1;
337  	u8 reserved:3;
338  };
339  
340  struct alvium_mode {
341  	struct v4l2_rect crop;
342  	struct v4l2_mbus_framefmt fmt;
343  	u32 width;
344  	u32 height;
345  };
346  
347  struct alvium_pixfmt {
348  	u32 code;
349  	u32 colorspace;
350  	u64 mipi_fmt_regval;
351  	u64 bay_fmt_regval;
352  	u8 id;
353  	u8 is_raw;
354  	u8 fmt_av_bit;
355  	u8 bay_av_bit;
356  };
357  
358  struct alvium_ctrls {
359  	struct v4l2_ctrl_handler handler;
360  	struct v4l2_ctrl *pixel_rate;
361  	struct v4l2_ctrl *link_freq;
362  	struct v4l2_ctrl *auto_exp;
363  	struct v4l2_ctrl *exposure;
364  	struct v4l2_ctrl *auto_wb;
365  	struct v4l2_ctrl *blue_balance;
366  	struct v4l2_ctrl *red_balance;
367  	struct v4l2_ctrl *auto_gain;
368  	struct v4l2_ctrl *gain;
369  	struct v4l2_ctrl *saturation;
370  	struct v4l2_ctrl *hue;
371  	struct v4l2_ctrl *contrast;
372  	struct v4l2_ctrl *gamma;
373  	struct v4l2_ctrl *sharpness;
374  	struct v4l2_ctrl *hflip;
375  	struct v4l2_ctrl *vflip;
376  };
377  
378  struct alvium_dev {
379  	struct i2c_client *i2c_client;
380  	struct v4l2_subdev sd;
381  	struct v4l2_fwnode_endpoint ep;
382  	struct media_pad pad;
383  	struct regmap *regmap;
384  
385  	struct regulator *reg_vcc;
386  
387  	u16 bcrm_addr;
388  
389  	struct alvium_avail_feat avail_ft;
390  	u8 is_mipi_fmt_avail[ALVIUM_NUM_SUPP_MIPI_DATA_BIT];
391  	u8 is_bay_avail[ALVIUM_NUM_BAY_AV_BIT];
392  
393  	u32 min_csi_clk;
394  	u32 max_csi_clk;
395  	u32 dft_img_width;
396  	u32 img_min_width;
397  	u32 img_max_width;
398  	u32 img_inc_width;
399  	u32 dft_img_height;
400  	u32 img_min_height;
401  	u32 img_max_height;
402  	u32 img_inc_height;
403  	u32 min_offx;
404  	u32 max_offx;
405  	u32 inc_offx;
406  	u32 min_offy;
407  	u32 max_offy;
408  	u32 inc_offy;
409  	u64 dft_gain;
410  	u64 min_gain;
411  	u64 max_gain;
412  	u64 inc_gain;
413  	u64 dft_exp;
414  	u64 min_exp;
415  	u64 max_exp;
416  	u64 inc_exp;
417  	u64 dft_rbalance;
418  	u64 min_rbalance;
419  	u64 max_rbalance;
420  	u64 inc_rbalance;
421  	u64 dft_bbalance;
422  	u64 min_bbalance;
423  	u64 max_bbalance;
424  	u64 inc_bbalance;
425  	s32 dft_hue;
426  	s32 min_hue;
427  	s32 max_hue;
428  	s32 inc_hue;
429  	u32 dft_contrast;
430  	u32 min_contrast;
431  	u32 max_contrast;
432  	u32 inc_contrast;
433  	u32 dft_sat;
434  	u32 min_sat;
435  	u32 max_sat;
436  	u32 inc_sat;
437  	s32 dft_black_lvl;
438  	s32 min_black_lvl;
439  	s32 max_black_lvl;
440  	s32 inc_black_lvl;
441  	u64 dft_gamma;
442  	u64 min_gamma;
443  	u64 max_gamma;
444  	u64 inc_gamma;
445  	s32 dft_sharp;
446  	s32 min_sharp;
447  	s32 max_sharp;
448  	s32 inc_sharp;
449  
450  	struct alvium_mode mode;
451  
452  	u8 h_sup_csi_lanes;
453  	u64 link_freq;
454  
455  	struct alvium_ctrls ctrls;
456  
457  	u8 bcrm_mode;
458  
459  	struct alvium_pixfmt *alvium_csi2_fmt;
460  	u8 alvium_csi2_fmt_n;
461  
462  	u8 streaming;
463  	u8 apply_fiv;
464  };
465  
sd_to_alvium(struct v4l2_subdev * sd)466  static inline struct alvium_dev *sd_to_alvium(struct v4l2_subdev *sd)
467  {
468  	return container_of_const(sd, struct alvium_dev, sd);
469  }
470  
ctrl_to_sd(struct v4l2_ctrl * ctrl)471  static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
472  {
473  	return &container_of_const(ctrl->handler, struct alvium_dev,
474  					  ctrls.handler)->sd;
475  }
476  #endif /* ALVIUM_CSI2_H_ */
477