1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RCFW_H__ 40 #define __BNXT_QPLIB_RCFW_H__ 41 42 #include "qplib_tlv.h" 43 44 #define RCFW_CMDQ_TRIG_VAL 1 45 #define RCFW_COMM_PCI_BAR_REGION 0 46 #define RCFW_COMM_CONS_PCI_BAR_REGION 2 47 #define RCFW_COMM_BASE_OFFSET 0x600 48 #define RCFW_PF_VF_COMM_PROD_OFFSET 0xc 49 #define RCFW_COMM_TRIG_OFFSET 0x100 50 #define RCFW_COMM_SIZE 0x104 51 52 #define RCFW_DBR_PCI_BAR_REGION 2 53 #define RCFW_DBR_BASE_PAGE_SHIFT 12 54 #define RCFW_FW_STALL_MAX_TIMEOUT 40 55 56 /* Cmdq contains a fix number of a 16-Byte slots */ 57 struct bnxt_qplib_cmdqe { 58 u8 data[16]; 59 }; 60 61 #define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe) 62 bnxt_qplib_rcfw_cmd_prep(struct cmdq_base * req,u8 opcode,u8 cmd_size)63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req, 64 u8 opcode, u8 cmd_size) 65 { 66 req->opcode = opcode; 67 req->cmd_size = cmd_size; 68 } 69 70 /* Shadow queue depth for non blocking command */ 71 #define RCFW_CMD_NON_BLOCKING_SHADOW_QD 64 72 #define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */ 73 74 /* CMDQ elements */ 75 #define BNXT_QPLIB_CMDQE_MAX_CNT 8192 76 #define BNXT_QPLIB_CMDQE_BYTES(depth) ((depth) * BNXT_QPLIB_CMDQE_UNITS) 77 bnxt_qplib_cmdqe_npages(u32 depth)78 static inline u32 bnxt_qplib_cmdqe_npages(u32 depth) 79 { 80 u32 npages; 81 82 npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE; 83 if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE) 84 npages++; 85 return npages; 86 } 87 bnxt_qplib_cmdqe_page_size(u32 depth)88 static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth) 89 { 90 return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE); 91 } 92 93 /* Get the number of command units required for the req. The 94 * function returns correct value only if called before 95 * setting using bnxt_qplib_set_cmd_slots 96 */ bnxt_qplib_get_cmd_slots(struct cmdq_base * req)97 static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req) 98 { 99 u32 cmd_units = 0; 100 101 if (HAS_TLV_HEADER(req)) { 102 struct roce_tlv *tlv_req = (struct roce_tlv *)req; 103 104 cmd_units = tlv_req->total_size; 105 } else { 106 cmd_units = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) / 107 BNXT_QPLIB_CMDQE_UNITS; 108 } 109 110 return cmd_units; 111 } 112 bnxt_qplib_set_cmd_slots(struct cmdq_base * req)113 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req) 114 { 115 u32 cmd_byte = 0; 116 117 if (HAS_TLV_HEADER(req)) { 118 struct roce_tlv *tlv_req = (struct roce_tlv *)req; 119 120 cmd_byte = tlv_req->total_size * BNXT_QPLIB_CMDQE_UNITS; 121 } else { 122 cmd_byte = req->cmd_size; 123 req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) / 124 BNXT_QPLIB_CMDQE_UNITS; 125 } 126 127 return cmd_byte; 128 } 129 130 #define RCFW_MAX_COOKIE_VALUE (BNXT_QPLIB_CMDQE_MAX_CNT - 1) 131 #define RCFW_CMD_IS_BLOCKING 0x8000 132 133 #define HWRM_VERSION_DEV_ATTR_MAX_DPI 0x1000A0000000DULL 134 135 /* Crsq buf is 1024-Byte */ 136 struct bnxt_qplib_crsbe { 137 u8 data[1024]; 138 }; 139 140 /* CREQ */ 141 /* Allocate 1 per QP for async error notification for now */ 142 #define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024) 143 #define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */ 144 #define CREQ_CMP_VALID(hdr, pass) \ 145 (!!((hdr)->v & CREQ_BASE_V) == \ 146 !((pass) & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK)) 147 #define CREQ_ENTRY_POLL_BUDGET 0x100 148 149 /* HWQ */ 150 typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *); 151 152 struct bnxt_qplib_crsqe { 153 struct creq_qp_event *resp; 154 u32 req_size; 155 /* Free slots at the time of submission */ 156 u32 free_slots; 157 u8 opcode; 158 bool is_waiter_alive; 159 bool is_internal_cmd; 160 bool is_in_used; 161 }; 162 163 struct bnxt_qplib_rcfw_sbuf { 164 void *sb; 165 dma_addr_t dma_addr; 166 u32 size; 167 }; 168 169 struct bnxt_qplib_qp_node { 170 u32 qp_id; /* QP id */ 171 void *qp_handle; /* ptr to qplib_qp */ 172 }; 173 174 #define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF 175 176 #define FIRMWARE_INITIALIZED_FLAG (0) 177 #define FIRMWARE_FIRST_FLAG (31) 178 #define FIRMWARE_STALL_DETECTED (3) 179 #define ERR_DEVICE_DETACHED (4) 180 181 struct bnxt_qplib_cmdq_mbox { 182 struct bnxt_qplib_reg_desc reg; 183 void __iomem *prod; 184 void __iomem *db; 185 }; 186 187 struct bnxt_qplib_cmdq_ctx { 188 struct bnxt_qplib_hwq hwq; 189 struct bnxt_qplib_cmdq_mbox cmdq_mbox; 190 wait_queue_head_t waitq; 191 unsigned long flags; 192 unsigned long last_seen; 193 u32 seq_num; 194 }; 195 196 struct bnxt_qplib_creq_db { 197 struct bnxt_qplib_reg_desc reg; 198 struct bnxt_qplib_db_info dbinfo; 199 }; 200 201 struct bnxt_qplib_creq_stat { 202 u64 creq_qp_event_processed; 203 u64 creq_func_event_processed; 204 }; 205 206 struct bnxt_qplib_creq_ctx { 207 struct bnxt_qplib_hwq hwq; 208 struct bnxt_qplib_creq_db creq_db; 209 struct bnxt_qplib_creq_stat stats; 210 struct tasklet_struct creq_tasklet; 211 aeq_handler_t aeq_handler; 212 u16 ring_id; 213 int msix_vec; 214 bool requested; /*irq handler installed */ 215 char *irq_name; 216 }; 217 218 /* RCFW Communication Channels */ 219 struct bnxt_qplib_rcfw { 220 struct pci_dev *pdev; 221 struct bnxt_qplib_res *res; 222 struct bnxt_qplib_cmdq_ctx cmdq; 223 struct bnxt_qplib_creq_ctx creq; 224 struct bnxt_qplib_crsqe *crsqe_tbl; 225 int qp_tbl_size; 226 struct bnxt_qplib_qp_node *qp_tbl; 227 /* To synchronize the qp-handle hash table */ 228 spinlock_t tbl_lock; 229 u64 oos_prev; 230 u32 init_oos_stats; 231 u32 cmdq_depth; 232 atomic_t rcfw_intr_enabled; 233 struct semaphore rcfw_inflight; 234 atomic_t timeout_send; 235 /* cached from chip cctx for quick reference in slow path */ 236 u16 max_timeout; 237 }; 238 239 struct bnxt_qplib_cmdqmsg { 240 struct cmdq_base *req; 241 struct creq_base *resp; 242 void *sb; 243 u32 req_sz; 244 u32 res_sz; 245 u8 block; 246 }; 247 bnxt_qplib_fill_cmdqmsg(struct bnxt_qplib_cmdqmsg * msg,void * req,void * resp,void * sb,u32 req_sz,u32 res_sz,u8 block)248 static inline void bnxt_qplib_fill_cmdqmsg(struct bnxt_qplib_cmdqmsg *msg, 249 void *req, void *resp, void *sb, 250 u32 req_sz, u32 res_sz, u8 block) 251 { 252 msg->req = req; 253 msg->resp = resp; 254 msg->sb = sb; 255 msg->req_sz = req_sz; 256 msg->res_sz = res_sz; 257 msg->block = block; 258 } 259 260 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); 261 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 262 struct bnxt_qplib_rcfw *rcfw, 263 struct bnxt_qplib_ctx *ctx, 264 int qp_tbl_sz); 265 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill); 266 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); 267 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 268 bool need_init); 269 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 270 int msix_vector, 271 int cp_bar_reg_off, 272 aeq_handler_t aeq_handler); 273 274 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 275 struct bnxt_qplib_rcfw *rcfw, 276 u32 size); 277 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 278 struct bnxt_qplib_rcfw_sbuf *sbuf); 279 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 280 struct bnxt_qplib_cmdqmsg *msg); 281 282 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw); 283 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 284 struct bnxt_qplib_ctx *ctx, int is_virtfn); 285 void bnxt_qplib_mark_qp_error(void *qp_handle); map_qp_id_to_tbl_indx(u32 qid,struct bnxt_qplib_rcfw * rcfw)286 static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw) 287 { 288 /* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/ 289 return (qid == 1) ? rcfw->qp_tbl_size - 1 : qid % rcfw->qp_tbl_size - 2; 290 } 291 #endif /* __BNXT_QPLIB_RCFW_H__ */ 292