1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Qualcomm PM8xxx PMIC XOADC driver 4 * 5 * These ADCs are known as HK/XO (house keeping / chrystal oscillator) 6 * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of 7 * specific-purpose and general purpose ADC converters and channels. 8 * 9 * Copyright (C) 2017 Linaro Ltd. 10 * Author: Linus Walleij <linus.walleij@linaro.org> 11 */ 12 13 #include <linux/iio/adc/qcom-vadc-common.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/regulator/consumer.h> 24 25 /* 26 * Definitions for the "user processor" registers lifted from the v3.4 27 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC: 28 * drivers/misc/pmic8058-xoadc.c 29 * drivers/hwmon/pm8xxx-adc.c 30 * None of them contain any complete register specification, so this is 31 * a best effort of combining the information. 32 */ 33 34 /* These appear to be "battery monitor" registers */ 35 #define ADC_ARB_BTM_CNTRL1 0x17e 36 #define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0) 37 #define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1) 38 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2) 39 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3) 40 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4) 41 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5) 42 #define ADC_ARB_BTM_CNTRL1_EOC BIT(6) 43 #define ADC_ARB_BTM_CNTRL1_REQ BIT(7) 44 45 #define ADC_ARB_BTM_AMUX_CNTRL 0x17f 46 #define ADC_ARB_BTM_ANA_PARAM 0x180 47 #define ADC_ARB_BTM_DIG_PARAM 0x181 48 #define ADC_ARB_BTM_RSV 0x182 49 #define ADC_ARB_BTM_DATA1 0x183 50 #define ADC_ARB_BTM_DATA0 0x184 51 #define ADC_ARB_BTM_BAT_COOL_THR1 0x185 52 #define ADC_ARB_BTM_BAT_COOL_THR0 0x186 53 #define ADC_ARB_BTM_BAT_WARM_THR1 0x187 54 #define ADC_ARB_BTM_BAT_WARM_THR0 0x188 55 #define ADC_ARB_BTM_CNTRL2 0x18c 56 57 /* Proper ADC registers */ 58 59 #define ADC_ARB_USRP_CNTRL 0x197 60 #define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0) 61 #define ADC_ARB_USRP_CNTRL_RSV1 BIT(1) 62 #define ADC_ARB_USRP_CNTRL_RSV2 BIT(2) 63 #define ADC_ARB_USRP_CNTRL_RSV3 BIT(3) 64 #define ADC_ARB_USRP_CNTRL_RSV4 BIT(4) 65 #define ADC_ARB_USRP_CNTRL_RSV5 BIT(5) 66 #define ADC_ARB_USRP_CNTRL_EOC BIT(6) 67 #define ADC_ARB_USRP_CNTRL_REQ BIT(7) 68 69 #define ADC_ARB_USRP_AMUX_CNTRL 0x198 70 /* 71 * The channel mask includes the bits selecting channel mux and prescaler 72 * on PM8058, or channel mux and premux on PM8921. 73 */ 74 #define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK 0xfc 75 #define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0) 76 #define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1) 77 /* On PM8058 this is prescaling, on PM8921 this is premux */ 78 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2) 79 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3) 80 #define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4) 81 #define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5) 82 #define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6) 83 #define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7) 84 #define ADC_AMUX_PREMUX_SHIFT 2 85 #define ADC_AMUX_SEL_SHIFT 4 86 87 /* We know very little about the bits in this register */ 88 #define ADC_ARB_USRP_ANA_PARAM 0x199 89 #define ADC_ARB_USRP_ANA_PARAM_DIS 0xFE 90 #define ADC_ARB_USRP_ANA_PARAM_EN 0xFF 91 92 #define ADC_ARB_USRP_DIG_PARAM 0x19A 93 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0) 94 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1) 95 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2) 96 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3) 97 #define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4) 98 /* 99 * On a later ADC the decimation factors are defined as 100 * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this 101 * holds also for this older XOADC. 102 */ 103 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5) 104 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6) 105 #define ADC_ARB_USRP_DIG_PARAM_EN BIT(7) 106 #define ADC_DIG_PARAM_DEC_SHIFT 5 107 108 #define ADC_ARB_USRP_RSV 0x19B 109 #define ADC_ARB_USRP_RSV_RST BIT(0) 110 #define ADC_ARB_USRP_RSV_DTEST0 BIT(1) 111 #define ADC_ARB_USRP_RSV_DTEST1 BIT(2) 112 #define ADC_ARB_USRP_RSV_OP BIT(3) 113 #define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4) 114 #define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5) 115 #define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6) 116 #define ADC_ARB_USRP_RSV_TRM BIT(7) 117 #define ADC_RSV_IP_SEL_SHIFT 4 118 119 #define ADC_ARB_USRP_DATA0 0x19D 120 #define ADC_ARB_USRP_DATA1 0x19C 121 122 /* 123 * Physical channels which MUST exist on all PM variants in order to provide 124 * proper reference points for calibration. 125 * 126 * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel 127 * @PM8XXX_CHANNEL_125V: 1250mV reference channel 128 * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel 129 * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also 130 * measures XO temperature 131 */ 132 #define PM8XXX_CHANNEL_INTERNAL 0x0c 133 #define PM8XXX_CHANNEL_125V 0x0d 134 #define PM8XXX_CHANNEL_INTERNAL_2 0x0e 135 #define PM8XXX_CHANNEL_MUXOFF 0x0f 136 137 /* 138 * PM8058 AMUX premux scaling, two bits. This is done of the channel before 139 * reaching the AMUX. 140 */ 141 #define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */ 142 #define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */ 143 #define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */ 144 145 /* Defines reference voltage for the XOADC */ 146 #define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */ 147 #define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */ 148 #define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */ 149 #define AMUX_RSV3 0x3 /* not used */ 150 #define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */ 151 #define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */ 152 #define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */ 153 154 /** 155 * struct xoadc_channel - encodes channel properties and defaults 156 * @datasheet_name: the hardwarename of this channel 157 * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting 158 * this channel. Both this and the amux channel is needed to uniquely 159 * identify a channel. Values 0..3. 160 * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this 161 * channel, bits 4..7, selects the amux, values 0..f 162 * @prescale: the channels have hard-coded prescale ratios defined 163 * by the hardware, this tells us what it is 164 * @type: corresponding IIO channel type, usually IIO_VOLTAGE or 165 * IIO_TEMP 166 * @scale_fn_type: the liner interpolation etc to convert the 167 * ADC code to the value that IIO expects, in uV or millicelsius 168 * etc. This scale function can be pretty elaborate if different 169 * thermistors are connected or other hardware characteristics are 170 * deployed. 171 * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this 172 * selects the reference voltage for ratiometric scaling 173 */ 174 struct xoadc_channel { 175 const char *datasheet_name; 176 u8 pre_scale_mux:2; 177 u8 amux_channel:4; 178 const struct u32_fract prescale; 179 enum iio_chan_type type; 180 enum vadc_scale_fn_type scale_fn_type; 181 u8 amux_ip_rsv:3; 182 }; 183 184 /** 185 * struct xoadc_variant - encodes the XOADC variant characteristics 186 * @name: name of this PMIC variant 187 * @channels: the hardware channels and respective settings and defaults 188 * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this 189 * is a known problem on PM8058) 190 * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058) 191 * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level 192 * mux 193 */ 194 struct xoadc_variant { 195 const char name[16]; 196 const struct xoadc_channel *channels; 197 bool broken_ratiometric; 198 bool prescaling; 199 bool second_level_mux; 200 }; 201 202 /* 203 * XOADC_CHAN macro parameters: 204 * _dname: the name of the channel 205 * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel 206 * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register 207 * for this channel. On some PMICs some of the bits select a prescaler, and 208 * on some PMICs some of the bits select various complex multiplex settings. 209 * _type: IIO channel type 210 * _prenum: prescaler numerator (dividend) 211 * _preden: prescaler denominator (divisor) 212 * _scale: scaling function type, this selects how the raw valued is mangled 213 * to output the actual processed measurement 214 * _amip: analog mux input parent when using ratiometric measurements 215 */ 216 #define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \ 217 { \ 218 .datasheet_name = __stringify(_dname), \ 219 .pre_scale_mux = _presmux, \ 220 .amux_channel = _amux, \ 221 .prescale = { \ 222 .numerator = _prenum, .denominator = _preden, \ 223 }, \ 224 .type = _type, \ 225 .scale_fn_type = _scale, \ 226 .amux_ip_rsv = _amip, \ 227 } 228 229 /* 230 * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree: 231 * TODO: incomplete, needs testing. 232 */ 233 static const struct xoadc_channel pm8018_xoadc_channels[] = { 234 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 235 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 236 XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 237 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1), 238 /* Used for battery ID or battery temperature */ 239 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2), 240 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 241 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 242 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0), 243 { }, /* Sentinel */ 244 }; 245 246 /* 247 * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree: 248 * TODO: needs testing. 249 */ 250 static const struct xoadc_channel pm8038_xoadc_channels[] = { 251 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 252 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 253 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1), 254 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 255 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 256 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 257 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 258 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 259 /* AMUX8 used for battery temperature in most cases */ 260 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2), 261 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 262 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1), 263 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1), 264 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 265 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 266 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 267 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0), 268 { }, /* Sentinel */ 269 }; 270 271 /* 272 * This was created by cross-referencing the vendor tree 273 * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[] 274 * with the "channel types" (first field) to find the right 275 * configuration for these channels on an MSM8x60 i.e. PM8058 276 * setup. 277 */ 278 static const struct xoadc_channel pm8058_xoadc_channels[] = { 279 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1), 280 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 281 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1), 282 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 283 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 284 /* 285 * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in 286 * some code and documentation. But they are really just 5 287 * channels just like any other. They are connected to a switching 288 * matrix where they can be routed to any of the MPPs, not just 289 * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is 290 * very confusing. 291 */ 292 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 293 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 294 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1), 295 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1), 296 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 297 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 298 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1), 299 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 300 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 301 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 302 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0), 303 /* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */ 304 { }, /* Sentinel */ 305 }; 306 307 /* 308 * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree 309 * include/linux/mfd/pm8xxx/pm8xxx-adc.h 310 * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c 311 */ 312 static const struct xoadc_channel pm8921_xoadc_channels[] = { 313 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 314 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 315 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1), 316 /* channel "ICHG" is reserved and not used on PM8921 */ 317 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 318 XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 319 /* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */ 320 XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1), 321 XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 322 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1), 323 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1), 324 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 325 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 326 /* FIXME: look into the scaling of this temperature */ 327 XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 328 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0), 329 /* The following channels have premux bit 0 set to 1 (all end in 4) */ 330 XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 331 /* Set scaling to 1/2 based on the name for these two */ 332 XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1), 333 XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1), 334 XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 335 XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 336 XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 337 XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 338 XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 339 XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 340 /* Internal test signals, I think */ 341 XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 342 XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 343 XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 344 XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 345 XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 346 XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 347 XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1), 348 /* The following channels have premux bit 1 set to 1 (all end in 8) */ 349 /* I guess even ATEST8 will be divided by 3 here */ 350 XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 351 /* I guess div 2 div 3 becomes div 6 */ 352 XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1), 353 XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1), 354 XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 355 XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 356 XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 357 XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 358 XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 359 XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 360 XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 361 XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 362 XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 363 XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 364 XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 365 XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 366 XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1), 367 { }, /* Sentinel */ 368 }; 369 370 /** 371 * struct pm8xxx_chan_info - ADC channel information 372 * @name: name of this channel 373 * @hwchan: pointer to hardware channel information (muxing & scaling settings) 374 * @calibration: whether to use absolute or ratiometric calibration 375 * @decimation: 0,1,2,3 376 * @amux_ip_rsv: ratiometric scale value if using ratiometric 377 * calibration: 0, 1, 2, 4, 5. 378 */ 379 struct pm8xxx_chan_info { 380 const char *name; 381 const struct xoadc_channel *hwchan; 382 enum vadc_calibration calibration; 383 u8 decimation:2; 384 u8 amux_ip_rsv:3; 385 }; 386 387 /** 388 * struct pm8xxx_xoadc - state container for the XOADC 389 * @dev: pointer to device 390 * @map: regmap to access registers 391 * @variant: XOADC variant characteristics 392 * @vref: reference voltage regulator 393 * characteristics of the channels, and sensible default settings 394 * @nchans: number of channels, configured by the device tree 395 * @chans: the channel information per-channel, configured by the device tree 396 * @iio_chans: IIO channel specifiers 397 * @graph: linear calibration parameters for absolute and 398 * ratiometric measurements 399 * @complete: completion to indicate end of conversion 400 * @lock: lock to restrict access to the hardware to one client at the time 401 */ 402 struct pm8xxx_xoadc { 403 struct device *dev; 404 struct regmap *map; 405 const struct xoadc_variant *variant; 406 struct regulator *vref; 407 unsigned int nchans; 408 struct pm8xxx_chan_info *chans; 409 struct iio_chan_spec *iio_chans; 410 struct vadc_linear_graph graph[2]; 411 struct completion complete; 412 struct mutex lock; 413 }; 414 pm8xxx_eoc_irq(int irq,void * d)415 static irqreturn_t pm8xxx_eoc_irq(int irq, void *d) 416 { 417 struct iio_dev *indio_dev = d; 418 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); 419 420 complete(&adc->complete); 421 422 return IRQ_HANDLED; 423 } 424 425 static struct pm8xxx_chan_info * pm8xxx_get_channel(struct pm8xxx_xoadc * adc,u8 chan)426 pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan) 427 { 428 int i; 429 430 for (i = 0; i < adc->nchans; i++) { 431 struct pm8xxx_chan_info *ch = &adc->chans[i]; 432 if (ch->hwchan->amux_channel == chan) 433 return ch; 434 } 435 return NULL; 436 } 437 pm8xxx_read_channel_rsv(struct pm8xxx_xoadc * adc,const struct pm8xxx_chan_info * ch,u8 rsv,u16 * adc_code,bool force_ratiometric)438 static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc, 439 const struct pm8xxx_chan_info *ch, 440 u8 rsv, u16 *adc_code, 441 bool force_ratiometric) 442 { 443 int ret; 444 unsigned int val; 445 u8 rsvmask, rsvval; 446 u8 lsb, msb; 447 448 dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n", 449 ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv); 450 451 mutex_lock(&adc->lock); 452 453 /* Mux in this channel */ 454 val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT; 455 val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT; 456 ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val); 457 if (ret) 458 goto unlock; 459 460 /* Set up ratiometric scale value, mask off all bits except these */ 461 rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 | 462 ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP); 463 if (adc->variant->broken_ratiometric && !force_ratiometric) { 464 /* 465 * Apparently the PM8058 has some kind of bug which is 466 * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c 467 * which just hardcodes the RSV selector to SEL1 (0x20) for 468 * most cases and SEL0 (0x10) for the MUXOFF channel only. 469 * If we force ratiometric (currently only done when attempting 470 * to do ratiometric calibration) this doesn't seem to work 471 * very well and I suspect ratiometric conversion is simply 472 * broken or not supported on the PM8058. 473 * 474 * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select 475 * the mode alone. 476 * 477 * Some PM8058 register documentation would be nice to get 478 * this right. 479 */ 480 if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF) 481 rsvval = ADC_ARB_USRP_RSV_IP_SEL0; 482 else 483 rsvval = ADC_ARB_USRP_RSV_IP_SEL1; 484 } else { 485 if (rsv == 0xff) 486 rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) | 487 ADC_ARB_USRP_RSV_TRM; 488 else 489 rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) | 490 ADC_ARB_USRP_RSV_TRM; 491 } 492 493 ret = regmap_update_bits(adc->map, 494 ADC_ARB_USRP_RSV, 495 ~rsvmask, 496 rsvval); 497 if (ret) 498 goto unlock; 499 500 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM, 501 ADC_ARB_USRP_ANA_PARAM_DIS); 502 if (ret) 503 goto unlock; 504 505 /* Decimation factor */ 506 ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM, 507 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 | 508 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 | 509 ch->decimation << ADC_DIG_PARAM_DEC_SHIFT); 510 if (ret) 511 goto unlock; 512 513 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM, 514 ADC_ARB_USRP_ANA_PARAM_EN); 515 if (ret) 516 goto unlock; 517 518 /* Enable the arbiter, the Qualcomm code does it twice like this */ 519 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 520 ADC_ARB_USRP_CNTRL_EN_ARB); 521 if (ret) 522 goto unlock; 523 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 524 ADC_ARB_USRP_CNTRL_EN_ARB); 525 if (ret) 526 goto unlock; 527 528 529 /* Fire a request! */ 530 reinit_completion(&adc->complete); 531 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 532 ADC_ARB_USRP_CNTRL_EN_ARB | 533 ADC_ARB_USRP_CNTRL_REQ); 534 if (ret) 535 goto unlock; 536 537 /* Next the interrupt occurs */ 538 ret = wait_for_completion_timeout(&adc->complete, 539 VADC_CONV_TIME_MAX_US); 540 if (!ret) { 541 dev_err(adc->dev, "conversion timed out\n"); 542 ret = -ETIMEDOUT; 543 goto unlock; 544 } 545 546 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val); 547 if (ret) 548 goto unlock; 549 lsb = val; 550 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val); 551 if (ret) 552 goto unlock; 553 msb = val; 554 *adc_code = (msb << 8) | lsb; 555 556 /* Turn off the ADC by setting the arbiter to 0 twice */ 557 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0); 558 if (ret) 559 goto unlock; 560 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0); 561 if (ret) 562 goto unlock; 563 564 unlock: 565 mutex_unlock(&adc->lock); 566 return ret; 567 } 568 pm8xxx_read_channel(struct pm8xxx_xoadc * adc,const struct pm8xxx_chan_info * ch,u16 * adc_code)569 static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc, 570 const struct pm8xxx_chan_info *ch, 571 u16 *adc_code) 572 { 573 /* 574 * Normally we just use the ratiometric scale value (RSV) predefined 575 * for the channel, but during calibration we need to modify this 576 * so this wrapper is a helper hiding the more complex version. 577 */ 578 return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false); 579 } 580 pm8xxx_calibrate_device(struct pm8xxx_xoadc * adc)581 static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc) 582 { 583 const struct pm8xxx_chan_info *ch; 584 u16 read_1250v; 585 u16 read_0625v; 586 u16 read_nomux_rsv5; 587 u16 read_nomux_rsv4; 588 int ret; 589 590 adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV; 591 adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE; 592 593 /* Common reference channel calibration */ 594 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V); 595 if (!ch) 596 return -ENODEV; 597 ret = pm8xxx_read_channel(adc, ch, &read_1250v); 598 if (ret) { 599 dev_err(adc->dev, "could not read 1.25V reference channel\n"); 600 return -ENODEV; 601 } 602 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL); 603 if (!ch) 604 return -ENODEV; 605 ret = pm8xxx_read_channel(adc, ch, &read_0625v); 606 if (ret) { 607 dev_err(adc->dev, "could not read 0.625V reference channel\n"); 608 return -ENODEV; 609 } 610 if (read_1250v == read_0625v) { 611 dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n"); 612 return -ENODEV; 613 } 614 615 adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v; 616 adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v; 617 618 dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n", 619 VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy); 620 621 /* Ratiometric calibration */ 622 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF); 623 if (!ch) 624 return -ENODEV; 625 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5, 626 &read_nomux_rsv5, true); 627 if (ret) { 628 dev_err(adc->dev, "could not read MUXOFF reference channel\n"); 629 return -ENODEV; 630 } 631 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4, 632 &read_nomux_rsv4, true); 633 if (ret) { 634 dev_err(adc->dev, "could not read MUXOFF reference channel\n"); 635 return -ENODEV; 636 } 637 adc->graph[VADC_CALIB_RATIOMETRIC].dy = 638 read_nomux_rsv5 - read_nomux_rsv4; 639 adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4; 640 641 dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n", 642 VADC_RATIOMETRIC_RANGE, 643 adc->graph[VADC_CALIB_RATIOMETRIC].dy); 644 645 return 0; 646 } 647 pm8xxx_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)648 static int pm8xxx_read_raw(struct iio_dev *indio_dev, 649 struct iio_chan_spec const *chan, 650 int *val, int *val2, long mask) 651 { 652 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); 653 const struct pm8xxx_chan_info *ch; 654 u16 adc_code; 655 int ret; 656 657 switch (mask) { 658 case IIO_CHAN_INFO_PROCESSED: 659 ch = pm8xxx_get_channel(adc, chan->address); 660 if (!ch) { 661 dev_err(adc->dev, "no such channel %lu\n", 662 chan->address); 663 return -EINVAL; 664 } 665 ret = pm8xxx_read_channel(adc, ch, &adc_code); 666 if (ret) 667 return ret; 668 669 ret = qcom_vadc_scale(ch->hwchan->scale_fn_type, 670 &adc->graph[ch->calibration], 671 &ch->hwchan->prescale, 672 (ch->calibration == VADC_CALIB_ABSOLUTE), 673 adc_code, val); 674 if (ret) 675 return ret; 676 677 return IIO_VAL_INT; 678 case IIO_CHAN_INFO_RAW: 679 ch = pm8xxx_get_channel(adc, chan->address); 680 if (!ch) { 681 dev_err(adc->dev, "no such channel %lu\n", 682 chan->address); 683 return -EINVAL; 684 } 685 ret = pm8xxx_read_channel(adc, ch, &adc_code); 686 if (ret) 687 return ret; 688 689 *val = (int)adc_code; 690 return IIO_VAL_INT; 691 default: 692 return -EINVAL; 693 } 694 } 695 pm8xxx_fwnode_xlate(struct iio_dev * indio_dev,const struct fwnode_reference_args * iiospec)696 static int pm8xxx_fwnode_xlate(struct iio_dev *indio_dev, 697 const struct fwnode_reference_args *iiospec) 698 { 699 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); 700 u8 pre_scale_mux; 701 u8 amux_channel; 702 unsigned int i; 703 704 /* 705 * First cell is prescaler or premux, second cell is analog 706 * mux. 707 */ 708 if (iiospec->nargs != 2) { 709 dev_err(&indio_dev->dev, "wrong number of arguments for %pfwP need 2 got %d\n", 710 iiospec->fwnode, 711 iiospec->nargs); 712 return -EINVAL; 713 } 714 pre_scale_mux = (u8)iiospec->args[0]; 715 amux_channel = (u8)iiospec->args[1]; 716 dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n", 717 pre_scale_mux, amux_channel); 718 719 /* We need to match exactly on the prescale/premux and channel */ 720 for (i = 0; i < adc->nchans; i++) 721 if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux && 722 adc->chans[i].hwchan->amux_channel == amux_channel) 723 return i; 724 725 return -EINVAL; 726 } 727 728 static const struct iio_info pm8xxx_xoadc_info = { 729 .fwnode_xlate = pm8xxx_fwnode_xlate, 730 .read_raw = pm8xxx_read_raw, 731 }; 732 pm8xxx_xoadc_parse_channel(struct device * dev,struct fwnode_handle * fwnode,const struct xoadc_channel * hw_channels,struct iio_chan_spec * iio_chan,struct pm8xxx_chan_info * ch)733 static int pm8xxx_xoadc_parse_channel(struct device *dev, 734 struct fwnode_handle *fwnode, 735 const struct xoadc_channel *hw_channels, 736 struct iio_chan_spec *iio_chan, 737 struct pm8xxx_chan_info *ch) 738 { 739 const char *name = fwnode_get_name(fwnode); 740 const struct xoadc_channel *hwchan; 741 u32 pre_scale_mux, amux_channel, reg[2]; 742 u32 rsv, dec; 743 int ret; 744 int chid; 745 746 ret = fwnode_property_read_u32_array(fwnode, "reg", reg, 747 ARRAY_SIZE(reg)); 748 if (ret) { 749 dev_err(dev, "invalid pre scale/mux or amux channel number %s\n", 750 name); 751 return ret; 752 } 753 754 pre_scale_mux = reg[0]; 755 amux_channel = reg[1]; 756 757 /* Find the right channel setting */ 758 chid = 0; 759 hwchan = &hw_channels[0]; 760 while (hwchan->datasheet_name) { 761 if (hwchan->pre_scale_mux == pre_scale_mux && 762 hwchan->amux_channel == amux_channel) 763 break; 764 hwchan++; 765 chid++; 766 } 767 /* The sentinel does not have a name assigned */ 768 if (!hwchan->datasheet_name) { 769 dev_err(dev, "could not locate channel %02x/%02x\n", 770 pre_scale_mux, amux_channel); 771 return -EINVAL; 772 } 773 ch->name = name; 774 ch->hwchan = hwchan; 775 /* Everyone seems to use absolute calibration except in special cases */ 776 ch->calibration = VADC_CALIB_ABSOLUTE; 777 /* Everyone seems to use default ("type 2") decimation */ 778 ch->decimation = VADC_DEF_DECIMATION; 779 780 if (!fwnode_property_read_u32(fwnode, "qcom,ratiometric", &rsv)) { 781 ch->calibration = VADC_CALIB_RATIOMETRIC; 782 if (rsv > XOADC_RSV_MAX) { 783 dev_err(dev, "%s too large RSV value %d\n", name, rsv); 784 return -EINVAL; 785 } 786 if (rsv == AMUX_RSV3) { 787 dev_err(dev, "%s invalid RSV value %d\n", name, rsv); 788 return -EINVAL; 789 } 790 } 791 792 /* Optional decimation, if omitted we use the default */ 793 ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &dec); 794 if (!ret) { 795 ret = qcom_vadc_decimation_from_dt(dec); 796 if (ret < 0) { 797 dev_err(dev, "%s invalid decimation %d\n", 798 name, dec); 799 return ret; 800 } 801 ch->decimation = ret; 802 } 803 804 iio_chan->channel = chid; 805 iio_chan->address = hwchan->amux_channel; 806 iio_chan->datasheet_name = hwchan->datasheet_name; 807 iio_chan->type = hwchan->type; 808 /* All channels are raw or processed */ 809 iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 810 BIT(IIO_CHAN_INFO_PROCESSED); 811 iio_chan->indexed = 1; 812 813 dev_dbg(dev, 814 "channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" ref voltage: %d, decimation %d prescale %d/%d, scale function %d\n", 815 hwchan->pre_scale_mux, hwchan->amux_channel, ch->name, 816 ch->amux_ip_rsv, ch->decimation, hwchan->prescale.numerator, 817 hwchan->prescale.denominator, hwchan->scale_fn_type); 818 819 return 0; 820 } 821 pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc * adc)822 static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc) 823 { 824 struct fwnode_handle *child; 825 struct pm8xxx_chan_info *ch; 826 int ret; 827 int i; 828 829 adc->nchans = device_get_child_node_count(adc->dev); 830 if (!adc->nchans) { 831 dev_err(adc->dev, "no channel children\n"); 832 return -ENODEV; 833 } 834 dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans); 835 836 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans, 837 sizeof(*adc->iio_chans), GFP_KERNEL); 838 if (!adc->iio_chans) 839 return -ENOMEM; 840 841 adc->chans = devm_kcalloc(adc->dev, adc->nchans, 842 sizeof(*adc->chans), GFP_KERNEL); 843 if (!adc->chans) 844 return -ENOMEM; 845 846 i = 0; 847 device_for_each_child_node(adc->dev, child) { 848 ch = &adc->chans[i]; 849 ret = pm8xxx_xoadc_parse_channel(adc->dev, child, 850 adc->variant->channels, 851 &adc->iio_chans[i], 852 ch); 853 if (ret) { 854 fwnode_handle_put(child); 855 return ret; 856 } 857 i++; 858 } 859 860 /* Check for required channels */ 861 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V); 862 if (!ch) { 863 dev_err(adc->dev, "missing 1.25V reference channel\n"); 864 return -ENODEV; 865 } 866 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL); 867 if (!ch) { 868 dev_err(adc->dev, "missing 0.625V reference channel\n"); 869 return -ENODEV; 870 } 871 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF); 872 if (!ch) { 873 dev_err(adc->dev, "missing MUXOFF reference channel\n"); 874 return -ENODEV; 875 } 876 877 return 0; 878 } 879 pm8xxx_xoadc_probe(struct platform_device * pdev)880 static int pm8xxx_xoadc_probe(struct platform_device *pdev) 881 { 882 const struct xoadc_variant *variant; 883 struct pm8xxx_xoadc *adc; 884 struct iio_dev *indio_dev; 885 struct regmap *map; 886 struct device *dev = &pdev->dev; 887 int ret; 888 889 variant = device_get_match_data(dev); 890 if (!variant) 891 return -ENODEV; 892 893 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 894 if (!indio_dev) 895 return -ENOMEM; 896 platform_set_drvdata(pdev, indio_dev); 897 898 adc = iio_priv(indio_dev); 899 adc->dev = dev; 900 adc->variant = variant; 901 init_completion(&adc->complete); 902 mutex_init(&adc->lock); 903 904 ret = pm8xxx_xoadc_parse_channels(adc); 905 if (ret) 906 return ret; 907 908 map = dev_get_regmap(dev->parent, NULL); 909 if (!map) { 910 dev_err(dev, "parent regmap unavailable.\n"); 911 return -ENODEV; 912 } 913 adc->map = map; 914 915 /* Bring up regulator */ 916 adc->vref = devm_regulator_get(dev, "xoadc-ref"); 917 if (IS_ERR(adc->vref)) 918 return dev_err_probe(dev, PTR_ERR(adc->vref), 919 "failed to get XOADC VREF regulator\n"); 920 ret = regulator_enable(adc->vref); 921 if (ret) { 922 dev_err(dev, "failed to enable XOADC VREF regulator\n"); 923 return ret; 924 } 925 926 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 927 pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev); 928 if (ret) { 929 dev_err(dev, "unable to request IRQ\n"); 930 goto out_disable_vref; 931 } 932 933 indio_dev->name = variant->name; 934 indio_dev->modes = INDIO_DIRECT_MODE; 935 indio_dev->info = &pm8xxx_xoadc_info; 936 indio_dev->channels = adc->iio_chans; 937 indio_dev->num_channels = adc->nchans; 938 939 ret = iio_device_register(indio_dev); 940 if (ret) 941 goto out_disable_vref; 942 943 ret = pm8xxx_calibrate_device(adc); 944 if (ret) 945 goto out_unreg_device; 946 947 dev_info(dev, "%s XOADC driver enabled\n", variant->name); 948 949 return 0; 950 951 out_unreg_device: 952 iio_device_unregister(indio_dev); 953 out_disable_vref: 954 regulator_disable(adc->vref); 955 956 return ret; 957 } 958 pm8xxx_xoadc_remove(struct platform_device * pdev)959 static void pm8xxx_xoadc_remove(struct platform_device *pdev) 960 { 961 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 962 struct pm8xxx_xoadc *adc = iio_priv(indio_dev); 963 964 iio_device_unregister(indio_dev); 965 966 regulator_disable(adc->vref); 967 } 968 969 static const struct xoadc_variant pm8018_variant = { 970 .name = "PM8018-XOADC", 971 .channels = pm8018_xoadc_channels, 972 }; 973 974 static const struct xoadc_variant pm8038_variant = { 975 .name = "PM8038-XOADC", 976 .channels = pm8038_xoadc_channels, 977 }; 978 979 static const struct xoadc_variant pm8058_variant = { 980 .name = "PM8058-XOADC", 981 .channels = pm8058_xoadc_channels, 982 .broken_ratiometric = true, 983 .prescaling = true, 984 }; 985 986 static const struct xoadc_variant pm8921_variant = { 987 .name = "PM8921-XOADC", 988 .channels = pm8921_xoadc_channels, 989 .second_level_mux = true, 990 }; 991 992 static const struct of_device_id pm8xxx_xoadc_id_table[] = { 993 { 994 .compatible = "qcom,pm8018-adc", 995 .data = &pm8018_variant, 996 }, 997 { 998 .compatible = "qcom,pm8038-adc", 999 .data = &pm8038_variant, 1000 }, 1001 { 1002 .compatible = "qcom,pm8058-adc", 1003 .data = &pm8058_variant, 1004 }, 1005 { 1006 .compatible = "qcom,pm8921-adc", 1007 .data = &pm8921_variant, 1008 }, 1009 { } 1010 }; 1011 MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table); 1012 1013 static struct platform_driver pm8xxx_xoadc_driver = { 1014 .driver = { 1015 .name = "pm8xxx-adc", 1016 .of_match_table = pm8xxx_xoadc_id_table, 1017 }, 1018 .probe = pm8xxx_xoadc_probe, 1019 .remove_new = pm8xxx_xoadc_remove, 1020 }; 1021 module_platform_driver(pm8xxx_xoadc_driver); 1022 1023 MODULE_DESCRIPTION("PM8xxx XOADC driver"); 1024 MODULE_LICENSE("GPL v2"); 1025 MODULE_ALIAS("platform:pm8xxx-xoadc"); 1026