1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "soc15.h"
29
30 #include "oss/osssys_4_2_0_offset.h"
31 #include "oss/osssys_4_2_0_sh_mask.h"
32
33 #include "soc15_common.h"
34 #include "vega20_ih.h"
35
36 #define MAX_REARM_RETRY 10
37
38 #define mmIH_CHICKEN_ALDEBARAN 0x18d
39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45
46 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47
48 /**
49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
50 *
51 * @adev: amdgpu_device pointer
52 *
53 * Initialize register offset ih rings (VEGA20).
54 */
vega20_ih_init_register_offset(struct amdgpu_device * adev)55 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
56 {
57 struct amdgpu_ih_regs *ih_regs;
58
59 if (adev->irq.ih.ring_size) {
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
70 }
71
72 if (adev->irq.ih1.ring_size) {
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
81 }
82
83 if (adev->irq.ih2.ring_size) {
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
92 }
93 }
94
95 /**
96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
97 *
98 * @adev: amdgpu_device pointer
99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
vega20_ih_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)104 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105 struct amdgpu_ih_ring *ih,
106 bool enable)
107 {
108 struct amdgpu_ih_regs *ih_regs;
109 uint32_t tmp;
110
111 ih_regs = &ih->ih_regs;
112
113 tmp = RREG32(ih_regs->ih_rb_cntl);
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117 /* enable_intr field is only valid in ring0 */
118 if (ih == &adev->irq.ih)
119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
120 if (amdgpu_sriov_vf(adev)) {
121 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
122 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
123 return -ETIMEDOUT;
124 }
125 } else {
126 WREG32(ih_regs->ih_rb_cntl, tmp);
127 }
128
129 if (enable) {
130 ih->enabled = true;
131 } else {
132 /* set rptr, wptr to 0 */
133 WREG32(ih_regs->ih_rb_rptr, 0);
134 WREG32(ih_regs->ih_rb_wptr, 0);
135 ih->enabled = false;
136 ih->rptr = 0;
137 }
138
139 return 0;
140 }
141
142 /**
143 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
144 *
145 * @adev: amdgpu_device pointer
146 * @enable: enable or disable interrupt ring buffers
147 *
148 * Toggle all the available interrupt ring buffers (VEGA20).
149 */
vega20_ih_toggle_interrupts(struct amdgpu_device * adev,bool enable)150 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
151 {
152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
153 int i;
154 int r;
155
156 for (i = 0; i < ARRAY_SIZE(ih); i++) {
157 if (ih[i]->ring_size) {
158 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
159 if (r)
160 return r;
161 }
162 }
163
164 return 0;
165 }
166
vega20_ih_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
168 {
169 int rb_bufsz = order_base_2(ih->ring_size / 4);
170
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
172 MC_SPACE, ih->use_bus_addr ? 1 : 4);
173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
174 WPTR_OVERFLOW_CLEAR, 1);
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
176 WPTR_OVERFLOW_ENABLE, 1);
177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
178 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
179 * value is written to memory
180 */
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
182 WPTR_WRITEBACK_ENABLE, 1);
183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
186
187 return ih_rb_cntl;
188 }
189
vega20_ih_doorbell_rptr(struct amdgpu_ih_ring * ih)190 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
191 {
192 u32 ih_doorbell_rtpr = 0;
193
194 if (ih->use_doorbell) {
195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
196 IH_DOORBELL_RPTR, OFFSET,
197 ih->doorbell_index);
198 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
199 IH_DOORBELL_RPTR,
200 ENABLE, 1);
201 } else {
202 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
203 IH_DOORBELL_RPTR,
204 ENABLE, 0);
205 }
206 return ih_doorbell_rtpr;
207 }
208
209 /**
210 * vega20_ih_enable_ring - enable an ih ring buffer
211 *
212 * @adev: amdgpu_device pointer
213 * @ih: amdgpu_ih_ring pointer
214 *
215 * Enable an ih ring buffer (VEGA20)
216 */
vega20_ih_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)217 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
218 struct amdgpu_ih_ring *ih)
219 {
220 struct amdgpu_ih_regs *ih_regs;
221 uint32_t tmp;
222
223 ih_regs = &ih->ih_regs;
224
225 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
226 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
227 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
228
229 tmp = RREG32(ih_regs->ih_rb_cntl);
230 tmp = vega20_ih_rb_cntl(ih, tmp);
231 if (ih == &adev->irq.ih)
232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
233 if (ih == &adev->irq.ih1)
234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
235 if (amdgpu_sriov_vf(adev)) {
236 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
237 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
238 return -ETIMEDOUT;
239 }
240 } else {
241 WREG32(ih_regs->ih_rb_cntl, tmp);
242 }
243
244 if (ih == &adev->irq.ih) {
245 /* set the ih ring 0 writeback address whether it's enabled or not */
246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
248 }
249
250 /* set rptr, wptr to 0 */
251 WREG32(ih_regs->ih_rb_wptr, 0);
252 WREG32(ih_regs->ih_rb_rptr, 0);
253
254 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
255
256 return 0;
257 }
258
vega20_setup_retry_doorbell(u32 doorbell_index)259 static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
260 {
261 u32 val = 0;
262
263 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
264 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
265
266 return val;
267 }
268
269 /**
270 * vega20_ih_irq_init - init and enable the interrupt ring
271 *
272 * @adev: amdgpu_device pointer
273 *
274 * Allocate a ring buffer for the interrupt controller,
275 * enable the RLC, disable interrupts, enable the IH
276 * ring buffer and enable it (VI).
277 * Called at device load and reume.
278 * Returns 0 for success, errors for failure.
279 */
vega20_ih_irq_init(struct amdgpu_device * adev)280 static int vega20_ih_irq_init(struct amdgpu_device *adev)
281 {
282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
283 u32 ih_chicken;
284 int ret;
285 int i;
286
287 /* disable irqs */
288 ret = vega20_ih_toggle_interrupts(adev, false);
289 if (ret)
290 return ret;
291
292 adev->nbio.funcs->ih_control(adev);
293
294 if (!amdgpu_sriov_vf(adev)) {
295 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) &&
296 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
297 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
298 if (adev->irq.ih.use_bus_addr) {
299 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
300 MC_SPACE_GPA_ENABLE, 1);
301 }
302 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
303 }
304
305 /* psp firmware won't program IH_CHICKEN for aldebaran
306 * driver needs to program it properly according to
307 * MC_SPACE type in IH_RB_CNTL */
308 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||
309 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) ||
310 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) {
311 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
312 if (adev->irq.ih.use_bus_addr) {
313 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
314 MC_SPACE_GPA_ENABLE, 1);
315 }
316 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
317 }
318 }
319
320 for (i = 0; i < ARRAY_SIZE(ih); i++) {
321 if (ih[i]->ring_size) {
322 ret = vega20_ih_enable_ring(adev, ih[i]);
323 if (ret)
324 return ret;
325 }
326 }
327
328 if (!amdgpu_sriov_vf(adev))
329 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
330 adev->irq.ih.doorbell_index);
331
332 pci_set_master(adev->pdev);
333
334 /* Allocate the doorbell for IH Retry CAM */
335 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
336 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
337 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
338
339 /* Enable IH Retry CAM */
340 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||
341 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) ||
342 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))
343 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
344 ENABLE, 1);
345 else
346 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
347
348 adev->irq.retry_cam_enabled = true;
349
350 /* enable interrupts */
351 ret = vega20_ih_toggle_interrupts(adev, true);
352 if (ret)
353 return ret;
354
355 if (adev->irq.ih_soft.ring_size)
356 adev->irq.ih_soft.enabled = true;
357
358 return 0;
359 }
360
361 /**
362 * vega20_ih_irq_disable - disable interrupts
363 *
364 * @adev: amdgpu_device pointer
365 *
366 * Disable interrupts on the hw (VEGA20).
367 */
vega20_ih_irq_disable(struct amdgpu_device * adev)368 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
369 {
370 vega20_ih_toggle_interrupts(adev, false);
371
372 /* Wait and acknowledge irq */
373 mdelay(1);
374 }
375
376 /**
377 * vega20_ih_get_wptr - get the IH ring buffer wptr
378 *
379 * @adev: amdgpu_device pointer
380 * @ih: amdgpu_ih_ring pointer
381 *
382 * Get the IH ring buffer wptr from either the register
383 * or the writeback memory buffer (VEGA20). Also check for
384 * ring buffer overflow and deal with it.
385 * Returns the value of the wptr.
386 */
vega20_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)387 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
388 struct amdgpu_ih_ring *ih)
389 {
390 u32 wptr, tmp;
391 struct amdgpu_ih_regs *ih_regs;
392
393 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
394 /* Only ring0 supports writeback. On other rings fall back
395 * to register-based code with overflow checking below.
396 * ih_soft ring doesn't have any backing hardware registers,
397 * update wptr and return.
398 */
399 wptr = le32_to_cpu(*ih->wptr_cpu);
400
401 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
402 goto out;
403 }
404
405 ih_regs = &ih->ih_regs;
406
407 /* Double check that the overflow wasn't already cleared. */
408 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
409 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
410 goto out;
411
412 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
413
414 /* When a ring buffer overflow happen start parsing interrupt
415 * from the last not overwritten vector (wptr + 32). Hopefully
416 * this should allow us to catchup.
417 */
418 tmp = (wptr + 32) & ih->ptr_mask;
419 dev_warn(adev->dev, "IH ring buffer overflow "
420 "(0x%08X, 0x%08X, 0x%08X)\n",
421 wptr, ih->rptr, tmp);
422 ih->rptr = tmp;
423
424 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
425 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
426 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
427
428 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
429 * can be detected.
430 */
431 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
432 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
433
434 out:
435 return (wptr & ih->ptr_mask);
436 }
437
438 /**
439 * vega20_ih_irq_rearm - rearm IRQ if lost
440 *
441 * @adev: amdgpu_device pointer
442 * @ih: amdgpu_ih_ring pointer
443 *
444 */
vega20_ih_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)445 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
446 struct amdgpu_ih_ring *ih)
447 {
448 uint32_t v = 0;
449 uint32_t i = 0;
450 struct amdgpu_ih_regs *ih_regs;
451
452 ih_regs = &ih->ih_regs;
453
454 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
455 for (i = 0; i < MAX_REARM_RETRY; i++) {
456 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
457 if ((v < ih->ring_size) && (v != ih->rptr))
458 WDOORBELL32(ih->doorbell_index, ih->rptr);
459 else
460 break;
461 }
462 }
463
464 /**
465 * vega20_ih_set_rptr - set the IH ring buffer rptr
466 *
467 * @adev: amdgpu_device pointer
468 * @ih: amdgpu_ih_ring pointer
469 *
470 * Set the IH ring buffer rptr.
471 */
vega20_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)472 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
473 struct amdgpu_ih_ring *ih)
474 {
475 struct amdgpu_ih_regs *ih_regs;
476
477 if (ih == &adev->irq.ih_soft)
478 return;
479
480 if (ih->use_doorbell) {
481 /* XXX check if swapping is necessary on BE */
482 *ih->rptr_cpu = ih->rptr;
483 WDOORBELL32(ih->doorbell_index, ih->rptr);
484
485 if (amdgpu_sriov_vf(adev))
486 vega20_ih_irq_rearm(adev, ih);
487 } else {
488 ih_regs = &ih->ih_regs;
489 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
490 }
491 }
492
493 /**
494 * vega20_ih_self_irq - dispatch work for ring 1 and 2
495 *
496 * @adev: amdgpu_device pointer
497 * @source: irq source
498 * @entry: IV with WPTR update
499 *
500 * Update the WPTR from the IV and schedule work to handle the entries.
501 */
vega20_ih_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)502 static int vega20_ih_self_irq(struct amdgpu_device *adev,
503 struct amdgpu_irq_src *source,
504 struct amdgpu_iv_entry *entry)
505 {
506 switch (entry->ring_id) {
507 case 1:
508 schedule_work(&adev->irq.ih1_work);
509 break;
510 case 2:
511 schedule_work(&adev->irq.ih2_work);
512 break;
513 default:
514 break;
515 }
516 return 0;
517 }
518
519 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
520 .process = vega20_ih_self_irq,
521 };
522
vega20_ih_set_self_irq_funcs(struct amdgpu_device * adev)523 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
524 {
525 adev->irq.self_irq.num_types = 0;
526 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
527 }
528
vega20_ih_early_init(void * handle)529 static int vega20_ih_early_init(void *handle)
530 {
531 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
532
533 vega20_ih_set_interrupt_funcs(adev);
534 vega20_ih_set_self_irq_funcs(adev);
535 return 0;
536 }
537
vega20_ih_sw_init(void * handle)538 static int vega20_ih_sw_init(void *handle)
539 {
540 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
541 bool use_bus_addr = true;
542 int r;
543
544 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
545 &adev->irq.self_irq);
546 if (r)
547 return r;
548
549 if ((adev->flags & AMD_IS_APU) &&
550 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)))
551 use_bus_addr = false;
552
553 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
554 if (r)
555 return r;
556
557 adev->irq.ih.use_doorbell = true;
558 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
559
560 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
561 if (r)
562 return r;
563
564 adev->irq.ih1.use_doorbell = true;
565 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
566
567 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) &&
568 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) {
569 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
570 if (r)
571 return r;
572
573 adev->irq.ih2.use_doorbell = true;
574 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
575 }
576
577 /* initialize ih control registers offset */
578 vega20_ih_init_register_offset(adev);
579
580 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
581 if (r)
582 return r;
583
584 r = amdgpu_irq_init(adev);
585
586 return r;
587 }
588
vega20_ih_sw_fini(void * handle)589 static int vega20_ih_sw_fini(void *handle)
590 {
591 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
592
593 amdgpu_irq_fini_sw(adev);
594
595 return 0;
596 }
597
vega20_ih_hw_init(void * handle)598 static int vega20_ih_hw_init(void *handle)
599 {
600 int r;
601 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
602
603 r = vega20_ih_irq_init(adev);
604 if (r)
605 return r;
606
607 return 0;
608 }
609
vega20_ih_hw_fini(void * handle)610 static int vega20_ih_hw_fini(void *handle)
611 {
612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613
614 vega20_ih_irq_disable(adev);
615
616 return 0;
617 }
618
vega20_ih_suspend(void * handle)619 static int vega20_ih_suspend(void *handle)
620 {
621 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
622
623 return vega20_ih_hw_fini(adev);
624 }
625
vega20_ih_resume(void * handle)626 static int vega20_ih_resume(void *handle)
627 {
628 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
629
630 return vega20_ih_hw_init(adev);
631 }
632
vega20_ih_is_idle(void * handle)633 static bool vega20_ih_is_idle(void *handle)
634 {
635 /* todo */
636 return true;
637 }
638
vega20_ih_wait_for_idle(void * handle)639 static int vega20_ih_wait_for_idle(void *handle)
640 {
641 /* todo */
642 return -ETIMEDOUT;
643 }
644
vega20_ih_soft_reset(void * handle)645 static int vega20_ih_soft_reset(void *handle)
646 {
647 /* todo */
648
649 return 0;
650 }
651
vega20_ih_update_clockgating_state(struct amdgpu_device * adev,bool enable)652 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
653 bool enable)
654 {
655 uint32_t data, def, field_val;
656
657 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
658 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
659 field_val = enable ? 0 : 1;
660 data = REG_SET_FIELD(data, IH_CLK_CTRL,
661 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
662 data = REG_SET_FIELD(data, IH_CLK_CTRL,
663 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
664 data = REG_SET_FIELD(data, IH_CLK_CTRL,
665 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
666 data = REG_SET_FIELD(data, IH_CLK_CTRL,
667 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
668 data = REG_SET_FIELD(data, IH_CLK_CTRL,
669 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
670 data = REG_SET_FIELD(data, IH_CLK_CTRL,
671 DYN_CLK_SOFT_OVERRIDE, field_val);
672 data = REG_SET_FIELD(data, IH_CLK_CTRL,
673 REG_CLK_SOFT_OVERRIDE, field_val);
674 if (def != data)
675 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
676 }
677 }
678
vega20_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)679 static int vega20_ih_set_clockgating_state(void *handle,
680 enum amd_clockgating_state state)
681 {
682 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
683
684 vega20_ih_update_clockgating_state(adev,
685 state == AMD_CG_STATE_GATE);
686 return 0;
687
688 }
689
vega20_ih_set_powergating_state(void * handle,enum amd_powergating_state state)690 static int vega20_ih_set_powergating_state(void *handle,
691 enum amd_powergating_state state)
692 {
693 return 0;
694 }
695
696 const struct amd_ip_funcs vega20_ih_ip_funcs = {
697 .name = "vega20_ih",
698 .early_init = vega20_ih_early_init,
699 .late_init = NULL,
700 .sw_init = vega20_ih_sw_init,
701 .sw_fini = vega20_ih_sw_fini,
702 .hw_init = vega20_ih_hw_init,
703 .hw_fini = vega20_ih_hw_fini,
704 .suspend = vega20_ih_suspend,
705 .resume = vega20_ih_resume,
706 .is_idle = vega20_ih_is_idle,
707 .wait_for_idle = vega20_ih_wait_for_idle,
708 .soft_reset = vega20_ih_soft_reset,
709 .set_clockgating_state = vega20_ih_set_clockgating_state,
710 .set_powergating_state = vega20_ih_set_powergating_state,
711 };
712
713 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
714 .get_wptr = vega20_ih_get_wptr,
715 .decode_iv = amdgpu_ih_decode_iv_helper,
716 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
717 .set_rptr = vega20_ih_set_rptr
718 };
719
vega20_ih_set_interrupt_funcs(struct amdgpu_device * adev)720 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
721 {
722 adev->irq.ih_funcs = &vega20_ih_funcs;
723 }
724
725 const struct amdgpu_ip_block_version vega20_ih_ip_block = {
726 .type = AMD_IP_BLOCK_TYPE_IH,
727 .major = 4,
728 .minor = 2,
729 .rev = 0,
730 .funcs = &vega20_ih_ip_funcs,
731 };
732